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tests/acpi: allow changes for microvm/APIC.pcie
[qemu/ar7.git] / hw / arm / aspeed.c
blobbdb981d2f87855e9db727bcc35a9db4167291b9b
1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "cpu.h"
15 #include "exec/address-spaces.h"
16 #include "hw/arm/boot.h"
17 #include "hw/arm/aspeed.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/boards.h"
20 #include "hw/i2c/smbus_eeprom.h"
21 #include "hw/misc/pca9552.h"
22 #include "hw/misc/tmp105.h"
23 #include "hw/qdev-properties.h"
24 #include "qemu/log.h"
25 #include "sysemu/block-backend.h"
26 #include "sysemu/sysemu.h"
27 #include "hw/loader.h"
28 #include "qemu/error-report.h"
29 #include "qemu/units.h"
30
31 static struct arm_boot_info aspeed_board_binfo = {
32 .board_id = -1, /* device-tree-only board */
33 };
34
35 struct AspeedMachineState {
36 /* Private */
37 MachineState parent_obj;
38 /* Public */
39
40 AspeedSoCState soc;
41 MemoryRegion ram_container;
42 MemoryRegion max_ram;
43 bool mmio_exec;
44 char *fmc_model;
45 char *spi_model;
46 };
47
48 /* Palmetto hardware value: 0x120CE416 */
49 #define PALMETTO_BMC_HW_STRAP1 ( \
50 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
51 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
52 SCU_AST2400_HW_STRAP_ACPI_DIS | \
53 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
54 SCU_HW_STRAP_VGA_CLASS_CODE | \
55 SCU_HW_STRAP_LPC_RESET_PIN | \
56 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
57 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
58 SCU_HW_STRAP_SPI_WIDTH | \
59 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
60 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
61
62 /* TODO: Find the actual hardware value */
63 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
64 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
65 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
66 SCU_AST2400_HW_STRAP_ACPI_DIS | \
67 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
68 SCU_HW_STRAP_VGA_CLASS_CODE | \
69 SCU_HW_STRAP_LPC_RESET_PIN | \
70 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
71 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
72 SCU_HW_STRAP_SPI_WIDTH | \
73 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
74 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
75
76 /* AST2500 evb hardware value: 0xF100C2E6 */
77 #define AST2500_EVB_HW_STRAP1 (( \
78 AST2500_HW_STRAP1_DEFAULTS | \
79 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
80 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
81 SCU_AST2500_HW_STRAP_UART_DEBUG | \
82 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
83 SCU_HW_STRAP_MAC1_RGMII | \
84 SCU_HW_STRAP_MAC0_RGMII) & \
85 ~SCU_HW_STRAP_2ND_BOOT_WDT)
86
87 /* Romulus hardware value: 0xF10AD206 */
88 #define ROMULUS_BMC_HW_STRAP1 ( \
89 AST2500_HW_STRAP1_DEFAULTS | \
90 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
91 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
92 SCU_AST2500_HW_STRAP_UART_DEBUG | \
93 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
94 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
95 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
96
97 /* Sonorapass hardware value: 0xF100D216 */
98 #define SONORAPASS_BMC_HW_STRAP1 ( \
99 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
100 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
101 SCU_AST2500_HW_STRAP_UART_DEBUG | \
102 SCU_AST2500_HW_STRAP_RESERVED28 | \
103 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
104 SCU_HW_STRAP_VGA_CLASS_CODE | \
105 SCU_HW_STRAP_LPC_RESET_PIN | \
106 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
107 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
108 SCU_HW_STRAP_VGA_BIOS_ROM | \
109 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
110 SCU_AST2500_HW_STRAP_RESERVED1)
111
112 /* Swift hardware value: 0xF11AD206 */
113 #define SWIFT_BMC_HW_STRAP1 ( \
114 AST2500_HW_STRAP1_DEFAULTS | \
115 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
116 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
117 SCU_AST2500_HW_STRAP_UART_DEBUG | \
118 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
119 SCU_H_PLL_BYPASS_EN | \
120 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
121 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
122
123 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
124 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
125
126 /* AST2600 evb hardware value */
127 #define AST2600_EVB_HW_STRAP1 0x000000C0
128 #define AST2600_EVB_HW_STRAP2 0x00000003
129
130 /* Tacoma hardware value */
131 #define TACOMA_BMC_HW_STRAP1 0x00000000
132 #define TACOMA_BMC_HW_STRAP2 0x00000040
133
134 /*
135 * The max ram region is for firmwares that scan the address space
136 * with load/store to guess how much RAM the SoC has.
137 */
138 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
139 {
140 return 0;
141 }
142
143 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
144 unsigned size)
145 {
146 /* Discard writes */
147 }
148
149 static const MemoryRegionOps max_ram_ops = {
150 .read = max_ram_read,
151 .write = max_ram_write,
152 .endianness = DEVICE_NATIVE_ENDIAN,
153 };
154
155 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
156 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
157 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
158 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
159 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
160 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
161 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
162
163 static void aspeed_write_smpboot(ARMCPU *cpu,
164 const struct arm_boot_info *info)
165 {
166 static const uint32_t poll_mailbox_ready[] = {
167 /*
168 * r2 = per-cpu go sign value
169 * r1 = AST_SMP_MBOX_FIELD_ENTRY
170 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
171 */
172 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
173 0xe21000ff, /* ands r0, r0, #255 */
174 0xe59f201c, /* ldr r2, [pc, #28] */
175 0xe1822000, /* orr r2, r2, r0 */
176
177 0xe59f1018, /* ldr r1, [pc, #24] */
178 0xe59f0018, /* ldr r0, [pc, #24] */
179
180 0xe320f002, /* wfe */
181 0xe5904000, /* ldr r4, [r0] */
182 0xe1520004, /* cmp r2, r4 */
183 0x1afffffb, /* bne <wfe> */
184 0xe591f000, /* ldr pc, [r1] */
185 AST_SMP_MBOX_GOSIGN,
186 AST_SMP_MBOX_FIELD_ENTRY,
187 AST_SMP_MBOX_FIELD_GOSIGN,
188 };
189
190 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
191 sizeof(poll_mailbox_ready),
192 info->smp_loader_start);
193 }
194
195 static void aspeed_reset_secondary(ARMCPU *cpu,
196 const struct arm_boot_info *info)
197 {
198 AddressSpace *as = arm_boot_address_space(cpu, info);
199 CPUState *cs = CPU(cpu);
200
201 /* info->smp_bootreg_addr */
202 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
203 MEMTXATTRS_UNSPECIFIED, NULL);
204 cpu_set_pc(cs, info->smp_loader_start);
205 }
206
207 #define FIRMWARE_ADDR 0x0
208
209 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
210 Error **errp)
211 {
212 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
213 uint8_t *storage;
214 int64_t size;
215
216 /* The block backend size should have already been 'validated' by
217 * the creation of the m25p80 object.
218 */
219 size = blk_getlength(blk);
220 if (size <= 0) {
221 error_setg(errp, "failed to get flash size");
222 return;
223 }
224
225 if (rom_size > size) {
226 rom_size = size;
227 }
228
229 storage = g_new0(uint8_t, rom_size);
230 if (blk_pread(blk, 0, storage, rom_size) < 0) {
231 error_setg(errp, "failed to read the initial flash content");
232 return;
233 }
234
235 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
236 g_free(storage);
237 }
238
239 static void aspeed_board_init_flashes(AspeedSMCState *s,
240 const char *flashtype)
241 {
242 int i ;
243
244 for (i = 0; i < s->num_cs; ++i) {
245 AspeedSMCFlash *fl = &s->flashes[i];
246 DriveInfo *dinfo = drive_get_next(IF_MTD);
247 qemu_irq cs_line;
248
249 fl->flash = qdev_new(flashtype);
250 if (dinfo) {
251 qdev_prop_set_drive(fl->flash, "drive",
252 blk_by_legacy_dinfo(dinfo));
253 }
254 qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal);
255
256 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
257 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
258 }
259 }
260
261 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
262 {
263 DeviceState *card;
264
265 if (!dinfo) {
266 return;
267 }
268 card = qdev_new(TYPE_SD_CARD);
269 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
270 &error_fatal);
271 qdev_realize_and_unref(card,
272 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
273 &error_fatal);
274 }
275
276 static void aspeed_machine_init(MachineState *machine)
277 {
278 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
279 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
280 AspeedSoCClass *sc;
281 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
282 ram_addr_t max_ram_size;
283 int i;
284 NICInfo *nd = &nd_table[0];
285
286 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
287 4 * GiB);
288 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
289
290 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
291
292 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
293
294 /*
295 * This will error out if isize is not supported by memory controller.
296 */
297 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", ram_size,
298 &error_fatal);
299
300 for (i = 0; i < sc->macs_num; i++) {
301 if ((amc->macs_mask & (1 << i)) && nd->used) {
302 qemu_check_nic_model(nd, TYPE_FTGMAC100);
303 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
304 nd++;
305 }
306 }
307
308 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
309 &error_abort);
310 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
311 &error_abort);
312 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs,
313 &error_abort);
314 object_property_set_link(OBJECT(&bmc->soc), "dram",
315 OBJECT(&bmc->ram_container), &error_abort);
316 if (machine->kernel_filename) {
317 /*
318 * When booting with a -kernel command line there is no u-boot
319 * that runs to unlock the SCU. In this case set the default to
320 * be unlocked as the kernel expects
321 */
322 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
323 ASPEED_SCU_PROT_KEY, &error_abort);
324 }
325 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
326
327 memory_region_add_subregion(get_system_memory(),
328 sc->memmap[ASPEED_DEV_SDRAM],
329 &bmc->ram_container);
330
331 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
332 &error_abort);
333 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
334 "max_ram", max_ram_size - ram_size);
335 memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram);
336
337 aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ?
338 bmc->fmc_model : amc->fmc_model);
339 aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ?
340 bmc->spi_model : amc->spi_model);
341
342 /* Install first FMC flash content as a boot rom. */
343 if (drive0) {
344 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
345 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
346
347 /*
348 * create a ROM region using the default mapping window size of
349 * the flash module. The window size is 64MB for the AST2400
350 * SoC and 128MB for the AST2500 SoC, which is twice as big as
351 * needed by the flash modules of the Aspeed machines.
352 */
353 if (ASPEED_MACHINE(machine)->mmio_exec) {
354 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
355 &fl->mmio, 0, fl->size);
356 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
357 boot_rom);
358 } else {
359 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
360 fl->size, &error_abort);
361 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
362 boot_rom);
363 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
364 }
365 }
366
367 if (machine->kernel_filename && sc->num_cpus > 1) {
368 /* With no u-boot we must set up a boot stub for the secondary CPU */
369 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
370 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
371 0x80, &error_abort);
372 memory_region_add_subregion(get_system_memory(),
373 AST_SMP_MAILBOX_BASE, smpboot);
374
375 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
376 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
377 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
378 }
379
380 aspeed_board_binfo.ram_size = ram_size;
381 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
382 aspeed_board_binfo.nb_cpus = sc->num_cpus;
383
384 if (amc->i2c_init) {
385 amc->i2c_init(bmc);
386 }
387
388 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
389 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD));
390 }
391
392 if (bmc->soc.emmc.num_slots) {
393 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD));
394 }
395
396 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
397 }
398
399 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
400 {
401 AspeedSoCState *soc = &bmc->soc;
402 DeviceState *dev;
403 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
404
405 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
406 * enough to provide basic RTC features. Alarms will be missing */
407 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
408
409 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
410 eeprom_buf);
411
412 /* add a TMP423 temperature sensor */
413 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
414 "tmp423", 0x4c));
415 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
416 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
417 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
418 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
419 }
420
421 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
422 {
423 AspeedSoCState *soc = &bmc->soc;
424 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
425
426 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
427 eeprom_buf);
428
429 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
430 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
431 TYPE_TMP105, 0x4d);
432
433 /* The AST2500 EVB does not have an RTC. Let's pretend that one is
434 * plugged on the I2C bus header */
435 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
436 }
437
438 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
439 {
440 /* Start with some devices on our I2C busses */
441 ast2500_evb_i2c_init(bmc);
442 }
443
444 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
445 {
446 AspeedSoCState *soc = &bmc->soc;
447
448 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
449 * good enough */
450 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
451 }
452
453 static void swift_bmc_i2c_init(AspeedMachineState *bmc)
454 {
455 AspeedSoCState *soc = &bmc->soc;
456
457 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60);
458
459 /* The swift board expects a TMP275 but a TMP105 is compatible */
460 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48);
461 /* The swift board expects a pca9551 but a pca9552 is compatible */
462 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
463
464 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
465 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32);
466 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
467
468 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
469 /* The swift board expects a pca9539 but a pca9552 is compatible */
470 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74);
471
472 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
473 /* The swift board expects a pca9539 but a pca9552 is compatible */
474 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552",
475 0x74);
476
477 /* The swift board expects a TMP275 but a TMP105 is compatible */
478 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48);
479 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a);
480 }
481
482 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
483 {
484 AspeedSoCState *soc = &bmc->soc;
485
486 /* bus 2 : */
487 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
488 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
489 /* bus 2 : pca9546 @ 0x73 */
490
491 /* bus 3 : pca9548 @ 0x70 */
492
493 /* bus 4 : */
494 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
495 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
496 eeprom4_54);
497 /* PCA9539 @ 0x76, but PCA9552 is compatible */
498 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76);
499 /* PCA9539 @ 0x77, but PCA9552 is compatible */
500 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77);
501
502 /* bus 6 : */
503 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
504 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
505 /* bus 6 : pca9546 @ 0x73 */
506
507 /* bus 8 : */
508 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
509 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
510 eeprom8_56);
511 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
512 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
513 /* bus 8 : adc128d818 @ 0x1d */
514 /* bus 8 : adc128d818 @ 0x1f */
515
516 /*
517 * bus 13 : pca9548 @ 0x71
518 * - channel 3:
519 * - tmm421 @ 0x4c
520 * - tmp421 @ 0x4e
521 * - tmp421 @ 0x4f
522 */
523
524 }
525
526 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
527 {
528 AspeedSoCState *soc = &bmc->soc;
529 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
530 DeviceState *dev;
531
532 /* Bus 3: TODO bmp280@77 */
533 /* Bus 3: TODO max31785@52 */
534 /* Bus 3: TODO dps310@76 */
535 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
536 qdev_prop_set_string(dev, "description", "pca1");
537 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
538 aspeed_i2c_get_bus(&soc->i2c, 3),
539 &error_fatal);
540
541 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
542 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
543
544 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
545 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
546 0x4a);
547
548 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
549 * good enough */
550 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
551
552 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
553 eeprom_buf);
554 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
555 qdev_prop_set_string(dev, "description", "pca0");
556 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
557 aspeed_i2c_get_bus(&soc->i2c, 11),
558 &error_fatal);
559 /* Bus 11: TODO ucd90160@64 */
560 }
561
562 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
563 {
564 return ASPEED_MACHINE(obj)->mmio_exec;
565 }
566
567 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
568 {
569 ASPEED_MACHINE(obj)->mmio_exec = value;
570 }
571
572 static void aspeed_machine_instance_init(Object *obj)
573 {
574 ASPEED_MACHINE(obj)->mmio_exec = false;
575 }
576
577 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
578 {
579 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
580 return g_strdup(bmc->fmc_model);
581 }
582
583 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
584 {
585 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
586
587 g_free(bmc->fmc_model);
588 bmc->fmc_model = g_strdup(value);
589 }
590
591 static char *aspeed_get_spi_model(Object *obj, Error **errp)
592 {
593 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
594 return g_strdup(bmc->spi_model);
595 }
596
597 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
598 {
599 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
600
601 g_free(bmc->spi_model);
602 bmc->spi_model = g_strdup(value);
603 }
604
605 static void aspeed_machine_class_props_init(ObjectClass *oc)
606 {
607 object_class_property_add_bool(oc, "execute-in-place",
608 aspeed_get_mmio_exec,
609 aspeed_set_mmio_exec);
610 object_class_property_set_description(oc, "execute-in-place",
611 "boot directly from CE0 flash device");
612
613 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
614 aspeed_set_fmc_model);
615 object_class_property_set_description(oc, "fmc-model",
616 "Change the FMC Flash model");
617 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
618 aspeed_set_spi_model);
619 object_class_property_set_description(oc, "spi-model",
620 "Change the SPI Flash model");
621 }
622
623 static int aspeed_soc_num_cpus(const char *soc_name)
624 {
625 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
626 return sc->num_cpus;
627 }
628
629 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
630 {
631 MachineClass *mc = MACHINE_CLASS(oc);
632 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
633
634 mc->init = aspeed_machine_init;
635 mc->no_floppy = 1;
636 mc->no_cdrom = 1;
637 mc->no_parallel = 1;
638 mc->default_ram_id = "ram";
639 amc->macs_mask = ASPEED_MAC0_ON;
640
641 aspeed_machine_class_props_init(oc);
642 }
643
644 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
645 {
646 MachineClass *mc = MACHINE_CLASS(oc);
647 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
648
649 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
650 amc->soc_name = "ast2400-a1";
651 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
652 amc->fmc_model = "n25q256a";
653 amc->spi_model = "mx25l25635e";
654 amc->num_cs = 1;
655 amc->i2c_init = palmetto_bmc_i2c_init;
656 mc->default_ram_size = 256 * MiB;
657 mc->default_cpus = mc->min_cpus = mc->max_cpus =
658 aspeed_soc_num_cpus(amc->soc_name);
659 };
660
661 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
662 void *data)
663 {
664 MachineClass *mc = MACHINE_CLASS(oc);
665 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
666
667 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
668 amc->soc_name = "ast2400-a1";
669 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
670 amc->fmc_model = "mx25l25635e";
671 amc->spi_model = "mx25l25635e";
672 amc->num_cs = 1;
673 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
674 amc->i2c_init = palmetto_bmc_i2c_init;
675 mc->default_ram_size = 256 * MiB;
676 }
677
678 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
679 {
680 MachineClass *mc = MACHINE_CLASS(oc);
681 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
682
683 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
684 amc->soc_name = "ast2500-a1";
685 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
686 amc->fmc_model = "w25q256";
687 amc->spi_model = "mx25l25635e";
688 amc->num_cs = 1;
689 amc->i2c_init = ast2500_evb_i2c_init;
690 mc->default_ram_size = 512 * MiB;
691 mc->default_cpus = mc->min_cpus = mc->max_cpus =
692 aspeed_soc_num_cpus(amc->soc_name);
693 };
694
695 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
696 {
697 MachineClass *mc = MACHINE_CLASS(oc);
698 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
699
700 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
701 amc->soc_name = "ast2500-a1";
702 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
703 amc->fmc_model = "n25q256a";
704 amc->spi_model = "mx66l1g45g";
705 amc->num_cs = 2;
706 amc->i2c_init = romulus_bmc_i2c_init;
707 mc->default_ram_size = 512 * MiB;
708 mc->default_cpus = mc->min_cpus = mc->max_cpus =
709 aspeed_soc_num_cpus(amc->soc_name);
710 };
711
712 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
713 {
714 MachineClass *mc = MACHINE_CLASS(oc);
715 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
716
717 mc->desc = "OCP SonoraPass BMC (ARM1176)";
718 amc->soc_name = "ast2500-a1";
719 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
720 amc->fmc_model = "mx66l1g45g";
721 amc->spi_model = "mx66l1g45g";
722 amc->num_cs = 2;
723 amc->i2c_init = sonorapass_bmc_i2c_init;
724 mc->default_ram_size = 512 * MiB;
725 mc->default_cpus = mc->min_cpus = mc->max_cpus =
726 aspeed_soc_num_cpus(amc->soc_name);
727 };
728
729 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
730 {
731 MachineClass *mc = MACHINE_CLASS(oc);
732 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
733
734 mc->desc = "OpenPOWER Swift BMC (ARM1176)";
735 amc->soc_name = "ast2500-a1";
736 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1;
737 amc->fmc_model = "mx66l1g45g";
738 amc->spi_model = "mx66l1g45g";
739 amc->num_cs = 2;
740 amc->i2c_init = swift_bmc_i2c_init;
741 mc->default_ram_size = 512 * MiB;
742 mc->default_cpus = mc->min_cpus = mc->max_cpus =
743 aspeed_soc_num_cpus(amc->soc_name);
744 };
745
746 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
747 {
748 MachineClass *mc = MACHINE_CLASS(oc);
749 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
750
751 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
752 amc->soc_name = "ast2500-a1";
753 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
754 amc->fmc_model = "mx25l25635e";
755 amc->spi_model = "mx66l1g45g";
756 amc->num_cs = 2;
757 amc->i2c_init = witherspoon_bmc_i2c_init;
758 mc->default_ram_size = 512 * MiB;
759 mc->default_cpus = mc->min_cpus = mc->max_cpus =
760 aspeed_soc_num_cpus(amc->soc_name);
761 };
762
763 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
764 {
765 MachineClass *mc = MACHINE_CLASS(oc);
766 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
767
768 mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
769 amc->soc_name = "ast2600-a1";
770 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
771 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
772 amc->fmc_model = "w25q512jv";
773 amc->spi_model = "mx66u51235f";
774 amc->num_cs = 1;
775 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON;
776 amc->i2c_init = ast2600_evb_i2c_init;
777 mc->default_ram_size = 1 * GiB;
778 mc->default_cpus = mc->min_cpus = mc->max_cpus =
779 aspeed_soc_num_cpus(amc->soc_name);
780 };
781
782 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
783 {
784 MachineClass *mc = MACHINE_CLASS(oc);
785 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
786
787 mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)";
788 amc->soc_name = "ast2600-a1";
789 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
790 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
791 amc->fmc_model = "mx66l1g45g";
792 amc->spi_model = "mx66l1g45g";
793 amc->num_cs = 2;
794 amc->macs_mask = ASPEED_MAC2_ON;
795 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
796 mc->default_ram_size = 1 * GiB;
797 mc->default_cpus = mc->min_cpus = mc->max_cpus =
798 aspeed_soc_num_cpus(amc->soc_name);
799 };
800
801 static const TypeInfo aspeed_machine_types[] = {
802 {
803 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
804 .parent = TYPE_ASPEED_MACHINE,
805 .class_init = aspeed_machine_palmetto_class_init,
806 }, {
807 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
808 .parent = TYPE_ASPEED_MACHINE,
809 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
810 }, {
811 .name = MACHINE_TYPE_NAME("ast2500-evb"),
812 .parent = TYPE_ASPEED_MACHINE,
813 .class_init = aspeed_machine_ast2500_evb_class_init,
814 }, {
815 .name = MACHINE_TYPE_NAME("romulus-bmc"),
816 .parent = TYPE_ASPEED_MACHINE,
817 .class_init = aspeed_machine_romulus_class_init,
818 }, {
819 .name = MACHINE_TYPE_NAME("swift-bmc"),
820 .parent = TYPE_ASPEED_MACHINE,
821 .class_init = aspeed_machine_swift_class_init,
822 }, {
823 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
824 .parent = TYPE_ASPEED_MACHINE,
825 .class_init = aspeed_machine_sonorapass_class_init,
826 }, {
827 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
828 .parent = TYPE_ASPEED_MACHINE,
829 .class_init = aspeed_machine_witherspoon_class_init,
830 }, {
831 .name = MACHINE_TYPE_NAME("ast2600-evb"),
832 .parent = TYPE_ASPEED_MACHINE,
833 .class_init = aspeed_machine_ast2600_evb_class_init,
834 }, {
835 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
836 .parent = TYPE_ASPEED_MACHINE,
837 .class_init = aspeed_machine_tacoma_class_init,
838 }, {
839 .name = TYPE_ASPEED_MACHINE,
840 .parent = TYPE_MACHINE,
841 .instance_size = sizeof(AspeedMachineState),
842 .instance_init = aspeed_machine_instance_init,
843 .class_size = sizeof(AspeedMachineClass),
844 .class_init = aspeed_machine_class_init,
845 .abstract = true,
846 }
847 };
848
849 DEFINE_TYPES(aspeed_machine_types)
AR7 emulation for QEMU