2 * QEMU GT64120 PCI host
4 * Copyright (c) 2006,2007 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "qemu/units.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/registerfields.h"
31 #include "hw/pci/pci_device.h"
32 #include "hw/pci/pci_host.h"
33 #include "hw/misc/empty_slot.h"
34 #include "migration/vmstate.h"
35 #include "hw/intc/i8259.h"
38 #include "qom/object.h"
40 #define GT_REGS (0x1000 >> 2)
42 /* CPU Configuration */
43 #define GT_CPU (0x000 >> 2)
44 #define GT_MULTI (0x120 >> 2)
47 FIELD(GT_CPU
, Endianness
, 12, 1)
49 /* CPU Address Decode */
50 #define GT_SCS10LD (0x008 >> 2)
51 #define GT_SCS10HD (0x010 >> 2)
52 #define GT_SCS32LD (0x018 >> 2)
53 #define GT_SCS32HD (0x020 >> 2)
54 #define GT_CS20LD (0x028 >> 2)
55 #define GT_CS20HD (0x030 >> 2)
56 #define GT_CS3BOOTLD (0x038 >> 2)
57 #define GT_CS3BOOTHD (0x040 >> 2)
58 #define GT_PCI0IOLD (0x048 >> 2)
59 #define GT_PCI0IOHD (0x050 >> 2)
60 #define GT_PCI0M0LD (0x058 >> 2)
61 #define GT_PCI0M0HD (0x060 >> 2)
62 #define GT_PCI0M1LD (0x080 >> 2)
63 #define GT_PCI0M1HD (0x088 >> 2)
64 #define GT_PCI1IOLD (0x090 >> 2)
65 #define GT_PCI1IOHD (0x098 >> 2)
66 #define GT_PCI1M0LD (0x0a0 >> 2)
67 #define GT_PCI1M0HD (0x0a8 >> 2)
68 #define GT_PCI1M1LD (0x0b0 >> 2)
69 #define GT_PCI1M1HD (0x0b8 >> 2)
70 #define GT_ISD (0x068 >> 2)
72 #define GT_SCS10AR (0x0d0 >> 2)
73 #define GT_SCS32AR (0x0d8 >> 2)
74 #define GT_CS20R (0x0e0 >> 2)
75 #define GT_CS3BOOTR (0x0e8 >> 2)
77 #define GT_PCI0IOREMAP (0x0f0 >> 2)
78 #define GT_PCI0M0REMAP (0x0f8 >> 2)
79 #define GT_PCI0M1REMAP (0x100 >> 2)
80 #define GT_PCI1IOREMAP (0x108 >> 2)
81 #define GT_PCI1M0REMAP (0x110 >> 2)
82 #define GT_PCI1M1REMAP (0x118 >> 2)
84 /* CPU Error Report */
85 #define GT_CPUERR_ADDRLO (0x070 >> 2)
86 #define GT_CPUERR_ADDRHI (0x078 >> 2)
87 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
88 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
89 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
91 /* CPU Sync Barrier */
92 #define GT_PCI0SYNC (0x0c0 >> 2)
93 #define GT_PCI1SYNC (0x0c8 >> 2)
95 /* SDRAM and Device Address Decode */
96 #define GT_SCS0LD (0x400 >> 2)
97 #define GT_SCS0HD (0x404 >> 2)
98 #define GT_SCS1LD (0x408 >> 2)
99 #define GT_SCS1HD (0x40c >> 2)
100 #define GT_SCS2LD (0x410 >> 2)
101 #define GT_SCS2HD (0x414 >> 2)
102 #define GT_SCS3LD (0x418 >> 2)
103 #define GT_SCS3HD (0x41c >> 2)
104 #define GT_CS0LD (0x420 >> 2)
105 #define GT_CS0HD (0x424 >> 2)
106 #define GT_CS1LD (0x428 >> 2)
107 #define GT_CS1HD (0x42c >> 2)
108 #define GT_CS2LD (0x430 >> 2)
109 #define GT_CS2HD (0x434 >> 2)
110 #define GT_CS3LD (0x438 >> 2)
111 #define GT_CS3HD (0x43c >> 2)
112 #define GT_BOOTLD (0x440 >> 2)
113 #define GT_BOOTHD (0x444 >> 2)
114 #define GT_ADERR (0x470 >> 2)
116 /* SDRAM Configuration */
117 #define GT_SDRAM_CFG (0x448 >> 2)
118 #define GT_SDRAM_OPMODE (0x474 >> 2)
119 #define GT_SDRAM_BM (0x478 >> 2)
120 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
122 /* SDRAM Parameters */
123 #define GT_SDRAM_B0 (0x44c >> 2)
124 #define GT_SDRAM_B1 (0x450 >> 2)
125 #define GT_SDRAM_B2 (0x454 >> 2)
126 #define GT_SDRAM_B3 (0x458 >> 2)
128 /* Device Parameters */
129 #define GT_DEV_B0 (0x45c >> 2)
130 #define GT_DEV_B1 (0x460 >> 2)
131 #define GT_DEV_B2 (0x464 >> 2)
132 #define GT_DEV_B3 (0x468 >> 2)
133 #define GT_DEV_BOOT (0x46c >> 2)
136 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
137 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
138 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
139 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
140 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
143 #define GT_DMA0_CNT (0x800 >> 2)
144 #define GT_DMA1_CNT (0x804 >> 2)
145 #define GT_DMA2_CNT (0x808 >> 2)
146 #define GT_DMA3_CNT (0x80c >> 2)
147 #define GT_DMA0_SA (0x810 >> 2)
148 #define GT_DMA1_SA (0x814 >> 2)
149 #define GT_DMA2_SA (0x818 >> 2)
150 #define GT_DMA3_SA (0x81c >> 2)
151 #define GT_DMA0_DA (0x820 >> 2)
152 #define GT_DMA1_DA (0x824 >> 2)
153 #define GT_DMA2_DA (0x828 >> 2)
154 #define GT_DMA3_DA (0x82c >> 2)
155 #define GT_DMA0_NEXT (0x830 >> 2)
156 #define GT_DMA1_NEXT (0x834 >> 2)
157 #define GT_DMA2_NEXT (0x838 >> 2)
158 #define GT_DMA3_NEXT (0x83c >> 2)
159 #define GT_DMA0_CUR (0x870 >> 2)
160 #define GT_DMA1_CUR (0x874 >> 2)
161 #define GT_DMA2_CUR (0x878 >> 2)
162 #define GT_DMA3_CUR (0x87c >> 2)
164 /* DMA Channel Control */
165 #define GT_DMA0_CTRL (0x840 >> 2)
166 #define GT_DMA1_CTRL (0x844 >> 2)
167 #define GT_DMA2_CTRL (0x848 >> 2)
168 #define GT_DMA3_CTRL (0x84c >> 2)
171 #define GT_DMA_ARB (0x860 >> 2)
174 #define GT_TC0 (0x850 >> 2)
175 #define GT_TC1 (0x854 >> 2)
176 #define GT_TC2 (0x858 >> 2)
177 #define GT_TC3 (0x85c >> 2)
178 #define GT_TC_CONTROL (0x864 >> 2)
181 #define GT_PCI0_CMD (0xc00 >> 2)
182 #define GT_PCI0_TOR (0xc04 >> 2)
183 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
184 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
185 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
186 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
187 #define GT_PCI1_IACK (0xc30 >> 2)
188 #define GT_PCI0_IACK (0xc34 >> 2)
189 #define GT_PCI0_BARE (0xc3c >> 2)
190 #define GT_PCI0_PREFMBR (0xc40 >> 2)
191 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
192 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
193 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
194 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
195 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
196 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
197 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
198 #define GT_PCI1_CMD (0xc80 >> 2)
199 #define GT_PCI1_TOR (0xc84 >> 2)
200 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
201 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
202 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
203 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
204 #define GT_PCI1_BARE (0xcbc >> 2)
205 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
206 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
207 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
208 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
209 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
210 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
211 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
212 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
213 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
214 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
215 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
216 #define GT_PCI0_CFGDATA (0xcfc >> 2)
218 REG32(GT_PCI0_CMD
, 0xc00)
219 FIELD(GT_PCI0_CMD
, MByteSwap
, 0, 1)
220 FIELD(GT_PCI0_CMD
, SByteSwap
, 16, 1)
221 #define R_GT_PCI0_CMD_ByteSwap_MASK \
222 (R_GT_PCI0_CMD_MByteSwap_MASK | R_GT_PCI0_CMD_SByteSwap_MASK)
223 REG32(GT_PCI1_CMD
, 0xc80)
224 FIELD(GT_PCI1_CMD
, MByteSwap
, 0, 1)
225 FIELD(GT_PCI1_CMD
, SByteSwap
, 16, 1)
226 #define R_GT_PCI1_CMD_ByteSwap_MASK \
227 (R_GT_PCI1_CMD_MByteSwap_MASK | R_GT_PCI1_CMD_SByteSwap_MASK)
230 #define GT_INTRCAUSE (0xc18 >> 2)
231 #define GT_INTRMASK (0xc1c >> 2)
232 #define GT_PCI0_ICMASK (0xc24 >> 2)
233 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
234 #define GT_CPU_INTSEL (0xc70 >> 2)
235 #define GT_PCI0_INTSEL (0xc74 >> 2)
236 #define GT_HINTRCAUSE (0xc98 >> 2)
237 #define GT_HINTRMASK (0xc9c >> 2)
238 #define GT_PCI0_HICMASK (0xca4 >> 2)
239 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
241 #define PCI_MAPPING_ENTRY(regname) \
242 hwaddr regname ##_start; \
243 hwaddr regname ##_length; \
244 MemoryRegion regname ##_mem
246 #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
248 OBJECT_DECLARE_SIMPLE_TYPE(GT64120State
, GT64120_PCI_HOST_BRIDGE
)
250 struct GT64120State
{
251 PCIHostState parent_obj
;
253 uint32_t regs
[GT_REGS
];
254 PCI_MAPPING_ENTRY(PCI0IO
);
255 PCI_MAPPING_ENTRY(PCI0M0
);
256 PCI_MAPPING_ENTRY(PCI0M1
);
257 PCI_MAPPING_ENTRY(ISD
);
258 MemoryRegion pci0_mem
;
259 AddressSpace pci0_mem_as
;
262 bool cpu_little_endian
;
265 /* Adjust range to avoid touching space which isn't mappable via PCI */
267 * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
268 * 0x1fc00000 - 0x1fd00000
270 static void check_reserved_space(hwaddr
*start
, hwaddr
*length
)
272 hwaddr begin
= *start
;
273 hwaddr end
= *start
+ *length
;
275 if (end
>= 0x1e000000LL
&& end
< 0x1f100000LL
) {
278 if (begin
>= 0x1e000000LL
&& begin
< 0x1f100000LL
) {
279 begin
= 0x1f100000LL
;
281 if (end
>= 0x1fc00000LL
&& end
< 0x1fd00000LL
) {
284 if (begin
>= 0x1fc00000LL
&& begin
< 0x1fd00000LL
) {
285 begin
= 0x1fd00000LL
;
287 /* XXX: This is broken when a reserved range splits the requested range */
288 if (end
>= 0x1f100000LL
&& begin
< 0x1e000000LL
) {
291 if (end
>= 0x1fd00000LL
&& begin
< 0x1fc00000LL
) {
296 *length
= end
- begin
;
299 static void gt64120_isd_mapping(GT64120State
*s
)
301 /* Bits 14:0 of ISD map to bits 35:21 of the start address. */
302 hwaddr start
= ((hwaddr
)s
->regs
[GT_ISD
] << 21) & 0xFFFE00000ull
;
303 hwaddr length
= 0x1000;
305 memory_region_transaction_begin();
308 memory_region_del_subregion(get_system_memory(), &s
->ISD_mem
);
310 check_reserved_space(&start
, &length
);
312 /* Map new address */
313 trace_gt64120_isd_remap(s
->ISD_length
, s
->ISD_start
, length
, start
);
314 s
->ISD_start
= start
;
315 s
->ISD_length
= length
;
316 memory_region_add_subregion(get_system_memory(), s
->ISD_start
, &s
->ISD_mem
);
318 memory_region_transaction_commit();
321 static void gt64120_update_pci_cfgdata_mapping(GT64120State
*s
)
323 /* Indexed on MByteSwap bit, see Table 158: PCI_0 Command, Offset: 0xc00 */
324 static const MemoryRegionOps
*pci_host_data_ops
[] = {
325 &pci_host_data_be_ops
, &pci_host_data_le_ops
327 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
329 memory_region_transaction_begin();
332 * The setting of the MByteSwap bit and MWordSwap bit in the PCI Internal
333 * Command Register determines how data transactions from the CPU to/from
334 * PCI are handled along with the setting of the Endianess bit in the CPU
335 * Configuration Register. See:
336 * - Table 16: 32-bit PCI Transaction Endianess
337 * - Table 158: PCI_0 Command, Offset: 0xc00
340 if (memory_region_is_mapped(&phb
->data_mem
)) {
341 memory_region_del_subregion(&s
->ISD_mem
, &phb
->data_mem
);
342 object_unparent(OBJECT(&phb
->data_mem
));
344 memory_region_init_io(&phb
->data_mem
, OBJECT(phb
),
345 pci_host_data_ops
[s
->regs
[GT_PCI0_CMD
] & 1],
346 s
, "pci-conf-data", 4);
347 memory_region_add_subregion_overlap(&s
->ISD_mem
, GT_PCI0_CFGDATA
<< 2,
350 memory_region_transaction_commit();
353 static void gt64120_pci_mapping(GT64120State
*s
)
355 memory_region_transaction_begin();
357 /* Update PCI0IO mapping */
358 if ((s
->regs
[GT_PCI0IOLD
] & 0x7f) <= s
->regs
[GT_PCI0IOHD
]) {
359 /* Unmap old IO address */
360 if (s
->PCI0IO_length
) {
361 memory_region_del_subregion(get_system_memory(), &s
->PCI0IO_mem
);
362 object_unparent(OBJECT(&s
->PCI0IO_mem
));
364 /* Map new IO address */
365 s
->PCI0IO_start
= s
->regs
[GT_PCI0IOLD
] << 21;
366 s
->PCI0IO_length
= ((s
->regs
[GT_PCI0IOHD
] + 1) -
367 (s
->regs
[GT_PCI0IOLD
] & 0x7f)) << 21;
368 if (s
->PCI0IO_length
) {
369 memory_region_init_alias(&s
->PCI0IO_mem
, OBJECT(s
), "pci0-io",
370 get_system_io(), 0, s
->PCI0IO_length
);
371 memory_region_add_subregion(get_system_memory(), s
->PCI0IO_start
,
376 /* Update PCI0M0 mapping */
377 if ((s
->regs
[GT_PCI0M0LD
] & 0x7f) <= s
->regs
[GT_PCI0M0HD
]) {
378 /* Unmap old MEM address */
379 if (s
->PCI0M0_length
) {
380 memory_region_del_subregion(get_system_memory(), &s
->PCI0M0_mem
);
381 object_unparent(OBJECT(&s
->PCI0M0_mem
));
383 /* Map new mem address */
384 s
->PCI0M0_start
= s
->regs
[GT_PCI0M0LD
] << 21;
385 s
->PCI0M0_length
= ((s
->regs
[GT_PCI0M0HD
] + 1) -
386 (s
->regs
[GT_PCI0M0LD
] & 0x7f)) << 21;
387 if (s
->PCI0M0_length
) {
388 memory_region_init_alias(&s
->PCI0M0_mem
, OBJECT(s
), "pci0-mem0",
389 &s
->pci0_mem
, s
->PCI0M0_start
,
391 memory_region_add_subregion(get_system_memory(), s
->PCI0M0_start
,
396 /* Update PCI0M1 mapping */
397 if ((s
->regs
[GT_PCI0M1LD
] & 0x7f) <= s
->regs
[GT_PCI0M1HD
]) {
398 /* Unmap old MEM address */
399 if (s
->PCI0M1_length
) {
400 memory_region_del_subregion(get_system_memory(), &s
->PCI0M1_mem
);
401 object_unparent(OBJECT(&s
->PCI0M1_mem
));
403 /* Map new mem address */
404 s
->PCI0M1_start
= s
->regs
[GT_PCI0M1LD
] << 21;
405 s
->PCI0M1_length
= ((s
->regs
[GT_PCI0M1HD
] + 1) -
406 (s
->regs
[GT_PCI0M1LD
] & 0x7f)) << 21;
407 if (s
->PCI0M1_length
) {
408 memory_region_init_alias(&s
->PCI0M1_mem
, OBJECT(s
), "pci0-mem1",
409 &s
->pci0_mem
, s
->PCI0M1_start
,
411 memory_region_add_subregion(get_system_memory(), s
->PCI0M1_start
,
416 memory_region_transaction_commit();
419 static int gt64120_post_load(void *opaque
, int version_id
)
421 GT64120State
*s
= opaque
;
423 gt64120_isd_mapping(s
);
424 gt64120_pci_mapping(s
);
429 static const VMStateDescription vmstate_gt64120
= {
432 .minimum_version_id
= 1,
433 .post_load
= gt64120_post_load
,
434 .fields
= (VMStateField
[]) {
435 VMSTATE_UINT32_ARRAY(regs
, GT64120State
, GT_REGS
),
436 VMSTATE_END_OF_LIST()
440 static void gt64120_writel(void *opaque
, hwaddr addr
,
441 uint64_t val
, unsigned size
)
443 GT64120State
*s
= opaque
;
444 uint32_t saddr
= addr
>> 2;
446 trace_gt64120_write(addr
, val
);
447 if (!(s
->regs
[GT_CPU
] & 0x00001000)) {
453 /* CPU Configuration */
455 s
->regs
[GT_CPU
] = val
;
458 /* Read-only register as only one GT64xxx is present on the CPU bus */
461 /* CPU Address Decode */
463 s
->regs
[GT_PCI0IOLD
] = val
& 0x00007fff;
464 s
->regs
[GT_PCI0IOREMAP
] = val
& 0x000007ff;
465 gt64120_pci_mapping(s
);
468 s
->regs
[GT_PCI0M0LD
] = val
& 0x00007fff;
469 s
->regs
[GT_PCI0M0REMAP
] = val
& 0x000007ff;
470 gt64120_pci_mapping(s
);
473 s
->regs
[GT_PCI0M1LD
] = val
& 0x00007fff;
474 s
->regs
[GT_PCI0M1REMAP
] = val
& 0x000007ff;
475 gt64120_pci_mapping(s
);
478 s
->regs
[GT_PCI1IOLD
] = val
& 0x00007fff;
479 s
->regs
[GT_PCI1IOREMAP
] = val
& 0x000007ff;
482 s
->regs
[GT_PCI1M0LD
] = val
& 0x00007fff;
483 s
->regs
[GT_PCI1M0REMAP
] = val
& 0x000007ff;
486 s
->regs
[GT_PCI1M1LD
] = val
& 0x00007fff;
487 s
->regs
[GT_PCI1M1REMAP
] = val
& 0x000007ff;
492 s
->regs
[saddr
] = val
& 0x0000007f;
493 gt64120_pci_mapping(s
);
498 s
->regs
[saddr
] = val
& 0x0000007f;
501 s
->regs
[saddr
] = val
& 0x00007fff;
502 gt64120_isd_mapping(s
);
511 s
->regs
[saddr
] = val
& 0x000007ff;
514 /* CPU Error Report */
515 case GT_CPUERR_ADDRLO
:
516 case GT_CPUERR_ADDRHI
:
517 case GT_CPUERR_DATALO
:
518 case GT_CPUERR_DATAHI
:
519 case GT_CPUERR_PARITY
:
520 /* Read-only registers, do nothing */
521 qemu_log_mask(LOG_GUEST_ERROR
,
522 "gt64120: Read-only register write "
523 "reg:0x%03x size:%u value:0x%0*" PRIx64
"\n",
524 saddr
<< 2, size
, size
<< 1, val
);
527 /* CPU Sync Barrier */
530 /* Read-only registers, do nothing */
531 qemu_log_mask(LOG_GUEST_ERROR
,
532 "gt64120: Read-only register write "
533 "reg:0x%03x size:%u value:0x%0*" PRIx64
"\n",
534 saddr
<< 2, size
, size
<< 1, val
);
537 /* SDRAM and Device Address Decode */
557 /* SDRAM Configuration */
559 case GT_SDRAM_OPMODE
:
561 case GT_SDRAM_ADDRDECODE
:
562 /* Accept and ignore SDRAM interleave configuration */
563 s
->regs
[saddr
] = val
;
566 /* Device Parameters */
572 /* Not implemented */
573 qemu_log_mask(LOG_UNIMP
,
574 "gt64120: Unimplemented device register write "
575 "reg:0x%03x size:%u value:0x%0*" PRIx64
"\n",
576 saddr
<< 2, size
, size
<< 1, val
);
580 case GT_ECC_ERRDATALO
:
581 case GT_ECC_ERRDATAHI
:
585 /* Read-only registers, do nothing */
586 qemu_log_mask(LOG_GUEST_ERROR
,
587 "gt64120: Read-only register write "
588 "reg:0x%03x size:%u value:0x%0*" PRIx64
"\n",
589 saddr
<< 2, size
, size
<< 1, val
);
614 /* DMA Channel Control */
622 /* Not implemented */
623 qemu_log_mask(LOG_UNIMP
,
624 "gt64120: Unimplemented DMA register write "
625 "reg:0x%03x size:%u value:0x%0*" PRIx64
"\n",
626 saddr
<< 2, size
, size
<< 1, val
);
635 /* Not implemented */
636 qemu_log_mask(LOG_UNIMP
,
637 "gt64120: Unimplemented timer register write "
638 "reg:0x%03x size:%u value:0x%0*" PRIx64
"\n",
639 saddr
<< 2, size
, size
<< 1, val
);
645 s
->regs
[saddr
] = val
& 0x0401fc0f;
646 gt64120_update_pci_cfgdata_mapping(s
);
649 case GT_PCI0_BS_SCS10
:
650 case GT_PCI0_BS_SCS32
:
651 case GT_PCI0_BS_CS20
:
652 case GT_PCI0_BS_CS3BT
:
656 case GT_PCI0_PREFMBR
:
657 case GT_PCI0_SCS10_BAR
:
658 case GT_PCI0_SCS32_BAR
:
659 case GT_PCI0_CS20_BAR
:
660 case GT_PCI0_CS3BT_BAR
:
661 case GT_PCI0_SSCS10_BAR
:
662 case GT_PCI0_SSCS32_BAR
:
663 case GT_PCI0_SCS3BT_BAR
:
665 case GT_PCI1_BS_SCS10
:
666 case GT_PCI1_BS_SCS32
:
667 case GT_PCI1_BS_CS20
:
668 case GT_PCI1_BS_CS3BT
:
670 case GT_PCI1_PREFMBR
:
671 case GT_PCI1_SCS10_BAR
:
672 case GT_PCI1_SCS32_BAR
:
673 case GT_PCI1_CS20_BAR
:
674 case GT_PCI1_CS3BT_BAR
:
675 case GT_PCI1_SSCS10_BAR
:
676 case GT_PCI1_SSCS32_BAR
:
677 case GT_PCI1_SCS3BT_BAR
:
678 case GT_PCI1_CFGADDR
:
679 case GT_PCI1_CFGDATA
:
680 /* not implemented */
681 qemu_log_mask(LOG_UNIMP
,
682 "gt64120: Unimplemented PCI register write "
683 "reg:0x%03x size:%u value:0x%0*" PRIx64
"\n",
684 saddr
<< 2, size
, size
<< 1, val
);
686 case GT_PCI0_CFGADDR
:
687 case GT_PCI0_CFGDATA
:
688 /* Mapped via in gt64120_pci_mapping() */
689 g_assert_not_reached();
694 /* not really implemented */
695 s
->regs
[saddr
] = ~(~(s
->regs
[saddr
]) | ~(val
& 0xfffffffe));
696 s
->regs
[saddr
] |= !!(s
->regs
[saddr
] & 0xfffffffe);
697 trace_gt64120_write_intreg("INTRCAUSE", size
, val
);
700 s
->regs
[saddr
] = val
& 0x3c3ffffe;
701 trace_gt64120_write_intreg("INTRMASK", size
, val
);
704 s
->regs
[saddr
] = val
& 0x03fffffe;
705 trace_gt64120_write_intreg("ICMASK", size
, val
);
707 case GT_PCI0_SERR0MASK
:
708 s
->regs
[saddr
] = val
& 0x0000003f;
709 trace_gt64120_write_intreg("SERR0MASK", size
, val
);
712 /* Reserved when only PCI_0 is configured. */
717 case GT_PCI0_HICMASK
:
718 case GT_PCI1_SERR1MASK
:
719 /* not implemented */
722 /* SDRAM Parameters */
728 * We don't simulate electrical parameters of the SDRAM.
729 * Accept, but ignore the values.
731 s
->regs
[saddr
] = val
;
735 qemu_log_mask(LOG_GUEST_ERROR
,
736 "gt64120: Illegal register write "
737 "reg:0x%03x size:%u value:0x%0*" PRIx64
"\n",
738 saddr
<< 2, size
, size
<< 1, val
);
743 static uint64_t gt64120_readl(void *opaque
,
744 hwaddr addr
, unsigned size
)
746 GT64120State
*s
= opaque
;
748 uint32_t saddr
= addr
>> 2;
752 /* CPU Configuration */
755 * Only one GT64xxx is present on the CPU bus, return
758 val
= s
->regs
[saddr
];
761 /* CPU Error Report */
762 case GT_CPUERR_ADDRLO
:
763 case GT_CPUERR_ADDRHI
:
764 case GT_CPUERR_DATALO
:
765 case GT_CPUERR_DATAHI
:
766 case GT_CPUERR_PARITY
:
767 /* Emulated memory has no error, always return the initial values. */
768 val
= s
->regs
[saddr
];
771 /* CPU Sync Barrier */
775 * Reading those register should empty all FIFO on the PCI
776 * bus, which are not emulated. The return value should be
777 * a random value that should be ignored.
783 case GT_ECC_ERRDATALO
:
784 case GT_ECC_ERRDATAHI
:
788 /* Emulated memory has no error, always return the initial values. */
789 val
= s
->regs
[saddr
];
824 val
= s
->regs
[saddr
];
827 /* Read the IRQ number */
828 val
= pic_read_irq(isa_pic
);
831 /* SDRAM and Device Address Decode */
851 val
= s
->regs
[saddr
];
854 /* SDRAM Configuration */
856 case GT_SDRAM_OPMODE
:
858 case GT_SDRAM_ADDRDECODE
:
859 val
= s
->regs
[saddr
];
862 /* SDRAM Parameters */
868 * We don't simulate electrical parameters of the SDRAM.
869 * Just return the last written value.
871 val
= s
->regs
[saddr
];
874 /* Device Parameters */
880 val
= s
->regs
[saddr
];
904 val
= s
->regs
[saddr
];
907 /* DMA Channel Control */
912 val
= s
->regs
[saddr
];
917 val
= s
->regs
[saddr
];
926 val
= s
->regs
[saddr
];
930 case GT_PCI0_CFGADDR
:
931 case GT_PCI0_CFGDATA
:
932 /* Mapped via in gt64120_pci_mapping() */
933 g_assert_not_reached();
938 case GT_PCI0_BS_SCS10
:
939 case GT_PCI0_BS_SCS32
:
940 case GT_PCI0_BS_CS20
:
941 case GT_PCI0_BS_CS3BT
:
944 case GT_PCI0_PREFMBR
:
945 case GT_PCI0_SCS10_BAR
:
946 case GT_PCI0_SCS32_BAR
:
947 case GT_PCI0_CS20_BAR
:
948 case GT_PCI0_CS3BT_BAR
:
949 case GT_PCI0_SSCS10_BAR
:
950 case GT_PCI0_SSCS32_BAR
:
951 case GT_PCI0_SCS3BT_BAR
:
954 case GT_PCI1_BS_SCS10
:
955 case GT_PCI1_BS_SCS32
:
956 case GT_PCI1_BS_CS20
:
957 case GT_PCI1_BS_CS3BT
:
959 case GT_PCI1_PREFMBR
:
960 case GT_PCI1_SCS10_BAR
:
961 case GT_PCI1_SCS32_BAR
:
962 case GT_PCI1_CS20_BAR
:
963 case GT_PCI1_CS3BT_BAR
:
964 case GT_PCI1_SSCS10_BAR
:
965 case GT_PCI1_SSCS32_BAR
:
966 case GT_PCI1_SCS3BT_BAR
:
967 case GT_PCI1_CFGADDR
:
968 case GT_PCI1_CFGDATA
:
969 val
= s
->regs
[saddr
];
974 val
= s
->regs
[saddr
];
975 trace_gt64120_read_intreg("INTRCAUSE", size
, val
);
978 val
= s
->regs
[saddr
];
979 trace_gt64120_read_intreg("INTRMASK", size
, val
);
982 val
= s
->regs
[saddr
];
983 trace_gt64120_read_intreg("ICMASK", size
, val
);
985 case GT_PCI0_SERR0MASK
:
986 val
= s
->regs
[saddr
];
987 trace_gt64120_read_intreg("SERR0MASK", size
, val
);
990 /* Reserved when only PCI_0 is configured. */
995 case GT_PCI0_HICMASK
:
996 case GT_PCI1_SERR1MASK
:
997 val
= s
->regs
[saddr
];
1001 val
= s
->regs
[saddr
];
1002 qemu_log_mask(LOG_GUEST_ERROR
,
1003 "gt64120: Illegal register read "
1004 "reg:0x%03x size:%u value:0x%0*x\n",
1005 saddr
<< 2, size
, size
<< 1, val
);
1009 if (!(s
->regs
[GT_CPU
] & 0x00001000)) {
1012 trace_gt64120_read(addr
, val
);
1017 static const MemoryRegionOps isd_mem_ops
= {
1018 .read
= gt64120_readl
,
1019 .write
= gt64120_writel
,
1020 .endianness
= DEVICE_NATIVE_ENDIAN
,
1022 .min_access_size
= 4,
1023 .max_access_size
= 4,
1027 static void gt64120_reset(DeviceState
*dev
)
1029 GT64120State
*s
= GT64120_PCI_HOST_BRIDGE(dev
);
1031 /* FIXME: Malta specific hw assumptions ahead */
1033 /* CPU Configuration */
1034 s
->regs
[GT_CPU
] = s
->cpu_little_endian
? R_GT_CPU_Endianness_MASK
: 0;
1035 s
->regs
[GT_MULTI
] = 0x00000003;
1037 /* CPU Address decode */
1038 s
->regs
[GT_SCS10LD
] = 0x00000000;
1039 s
->regs
[GT_SCS10HD
] = 0x00000007;
1040 s
->regs
[GT_SCS32LD
] = 0x00000008;
1041 s
->regs
[GT_SCS32HD
] = 0x0000000f;
1042 s
->regs
[GT_CS20LD
] = 0x000000e0;
1043 s
->regs
[GT_CS20HD
] = 0x00000070;
1044 s
->regs
[GT_CS3BOOTLD
] = 0x000000f8;
1045 s
->regs
[GT_CS3BOOTHD
] = 0x0000007f;
1047 s
->regs
[GT_PCI0IOLD
] = 0x00000080;
1048 s
->regs
[GT_PCI0IOHD
] = 0x0000000f;
1049 s
->regs
[GT_PCI0M0LD
] = 0x00000090;
1050 s
->regs
[GT_PCI0M0HD
] = 0x0000001f;
1051 s
->regs
[GT_ISD
] = 0x000000a0;
1052 s
->regs
[GT_PCI0M1LD
] = 0x00000790;
1053 s
->regs
[GT_PCI0M1HD
] = 0x0000001f;
1054 s
->regs
[GT_PCI1IOLD
] = 0x00000100;
1055 s
->regs
[GT_PCI1IOHD
] = 0x0000000f;
1056 s
->regs
[GT_PCI1M0LD
] = 0x00000110;
1057 s
->regs
[GT_PCI1M0HD
] = 0x0000001f;
1058 s
->regs
[GT_PCI1M1LD
] = 0x00000120;
1059 s
->regs
[GT_PCI1M1HD
] = 0x0000002f;
1061 s
->regs
[GT_SCS10AR
] = 0x00000000;
1062 s
->regs
[GT_SCS32AR
] = 0x00000008;
1063 s
->regs
[GT_CS20R
] = 0x000000e0;
1064 s
->regs
[GT_CS3BOOTR
] = 0x000000f8;
1066 s
->regs
[GT_PCI0IOREMAP
] = 0x00000080;
1067 s
->regs
[GT_PCI0M0REMAP
] = 0x00000090;
1068 s
->regs
[GT_PCI0M1REMAP
] = 0x00000790;
1069 s
->regs
[GT_PCI1IOREMAP
] = 0x00000100;
1070 s
->regs
[GT_PCI1M0REMAP
] = 0x00000110;
1071 s
->regs
[GT_PCI1M1REMAP
] = 0x00000120;
1073 /* CPU Error Report */
1074 s
->regs
[GT_CPUERR_ADDRLO
] = 0x00000000;
1075 s
->regs
[GT_CPUERR_ADDRHI
] = 0x00000000;
1076 s
->regs
[GT_CPUERR_DATALO
] = 0xffffffff;
1077 s
->regs
[GT_CPUERR_DATAHI
] = 0xffffffff;
1078 s
->regs
[GT_CPUERR_PARITY
] = 0x000000ff;
1080 /* CPU Sync Barrier */
1081 s
->regs
[GT_PCI0SYNC
] = 0x00000000;
1082 s
->regs
[GT_PCI1SYNC
] = 0x00000000;
1084 /* SDRAM and Device Address Decode */
1085 s
->regs
[GT_SCS0LD
] = 0x00000000;
1086 s
->regs
[GT_SCS0HD
] = 0x00000007;
1087 s
->regs
[GT_SCS1LD
] = 0x00000008;
1088 s
->regs
[GT_SCS1HD
] = 0x0000000f;
1089 s
->regs
[GT_SCS2LD
] = 0x00000010;
1090 s
->regs
[GT_SCS2HD
] = 0x00000017;
1091 s
->regs
[GT_SCS3LD
] = 0x00000018;
1092 s
->regs
[GT_SCS3HD
] = 0x0000001f;
1093 s
->regs
[GT_CS0LD
] = 0x000000c0;
1094 s
->regs
[GT_CS0HD
] = 0x000000c7;
1095 s
->regs
[GT_CS1LD
] = 0x000000c8;
1096 s
->regs
[GT_CS1HD
] = 0x000000cf;
1097 s
->regs
[GT_CS2LD
] = 0x000000d0;
1098 s
->regs
[GT_CS2HD
] = 0x000000df;
1099 s
->regs
[GT_CS3LD
] = 0x000000f0;
1100 s
->regs
[GT_CS3HD
] = 0x000000fb;
1101 s
->regs
[GT_BOOTLD
] = 0x000000fc;
1102 s
->regs
[GT_BOOTHD
] = 0x000000ff;
1103 s
->regs
[GT_ADERR
] = 0xffffffff;
1105 /* SDRAM Configuration */
1106 s
->regs
[GT_SDRAM_CFG
] = 0x00000200;
1107 s
->regs
[GT_SDRAM_OPMODE
] = 0x00000000;
1108 s
->regs
[GT_SDRAM_BM
] = 0x00000007;
1109 s
->regs
[GT_SDRAM_ADDRDECODE
] = 0x00000002;
1111 /* SDRAM Parameters */
1112 s
->regs
[GT_SDRAM_B0
] = 0x00000005;
1113 s
->regs
[GT_SDRAM_B1
] = 0x00000005;
1114 s
->regs
[GT_SDRAM_B2
] = 0x00000005;
1115 s
->regs
[GT_SDRAM_B3
] = 0x00000005;
1118 s
->regs
[GT_ECC_ERRDATALO
] = 0x00000000;
1119 s
->regs
[GT_ECC_ERRDATAHI
] = 0x00000000;
1120 s
->regs
[GT_ECC_MEM
] = 0x00000000;
1121 s
->regs
[GT_ECC_CALC
] = 0x00000000;
1122 s
->regs
[GT_ECC_ERRADDR
] = 0x00000000;
1124 /* Device Parameters */
1125 s
->regs
[GT_DEV_B0
] = 0x386fffff;
1126 s
->regs
[GT_DEV_B1
] = 0x386fffff;
1127 s
->regs
[GT_DEV_B2
] = 0x386fffff;
1128 s
->regs
[GT_DEV_B3
] = 0x386fffff;
1129 s
->regs
[GT_DEV_BOOT
] = 0x146fffff;
1131 /* DMA registers are all zeroed at reset */
1134 s
->regs
[GT_TC0
] = 0xffffffff;
1135 s
->regs
[GT_TC1
] = 0x00ffffff;
1136 s
->regs
[GT_TC2
] = 0x00ffffff;
1137 s
->regs
[GT_TC3
] = 0x00ffffff;
1138 s
->regs
[GT_TC_CONTROL
] = 0x00000000;
1141 s
->regs
[GT_PCI0_CMD
] = s
->cpu_little_endian
? R_GT_PCI0_CMD_ByteSwap_MASK
: 0;
1142 s
->regs
[GT_PCI0_TOR
] = 0x0000070f;
1143 s
->regs
[GT_PCI0_BS_SCS10
] = 0x00fff000;
1144 s
->regs
[GT_PCI0_BS_SCS32
] = 0x00fff000;
1145 s
->regs
[GT_PCI0_BS_CS20
] = 0x01fff000;
1146 s
->regs
[GT_PCI0_BS_CS3BT
] = 0x00fff000;
1147 s
->regs
[GT_PCI1_IACK
] = 0x00000000;
1148 s
->regs
[GT_PCI0_IACK
] = 0x00000000;
1149 s
->regs
[GT_PCI0_BARE
] = 0x0000000f;
1150 s
->regs
[GT_PCI0_PREFMBR
] = 0x00000040;
1151 s
->regs
[GT_PCI0_SCS10_BAR
] = 0x00000000;
1152 s
->regs
[GT_PCI0_SCS32_BAR
] = 0x01000000;
1153 s
->regs
[GT_PCI0_CS20_BAR
] = 0x1c000000;
1154 s
->regs
[GT_PCI0_CS3BT_BAR
] = 0x1f000000;
1155 s
->regs
[GT_PCI0_SSCS10_BAR
] = 0x00000000;
1156 s
->regs
[GT_PCI0_SSCS32_BAR
] = 0x01000000;
1157 s
->regs
[GT_PCI0_SCS3BT_BAR
] = 0x1f000000;
1158 s
->regs
[GT_PCI1_CMD
] = s
->cpu_little_endian
? R_GT_PCI1_CMD_ByteSwap_MASK
: 0;
1159 s
->regs
[GT_PCI1_TOR
] = 0x0000070f;
1160 s
->regs
[GT_PCI1_BS_SCS10
] = 0x00fff000;
1161 s
->regs
[GT_PCI1_BS_SCS32
] = 0x00fff000;
1162 s
->regs
[GT_PCI1_BS_CS20
] = 0x01fff000;
1163 s
->regs
[GT_PCI1_BS_CS3BT
] = 0x00fff000;
1164 s
->regs
[GT_PCI1_BARE
] = 0x0000000f;
1165 s
->regs
[GT_PCI1_PREFMBR
] = 0x00000040;
1166 s
->regs
[GT_PCI1_SCS10_BAR
] = 0x00000000;
1167 s
->regs
[GT_PCI1_SCS32_BAR
] = 0x01000000;
1168 s
->regs
[GT_PCI1_CS20_BAR
] = 0x1c000000;
1169 s
->regs
[GT_PCI1_CS3BT_BAR
] = 0x1f000000;
1170 s
->regs
[GT_PCI1_SSCS10_BAR
] = 0x00000000;
1171 s
->regs
[GT_PCI1_SSCS32_BAR
] = 0x01000000;
1172 s
->regs
[GT_PCI1_SCS3BT_BAR
] = 0x1f000000;
1173 s
->regs
[GT_PCI1_CFGADDR
] = 0x00000000;
1174 s
->regs
[GT_PCI1_CFGDATA
] = 0x00000000;
1175 s
->regs
[GT_PCI0_CFGADDR
] = 0x00000000;
1177 /* Interrupt registers are all zeroed at reset */
1179 gt64120_isd_mapping(s
);
1180 gt64120_pci_mapping(s
);
1181 gt64120_update_pci_cfgdata_mapping(s
);
1184 static void gt64120_realize(DeviceState
*dev
, Error
**errp
)
1186 GT64120State
*s
= GT64120_PCI_HOST_BRIDGE(dev
);
1187 PCIHostState
*phb
= PCI_HOST_BRIDGE(dev
);
1189 memory_region_init_io(&s
->ISD_mem
, OBJECT(dev
), &isd_mem_ops
, s
,
1190 "gt64120-isd", 0x1000);
1191 memory_region_init(&s
->pci0_mem
, OBJECT(dev
), "pci0-mem", 4 * GiB
);
1192 address_space_init(&s
->pci0_mem_as
, &s
->pci0_mem
, "pci0-mem");
1193 phb
->bus
= pci_root_bus_new(dev
, "pci",
1196 PCI_DEVFN(18, 0), TYPE_PCI_BUS
);
1198 pci_create_simple(phb
->bus
, PCI_DEVFN(0, 0), "gt64120_pci");
1199 memory_region_init_io(&phb
->conf_mem
, OBJECT(phb
),
1200 &pci_host_conf_le_ops
,
1201 s
, "pci-conf-idx", 4);
1202 memory_region_add_subregion_overlap(&s
->ISD_mem
, GT_PCI0_CFGADDR
<< 2,
1207 * The whole address space decoded by the GT-64120A doesn't generate
1208 * exception when accessing invalid memory. Create an empty slot to
1209 * emulate this feature.
1211 empty_slot_init("GT64120", 0, 0x20000000);
1214 static void gt64120_pci_realize(PCIDevice
*d
, Error
**errp
)
1216 /* FIXME: Malta specific hw assumptions ahead */
1217 //~ pci_set_word(d->config + PCI_COMMAND, 0);
1218 pci_set_word(d
->config
+ PCI_STATUS
,
1219 PCI_STATUS_FAST_BACK
| PCI_STATUS_DEVSEL_MEDIUM
);
1220 pci_config_set_prog_interface(d
->config
, 0);
1221 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_0
, 0x00000008);
1222 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_1
, 0x01000008);
1223 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_2
, 0x1c000000);
1224 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_3
, 0x1f000000);
1225 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_4
, 0x14000000);
1226 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_5
, 0x14000001);
1227 pci_set_byte(d
->config
+ 0x3d, 0x01);
1230 static void gt64120_pci_class_init(ObjectClass
*klass
, void *data
)
1232 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1233 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1235 k
->realize
= gt64120_pci_realize
;
1236 k
->vendor_id
= PCI_VENDOR_ID_MARVELL
;
1237 k
->device_id
= PCI_DEVICE_ID_MARVELL_GT6412X
;
1239 k
->class_id
= PCI_CLASS_BRIDGE_HOST
;
1241 * PCI-facing part of the host bridge, not usable without the
1242 * host-facing part, which can't be device_add'ed, yet.
1244 dc
->user_creatable
= false;
1247 static const TypeInfo gt64120_pci_info
= {
1248 .name
= "gt64120_pci",
1249 .parent
= TYPE_PCI_DEVICE
,
1250 .instance_size
= sizeof(PCIDevice
),
1251 .class_init
= gt64120_pci_class_init
,
1252 .interfaces
= (InterfaceInfo
[]) {
1253 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
1258 static Property gt64120_properties
[] = {
1259 DEFINE_PROP_BOOL("cpu-little-endian", GT64120State
,
1260 cpu_little_endian
, false),
1261 DEFINE_PROP_END_OF_LIST(),
1264 static void gt64120_class_init(ObjectClass
*klass
, void *data
)
1266 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1268 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
1269 device_class_set_props(dc
, gt64120_properties
);
1270 dc
->realize
= gt64120_realize
;
1271 dc
->reset
= gt64120_reset
;
1272 dc
->vmsd
= &vmstate_gt64120
;
1275 static const TypeInfo gt64120_info
= {
1276 .name
= TYPE_GT64120_PCI_HOST_BRIDGE
,
1277 .parent
= TYPE_PCI_HOST_BRIDGE
,
1278 .instance_size
= sizeof(GT64120State
),
1279 .class_init
= gt64120_class_init
,
1282 static void gt64120_pci_register_types(void)
1284 type_register_static(>64120_info
);
1285 type_register_static(>64120_pci_info
);
1288 type_init(gt64120_pci_register_types
)