hw/block/nand.c

   1 /*
   2  * Flash NAND memory emulation.  Based on "16M x 8 Bit NAND Flash
   3  * Memory" datasheet for the KM29U128AT / K9F2808U0A chips from
   4  * Samsung Electronic.
   5  *
   6  * Copyright (c) 2006 Openedhand Ltd.
   7  * Written by Andrzej Zaborowski <balrog@zabor.org>
   8  *
   9  * Support for additional features based on "MT29F2G16ABCWP 2Gx16"
  10  * datasheet from Micron Technology and "NAND02G-B2C" datasheet
  11  * from ST Microelectronics.
  12  *
  13  * This code is licensed under the GNU GPL v2.
  14  *
  15  * Contributions after 2012-01-13 are licensed under the terms of the
  16  * GNU GPL, version 2 or (at your option) any later version.
  17  */
  18
  19 #ifndef NAND_IO
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/hw.h"
  23 #include "hw/block/flash.h"
  24 #include "sysemu/block-backend.h"
  25 #include "hw/qdev.h"
  26 #include "qapi/error.h"
  27 #include "qemu/error-report.h"
  28
  29 # define NAND_CMD_READ0         0x00
  30 # define NAND_CMD_READ1         0x01
  31 # define NAND_CMD_READ2         0x50
  32 # define NAND_CMD_LPREAD2       0x30
  33 # define NAND_CMD_NOSERIALREAD2 0x35
  34 # define NAND_CMD_RANDOMREAD1   0x05
  35 # define NAND_CMD_RANDOMREAD2   0xe0
  36 # define NAND_CMD_READID        0x90
  37 # define NAND_CMD_RESET         0xff
  38 # define NAND_CMD_PAGEPROGRAM1  0x80
  39 # define NAND_CMD_PAGEPROGRAM2  0x10
  40 # define NAND_CMD_CACHEPROGRAM2 0x15
  41 # define NAND_CMD_BLOCKERASE1   0x60
  42 # define NAND_CMD_BLOCKERASE2   0xd0
  43 # define NAND_CMD_READSTATUS    0x70
  44 # define NAND_CMD_COPYBACKPRG1  0x85
  45
  46 # define NAND_IOSTATUS_ERROR    (1 << 0)
  47 # define NAND_IOSTATUS_PLANE0   (1 << 1)
  48 # define NAND_IOSTATUS_PLANE1   (1 << 2)
  49 # define NAND_IOSTATUS_PLANE2   (1 << 3)
  50 # define NAND_IOSTATUS_PLANE3   (1 << 4)
  51 # define NAND_IOSTATUS_READY    (1 << 6)
  52 # define NAND_IOSTATUS_UNPROTCT (1 << 7)
  53
  54 # define MAX_PAGE               0x800
  55 # define MAX_OOB                0x40
  56
  57 typedef struct NANDFlashState NANDFlashState;
  58 struct NANDFlashState {
  59     DeviceState parent_obj;
  60
  61     uint8_t manf_id, chip_id;
  62     uint8_t buswidth; /* in BYTES */
  63     int size, pages;
  64     int page_shift, oob_shift, erase_shift, addr_shift;
  65     uint8_t *storage;
  66     BlockBackend *blk;
  67     int mem_oob;
  68
  69     uint8_t cle, ale, ce, wp, gnd;
  70
  71     uint8_t io[MAX_PAGE + MAX_OOB + 0x400];
  72     uint8_t *ioaddr;
  73     int iolen;
  74
  75     uint32_t cmd;
  76     uint64_t addr;
  77     int addrlen;
  78     int status;
  79     int offset;
  80
  81     void (*blk_write)(NANDFlashState *s);
  82     void (*blk_erase)(NANDFlashState *s);
  83     void (*blk_load)(NANDFlashState *s, uint64_t addr, int offset);
  84
  85     uint32_t ioaddr_vmstate;
  86 };
  87
  88 #define TYPE_NAND "nand"
  89
  90 #define NAND(obj) \
  91     OBJECT_CHECK(NANDFlashState, (obj), TYPE_NAND)
  92
  93 static void mem_and(uint8_t *dest, const uint8_t *src, size_t n)
  94 {
  95     /* Like memcpy() but we logical-AND the data into the destination */
  96     int i;
  97     for (i = 0; i < n; i++) {
  98         dest[i] &= src[i];
  99     }
 100 }
 101
 102 # define NAND_NO_AUTOINCR       0x00000001
 103 # define NAND_BUSWIDTH_16       0x00000002
 104 # define NAND_NO_PADDING        0x00000004
 105 # define NAND_CACHEPRG          0x00000008
 106 # define NAND_COPYBACK          0x00000010
 107 # define NAND_IS_AND            0x00000020
 108 # define NAND_4PAGE_ARRAY       0x00000040
 109 # define NAND_NO_READRDY        0x00000100
 110 # define NAND_SAMSUNG_LP        (NAND_NO_PADDING | NAND_COPYBACK)
 111
 112 # define NAND_IO
 113
 114 # define PAGE(addr)             ((addr) >> ADDR_SHIFT)
 115 # define PAGE_START(page)       (PAGE(page) * (PAGE_SIZE + OOB_SIZE))
 116 # define PAGE_MASK              ((1 << ADDR_SHIFT) - 1)
 117 # define OOB_SHIFT              (PAGE_SHIFT - 5)
 118 # define OOB_SIZE               (1 << OOB_SHIFT)
 119 # define SECTOR(addr)           ((addr) >> (9 + ADDR_SHIFT - PAGE_SHIFT))
 120 # define SECTOR_OFFSET(addr)    ((addr) & ((511 >> PAGE_SHIFT) << 8))
 121
 122 # define PAGE_SIZE              256
 123 # define PAGE_SHIFT             8
 124 # define PAGE_SECTORS           1
 125 # define ADDR_SHIFT             8
 126 # include "nand.c"
 127 # define PAGE_SIZE              512
 128 # define PAGE_SHIFT             9
 129 # define PAGE_SECTORS           1
 130 # define ADDR_SHIFT             8
 131 # include "nand.c"
 132 # define PAGE_SIZE              2048
 133 # define PAGE_SHIFT             11
 134 # define PAGE_SECTORS           4
 135 # define ADDR_SHIFT             16
 136 # include "nand.c"
 137
 138 /* Information based on Linux drivers/mtd/nand/nand_ids.c */
 139 static const struct {
 140     int size;
 141     int width;
 142     int page_shift;
 143     int erase_shift;
 144     uint32_t options;
 145 } nand_flash_ids[0x100] = {
 146     [0 ... 0xff] = { 0 },
 147
 148     [0x6e] = { 1,       8,      8, 4, 0 },
 149     [0x64] = { 2,       8,      8, 4, 0 },
 150     [0x6b] = { 4,       8,      9, 4, 0 },
 151     [0xe8] = { 1,       8,      8, 4, 0 },
 152     [0xec] = { 1,       8,      8, 4, 0 },
 153     [0xea] = { 2,       8,      8, 4, 0 },
 154     [0xd5] = { 4,       8,      9, 4, 0 },
 155     [0xe3] = { 4,       8,      9, 4, 0 },
 156     [0xe5] = { 4,       8,      9, 4, 0 },
 157     [0xd6] = { 8,       8,      9, 4, 0 },
 158
 159     [0x39] = { 8,       8,      9, 4, 0 },
 160     [0xe6] = { 8,       8,      9, 4, 0 },
 161     [0x49] = { 8,       16,     9, 4, NAND_BUSWIDTH_16 },
 162     [0x59] = { 8,       16,     9, 4, NAND_BUSWIDTH_16 },
 163
 164     [0x33] = { 16,      8,      9, 5, 0 },
 165     [0x73] = { 16,      8,      9, 5, 0 },
 166     [0x43] = { 16,      16,     9, 5, NAND_BUSWIDTH_16 },
 167     [0x53] = { 16,      16,     9, 5, NAND_BUSWIDTH_16 },
 168
 169     [0x35] = { 32,      8,      9, 5, 0 },
 170     [0x75] = { 32,      8,      9, 5, 0 },
 171     [0x45] = { 32,      16,     9, 5, NAND_BUSWIDTH_16 },
 172     [0x55] = { 32,      16,     9, 5, NAND_BUSWIDTH_16 },
 173
 174     [0x36] = { 64,      8,      9, 5, 0 },
 175     [0x76] = { 64,      8,      9, 5, 0 },
 176     [0x46] = { 64,      16,     9, 5, NAND_BUSWIDTH_16 },
 177     [0x56] = { 64,      16,     9, 5, NAND_BUSWIDTH_16 },
 178
 179     [0x78] = { 128,     8,      9, 5, 0 },
 180     [0x39] = { 128,     8,      9, 5, 0 },
 181     [0x79] = { 128,     8,      9, 5, 0 },
 182     [0x72] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 183     [0x49] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 184     [0x74] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 185     [0x59] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 186
 187     [0x71] = { 256,     8,      9, 5, 0 },
 188
 189     /*
 190      * These are the new chips with large page size. The pagesize and the
 191      * erasesize is determined from the extended id bytes
 192      */
 193 # define LP_OPTIONS     (NAND_SAMSUNG_LP | NAND_NO_READRDY | NAND_NO_AUTOINCR)
 194 # define LP_OPTIONS16   (LP_OPTIONS | NAND_BUSWIDTH_16)
 195
 196     /* 512 Megabit */
 197     [0xa2] = { 64,      8,      0, 0, LP_OPTIONS },
 198     [0xf2] = { 64,      8,      0, 0, LP_OPTIONS },
 199     [0xb2] = { 64,      16,     0, 0, LP_OPTIONS16 },
 200     [0xc2] = { 64,      16,     0, 0, LP_OPTIONS16 },
 201
 202     /* 1 Gigabit */
 203     [0xa1] = { 128,     8,      0, 0, LP_OPTIONS },
 204     [0xf1] = { 128,     8,      0, 0, LP_OPTIONS },
 205     [0xb1] = { 128,     16,     0, 0, LP_OPTIONS16 },
 206     [0xc1] = { 128,     16,     0, 0, LP_OPTIONS16 },
 207
 208     /* 2 Gigabit */
 209     [0xaa] = { 256,     8,      0, 0, LP_OPTIONS },
 210     [0xda] = { 256,     8,      0, 0, LP_OPTIONS },
 211     [0xba] = { 256,     16,     0, 0, LP_OPTIONS16 },
 212     [0xca] = { 256,     16,     0, 0, LP_OPTIONS16 },
 213
 214     /* 4 Gigabit */
 215     [0xac] = { 512,     8,      0, 0, LP_OPTIONS },
 216     [0xdc] = { 512,     8,      0, 0, LP_OPTIONS },
 217     [0xbc] = { 512,     16,     0, 0, LP_OPTIONS16 },
 218     [0xcc] = { 512,     16,     0, 0, LP_OPTIONS16 },
 219
 220     /* 8 Gigabit */
 221     [0xa3] = { 1024,    8,      0, 0, LP_OPTIONS },
 222     [0xd3] = { 1024,    8,      0, 0, LP_OPTIONS },
 223     [0xb3] = { 1024,    16,     0, 0, LP_OPTIONS16 },
 224     [0xc3] = { 1024,    16,     0, 0, LP_OPTIONS16 },
 225
 226     /* 16 Gigabit */
 227     [0xa5] = { 2048,    8,      0, 0, LP_OPTIONS },
 228     [0xd5] = { 2048,    8,      0, 0, LP_OPTIONS },
 229     [0xb5] = { 2048,    16,     0, 0, LP_OPTIONS16 },
 230     [0xc5] = { 2048,    16,     0, 0, LP_OPTIONS16 },
 231 };
 232
 233 static void nand_reset(DeviceState *dev)
 234 {
 235     NANDFlashState *s = NAND(dev);
 236     s->cmd = NAND_CMD_READ0;
 237     s->addr = 0;
 238     s->addrlen = 0;
 239     s->iolen = 0;
 240     s->offset = 0;
 241     s->status &= NAND_IOSTATUS_UNPROTCT;
 242     s->status |= NAND_IOSTATUS_READY;
 243 }
 244
 245 static inline void nand_pushio_byte(NANDFlashState *s, uint8_t value)
 246 {
 247     s->ioaddr[s->iolen++] = value;
 248     for (value = s->buswidth; --value;) {
 249         s->ioaddr[s->iolen++] = 0;
 250     }
 251 }
 252
 253 static void nand_command(NANDFlashState *s)
 254 {
 255     unsigned int offset;
 256     switch (s->cmd) {
 257     case NAND_CMD_READ0:
 258         s->iolen = 0;
 259         break;
 260
 261     case NAND_CMD_READID:
 262         s->ioaddr = s->io;
 263         s->iolen = 0;
 264         nand_pushio_byte(s, s->manf_id);
 265         nand_pushio_byte(s, s->chip_id);
 266         nand_pushio_byte(s, 'Q'); /* Don't-care byte (often 0xa5) */
 267         if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
 268             /* Page Size, Block Size, Spare Size; bit 6 indicates
 269              * 8 vs 16 bit width NAND.
 270              */
 271             nand_pushio_byte(s, (s->buswidth == 2) ? 0x55 : 0x15);
 272         } else {
 273             nand_pushio_byte(s, 0xc0); /* Multi-plane */
 274         }
 275         break;
 276
 277     case NAND_CMD_RANDOMREAD2:
 278     case NAND_CMD_NOSERIALREAD2:
 279         if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP))
 280             break;
 281         offset = s->addr & ((1 << s->addr_shift) - 1);
 282         s->blk_load(s, s->addr, offset);
 283         if (s->gnd)
 284             s->iolen = (1 << s->page_shift) - offset;
 285         else
 286             s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
 287         break;
 288
 289     case NAND_CMD_RESET:
 290         nand_reset(DEVICE(s));
 291         break;
 292
 293     case NAND_CMD_PAGEPROGRAM1:
 294         s->ioaddr = s->io;
 295         s->iolen = 0;
 296         break;
 297
 298     case NAND_CMD_PAGEPROGRAM2:
 299         if (s->wp) {
 300             s->blk_write(s);
 301         }
 302         break;
 303
 304     case NAND_CMD_BLOCKERASE1:
 305         break;
 306
 307     case NAND_CMD_BLOCKERASE2:
 308         s->addr &= (1ull << s->addrlen * 8) - 1;
 309         s->addr <<= nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP ?
 310                                                                     16 : 8;
 311
 312         if (s->wp) {
 313             s->blk_erase(s);
 314         }
 315         break;
 316
 317     case NAND_CMD_READSTATUS:
 318         s->ioaddr = s->io;
 319         s->iolen = 0;
 320         nand_pushio_byte(s, s->status);
 321         break;
 322
 323     default:
 324         printf("%s: Unknown NAND command 0x%02x\n", __FUNCTION__, s->cmd);
 325     }
 326 }
 327
 328 static void nand_pre_save(void *opaque)
 329 {
 330     NANDFlashState *s = NAND(opaque);
 331
 332     s->ioaddr_vmstate = s->ioaddr - s->io;
 333 }
 334
 335 static int nand_post_load(void *opaque, int version_id)
 336 {
 337     NANDFlashState *s = NAND(opaque);
 338
 339     if (s->ioaddr_vmstate > sizeof(s->io)) {
 340         return -EINVAL;
 341     }
 342     s->ioaddr = s->io + s->ioaddr_vmstate;
 343
 344     return 0;
 345 }
 346
 347 static const VMStateDescription vmstate_nand = {
 348     .name = "nand",
 349     .version_id = 1,
 350     .minimum_version_id = 1,
 351     .pre_save = nand_pre_save,
 352     .post_load = nand_post_load,
 353     .fields = (VMStateField[]) {
 354         VMSTATE_UINT8(cle, NANDFlashState),
 355         VMSTATE_UINT8(ale, NANDFlashState),
 356         VMSTATE_UINT8(ce, NANDFlashState),
 357         VMSTATE_UINT8(wp, NANDFlashState),
 358         VMSTATE_UINT8(gnd, NANDFlashState),
 359         VMSTATE_BUFFER(io, NANDFlashState),
 360         VMSTATE_UINT32(ioaddr_vmstate, NANDFlashState),
 361         VMSTATE_INT32(iolen, NANDFlashState),
 362         VMSTATE_UINT32(cmd, NANDFlashState),
 363         VMSTATE_UINT64(addr, NANDFlashState),
 364         VMSTATE_INT32(addrlen, NANDFlashState),
 365         VMSTATE_INT32(status, NANDFlashState),
 366         VMSTATE_INT32(offset, NANDFlashState),
 367         /* XXX: do we want to save s->storage too? */
 368         VMSTATE_END_OF_LIST()
 369     }
 370 };
 371
 372 static void nand_realize(DeviceState *dev, Error **errp)
 373 {
 374     int pagesize;
 375     NANDFlashState *s = NAND(dev);
 376
 377     s->buswidth = nand_flash_ids[s->chip_id].width >> 3;
 378     s->size = nand_flash_ids[s->chip_id].size << 20;
 379     if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
 380         s->page_shift = 11;
 381         s->erase_shift = 6;
 382     } else {
 383         s->page_shift = nand_flash_ids[s->chip_id].page_shift;
 384         s->erase_shift = nand_flash_ids[s->chip_id].erase_shift;
 385     }
 386
 387     switch (1 << s->page_shift) {
 388     case 256:
 389         nand_init_256(s);
 390         break;
 391     case 512:
 392         nand_init_512(s);
 393         break;
 394     case 2048:
 395         nand_init_2048(s);
 396         break;
 397     default:
 398         error_setg(errp, "Unsupported NAND block size %#x",
 399                    1 << s->page_shift);
 400         return;
 401     }
 402
 403     pagesize = 1 << s->oob_shift;
 404     s->mem_oob = 1;
 405     if (s->blk) {
 406         if (blk_is_read_only(s->blk)) {
 407             error_setg(errp, "Can't use a read-only drive");
 408             return;
 409         }
 410         if (blk_getlength(s->blk) >=
 411                 (s->pages << s->page_shift) + (s->pages << s->oob_shift)) {
 412             pagesize = 0;
 413             s->mem_oob = 0;
 414         }
 415     } else {
 416         pagesize += 1 << s->page_shift;
 417     }
 418     if (pagesize) {
 419         s->storage = (uint8_t *) memset(g_malloc(s->pages * pagesize),
 420                         0xff, s->pages * pagesize);
 421     }
 422     /* Give s->ioaddr a sane value in case we save state before it is used. */
 423     s->ioaddr = s->io;
 424 }
 425
 426 static Property nand_properties[] = {
 427     DEFINE_PROP_UINT8("manufacturer_id", NANDFlashState, manf_id, 0),
 428     DEFINE_PROP_UINT8("chip_id", NANDFlashState, chip_id, 0),
 429     DEFINE_PROP_DRIVE("drive", NANDFlashState, blk),
 430     DEFINE_PROP_END_OF_LIST(),
 431 };
 432
 433 static void nand_class_init(ObjectClass *klass, void *data)
 434 {
 435     DeviceClass *dc = DEVICE_CLASS(klass);
 436
 437     dc->realize = nand_realize;
 438     dc->reset = nand_reset;
 439     dc->vmsd = &vmstate_nand;
 440     dc->props = nand_properties;
 441 }
 442
 443 static const TypeInfo nand_info = {
 444     .name          = TYPE_NAND,
 445     .parent        = TYPE_DEVICE,
 446     .instance_size = sizeof(NANDFlashState),
 447     .class_init    = nand_class_init,
 448 };
 449
 450 static void nand_register_types(void)
 451 {
 452     type_register_static(&nand_info);
 453 }
 454
 455 /*
 456  * Chip inputs are CLE, ALE, CE, WP, GND and eight I/O pins.  Chip
 457  * outputs are R/B and eight I/O pins.
 458  *
 459  * CE, WP and R/B are active low.
 460  */
 461 void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
 462                   uint8_t ce, uint8_t wp, uint8_t gnd)
 463 {
 464     NANDFlashState *s = NAND(dev);
 465
 466     s->cle = cle;
 467     s->ale = ale;
 468     s->ce = ce;
 469     s->wp = wp;
 470     s->gnd = gnd;
 471     if (wp) {
 472         s->status |= NAND_IOSTATUS_UNPROTCT;
 473     } else {
 474         s->status &= ~NAND_IOSTATUS_UNPROTCT;
 475     }
 476 }
 477
 478 void nand_getpins(DeviceState *dev, int *rb)
 479 {
 480     *rb = 1;
 481 }
 482
 483 void nand_setio(DeviceState *dev, uint32_t value)
 484 {
 485     int i;
 486     NANDFlashState *s = NAND(dev);
 487
 488     if (!s->ce && s->cle) {
 489         if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
 490             if (s->cmd == NAND_CMD_READ0 && value == NAND_CMD_LPREAD2)
 491                 return;
 492             if (value == NAND_CMD_RANDOMREAD1) {
 493                 s->addr &= ~((1 << s->addr_shift) - 1);
 494                 s->addrlen = 0;
 495                 return;
 496             }
 497         }
 498         if (value == NAND_CMD_READ0) {
 499             s->offset = 0;
 500         } else if (value == NAND_CMD_READ1) {
 501             s->offset = 0x100;
 502             value = NAND_CMD_READ0;
 503         } else if (value == NAND_CMD_READ2) {
 504             s->offset = 1 << s->page_shift;
 505             value = NAND_CMD_READ0;
 506         }
 507
 508         s->cmd = value;
 509
 510         if (s->cmd == NAND_CMD_READSTATUS ||
 511                 s->cmd == NAND_CMD_PAGEPROGRAM2 ||
 512                 s->cmd == NAND_CMD_BLOCKERASE1 ||
 513                 s->cmd == NAND_CMD_BLOCKERASE2 ||
 514                 s->cmd == NAND_CMD_NOSERIALREAD2 ||
 515                 s->cmd == NAND_CMD_RANDOMREAD2 ||
 516                 s->cmd == NAND_CMD_RESET) {
 517             nand_command(s);
 518         }
 519
 520         if (s->cmd != NAND_CMD_RANDOMREAD2) {
 521             s->addrlen = 0;
 522         }
 523     }
 524
 525     if (s->ale) {
 526         unsigned int shift = s->addrlen * 8;
 527         uint64_t mask = ~(0xffull << shift);
 528         uint64_t v = (uint64_t)value << shift;
 529
 530         s->addr = (s->addr & mask) | v;
 531         s->addrlen ++;
 532
 533         switch (s->addrlen) {
 534         case 1:
 535             if (s->cmd == NAND_CMD_READID) {
 536                 nand_command(s);
 537             }
 538             break;
 539         case 2: /* fix cache address as a byte address */
 540             s->addr <<= (s->buswidth - 1);
 541             break;
 542         case 3:
 543             if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
 544                     (s->cmd == NAND_CMD_READ0 ||
 545                      s->cmd == NAND_CMD_PAGEPROGRAM1)) {
 546                 nand_command(s);
 547             }
 548             break;
 549         case 4:
 550             if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
 551                     nand_flash_ids[s->chip_id].size < 256 && /* 1Gb or less */
 552                     (s->cmd == NAND_CMD_READ0 ||
 553                      s->cmd == NAND_CMD_PAGEPROGRAM1)) {
 554                 nand_command(s);
 555             }
 556             break;
 557         case 5:
 558             if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
 559                     nand_flash_ids[s->chip_id].size >= 256 && /* 2Gb or more */
 560                     (s->cmd == NAND_CMD_READ0 ||
 561                      s->cmd == NAND_CMD_PAGEPROGRAM1)) {
 562                 nand_command(s);
 563             }
 564             break;
 565         default:
 566             break;
 567         }
 568     }
 569
 570     if (!s->cle && !s->ale && s->cmd == NAND_CMD_PAGEPROGRAM1) {
 571         if (s->iolen < (1 << s->page_shift) + (1 << s->oob_shift)) {
 572             for (i = s->buswidth; i--; value >>= 8) {
 573                 s->io[s->iolen ++] = (uint8_t) (value & 0xff);
 574             }
 575         }
 576     } else if (!s->cle && !s->ale && s->cmd == NAND_CMD_COPYBACKPRG1) {
 577         if ((s->addr & ((1 << s->addr_shift) - 1)) <
 578                 (1 << s->page_shift) + (1 << s->oob_shift)) {
 579             for (i = s->buswidth; i--; s->addr++, value >>= 8) {
 580                 s->io[s->iolen + (s->addr & ((1 << s->addr_shift) - 1))] =
 581                     (uint8_t) (value & 0xff);
 582             }
 583         }
 584     }
 585 }
 586
 587 uint32_t nand_getio(DeviceState *dev)
 588 {
 589     int offset;
 590     uint32_t x = 0;
 591     NANDFlashState *s = NAND(dev);
 592
 593     /* Allow sequential reading */
 594     if (!s->iolen && s->cmd == NAND_CMD_READ0) {
 595         offset = (int) (s->addr & ((1 << s->addr_shift) - 1)) + s->offset;
 596         s->offset = 0;
 597
 598         s->blk_load(s, s->addr, offset);
 599         if (s->gnd)
 600             s->iolen = (1 << s->page_shift) - offset;
 601         else
 602             s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
 603     }
 604
 605     if (s->ce || s->iolen <= 0) {
 606         return 0;
 607     }
 608
 609     for (offset = s->buswidth; offset--;) {
 610         x |= s->ioaddr[offset] << (offset << 3);
 611     }
 612     /* after receiving READ STATUS command all subsequent reads will
 613      * return the status register value until another command is issued
 614      */
 615     if (s->cmd != NAND_CMD_READSTATUS) {
 616         s->addr   += s->buswidth;
 617         s->ioaddr += s->buswidth;
 618         s->iolen  -= s->buswidth;
 619     }
 620     return x;
 621 }
 622
 623 uint32_t nand_getbuswidth(DeviceState *dev)
 624 {
 625     NANDFlashState *s = (NANDFlashState *) dev;
 626     return s->buswidth << 3;
 627 }
 628
 629 DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id)
 630 {
 631     DeviceState *dev;
 632
 633     if (nand_flash_ids[chip_id].size == 0) {
 634         hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__);
 635     }
 636     dev = DEVICE(object_new(TYPE_NAND));
 637     qdev_prop_set_uint8(dev, "manufacturer_id", manf_id);
 638     qdev_prop_set_uint8(dev, "chip_id", chip_id);
 639     if (blk) {
 640         qdev_prop_set_drive(dev, "drive", blk, &error_fatal);
 641     }
 642
 643     qdev_init_nofail(dev);
 644     return dev;
 645 }
 646
 647 type_init(nand_register_types)
 648
 649 #else
 650
 651 /* Program a single page */
 652 static void glue(nand_blk_write_, PAGE_SIZE)(NANDFlashState *s)
 653 {
 654     uint64_t off, page, sector, soff;
 655     uint8_t iobuf[(PAGE_SECTORS + 2) * 0x200];
 656     if (PAGE(s->addr) >= s->pages)
 657         return;
 658
 659     if (!s->blk) {
 660         mem_and(s->storage + PAGE_START(s->addr) + (s->addr & PAGE_MASK) +
 661                         s->offset, s->io, s->iolen);
 662     } else if (s->mem_oob) {
 663         sector = SECTOR(s->addr);
 664         off = (s->addr & PAGE_MASK) + s->offset;
 665         soff = SECTOR_OFFSET(s->addr);
 666         if (blk_pread(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
 667                       PAGE_SECTORS << BDRV_SECTOR_BITS) < 0) {
 668             printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
 669             return;
 670         }
 671
 672         mem_and(iobuf + (soff | off), s->io, MIN(s->iolen, PAGE_SIZE - off));
 673         if (off + s->iolen > PAGE_SIZE) {
 674             page = PAGE(s->addr);
 675             mem_and(s->storage + (page << OOB_SHIFT), s->io + PAGE_SIZE - off,
 676                             MIN(OOB_SIZE, off + s->iolen - PAGE_SIZE));
 677         }
 678
 679         if (blk_pwrite(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
 680                        PAGE_SECTORS << BDRV_SECTOR_BITS, 0) < 0) {
 681             printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
 682         }
 683     } else {
 684         off = PAGE_START(s->addr) + (s->addr & PAGE_MASK) + s->offset;
 685         sector = off >> 9;
 686         soff = off & 0x1ff;
 687         if (blk_pread(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
 688                       (PAGE_SECTORS + 2) << BDRV_SECTOR_BITS) < 0) {
 689             printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
 690             return;
 691         }
 692
 693         mem_and(iobuf + soff, s->io, s->iolen);
 694
 695         if (blk_pwrite(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
 696                        (PAGE_SECTORS + 2) << BDRV_SECTOR_BITS, 0) < 0) {
 697             printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
 698         }
 699     }
 700     s->offset = 0;
 701 }
 702
 703 /* Erase a single block */
 704 static void glue(nand_blk_erase_, PAGE_SIZE)(NANDFlashState *s)
 705 {
 706     uint64_t i, page, addr;
 707     uint8_t iobuf[0x200] = { [0 ... 0x1ff] = 0xff, };
 708     addr = s->addr & ~((1 << (ADDR_SHIFT + s->erase_shift)) - 1);
 709
 710     if (PAGE(addr) >= s->pages) {
 711         return;
 712     }
 713
 714     if (!s->blk) {
 715         memset(s->storage + PAGE_START(addr),
 716                         0xff, (PAGE_SIZE + OOB_SIZE) << s->erase_shift);
 717     } else if (s->mem_oob) {
 718         memset(s->storage + (PAGE(addr) << OOB_SHIFT),
 719                         0xff, OOB_SIZE << s->erase_shift);
 720         i = SECTOR(addr);
 721         page = SECTOR(addr + (1 << (ADDR_SHIFT + s->erase_shift)));
 722         for (; i < page; i ++)
 723             if (blk_pwrite(s->blk, i << BDRV_SECTOR_BITS, iobuf,
 724                            BDRV_SECTOR_SIZE, 0) < 0) {
 725                 printf("%s: write error in sector %" PRIu64 "\n", __func__, i);
 726             }
 727     } else {
 728         addr = PAGE_START(addr);
 729         page = addr >> 9;
 730         if (blk_pread(s->blk, page << BDRV_SECTOR_BITS, iobuf,
 731                       BDRV_SECTOR_SIZE) < 0) {
 732             printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
 733         }
 734         memset(iobuf + (addr & 0x1ff), 0xff, (~addr & 0x1ff) + 1);
 735         if (blk_pwrite(s->blk, page << BDRV_SECTOR_BITS, iobuf,
 736                        BDRV_SECTOR_SIZE, 0) < 0) {
 737             printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
 738         }
 739
 740         memset(iobuf, 0xff, 0x200);
 741         i = (addr & ~0x1ff) + 0x200;
 742         for (addr += ((PAGE_SIZE + OOB_SIZE) << s->erase_shift) - 0x200;
 743                         i < addr; i += 0x200) {
 744             if (blk_pwrite(s->blk, i, iobuf, BDRV_SECTOR_SIZE, 0) < 0) {
 745                 printf("%s: write error in sector %" PRIu64 "\n",
 746                        __func__, i >> 9);
 747             }
 748         }
 749
 750         page = i >> 9;
 751         if (blk_pread(s->blk, page << BDRV_SECTOR_BITS, iobuf,
 752                       BDRV_SECTOR_SIZE) < 0) {
 753             printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
 754         }
 755         memset(iobuf, 0xff, ((addr - 1) & 0x1ff) + 1);
 756         if (blk_pwrite(s->blk, page << BDRV_SECTOR_BITS, iobuf,
 757                        BDRV_SECTOR_SIZE, 0) < 0) {
 758             printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
 759         }
 760     }
 761 }
 762
 763 static void glue(nand_blk_load_, PAGE_SIZE)(NANDFlashState *s,
 764                 uint64_t addr, int offset)
 765 {
 766     if (PAGE(addr) >= s->pages) {
 767         return;
 768     }
 769
 770     if (s->blk) {
 771         if (s->mem_oob) {
 772             if (blk_pread(s->blk, SECTOR(addr) << BDRV_SECTOR_BITS, s->io,
 773                           PAGE_SECTORS << BDRV_SECTOR_BITS) < 0) {
 774                 printf("%s: read error in sector %" PRIu64 "\n",
 775                                 __func__, SECTOR(addr));
 776             }
 777             memcpy(s->io + SECTOR_OFFSET(s->addr) + PAGE_SIZE,
 778                             s->storage + (PAGE(s->addr) << OOB_SHIFT),
 779                             OOB_SIZE);
 780             s->ioaddr = s->io + SECTOR_OFFSET(s->addr) + offset;
 781         } else {
 782             if (blk_pread(s->blk, PAGE_START(addr), s->io,
 783                           (PAGE_SECTORS + 2) << BDRV_SECTOR_BITS) < 0) {
 784                 printf("%s: read error in sector %" PRIu64 "\n",
 785                                 __func__, PAGE_START(addr) >> 9);
 786             }
 787             s->ioaddr = s->io + (PAGE_START(addr) & 0x1ff) + offset;
 788         }
 789     } else {
 790         memcpy(s->io, s->storage + PAGE_START(s->addr) +
 791                         offset, PAGE_SIZE + OOB_SIZE - offset);
 792         s->ioaddr = s->io;
 793     }
 794 }
 795
 796 static void glue(nand_init_, PAGE_SIZE)(NANDFlashState *s)
 797 {
 798     s->oob_shift = PAGE_SHIFT - 5;
 799     s->pages = s->size >> PAGE_SHIFT;
 800     s->addr_shift = ADDR_SHIFT;
 801
 802     s->blk_erase = glue(nand_blk_erase_, PAGE_SIZE);
 803     s->blk_write = glue(nand_blk_write_, PAGE_SIZE);
 804     s->blk_load = glue(nand_blk_load_, PAGE_SIZE);
 805 }
 806
 807 # undef PAGE_SIZE
 808 # undef PAGE_SHIFT
 809 # undef PAGE_SECTORS
 810 # undef ADDR_SHIFT
 811 #endif  /* NAND_IO */