?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
hw/core/loader: Add new function rom_ptr_for_as()
[qemu/ar7.git] / target / mips / translate.c
blobc518bf3963b67c2bd38a25dd17a3ee2d73567bda
1 /*
2 * MIPS emulation for QEMU - main translation routines
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
9 * Copyright (c) 2020 Philippe Mathieu-Daudé
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2.1 of the License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "qemu/osdep.h"
26 #include "cpu.h"
27 #include "internal.h"
28 #include "tcg/tcg-op.h"
29 #include "exec/translator.h"
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32 #include "semihosting/semihost.h"
33
34 #include "target/mips/trace.h"
35 #include "trace-tcg.h"
36 #include "exec/translator.h"
37 #include "exec/log.h"
38 #include "qemu/qemu-print.h"
39 #include "fpu_helper.h"
40 #include "translate.h"
41
42 enum {
43 /* indirect opcode tables */
44 OPC_SPECIAL = (0x00 << 26),
45 OPC_REGIMM = (0x01 << 26),
46 OPC_CP0 = (0x10 << 26),
47 OPC_CP2 = (0x12 << 26),
48 OPC_CP3 = (0x13 << 26),
49 OPC_SPECIAL2 = (0x1C << 26),
50 OPC_SPECIAL3 = (0x1F << 26),
51 /* arithmetic with immediate */
52 OPC_ADDI = (0x08 << 26),
53 OPC_ADDIU = (0x09 << 26),
54 OPC_SLTI = (0x0A << 26),
55 OPC_SLTIU = (0x0B << 26),
56 /* logic with immediate */
57 OPC_ANDI = (0x0C << 26),
58 OPC_ORI = (0x0D << 26),
59 OPC_XORI = (0x0E << 26),
60 OPC_LUI = (0x0F << 26),
61 /* arithmetic with immediate */
62 OPC_DADDI = (0x18 << 26),
63 OPC_DADDIU = (0x19 << 26),
64 /* Jump and branches */
65 OPC_J = (0x02 << 26),
66 OPC_JAL = (0x03 << 26),
67 OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
68 OPC_BEQL = (0x14 << 26),
69 OPC_BNE = (0x05 << 26),
70 OPC_BNEL = (0x15 << 26),
71 OPC_BLEZ = (0x06 << 26),
72 OPC_BLEZL = (0x16 << 26),
73 OPC_BGTZ = (0x07 << 26),
74 OPC_BGTZL = (0x17 << 26),
75 OPC_JALX = (0x1D << 26),
76 OPC_DAUI = (0x1D << 26),
77 /* Load and stores */
78 OPC_LDL = (0x1A << 26),
79 OPC_LDR = (0x1B << 26),
80 OPC_LB = (0x20 << 26),
81 OPC_LH = (0x21 << 26),
82 OPC_LWL = (0x22 << 26),
83 OPC_LW = (0x23 << 26),
84 OPC_LWPC = OPC_LW | 0x5,
85 OPC_LBU = (0x24 << 26),
86 OPC_LHU = (0x25 << 26),
87 OPC_LWR = (0x26 << 26),
88 OPC_LWU = (0x27 << 26),
89 OPC_SB = (0x28 << 26),
90 OPC_SH = (0x29 << 26),
91 OPC_SWL = (0x2A << 26),
92 OPC_SW = (0x2B << 26),
93 OPC_SDL = (0x2C << 26),
94 OPC_SDR = (0x2D << 26),
95 OPC_SWR = (0x2E << 26),
96 OPC_LL = (0x30 << 26),
97 OPC_LLD = (0x34 << 26),
98 OPC_LD = (0x37 << 26),
99 OPC_LDPC = OPC_LD | 0x5,
100 OPC_SC = (0x38 << 26),
101 OPC_SCD = (0x3C << 26),
102 OPC_SD = (0x3F << 26),
103 /* Floating point load/store */
104 OPC_LWC1 = (0x31 << 26),
105 OPC_LWC2 = (0x32 << 26),
106 OPC_LDC1 = (0x35 << 26),
107 OPC_LDC2 = (0x36 << 26),
108 OPC_SWC1 = (0x39 << 26),
109 OPC_SWC2 = (0x3A << 26),
110 OPC_SDC1 = (0x3D << 26),
111 OPC_SDC2 = (0x3E << 26),
112 /* Compact Branches */
113 OPC_BLEZALC = (0x06 << 26),
114 OPC_BGEZALC = (0x06 << 26),
115 OPC_BGEUC = (0x06 << 26),
116 OPC_BGTZALC = (0x07 << 26),
117 OPC_BLTZALC = (0x07 << 26),
118 OPC_BLTUC = (0x07 << 26),
119 OPC_BOVC = (0x08 << 26),
120 OPC_BEQZALC = (0x08 << 26),
121 OPC_BEQC = (0x08 << 26),
122 OPC_BLEZC = (0x16 << 26),
123 OPC_BGEZC = (0x16 << 26),
124 OPC_BGEC = (0x16 << 26),
125 OPC_BGTZC = (0x17 << 26),
126 OPC_BLTZC = (0x17 << 26),
127 OPC_BLTC = (0x17 << 26),
128 OPC_BNVC = (0x18 << 26),
129 OPC_BNEZALC = (0x18 << 26),
130 OPC_BNEC = (0x18 << 26),
131 OPC_BC = (0x32 << 26),
132 OPC_BEQZC = (0x36 << 26),
133 OPC_JIC = (0x36 << 26),
134 OPC_BALC = (0x3A << 26),
135 OPC_BNEZC = (0x3E << 26),
136 OPC_JIALC = (0x3E << 26),
137 /* MDMX ASE specific */
138 OPC_MDMX = (0x1E << 26),
139 /* Cache and prefetch */
140 OPC_CACHE = (0x2F << 26),
141 OPC_PREF = (0x33 << 26),
142 /* PC-relative address computation / loads */
143 OPC_PCREL = (0x3B << 26),
144 };
145
146 /* PC-relative address computation / loads */
147 #define MASK_OPC_PCREL_TOP2BITS(op) (MASK_OP_MAJOR(op) | (op & (3 << 19)))
148 #define MASK_OPC_PCREL_TOP5BITS(op) (MASK_OP_MAJOR(op) | (op & (0x1f << 16)))
149 enum {
150 /* Instructions determined by bits 19 and 20 */
151 OPC_ADDIUPC = OPC_PCREL | (0 << 19),
152 R6_OPC_LWPC = OPC_PCREL | (1 << 19),
153 OPC_LWUPC = OPC_PCREL | (2 << 19),
154
155 /* Instructions determined by bits 16 ... 20 */
156 OPC_AUIPC = OPC_PCREL | (0x1e << 16),
157 OPC_ALUIPC = OPC_PCREL | (0x1f << 16),
158
159 /* Other */
160 R6_OPC_LDPC = OPC_PCREL | (6 << 18),
161 };
162
163 /* MIPS special opcodes */
164 #define MASK_SPECIAL(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
165
166 enum {
167 /* Shifts */
168 OPC_SLL = 0x00 | OPC_SPECIAL,
169 /* NOP is SLL r0, r0, 0 */
170 /* SSNOP is SLL r0, r0, 1 */
171 /* EHB is SLL r0, r0, 3 */
172 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */
173 OPC_ROTR = OPC_SRL | (1 << 21),
174 OPC_SRA = 0x03 | OPC_SPECIAL,
175 OPC_SLLV = 0x04 | OPC_SPECIAL,
176 OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */
177 OPC_ROTRV = OPC_SRLV | (1 << 6),
178 OPC_SRAV = 0x07 | OPC_SPECIAL,
179 OPC_DSLLV = 0x14 | OPC_SPECIAL,
180 OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */
181 OPC_DROTRV = OPC_DSRLV | (1 << 6),
182 OPC_DSRAV = 0x17 | OPC_SPECIAL,
183 OPC_DSLL = 0x38 | OPC_SPECIAL,
184 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */
185 OPC_DROTR = OPC_DSRL | (1 << 21),
186 OPC_DSRA = 0x3B | OPC_SPECIAL,
187 OPC_DSLL32 = 0x3C | OPC_SPECIAL,
188 OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */
189 OPC_DROTR32 = OPC_DSRL32 | (1 << 21),
190 OPC_DSRA32 = 0x3F | OPC_SPECIAL,
191 /* Multiplication / division */
192 OPC_MULT = 0x18 | OPC_SPECIAL,
193 OPC_MULTU = 0x19 | OPC_SPECIAL,
194 OPC_DIV = 0x1A | OPC_SPECIAL,
195 OPC_DIVU = 0x1B | OPC_SPECIAL,
196 OPC_DMULT = 0x1C | OPC_SPECIAL,
197 OPC_DMULTU = 0x1D | OPC_SPECIAL,
198 OPC_DDIV = 0x1E | OPC_SPECIAL,
199 OPC_DDIVU = 0x1F | OPC_SPECIAL,
200
201 /* 2 registers arithmetic / logic */
202 OPC_ADD = 0x20 | OPC_SPECIAL,
203 OPC_ADDU = 0x21 | OPC_SPECIAL,
204 OPC_SUB = 0x22 | OPC_SPECIAL,
205 OPC_SUBU = 0x23 | OPC_SPECIAL,
206 OPC_AND = 0x24 | OPC_SPECIAL,
207 OPC_OR = 0x25 | OPC_SPECIAL,
208 OPC_XOR = 0x26 | OPC_SPECIAL,
209 OPC_NOR = 0x27 | OPC_SPECIAL,
210 OPC_SLT = 0x2A | OPC_SPECIAL,
211 OPC_SLTU = 0x2B | OPC_SPECIAL,
212 OPC_DADD = 0x2C | OPC_SPECIAL,
213 OPC_DADDU = 0x2D | OPC_SPECIAL,
214 OPC_DSUB = 0x2E | OPC_SPECIAL,
215 OPC_DSUBU = 0x2F | OPC_SPECIAL,
216 /* Jumps */
217 OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */
218 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */
219 /* Traps */
220 OPC_TGE = 0x30 | OPC_SPECIAL,
221 OPC_TGEU = 0x31 | OPC_SPECIAL,
222 OPC_TLT = 0x32 | OPC_SPECIAL,
223 OPC_TLTU = 0x33 | OPC_SPECIAL,
224 OPC_TEQ = 0x34 | OPC_SPECIAL,
225 OPC_TNE = 0x36 | OPC_SPECIAL,
226 /* HI / LO registers load & stores */
227 OPC_MFHI = 0x10 | OPC_SPECIAL,
228 OPC_MTHI = 0x11 | OPC_SPECIAL,
229 OPC_MFLO = 0x12 | OPC_SPECIAL,
230 OPC_MTLO = 0x13 | OPC_SPECIAL,
231 /* Conditional moves */
232 OPC_MOVZ = 0x0A | OPC_SPECIAL,
233 OPC_MOVN = 0x0B | OPC_SPECIAL,
234
235 OPC_SELEQZ = 0x35 | OPC_SPECIAL,
236 OPC_SELNEZ = 0x37 | OPC_SPECIAL,
237
238 OPC_MOVCI = 0x01 | OPC_SPECIAL,
239
240 /* Special */
241 OPC_PMON = 0x05 | OPC_SPECIAL, /* unofficial */
242 OPC_SYSCALL = 0x0C | OPC_SPECIAL,
243 OPC_BREAK = 0x0D | OPC_SPECIAL,
244 OPC_SPIM = 0x0E | OPC_SPECIAL, /* unofficial */
245 OPC_SYNC = 0x0F | OPC_SPECIAL,
246
247 OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,
248 OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,
249 OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,
250 OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
251 };
252
253 /*
254 * R6 Multiply and Divide instructions have the same opcode
255 * and function field as legacy OPC_MULT[U]/OPC_DIV[U]
256 */
257 #define MASK_R6_MULDIV(op) (MASK_SPECIAL(op) | (op & (0x7ff)))
258
259 enum {
260 R6_OPC_MUL = OPC_MULT | (2 << 6),
261 R6_OPC_MUH = OPC_MULT | (3 << 6),
262 R6_OPC_MULU = OPC_MULTU | (2 << 6),
263 R6_OPC_MUHU = OPC_MULTU | (3 << 6),
264 R6_OPC_DIV = OPC_DIV | (2 << 6),
265 R6_OPC_MOD = OPC_DIV | (3 << 6),
266 R6_OPC_DIVU = OPC_DIVU | (2 << 6),
267 R6_OPC_MODU = OPC_DIVU | (3 << 6),
268
269 R6_OPC_DMUL = OPC_DMULT | (2 << 6),
270 R6_OPC_DMUH = OPC_DMULT | (3 << 6),
271 R6_OPC_DMULU = OPC_DMULTU | (2 << 6),
272 R6_OPC_DMUHU = OPC_DMULTU | (3 << 6),
273 R6_OPC_DDIV = OPC_DDIV | (2 << 6),
274 R6_OPC_DMOD = OPC_DDIV | (3 << 6),
275 R6_OPC_DDIVU = OPC_DDIVU | (2 << 6),
276 R6_OPC_DMODU = OPC_DDIVU | (3 << 6),
277
278 R6_OPC_CLZ = 0x10 | OPC_SPECIAL,
279 R6_OPC_CLO = 0x11 | OPC_SPECIAL,
280 R6_OPC_DCLZ = 0x12 | OPC_SPECIAL,
281 R6_OPC_DCLO = 0x13 | OPC_SPECIAL,
282 R6_OPC_SDBBP = 0x0e | OPC_SPECIAL,
283 };
284
285 /* Multiplication variants of the vr54xx. */
286 #define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6)))
287
288 enum {
289 OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
290 OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
291 OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT,
292 OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU,
293 OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
294 OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
295 OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
296 OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
297 OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
298 OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
299 OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT,
300 OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
301 OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
302 OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
303 };
304
305 /* REGIMM (rt field) opcodes */
306 #define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16)))
307
308 enum {
309 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM,
310 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM,
311 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM,
312 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM,
313 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM,
314 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM,
315 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM,
316 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM,
317 OPC_TGEI = (0x08 << 16) | OPC_REGIMM,
318 OPC_TGEIU = (0x09 << 16) | OPC_REGIMM,
319 OPC_TLTI = (0x0A << 16) | OPC_REGIMM,
320 OPC_TLTIU = (0x0B << 16) | OPC_REGIMM,
321 OPC_TEQI = (0x0C << 16) | OPC_REGIMM,
322 OPC_TNEI = (0x0E << 16) | OPC_REGIMM,
323 OPC_SIGRIE = (0x17 << 16) | OPC_REGIMM,
324 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM,
325
326 OPC_DAHI = (0x06 << 16) | OPC_REGIMM,
327 OPC_DATI = (0x1e << 16) | OPC_REGIMM,
328 };
329
330 /* Special2 opcodes */
331 #define MASK_SPECIAL2(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
332
333 enum {
334 /* Multiply & xxx operations */
335 OPC_MADD = 0x00 | OPC_SPECIAL2,
336 OPC_MADDU = 0x01 | OPC_SPECIAL2,
337 OPC_MUL = 0x02 | OPC_SPECIAL2,
338 OPC_MSUB = 0x04 | OPC_SPECIAL2,
339 OPC_MSUBU = 0x05 | OPC_SPECIAL2,
340 /* Loongson 2F */
341 OPC_MULT_G_2F = 0x10 | OPC_SPECIAL2,
342 OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
343 OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
344 OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
345 OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2,
346 OPC_DDIV_G_2F = 0x15 | OPC_SPECIAL2,
347 OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2,
348 OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2,
349 OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
350 OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2,
351 OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2,
352 OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2,
353 /* Misc */
354 OPC_CLZ = 0x20 | OPC_SPECIAL2,
355 OPC_CLO = 0x21 | OPC_SPECIAL2,
356 OPC_DCLZ = 0x24 | OPC_SPECIAL2,
357 OPC_DCLO = 0x25 | OPC_SPECIAL2,
358 /* Special */
359 OPC_SDBBP = 0x3F | OPC_SPECIAL2,
360 };
361
362 /* Special3 opcodes */
363 #define MASK_SPECIAL3(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
364
365 enum {
366 OPC_EXT = 0x00 | OPC_SPECIAL3,
367 OPC_DEXTM = 0x01 | OPC_SPECIAL3,
368 OPC_DEXTU = 0x02 | OPC_SPECIAL3,
369 OPC_DEXT = 0x03 | OPC_SPECIAL3,
370 OPC_INS = 0x04 | OPC_SPECIAL3,
371 OPC_DINSM = 0x05 | OPC_SPECIAL3,
372 OPC_DINSU = 0x06 | OPC_SPECIAL3,
373 OPC_DINS = 0x07 | OPC_SPECIAL3,
374 OPC_FORK = 0x08 | OPC_SPECIAL3,
375 OPC_YIELD = 0x09 | OPC_SPECIAL3,
376 OPC_BSHFL = 0x20 | OPC_SPECIAL3,
377 OPC_DBSHFL = 0x24 | OPC_SPECIAL3,
378 OPC_RDHWR = 0x3B | OPC_SPECIAL3,
379 OPC_GINV = 0x3D | OPC_SPECIAL3,
380
381 /* Loongson 2E */
382 OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3,
383 OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
384 OPC_DIV_G_2E = 0x1A | OPC_SPECIAL3,
385 OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3,
386 OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
387 OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
388 OPC_DDIV_G_2E = 0x1E | OPC_SPECIAL3,
389 OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3,
390 OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3,
391 OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
392 OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3,
393 OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3,
394
395 /* MIPS DSP Load */
396 OPC_LX_DSP = 0x0A | OPC_SPECIAL3,
397 /* MIPS DSP Arithmetic */
398 OPC_ADDU_QB_DSP = 0x10 | OPC_SPECIAL3,
399 OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3,
400 OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3,
401 OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3,
402 /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */
403 /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */
404 OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3,
405 OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3,
406 /* MIPS DSP GPR-Based Shift Sub-class */
407 OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3,
408 OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3,
409 /* MIPS DSP Multiply Sub-class insns */
410 /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */
411 /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */
412 OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3,
413 OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3,
414 /* DSP Bit/Manipulation Sub-class */
415 OPC_INSV_DSP = 0x0C | OPC_SPECIAL3,
416 OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3,
417 /* MIPS DSP Append Sub-class */
418 OPC_APPEND_DSP = 0x31 | OPC_SPECIAL3,
419 OPC_DAPPEND_DSP = 0x35 | OPC_SPECIAL3,
420 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
421 OPC_EXTR_W_DSP = 0x38 | OPC_SPECIAL3,
422 OPC_DEXTR_W_DSP = 0x3C | OPC_SPECIAL3,
423
424 /* EVA */
425 OPC_LWLE = 0x19 | OPC_SPECIAL3,
426 OPC_LWRE = 0x1A | OPC_SPECIAL3,
427 OPC_CACHEE = 0x1B | OPC_SPECIAL3,
428 OPC_SBE = 0x1C | OPC_SPECIAL3,
429 OPC_SHE = 0x1D | OPC_SPECIAL3,
430 OPC_SCE = 0x1E | OPC_SPECIAL3,
431 OPC_SWE = 0x1F | OPC_SPECIAL3,
432 OPC_SWLE = 0x21 | OPC_SPECIAL3,
433 OPC_SWRE = 0x22 | OPC_SPECIAL3,
434 OPC_PREFE = 0x23 | OPC_SPECIAL3,
435 OPC_LBUE = 0x28 | OPC_SPECIAL3,
436 OPC_LHUE = 0x29 | OPC_SPECIAL3,
437 OPC_LBE = 0x2C | OPC_SPECIAL3,
438 OPC_LHE = 0x2D | OPC_SPECIAL3,
439 OPC_LLE = 0x2E | OPC_SPECIAL3,
440 OPC_LWE = 0x2F | OPC_SPECIAL3,
441
442 /* R6 */
443 R6_OPC_PREF = 0x35 | OPC_SPECIAL3,
444 R6_OPC_CACHE = 0x25 | OPC_SPECIAL3,
445 R6_OPC_LL = 0x36 | OPC_SPECIAL3,
446 R6_OPC_SC = 0x26 | OPC_SPECIAL3,
447 R6_OPC_LLD = 0x37 | OPC_SPECIAL3,
448 R6_OPC_SCD = 0x27 | OPC_SPECIAL3,
449 };
450
451 /* Loongson EXT load/store quad word opcodes */
452 #define MASK_LOONGSON_GSLSQ(op) (MASK_OP_MAJOR(op) | (op & 0x8020))
453 enum {
454 OPC_GSLQ = 0x0020 | OPC_LWC2,
455 OPC_GSLQC1 = 0x8020 | OPC_LWC2,
456 OPC_GSSHFL = OPC_LWC2,
457 OPC_GSSQ = 0x0020 | OPC_SWC2,
458 OPC_GSSQC1 = 0x8020 | OPC_SWC2,
459 OPC_GSSHFS = OPC_SWC2,
460 };
461
462 /* Loongson EXT shifted load/store opcodes */
463 #define MASK_LOONGSON_GSSHFLS(op) (MASK_OP_MAJOR(op) | (op & 0xc03f))
464 enum {
465 OPC_GSLWLC1 = 0x4 | OPC_GSSHFL,
466 OPC_GSLWRC1 = 0x5 | OPC_GSSHFL,
467 OPC_GSLDLC1 = 0x6 | OPC_GSSHFL,
468 OPC_GSLDRC1 = 0x7 | OPC_GSSHFL,
469 OPC_GSSWLC1 = 0x4 | OPC_GSSHFS,
470 OPC_GSSWRC1 = 0x5 | OPC_GSSHFS,
471 OPC_GSSDLC1 = 0x6 | OPC_GSSHFS,
472 OPC_GSSDRC1 = 0x7 | OPC_GSSHFS,
473 };
474
475 /* Loongson EXT LDC2/SDC2 opcodes */
476 #define MASK_LOONGSON_LSDC2(op) (MASK_OP_MAJOR(op) | (op & 0x7))
477
478 enum {
479 OPC_GSLBX = 0x0 | OPC_LDC2,
480 OPC_GSLHX = 0x1 | OPC_LDC2,
481 OPC_GSLWX = 0x2 | OPC_LDC2,
482 OPC_GSLDX = 0x3 | OPC_LDC2,
483 OPC_GSLWXC1 = 0x6 | OPC_LDC2,
484 OPC_GSLDXC1 = 0x7 | OPC_LDC2,
485 OPC_GSSBX = 0x0 | OPC_SDC2,
486 OPC_GSSHX = 0x1 | OPC_SDC2,
487 OPC_GSSWX = 0x2 | OPC_SDC2,
488 OPC_GSSDX = 0x3 | OPC_SDC2,
489 OPC_GSSWXC1 = 0x6 | OPC_SDC2,
490 OPC_GSSDXC1 = 0x7 | OPC_SDC2,
491 };
492
493 /* BSHFL opcodes */
494 #define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
495
496 enum {
497 OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
498 OPC_SEB = (0x10 << 6) | OPC_BSHFL,
499 OPC_SEH = (0x18 << 6) | OPC_BSHFL,
500 OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp (010.00 to 010.11) */
501 OPC_ALIGN_1 = (0x09 << 6) | OPC_BSHFL,
502 OPC_ALIGN_2 = (0x0A << 6) | OPC_BSHFL,
503 OPC_ALIGN_3 = (0x0B << 6) | OPC_BSHFL,
504 OPC_BITSWAP = (0x00 << 6) | OPC_BSHFL /* 00000 */
505 };
506
507 /* DBSHFL opcodes */
508 #define MASK_DBSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
509
510 enum {
511 OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
512 OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
513 OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp (01.000 to 01.111) */
514 OPC_DALIGN_1 = (0x09 << 6) | OPC_DBSHFL,
515 OPC_DALIGN_2 = (0x0A << 6) | OPC_DBSHFL,
516 OPC_DALIGN_3 = (0x0B << 6) | OPC_DBSHFL,
517 OPC_DALIGN_4 = (0x0C << 6) | OPC_DBSHFL,
518 OPC_DALIGN_5 = (0x0D << 6) | OPC_DBSHFL,
519 OPC_DALIGN_6 = (0x0E << 6) | OPC_DBSHFL,
520 OPC_DALIGN_7 = (0x0F << 6) | OPC_DBSHFL,
521 OPC_DBITSWAP = (0x00 << 6) | OPC_DBSHFL, /* 00000 */
522 };
523
524 /* MIPS DSP REGIMM opcodes */
525 enum {
526 OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM,
527 OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM,
528 };
529
530 #define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
531 /* MIPS DSP Load */
532 enum {
533 OPC_LBUX = (0x06 << 6) | OPC_LX_DSP,
534 OPC_LHX = (0x04 << 6) | OPC_LX_DSP,
535 OPC_LWX = (0x00 << 6) | OPC_LX_DSP,
536 OPC_LDX = (0x08 << 6) | OPC_LX_DSP,
537 };
538
539 #define MASK_ADDU_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
540 enum {
541 /* MIPS DSP Arithmetic Sub-class */
542 OPC_ADDQ_PH = (0x0A << 6) | OPC_ADDU_QB_DSP,
543 OPC_ADDQ_S_PH = (0x0E << 6) | OPC_ADDU_QB_DSP,
544 OPC_ADDQ_S_W = (0x16 << 6) | OPC_ADDU_QB_DSP,
545 OPC_ADDU_QB = (0x00 << 6) | OPC_ADDU_QB_DSP,
546 OPC_ADDU_S_QB = (0x04 << 6) | OPC_ADDU_QB_DSP,
547 OPC_ADDU_PH = (0x08 << 6) | OPC_ADDU_QB_DSP,
548 OPC_ADDU_S_PH = (0x0C << 6) | OPC_ADDU_QB_DSP,
549 OPC_SUBQ_PH = (0x0B << 6) | OPC_ADDU_QB_DSP,
550 OPC_SUBQ_S_PH = (0x0F << 6) | OPC_ADDU_QB_DSP,
551 OPC_SUBQ_S_W = (0x17 << 6) | OPC_ADDU_QB_DSP,
552 OPC_SUBU_QB = (0x01 << 6) | OPC_ADDU_QB_DSP,
553 OPC_SUBU_S_QB = (0x05 << 6) | OPC_ADDU_QB_DSP,
554 OPC_SUBU_PH = (0x09 << 6) | OPC_ADDU_QB_DSP,
555 OPC_SUBU_S_PH = (0x0D << 6) | OPC_ADDU_QB_DSP,
556 OPC_ADDSC = (0x10 << 6) | OPC_ADDU_QB_DSP,
557 OPC_ADDWC = (0x11 << 6) | OPC_ADDU_QB_DSP,
558 OPC_MODSUB = (0x12 << 6) | OPC_ADDU_QB_DSP,
559 OPC_RADDU_W_QB = (0x14 << 6) | OPC_ADDU_QB_DSP,
560 /* MIPS DSP Multiply Sub-class insns */
561 OPC_MULEU_S_PH_QBL = (0x06 << 6) | OPC_ADDU_QB_DSP,
562 OPC_MULEU_S_PH_QBR = (0x07 << 6) | OPC_ADDU_QB_DSP,
563 OPC_MULQ_RS_PH = (0x1F << 6) | OPC_ADDU_QB_DSP,
564 OPC_MULEQ_S_W_PHL = (0x1C << 6) | OPC_ADDU_QB_DSP,
565 OPC_MULEQ_S_W_PHR = (0x1D << 6) | OPC_ADDU_QB_DSP,
566 OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP,
567 };
568
569 #define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
570 #define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
571 enum {
572 /* MIPS DSP Arithmetic Sub-class */
573 OPC_ADDUH_QB = (0x00 << 6) | OPC_ADDUH_QB_DSP,
574 OPC_ADDUH_R_QB = (0x02 << 6) | OPC_ADDUH_QB_DSP,
575 OPC_ADDQH_PH = (0x08 << 6) | OPC_ADDUH_QB_DSP,
576 OPC_ADDQH_R_PH = (0x0A << 6) | OPC_ADDUH_QB_DSP,
577 OPC_ADDQH_W = (0x10 << 6) | OPC_ADDUH_QB_DSP,
578 OPC_ADDQH_R_W = (0x12 << 6) | OPC_ADDUH_QB_DSP,
579 OPC_SUBUH_QB = (0x01 << 6) | OPC_ADDUH_QB_DSP,
580 OPC_SUBUH_R_QB = (0x03 << 6) | OPC_ADDUH_QB_DSP,
581 OPC_SUBQH_PH = (0x09 << 6) | OPC_ADDUH_QB_DSP,
582 OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP,
583 OPC_SUBQH_W = (0x11 << 6) | OPC_ADDUH_QB_DSP,
584 OPC_SUBQH_R_W = (0x13 << 6) | OPC_ADDUH_QB_DSP,
585 /* MIPS DSP Multiply Sub-class insns */
586 OPC_MUL_PH = (0x0C << 6) | OPC_ADDUH_QB_DSP,
587 OPC_MUL_S_PH = (0x0E << 6) | OPC_ADDUH_QB_DSP,
588 OPC_MULQ_S_W = (0x16 << 6) | OPC_ADDUH_QB_DSP,
589 OPC_MULQ_RS_W = (0x17 << 6) | OPC_ADDUH_QB_DSP,
590 };
591
592 #define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
593 enum {
594 /* MIPS DSP Arithmetic Sub-class */
595 OPC_ABSQ_S_QB = (0x01 << 6) | OPC_ABSQ_S_PH_DSP,
596 OPC_ABSQ_S_PH = (0x09 << 6) | OPC_ABSQ_S_PH_DSP,
597 OPC_ABSQ_S_W = (0x11 << 6) | OPC_ABSQ_S_PH_DSP,
598 OPC_PRECEQ_W_PHL = (0x0C << 6) | OPC_ABSQ_S_PH_DSP,
599 OPC_PRECEQ_W_PHR = (0x0D << 6) | OPC_ABSQ_S_PH_DSP,
600 OPC_PRECEQU_PH_QBL = (0x04 << 6) | OPC_ABSQ_S_PH_DSP,
601 OPC_PRECEQU_PH_QBR = (0x05 << 6) | OPC_ABSQ_S_PH_DSP,
602 OPC_PRECEQU_PH_QBLA = (0x06 << 6) | OPC_ABSQ_S_PH_DSP,
603 OPC_PRECEQU_PH_QBRA = (0x07 << 6) | OPC_ABSQ_S_PH_DSP,
604 OPC_PRECEU_PH_QBL = (0x1C << 6) | OPC_ABSQ_S_PH_DSP,
605 OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP,
606 OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP,
607 OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP,
608 /* DSP Bit/Manipulation Sub-class */
609 OPC_BITREV = (0x1B << 6) | OPC_ABSQ_S_PH_DSP,
610 OPC_REPL_QB = (0x02 << 6) | OPC_ABSQ_S_PH_DSP,
611 OPC_REPLV_QB = (0x03 << 6) | OPC_ABSQ_S_PH_DSP,
612 OPC_REPL_PH = (0x0A << 6) | OPC_ABSQ_S_PH_DSP,
613 OPC_REPLV_PH = (0x0B << 6) | OPC_ABSQ_S_PH_DSP,
614 };
615
616 #define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
617 enum {
618 /* MIPS DSP Arithmetic Sub-class */
619 OPC_PRECR_QB_PH = (0x0D << 6) | OPC_CMPU_EQ_QB_DSP,
620 OPC_PRECRQ_QB_PH = (0x0C << 6) | OPC_CMPU_EQ_QB_DSP,
621 OPC_PRECR_SRA_PH_W = (0x1E << 6) | OPC_CMPU_EQ_QB_DSP,
622 OPC_PRECR_SRA_R_PH_W = (0x1F << 6) | OPC_CMPU_EQ_QB_DSP,
623 OPC_PRECRQ_PH_W = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP,
624 OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP,
625 OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP,
626 /* DSP Compare-Pick Sub-class */
627 OPC_CMPU_EQ_QB = (0x00 << 6) | OPC_CMPU_EQ_QB_DSP,
628 OPC_CMPU_LT_QB = (0x01 << 6) | OPC_CMPU_EQ_QB_DSP,
629 OPC_CMPU_LE_QB = (0x02 << 6) | OPC_CMPU_EQ_QB_DSP,
630 OPC_CMPGU_EQ_QB = (0x04 << 6) | OPC_CMPU_EQ_QB_DSP,
631 OPC_CMPGU_LT_QB = (0x05 << 6) | OPC_CMPU_EQ_QB_DSP,
632 OPC_CMPGU_LE_QB = (0x06 << 6) | OPC_CMPU_EQ_QB_DSP,
633 OPC_CMPGDU_EQ_QB = (0x18 << 6) | OPC_CMPU_EQ_QB_DSP,
634 OPC_CMPGDU_LT_QB = (0x19 << 6) | OPC_CMPU_EQ_QB_DSP,
635 OPC_CMPGDU_LE_QB = (0x1A << 6) | OPC_CMPU_EQ_QB_DSP,
636 OPC_CMP_EQ_PH = (0x08 << 6) | OPC_CMPU_EQ_QB_DSP,
637 OPC_CMP_LT_PH = (0x09 << 6) | OPC_CMPU_EQ_QB_DSP,
638 OPC_CMP_LE_PH = (0x0A << 6) | OPC_CMPU_EQ_QB_DSP,
639 OPC_PICK_QB = (0x03 << 6) | OPC_CMPU_EQ_QB_DSP,
640 OPC_PICK_PH = (0x0B << 6) | OPC_CMPU_EQ_QB_DSP,
641 OPC_PACKRL_PH = (0x0E << 6) | OPC_CMPU_EQ_QB_DSP,
642 };
643
644 #define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
645 enum {
646 /* MIPS DSP GPR-Based Shift Sub-class */
647 OPC_SHLL_QB = (0x00 << 6) | OPC_SHLL_QB_DSP,
648 OPC_SHLLV_QB = (0x02 << 6) | OPC_SHLL_QB_DSP,
649 OPC_SHLL_PH = (0x08 << 6) | OPC_SHLL_QB_DSP,
650 OPC_SHLLV_PH = (0x0A << 6) | OPC_SHLL_QB_DSP,
651 OPC_SHLL_S_PH = (0x0C << 6) | OPC_SHLL_QB_DSP,
652 OPC_SHLLV_S_PH = (0x0E << 6) | OPC_SHLL_QB_DSP,
653 OPC_SHLL_S_W = (0x14 << 6) | OPC_SHLL_QB_DSP,
654 OPC_SHLLV_S_W = (0x16 << 6) | OPC_SHLL_QB_DSP,
655 OPC_SHRL_QB = (0x01 << 6) | OPC_SHLL_QB_DSP,
656 OPC_SHRLV_QB = (0x03 << 6) | OPC_SHLL_QB_DSP,
657 OPC_SHRL_PH = (0x19 << 6) | OPC_SHLL_QB_DSP,
658 OPC_SHRLV_PH = (0x1B << 6) | OPC_SHLL_QB_DSP,
659 OPC_SHRA_QB = (0x04 << 6) | OPC_SHLL_QB_DSP,
660 OPC_SHRA_R_QB = (0x05 << 6) | OPC_SHLL_QB_DSP,
661 OPC_SHRAV_QB = (0x06 << 6) | OPC_SHLL_QB_DSP,
662 OPC_SHRAV_R_QB = (0x07 << 6) | OPC_SHLL_QB_DSP,
663 OPC_SHRA_PH = (0x09 << 6) | OPC_SHLL_QB_DSP,
664 OPC_SHRAV_PH = (0x0B << 6) | OPC_SHLL_QB_DSP,
665 OPC_SHRA_R_PH = (0x0D << 6) | OPC_SHLL_QB_DSP,
666 OPC_SHRAV_R_PH = (0x0F << 6) | OPC_SHLL_QB_DSP,
667 OPC_SHRA_R_W = (0x15 << 6) | OPC_SHLL_QB_DSP,
668 OPC_SHRAV_R_W = (0x17 << 6) | OPC_SHLL_QB_DSP,
669 };
670
671 #define MASK_DPA_W_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
672 enum {
673 /* MIPS DSP Multiply Sub-class insns */
674 OPC_DPAU_H_QBL = (0x03 << 6) | OPC_DPA_W_PH_DSP,
675 OPC_DPAU_H_QBR = (0x07 << 6) | OPC_DPA_W_PH_DSP,
676 OPC_DPSU_H_QBL = (0x0B << 6) | OPC_DPA_W_PH_DSP,
677 OPC_DPSU_H_QBR = (0x0F << 6) | OPC_DPA_W_PH_DSP,
678 OPC_DPA_W_PH = (0x00 << 6) | OPC_DPA_W_PH_DSP,
679 OPC_DPAX_W_PH = (0x08 << 6) | OPC_DPA_W_PH_DSP,
680 OPC_DPAQ_S_W_PH = (0x04 << 6) | OPC_DPA_W_PH_DSP,
681 OPC_DPAQX_S_W_PH = (0x18 << 6) | OPC_DPA_W_PH_DSP,
682 OPC_DPAQX_SA_W_PH = (0x1A << 6) | OPC_DPA_W_PH_DSP,
683 OPC_DPS_W_PH = (0x01 << 6) | OPC_DPA_W_PH_DSP,
684 OPC_DPSX_W_PH = (0x09 << 6) | OPC_DPA_W_PH_DSP,
685 OPC_DPSQ_S_W_PH = (0x05 << 6) | OPC_DPA_W_PH_DSP,
686 OPC_DPSQX_S_W_PH = (0x19 << 6) | OPC_DPA_W_PH_DSP,
687 OPC_DPSQX_SA_W_PH = (0x1B << 6) | OPC_DPA_W_PH_DSP,
688 OPC_MULSAQ_S_W_PH = (0x06 << 6) | OPC_DPA_W_PH_DSP,
689 OPC_DPAQ_SA_L_W = (0x0C << 6) | OPC_DPA_W_PH_DSP,
690 OPC_DPSQ_SA_L_W = (0x0D << 6) | OPC_DPA_W_PH_DSP,
691 OPC_MAQ_S_W_PHL = (0x14 << 6) | OPC_DPA_W_PH_DSP,
692 OPC_MAQ_S_W_PHR = (0x16 << 6) | OPC_DPA_W_PH_DSP,
693 OPC_MAQ_SA_W_PHL = (0x10 << 6) | OPC_DPA_W_PH_DSP,
694 OPC_MAQ_SA_W_PHR = (0x12 << 6) | OPC_DPA_W_PH_DSP,
695 OPC_MULSA_W_PH = (0x02 << 6) | OPC_DPA_W_PH_DSP,
696 };
697
698 #define MASK_INSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
699 enum {
700 /* DSP Bit/Manipulation Sub-class */
701 OPC_INSV = (0x00 << 6) | OPC_INSV_DSP,
702 };
703
704 #define MASK_APPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
705 enum {
706 /* MIPS DSP Append Sub-class */
707 OPC_APPEND = (0x00 << 6) | OPC_APPEND_DSP,
708 OPC_PREPEND = (0x01 << 6) | OPC_APPEND_DSP,
709 OPC_BALIGN = (0x10 << 6) | OPC_APPEND_DSP,
710 };
711
712 #define MASK_EXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
713 enum {
714 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
715 OPC_EXTR_W = (0x00 << 6) | OPC_EXTR_W_DSP,
716 OPC_EXTR_R_W = (0x04 << 6) | OPC_EXTR_W_DSP,
717 OPC_EXTR_RS_W = (0x06 << 6) | OPC_EXTR_W_DSP,
718 OPC_EXTR_S_H = (0x0E << 6) | OPC_EXTR_W_DSP,
719 OPC_EXTRV_S_H = (0x0F << 6) | OPC_EXTR_W_DSP,
720 OPC_EXTRV_W = (0x01 << 6) | OPC_EXTR_W_DSP,
721 OPC_EXTRV_R_W = (0x05 << 6) | OPC_EXTR_W_DSP,
722 OPC_EXTRV_RS_W = (0x07 << 6) | OPC_EXTR_W_DSP,
723 OPC_EXTP = (0x02 << 6) | OPC_EXTR_W_DSP,
724 OPC_EXTPV = (0x03 << 6) | OPC_EXTR_W_DSP,
725 OPC_EXTPDP = (0x0A << 6) | OPC_EXTR_W_DSP,
726 OPC_EXTPDPV = (0x0B << 6) | OPC_EXTR_W_DSP,
727 OPC_SHILO = (0x1A << 6) | OPC_EXTR_W_DSP,
728 OPC_SHILOV = (0x1B << 6) | OPC_EXTR_W_DSP,
729 OPC_MTHLIP = (0x1F << 6) | OPC_EXTR_W_DSP,
730 OPC_WRDSP = (0x13 << 6) | OPC_EXTR_W_DSP,
731 OPC_RDDSP = (0x12 << 6) | OPC_EXTR_W_DSP,
732 };
733
734 #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
735 enum {
736 /* MIPS DSP Arithmetic Sub-class */
737 OPC_PRECEQ_L_PWL = (0x14 << 6) | OPC_ABSQ_S_QH_DSP,
738 OPC_PRECEQ_L_PWR = (0x15 << 6) | OPC_ABSQ_S_QH_DSP,
739 OPC_PRECEQ_PW_QHL = (0x0C << 6) | OPC_ABSQ_S_QH_DSP,
740 OPC_PRECEQ_PW_QHR = (0x0D << 6) | OPC_ABSQ_S_QH_DSP,
741 OPC_PRECEQ_PW_QHLA = (0x0E << 6) | OPC_ABSQ_S_QH_DSP,
742 OPC_PRECEQ_PW_QHRA = (0x0F << 6) | OPC_ABSQ_S_QH_DSP,
743 OPC_PRECEQU_QH_OBL = (0x04 << 6) | OPC_ABSQ_S_QH_DSP,
744 OPC_PRECEQU_QH_OBR = (0x05 << 6) | OPC_ABSQ_S_QH_DSP,
745 OPC_PRECEQU_QH_OBLA = (0x06 << 6) | OPC_ABSQ_S_QH_DSP,
746 OPC_PRECEQU_QH_OBRA = (0x07 << 6) | OPC_ABSQ_S_QH_DSP,
747 OPC_PRECEU_QH_OBL = (0x1C << 6) | OPC_ABSQ_S_QH_DSP,
748 OPC_PRECEU_QH_OBR = (0x1D << 6) | OPC_ABSQ_S_QH_DSP,
749 OPC_PRECEU_QH_OBLA = (0x1E << 6) | OPC_ABSQ_S_QH_DSP,
750 OPC_PRECEU_QH_OBRA = (0x1F << 6) | OPC_ABSQ_S_QH_DSP,
751 OPC_ABSQ_S_OB = (0x01 << 6) | OPC_ABSQ_S_QH_DSP,
752 OPC_ABSQ_S_PW = (0x11 << 6) | OPC_ABSQ_S_QH_DSP,
753 OPC_ABSQ_S_QH = (0x09 << 6) | OPC_ABSQ_S_QH_DSP,
754 /* DSP Bit/Manipulation Sub-class */
755 OPC_REPL_OB = (0x02 << 6) | OPC_ABSQ_S_QH_DSP,
756 OPC_REPL_PW = (0x12 << 6) | OPC_ABSQ_S_QH_DSP,
757 OPC_REPL_QH = (0x0A << 6) | OPC_ABSQ_S_QH_DSP,
758 OPC_REPLV_OB = (0x03 << 6) | OPC_ABSQ_S_QH_DSP,
759 OPC_REPLV_PW = (0x13 << 6) | OPC_ABSQ_S_QH_DSP,
760 OPC_REPLV_QH = (0x0B << 6) | OPC_ABSQ_S_QH_DSP,
761 };
762
763 #define MASK_ADDU_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
764 enum {
765 /* MIPS DSP Multiply Sub-class insns */
766 OPC_MULEQ_S_PW_QHL = (0x1C << 6) | OPC_ADDU_OB_DSP,
767 OPC_MULEQ_S_PW_QHR = (0x1D << 6) | OPC_ADDU_OB_DSP,
768 OPC_MULEU_S_QH_OBL = (0x06 << 6) | OPC_ADDU_OB_DSP,
769 OPC_MULEU_S_QH_OBR = (0x07 << 6) | OPC_ADDU_OB_DSP,
770 OPC_MULQ_RS_QH = (0x1F << 6) | OPC_ADDU_OB_DSP,
771 /* MIPS DSP Arithmetic Sub-class */
772 OPC_RADDU_L_OB = (0x14 << 6) | OPC_ADDU_OB_DSP,
773 OPC_SUBQ_PW = (0x13 << 6) | OPC_ADDU_OB_DSP,
774 OPC_SUBQ_S_PW = (0x17 << 6) | OPC_ADDU_OB_DSP,
775 OPC_SUBQ_QH = (0x0B << 6) | OPC_ADDU_OB_DSP,
776 OPC_SUBQ_S_QH = (0x0F << 6) | OPC_ADDU_OB_DSP,
777 OPC_SUBU_OB = (0x01 << 6) | OPC_ADDU_OB_DSP,
778 OPC_SUBU_S_OB = (0x05 << 6) | OPC_ADDU_OB_DSP,
779 OPC_SUBU_QH = (0x09 << 6) | OPC_ADDU_OB_DSP,
780 OPC_SUBU_S_QH = (0x0D << 6) | OPC_ADDU_OB_DSP,
781 OPC_SUBUH_OB = (0x19 << 6) | OPC_ADDU_OB_DSP,
782 OPC_SUBUH_R_OB = (0x1B << 6) | OPC_ADDU_OB_DSP,
783 OPC_ADDQ_PW = (0x12 << 6) | OPC_ADDU_OB_DSP,
784 OPC_ADDQ_S_PW = (0x16 << 6) | OPC_ADDU_OB_DSP,
785 OPC_ADDQ_QH = (0x0A << 6) | OPC_ADDU_OB_DSP,
786 OPC_ADDQ_S_QH = (0x0E << 6) | OPC_ADDU_OB_DSP,
787 OPC_ADDU_OB = (0x00 << 6) | OPC_ADDU_OB_DSP,
788 OPC_ADDU_S_OB = (0x04 << 6) | OPC_ADDU_OB_DSP,
789 OPC_ADDU_QH = (0x08 << 6) | OPC_ADDU_OB_DSP,
790 OPC_ADDU_S_QH = (0x0C << 6) | OPC_ADDU_OB_DSP,
791 OPC_ADDUH_OB = (0x18 << 6) | OPC_ADDU_OB_DSP,
792 OPC_ADDUH_R_OB = (0x1A << 6) | OPC_ADDU_OB_DSP,
793 };
794
795 #define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
796 enum {
797 /* DSP Compare-Pick Sub-class */
798 OPC_CMP_EQ_PW = (0x10 << 6) | OPC_CMPU_EQ_OB_DSP,
799 OPC_CMP_LT_PW = (0x11 << 6) | OPC_CMPU_EQ_OB_DSP,
800 OPC_CMP_LE_PW = (0x12 << 6) | OPC_CMPU_EQ_OB_DSP,
801 OPC_CMP_EQ_QH = (0x08 << 6) | OPC_CMPU_EQ_OB_DSP,
802 OPC_CMP_LT_QH = (0x09 << 6) | OPC_CMPU_EQ_OB_DSP,
803 OPC_CMP_LE_QH = (0x0A << 6) | OPC_CMPU_EQ_OB_DSP,
804 OPC_CMPGDU_EQ_OB = (0x18 << 6) | OPC_CMPU_EQ_OB_DSP,
805 OPC_CMPGDU_LT_OB = (0x19 << 6) | OPC_CMPU_EQ_OB_DSP,
806 OPC_CMPGDU_LE_OB = (0x1A << 6) | OPC_CMPU_EQ_OB_DSP,
807 OPC_CMPGU_EQ_OB = (0x04 << 6) | OPC_CMPU_EQ_OB_DSP,
808 OPC_CMPGU_LT_OB = (0x05 << 6) | OPC_CMPU_EQ_OB_DSP,
809 OPC_CMPGU_LE_OB = (0x06 << 6) | OPC_CMPU_EQ_OB_DSP,
810 OPC_CMPU_EQ_OB = (0x00 << 6) | OPC_CMPU_EQ_OB_DSP,
811 OPC_CMPU_LT_OB = (0x01 << 6) | OPC_CMPU_EQ_OB_DSP,
812 OPC_CMPU_LE_OB = (0x02 << 6) | OPC_CMPU_EQ_OB_DSP,
813 OPC_PACKRL_PW = (0x0E << 6) | OPC_CMPU_EQ_OB_DSP,
814 OPC_PICK_OB = (0x03 << 6) | OPC_CMPU_EQ_OB_DSP,
815 OPC_PICK_PW = (0x13 << 6) | OPC_CMPU_EQ_OB_DSP,
816 OPC_PICK_QH = (0x0B << 6) | OPC_CMPU_EQ_OB_DSP,
817 /* MIPS DSP Arithmetic Sub-class */
818 OPC_PRECR_OB_QH = (0x0D << 6) | OPC_CMPU_EQ_OB_DSP,
819 OPC_PRECR_SRA_QH_PW = (0x1E << 6) | OPC_CMPU_EQ_OB_DSP,
820 OPC_PRECR_SRA_R_QH_PW = (0x1F << 6) | OPC_CMPU_EQ_OB_DSP,
821 OPC_PRECRQ_OB_QH = (0x0C << 6) | OPC_CMPU_EQ_OB_DSP,
822 OPC_PRECRQ_PW_L = (0x1C << 6) | OPC_CMPU_EQ_OB_DSP,
823 OPC_PRECRQ_QH_PW = (0x14 << 6) | OPC_CMPU_EQ_OB_DSP,
824 OPC_PRECRQ_RS_QH_PW = (0x15 << 6) | OPC_CMPU_EQ_OB_DSP,
825 OPC_PRECRQU_S_OB_QH = (0x0F << 6) | OPC_CMPU_EQ_OB_DSP,
826 };
827
828 #define MASK_DAPPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
829 enum {
830 /* DSP Append Sub-class */
831 OPC_DAPPEND = (0x00 << 6) | OPC_DAPPEND_DSP,
832 OPC_PREPENDD = (0x03 << 6) | OPC_DAPPEND_DSP,
833 OPC_PREPENDW = (0x01 << 6) | OPC_DAPPEND_DSP,
834 OPC_DBALIGN = (0x10 << 6) | OPC_DAPPEND_DSP,
835 };
836
837 #define MASK_DEXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
838 enum {
839 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
840 OPC_DMTHLIP = (0x1F << 6) | OPC_DEXTR_W_DSP,
841 OPC_DSHILO = (0x1A << 6) | OPC_DEXTR_W_DSP,
842 OPC_DEXTP = (0x02 << 6) | OPC_DEXTR_W_DSP,
843 OPC_DEXTPDP = (0x0A << 6) | OPC_DEXTR_W_DSP,
844 OPC_DEXTPDPV = (0x0B << 6) | OPC_DEXTR_W_DSP,
845 OPC_DEXTPV = (0x03 << 6) | OPC_DEXTR_W_DSP,
846 OPC_DEXTR_L = (0x10 << 6) | OPC_DEXTR_W_DSP,
847 OPC_DEXTR_R_L = (0x14 << 6) | OPC_DEXTR_W_DSP,
848 OPC_DEXTR_RS_L = (0x16 << 6) | OPC_DEXTR_W_DSP,
849 OPC_DEXTR_W = (0x00 << 6) | OPC_DEXTR_W_DSP,
850 OPC_DEXTR_R_W = (0x04 << 6) | OPC_DEXTR_W_DSP,
851 OPC_DEXTR_RS_W = (0x06 << 6) | OPC_DEXTR_W_DSP,
852 OPC_DEXTR_S_H = (0x0E << 6) | OPC_DEXTR_W_DSP,
853 OPC_DEXTRV_L = (0x11 << 6) | OPC_DEXTR_W_DSP,
854 OPC_DEXTRV_R_L = (0x15 << 6) | OPC_DEXTR_W_DSP,
855 OPC_DEXTRV_RS_L = (0x17 << 6) | OPC_DEXTR_W_DSP,
856 OPC_DEXTRV_S_H = (0x0F << 6) | OPC_DEXTR_W_DSP,
857 OPC_DEXTRV_W = (0x01 << 6) | OPC_DEXTR_W_DSP,
858 OPC_DEXTRV_R_W = (0x05 << 6) | OPC_DEXTR_W_DSP,
859 OPC_DEXTRV_RS_W = (0x07 << 6) | OPC_DEXTR_W_DSP,
860 OPC_DSHILOV = (0x1B << 6) | OPC_DEXTR_W_DSP,
861 };
862
863 #define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
864 enum {
865 /* DSP Bit/Manipulation Sub-class */
866 OPC_DINSV = (0x00 << 6) | OPC_DINSV_DSP,
867 };
868
869 #define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
870 enum {
871 /* MIPS DSP Multiply Sub-class insns */
872 OPC_DMADD = (0x19 << 6) | OPC_DPAQ_W_QH_DSP,
873 OPC_DMADDU = (0x1D << 6) | OPC_DPAQ_W_QH_DSP,
874 OPC_DMSUB = (0x1B << 6) | OPC_DPAQ_W_QH_DSP,
875 OPC_DMSUBU = (0x1F << 6) | OPC_DPAQ_W_QH_DSP,
876 OPC_DPA_W_QH = (0x00 << 6) | OPC_DPAQ_W_QH_DSP,
877 OPC_DPAQ_S_W_QH = (0x04 << 6) | OPC_DPAQ_W_QH_DSP,
878 OPC_DPAQ_SA_L_PW = (0x0C << 6) | OPC_DPAQ_W_QH_DSP,
879 OPC_DPAU_H_OBL = (0x03 << 6) | OPC_DPAQ_W_QH_DSP,
880 OPC_DPAU_H_OBR = (0x07 << 6) | OPC_DPAQ_W_QH_DSP,
881 OPC_DPS_W_QH = (0x01 << 6) | OPC_DPAQ_W_QH_DSP,
882 OPC_DPSQ_S_W_QH = (0x05 << 6) | OPC_DPAQ_W_QH_DSP,
883 OPC_DPSQ_SA_L_PW = (0x0D << 6) | OPC_DPAQ_W_QH_DSP,
884 OPC_DPSU_H_OBL = (0x0B << 6) | OPC_DPAQ_W_QH_DSP,
885 OPC_DPSU_H_OBR = (0x0F << 6) | OPC_DPAQ_W_QH_DSP,
886 OPC_MAQ_S_L_PWL = (0x1C << 6) | OPC_DPAQ_W_QH_DSP,
887 OPC_MAQ_S_L_PWR = (0x1E << 6) | OPC_DPAQ_W_QH_DSP,
888 OPC_MAQ_S_W_QHLL = (0x14 << 6) | OPC_DPAQ_W_QH_DSP,
889 OPC_MAQ_SA_W_QHLL = (0x10 << 6) | OPC_DPAQ_W_QH_DSP,
890 OPC_MAQ_S_W_QHLR = (0x15 << 6) | OPC_DPAQ_W_QH_DSP,
891 OPC_MAQ_SA_W_QHLR = (0x11 << 6) | OPC_DPAQ_W_QH_DSP,
892 OPC_MAQ_S_W_QHRL = (0x16 << 6) | OPC_DPAQ_W_QH_DSP,
893 OPC_MAQ_SA_W_QHRL = (0x12 << 6) | OPC_DPAQ_W_QH_DSP,
894 OPC_MAQ_S_W_QHRR = (0x17 << 6) | OPC_DPAQ_W_QH_DSP,
895 OPC_MAQ_SA_W_QHRR = (0x13 << 6) | OPC_DPAQ_W_QH_DSP,
896 OPC_MULSAQ_S_L_PW = (0x0E << 6) | OPC_DPAQ_W_QH_DSP,
897 OPC_MULSAQ_S_W_QH = (0x06 << 6) | OPC_DPAQ_W_QH_DSP,
898 };
899
900 #define MASK_SHLL_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
901 enum {
902 /* MIPS DSP GPR-Based Shift Sub-class */
903 OPC_SHLL_PW = (0x10 << 6) | OPC_SHLL_OB_DSP,
904 OPC_SHLL_S_PW = (0x14 << 6) | OPC_SHLL_OB_DSP,
905 OPC_SHLLV_OB = (0x02 << 6) | OPC_SHLL_OB_DSP,
906 OPC_SHLLV_PW = (0x12 << 6) | OPC_SHLL_OB_DSP,
907 OPC_SHLLV_S_PW = (0x16 << 6) | OPC_SHLL_OB_DSP,
908 OPC_SHLLV_QH = (0x0A << 6) | OPC_SHLL_OB_DSP,
909 OPC_SHLLV_S_QH = (0x0E << 6) | OPC_SHLL_OB_DSP,
910 OPC_SHRA_PW = (0x11 << 6) | OPC_SHLL_OB_DSP,
911 OPC_SHRA_R_PW = (0x15 << 6) | OPC_SHLL_OB_DSP,
912 OPC_SHRAV_OB = (0x06 << 6) | OPC_SHLL_OB_DSP,
913 OPC_SHRAV_R_OB = (0x07 << 6) | OPC_SHLL_OB_DSP,
914 OPC_SHRAV_PW = (0x13 << 6) | OPC_SHLL_OB_DSP,
915 OPC_SHRAV_R_PW = (0x17 << 6) | OPC_SHLL_OB_DSP,
916 OPC_SHRAV_QH = (0x0B << 6) | OPC_SHLL_OB_DSP,
917 OPC_SHRAV_R_QH = (0x0F << 6) | OPC_SHLL_OB_DSP,
918 OPC_SHRLV_OB = (0x03 << 6) | OPC_SHLL_OB_DSP,
919 OPC_SHRLV_QH = (0x1B << 6) | OPC_SHLL_OB_DSP,
920 OPC_SHLL_OB = (0x00 << 6) | OPC_SHLL_OB_DSP,
921 OPC_SHLL_QH = (0x08 << 6) | OPC_SHLL_OB_DSP,
922 OPC_SHLL_S_QH = (0x0C << 6) | OPC_SHLL_OB_DSP,
923 OPC_SHRA_OB = (0x04 << 6) | OPC_SHLL_OB_DSP,
924 OPC_SHRA_R_OB = (0x05 << 6) | OPC_SHLL_OB_DSP,
925 OPC_SHRA_QH = (0x09 << 6) | OPC_SHLL_OB_DSP,
926 OPC_SHRA_R_QH = (0x0D << 6) | OPC_SHLL_OB_DSP,
927 OPC_SHRL_OB = (0x01 << 6) | OPC_SHLL_OB_DSP,
928 OPC_SHRL_QH = (0x19 << 6) | OPC_SHLL_OB_DSP,
929 };
930
931 /* Coprocessor 0 (rs field) */
932 #define MASK_CP0(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
933
934 enum {
935 OPC_MFC0 = (0x00 << 21) | OPC_CP0,
936 OPC_DMFC0 = (0x01 << 21) | OPC_CP0,
937 OPC_MFHC0 = (0x02 << 21) | OPC_CP0,
938 OPC_MTC0 = (0x04 << 21) | OPC_CP0,
939 OPC_DMTC0 = (0x05 << 21) | OPC_CP0,
940 OPC_MTHC0 = (0x06 << 21) | OPC_CP0,
941 OPC_MFTR = (0x08 << 21) | OPC_CP0,
942 OPC_RDPGPR = (0x0A << 21) | OPC_CP0,
943 OPC_MFMC0 = (0x0B << 21) | OPC_CP0,
944 OPC_MTTR = (0x0C << 21) | OPC_CP0,
945 OPC_WRPGPR = (0x0E << 21) | OPC_CP0,
946 OPC_C0 = (0x10 << 21) | OPC_CP0,
947 OPC_C0_1 = (0x11 << 21) | OPC_CP0,
948 OPC_C0_2 = (0x12 << 21) | OPC_CP0,
949 OPC_C0_3 = (0x13 << 21) | OPC_CP0,
950 OPC_C0_4 = (0x14 << 21) | OPC_CP0,
951 OPC_C0_5 = (0x15 << 21) | OPC_CP0,
952 OPC_C0_6 = (0x16 << 21) | OPC_CP0,
953 OPC_C0_7 = (0x17 << 21) | OPC_CP0,
954 OPC_C0_8 = (0x18 << 21) | OPC_CP0,
955 OPC_C0_9 = (0x19 << 21) | OPC_CP0,
956 OPC_C0_A = (0x1A << 21) | OPC_CP0,
957 OPC_C0_B = (0x1B << 21) | OPC_CP0,
958 OPC_C0_C = (0x1C << 21) | OPC_CP0,
959 OPC_C0_D = (0x1D << 21) | OPC_CP0,
960 OPC_C0_E = (0x1E << 21) | OPC_CP0,
961 OPC_C0_F = (0x1F << 21) | OPC_CP0,
962 };
963
964 /* MFMC0 opcodes */
965 #define MASK_MFMC0(op) (MASK_CP0(op) | (op & 0xFFFF))
966
967 enum {
968 OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
969 OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
970 OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0,
971 OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0,
972 OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
973 OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0,
974 OPC_DVP = 0x04 | (0 << 3) | (1 << 5) | (0 << 11) | OPC_MFMC0,
975 OPC_EVP = 0x04 | (0 << 3) | (0 << 5) | (0 << 11) | OPC_MFMC0,
976 };
977
978 /* Coprocessor 0 (with rs == C0) */
979 #define MASK_C0(op) (MASK_CP0(op) | (op & 0x3F))
980
981 enum {
982 OPC_TLBR = 0x01 | OPC_C0,
983 OPC_TLBWI = 0x02 | OPC_C0,
984 OPC_TLBINV = 0x03 | OPC_C0,
985 OPC_TLBINVF = 0x04 | OPC_C0,
986 OPC_TLBWR = 0x06 | OPC_C0,
987 OPC_TLBP = 0x08 | OPC_C0,
988 OPC_RFE = 0x10 | OPC_C0,
989 OPC_ERET = 0x18 | OPC_C0,
990 OPC_DERET = 0x1F | OPC_C0,
991 OPC_WAIT = 0x20 | OPC_C0,
992 };
993
994 #define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
995
996 enum {
997 OPC_MFC2 = (0x00 << 21) | OPC_CP2,
998 OPC_DMFC2 = (0x01 << 21) | OPC_CP2,
999 OPC_CFC2 = (0x02 << 21) | OPC_CP2,
1000 OPC_MFHC2 = (0x03 << 21) | OPC_CP2,
1001 OPC_MTC2 = (0x04 << 21) | OPC_CP2,
1002 OPC_DMTC2 = (0x05 << 21) | OPC_CP2,
1003 OPC_CTC2 = (0x06 << 21) | OPC_CP2,
1004 OPC_MTHC2 = (0x07 << 21) | OPC_CP2,
1005 OPC_BC2 = (0x08 << 21) | OPC_CP2,
1006 OPC_BC2EQZ = (0x09 << 21) | OPC_CP2,
1007 OPC_BC2NEZ = (0x0D << 21) | OPC_CP2,
1008 };
1009
1010 #define MASK_LMMI(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))
1011
1012 enum {
1013 OPC_PADDSH = (24 << 21) | (0x00) | OPC_CP2,
1014 OPC_PADDUSH = (25 << 21) | (0x00) | OPC_CP2,
1015 OPC_PADDH = (26 << 21) | (0x00) | OPC_CP2,
1016 OPC_PADDW = (27 << 21) | (0x00) | OPC_CP2,
1017 OPC_PADDSB = (28 << 21) | (0x00) | OPC_CP2,
1018 OPC_PADDUSB = (29 << 21) | (0x00) | OPC_CP2,
1019 OPC_PADDB = (30 << 21) | (0x00) | OPC_CP2,
1020 OPC_PADDD = (31 << 21) | (0x00) | OPC_CP2,
1021
1022 OPC_PSUBSH = (24 << 21) | (0x01) | OPC_CP2,
1023 OPC_PSUBUSH = (25 << 21) | (0x01) | OPC_CP2,
1024 OPC_PSUBH = (26 << 21) | (0x01) | OPC_CP2,
1025 OPC_PSUBW = (27 << 21) | (0x01) | OPC_CP2,
1026 OPC_PSUBSB = (28 << 21) | (0x01) | OPC_CP2,
1027 OPC_PSUBUSB = (29 << 21) | (0x01) | OPC_CP2,
1028 OPC_PSUBB = (30 << 21) | (0x01) | OPC_CP2,
1029 OPC_PSUBD = (31 << 21) | (0x01) | OPC_CP2,
1030
1031 OPC_PSHUFH = (24 << 21) | (0x02) | OPC_CP2,
1032 OPC_PACKSSWH = (25 << 21) | (0x02) | OPC_CP2,
1033 OPC_PACKSSHB = (26 << 21) | (0x02) | OPC_CP2,
1034 OPC_PACKUSHB = (27 << 21) | (0x02) | OPC_CP2,
1035 OPC_XOR_CP2 = (28 << 21) | (0x02) | OPC_CP2,
1036 OPC_NOR_CP2 = (29 << 21) | (0x02) | OPC_CP2,
1037 OPC_AND_CP2 = (30 << 21) | (0x02) | OPC_CP2,
1038 OPC_PANDN = (31 << 21) | (0x02) | OPC_CP2,
1039
1040 OPC_PUNPCKLHW = (24 << 21) | (0x03) | OPC_CP2,
1041 OPC_PUNPCKHHW = (25 << 21) | (0x03) | OPC_CP2,
1042 OPC_PUNPCKLBH = (26 << 21) | (0x03) | OPC_CP2,
1043 OPC_PUNPCKHBH = (27 << 21) | (0x03) | OPC_CP2,
1044 OPC_PINSRH_0 = (28 << 21) | (0x03) | OPC_CP2,
1045 OPC_PINSRH_1 = (29 << 21) | (0x03) | OPC_CP2,
1046 OPC_PINSRH_2 = (30 << 21) | (0x03) | OPC_CP2,
1047 OPC_PINSRH_3 = (31 << 21) | (0x03) | OPC_CP2,
1048
1049 OPC_PAVGH = (24 << 21) | (0x08) | OPC_CP2,
1050 OPC_PAVGB = (25 << 21) | (0x08) | OPC_CP2,
1051 OPC_PMAXSH = (26 << 21) | (0x08) | OPC_CP2,
1052 OPC_PMINSH = (27 << 21) | (0x08) | OPC_CP2,
1053 OPC_PMAXUB = (28 << 21) | (0x08) | OPC_CP2,
1054 OPC_PMINUB = (29 << 21) | (0x08) | OPC_CP2,
1055
1056 OPC_PCMPEQW = (24 << 21) | (0x09) | OPC_CP2,
1057 OPC_PCMPGTW = (25 << 21) | (0x09) | OPC_CP2,
1058 OPC_PCMPEQH = (26 << 21) | (0x09) | OPC_CP2,
1059 OPC_PCMPGTH = (27 << 21) | (0x09) | OPC_CP2,
1060 OPC_PCMPEQB = (28 << 21) | (0x09) | OPC_CP2,
1061 OPC_PCMPGTB = (29 << 21) | (0x09) | OPC_CP2,
1062
1063 OPC_PSLLW = (24 << 21) | (0x0A) | OPC_CP2,
1064 OPC_PSLLH = (25 << 21) | (0x0A) | OPC_CP2,
1065 OPC_PMULLH = (26 << 21) | (0x0A) | OPC_CP2,
1066 OPC_PMULHH = (27 << 21) | (0x0A) | OPC_CP2,
1067 OPC_PMULUW = (28 << 21) | (0x0A) | OPC_CP2,
1068 OPC_PMULHUH = (29 << 21) | (0x0A) | OPC_CP2,
1069
1070 OPC_PSRLW = (24 << 21) | (0x0B) | OPC_CP2,
1071 OPC_PSRLH = (25 << 21) | (0x0B) | OPC_CP2,
1072 OPC_PSRAW = (26 << 21) | (0x0B) | OPC_CP2,
1073 OPC_PSRAH = (27 << 21) | (0x0B) | OPC_CP2,
1074 OPC_PUNPCKLWD = (28 << 21) | (0x0B) | OPC_CP2,
1075 OPC_PUNPCKHWD = (29 << 21) | (0x0B) | OPC_CP2,
1076
1077 OPC_ADDU_CP2 = (24 << 21) | (0x0C) | OPC_CP2,
1078 OPC_OR_CP2 = (25 << 21) | (0x0C) | OPC_CP2,
1079 OPC_ADD_CP2 = (26 << 21) | (0x0C) | OPC_CP2,
1080 OPC_DADD_CP2 = (27 << 21) | (0x0C) | OPC_CP2,
1081 OPC_SEQU_CP2 = (28 << 21) | (0x0C) | OPC_CP2,
1082 OPC_SEQ_CP2 = (29 << 21) | (0x0C) | OPC_CP2,
1083
1084 OPC_SUBU_CP2 = (24 << 21) | (0x0D) | OPC_CP2,
1085 OPC_PASUBUB = (25 << 21) | (0x0D) | OPC_CP2,
1086 OPC_SUB_CP2 = (26 << 21) | (0x0D) | OPC_CP2,
1087 OPC_DSUB_CP2 = (27 << 21) | (0x0D) | OPC_CP2,
1088 OPC_SLTU_CP2 = (28 << 21) | (0x0D) | OPC_CP2,
1089 OPC_SLT_CP2 = (29 << 21) | (0x0D) | OPC_CP2,
1090
1091 OPC_SLL_CP2 = (24 << 21) | (0x0E) | OPC_CP2,
1092 OPC_DSLL_CP2 = (25 << 21) | (0x0E) | OPC_CP2,
1093 OPC_PEXTRH = (26 << 21) | (0x0E) | OPC_CP2,
1094 OPC_PMADDHW = (27 << 21) | (0x0E) | OPC_CP2,
1095 OPC_SLEU_CP2 = (28 << 21) | (0x0E) | OPC_CP2,
1096 OPC_SLE_CP2 = (29 << 21) | (0x0E) | OPC_CP2,
1097
1098 OPC_SRL_CP2 = (24 << 21) | (0x0F) | OPC_CP2,
1099 OPC_DSRL_CP2 = (25 << 21) | (0x0F) | OPC_CP2,
1100 OPC_SRA_CP2 = (26 << 21) | (0x0F) | OPC_CP2,
1101 OPC_DSRA_CP2 = (27 << 21) | (0x0F) | OPC_CP2,
1102 OPC_BIADD = (28 << 21) | (0x0F) | OPC_CP2,
1103 OPC_PMOVMSKB = (29 << 21) | (0x0F) | OPC_CP2,
1104 };
1105
1106
1107 #define MASK_CP3(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
1108
1109 enum {
1110 OPC_LWXC1 = 0x00 | OPC_CP3,
1111 OPC_LDXC1 = 0x01 | OPC_CP3,
1112 OPC_LUXC1 = 0x05 | OPC_CP3,
1113 OPC_SWXC1 = 0x08 | OPC_CP3,
1114 OPC_SDXC1 = 0x09 | OPC_CP3,
1115 OPC_SUXC1 = 0x0D | OPC_CP3,
1116 OPC_PREFX = 0x0F | OPC_CP3,
1117 OPC_ALNV_PS = 0x1E | OPC_CP3,
1118 OPC_MADD_S = 0x20 | OPC_CP3,
1119 OPC_MADD_D = 0x21 | OPC_CP3,
1120 OPC_MADD_PS = 0x26 | OPC_CP3,
1121 OPC_MSUB_S = 0x28 | OPC_CP3,
1122 OPC_MSUB_D = 0x29 | OPC_CP3,
1123 OPC_MSUB_PS = 0x2E | OPC_CP3,
1124 OPC_NMADD_S = 0x30 | OPC_CP3,
1125 OPC_NMADD_D = 0x31 | OPC_CP3,
1126 OPC_NMADD_PS = 0x36 | OPC_CP3,
1127 OPC_NMSUB_S = 0x38 | OPC_CP3,
1128 OPC_NMSUB_D = 0x39 | OPC_CP3,
1129 OPC_NMSUB_PS = 0x3E | OPC_CP3,
1130 };
1131
1132 /*
1133 * MMI (MultiMedia Instruction) encodings
1134 * ======================================
1135 *
1136 * MMI instructions encoding table keys:
1137 *
1138 * * This code is reserved for future use. An attempt to execute it
1139 * causes a Reserved Instruction exception.
1140 * % This code indicates an instruction class. The instruction word
1141 * must be further decoded by examining additional tables that show
1142 * the values for other instruction fields.
1143 * # This code is reserved for the unsupported instructions DMULT,
1144 * DMULTU, DDIV, DDIVU, LL, LLD, SC, SCD, LWC2 and SWC2. An attempt
1145 * to execute it causes a Reserved Instruction exception.
1146 *
1147 * MMI instructions encoded by opcode field (MMI, LQ, SQ):
1148 *
1149 * 31 26 0
1150 * +--------+----------------------------------------+
1151 * | opcode | |
1152 * +--------+----------------------------------------+
1153 *
1154 * opcode bits 28..26
1155 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
1156 * 31..29 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
1157 * -------+-------+-------+-------+-------+-------+-------+-------+-------
1158 * 0 000 |SPECIAL| REGIMM| J | JAL | BEQ | BNE | BLEZ | BGTZ
1159 * 1 001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI
1160 * 2 010 | COP0 | COP1 | * | * | BEQL | BNEL | BLEZL | BGTZL
1161 * 3 011 | DADDI | DADDIU| LDL | LDR | MMI% | * | LQ | SQ
1162 * 4 100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU
1163 * 5 101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE
1164 * 6 110 | # | LWC1 | # | PREF | # | LDC1 | # | LD
1165 * 7 111 | # | SWC1 | # | * | # | SDC1 | # | SD
1166 */
1167
1168 enum {
1169 MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */
1170 MMI_OPC_LQ = 0x1E << 26, /* Same as OPC_MSA */
1171 MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
1172 };
1173
1174 /*
1175 * MMI instructions with opcode field = MMI:
1176 *
1177 * 31 26 5 0
1178 * +--------+-------------------------------+--------+
1179 * | MMI | |function|
1180 * +--------+-------------------------------+--------+
1181 *
1182 * function bits 2..0
1183 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
1184 * 5..3 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
1185 * -------+-------+-------+-------+-------+-------+-------+-------+-------
1186 * 0 000 | MADD | MADDU | * | * | PLZCW | * | * | *
1187 * 1 001 | MMI0% | MMI2% | * | * | * | * | * | *
1188 * 2 010 | MFHI1 | MTHI1 | MFLO1 | MTLO1 | * | * | * | *
1189 * 3 011 | MULT1 | MULTU1| DIV1 | DIVU1 | * | * | * | *
1190 * 4 100 | MADD1 | MADDU1| * | * | * | * | * | *
1191 * 5 101 | MMI1% | MMI3% | * | * | * | * | * | *
1192 * 6 110 | PMFHL | PMTHL | * | * | PSLLH | * | PSRLH | PSRAH
1193 * 7 111 | * | * | * | * | PSLLW | * | PSRLW | PSRAW
1194 */
1195
1196 #define MASK_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F))
1197 enum {
1198 MMI_OPC_MADD = 0x00 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADD */
1199 MMI_OPC_MADDU = 0x01 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADDU */
1200 MMI_OPC_MULT1 = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */
1201 MMI_OPC_MULTU1 = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */
1202 MMI_OPC_DIV1 = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV */
1203 MMI_OPC_DIVU1 = 0x1B | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIVU */
1204 MMI_OPC_MADD1 = 0x20 | MMI_OPC_CLASS_MMI,
1205 MMI_OPC_MADDU1 = 0x21 | MMI_OPC_CLASS_MMI,
1206 };
1207
1208 /* global register indices */
1209 TCGv cpu_gpr[32], cpu_PC;
1210 /*
1211 * For CPUs using 128-bit GPR registers, we put the lower halves in cpu_gpr[])
1212 * and the upper halves in cpu_gpr_hi[].
1213 */
1214 TCGv_i64 cpu_gpr_hi[32];
1215 TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
1216 static TCGv cpu_dspctrl, btarget;
1217 TCGv bcond;
1218 static TCGv cpu_lladdr, cpu_llval;
1219 static TCGv_i32 hflags;
1220 TCGv_i32 fpu_fcr0, fpu_fcr31;
1221 TCGv_i64 fpu_f64[32];
1222
1223 #include "exec/gen-icount.h"
1224
1225 #define gen_helper_0e0i(name, arg) do { \
1226 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
1227 gen_helper_##name(cpu_env, helper_tmp); \
1228 tcg_temp_free_i32(helper_tmp); \
1229 } while (0)
1230
1231 #define gen_helper_0e1i(name, arg1, arg2) do { \
1232 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
1233 gen_helper_##name(cpu_env, arg1, helper_tmp); \
1234 tcg_temp_free_i32(helper_tmp); \
1235 } while (0)
1236
1237 #define gen_helper_1e0i(name, ret, arg1) do { \
1238 TCGv_i32 helper_tmp = tcg_const_i32(arg1); \
1239 gen_helper_##name(ret, cpu_env, helper_tmp); \
1240 tcg_temp_free_i32(helper_tmp); \
1241 } while (0)
1242
1243 #define gen_helper_1e1i(name, ret, arg1, arg2) do { \
1244 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
1245 gen_helper_##name(ret, cpu_env, arg1, helper_tmp); \
1246 tcg_temp_free_i32(helper_tmp); \
1247 } while (0)
1248
1249 #define gen_helper_0e2i(name, arg1, arg2, arg3) do { \
1250 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
1251 gen_helper_##name(cpu_env, arg1, arg2, helper_tmp); \
1252 tcg_temp_free_i32(helper_tmp); \
1253 } while (0)
1254
1255 #define gen_helper_1e2i(name, ret, arg1, arg2, arg3) do { \
1256 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
1257 gen_helper_##name(ret, cpu_env, arg1, arg2, helper_tmp); \
1258 tcg_temp_free_i32(helper_tmp); \
1259 } while (0)
1260
1261 #define gen_helper_0e3i(name, arg1, arg2, arg3, arg4) do { \
1262 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
1263 gen_helper_##name(cpu_env, arg1, arg2, arg3, helper_tmp); \
1264 tcg_temp_free_i32(helper_tmp); \
1265 } while (0)
1266
1267 #define DISAS_STOP DISAS_TARGET_0
1268 #define DISAS_EXIT DISAS_TARGET_1
1269
1270 static const char * const regnames[] = {
1271 "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
1272 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
1273 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1274 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
1275 };
1276
1277 static const char * const regnames_HI[] = {
1278 "HI0", "HI1", "HI2", "HI3",
1279 };
1280
1281 static const char * const regnames_LO[] = {
1282 "LO0", "LO1", "LO2", "LO3",
1283 };
1284
1285 static const char * const fregnames[] = {
1286 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1287 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1288 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1289 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1290 };
1291
1292 /* General purpose registers moves. */
1293 void gen_load_gpr(TCGv t, int reg)
1294 {
1295 if (reg == 0) {
1296 tcg_gen_movi_tl(t, 0);
1297 } else {
1298 tcg_gen_mov_tl(t, cpu_gpr[reg]);
1299 }
1300 }
1301
1302 void gen_store_gpr(TCGv t, int reg)
1303 {
1304 if (reg != 0) {
1305 tcg_gen_mov_tl(cpu_gpr[reg], t);
1306 }
1307 }
1308
1309 #if defined(TARGET_MIPS64)
1310 void gen_load_gpr_hi(TCGv_i64 t, int reg)
1311 {
1312 if (reg == 0) {
1313 tcg_gen_movi_i64(t, 0);
1314 } else {
1315 tcg_gen_mov_i64(t, cpu_gpr_hi[reg]);
1316 }
1317 }
1318
1319 void gen_store_gpr_hi(TCGv_i64 t, int reg)
1320 {
1321 if (reg != 0) {
1322 tcg_gen_mov_i64(cpu_gpr_hi[reg], t);
1323 }
1324 }
1325 #endif /* TARGET_MIPS64 */
1326
1327 /* Moves to/from shadow registers. */
1328 static inline void gen_load_srsgpr(int from, int to)
1329 {
1330 TCGv t0 = tcg_temp_new();
1331
1332 if (from == 0) {
1333 tcg_gen_movi_tl(t0, 0);
1334 } else {
1335 TCGv_i32 t2 = tcg_temp_new_i32();
1336 TCGv_ptr addr = tcg_temp_new_ptr();
1337
1338 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
1339 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
1340 tcg_gen_andi_i32(t2, t2, 0xf);
1341 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
1342 tcg_gen_ext_i32_ptr(addr, t2);
1343 tcg_gen_add_ptr(addr, cpu_env, addr);
1344
1345 tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
1346 tcg_temp_free_ptr(addr);
1347 tcg_temp_free_i32(t2);
1348 }
1349 gen_store_gpr(t0, to);
1350 tcg_temp_free(t0);
1351 }
1352
1353 static inline void gen_store_srsgpr(int from, int to)
1354 {
1355 if (to != 0) {
1356 TCGv t0 = tcg_temp_new();
1357 TCGv_i32 t2 = tcg_temp_new_i32();
1358 TCGv_ptr addr = tcg_temp_new_ptr();
1359
1360 gen_load_gpr(t0, from);
1361 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
1362 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
1363 tcg_gen_andi_i32(t2, t2, 0xf);
1364 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
1365 tcg_gen_ext_i32_ptr(addr, t2);
1366 tcg_gen_add_ptr(addr, cpu_env, addr);
1367
1368 tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
1369 tcg_temp_free_ptr(addr);
1370 tcg_temp_free_i32(t2);
1371 tcg_temp_free(t0);
1372 }
1373 }
1374
1375 /* Tests */
1376 static inline void gen_save_pc(target_ulong pc)
1377 {
1378 tcg_gen_movi_tl(cpu_PC, pc);
1379 }
1380
1381 static inline void save_cpu_state(DisasContext *ctx, int do_save_pc)
1382 {
1383 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
1384 if (do_save_pc && ctx->base.pc_next != ctx->saved_pc) {
1385 gen_save_pc(ctx->base.pc_next);
1386 ctx->saved_pc = ctx->base.pc_next;
1387 }
1388 if (ctx->hflags != ctx->saved_hflags) {
1389 tcg_gen_movi_i32(hflags, ctx->hflags);
1390 ctx->saved_hflags = ctx->hflags;
1391 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
1392 case MIPS_HFLAG_BR:
1393 break;
1394 case MIPS_HFLAG_BC:
1395 case MIPS_HFLAG_BL:
1396 case MIPS_HFLAG_B:
1397 tcg_gen_movi_tl(btarget, ctx->btarget);
1398 break;
1399 }
1400 }
1401 }
1402
1403 static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx)
1404 {
1405 ctx->saved_hflags = ctx->hflags;
1406 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
1407 case MIPS_HFLAG_BR:
1408 break;
1409 case MIPS_HFLAG_BC:
1410 case MIPS_HFLAG_BL:
1411 case MIPS_HFLAG_B:
1412 ctx->btarget = env->btarget;
1413 break;
1414 }
1415 }
1416
1417 void generate_exception_err(DisasContext *ctx, int excp, int err)
1418 {
1419 TCGv_i32 texcp = tcg_const_i32(excp);
1420 TCGv_i32 terr = tcg_const_i32(err);
1421 save_cpu_state(ctx, 1);
1422 gen_helper_raise_exception_err(cpu_env, texcp, terr);
1423 tcg_temp_free_i32(terr);
1424 tcg_temp_free_i32(texcp);
1425 ctx->base.is_jmp = DISAS_NORETURN;
1426 }
1427
1428 void generate_exception(DisasContext *ctx, int excp)
1429 {
1430 gen_helper_0e0i(raise_exception, excp);
1431 }
1432
1433 void generate_exception_end(DisasContext *ctx, int excp)
1434 {
1435 generate_exception_err(ctx, excp, 0);
1436 }
1437
1438 void gen_reserved_instruction(DisasContext *ctx)
1439 {
1440 generate_exception_end(ctx, EXCP_RI);
1441 }
1442
1443 /* Floating point register moves. */
1444 void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
1445 {
1446 if (ctx->hflags & MIPS_HFLAG_FRE) {
1447 generate_exception(ctx, EXCP_RI);
1448 }
1449 tcg_gen_extrl_i64_i32(t, fpu_f64[reg]);
1450 }
1451
1452 void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
1453 {
1454 TCGv_i64 t64;
1455 if (ctx->hflags & MIPS_HFLAG_FRE) {
1456 generate_exception(ctx, EXCP_RI);
1457 }
1458 t64 = tcg_temp_new_i64();
1459 tcg_gen_extu_i32_i64(t64, t);
1460 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32);
1461 tcg_temp_free_i64(t64);
1462 }
1463
1464 static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
1465 {
1466 if (ctx->hflags & MIPS_HFLAG_F64) {
1467 tcg_gen_extrh_i64_i32(t, fpu_f64[reg]);
1468 } else {
1469 gen_load_fpr32(ctx, t, reg | 1);
1470 }
1471 }
1472
1473 static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
1474 {
1475 if (ctx->hflags & MIPS_HFLAG_F64) {
1476 TCGv_i64 t64 = tcg_temp_new_i64();
1477 tcg_gen_extu_i32_i64(t64, t);
1478 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32);
1479 tcg_temp_free_i64(t64);
1480 } else {
1481 gen_store_fpr32(ctx, t, reg | 1);
1482 }
1483 }
1484
1485 void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
1486 {
1487 if (ctx->hflags & MIPS_HFLAG_F64) {
1488 tcg_gen_mov_i64(t, fpu_f64[reg]);
1489 } else {
1490 tcg_gen_concat32_i64(t, fpu_f64[reg & ~1], fpu_f64[reg | 1]);
1491 }
1492 }
1493
1494 void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
1495 {
1496 if (ctx->hflags & MIPS_HFLAG_F64) {
1497 tcg_gen_mov_i64(fpu_f64[reg], t);
1498 } else {
1499 TCGv_i64 t0;
1500 tcg_gen_deposit_i64(fpu_f64[reg & ~1], fpu_f64[reg & ~1], t, 0, 32);
1501 t0 = tcg_temp_new_i64();
1502 tcg_gen_shri_i64(t0, t, 32);
1503 tcg_gen_deposit_i64(fpu_f64[reg | 1], fpu_f64[reg | 1], t0, 0, 32);
1504 tcg_temp_free_i64(t0);
1505 }
1506 }
1507
1508 int get_fp_bit(int cc)
1509 {
1510 if (cc) {
1511 return 24 + cc;
1512 } else {
1513 return 23;
1514 }
1515 }
1516
1517 /* Addresses computation */
1518 void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
1519 {
1520 tcg_gen_add_tl(ret, arg0, arg1);
1521
1522 #if defined(TARGET_MIPS64)
1523 if (ctx->hflags & MIPS_HFLAG_AWRAP) {
1524 tcg_gen_ext32s_i64(ret, ret);
1525 }
1526 #endif
1527 }
1528
1529 static inline void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base,
1530 target_long ofs)
1531 {
1532 tcg_gen_addi_tl(ret, base, ofs);
1533
1534 #if defined(TARGET_MIPS64)
1535 if (ctx->hflags & MIPS_HFLAG_AWRAP) {
1536 tcg_gen_ext32s_i64(ret, ret);
1537 }
1538 #endif
1539 }
1540
1541 /* Addresses computation (translation time) */
1542 static target_long addr_add(DisasContext *ctx, target_long base,
1543 target_long offset)
1544 {
1545 target_long sum = base + offset;
1546
1547 #if defined(TARGET_MIPS64)
1548 if (ctx->hflags & MIPS_HFLAG_AWRAP) {
1549 sum = (int32_t)sum;
1550 }
1551 #endif
1552 return sum;
1553 }
1554
1555 /* Sign-extract the low 32-bits to a target_long. */
1556 void gen_move_low32(TCGv ret, TCGv_i64 arg)
1557 {
1558 #if defined(TARGET_MIPS64)
1559 tcg_gen_ext32s_i64(ret, arg);
1560 #else
1561 tcg_gen_extrl_i64_i32(ret, arg);
1562 #endif
1563 }
1564
1565 /* Sign-extract the high 32-bits to a target_long. */
1566 void gen_move_high32(TCGv ret, TCGv_i64 arg)
1567 {
1568 #if defined(TARGET_MIPS64)
1569 tcg_gen_sari_i64(ret, arg, 32);
1570 #else
1571 tcg_gen_extrh_i64_i32(ret, arg);
1572 #endif
1573 }
1574
1575 void check_cp0_enabled(DisasContext *ctx)
1576 {
1577 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
1578 generate_exception_end(ctx, EXCP_CpU);
1579 }
1580 }
1581
1582 void check_cp1_enabled(DisasContext *ctx)
1583 {
1584 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {
1585 generate_exception_err(ctx, EXCP_CpU, 1);
1586 }
1587 }
1588
1589 /*
1590 * Verify that the processor is running with COP1X instructions enabled.
1591 * This is associated with the nabla symbol in the MIPS32 and MIPS64
1592 * opcode tables.
1593 */
1594 void check_cop1x(DisasContext *ctx)
1595 {
1596 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) {
1597 gen_reserved_instruction(ctx);
1598 }
1599 }
1600
1601 /*
1602 * Verify that the processor is running with 64-bit floating-point
1603 * operations enabled.
1604 */
1605 void check_cp1_64bitmode(DisasContext *ctx)
1606 {
1607 if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) {
1608 gen_reserved_instruction(ctx);
1609 }
1610 }
1611
1612 /*
1613 * Verify if floating point register is valid; an operation is not defined
1614 * if bit 0 of any register specification is set and the FR bit in the
1615 * Status register equals zero, since the register numbers specify an
1616 * even-odd pair of adjacent coprocessor general registers. When the FR bit
1617 * in the Status register equals one, both even and odd register numbers
1618 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
1619 *
1620 * Multiple 64 bit wide registers can be checked by calling
1621 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
1622 */
1623 void check_cp1_registers(DisasContext *ctx, int regs)
1624 {
1625 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) {
1626 gen_reserved_instruction(ctx);
1627 }
1628 }
1629
1630 /*
1631 * Verify that the processor is running with DSP instructions enabled.
1632 * This is enabled by CP0 Status register MX(24) bit.
1633 */
1634 static inline void check_dsp(DisasContext *ctx)
1635 {
1636 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) {
1637 if (ctx->insn_flags & ASE_DSP) {
1638 generate_exception_end(ctx, EXCP_DSPDIS);
1639 } else {
1640 gen_reserved_instruction(ctx);
1641 }
1642 }
1643 }
1644
1645 static inline void check_dsp_r2(DisasContext *ctx)
1646 {
1647 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R2))) {
1648 if (ctx->insn_flags & ASE_DSP) {
1649 generate_exception_end(ctx, EXCP_DSPDIS);
1650 } else {
1651 gen_reserved_instruction(ctx);
1652 }
1653 }
1654 }
1655
1656 static inline void check_dsp_r3(DisasContext *ctx)
1657 {
1658 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R3))) {
1659 if (ctx->insn_flags & ASE_DSP) {
1660 generate_exception_end(ctx, EXCP_DSPDIS);
1661 } else {
1662 gen_reserved_instruction(ctx);
1663 }
1664 }
1665 }
1666
1667 /*
1668 * This code generates a "reserved instruction" exception if the
1669 * CPU does not support the instruction set corresponding to flags.
1670 */
1671 void check_insn(DisasContext *ctx, uint64_t flags)
1672 {
1673 if (unlikely(!(ctx->insn_flags & flags))) {
1674 gen_reserved_instruction(ctx);
1675 }
1676 }
1677
1678 /*
1679 * This code generates a "reserved instruction" exception if the
1680 * CPU has corresponding flag set which indicates that the instruction
1681 * has been removed.
1682 */
1683 static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
1684 {
1685 if (unlikely(ctx->insn_flags & flags)) {
1686 gen_reserved_instruction(ctx);
1687 }
1688 }
1689
1690 /*
1691 * The Linux kernel traps certain reserved instruction exceptions to
1692 * emulate the corresponding instructions. QEMU is the kernel in user
1693 * mode, so those traps are emulated by accepting the instructions.
1694 *
1695 * A reserved instruction exception is generated for flagged CPUs if
1696 * QEMU runs in system mode.
1697 */
1698 static inline void check_insn_opc_user_only(DisasContext *ctx, uint64_t flags)
1699 {
1700 #ifndef CONFIG_USER_ONLY
1701 check_insn_opc_removed(ctx, flags);
1702 #endif
1703 }
1704
1705 /*
1706 * This code generates a "reserved instruction" exception if the
1707 * CPU does not support 64-bit paired-single (PS) floating point data type.
1708 */
1709 static inline void check_ps(DisasContext *ctx)
1710 {
1711 if (unlikely(!ctx->ps)) {
1712 generate_exception(ctx, EXCP_RI);
1713 }
1714 check_cp1_64bitmode(ctx);
1715 }
1716
1717 /*
1718 * This code generates a "reserved instruction" exception if cpu is not
1719 * 64-bit or 64-bit instructions are not enabled.
1720 */
1721 void check_mips_64(DisasContext *ctx)
1722 {
1723 if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) {
1724 gen_reserved_instruction(ctx);
1725 }
1726 }
1727
1728 #ifndef CONFIG_USER_ONLY
1729 static inline void check_mvh(DisasContext *ctx)
1730 {
1731 if (unlikely(!ctx->mvh)) {
1732 generate_exception(ctx, EXCP_RI);
1733 }
1734 }
1735 #endif
1736
1737 /*
1738 * This code generates a "reserved instruction" exception if the
1739 * Config5 XNP bit is set.
1740 */
1741 static inline void check_xnp(DisasContext *ctx)
1742 {
1743 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) {
1744 gen_reserved_instruction(ctx);
1745 }
1746 }
1747
1748 #ifndef CONFIG_USER_ONLY
1749 /*
1750 * This code generates a "reserved instruction" exception if the
1751 * Config3 PW bit is NOT set.
1752 */
1753 static inline void check_pw(DisasContext *ctx)
1754 {
1755 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) {
1756 gen_reserved_instruction(ctx);
1757 }
1758 }
1759 #endif
1760
1761 /*
1762 * This code generates a "reserved instruction" exception if the
1763 * Config3 MT bit is NOT set.
1764 */
1765 static inline void check_mt(DisasContext *ctx)
1766 {
1767 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
1768 gen_reserved_instruction(ctx);
1769 }
1770 }
1771
1772 #ifndef CONFIG_USER_ONLY
1773 /*
1774 * This code generates a "coprocessor unusable" exception if CP0 is not
1775 * available, and, if that is not the case, generates a "reserved instruction"
1776 * exception if the Config5 MT bit is NOT set. This is needed for availability
1777 * control of some of MT ASE instructions.
1778 */
1779 static inline void check_cp0_mt(DisasContext *ctx)
1780 {
1781 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
1782 generate_exception_end(ctx, EXCP_CpU);
1783 } else {
1784 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
1785 gen_reserved_instruction(ctx);
1786 }
1787 }
1788 }
1789 #endif
1790
1791 /*
1792 * This code generates a "reserved instruction" exception if the
1793 * Config5 NMS bit is set.
1794 */
1795 static inline void check_nms(DisasContext *ctx)
1796 {
1797 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) {
1798 gen_reserved_instruction(ctx);
1799 }
1800 }
1801
1802 /*
1803 * This code generates a "reserved instruction" exception if the
1804 * Config5 NMS bit is set, and Config1 DL, Config1 IL, Config2 SL,
1805 * Config2 TL, and Config5 L2C are unset.
1806 */
1807 static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
1808 {
1809 if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) &&
1810 !(ctx->CP0_Config1 & (1 << CP0C1_DL)) &&
1811 !(ctx->CP0_Config1 & (1 << CP0C1_IL)) &&
1812 !(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
1813 !(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
1814 !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) {
1815 gen_reserved_instruction(ctx);
1816 }
1817 }
1818
1819 /*
1820 * This code generates a "reserved instruction" exception if the
1821 * Config5 EVA bit is NOT set.
1822 */
1823 static inline void check_eva(DisasContext *ctx)
1824 {
1825 if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) {
1826 gen_reserved_instruction(ctx);
1827 }
1828 }
1829
1830
1831 /*
1832 * Define small wrappers for gen_load_fpr* so that we have a uniform
1833 * calling interface for 32 and 64-bit FPRs. No sense in changing
1834 * all callers for gen_load_fpr32 when we need the CTX parameter for
1835 * this one use.
1836 */
1837 #define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(ctx, x, y)
1838 #define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y)
1839 #define FOP_CONDS(type, abs, fmt, ifmt, bits) \
1840 static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
1841 int ft, int fs, int cc) \
1842 { \
1843 TCGv_i##bits fp0 = tcg_temp_new_i##bits(); \
1844 TCGv_i##bits fp1 = tcg_temp_new_i##bits(); \
1845 switch (ifmt) { \
1846 case FMT_PS: \
1847 check_ps(ctx); \
1848 break; \
1849 case FMT_D: \
1850 if (abs) { \
1851 check_cop1x(ctx); \
1852 } \
1853 check_cp1_registers(ctx, fs | ft); \
1854 break; \
1855 case FMT_S: \
1856 if (abs) { \
1857 check_cop1x(ctx); \
1858 } \
1859 break; \
1860 } \
1861 gen_ldcmp_fpr##bits(ctx, fp0, fs); \
1862 gen_ldcmp_fpr##bits(ctx, fp1, ft); \
1863 switch (n) { \
1864 case 0: \
1865 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); \
1866 break; \
1867 case 1: \
1868 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); \
1869 break; \
1870 case 2: \
1871 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); \
1872 break; \
1873 case 3: \
1874 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); \
1875 break; \
1876 case 4: \
1877 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); \
1878 break; \
1879 case 5: \
1880 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); \
1881 break; \
1882 case 6: \
1883 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); \
1884 break; \
1885 case 7: \
1886 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); \
1887 break; \
1888 case 8: \
1889 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); \
1890 break; \
1891 case 9: \
1892 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); \
1893 break; \
1894 case 10: \
1895 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); \
1896 break; \
1897 case 11: \
1898 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); \
1899 break; \
1900 case 12: \
1901 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); \
1902 break; \
1903 case 13: \
1904 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); \
1905 break; \
1906 case 14: \
1907 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); \
1908 break; \
1909 case 15: \
1910 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); \
1911 break; \
1912 default: \
1913 abort(); \
1914 } \
1915 tcg_temp_free_i##bits(fp0); \
1916 tcg_temp_free_i##bits(fp1); \
1917 }
1918
1919 FOP_CONDS(, 0, d, FMT_D, 64)
1920 FOP_CONDS(abs, 1, d, FMT_D, 64)
1921 FOP_CONDS(, 0, s, FMT_S, 32)
1922 FOP_CONDS(abs, 1, s, FMT_S, 32)
1923 FOP_CONDS(, 0, ps, FMT_PS, 64)
1924 FOP_CONDS(abs, 1, ps, FMT_PS, 64)
1925 #undef FOP_CONDS
1926
1927 #define FOP_CONDNS(fmt, ifmt, bits, STORE) \
1928 static inline void gen_r6_cmp_ ## fmt(DisasContext *ctx, int n, \
1929 int ft, int fs, int fd) \
1930 { \
1931 TCGv_i ## bits fp0 = tcg_temp_new_i ## bits(); \
1932 TCGv_i ## bits fp1 = tcg_temp_new_i ## bits(); \
1933 if (ifmt == FMT_D) { \
1934 check_cp1_registers(ctx, fs | ft | fd); \
1935 } \
1936 gen_ldcmp_fpr ## bits(ctx, fp0, fs); \
1937 gen_ldcmp_fpr ## bits(ctx, fp1, ft); \
1938 switch (n) { \
1939 case 0: \
1940 gen_helper_r6_cmp_ ## fmt ## _af(fp0, cpu_env, fp0, fp1); \
1941 break; \
1942 case 1: \
1943 gen_helper_r6_cmp_ ## fmt ## _un(fp0, cpu_env, fp0, fp1); \
1944 break; \
1945 case 2: \
1946 gen_helper_r6_cmp_ ## fmt ## _eq(fp0, cpu_env, fp0, fp1); \
1947 break; \
1948 case 3: \
1949 gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, cpu_env, fp0, fp1); \
1950 break; \
1951 case 4: \
1952 gen_helper_r6_cmp_ ## fmt ## _lt(fp0, cpu_env, fp0, fp1); \
1953 break; \
1954 case 5: \
1955 gen_helper_r6_cmp_ ## fmt ## _ult(fp0, cpu_env, fp0, fp1); \
1956 break; \
1957 case 6: \
1958 gen_helper_r6_cmp_ ## fmt ## _le(fp0, cpu_env, fp0, fp1); \
1959 break; \
1960 case 7: \
1961 gen_helper_r6_cmp_ ## fmt ## _ule(fp0, cpu_env, fp0, fp1); \
1962 break; \
1963 case 8: \
1964 gen_helper_r6_cmp_ ## fmt ## _saf(fp0, cpu_env, fp0, fp1); \
1965 break; \
1966 case 9: \
1967 gen_helper_r6_cmp_ ## fmt ## _sun(fp0, cpu_env, fp0, fp1); \
1968 break; \
1969 case 10: \
1970 gen_helper_r6_cmp_ ## fmt ## _seq(fp0, cpu_env, fp0, fp1); \
1971 break; \
1972 case 11: \
1973 gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, cpu_env, fp0, fp1); \
1974 break; \
1975 case 12: \
1976 gen_helper_r6_cmp_ ## fmt ## _slt(fp0, cpu_env, fp0, fp1); \
1977 break; \
1978 case 13: \
1979 gen_helper_r6_cmp_ ## fmt ## _sult(fp0, cpu_env, fp0, fp1); \
1980 break; \
1981 case 14: \
1982 gen_helper_r6_cmp_ ## fmt ## _sle(fp0, cpu_env, fp0, fp1); \
1983 break; \
1984 case 15: \
1985 gen_helper_r6_cmp_ ## fmt ## _sule(fp0, cpu_env, fp0, fp1); \
1986 break; \
1987 case 17: \
1988 gen_helper_r6_cmp_ ## fmt ## _or(fp0, cpu_env, fp0, fp1); \
1989 break; \
1990 case 18: \
1991 gen_helper_r6_cmp_ ## fmt ## _une(fp0, cpu_env, fp0, fp1); \
1992 break; \
1993 case 19: \
1994 gen_helper_r6_cmp_ ## fmt ## _ne(fp0, cpu_env, fp0, fp1); \
1995 break; \
1996 case 25: \
1997 gen_helper_r6_cmp_ ## fmt ## _sor(fp0, cpu_env, fp0, fp1); \
1998 break; \
1999 case 26: \
2000 gen_helper_r6_cmp_ ## fmt ## _sune(fp0, cpu_env, fp0, fp1); \
2001 break; \
2002 case 27: \
2003 gen_helper_r6_cmp_ ## fmt ## _sne(fp0, cpu_env, fp0, fp1); \
2004 break; \
2005 default: \
2006 abort(); \
2007 } \
2008 STORE; \
2009 tcg_temp_free_i ## bits(fp0); \
2010 tcg_temp_free_i ## bits(fp1); \
2011 }
2012
2013 FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd))
2014 FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd))
2015 #undef FOP_CONDNS
2016 #undef gen_ldcmp_fpr32
2017 #undef gen_ldcmp_fpr64
2018
2019 /* load/store instructions. */
2020 #ifdef CONFIG_USER_ONLY
2021 #define OP_LD_ATOMIC(insn, fname) \
2022 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
2023 DisasContext *ctx) \
2024 { \
2025 TCGv t0 = tcg_temp_new(); \
2026 tcg_gen_mov_tl(t0, arg1); \
2027 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
2028 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
2029 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \
2030 tcg_temp_free(t0); \
2031 }
2032 #else
2033 #define OP_LD_ATOMIC(insn, fname) \
2034 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
2035 DisasContext *ctx) \
2036 { \
2037 gen_helper_1e1i(insn, ret, arg1, mem_idx); \
2038 }
2039 #endif
2040 OP_LD_ATOMIC(ll, ld32s);
2041 #if defined(TARGET_MIPS64)
2042 OP_LD_ATOMIC(lld, ld64);
2043 #endif
2044 #undef OP_LD_ATOMIC
2045
2046 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset)
2047 {
2048 if (base == 0) {
2049 tcg_gen_movi_tl(addr, offset);
2050 } else if (offset == 0) {
2051 gen_load_gpr(addr, base);
2052 } else {
2053 tcg_gen_movi_tl(addr, offset);
2054 gen_op_addr_add(ctx, addr, cpu_gpr[base], addr);
2055 }
2056 }
2057
2058 static target_ulong pc_relative_pc(DisasContext *ctx)
2059 {
2060 target_ulong pc = ctx->base.pc_next;
2061
2062 if (ctx->hflags & MIPS_HFLAG_BMASK) {
2063 int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4;
2064
2065 pc -= branch_bytes;
2066 }
2067
2068 pc &= ~(target_ulong)3;
2069 return pc;
2070 }
2071
2072 /* Load */
2073 static void gen_ld(DisasContext *ctx, uint32_t opc,
2074 int rt, int base, int offset)
2075 {
2076 TCGv t0, t1, t2;
2077 int mem_idx = ctx->mem_idx;
2078
2079 if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F |
2080 INSN_LOONGSON3A)) {
2081 /*
2082 * Loongson CPU uses a load to zero register for prefetch.
2083 * We emulate it as a NOP. On other CPU we must perform the
2084 * actual memory access.
2085 */
2086 return;
2087 }
2088
2089 t0 = tcg_temp_new();
2090 gen_base_offset_addr(ctx, t0, base, offset);
2091
2092 switch (opc) {
2093 #if defined(TARGET_MIPS64)
2094 case OPC_LWU:
2095 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL |
2096 ctx->default_tcg_memop_mask);
2097 gen_store_gpr(t0, rt);
2098 break;
2099 case OPC_LD:
2100 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEQ |
2101 ctx->default_tcg_memop_mask);
2102 gen_store_gpr(t0, rt);
2103 break;
2104 case OPC_LLD:
2105 case R6_OPC_LLD:
2106 op_ld_lld(t0, t0, mem_idx, ctx);
2107 gen_store_gpr(t0, rt);
2108 break;
2109 case OPC_LDL:
2110 t1 = tcg_temp_new();
2111 /*
2112 * Do a byte access to possibly trigger a page
2113 * fault with the unaligned address.
2114 */
2115 tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
2116 tcg_gen_andi_tl(t1, t0, 7);
2117 #ifndef TARGET_WORDS_BIGENDIAN
2118 tcg_gen_xori_tl(t1, t1, 7);
2119 #endif
2120 tcg_gen_shli_tl(t1, t1, 3);
2121 tcg_gen_andi_tl(t0, t0, ~7);
2122 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEQ);
2123 tcg_gen_shl_tl(t0, t0, t1);
2124 t2 = tcg_const_tl(-1);
2125 tcg_gen_shl_tl(t2, t2, t1);
2126 gen_load_gpr(t1, rt);
2127 tcg_gen_andc_tl(t1, t1, t2);
2128 tcg_temp_free(t2);
2129 tcg_gen_or_tl(t0, t0, t1);
2130 tcg_temp_free(t1);
2131 gen_store_gpr(t0, rt);
2132 break;
2133 case OPC_LDR:
2134 t1 = tcg_temp_new();
2135 /*
2136 * Do a byte access to possibly trigger a page
2137 * fault with the unaligned address.
2138 */
2139 tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
2140 tcg_gen_andi_tl(t1, t0, 7);
2141 #ifdef TARGET_WORDS_BIGENDIAN
2142 tcg_gen_xori_tl(t1, t1, 7);
2143 #endif
2144 tcg_gen_shli_tl(t1, t1, 3);
2145 tcg_gen_andi_tl(t0, t0, ~7);
2146 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEQ);
2147 tcg_gen_shr_tl(t0, t0, t1);
2148 tcg_gen_xori_tl(t1, t1, 63);
2149 t2 = tcg_const_tl(0xfffffffffffffffeull);
2150 tcg_gen_shl_tl(t2, t2, t1);
2151 gen_load_gpr(t1, rt);
2152 tcg_gen_and_tl(t1, t1, t2);
2153 tcg_temp_free(t2);
2154 tcg_gen_or_tl(t0, t0, t1);
2155 tcg_temp_free(t1);
2156 gen_store_gpr(t0, rt);
2157 break;
2158 case OPC_LDPC:
2159 t1 = tcg_const_tl(pc_relative_pc(ctx));
2160 gen_op_addr_add(ctx, t0, t0, t1);
2161 tcg_temp_free(t1);
2162 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEQ);
2163 gen_store_gpr(t0, rt);
2164 break;
2165 #endif
2166 case OPC_LWPC:
2167 t1 = tcg_const_tl(pc_relative_pc(ctx));
2168 gen_op_addr_add(ctx, t0, t0, t1);
2169 tcg_temp_free(t1);
2170 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL);
2171 gen_store_gpr(t0, rt);
2172 break;
2173 case OPC_LWE:
2174 mem_idx = MIPS_HFLAG_UM;
2175 /* fall through */
2176 case OPC_LW:
2177 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL |
2178 ctx->default_tcg_memop_mask);
2179 gen_store_gpr(t0, rt);
2180 break;
2181 case OPC_LHE:
2182 mem_idx = MIPS_HFLAG_UM;
2183 /* fall through */
2184 case OPC_LH:
2185 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESW |
2186 ctx->default_tcg_memop_mask);
2187 gen_store_gpr(t0, rt);
2188 break;
2189 case OPC_LHUE:
2190 mem_idx = MIPS_HFLAG_UM;
2191 /* fall through */
2192 case OPC_LHU:
2193 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUW |
2194 ctx->default_tcg_memop_mask);
2195 gen_store_gpr(t0, rt);
2196 break;
2197 case OPC_LBE:
2198 mem_idx = MIPS_HFLAG_UM;
2199 /* fall through */
2200 case OPC_LB:
2201 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_SB);
2202 gen_store_gpr(t0, rt);
2203 break;
2204 case OPC_LBUE:
2205 mem_idx = MIPS_HFLAG_UM;
2206 /* fall through */
2207 case OPC_LBU:
2208 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_UB);
2209 gen_store_gpr(t0, rt);
2210 break;
2211 case OPC_LWLE:
2212 mem_idx = MIPS_HFLAG_UM;
2213 /* fall through */
2214 case OPC_LWL:
2215 t1 = tcg_temp_new();
2216 /*
2217 * Do a byte access to possibly trigger a page
2218 * fault with the unaligned address.
2219 */
2220 tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
2221 tcg_gen_andi_tl(t1, t0, 3);
2222 #ifndef TARGET_WORDS_BIGENDIAN
2223 tcg_gen_xori_tl(t1, t1, 3);
2224 #endif
2225 tcg_gen_shli_tl(t1, t1, 3);
2226 tcg_gen_andi_tl(t0, t0, ~3);
2227 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL);
2228 tcg_gen_shl_tl(t0, t0, t1);
2229 t2 = tcg_const_tl(-1);
2230 tcg_gen_shl_tl(t2, t2, t1);
2231 gen_load_gpr(t1, rt);
2232 tcg_gen_andc_tl(t1, t1, t2);
2233 tcg_temp_free(t2);
2234 tcg_gen_or_tl(t0, t0, t1);
2235 tcg_temp_free(t1);
2236 tcg_gen_ext32s_tl(t0, t0);
2237 gen_store_gpr(t0, rt);
2238 break;
2239 case OPC_LWRE:
2240 mem_idx = MIPS_HFLAG_UM;
2241 /* fall through */
2242 case OPC_LWR:
2243 t1 = tcg_temp_new();
2244 /*
2245 * Do a byte access to possibly trigger a page
2246 * fault with the unaligned address.
2247 */
2248 tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
2249 tcg_gen_andi_tl(t1, t0, 3);
2250 #ifdef TARGET_WORDS_BIGENDIAN
2251 tcg_gen_xori_tl(t1, t1, 3);
2252 #endif
2253 tcg_gen_shli_tl(t1, t1, 3);
2254 tcg_gen_andi_tl(t0, t0, ~3);
2255 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL);
2256 tcg_gen_shr_tl(t0, t0, t1);
2257 tcg_gen_xori_tl(t1, t1, 31);
2258 t2 = tcg_const_tl(0xfffffffeull);
2259 tcg_gen_shl_tl(t2, t2, t1);
2260 gen_load_gpr(t1, rt);
2261 tcg_gen_and_tl(t1, t1, t2);
2262 tcg_temp_free(t2);
2263 tcg_gen_or_tl(t0, t0, t1);
2264 tcg_temp_free(t1);
2265 tcg_gen_ext32s_tl(t0, t0);
2266 gen_store_gpr(t0, rt);
2267 break;
2268 case OPC_LLE:
2269 mem_idx = MIPS_HFLAG_UM;
2270 /* fall through */
2271 case OPC_LL:
2272 case R6_OPC_LL:
2273 op_ld_ll(t0, t0, mem_idx, ctx);
2274 gen_store_gpr(t0, rt);
2275 break;
2276 }
2277 tcg_temp_free(t0);
2278 }
2279
2280 static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
2281 uint32_t reg1, uint32_t reg2)
2282 {
2283 TCGv taddr = tcg_temp_new();
2284 TCGv_i64 tval = tcg_temp_new_i64();
2285 TCGv tmp1 = tcg_temp_new();
2286 TCGv tmp2 = tcg_temp_new();
2287
2288 gen_base_offset_addr(ctx, taddr, base, offset);
2289 tcg_gen_qemu_ld64(tval, taddr, ctx->mem_idx);
2290 #ifdef TARGET_WORDS_BIGENDIAN
2291 tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
2292 #else
2293 tcg_gen_extr_i64_tl(tmp1, tmp2, tval);
2294 #endif
2295 gen_store_gpr(tmp1, reg1);
2296 tcg_temp_free(tmp1);
2297 gen_store_gpr(tmp2, reg2);
2298 tcg_temp_free(tmp2);
2299 tcg_gen_st_i64(tval, cpu_env, offsetof(CPUMIPSState, llval_wp));
2300 tcg_temp_free_i64(tval);
2301 tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr));
2302 tcg_temp_free(taddr);
2303 }
2304
2305 /* Store */
2306 static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
2307 int base, int offset)
2308 {
2309 TCGv t0 = tcg_temp_new();
2310 TCGv t1 = tcg_temp_new();
2311 int mem_idx = ctx->mem_idx;
2312
2313 gen_base_offset_addr(ctx, t0, base, offset);
2314 gen_load_gpr(t1, rt);
2315 switch (opc) {
2316 #if defined(TARGET_MIPS64)
2317 case OPC_SD:
2318 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEQ |
2319 ctx->default_tcg_memop_mask);
2320 break;
2321 case OPC_SDL:
2322 gen_helper_0e2i(sdl, t1, t0, mem_idx);
2323 break;
2324 case OPC_SDR:
2325 gen_helper_0e2i(sdr, t1, t0, mem_idx);
2326 break;
2327 #endif
2328 case OPC_SWE:
2329 mem_idx = MIPS_HFLAG_UM;
2330 /* fall through */
2331 case OPC_SW:
2332 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUL |
2333 ctx->default_tcg_memop_mask);
2334 break;
2335 case OPC_SHE:
2336 mem_idx = MIPS_HFLAG_UM;
2337 /* fall through */
2338 case OPC_SH:
2339 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUW |
2340 ctx->default_tcg_memop_mask);
2341 break;
2342 case OPC_SBE:
2343 mem_idx = MIPS_HFLAG_UM;
2344 /* fall through */
2345 case OPC_SB:
2346 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_8);
2347 break;
2348 case OPC_SWLE:
2349 mem_idx = MIPS_HFLAG_UM;
2350 /* fall through */
2351 case OPC_SWL:
2352 gen_helper_0e2i(swl, t1, t0, mem_idx);
2353 break;
2354 case OPC_SWRE:
2355 mem_idx = MIPS_HFLAG_UM;
2356 /* fall through */
2357 case OPC_SWR:
2358 gen_helper_0e2i(swr, t1, t0, mem_idx);
2359 break;
2360 }
2361 tcg_temp_free(t0);
2362 tcg_temp_free(t1);
2363 }
2364
2365
2366 /* Store conditional */
2367 static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
2368 MemOp tcg_mo, bool eva)
2369 {
2370 TCGv addr, t0, val;
2371 TCGLabel *l1 = gen_new_label();
2372 TCGLabel *done = gen_new_label();
2373
2374 t0 = tcg_temp_new();
2375 addr = tcg_temp_new();
2376 /* compare the address against that of the preceding LL */
2377 gen_base_offset_addr(ctx, addr, base, offset);
2378 tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
2379 tcg_temp_free(addr);
2380 tcg_gen_movi_tl(t0, 0);
2381 gen_store_gpr(t0, rt);
2382 tcg_gen_br(done);
2383
2384 gen_set_label(l1);
2385 /* generate cmpxchg */
2386 val = tcg_temp_new();
2387 gen_load_gpr(val, rt);
2388 tcg_gen_atomic_cmpxchg_tl(t0, cpu_lladdr, cpu_llval, val,
2389 eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo);
2390 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval);
2391 gen_store_gpr(t0, rt);
2392 tcg_temp_free(val);
2393
2394 gen_set_label(done);
2395 tcg_temp_free(t0);
2396 }
2397
2398
2399 static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
2400 uint32_t reg1, uint32_t reg2, bool eva)
2401 {
2402 TCGv taddr = tcg_temp_local_new();
2403 TCGv lladdr = tcg_temp_local_new();
2404 TCGv_i64 tval = tcg_temp_new_i64();
2405 TCGv_i64 llval = tcg_temp_new_i64();
2406 TCGv_i64 val = tcg_temp_new_i64();
2407 TCGv tmp1 = tcg_temp_new();
2408 TCGv tmp2 = tcg_temp_new();
2409 TCGLabel *lab_fail = gen_new_label();
2410 TCGLabel *lab_done = gen_new_label();
2411
2412 gen_base_offset_addr(ctx, taddr, base, offset);
2413
2414 tcg_gen_ld_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr));
2415 tcg_gen_brcond_tl(TCG_COND_NE, taddr, lladdr, lab_fail);
2416
2417 gen_load_gpr(tmp1, reg1);
2418 gen_load_gpr(tmp2, reg2);
2419
2420 #ifdef TARGET_WORDS_BIGENDIAN
2421 tcg_gen_concat_tl_i64(tval, tmp2, tmp1);
2422 #else
2423 tcg_gen_concat_tl_i64(tval, tmp1, tmp2);
2424 #endif
2425
2426 tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp));
2427 tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,
2428 eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64);
2429 if (reg1 != 0) {
2430 tcg_gen_movi_tl(cpu_gpr[reg1], 1);
2431 }
2432 tcg_gen_brcond_i64(TCG_COND_EQ, val, llval, lab_done);
2433
2434 gen_set_label(lab_fail);
2435
2436 if (reg1 != 0) {
2437 tcg_gen_movi_tl(cpu_gpr[reg1], 0);
2438 }
2439 gen_set_label(lab_done);
2440 tcg_gen_movi_tl(lladdr, -1);
2441 tcg_gen_st_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr));
2442 }
2443
2444 /* Load and store */
2445 static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
2446 TCGv t0)
2447 {
2448 /*
2449 * Don't do NOP if destination is zero: we must perform the actual
2450 * memory access.
2451 */
2452 switch (opc) {
2453 case OPC_LWC1:
2454 {
2455 TCGv_i32 fp0 = tcg_temp_new_i32();
2456 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
2457 ctx->default_tcg_memop_mask);
2458 gen_store_fpr32(ctx, fp0, ft);
2459 tcg_temp_free_i32(fp0);
2460 }
2461 break;
2462 case OPC_SWC1:
2463 {
2464 TCGv_i32 fp0 = tcg_temp_new_i32();
2465 gen_load_fpr32(ctx, fp0, ft);
2466 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
2467 ctx->default_tcg_memop_mask);
2468 tcg_temp_free_i32(fp0);
2469 }
2470 break;
2471 case OPC_LDC1:
2472 {
2473 TCGv_i64 fp0 = tcg_temp_new_i64();
2474 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ |
2475 ctx->default_tcg_memop_mask);
2476 gen_store_fpr64(ctx, fp0, ft);
2477 tcg_temp_free_i64(fp0);
2478 }
2479 break;
2480 case OPC_SDC1:
2481 {
2482 TCGv_i64 fp0 = tcg_temp_new_i64();
2483 gen_load_fpr64(ctx, fp0, ft);
2484 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ |
2485 ctx->default_tcg_memop_mask);
2486 tcg_temp_free_i64(fp0);
2487 }
2488 break;
2489 default:
2490 MIPS_INVAL("flt_ldst");
2491 gen_reserved_instruction(ctx);
2492 break;
2493 }
2494 }
2495
2496 static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
2497 int rs, int16_t imm)
2498 {
2499 TCGv t0 = tcg_temp_new();
2500
2501 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
2502 check_cp1_enabled(ctx);
2503 switch (op) {
2504 case OPC_LDC1:
2505 case OPC_SDC1:
2506 check_insn(ctx, ISA_MIPS2);
2507 /* Fallthrough */
2508 default:
2509 gen_base_offset_addr(ctx, t0, rs, imm);
2510 gen_flt_ldst(ctx, op, rt, t0);
2511 }
2512 } else {
2513 generate_exception_err(ctx, EXCP_CpU, 1);
2514 }
2515 tcg_temp_free(t0);
2516 }
2517
2518 /* Arithmetic with immediate operand */
2519 static void gen_arith_imm(DisasContext *ctx, uint32_t opc,
2520 int rt, int rs, int imm)
2521 {
2522 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
2523
2524 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
2525 /*
2526 * If no destination, treat it as a NOP.
2527 * For addi, we must generate the overflow exception when needed.
2528 */
2529 return;
2530 }
2531 switch (opc) {
2532 case OPC_ADDI:
2533 {
2534 TCGv t0 = tcg_temp_local_new();
2535 TCGv t1 = tcg_temp_new();
2536 TCGv t2 = tcg_temp_new();
2537 TCGLabel *l1 = gen_new_label();
2538
2539 gen_load_gpr(t1, rs);
2540 tcg_gen_addi_tl(t0, t1, uimm);
2541 tcg_gen_ext32s_tl(t0, t0);
2542
2543 tcg_gen_xori_tl(t1, t1, ~uimm);
2544 tcg_gen_xori_tl(t2, t0, uimm);
2545 tcg_gen_and_tl(t1, t1, t2);
2546 tcg_temp_free(t2);
2547 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2548 tcg_temp_free(t1);
2549 /* operands of same sign, result different sign */
2550 generate_exception(ctx, EXCP_OVERFLOW);
2551 gen_set_label(l1);
2552 tcg_gen_ext32s_tl(t0, t0);
2553 gen_store_gpr(t0, rt);
2554 tcg_temp_free(t0);
2555 }
2556 break;
2557 case OPC_ADDIU:
2558 if (rs != 0) {
2559 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2560 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
2561 } else {
2562 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2563 }
2564 break;
2565 #if defined(TARGET_MIPS64)
2566 case OPC_DADDI:
2567 {
2568 TCGv t0 = tcg_temp_local_new();
2569 TCGv t1 = tcg_temp_new();
2570 TCGv t2 = tcg_temp_new();
2571 TCGLabel *l1 = gen_new_label();
2572
2573 gen_load_gpr(t1, rs);
2574 tcg_gen_addi_tl(t0, t1, uimm);
2575
2576 tcg_gen_xori_tl(t1, t1, ~uimm);
2577 tcg_gen_xori_tl(t2, t0, uimm);
2578 tcg_gen_and_tl(t1, t1, t2);
2579 tcg_temp_free(t2);
2580 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2581 tcg_temp_free(t1);
2582 /* operands of same sign, result different sign */
2583 generate_exception(ctx, EXCP_OVERFLOW);
2584 gen_set_label(l1);
2585 gen_store_gpr(t0, rt);
2586 tcg_temp_free(t0);
2587 }
2588 break;
2589 case OPC_DADDIU:
2590 if (rs != 0) {
2591 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2592 } else {
2593 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2594 }
2595 break;
2596 #endif
2597 }
2598 }
2599
2600 /* Logic with immediate operand */
2601 static void gen_logic_imm(DisasContext *ctx, uint32_t opc,
2602 int rt, int rs, int16_t imm)
2603 {
2604 target_ulong uimm;
2605
2606 if (rt == 0) {
2607 /* If no destination, treat it as a NOP. */
2608 return;
2609 }
2610 uimm = (uint16_t)imm;
2611 switch (opc) {
2612 case OPC_ANDI:
2613 if (likely(rs != 0)) {
2614 tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2615 } else {
2616 tcg_gen_movi_tl(cpu_gpr[rt], 0);
2617 }
2618 break;
2619 case OPC_ORI:
2620 if (rs != 0) {
2621 tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2622 } else {
2623 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2624 }
2625 break;
2626 case OPC_XORI:
2627 if (likely(rs != 0)) {
2628 tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2629 } else {
2630 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2631 }
2632 break;
2633 case OPC_LUI:
2634 if (rs != 0 && (ctx->insn_flags & ISA_MIPS_R6)) {
2635 /* OPC_AUI */
2636 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16);
2637 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
2638 } else {
2639 tcg_gen_movi_tl(cpu_gpr[rt], imm << 16);
2640 }
2641 break;
2642
2643 default:
2644 break;
2645 }
2646 }
2647
2648 /* Set on less than with immediate operand */
2649 static void gen_slt_imm(DisasContext *ctx, uint32_t opc,
2650 int rt, int rs, int16_t imm)
2651 {
2652 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
2653 TCGv t0;
2654
2655 if (rt == 0) {
2656 /* If no destination, treat it as a NOP. */
2657 return;
2658 }
2659 t0 = tcg_temp_new();
2660 gen_load_gpr(t0, rs);
2661 switch (opc) {
2662 case OPC_SLTI:
2663 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, uimm);
2664 break;
2665 case OPC_SLTIU:
2666 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm);
2667 break;
2668 }
2669 tcg_temp_free(t0);
2670 }
2671
2672 /* Shifts with immediate operand */
2673 static void gen_shift_imm(DisasContext *ctx, uint32_t opc,
2674 int rt, int rs, int16_t imm)
2675 {
2676 target_ulong uimm = ((uint16_t)imm) & 0x1f;
2677 TCGv t0;
2678
2679 if (rt == 0) {
2680 /* If no destination, treat it as a NOP. */
2681 return;
2682 }
2683
2684 t0 = tcg_temp_new();
2685 gen_load_gpr(t0, rs);
2686 switch (opc) {
2687 case OPC_SLL:
2688 tcg_gen_shli_tl(t0, t0, uimm);
2689 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
2690 break;
2691 case OPC_SRA:
2692 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
2693 break;
2694 case OPC_SRL:
2695 if (uimm != 0) {
2696 tcg_gen_ext32u_tl(t0, t0);
2697 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
2698 } else {
2699 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
2700 }
2701 break;
2702 case OPC_ROTR:
2703 if (uimm != 0) {
2704 TCGv_i32 t1 = tcg_temp_new_i32();
2705
2706 tcg_gen_trunc_tl_i32(t1, t0);
2707 tcg_gen_rotri_i32(t1, t1, uimm);
2708 tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
2709 tcg_temp_free_i32(t1);
2710 } else {
2711 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
2712 }
2713 break;
2714 #if defined(TARGET_MIPS64)
2715 case OPC_DSLL:
2716 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm);
2717 break;
2718 case OPC_DSRA:
2719 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
2720 break;
2721 case OPC_DSRL:
2722 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
2723 break;
2724 case OPC_DROTR:
2725 if (uimm != 0) {
2726 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm);
2727 } else {
2728 tcg_gen_mov_tl(cpu_gpr[rt], t0);
2729 }
2730 break;
2731 case OPC_DSLL32:
2732 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32);
2733 break;
2734 case OPC_DSRA32:
2735 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32);
2736 break;
2737 case OPC_DSRL32:
2738 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32);
2739 break;
2740 case OPC_DROTR32:
2741 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32);
2742 break;
2743 #endif
2744 }
2745 tcg_temp_free(t0);
2746 }
2747
2748 /* Arithmetic */
2749 static void gen_arith(DisasContext *ctx, uint32_t opc,
2750 int rd, int rs, int rt)
2751 {
2752 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
2753 && opc != OPC_DADD && opc != OPC_DSUB) {
2754 /*
2755 * If no destination, treat it as a NOP.
2756 * For add & sub, we must generate the overflow exception when needed.
2757 */
2758 return;
2759 }
2760
2761 switch (opc) {
2762 case OPC_ADD:
2763 {
2764 TCGv t0 = tcg_temp_local_new();
2765 TCGv t1 = tcg_temp_new();
2766 TCGv t2 = tcg_temp_new();
2767 TCGLabel *l1 = gen_new_label();
2768
2769 gen_load_gpr(t1, rs);
2770 gen_load_gpr(t2, rt);
2771 tcg_gen_add_tl(t0, t1, t2);
2772 tcg_gen_ext32s_tl(t0, t0);
2773 tcg_gen_xor_tl(t1, t1, t2);
2774 tcg_gen_xor_tl(t2, t0, t2);
2775 tcg_gen_andc_tl(t1, t2, t1);
2776 tcg_temp_free(t2);
2777 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2778 tcg_temp_free(t1);
2779 /* operands of same sign, result different sign */
2780 generate_exception(ctx, EXCP_OVERFLOW);
2781 gen_set_label(l1);
2782 gen_store_gpr(t0, rd);
2783 tcg_temp_free(t0);
2784 }
2785 break;
2786 case OPC_ADDU:
2787 if (rs != 0 && rt != 0) {
2788 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2789 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2790 } else if (rs == 0 && rt != 0) {
2791 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2792 } else if (rs != 0 && rt == 0) {
2793 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2794 } else {
2795 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2796 }
2797 break;
2798 case OPC_SUB:
2799 {
2800 TCGv t0 = tcg_temp_local_new();
2801 TCGv t1 = tcg_temp_new();
2802 TCGv t2 = tcg_temp_new();
2803 TCGLabel *l1 = gen_new_label();
2804
2805 gen_load_gpr(t1, rs);
2806 gen_load_gpr(t2, rt);
2807 tcg_gen_sub_tl(t0, t1, t2);
2808 tcg_gen_ext32s_tl(t0, t0);
2809 tcg_gen_xor_tl(t2, t1, t2);
2810 tcg_gen_xor_tl(t1, t0, t1);
2811 tcg_gen_and_tl(t1, t1, t2);
2812 tcg_temp_free(t2);
2813 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2814 tcg_temp_free(t1);
2815 /*
2816 * operands of different sign, first operand and the result
2817 * of different sign
2818 */
2819 generate_exception(ctx, EXCP_OVERFLOW);
2820 gen_set_label(l1);
2821 gen_store_gpr(t0, rd);
2822 tcg_temp_free(t0);
2823 }
2824 break;
2825 case OPC_SUBU:
2826 if (rs != 0 && rt != 0) {
2827 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2828 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2829 } else if (rs == 0 && rt != 0) {
2830 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
2831 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2832 } else if (rs != 0 && rt == 0) {
2833 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2834 } else {
2835 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2836 }
2837 break;
2838 #if defined(TARGET_MIPS64)
2839 case OPC_DADD:
2840 {
2841 TCGv t0 = tcg_temp_local_new();
2842 TCGv t1 = tcg_temp_new();
2843 TCGv t2 = tcg_temp_new();
2844 TCGLabel *l1 = gen_new_label();
2845
2846 gen_load_gpr(t1, rs);
2847 gen_load_gpr(t2, rt);
2848 tcg_gen_add_tl(t0, t1, t2);
2849 tcg_gen_xor_tl(t1, t1, t2);
2850 tcg_gen_xor_tl(t2, t0, t2);
2851 tcg_gen_andc_tl(t1, t2, t1);
2852 tcg_temp_free(t2);
2853 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2854 tcg_temp_free(t1);
2855 /* operands of same sign, result different sign */
2856 generate_exception(ctx, EXCP_OVERFLOW);
2857 gen_set_label(l1);
2858 gen_store_gpr(t0, rd);
2859 tcg_temp_free(t0);
2860 }
2861 break;
2862 case OPC_DADDU:
2863 if (rs != 0 && rt != 0) {
2864 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2865 } else if (rs == 0 && rt != 0) {
2866 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2867 } else if (rs != 0 && rt == 0) {
2868 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2869 } else {
2870 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2871 }
2872 break;
2873 case OPC_DSUB:
2874 {
2875 TCGv t0 = tcg_temp_local_new();
2876 TCGv t1 = tcg_temp_new();
2877 TCGv t2 = tcg_temp_new();
2878 TCGLabel *l1 = gen_new_label();
2879
2880 gen_load_gpr(t1, rs);
2881 gen_load_gpr(t2, rt);
2882 tcg_gen_sub_tl(t0, t1, t2);
2883 tcg_gen_xor_tl(t2, t1, t2);
2884 tcg_gen_xor_tl(t1, t0, t1);
2885 tcg_gen_and_tl(t1, t1, t2);
2886 tcg_temp_free(t2);
2887 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2888 tcg_temp_free(t1);
2889 /*
2890 * Operands of different sign, first operand and result different
2891 * sign.
2892 */
2893 generate_exception(ctx, EXCP_OVERFLOW);
2894 gen_set_label(l1);
2895 gen_store_gpr(t0, rd);
2896 tcg_temp_free(t0);
2897 }
2898 break;
2899 case OPC_DSUBU:
2900 if (rs != 0 && rt != 0) {
2901 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2902 } else if (rs == 0 && rt != 0) {
2903 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
2904 } else if (rs != 0 && rt == 0) {
2905 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2906 } else {
2907 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2908 }
2909 break;
2910 #endif
2911 case OPC_MUL:
2912 if (likely(rs != 0 && rt != 0)) {
2913 tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2914 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2915 } else {
2916 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2917 }
2918 break;
2919 }
2920 }
2921
2922 /* Conditional move */
2923 static void gen_cond_move(DisasContext *ctx, uint32_t opc,
2924 int rd, int rs, int rt)
2925 {
2926 TCGv t0, t1, t2;
2927
2928 if (rd == 0) {
2929 /* If no destination, treat it as a NOP. */
2930 return;
2931 }
2932
2933 t0 = tcg_temp_new();
2934 gen_load_gpr(t0, rt);
2935 t1 = tcg_const_tl(0);
2936 t2 = tcg_temp_new();
2937 gen_load_gpr(t2, rs);
2938 switch (opc) {
2939 case OPC_MOVN:
2940 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
2941 break;
2942 case OPC_MOVZ:
2943 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
2944 break;
2945 case OPC_SELNEZ:
2946 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, t1);
2947 break;
2948 case OPC_SELEQZ:
2949 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1);
2950 break;
2951 }
2952 tcg_temp_free(t2);
2953 tcg_temp_free(t1);
2954 tcg_temp_free(t0);
2955 }
2956
2957 /* Logic */
2958 static void gen_logic(DisasContext *ctx, uint32_t opc,
2959 int rd, int rs, int rt)
2960 {
2961 if (rd == 0) {
2962 /* If no destination, treat it as a NOP. */
2963 return;
2964 }
2965
2966 switch (opc) {
2967 case OPC_AND:
2968 if (likely(rs != 0 && rt != 0)) {
2969 tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2970 } else {
2971 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2972 }
2973 break;
2974 case OPC_NOR:
2975 if (rs != 0 && rt != 0) {
2976 tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2977 } else if (rs == 0 && rt != 0) {
2978 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]);
2979 } else if (rs != 0 && rt == 0) {
2980 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]);
2981 } else {
2982 tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0));
2983 }
2984 break;
2985 case OPC_OR:
2986 if (likely(rs != 0 && rt != 0)) {
2987 tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2988 } else if (rs == 0 && rt != 0) {
2989 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2990 } else if (rs != 0 && rt == 0) {
2991 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2992 } else {
2993 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2994 }
2995 break;
2996 case OPC_XOR:
2997 if (likely(rs != 0 && rt != 0)) {
2998 tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2999 } else if (rs == 0 && rt != 0) {
3000 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
3001 } else if (rs != 0 && rt == 0) {
3002 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
3003 } else {
3004 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3005 }
3006 break;
3007 }
3008 }
3009
3010 /* Set on lower than */
3011 static void gen_slt(DisasContext *ctx, uint32_t opc,
3012 int rd, int rs, int rt)
3013 {
3014 TCGv t0, t1;
3015
3016 if (rd == 0) {
3017 /* If no destination, treat it as a NOP. */
3018 return;
3019 }
3020
3021 t0 = tcg_temp_new();
3022 t1 = tcg_temp_new();
3023 gen_load_gpr(t0, rs);
3024 gen_load_gpr(t1, rt);
3025 switch (opc) {
3026 case OPC_SLT:
3027 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr[rd], t0, t1);
3028 break;
3029 case OPC_SLTU:
3030 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1);
3031 break;
3032 }
3033 tcg_temp_free(t0);
3034 tcg_temp_free(t1);
3035 }
3036
3037 /* Shifts */
3038 static void gen_shift(DisasContext *ctx, uint32_t opc,
3039 int rd, int rs, int rt)
3040 {
3041 TCGv t0, t1;
3042
3043 if (rd == 0) {
3044 /*
3045 * If no destination, treat it as a NOP.
3046 * For add & sub, we must generate the overflow exception when needed.
3047 */
3048 return;
3049 }
3050
3051 t0 = tcg_temp_new();
3052 t1 = tcg_temp_new();
3053 gen_load_gpr(t0, rs);
3054 gen_load_gpr(t1, rt);
3055 switch (opc) {
3056 case OPC_SLLV:
3057 tcg_gen_andi_tl(t0, t0, 0x1f);
3058 tcg_gen_shl_tl(t0, t1, t0);
3059 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
3060 break;
3061 case OPC_SRAV:
3062 tcg_gen_andi_tl(t0, t0, 0x1f);
3063 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
3064 break;
3065 case OPC_SRLV:
3066 tcg_gen_ext32u_tl(t1, t1);
3067 tcg_gen_andi_tl(t0, t0, 0x1f);
3068 tcg_gen_shr_tl(t0, t1, t0);
3069 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
3070 break;
3071 case OPC_ROTRV:
3072 {
3073 TCGv_i32 t2 = tcg_temp_new_i32();
3074 TCGv_i32 t3 = tcg_temp_new_i32();
3075
3076 tcg_gen_trunc_tl_i32(t2, t0);
3077 tcg_gen_trunc_tl_i32(t3, t1);
3078 tcg_gen_andi_i32(t2, t2, 0x1f);
3079 tcg_gen_rotr_i32(t2, t3, t2);
3080 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3081 tcg_temp_free_i32(t2);
3082 tcg_temp_free_i32(t3);
3083 }
3084 break;
3085 #if defined(TARGET_MIPS64)
3086 case OPC_DSLLV:
3087 tcg_gen_andi_tl(t0, t0, 0x3f);
3088 tcg_gen_shl_tl(cpu_gpr[rd], t1, t0);
3089 break;
3090 case OPC_DSRAV:
3091 tcg_gen_andi_tl(t0, t0, 0x3f);
3092 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
3093 break;
3094 case OPC_DSRLV:
3095 tcg_gen_andi_tl(t0, t0, 0x3f);
3096 tcg_gen_shr_tl(cpu_gpr[rd], t1, t0);
3097 break;
3098 case OPC_DROTRV:
3099 tcg_gen_andi_tl(t0, t0, 0x3f);
3100 tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0);
3101 break;
3102 #endif
3103 }
3104 tcg_temp_free(t0);
3105 tcg_temp_free(t1);
3106 }
3107
3108 /* Arithmetic on HI/LO registers */
3109 static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
3110 {
3111 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
3112 /* Treat as NOP. */
3113 return;
3114 }
3115
3116 if (acc != 0) {
3117 check_dsp(ctx);
3118 }
3119
3120 switch (opc) {
3121 case OPC_MFHI:
3122 #if defined(TARGET_MIPS64)
3123 if (acc != 0) {
3124 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]);
3125 } else
3126 #endif
3127 {
3128 tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]);
3129 }
3130 break;
3131 case OPC_MFLO:
3132 #if defined(TARGET_MIPS64)
3133 if (acc != 0) {
3134 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]);
3135 } else
3136 #endif
3137 {
3138 tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]);
3139 }
3140 break;
3141 case OPC_MTHI:
3142 if (reg != 0) {
3143 #if defined(TARGET_MIPS64)
3144 if (acc != 0) {
3145 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_gpr[reg]);
3146 } else
3147 #endif
3148 {
3149 tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]);
3150 }
3151 } else {
3152 tcg_gen_movi_tl(cpu_HI[acc], 0);
3153 }
3154 break;
3155 case OPC_MTLO:
3156 if (reg != 0) {
3157 #if defined(TARGET_MIPS64)
3158 if (acc != 0) {
3159 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_gpr[reg]);
3160 } else
3161 #endif
3162 {
3163 tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]);
3164 }
3165 } else {
3166 tcg_gen_movi_tl(cpu_LO[acc], 0);
3167 }
3168 break;
3169 }
3170 }
3171
3172 static inline void gen_r6_ld(target_long addr, int reg, int memidx,
3173 MemOp memop)
3174 {
3175 TCGv t0 = tcg_const_tl(addr);
3176 tcg_gen_qemu_ld_tl(t0, t0, memidx, memop);
3177 gen_store_gpr(t0, reg);
3178 tcg_temp_free(t0);
3179 }
3180
3181 static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
3182 int rs)
3183 {
3184 target_long offset;
3185 target_long addr;
3186
3187 switch (MASK_OPC_PCREL_TOP2BITS(opc)) {
3188 case OPC_ADDIUPC:
3189 if (rs != 0) {
3190 offset = sextract32(ctx->opcode << 2, 0, 21);
3191 addr = addr_add(ctx, pc, offset);
3192 tcg_gen_movi_tl(cpu_gpr[rs], addr);
3193 }
3194 break;
3195 case R6_OPC_LWPC:
3196 offset = sextract32(ctx->opcode << 2, 0, 21);
3197 addr = addr_add(ctx, pc, offset);
3198 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TESL);
3199 break;
3200 #if defined(TARGET_MIPS64)
3201 case OPC_LWUPC:
3202 check_mips_64(ctx);
3203 offset = sextract32(ctx->opcode << 2, 0, 21);
3204 addr = addr_add(ctx, pc, offset);
3205 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUL);
3206 break;
3207 #endif
3208 default:
3209 switch (MASK_OPC_PCREL_TOP5BITS(opc)) {
3210 case OPC_AUIPC:
3211 if (rs != 0) {
3212 offset = sextract32(ctx->opcode, 0, 16) << 16;
3213 addr = addr_add(ctx, pc, offset);
3214 tcg_gen_movi_tl(cpu_gpr[rs], addr);
3215 }
3216 break;
3217 case OPC_ALUIPC:
3218 if (rs != 0) {
3219 offset = sextract32(ctx->opcode, 0, 16) << 16;
3220 addr = ~0xFFFF & addr_add(ctx, pc, offset);
3221 tcg_gen_movi_tl(cpu_gpr[rs], addr);
3222 }
3223 break;
3224 #if defined(TARGET_MIPS64)
3225 case R6_OPC_LDPC: /* bits 16 and 17 are part of immediate */
3226 case R6_OPC_LDPC + (1 << 16):
3227 case R6_OPC_LDPC + (2 << 16):
3228 case R6_OPC_LDPC + (3 << 16):
3229 check_mips_64(ctx);
3230 offset = sextract32(ctx->opcode << 3, 0, 21);
3231 addr = addr_add(ctx, (pc & ~0x7), offset);
3232 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEQ);
3233 break;
3234 #endif
3235 default:
3236 MIPS_INVAL("OPC_PCREL");
3237 gen_reserved_instruction(ctx);
3238 break;
3239 }
3240 break;
3241 }
3242 }
3243
3244 static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
3245 {
3246 TCGv t0, t1;
3247
3248 if (rd == 0) {
3249 /* Treat as NOP. */
3250 return;
3251 }
3252
3253 t0 = tcg_temp_new();
3254 t1 = tcg_temp_new();
3255
3256 gen_load_gpr(t0, rs);
3257 gen_load_gpr(t1, rt);
3258
3259 switch (opc) {
3260 case R6_OPC_DIV:
3261 {
3262 TCGv t2 = tcg_temp_new();
3263 TCGv t3 = tcg_temp_new();
3264 tcg_gen_ext32s_tl(t0, t0);
3265 tcg_gen_ext32s_tl(t1, t1);
3266 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3267 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3268 tcg_gen_and_tl(t2, t2, t3);
3269 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3270 tcg_gen_or_tl(t2, t2, t3);
3271 tcg_gen_movi_tl(t3, 0);
3272 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3273 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3274 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3275 tcg_temp_free(t3);
3276 tcg_temp_free(t2);
3277 }
3278 break;
3279 case R6_OPC_MOD:
3280 {
3281 TCGv t2 = tcg_temp_new();
3282 TCGv t3 = tcg_temp_new();
3283 tcg_gen_ext32s_tl(t0, t0);
3284 tcg_gen_ext32s_tl(t1, t1);
3285 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3286 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3287 tcg_gen_and_tl(t2, t2, t3);
3288 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3289 tcg_gen_or_tl(t2, t2, t3);
3290 tcg_gen_movi_tl(t3, 0);
3291 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3292 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3293 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3294 tcg_temp_free(t3);
3295 tcg_temp_free(t2);
3296 }
3297 break;
3298 case R6_OPC_DIVU:
3299 {
3300 TCGv t2 = tcg_const_tl(0);
3301 TCGv t3 = tcg_const_tl(1);
3302 tcg_gen_ext32u_tl(t0, t0);
3303 tcg_gen_ext32u_tl(t1, t1);
3304 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3305 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
3306 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3307 tcg_temp_free(t3);
3308 tcg_temp_free(t2);
3309 }
3310 break;
3311 case R6_OPC_MODU:
3312 {
3313 TCGv t2 = tcg_const_tl(0);
3314 TCGv t3 = tcg_const_tl(1);
3315 tcg_gen_ext32u_tl(t0, t0);
3316 tcg_gen_ext32u_tl(t1, t1);
3317 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3318 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
3319 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3320 tcg_temp_free(t3);
3321 tcg_temp_free(t2);
3322 }
3323 break;
3324 case R6_OPC_MUL:
3325 {
3326 TCGv_i32 t2 = tcg_temp_new_i32();
3327 TCGv_i32 t3 = tcg_temp_new_i32();
3328 tcg_gen_trunc_tl_i32(t2, t0);
3329 tcg_gen_trunc_tl_i32(t3, t1);
3330 tcg_gen_mul_i32(t2, t2, t3);
3331 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3332 tcg_temp_free_i32(t2);
3333 tcg_temp_free_i32(t3);
3334 }
3335 break;
3336 case R6_OPC_MUH:
3337 {
3338 TCGv_i32 t2 = tcg_temp_new_i32();
3339 TCGv_i32 t3 = tcg_temp_new_i32();
3340 tcg_gen_trunc_tl_i32(t2, t0);
3341 tcg_gen_trunc_tl_i32(t3, t1);
3342 tcg_gen_muls2_i32(t2, t3, t2, t3);
3343 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
3344 tcg_temp_free_i32(t2);
3345 tcg_temp_free_i32(t3);
3346 }
3347 break;
3348 case R6_OPC_MULU:
3349 {
3350 TCGv_i32 t2 = tcg_temp_new_i32();
3351 TCGv_i32 t3 = tcg_temp_new_i32();
3352 tcg_gen_trunc_tl_i32(t2, t0);
3353 tcg_gen_trunc_tl_i32(t3, t1);
3354 tcg_gen_mul_i32(t2, t2, t3);
3355 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3356 tcg_temp_free_i32(t2);
3357 tcg_temp_free_i32(t3);
3358 }
3359 break;
3360 case R6_OPC_MUHU:
3361 {
3362 TCGv_i32 t2 = tcg_temp_new_i32();
3363 TCGv_i32 t3 = tcg_temp_new_i32();
3364 tcg_gen_trunc_tl_i32(t2, t0);
3365 tcg_gen_trunc_tl_i32(t3, t1);
3366 tcg_gen_mulu2_i32(t2, t3, t2, t3);
3367 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
3368 tcg_temp_free_i32(t2);
3369 tcg_temp_free_i32(t3);
3370 }
3371 break;
3372 #if defined(TARGET_MIPS64)
3373 case R6_OPC_DDIV:
3374 {
3375 TCGv t2 = tcg_temp_new();
3376 TCGv t3 = tcg_temp_new();
3377 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
3378 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
3379 tcg_gen_and_tl(t2, t2, t3);
3380 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3381 tcg_gen_or_tl(t2, t2, t3);
3382 tcg_gen_movi_tl(t3, 0);
3383 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3384 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3385 tcg_temp_free(t3);
3386 tcg_temp_free(t2);
3387 }
3388 break;
3389 case R6_OPC_DMOD:
3390 {
3391 TCGv t2 = tcg_temp_new();
3392 TCGv t3 = tcg_temp_new();
3393 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
3394 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
3395 tcg_gen_and_tl(t2, t2, t3);
3396 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3397 tcg_gen_or_tl(t2, t2, t3);
3398 tcg_gen_movi_tl(t3, 0);
3399 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3400 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3401 tcg_temp_free(t3);
3402 tcg_temp_free(t2);
3403 }
3404 break;
3405 case R6_OPC_DDIVU:
3406 {
3407 TCGv t2 = tcg_const_tl(0);
3408 TCGv t3 = tcg_const_tl(1);
3409 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3410 tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);
3411 tcg_temp_free(t3);
3412 tcg_temp_free(t2);
3413 }
3414 break;
3415 case R6_OPC_DMODU:
3416 {
3417 TCGv t2 = tcg_const_tl(0);
3418 TCGv t3 = tcg_const_tl(1);
3419 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3420 tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);
3421 tcg_temp_free(t3);
3422 tcg_temp_free(t2);
3423 }
3424 break;
3425 case R6_OPC_DMUL:
3426 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
3427 break;
3428 case R6_OPC_DMUH:
3429 {
3430 TCGv t2 = tcg_temp_new();
3431 tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1);
3432 tcg_temp_free(t2);
3433 }
3434 break;
3435 case R6_OPC_DMULU:
3436 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
3437 break;
3438 case R6_OPC_DMUHU:
3439 {
3440 TCGv t2 = tcg_temp_new();
3441 tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1);
3442 tcg_temp_free(t2);
3443 }
3444 break;
3445 #endif
3446 default:
3447 MIPS_INVAL("r6 mul/div");
3448 gen_reserved_instruction(ctx);
3449 goto out;
3450 }
3451 out:
3452 tcg_temp_free(t0);
3453 tcg_temp_free(t1);
3454 }
3455
3456 #if defined(TARGET_MIPS64)
3457 static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
3458 {
3459 TCGv t0, t1;
3460
3461 t0 = tcg_temp_new();
3462 t1 = tcg_temp_new();
3463
3464 gen_load_gpr(t0, rs);
3465 gen_load_gpr(t1, rt);
3466
3467 switch (opc) {
3468 case MMI_OPC_DIV1:
3469 {
3470 TCGv t2 = tcg_temp_new();
3471 TCGv t3 = tcg_temp_new();
3472 tcg_gen_ext32s_tl(t0, t0);
3473 tcg_gen_ext32s_tl(t1, t1);
3474 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3475 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3476 tcg_gen_and_tl(t2, t2, t3);
3477 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3478 tcg_gen_or_tl(t2, t2, t3);
3479 tcg_gen_movi_tl(t3, 0);
3480 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3481 tcg_gen_div_tl(cpu_LO[1], t0, t1);
3482 tcg_gen_rem_tl(cpu_HI[1], t0, t1);
3483 tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
3484 tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
3485 tcg_temp_free(t3);
3486 tcg_temp_free(t2);
3487 }
3488 break;
3489 case MMI_OPC_DIVU1:
3490 {
3491 TCGv t2 = tcg_const_tl(0);
3492 TCGv t3 = tcg_const_tl(1);
3493 tcg_gen_ext32u_tl(t0, t0);
3494 tcg_gen_ext32u_tl(t1, t1);
3495 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3496 tcg_gen_divu_tl(cpu_LO[1], t0, t1);
3497 tcg_gen_remu_tl(cpu_HI[1], t0, t1);
3498 tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
3499 tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
3500 tcg_temp_free(t3);
3501 tcg_temp_free(t2);
3502 }
3503 break;
3504 default:
3505 MIPS_INVAL("div1 TX79");
3506 gen_reserved_instruction(ctx);
3507 goto out;
3508 }
3509 out:
3510 tcg_temp_free(t0);
3511 tcg_temp_free(t1);
3512 }
3513 #endif
3514
3515 static void gen_muldiv(DisasContext *ctx, uint32_t opc,
3516 int acc, int rs, int rt)
3517 {
3518 TCGv t0, t1;
3519
3520 t0 = tcg_temp_new();
3521 t1 = tcg_temp_new();
3522
3523 gen_load_gpr(t0, rs);
3524 gen_load_gpr(t1, rt);
3525
3526 if (acc != 0) {
3527 check_dsp(ctx);
3528 }
3529
3530 switch (opc) {
3531 case OPC_DIV:
3532 {
3533 TCGv t2 = tcg_temp_new();
3534 TCGv t3 = tcg_temp_new();
3535 tcg_gen_ext32s_tl(t0, t0);
3536 tcg_gen_ext32s_tl(t1, t1);
3537 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3538 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3539 tcg_gen_and_tl(t2, t2, t3);
3540 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3541 tcg_gen_or_tl(t2, t2, t3);
3542 tcg_gen_movi_tl(t3, 0);
3543 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3544 tcg_gen_div_tl(cpu_LO[acc], t0, t1);
3545 tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
3546 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
3547 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
3548 tcg_temp_free(t3);
3549 tcg_temp_free(t2);
3550 }
3551 break;
3552 case OPC_DIVU:
3553 {
3554 TCGv t2 = tcg_const_tl(0);
3555 TCGv t3 = tcg_const_tl(1);
3556 tcg_gen_ext32u_tl(t0, t0);
3557 tcg_gen_ext32u_tl(t1, t1);
3558 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3559 tcg_gen_divu_tl(cpu_LO[acc], t0, t1);
3560 tcg_gen_remu_tl(cpu_HI[acc], t0, t1);
3561 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
3562 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
3563 tcg_temp_free(t3);
3564 tcg_temp_free(t2);
3565 }
3566 break;
3567 case OPC_MULT:
3568 {
3569 TCGv_i32 t2 = tcg_temp_new_i32();
3570 TCGv_i32 t3 = tcg_temp_new_i32();
3571 tcg_gen_trunc_tl_i32(t2, t0);
3572 tcg_gen_trunc_tl_i32(t3, t1);
3573 tcg_gen_muls2_i32(t2, t3, t2, t3);
3574 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3575 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3576 tcg_temp_free_i32(t2);
3577 tcg_temp_free_i32(t3);
3578 }
3579 break;
3580 case OPC_MULTU:
3581 {
3582 TCGv_i32 t2 = tcg_temp_new_i32();
3583 TCGv_i32 t3 = tcg_temp_new_i32();
3584 tcg_gen_trunc_tl_i32(t2, t0);
3585 tcg_gen_trunc_tl_i32(t3, t1);
3586 tcg_gen_mulu2_i32(t2, t3, t2, t3);
3587 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3588 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3589 tcg_temp_free_i32(t2);
3590 tcg_temp_free_i32(t3);
3591 }
3592 break;
3593 #if defined(TARGET_MIPS64)
3594 case OPC_DDIV:
3595 {
3596 TCGv t2 = tcg_temp_new();
3597 TCGv t3 = tcg_temp_new();
3598 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
3599 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
3600 tcg_gen_and_tl(t2, t2, t3);
3601 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3602 tcg_gen_or_tl(t2, t2, t3);
3603 tcg_gen_movi_tl(t3, 0);
3604 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3605 tcg_gen_div_tl(cpu_LO[acc], t0, t1);
3606 tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
3607 tcg_temp_free(t3);
3608 tcg_temp_free(t2);
3609 }
3610 break;
3611 case OPC_DDIVU:
3612 {
3613 TCGv t2 = tcg_const_tl(0);
3614 TCGv t3 = tcg_const_tl(1);
3615 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3616 tcg_gen_divu_i64(cpu_LO[acc], t0, t1);
3617 tcg_gen_remu_i64(cpu_HI[acc], t0, t1);
3618 tcg_temp_free(t3);
3619 tcg_temp_free(t2);
3620 }
3621 break;
3622 case OPC_DMULT:
3623 tcg_gen_muls2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1);
3624 break;
3625 case OPC_DMULTU:
3626 tcg_gen_mulu2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1);
3627 break;
3628 #endif
3629 case OPC_MADD:
3630 {
3631 TCGv_i64 t2 = tcg_temp_new_i64();
3632 TCGv_i64 t3 = tcg_temp_new_i64();
3633
3634 tcg_gen_ext_tl_i64(t2, t0);
3635 tcg_gen_ext_tl_i64(t3, t1);
3636 tcg_gen_mul_i64(t2, t2, t3);
3637 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3638 tcg_gen_add_i64(t2, t2, t3);
3639 tcg_temp_free_i64(t3);
3640 gen_move_low32(cpu_LO[acc], t2);
3641 gen_move_high32(cpu_HI[acc], t2);
3642 tcg_temp_free_i64(t2);
3643 }
3644 break;
3645 case OPC_MADDU:
3646 {
3647 TCGv_i64 t2 = tcg_temp_new_i64();
3648 TCGv_i64 t3 = tcg_temp_new_i64();
3649
3650 tcg_gen_ext32u_tl(t0, t0);
3651 tcg_gen_ext32u_tl(t1, t1);
3652 tcg_gen_extu_tl_i64(t2, t0);
3653 tcg_gen_extu_tl_i64(t3, t1);
3654 tcg_gen_mul_i64(t2, t2, t3);
3655 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3656 tcg_gen_add_i64(t2, t2, t3);
3657 tcg_temp_free_i64(t3);
3658 gen_move_low32(cpu_LO[acc], t2);
3659 gen_move_high32(cpu_HI[acc], t2);
3660 tcg_temp_free_i64(t2);
3661 }
3662 break;
3663 case OPC_MSUB:
3664 {
3665 TCGv_i64 t2 = tcg_temp_new_i64();
3666 TCGv_i64 t3 = tcg_temp_new_i64();
3667
3668 tcg_gen_ext_tl_i64(t2, t0);
3669 tcg_gen_ext_tl_i64(t3, t1);
3670 tcg_gen_mul_i64(t2, t2, t3);
3671 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3672 tcg_gen_sub_i64(t2, t3, t2);
3673 tcg_temp_free_i64(t3);
3674 gen_move_low32(cpu_LO[acc], t2);
3675 gen_move_high32(cpu_HI[acc], t2);
3676 tcg_temp_free_i64(t2);
3677 }
3678 break;
3679 case OPC_MSUBU:
3680 {
3681 TCGv_i64 t2 = tcg_temp_new_i64();
3682 TCGv_i64 t3 = tcg_temp_new_i64();
3683
3684 tcg_gen_ext32u_tl(t0, t0);
3685 tcg_gen_ext32u_tl(t1, t1);
3686 tcg_gen_extu_tl_i64(t2, t0);
3687 tcg_gen_extu_tl_i64(t3, t1);
3688 tcg_gen_mul_i64(t2, t2, t3);
3689 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3690 tcg_gen_sub_i64(t2, t3, t2);
3691 tcg_temp_free_i64(t3);
3692 gen_move_low32(cpu_LO[acc], t2);
3693 gen_move_high32(cpu_HI[acc], t2);
3694 tcg_temp_free_i64(t2);
3695 }
3696 break;
3697 default:
3698 MIPS_INVAL("mul/div");
3699 gen_reserved_instruction(ctx);
3700 goto out;
3701 }
3702 out:
3703 tcg_temp_free(t0);
3704 tcg_temp_free(t1);
3705 }
3706
3707 /*
3708 * These MULT[U] and MADD[U] instructions implemented in for example
3709 * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
3710 * architectures are special three-operand variants with the syntax
3711 *
3712 * MULT[U][1] rd, rs, rt
3713 *
3714 * such that
3715 *
3716 * (rd, LO, HI) <- rs * rt
3717 *
3718 * and
3719 *
3720 * MADD[U][1] rd, rs, rt
3721 *
3722 * such that
3723 *
3724 * (rd, LO, HI) <- (LO, HI) + rs * rt
3725 *
3726 * where the low-order 32-bits of the result is placed into both the
3727 * GPR rd and the special register LO. The high-order 32-bits of the
3728 * result is placed into the special register HI.
3729 *
3730 * If the GPR rd is omitted in assembly language, it is taken to be 0,
3731 * which is the zero register that always reads as 0.
3732 */
3733 static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
3734 int rd, int rs, int rt)
3735 {
3736 TCGv t0 = tcg_temp_new();
3737 TCGv t1 = tcg_temp_new();
3738 int acc = 0;
3739
3740 gen_load_gpr(t0, rs);
3741 gen_load_gpr(t1, rt);
3742
3743 switch (opc) {
3744 case MMI_OPC_MULT1:
3745 acc = 1;
3746 /* Fall through */
3747 case OPC_MULT:
3748 {
3749 TCGv_i32 t2 = tcg_temp_new_i32();
3750 TCGv_i32 t3 = tcg_temp_new_i32();
3751 tcg_gen_trunc_tl_i32(t2, t0);
3752 tcg_gen_trunc_tl_i32(t3, t1);
3753 tcg_gen_muls2_i32(t2, t3, t2, t3);
3754 if (rd) {
3755 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3756 }
3757 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3758 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3759 tcg_temp_free_i32(t2);
3760 tcg_temp_free_i32(t3);
3761 }
3762 break;
3763 case MMI_OPC_MULTU1:
3764 acc = 1;
3765 /* Fall through */
3766 case OPC_MULTU:
3767 {
3768 TCGv_i32 t2 = tcg_temp_new_i32();
3769 TCGv_i32 t3 = tcg_temp_new_i32();
3770 tcg_gen_trunc_tl_i32(t2, t0);
3771 tcg_gen_trunc_tl_i32(t3, t1);
3772 tcg_gen_mulu2_i32(t2, t3, t2, t3);
3773 if (rd) {
3774 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3775 }
3776 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3777 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3778 tcg_temp_free_i32(t2);
3779 tcg_temp_free_i32(t3);
3780 }
3781 break;
3782 case MMI_OPC_MADD1:
3783 acc = 1;
3784 /* Fall through */
3785 case MMI_OPC_MADD:
3786 {
3787 TCGv_i64 t2 = tcg_temp_new_i64();
3788 TCGv_i64 t3 = tcg_temp_new_i64();
3789
3790 tcg_gen_ext_tl_i64(t2, t0);
3791 tcg_gen_ext_tl_i64(t3, t1);
3792 tcg_gen_mul_i64(t2, t2, t3);
3793 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3794 tcg_gen_add_i64(t2, t2, t3);
3795 tcg_temp_free_i64(t3);
3796 gen_move_low32(cpu_LO[acc], t2);
3797 gen_move_high32(cpu_HI[acc], t2);
3798 if (rd) {
3799 gen_move_low32(cpu_gpr[rd], t2);
3800 }
3801 tcg_temp_free_i64(t2);
3802 }
3803 break;
3804 case MMI_OPC_MADDU1:
3805 acc = 1;
3806 /* Fall through */
3807 case MMI_OPC_MADDU:
3808 {
3809 TCGv_i64 t2 = tcg_temp_new_i64();
3810 TCGv_i64 t3 = tcg_temp_new_i64();
3811
3812 tcg_gen_ext32u_tl(t0, t0);
3813 tcg_gen_ext32u_tl(t1, t1);
3814 tcg_gen_extu_tl_i64(t2, t0);
3815 tcg_gen_extu_tl_i64(t3, t1);
3816 tcg_gen_mul_i64(t2, t2, t3);
3817 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3818 tcg_gen_add_i64(t2, t2, t3);
3819 tcg_temp_free_i64(t3);
3820 gen_move_low32(cpu_LO[acc], t2);
3821 gen_move_high32(cpu_HI[acc], t2);
3822 if (rd) {
3823 gen_move_low32(cpu_gpr[rd], t2);
3824 }
3825 tcg_temp_free_i64(t2);
3826 }
3827 break;
3828 default:
3829 MIPS_INVAL("mul/madd TXx9");
3830 gen_reserved_instruction(ctx);
3831 goto out;
3832 }
3833
3834 out:
3835 tcg_temp_free(t0);
3836 tcg_temp_free(t1);
3837 }
3838
3839 static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc,
3840 int rd, int rs, int rt)
3841 {
3842 TCGv t0 = tcg_temp_new();
3843 TCGv t1 = tcg_temp_new();
3844
3845 gen_load_gpr(t0, rs);
3846 gen_load_gpr(t1, rt);
3847
3848 switch (opc) {
3849 case OPC_VR54XX_MULS:
3850 gen_helper_muls(t0, cpu_env, t0, t1);
3851 break;
3852 case OPC_VR54XX_MULSU:
3853 gen_helper_mulsu(t0, cpu_env, t0, t1);
3854 break;
3855 case OPC_VR54XX_MACC:
3856 gen_helper_macc(t0, cpu_env, t0, t1);
3857 break;
3858 case OPC_VR54XX_MACCU:
3859 gen_helper_maccu(t0, cpu_env, t0, t1);
3860 break;
3861 case OPC_VR54XX_MSAC:
3862 gen_helper_msac(t0, cpu_env, t0, t1);
3863 break;
3864 case OPC_VR54XX_MSACU:
3865 gen_helper_msacu(t0, cpu_env, t0, t1);
3866 break;
3867 case OPC_VR54XX_MULHI:
3868 gen_helper_mulhi(t0, cpu_env, t0, t1);
3869 break;
3870 case OPC_VR54XX_MULHIU:
3871 gen_helper_mulhiu(t0, cpu_env, t0, t1);
3872 break;
3873 case OPC_VR54XX_MULSHI:
3874 gen_helper_mulshi(t0, cpu_env, t0, t1);
3875 break;
3876 case OPC_VR54XX_MULSHIU:
3877 gen_helper_mulshiu(t0, cpu_env, t0, t1);
3878 break;
3879 case OPC_VR54XX_MACCHI:
3880 gen_helper_macchi(t0, cpu_env, t0, t1);
3881 break;
3882 case OPC_VR54XX_MACCHIU:
3883 gen_helper_macchiu(t0, cpu_env, t0, t1);
3884 break;
3885 case OPC_VR54XX_MSACHI:
3886 gen_helper_msachi(t0, cpu_env, t0, t1);
3887 break;
3888 case OPC_VR54XX_MSACHIU:
3889 gen_helper_msachiu(t0, cpu_env, t0, t1);
3890 break;
3891 default:
3892 MIPS_INVAL("mul vr54xx");
3893 gen_reserved_instruction(ctx);
3894 goto out;
3895 }
3896 gen_store_gpr(t0, rd);
3897
3898 out:
3899 tcg_temp_free(t0);
3900 tcg_temp_free(t1);
3901 }
3902
3903 static void gen_cl(DisasContext *ctx, uint32_t opc,
3904 int rd, int rs)
3905 {
3906 TCGv t0;
3907
3908 if (rd == 0) {
3909 /* Treat as NOP. */
3910 return;
3911 }
3912 t0 = cpu_gpr[rd];
3913 gen_load_gpr(t0, rs);
3914
3915 switch (opc) {
3916 case OPC_CLO:
3917 case R6_OPC_CLO:
3918 #if defined(TARGET_MIPS64)
3919 case OPC_DCLO:
3920 case R6_OPC_DCLO:
3921 #endif
3922 tcg_gen_not_tl(t0, t0);
3923 break;
3924 }
3925
3926 switch (opc) {
3927 case OPC_CLO:
3928 case R6_OPC_CLO:
3929 case OPC_CLZ:
3930 case R6_OPC_CLZ:
3931 tcg_gen_ext32u_tl(t0, t0);
3932 tcg_gen_clzi_tl(t0, t0, TARGET_LONG_BITS);
3933 tcg_gen_subi_tl(t0, t0, TARGET_LONG_BITS - 32);
3934 break;
3935 #if defined(TARGET_MIPS64)
3936 case OPC_DCLO:
3937 case R6_OPC_DCLO:
3938 case OPC_DCLZ:
3939 case R6_OPC_DCLZ:
3940 tcg_gen_clzi_i64(t0, t0, 64);
3941 break;
3942 #endif
3943 }
3944 }
3945
3946 /* Godson integer instructions */
3947 static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
3948 int rd, int rs, int rt)
3949 {
3950 TCGv t0, t1;
3951
3952 if (rd == 0) {
3953 /* Treat as NOP. */
3954 return;
3955 }
3956
3957 switch (opc) {
3958 case OPC_MULT_G_2E:
3959 case OPC_MULT_G_2F:
3960 case OPC_MULTU_G_2E:
3961 case OPC_MULTU_G_2F:
3962 #if defined(TARGET_MIPS64)
3963 case OPC_DMULT_G_2E:
3964 case OPC_DMULT_G_2F:
3965 case OPC_DMULTU_G_2E:
3966 case OPC_DMULTU_G_2F:
3967 #endif
3968 t0 = tcg_temp_new();
3969 t1 = tcg_temp_new();
3970 break;
3971 default:
3972 t0 = tcg_temp_local_new();
3973 t1 = tcg_temp_local_new();
3974 break;
3975 }
3976
3977 gen_load_gpr(t0, rs);
3978 gen_load_gpr(t1, rt);
3979
3980 switch (opc) {
3981 case OPC_MULT_G_2E:
3982 case OPC_MULT_G_2F:
3983 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3984 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3985 break;
3986 case OPC_MULTU_G_2E:
3987 case OPC_MULTU_G_2F:
3988 tcg_gen_ext32u_tl(t0, t0);
3989 tcg_gen_ext32u_tl(t1, t1);
3990 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3991 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3992 break;
3993 case OPC_DIV_G_2E:
3994 case OPC_DIV_G_2F:
3995 {
3996 TCGLabel *l1 = gen_new_label();
3997 TCGLabel *l2 = gen_new_label();
3998 TCGLabel *l3 = gen_new_label();
3999 tcg_gen_ext32s_tl(t0, t0);
4000 tcg_gen_ext32s_tl(t1, t1);
4001 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
4002 tcg_gen_movi_tl(cpu_gpr[rd], 0);
4003 tcg_gen_br(l3);
4004 gen_set_label(l1);
4005 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
4006 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
4007 tcg_gen_mov_tl(cpu_gpr[rd], t0);
4008 tcg_gen_br(l3);
4009 gen_set_label(l2);
4010 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
4011 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
4012 gen_set_label(l3);
4013 }
4014 break;
4015 case OPC_DIVU_G_2E:
4016 case OPC_DIVU_G_2F:
4017 {
4018 TCGLabel *l1 = gen_new_label();
4019 TCGLabel *l2 = gen_new_label();
4020 tcg_gen_ext32u_tl(t0, t0);
4021 tcg_gen_ext32u_tl(t1, t1);
4022 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
4023 tcg_gen_movi_tl(cpu_gpr[rd], 0);
4024 tcg_gen_br(l2);
4025 gen_set_label(l1);
4026 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
4027 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
4028 gen_set_label(l2);
4029 }
4030 break;
4031 case OPC_MOD_G_2E:
4032 case OPC_MOD_G_2F:
4033 {
4034 TCGLabel *l1 = gen_new_label();
4035 TCGLabel *l2 = gen_new_label();
4036 TCGLabel *l3 = gen_new_label();
4037 tcg_gen_ext32u_tl(t0, t0);
4038 tcg_gen_ext32u_tl(t1, t1);
4039 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4040 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
4041 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
4042 gen_set_label(l1);
4043 tcg_gen_movi_tl(cpu_gpr[rd], 0);
4044 tcg_gen_br(l3);
4045 gen_set_label(l2);
4046 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
4047 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
4048 gen_set_label(l3);
4049 }
4050 break;
4051 case OPC_MODU_G_2E:
4052 case OPC_MODU_G_2F:
4053 {
4054 TCGLabel *l1 = gen_new_label();
4055 TCGLabel *l2 = gen_new_label();
4056 tcg_gen_ext32u_tl(t0, t0);
4057 tcg_gen_ext32u_tl(t1, t1);
4058 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
4059 tcg_gen_movi_tl(cpu_gpr[rd], 0);
4060 tcg_gen_br(l2);
4061 gen_set_label(l1);
4062 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
4063 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
4064 gen_set_label(l2);
4065 }
4066 break;
4067 #if defined(TARGET_MIPS64)
4068 case OPC_DMULT_G_2E:
4069 case OPC_DMULT_G_2F:
4070 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
4071 break;
4072 case OPC_DMULTU_G_2E:
4073 case OPC_DMULTU_G_2F:
4074 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
4075 break;
4076 case OPC_DDIV_G_2E:
4077 case OPC_DDIV_G_2F:
4078 {
4079 TCGLabel *l1 = gen_new_label();
4080 TCGLabel *l2 = gen_new_label();
4081 TCGLabel *l3 = gen_new_label();
4082 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
4083 tcg_gen_movi_tl(cpu_gpr[rd], 0);
4084 tcg_gen_br(l3);
4085 gen_set_label(l1);
4086 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
4087 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
4088 tcg_gen_mov_tl(cpu_gpr[rd], t0);
4089 tcg_gen_br(l3);
4090 gen_set_label(l2);
4091 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
4092 gen_set_label(l3);
4093 }
4094 break;
4095 case OPC_DDIVU_G_2E:
4096 case OPC_DDIVU_G_2F:
4097 {
4098 TCGLabel *l1 = gen_new_label();
4099 TCGLabel *l2 = gen_new_label();
4100 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
4101 tcg_gen_movi_tl(cpu_gpr[rd], 0);
4102 tcg_gen_br(l2);
4103 gen_set_label(l1);
4104 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
4105 gen_set_label(l2);
4106 }
4107 break;
4108 case OPC_DMOD_G_2E:
4109 case OPC_DMOD_G_2F:
4110 {
4111 TCGLabel *l1 = gen_new_label();
4112 TCGLabel *l2 = gen_new_label();
4113 TCGLabel *l3 = gen_new_label();
4114 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4115 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
4116 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
4117 gen_set_label(l1);
4118 tcg_gen_movi_tl(cpu_gpr[rd], 0);
4119 tcg_gen_br(l3);
4120 gen_set_label(l2);
4121 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
4122 gen_set_label(l3);
4123 }
4124 break;
4125 case OPC_DMODU_G_2E:
4126 case OPC_DMODU_G_2F:
4127 {
4128 TCGLabel *l1 = gen_new_label();
4129 TCGLabel *l2 = gen_new_label();
4130 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
4131 tcg_gen_movi_tl(cpu_gpr[rd], 0);
4132 tcg_gen_br(l2);
4133 gen_set_label(l1);
4134 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
4135 gen_set_label(l2);
4136 }
4137 break;
4138 #endif
4139 }
4140
4141 tcg_temp_free(t0);
4142 tcg_temp_free(t1);
4143 }
4144
4145 /* Loongson multimedia instructions */
4146 static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
4147 {
4148 uint32_t opc, shift_max;
4149 TCGv_i64 t0, t1;
4150 TCGCond cond;
4151
4152 opc = MASK_LMMI(ctx->opcode);
4153 switch (opc) {
4154 case OPC_ADD_CP2:
4155 case OPC_SUB_CP2:
4156 case OPC_DADD_CP2:
4157 case OPC_DSUB_CP2:
4158 t0 = tcg_temp_local_new_i64();
4159 t1 = tcg_temp_local_new_i64();
4160 break;
4161 default:
4162 t0 = tcg_temp_new_i64();
4163 t1 = tcg_temp_new_i64();
4164 break;
4165 }
4166
4167 check_cp1_enabled(ctx);
4168 gen_load_fpr64(ctx, t0, rs);
4169 gen_load_fpr64(ctx, t1, rt);
4170
4171 switch (opc) {
4172 case OPC_PADDSH:
4173 gen_helper_paddsh(t0, t0, t1);
4174 break;
4175 case OPC_PADDUSH:
4176 gen_helper_paddush(t0, t0, t1);
4177 break;
4178 case OPC_PADDH:
4179 gen_helper_paddh(t0, t0, t1);
4180 break;
4181 case OPC_PADDW:
4182 gen_helper_paddw(t0, t0, t1);
4183 break;
4184 case OPC_PADDSB:
4185 gen_helper_paddsb(t0, t0, t1);
4186 break;
4187 case OPC_PADDUSB:
4188 gen_helper_paddusb(t0, t0, t1);
4189 break;
4190 case OPC_PADDB:
4191 gen_helper_paddb(t0, t0, t1);
4192 break;
4193
4194 case OPC_PSUBSH:
4195 gen_helper_psubsh(t0, t0, t1);
4196 break;
4197 case OPC_PSUBUSH:
4198 gen_helper_psubush(t0, t0, t1);
4199 break;
4200 case OPC_PSUBH:
4201 gen_helper_psubh(t0, t0, t1);
4202 break;
4203 case OPC_PSUBW:
4204 gen_helper_psubw(t0, t0, t1);
4205 break;
4206 case OPC_PSUBSB:
4207 gen_helper_psubsb(t0, t0, t1);
4208 break;
4209 case OPC_PSUBUSB:
4210 gen_helper_psubusb(t0, t0, t1);
4211 break;
4212 case OPC_PSUBB:
4213 gen_helper_psubb(t0, t0, t1);
4214 break;
4215
4216 case OPC_PSHUFH:
4217 gen_helper_pshufh(t0, t0, t1);
4218 break;
4219 case OPC_PACKSSWH:
4220 gen_helper_packsswh(t0, t0, t1);
4221 break;
4222 case OPC_PACKSSHB:
4223 gen_helper_packsshb(t0, t0, t1);
4224 break;
4225 case OPC_PACKUSHB:
4226 gen_helper_packushb(t0, t0, t1);
4227 break;
4228
4229 case OPC_PUNPCKLHW:
4230 gen_helper_punpcklhw(t0, t0, t1);
4231 break;
4232 case OPC_PUNPCKHHW:
4233 gen_helper_punpckhhw(t0, t0, t1);
4234 break;
4235 case OPC_PUNPCKLBH:
4236 gen_helper_punpcklbh(t0, t0, t1);
4237 break;
4238 case OPC_PUNPCKHBH:
4239 gen_helper_punpckhbh(t0, t0, t1);
4240 break;
4241 case OPC_PUNPCKLWD:
4242 gen_helper_punpcklwd(t0, t0, t1);
4243 break;
4244 case OPC_PUNPCKHWD:
4245 gen_helper_punpckhwd(t0, t0, t1);
4246 break;
4247
4248 case OPC_PAVGH:
4249 gen_helper_pavgh(t0, t0, t1);
4250 break;
4251 case OPC_PAVGB:
4252 gen_helper_pavgb(t0, t0, t1);
4253 break;
4254 case OPC_PMAXSH:
4255 gen_helper_pmaxsh(t0, t0, t1);
4256 break;
4257 case OPC_PMINSH:
4258 gen_helper_pminsh(t0, t0, t1);
4259 break;
4260 case OPC_PMAXUB:
4261 gen_helper_pmaxub(t0, t0, t1);
4262 break;
4263 case OPC_PMINUB:
4264 gen_helper_pminub(t0, t0, t1);
4265 break;
4266
4267 case OPC_PCMPEQW:
4268 gen_helper_pcmpeqw(t0, t0, t1);
4269 break;
4270 case OPC_PCMPGTW:
4271 gen_helper_pcmpgtw(t0, t0, t1);
4272 break;
4273 case OPC_PCMPEQH:
4274 gen_helper_pcmpeqh(t0, t0, t1);
4275 break;
4276 case OPC_PCMPGTH:
4277 gen_helper_pcmpgth(t0, t0, t1);
4278 break;
4279 case OPC_PCMPEQB:
4280 gen_helper_pcmpeqb(t0, t0, t1);
4281 break;
4282 case OPC_PCMPGTB:
4283 gen_helper_pcmpgtb(t0, t0, t1);
4284 break;
4285
4286 case OPC_PSLLW:
4287 gen_helper_psllw(t0, t0, t1);
4288 break;
4289 case OPC_PSLLH:
4290 gen_helper_psllh(t0, t0, t1);
4291 break;
4292 case OPC_PSRLW:
4293 gen_helper_psrlw(t0, t0, t1);
4294 break;
4295 case OPC_PSRLH:
4296 gen_helper_psrlh(t0, t0, t1);
4297 break;
4298 case OPC_PSRAW:
4299 gen_helper_psraw(t0, t0, t1);
4300 break;
4301 case OPC_PSRAH:
4302 gen_helper_psrah(t0, t0, t1);
4303 break;
4304
4305 case OPC_PMULLH:
4306 gen_helper_pmullh(t0, t0, t1);
4307 break;
4308 case OPC_PMULHH:
4309 gen_helper_pmulhh(t0, t0, t1);
4310 break;
4311 case OPC_PMULHUH:
4312 gen_helper_pmulhuh(t0, t0, t1);
4313 break;
4314 case OPC_PMADDHW:
4315 gen_helper_pmaddhw(t0, t0, t1);
4316 break;
4317
4318 case OPC_PASUBUB:
4319 gen_helper_pasubub(t0, t0, t1);
4320 break;
4321 case OPC_BIADD:
4322 gen_helper_biadd(t0, t0);
4323 break;
4324 case OPC_PMOVMSKB:
4325 gen_helper_pmovmskb(t0, t0);
4326 break;
4327
4328 case OPC_PADDD:
4329 tcg_gen_add_i64(t0, t0, t1);
4330 break;
4331 case OPC_PSUBD:
4332 tcg_gen_sub_i64(t0, t0, t1);
4333 break;
4334 case OPC_XOR_CP2:
4335 tcg_gen_xor_i64(t0, t0, t1);
4336 break;
4337 case OPC_NOR_CP2:
4338 tcg_gen_nor_i64(t0, t0, t1);
4339 break;
4340 case OPC_AND_CP2:
4341 tcg_gen_and_i64(t0, t0, t1);
4342 break;
4343 case OPC_OR_CP2:
4344 tcg_gen_or_i64(t0, t0, t1);
4345 break;
4346
4347 case OPC_PANDN:
4348 tcg_gen_andc_i64(t0, t1, t0);
4349 break;
4350
4351 case OPC_PINSRH_0:
4352 tcg_gen_deposit_i64(t0, t0, t1, 0, 16);
4353 break;
4354 case OPC_PINSRH_1:
4355 tcg_gen_deposit_i64(t0, t0, t1, 16, 16);
4356 break;
4357 case OPC_PINSRH_2:
4358 tcg_gen_deposit_i64(t0, t0, t1, 32, 16);
4359 break;
4360 case OPC_PINSRH_3:
4361 tcg_gen_deposit_i64(t0, t0, t1, 48, 16);
4362 break;
4363
4364 case OPC_PEXTRH:
4365 tcg_gen_andi_i64(t1, t1, 3);
4366 tcg_gen_shli_i64(t1, t1, 4);
4367 tcg_gen_shr_i64(t0, t0, t1);
4368 tcg_gen_ext16u_i64(t0, t0);
4369 break;
4370
4371 case OPC_ADDU_CP2:
4372 tcg_gen_add_i64(t0, t0, t1);
4373 tcg_gen_ext32s_i64(t0, t0);
4374 break;
4375 case OPC_SUBU_CP2:
4376 tcg_gen_sub_i64(t0, t0, t1);
4377 tcg_gen_ext32s_i64(t0, t0);
4378 break;
4379
4380 case OPC_SLL_CP2:
4381 shift_max = 32;
4382 goto do_shift;
4383 case OPC_SRL_CP2:
4384 shift_max = 32;
4385 goto do_shift;
4386 case OPC_SRA_CP2:
4387 shift_max = 32;
4388 goto do_shift;
4389 case OPC_DSLL_CP2:
4390 shift_max = 64;
4391 goto do_shift;
4392 case OPC_DSRL_CP2:
4393 shift_max = 64;
4394 goto do_shift;
4395 case OPC_DSRA_CP2:
4396 shift_max = 64;
4397 goto do_shift;
4398 do_shift:
4399 /* Make sure shift count isn't TCG undefined behaviour. */
4400 tcg_gen_andi_i64(t1, t1, shift_max - 1);
4401
4402 switch (opc) {
4403 case OPC_SLL_CP2:
4404 case OPC_DSLL_CP2:
4405 tcg_gen_shl_i64(t0, t0, t1);
4406 break;
4407 case OPC_SRA_CP2:
4408 case OPC_DSRA_CP2:
4409 /*
4410 * Since SRA is UndefinedResult without sign-extended inputs,
4411 * we can treat SRA and DSRA the same.
4412 */
4413 tcg_gen_sar_i64(t0, t0, t1);
4414 break;
4415 case OPC_SRL_CP2:
4416 /* We want to shift in zeros for SRL; zero-extend first. */
4417 tcg_gen_ext32u_i64(t0, t0);
4418 /* FALLTHRU */
4419 case OPC_DSRL_CP2:
4420 tcg_gen_shr_i64(t0, t0, t1);
4421 break;
4422 }
4423
4424 if (shift_max == 32) {
4425 tcg_gen_ext32s_i64(t0, t0);
4426 }
4427
4428 /* Shifts larger than MAX produce zero. */
4429 tcg_gen_setcondi_i64(TCG_COND_LTU, t1, t1, shift_max);
4430 tcg_gen_neg_i64(t1, t1);
4431 tcg_gen_and_i64(t0, t0, t1);
4432 break;
4433
4434 case OPC_ADD_CP2:
4435 case OPC_DADD_CP2:
4436 {
4437 TCGv_i64 t2 = tcg_temp_new_i64();
4438 TCGLabel *lab = gen_new_label();
4439
4440 tcg_gen_mov_i64(t2, t0);
4441 tcg_gen_add_i64(t0, t1, t2);
4442 if (opc == OPC_ADD_CP2) {
4443 tcg_gen_ext32s_i64(t0, t0);
4444 }
4445 tcg_gen_xor_i64(t1, t1, t2);
4446 tcg_gen_xor_i64(t2, t2, t0);
4447 tcg_gen_andc_i64(t1, t2, t1);
4448 tcg_temp_free_i64(t2);
4449 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab);
4450 generate_exception(ctx, EXCP_OVERFLOW);
4451 gen_set_label(lab);
4452 break;
4453 }
4454
4455 case OPC_SUB_CP2:
4456 case OPC_DSUB_CP2:
4457 {
4458 TCGv_i64 t2 = tcg_temp_new_i64();
4459 TCGLabel *lab = gen_new_label();
4460
4461 tcg_gen_mov_i64(t2, t0);
4462 tcg_gen_sub_i64(t0, t1, t2);
4463 if (opc == OPC_SUB_CP2) {
4464 tcg_gen_ext32s_i64(t0, t0);
4465 }
4466 tcg_gen_xor_i64(t1, t1, t2);
4467 tcg_gen_xor_i64(t2, t2, t0);
4468 tcg_gen_and_i64(t1, t1, t2);
4469 tcg_temp_free_i64(t2);
4470 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab);
4471 generate_exception(ctx, EXCP_OVERFLOW);
4472 gen_set_label(lab);
4473 break;
4474 }
4475
4476 case OPC_PMULUW:
4477 tcg_gen_ext32u_i64(t0, t0);
4478 tcg_gen_ext32u_i64(t1, t1);
4479 tcg_gen_mul_i64(t0, t0, t1);
4480 break;
4481
4482 case OPC_SEQU_CP2:
4483 case OPC_SEQ_CP2:
4484 cond = TCG_COND_EQ;
4485 goto do_cc_cond;
4486 break;
4487 case OPC_SLTU_CP2:
4488 cond = TCG_COND_LTU;
4489 goto do_cc_cond;
4490 break;
4491 case OPC_SLT_CP2:
4492 cond = TCG_COND_LT;
4493 goto do_cc_cond;
4494 break;
4495 case OPC_SLEU_CP2:
4496 cond = TCG_COND_LEU;
4497 goto do_cc_cond;
4498 break;
4499 case OPC_SLE_CP2:
4500 cond = TCG_COND_LE;
4501 do_cc_cond:
4502 {
4503 int cc = (ctx->opcode >> 8) & 0x7;
4504 TCGv_i64 t64 = tcg_temp_new_i64();
4505 TCGv_i32 t32 = tcg_temp_new_i32();
4506
4507 tcg_gen_setcond_i64(cond, t64, t0, t1);
4508 tcg_gen_extrl_i64_i32(t32, t64);
4509 tcg_gen_deposit_i32(fpu_fcr31, fpu_fcr31, t32,
4510 get_fp_bit(cc), 1);
4511
4512 tcg_temp_free_i32(t32);
4513 tcg_temp_free_i64(t64);
4514 }
4515 goto no_rd;
4516 break;
4517 default:
4518 MIPS_INVAL("loongson_cp2");
4519 gen_reserved_instruction(ctx);
4520 return;
4521 }
4522
4523 gen_store_fpr64(ctx, t0, rd);
4524
4525 no_rd:
4526 tcg_temp_free_i64(t0);
4527 tcg_temp_free_i64(t1);
4528 }
4529
4530 static void gen_loongson_lswc2(DisasContext *ctx, int rt,
4531 int rs, int rd)
4532 {
4533 TCGv t0, t1, t2;
4534 TCGv_i32 fp0;
4535 #if defined(TARGET_MIPS64)
4536 int lsq_rt1 = ctx->opcode & 0x1f;
4537 int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4;
4538 #endif
4539 int shf_offset = sextract32(ctx->opcode, 6, 8);
4540
4541 t0 = tcg_temp_new();
4542
4543 switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) {
4544 #if defined(TARGET_MIPS64)
4545 case OPC_GSLQ:
4546 t1 = tcg_temp_new();
4547 gen_base_offset_addr(ctx, t0, rs, lsq_offset);
4548 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ |
4549 ctx->default_tcg_memop_mask);
4550 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
4551 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
4552 ctx->default_tcg_memop_mask);
4553 gen_store_gpr(t1, rt);
4554 gen_store_gpr(t0, lsq_rt1);
4555 tcg_temp_free(t1);
4556 break;
4557 case OPC_GSLQC1:
4558 check_cp1_enabled(ctx);
4559 t1 = tcg_temp_new();
4560 gen_base_offset_addr(ctx, t0, rs, lsq_offset);
4561 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ |
4562 ctx->default_tcg_memop_mask);
4563 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
4564 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
4565 ctx->default_tcg_memop_mask);
4566 gen_store_fpr64(ctx, t1, rt);
4567 gen_store_fpr64(ctx, t0, lsq_rt1);
4568 tcg_temp_free(t1);
4569 break;
4570 case OPC_GSSQ:
4571 t1 = tcg_temp_new();
4572 gen_base_offset_addr(ctx, t0, rs, lsq_offset);
4573 gen_load_gpr(t1, rt);
4574 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
4575 ctx->default_tcg_memop_mask);
4576 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
4577 gen_load_gpr(t1, lsq_rt1);
4578 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
4579 ctx->default_tcg_memop_mask);
4580 tcg_temp_free(t1);
4581 break;
4582 case OPC_GSSQC1:
4583 check_cp1_enabled(ctx);
4584 t1 = tcg_temp_new();
4585 gen_base_offset_addr(ctx, t0, rs, lsq_offset);
4586 gen_load_fpr64(ctx, t1, rt);
4587 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
4588 ctx->default_tcg_memop_mask);
4589 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
4590 gen_load_fpr64(ctx, t1, lsq_rt1);
4591 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
4592 ctx->default_tcg_memop_mask);
4593 tcg_temp_free(t1);
4594 break;
4595 #endif
4596 case OPC_GSSHFL:
4597 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) {
4598 case OPC_GSLWLC1:
4599 check_cp1_enabled(ctx);
4600 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4601 t1 = tcg_temp_new();
4602 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
4603 tcg_gen_andi_tl(t1, t0, 3);
4604 #ifndef TARGET_WORDS_BIGENDIAN
4605 tcg_gen_xori_tl(t1, t1, 3);
4606 #endif
4607 tcg_gen_shli_tl(t1, t1, 3);
4608 tcg_gen_andi_tl(t0, t0, ~3);
4609 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
4610 tcg_gen_shl_tl(t0, t0, t1);
4611 t2 = tcg_const_tl(-1);
4612 tcg_gen_shl_tl(t2, t2, t1);
4613 fp0 = tcg_temp_new_i32();
4614 gen_load_fpr32(ctx, fp0, rt);
4615 tcg_gen_ext_i32_tl(t1, fp0);
4616 tcg_gen_andc_tl(t1, t1, t2);
4617 tcg_temp_free(t2);
4618 tcg_gen_or_tl(t0, t0, t1);
4619 tcg_temp_free(t1);
4620 #if defined(TARGET_MIPS64)
4621 tcg_gen_extrl_i64_i32(fp0, t0);
4622 #else
4623 tcg_gen_ext32s_tl(fp0, t0);
4624 #endif
4625 gen_store_fpr32(ctx, fp0, rt);
4626 tcg_temp_free_i32(fp0);
4627 break;
4628 case OPC_GSLWRC1:
4629 check_cp1_enabled(ctx);
4630 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4631 t1 = tcg_temp_new();
4632 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
4633 tcg_gen_andi_tl(t1, t0, 3);
4634 #ifdef TARGET_WORDS_BIGENDIAN
4635 tcg_gen_xori_tl(t1, t1, 3);
4636 #endif
4637 tcg_gen_shli_tl(t1, t1, 3);
4638 tcg_gen_andi_tl(t0, t0, ~3);
4639 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
4640 tcg_gen_shr_tl(t0, t0, t1);
4641 tcg_gen_xori_tl(t1, t1, 31);
4642 t2 = tcg_const_tl(0xfffffffeull);
4643 tcg_gen_shl_tl(t2, t2, t1);
4644 fp0 = tcg_temp_new_i32();
4645 gen_load_fpr32(ctx, fp0, rt);
4646 tcg_gen_ext_i32_tl(t1, fp0);
4647 tcg_gen_and_tl(t1, t1, t2);
4648 tcg_temp_free(t2);
4649 tcg_gen_or_tl(t0, t0, t1);
4650 tcg_temp_free(t1);
4651 #if defined(TARGET_MIPS64)
4652 tcg_gen_extrl_i64_i32(fp0, t0);
4653 #else
4654 tcg_gen_ext32s_tl(fp0, t0);
4655 #endif
4656 gen_store_fpr32(ctx, fp0, rt);
4657 tcg_temp_free_i32(fp0);
4658 break;
4659 #if defined(TARGET_MIPS64)
4660 case OPC_GSLDLC1:
4661 check_cp1_enabled(ctx);
4662 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4663 t1 = tcg_temp_new();
4664 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
4665 tcg_gen_andi_tl(t1, t0, 7);
4666 #ifndef TARGET_WORDS_BIGENDIAN
4667 tcg_gen_xori_tl(t1, t1, 7);
4668 #endif
4669 tcg_gen_shli_tl(t1, t1, 3);
4670 tcg_gen_andi_tl(t0, t0, ~7);
4671 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
4672 tcg_gen_shl_tl(t0, t0, t1);
4673 t2 = tcg_const_tl(-1);
4674 tcg_gen_shl_tl(t2, t2, t1);
4675 gen_load_fpr64(ctx, t1, rt);
4676 tcg_gen_andc_tl(t1, t1, t2);
4677 tcg_temp_free(t2);
4678 tcg_gen_or_tl(t0, t0, t1);
4679 tcg_temp_free(t1);
4680 gen_store_fpr64(ctx, t0, rt);
4681 break;
4682 case OPC_GSLDRC1:
4683 check_cp1_enabled(ctx);
4684 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4685 t1 = tcg_temp_new();
4686 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
4687 tcg_gen_andi_tl(t1, t0, 7);
4688 #ifdef TARGET_WORDS_BIGENDIAN
4689 tcg_gen_xori_tl(t1, t1, 7);
4690 #endif
4691 tcg_gen_shli_tl(t1, t1, 3);
4692 tcg_gen_andi_tl(t0, t0, ~7);
4693 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
4694 tcg_gen_shr_tl(t0, t0, t1);
4695 tcg_gen_xori_tl(t1, t1, 63);
4696 t2 = tcg_const_tl(0xfffffffffffffffeull);
4697 tcg_gen_shl_tl(t2, t2, t1);
4698 gen_load_fpr64(ctx, t1, rt);
4699 tcg_gen_and_tl(t1, t1, t2);
4700 tcg_temp_free(t2);
4701 tcg_gen_or_tl(t0, t0, t1);
4702 tcg_temp_free(t1);
4703 gen_store_fpr64(ctx, t0, rt);
4704 break;
4705 #endif
4706 default:
4707 MIPS_INVAL("loongson_gsshfl");
4708 gen_reserved_instruction(ctx);
4709 break;
4710 }
4711 break;
4712 case OPC_GSSHFS:
4713 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) {
4714 case OPC_GSSWLC1:
4715 check_cp1_enabled(ctx);
4716 t1 = tcg_temp_new();
4717 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4718 fp0 = tcg_temp_new_i32();
4719 gen_load_fpr32(ctx, fp0, rt);
4720 tcg_gen_ext_i32_tl(t1, fp0);
4721 gen_helper_0e2i(swl, t1, t0, ctx->mem_idx);
4722 tcg_temp_free_i32(fp0);
4723 tcg_temp_free(t1);
4724 break;
4725 case OPC_GSSWRC1:
4726 check_cp1_enabled(ctx);
4727 t1 = tcg_temp_new();
4728 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4729 fp0 = tcg_temp_new_i32();
4730 gen_load_fpr32(ctx, fp0, rt);
4731 tcg_gen_ext_i32_tl(t1, fp0);
4732 gen_helper_0e2i(swr, t1, t0, ctx->mem_idx);
4733 tcg_temp_free_i32(fp0);
4734 tcg_temp_free(t1);
4735 break;
4736 #if defined(TARGET_MIPS64)
4737 case OPC_GSSDLC1:
4738 check_cp1_enabled(ctx);
4739 t1 = tcg_temp_new();
4740 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4741 gen_load_fpr64(ctx, t1, rt);
4742 gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx);
4743 tcg_temp_free(t1);
4744 break;
4745 case OPC_GSSDRC1:
4746 check_cp1_enabled(ctx);
4747 t1 = tcg_temp_new();
4748 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4749 gen_load_fpr64(ctx, t1, rt);
4750 gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx);
4751 tcg_temp_free(t1);
4752 break;
4753 #endif
4754 default:
4755 MIPS_INVAL("loongson_gsshfs");
4756 gen_reserved_instruction(ctx);
4757 break;
4758 }
4759 break;
4760 default:
4761 MIPS_INVAL("loongson_gslsq");
4762 gen_reserved_instruction(ctx);
4763 break;
4764 }
4765 tcg_temp_free(t0);
4766 }
4767
4768 /* Loongson EXT LDC2/SDC2 */
4769 static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
4770 int rs, int rd)
4771 {
4772 int offset = sextract32(ctx->opcode, 3, 8);
4773 uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode);
4774 TCGv t0, t1;
4775 TCGv_i32 fp0;
4776
4777 /* Pre-conditions */
4778 switch (opc) {
4779 case OPC_GSLBX:
4780 case OPC_GSLHX:
4781 case OPC_GSLWX:
4782 case OPC_GSLDX:
4783 /* prefetch, implement as NOP */
4784 if (rt == 0) {
4785 return;
4786 }
4787 break;
4788 case OPC_GSSBX:
4789 case OPC_GSSHX:
4790 case OPC_GSSWX:
4791 case OPC_GSSDX:
4792 break;
4793 case OPC_GSLWXC1:
4794 #if defined(TARGET_MIPS64)
4795 case OPC_GSLDXC1:
4796 #endif
4797 check_cp1_enabled(ctx);
4798 /* prefetch, implement as NOP */
4799 if (rt == 0) {
4800 return;
4801 }
4802 break;
4803 case OPC_GSSWXC1:
4804 #if defined(TARGET_MIPS64)
4805 case OPC_GSSDXC1:
4806 #endif
4807 check_cp1_enabled(ctx);
4808 break;
4809 default:
4810 MIPS_INVAL("loongson_lsdc2");
4811 gen_reserved_instruction(ctx);
4812 return;
4813 break;
4814 }
4815
4816 t0 = tcg_temp_new();
4817
4818 gen_base_offset_addr(ctx, t0, rs, offset);
4819 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
4820
4821 switch (opc) {
4822 case OPC_GSLBX:
4823 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
4824 gen_store_gpr(t0, rt);
4825 break;
4826 case OPC_GSLHX:
4827 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
4828 ctx->default_tcg_memop_mask);
4829 gen_store_gpr(t0, rt);
4830 break;
4831 case OPC_GSLWX:
4832 gen_base_offset_addr(ctx, t0, rs, offset);
4833 if (rd) {
4834 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
4835 }
4836 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL |
4837 ctx->default_tcg_memop_mask);
4838 gen_store_gpr(t0, rt);
4839 break;
4840 #if defined(TARGET_MIPS64)
4841 case OPC_GSLDX:
4842 gen_base_offset_addr(ctx, t0, rs, offset);
4843 if (rd) {
4844 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
4845 }
4846 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
4847 ctx->default_tcg_memop_mask);
4848 gen_store_gpr(t0, rt);
4849 break;
4850 #endif
4851 case OPC_GSLWXC1:
4852 check_cp1_enabled(ctx);
4853 gen_base_offset_addr(ctx, t0, rs, offset);
4854 if (rd) {
4855 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
4856 }
4857 fp0 = tcg_temp_new_i32();
4858 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
4859 ctx->default_tcg_memop_mask);
4860 gen_store_fpr32(ctx, fp0, rt);
4861 tcg_temp_free_i32(fp0);
4862 break;
4863 #if defined(TARGET_MIPS64)
4864 case OPC_GSLDXC1:
4865 check_cp1_enabled(ctx);
4866 gen_base_offset_addr(ctx, t0, rs, offset);
4867 if (rd) {
4868 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
4869 }
4870 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
4871 ctx->default_tcg_memop_mask);
4872 gen_store_fpr64(ctx, t0, rt);
4873 break;
4874 #endif
4875 case OPC_GSSBX:
4876 t1 = tcg_temp_new();
4877 gen_load_gpr(t1, rt);
4878 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB);
4879 tcg_temp_free(t1);
4880 break;
4881 case OPC_GSSHX:
4882 t1 = tcg_temp_new();
4883 gen_load_gpr(t1, rt);
4884 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
4885 ctx->default_tcg_memop_mask);
4886 tcg_temp_free(t1);
4887 break;
4888 case OPC_GSSWX:
4889 t1 = tcg_temp_new();
4890 gen_load_gpr(t1, rt);
4891 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
4892 ctx->default_tcg_memop_mask);
4893 tcg_temp_free(t1);
4894 break;
4895 #if defined(TARGET_MIPS64)
4896 case OPC_GSSDX:
4897 t1 = tcg_temp_new();
4898 gen_load_gpr(t1, rt);
4899 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
4900 ctx->default_tcg_memop_mask);
4901 tcg_temp_free(t1);
4902 break;
4903 #endif
4904 case OPC_GSSWXC1:
4905 fp0 = tcg_temp_new_i32();
4906 gen_load_fpr32(ctx, fp0, rt);
4907 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
4908 ctx->default_tcg_memop_mask);
4909 tcg_temp_free_i32(fp0);
4910 break;
4911 #if defined(TARGET_MIPS64)
4912 case OPC_GSSDXC1:
4913 t1 = tcg_temp_new();
4914 gen_load_fpr64(ctx, t1, rt);
4915 tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEQ |
4916 ctx->default_tcg_memop_mask);
4917 tcg_temp_free(t1);
4918 break;
4919 #endif
4920 default:
4921 break;
4922 }
4923
4924 tcg_temp_free(t0);
4925 }
4926
4927 /* Traps */
4928 static void gen_trap(DisasContext *ctx, uint32_t opc,
4929 int rs, int rt, int16_t imm)
4930 {
4931 int cond;
4932 TCGv t0 = tcg_temp_new();
4933 TCGv t1 = tcg_temp_new();
4934
4935 cond = 0;
4936 /* Load needed operands */
4937 switch (opc) {
4938 case OPC_TEQ:
4939 case OPC_TGE:
4940 case OPC_TGEU:
4941 case OPC_TLT:
4942 case OPC_TLTU:
4943 case OPC_TNE:
4944 /* Compare two registers */
4945 if (rs != rt) {
4946 gen_load_gpr(t0, rs);
4947 gen_load_gpr(t1, rt);
4948 cond = 1;
4949 }
4950 break;
4951 case OPC_TEQI:
4952 case OPC_TGEI:
4953 case OPC_TGEIU:
4954 case OPC_TLTI:
4955 case OPC_TLTIU:
4956 case OPC_TNEI:
4957 /* Compare register to immediate */
4958 if (rs != 0 || imm != 0) {
4959 gen_load_gpr(t0, rs);
4960 tcg_gen_movi_tl(t1, (int32_t)imm);
4961 cond = 1;
4962 }
4963 break;
4964 }
4965 if (cond == 0) {
4966 switch (opc) {
4967 case OPC_TEQ: /* rs == rs */
4968 case OPC_TEQI: /* r0 == 0 */
4969 case OPC_TGE: /* rs >= rs */
4970 case OPC_TGEI: /* r0 >= 0 */
4971 case OPC_TGEU: /* rs >= rs unsigned */
4972 case OPC_TGEIU: /* r0 >= 0 unsigned */
4973 /* Always trap */
4974 generate_exception_end(ctx, EXCP_TRAP);
4975 break;
4976 case OPC_TLT: /* rs < rs */
4977 case OPC_TLTI: /* r0 < 0 */
4978 case OPC_TLTU: /* rs < rs unsigned */
4979 case OPC_TLTIU: /* r0 < 0 unsigned */
4980 case OPC_TNE: /* rs != rs */
4981 case OPC_TNEI: /* r0 != 0 */
4982 /* Never trap: treat as NOP. */
4983 break;
4984 }
4985 } else {
4986 TCGLabel *l1 = gen_new_label();
4987
4988 switch (opc) {
4989 case OPC_TEQ:
4990 case OPC_TEQI:
4991 tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1);
4992 break;
4993 case OPC_TGE:
4994 case OPC_TGEI:
4995 tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1);
4996 break;
4997 case OPC_TGEU:
4998 case OPC_TGEIU:
4999 tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1);
5000 break;
5001 case OPC_TLT:
5002 case OPC_TLTI:
5003 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5004 break;
5005 case OPC_TLTU:
5006 case OPC_TLTIU:
5007 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5008 break;
5009 case OPC_TNE:
5010 case OPC_TNEI:
5011 tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1);
5012 break;
5013 }
5014 generate_exception(ctx, EXCP_TRAP);
5015 gen_set_label(l1);
5016 }
5017 tcg_temp_free(t0);
5018 tcg_temp_free(t1);
5019 }
5020
5021 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
5022 {
5023 if (unlikely(ctx->base.singlestep_enabled)) {
5024 return false;
5025 }
5026
5027 #ifndef CONFIG_USER_ONLY
5028 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
5029 #else
5030 return true;
5031 #endif
5032 }
5033
5034 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
5035 {
5036 if (use_goto_tb(ctx, dest)) {
5037 tcg_gen_goto_tb(n);
5038 gen_save_pc(dest);
5039 tcg_gen_exit_tb(ctx->base.tb, n);
5040 } else {
5041 gen_save_pc(dest);
5042 if (ctx->base.singlestep_enabled) {
5043 save_cpu_state(ctx, 0);
5044 gen_helper_raise_exception_debug(cpu_env);
5045 }
5046 tcg_gen_lookup_and_goto_ptr();
5047 }
5048 }
5049
5050 /* Branches (before delay slot) */
5051 static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
5052 int insn_bytes,
5053 int rs, int rt, int32_t offset,
5054 int delayslot_size)
5055 {
5056 target_ulong btgt = -1;
5057 int blink = 0;
5058 int bcond_compute = 0;
5059 TCGv t0 = tcg_temp_new();
5060 TCGv t1 = tcg_temp_new();
5061
5062 if (ctx->hflags & MIPS_HFLAG_BMASK) {
5063 #ifdef MIPS_DEBUG_DISAS
5064 LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
5065 TARGET_FMT_lx "\n", ctx->base.pc_next);
5066 #endif
5067 gen_reserved_instruction(ctx);
5068 goto out;
5069 }
5070
5071 /* Load needed operands */
5072 switch (opc) {
5073 case OPC_BEQ:
5074 case OPC_BEQL:
5075 case OPC_BNE:
5076 case OPC_BNEL:
5077 /* Compare two registers */
5078 if (rs != rt) {
5079 gen_load_gpr(t0, rs);
5080 gen_load_gpr(t1, rt);
5081 bcond_compute = 1;
5082 }
5083 btgt = ctx->base.pc_next + insn_bytes + offset;
5084 break;
5085 case OPC_BGEZ:
5086 case OPC_BGEZAL:
5087 case OPC_BGEZALL:
5088 case OPC_BGEZL:
5089 case OPC_BGTZ:
5090 case OPC_BGTZL:
5091 case OPC_BLEZ:
5092 case OPC_BLEZL:
5093 case OPC_BLTZ:
5094 case OPC_BLTZAL:
5095 case OPC_BLTZALL:
5096 case OPC_BLTZL:
5097 /* Compare to zero */
5098 if (rs != 0) {
5099 gen_load_gpr(t0, rs);
5100 bcond_compute = 1;
5101 }
5102 btgt = ctx->base.pc_next + insn_bytes + offset;
5103 break;
5104 case OPC_BPOSGE32:
5105 #if defined(TARGET_MIPS64)
5106 case OPC_BPOSGE64:
5107 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F);
5108 #else
5109 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
5110 #endif
5111 bcond_compute = 1;
5112 btgt = ctx->base.pc_next + insn_bytes + offset;
5113 break;
5114 case OPC_J:
5115 case OPC_JAL:
5116 case OPC_JALX:
5117 /* Jump to immediate */
5118 btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) |
5119 (uint32_t)offset;
5120 break;
5121 case OPC_JR:
5122 case OPC_JALR:
5123 /* Jump to register */
5124 if (offset != 0 && offset != 16) {
5125 /*
5126 * Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
5127 * others are reserved.
5128 */
5129 MIPS_INVAL("jump hint");
5130 gen_reserved_instruction(ctx);
5131 goto out;
5132 }
5133 gen_load_gpr(btarget, rs);
5134 break;
5135 default:
5136 MIPS_INVAL("branch/jump");
5137 gen_reserved_instruction(ctx);
5138 goto out;
5139 }
5140 if (bcond_compute == 0) {
5141 /* No condition to be computed */
5142 switch (opc) {
5143 case OPC_BEQ: /* rx == rx */
5144 case OPC_BEQL: /* rx == rx likely */
5145 case OPC_BGEZ: /* 0 >= 0 */
5146 case OPC_BGEZL: /* 0 >= 0 likely */
5147 case OPC_BLEZ: /* 0 <= 0 */
5148 case OPC_BLEZL: /* 0 <= 0 likely */
5149 /* Always take */
5150 ctx->hflags |= MIPS_HFLAG_B;
5151 break;
5152 case OPC_BGEZAL: /* 0 >= 0 */
5153 case OPC_BGEZALL: /* 0 >= 0 likely */
5154 /* Always take and link */
5155 blink = 31;
5156 ctx->hflags |= MIPS_HFLAG_B;
5157 break;
5158 case OPC_BNE: /* rx != rx */
5159 case OPC_BGTZ: /* 0 > 0 */
5160 case OPC_BLTZ: /* 0 < 0 */
5161 /* Treat as NOP. */
5162 goto out;
5163 case OPC_BLTZAL: /* 0 < 0 */
5164 /*
5165 * Handle as an unconditional branch to get correct delay
5166 * slot checking.
5167 */
5168 blink = 31;
5169 btgt = ctx->base.pc_next + insn_bytes + delayslot_size;
5170 ctx->hflags |= MIPS_HFLAG_B;
5171 break;
5172 case OPC_BLTZALL: /* 0 < 0 likely */
5173 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8);
5174 /* Skip the instruction in the delay slot */
5175 ctx->base.pc_next += 4;
5176 goto out;
5177 case OPC_BNEL: /* rx != rx likely */
5178 case OPC_BGTZL: /* 0 > 0 likely */
5179 case OPC_BLTZL: /* 0 < 0 likely */
5180 /* Skip the instruction in the delay slot */
5181 ctx->base.pc_next += 4;
5182 goto out;
5183 case OPC_J:
5184 ctx->hflags |= MIPS_HFLAG_B;
5185 break;
5186 case OPC_JALX:
5187 ctx->hflags |= MIPS_HFLAG_BX;
5188 /* Fallthrough */
5189 case OPC_JAL:
5190 blink = 31;
5191 ctx->hflags |= MIPS_HFLAG_B;
5192 break;
5193 case OPC_JR:
5194 ctx->hflags |= MIPS_HFLAG_BR;
5195 break;
5196 case OPC_JALR:
5197 blink = rt;
5198 ctx->hflags |= MIPS_HFLAG_BR;
5199 break;
5200 default:
5201 MIPS_INVAL("branch/jump");
5202 gen_reserved_instruction(ctx);
5203 goto out;
5204 }
5205 } else {
5206 switch (opc) {
5207 case OPC_BEQ:
5208 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
5209 goto not_likely;
5210 case OPC_BEQL:
5211 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
5212 goto likely;
5213 case OPC_BNE:
5214 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
5215 goto not_likely;
5216 case OPC_BNEL:
5217 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
5218 goto likely;
5219 case OPC_BGEZ:
5220 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
5221 goto not_likely;
5222 case OPC_BGEZL:
5223 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
5224 goto likely;
5225 case OPC_BGEZAL:
5226 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
5227 blink = 31;
5228 goto not_likely;
5229 case OPC_BGEZALL:
5230 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
5231 blink = 31;
5232 goto likely;
5233 case OPC_BGTZ:
5234 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0);
5235 goto not_likely;
5236 case OPC_BGTZL:
5237 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0);
5238 goto likely;
5239 case OPC_BLEZ:
5240 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0);
5241 goto not_likely;
5242 case OPC_BLEZL:
5243 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0);
5244 goto likely;
5245 case OPC_BLTZ:
5246 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
5247 goto not_likely;
5248 case OPC_BLTZL:
5249 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
5250 goto likely;
5251 case OPC_BPOSGE32:
5252 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32);
5253 goto not_likely;
5254 #if defined(TARGET_MIPS64)
5255 case OPC_BPOSGE64:
5256 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64);
5257 goto not_likely;
5258 #endif
5259 case OPC_BLTZAL:
5260 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
5261 blink = 31;
5262 not_likely:
5263 ctx->hflags |= MIPS_HFLAG_BC;
5264 break;
5265 case OPC_BLTZALL:
5266 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
5267 blink = 31;
5268 likely:
5269 ctx->hflags |= MIPS_HFLAG_BL;
5270 break;
5271 default:
5272 MIPS_INVAL("conditional branch/jump");
5273 gen_reserved_instruction(ctx);
5274 goto out;
5275 }
5276 }
5277
5278 ctx->btarget = btgt;
5279
5280 switch (delayslot_size) {
5281 case 2:
5282 ctx->hflags |= MIPS_HFLAG_BDS16;
5283 break;
5284 case 4:
5285 ctx->hflags |= MIPS_HFLAG_BDS32;
5286 break;
5287 }
5288
5289 if (blink > 0) {
5290 int post_delay = insn_bytes + delayslot_size;
5291 int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
5292
5293 tcg_gen_movi_tl(cpu_gpr[blink],
5294 ctx->base.pc_next + post_delay + lowbit);
5295 }
5296
5297 out:
5298 if (insn_bytes == 2) {
5299 ctx->hflags |= MIPS_HFLAG_B16;
5300 }
5301 tcg_temp_free(t0);
5302 tcg_temp_free(t1);
5303 }
5304
5305
5306 /* nanoMIPS Branches */
5307 static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
5308 int insn_bytes,
5309 int rs, int rt, int32_t offset)
5310 {
5311 target_ulong btgt = -1;
5312 int bcond_compute = 0;
5313 TCGv t0 = tcg_temp_new();
5314 TCGv t1 = tcg_temp_new();
5315
5316 /* Load needed operands */
5317 switch (opc) {
5318 case OPC_BEQ:
5319 case OPC_BNE:
5320 /* Compare two registers */
5321 if (rs != rt) {
5322 gen_load_gpr(t0, rs);
5323 gen_load_gpr(t1, rt);
5324 bcond_compute = 1;
5325 }
5326 btgt = ctx->base.pc_next + insn_bytes + offset;
5327 break;
5328 case OPC_BGEZAL:
5329 /* Compare to zero */
5330 if (rs != 0) {
5331 gen_load_gpr(t0, rs);
5332 bcond_compute = 1;
5333 }
5334 btgt = ctx->base.pc_next + insn_bytes + offset;
5335 break;
5336 case OPC_BPOSGE32:
5337 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
5338 bcond_compute = 1;
5339 btgt = ctx->base.pc_next + insn_bytes + offset;
5340 break;
5341 case OPC_JR:
5342 case OPC_JALR:
5343 /* Jump to register */
5344 if (offset != 0 && offset != 16) {
5345 /*
5346 * Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
5347 * others are reserved.
5348 */
5349 MIPS_INVAL("jump hint");
5350 gen_reserved_instruction(ctx);
5351 goto out;
5352 }
5353 gen_load_gpr(btarget, rs);
5354 break;
5355 default:
5356 MIPS_INVAL("branch/jump");
5357 gen_reserved_instruction(ctx);
5358 goto out;
5359 }
5360 if (bcond_compute == 0) {
5361 /* No condition to be computed */
5362 switch (opc) {
5363 case OPC_BEQ: /* rx == rx */
5364 /* Always take */
5365 ctx->hflags |= MIPS_HFLAG_B;
5366 break;
5367 case OPC_BGEZAL: /* 0 >= 0 */
5368 /* Always take and link */
5369 tcg_gen_movi_tl(cpu_gpr[31],
5370 ctx->base.pc_next + insn_bytes);
5371 ctx->hflags |= MIPS_HFLAG_B;
5372 break;
5373 case OPC_BNE: /* rx != rx */
5374 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8);
5375 /* Skip the instruction in the delay slot */
5376 ctx->base.pc_next += 4;
5377 goto out;
5378 case OPC_JR:
5379 ctx->hflags |= MIPS_HFLAG_BR;
5380 break;
5381 case OPC_JALR:
5382 if (rt > 0) {
5383 tcg_gen_movi_tl(cpu_gpr[rt],
5384 ctx->base.pc_next + insn_bytes);
5385 }
5386 ctx->hflags |= MIPS_HFLAG_BR;
5387 break;
5388 default:
5389 MIPS_INVAL("branch/jump");
5390 gen_reserved_instruction(ctx);
5391 goto out;
5392 }
5393 } else {
5394 switch (opc) {
5395 case OPC_BEQ:
5396 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
5397 goto not_likely;
5398 case OPC_BNE:
5399 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
5400 goto not_likely;
5401 case OPC_BGEZAL:
5402 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
5403 tcg_gen_movi_tl(cpu_gpr[31],
5404 ctx->base.pc_next + insn_bytes);
5405 goto not_likely;
5406 case OPC_BPOSGE32:
5407 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32);
5408 not_likely:
5409 ctx->hflags |= MIPS_HFLAG_BC;
5410 break;
5411 default:
5412 MIPS_INVAL("conditional branch/jump");
5413 gen_reserved_instruction(ctx);
5414 goto out;
5415 }
5416 }
5417
5418 ctx->btarget = btgt;
5419
5420 out:
5421 if (insn_bytes == 2) {
5422 ctx->hflags |= MIPS_HFLAG_B16;
5423 }
5424 tcg_temp_free(t0);
5425 tcg_temp_free(t1);
5426 }
5427
5428
5429 /* special3 bitfield operations */
5430 static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt,
5431 int rs, int lsb, int msb)
5432 {
5433 TCGv t0 = tcg_temp_new();
5434 TCGv t1 = tcg_temp_new();
5435
5436 gen_load_gpr(t1, rs);
5437 switch (opc) {
5438 case OPC_EXT:
5439 if (lsb + msb > 31) {
5440 goto fail;
5441 }
5442 if (msb != 31) {
5443 tcg_gen_extract_tl(t0, t1, lsb, msb + 1);
5444 } else {
5445 /*
5446 * The two checks together imply that lsb == 0,
5447 * so this is a simple sign-extension.
5448 */
5449 tcg_gen_ext32s_tl(t0, t1);
5450 }
5451 break;
5452 #if defined(TARGET_MIPS64)
5453 case OPC_DEXTU:
5454 lsb += 32;
5455 goto do_dext;
5456 case OPC_DEXTM:
5457 msb += 32;
5458 goto do_dext;
5459 case OPC_DEXT:
5460 do_dext:
5461 if (lsb + msb > 63) {
5462 goto fail;
5463 }
5464 tcg_gen_extract_tl(t0, t1, lsb, msb + 1);
5465 break;
5466 #endif
5467 case OPC_INS:
5468 if (lsb > msb) {
5469 goto fail;
5470 }
5471 gen_load_gpr(t0, rt);
5472 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
5473 tcg_gen_ext32s_tl(t0, t0);
5474 break;
5475 #if defined(TARGET_MIPS64)
5476 case OPC_DINSU:
5477 lsb += 32;
5478 /* FALLTHRU */
5479 case OPC_DINSM:
5480 msb += 32;
5481 /* FALLTHRU */
5482 case OPC_DINS:
5483 if (lsb > msb) {
5484 goto fail;
5485 }
5486 gen_load_gpr(t0, rt);
5487 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
5488 break;
5489 #endif
5490 default:
5491 fail:
5492 MIPS_INVAL("bitops");
5493 gen_reserved_instruction(ctx);
5494 tcg_temp_free(t0);
5495 tcg_temp_free(t1);
5496 return;
5497 }
5498 gen_store_gpr(t0, rt);
5499 tcg_temp_free(t0);
5500 tcg_temp_free(t1);
5501 }
5502
5503 static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
5504 {
5505 TCGv t0;
5506
5507 if (rd == 0) {
5508 /* If no destination, treat it as a NOP. */
5509 return;
5510 }
5511
5512 t0 = tcg_temp_new();
5513 gen_load_gpr(t0, rt);
5514 switch (op2) {
5515 case OPC_WSBH:
5516 {
5517 TCGv t1 = tcg_temp_new();
5518 TCGv t2 = tcg_const_tl(0x00FF00FF);
5519
5520 tcg_gen_shri_tl(t1, t0, 8);
5521 tcg_gen_and_tl(t1, t1, t2);
5522 tcg_gen_and_tl(t0, t0, t2);
5523 tcg_gen_shli_tl(t0, t0, 8);
5524 tcg_gen_or_tl(t0, t0, t1);
5525 tcg_temp_free(t2);
5526 tcg_temp_free(t1);
5527 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
5528 }
5529 break;
5530 case OPC_SEB:
5531 tcg_gen_ext8s_tl(cpu_gpr[rd], t0);
5532 break;
5533 case OPC_SEH:
5534 tcg_gen_ext16s_tl(cpu_gpr[rd], t0);
5535 break;
5536 #if defined(TARGET_MIPS64)
5537 case OPC_DSBH:
5538 {
5539 TCGv t1 = tcg_temp_new();
5540 TCGv t2 = tcg_const_tl(0x00FF00FF00FF00FFULL);
5541
5542 tcg_gen_shri_tl(t1, t0, 8);
5543 tcg_gen_and_tl(t1, t1, t2);
5544 tcg_gen_and_tl(t0, t0, t2);
5545 tcg_gen_shli_tl(t0, t0, 8);
5546 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
5547 tcg_temp_free(t2);
5548 tcg_temp_free(t1);
5549 }
5550 break;
5551 case OPC_DSHD:
5552 {
5553 TCGv t1 = tcg_temp_new();
5554 TCGv t2 = tcg_const_tl(0x0000FFFF0000FFFFULL);
5555
5556 tcg_gen_shri_tl(t1, t0, 16);
5557 tcg_gen_and_tl(t1, t1, t2);
5558 tcg_gen_and_tl(t0, t0, t2);
5559 tcg_gen_shli_tl(t0, t0, 16);
5560 tcg_gen_or_tl(t0, t0, t1);
5561 tcg_gen_shri_tl(t1, t0, 32);
5562 tcg_gen_shli_tl(t0, t0, 32);
5563 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
5564 tcg_temp_free(t2);
5565 tcg_temp_free(t1);
5566 }
5567 break;
5568 #endif
5569 default:
5570 MIPS_INVAL("bsfhl");
5571 gen_reserved_instruction(ctx);
5572 tcg_temp_free(t0);
5573 return;
5574 }
5575 tcg_temp_free(t0);
5576 }
5577
5578 static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
5579 int rt, int bits)
5580 {
5581 TCGv t0;
5582 if (rd == 0) {
5583 /* Treat as NOP. */
5584 return;
5585 }
5586 t0 = tcg_temp_new();
5587 if (bits == 0 || bits == wordsz) {
5588 if (bits == 0) {
5589 gen_load_gpr(t0, rt);
5590 } else {
5591 gen_load_gpr(t0, rs);
5592 }
5593 switch (wordsz) {
5594 case 32:
5595 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
5596 break;
5597 #if defined(TARGET_MIPS64)
5598 case 64:
5599 tcg_gen_mov_tl(cpu_gpr[rd], t0);
5600 break;
5601 #endif
5602 }
5603 } else {
5604 TCGv t1 = tcg_temp_new();
5605 gen_load_gpr(t0, rt);
5606 gen_load_gpr(t1, rs);
5607 switch (wordsz) {
5608 case 32:
5609 {
5610 TCGv_i64 t2 = tcg_temp_new_i64();
5611 tcg_gen_concat_tl_i64(t2, t1, t0);
5612 tcg_gen_shri_i64(t2, t2, 32 - bits);
5613 gen_move_low32(cpu_gpr[rd], t2);
5614 tcg_temp_free_i64(t2);
5615 }
5616 break;
5617 #if defined(TARGET_MIPS64)
5618 case 64:
5619 tcg_gen_shli_tl(t0, t0, bits);
5620 tcg_gen_shri_tl(t1, t1, 64 - bits);
5621 tcg_gen_or_tl(cpu_gpr[rd], t1, t0);
5622 break;
5623 #endif
5624 }
5625 tcg_temp_free(t1);
5626 }
5627
5628 tcg_temp_free(t0);
5629 }
5630
5631 static void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt,
5632 int bp)
5633 {
5634 gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8);
5635 }
5636
5637 static void gen_ext(DisasContext *ctx, int wordsz, int rd, int rs, int rt,
5638 int shift)
5639 {
5640 gen_align_bits(ctx, wordsz, rd, rs, rt, wordsz - shift);
5641 }
5642
5643 static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt)
5644 {
5645 TCGv t0;
5646 if (rd == 0) {
5647 /* Treat as NOP. */
5648 return;
5649 }
5650 t0 = tcg_temp_new();
5651 gen_load_gpr(t0, rt);
5652 switch (opc) {
5653 case OPC_BITSWAP:
5654 gen_helper_bitswap(cpu_gpr[rd], t0);
5655 break;
5656 #if defined(TARGET_MIPS64)
5657 case OPC_DBITSWAP:
5658 gen_helper_dbitswap(cpu_gpr[rd], t0);
5659 break;
5660 #endif
5661 }
5662 tcg_temp_free(t0);
5663 }
5664
5665 #ifndef CONFIG_USER_ONLY
5666 /* CP0 (MMU and control) */
5667 static inline void gen_mthc0_entrylo(TCGv arg, target_ulong off)
5668 {
5669 TCGv_i64 t0 = tcg_temp_new_i64();
5670 TCGv_i64 t1 = tcg_temp_new_i64();
5671
5672 tcg_gen_ext_tl_i64(t0, arg);
5673 tcg_gen_ld_i64(t1, cpu_env, off);
5674 #if defined(TARGET_MIPS64)
5675 tcg_gen_deposit_i64(t1, t1, t0, 30, 32);
5676 #else
5677 tcg_gen_concat32_i64(t1, t1, t0);
5678 #endif
5679 tcg_gen_st_i64(t1, cpu_env, off);
5680 tcg_temp_free_i64(t1);
5681 tcg_temp_free_i64(t0);
5682 }
5683
5684 static inline void gen_mthc0_store64(TCGv arg, target_ulong off)
5685 {
5686 TCGv_i64 t0 = tcg_temp_new_i64();
5687 TCGv_i64 t1 = tcg_temp_new_i64();
5688
5689 tcg_gen_ext_tl_i64(t0, arg);
5690 tcg_gen_ld_i64(t1, cpu_env, off);
5691 tcg_gen_concat32_i64(t1, t1, t0);
5692 tcg_gen_st_i64(t1, cpu_env, off);
5693 tcg_temp_free_i64(t1);
5694 tcg_temp_free_i64(t0);
5695 }
5696
5697 static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off)
5698 {
5699 TCGv_i64 t0 = tcg_temp_new_i64();
5700
5701 tcg_gen_ld_i64(t0, cpu_env, off);
5702 #if defined(TARGET_MIPS64)
5703 tcg_gen_shri_i64(t0, t0, 30);
5704 #else
5705 tcg_gen_shri_i64(t0, t0, 32);
5706 #endif
5707 gen_move_low32(arg, t0);
5708 tcg_temp_free_i64(t0);
5709 }
5710
5711 static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift)
5712 {
5713 TCGv_i64 t0 = tcg_temp_new_i64();
5714
5715 tcg_gen_ld_i64(t0, cpu_env, off);
5716 tcg_gen_shri_i64(t0, t0, 32 + shift);
5717 gen_move_low32(arg, t0);
5718 tcg_temp_free_i64(t0);
5719 }
5720
5721 static inline void gen_mfc0_load32(TCGv arg, target_ulong off)
5722 {
5723 TCGv_i32 t0 = tcg_temp_new_i32();
5724
5725 tcg_gen_ld_i32(t0, cpu_env, off);
5726 tcg_gen_ext_i32_tl(arg, t0);
5727 tcg_temp_free_i32(t0);
5728 }
5729
5730 static inline void gen_mfc0_load64(TCGv arg, target_ulong off)
5731 {
5732 tcg_gen_ld_tl(arg, cpu_env, off);
5733 tcg_gen_ext32s_tl(arg, arg);
5734 }
5735
5736 static inline void gen_mtc0_store32(TCGv arg, target_ulong off)
5737 {
5738 TCGv_i32 t0 = tcg_temp_new_i32();
5739
5740 tcg_gen_trunc_tl_i32(t0, arg);
5741 tcg_gen_st_i32(t0, cpu_env, off);
5742 tcg_temp_free_i32(t0);
5743 }
5744
5745 #define CP0_CHECK(c) \
5746 do { \
5747 if (!(c)) { \
5748 goto cp0_unimplemented; \
5749 } \
5750 } while (0)
5751
5752 static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
5753 {
5754 const char *register_name = "invalid";
5755
5756 switch (reg) {
5757 case CP0_REGISTER_02:
5758 switch (sel) {
5759 case 0:
5760 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
5761 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
5762 register_name = "EntryLo0";
5763 break;
5764 default:
5765 goto cp0_unimplemented;
5766 }
5767 break;
5768 case CP0_REGISTER_03:
5769 switch (sel) {
5770 case CP0_REG03__ENTRYLO1:
5771 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
5772 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
5773 register_name = "EntryLo1";
5774 break;
5775 default:
5776 goto cp0_unimplemented;
5777 }
5778 break;
5779 case CP0_REGISTER_09:
5780 switch (sel) {
5781 case CP0_REG09__SAAR:
5782 CP0_CHECK(ctx->saar);
5783 gen_helper_mfhc0_saar(arg, cpu_env);
5784 register_name = "SAAR";
5785 break;
5786 default:
5787 goto cp0_unimplemented;
5788 }
5789 break;
5790 case CP0_REGISTER_17:
5791 switch (sel) {
5792 case CP0_REG17__LLADDR:
5793 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr),
5794 ctx->CP0_LLAddr_shift);
5795 register_name = "LLAddr";
5796 break;
5797 case CP0_REG17__MAAR:
5798 CP0_CHECK(ctx->mrp);
5799 gen_helper_mfhc0_maar(arg, cpu_env);
5800 register_name = "MAAR";
5801 break;
5802 default:
5803 goto cp0_unimplemented;
5804 }
5805 break;
5806 case CP0_REGISTER_19:
5807 switch (sel) {
5808 case CP0_REG19__WATCHHI0:
5809 case CP0_REG19__WATCHHI1:
5810 case CP0_REG19__WATCHHI2:
5811 case CP0_REG19__WATCHHI3:
5812 case CP0_REG19__WATCHHI4:
5813 case CP0_REG19__WATCHHI5:
5814 case CP0_REG19__WATCHHI6:
5815 case CP0_REG19__WATCHHI7:
5816 /* upper 32 bits are only available when Config5MI != 0 */
5817 CP0_CHECK(ctx->mi);
5818 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_WatchHi[sel]), 0);
5819 register_name = "WatchHi";
5820 break;
5821 default:
5822 goto cp0_unimplemented;
5823 }
5824 break;
5825 case CP0_REGISTER_28:
5826 switch (sel) {
5827 case 0:
5828 case 2:
5829 case 4:
5830 case 6:
5831 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_TagLo), 0);
5832 register_name = "TagLo";
5833 break;
5834 default:
5835 goto cp0_unimplemented;
5836 }
5837 break;
5838 default:
5839 goto cp0_unimplemented;
5840 }
5841 trace_mips_translate_c0("mfhc0", register_name, reg, sel);
5842 return;
5843
5844 cp0_unimplemented:
5845 qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n",
5846 register_name, reg, sel);
5847 tcg_gen_movi_tl(arg, 0);
5848 }
5849
5850 static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
5851 {
5852 const char *register_name = "invalid";
5853 uint64_t mask = ctx->PAMask >> 36;
5854
5855 switch (reg) {
5856 case CP0_REGISTER_02:
5857 switch (sel) {
5858 case 0:
5859 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
5860 tcg_gen_andi_tl(arg, arg, mask);
5861 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
5862 register_name = "EntryLo0";
5863 break;
5864 default:
5865 goto cp0_unimplemented;
5866 }
5867 break;
5868 case CP0_REGISTER_03:
5869 switch (sel) {
5870 case CP0_REG03__ENTRYLO1:
5871 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
5872 tcg_gen_andi_tl(arg, arg, mask);
5873 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
5874 register_name = "EntryLo1";
5875 break;
5876 default:
5877 goto cp0_unimplemented;
5878 }
5879 break;
5880 case CP0_REGISTER_09:
5881 switch (sel) {
5882 case CP0_REG09__SAAR:
5883 CP0_CHECK(ctx->saar);
5884 gen_helper_mthc0_saar(cpu_env, arg);
5885 register_name = "SAAR";
5886 break;
5887 default:
5888 goto cp0_unimplemented;
5889 }
5890 break;
5891 case CP0_REGISTER_17:
5892 switch (sel) {
5893 case CP0_REG17__LLADDR:
5894 /*
5895 * LLAddr is read-only (the only exception is bit 0 if LLB is
5896 * supported); the CP0_LLAddr_rw_bitmask does not seem to be
5897 * relevant for modern MIPS cores supporting MTHC0, therefore
5898 * treating MTHC0 to LLAddr as NOP.
5899 */
5900 register_name = "LLAddr";
5901 break;
5902 case CP0_REG17__MAAR:
5903 CP0_CHECK(ctx->mrp);
5904 gen_helper_mthc0_maar(cpu_env, arg);
5905 register_name = "MAAR";
5906 break;
5907 default:
5908 goto cp0_unimplemented;
5909 }
5910 break;
5911 case CP0_REGISTER_19:
5912 switch (sel) {
5913 case CP0_REG19__WATCHHI0:
5914 case CP0_REG19__WATCHHI1:
5915 case CP0_REG19__WATCHHI2:
5916 case CP0_REG19__WATCHHI3:
5917 case CP0_REG19__WATCHHI4:
5918 case CP0_REG19__WATCHHI5:
5919 case CP0_REG19__WATCHHI6:
5920 case CP0_REG19__WATCHHI7:
5921 /* upper 32 bits are only available when Config5MI != 0 */
5922 CP0_CHECK(ctx->mi);
5923 gen_helper_0e1i(mthc0_watchhi, arg, sel);
5924 register_name = "WatchHi";
5925 break;
5926 default:
5927 goto cp0_unimplemented;
5928 }
5929 break;
5930 case CP0_REGISTER_28:
5931 switch (sel) {
5932 case 0:
5933 case 2:
5934 case 4:
5935 case 6:
5936 tcg_gen_andi_tl(arg, arg, mask);
5937 gen_mthc0_store64(arg, offsetof(CPUMIPSState, CP0_TagLo));
5938 register_name = "TagLo";
5939 break;
5940 default:
5941 goto cp0_unimplemented;
5942 }
5943 break;
5944 default:
5945 goto cp0_unimplemented;
5946 }
5947 trace_mips_translate_c0("mthc0", register_name, reg, sel);
5948
5949 cp0_unimplemented:
5950 qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n",
5951 register_name, reg, sel);
5952 }
5953
5954 static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
5955 {
5956 if (ctx->insn_flags & ISA_MIPS_R6) {
5957 tcg_gen_movi_tl(arg, 0);
5958 } else {
5959 tcg_gen_movi_tl(arg, ~0);
5960 }
5961 }
5962
5963 static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
5964 {
5965 const char *register_name = "invalid";
5966
5967 if (sel != 0) {
5968 check_insn(ctx, ISA_MIPS_R1);
5969 }
5970
5971 switch (reg) {
5972 case CP0_REGISTER_00:
5973 switch (sel) {
5974 case CP0_REG00__INDEX:
5975 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
5976 register_name = "Index";
5977 break;
5978 case CP0_REG00__MVPCONTROL:
5979 CP0_CHECK(ctx->insn_flags & ASE_MT);
5980 gen_helper_mfc0_mvpcontrol(arg, cpu_env);
5981 register_name = "MVPControl";
5982 break;
5983 case CP0_REG00__MVPCONF0:
5984 CP0_CHECK(ctx->insn_flags & ASE_MT);
5985 gen_helper_mfc0_mvpconf0(arg, cpu_env);
5986 register_name = "MVPConf0";
5987 break;
5988 case CP0_REG00__MVPCONF1:
5989 CP0_CHECK(ctx->insn_flags & ASE_MT);
5990 gen_helper_mfc0_mvpconf1(arg, cpu_env);
5991 register_name = "MVPConf1";
5992 break;
5993 case CP0_REG00__VPCONTROL:
5994 CP0_CHECK(ctx->vp);
5995 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
5996 register_name = "VPControl";
5997 break;
5998 default:
5999 goto cp0_unimplemented;
6000 }
6001 break;
6002 case CP0_REGISTER_01:
6003 switch (sel) {
6004 case CP0_REG01__RANDOM:
6005 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
6006 gen_helper_mfc0_random(arg, cpu_env);
6007 register_name = "Random";
6008 break;
6009 case CP0_REG01__VPECONTROL:
6010 CP0_CHECK(ctx->insn_flags & ASE_MT);
6011 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
6012 register_name = "VPEControl";
6013 break;
6014 case CP0_REG01__VPECONF0:
6015 CP0_CHECK(ctx->insn_flags & ASE_MT);
6016 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
6017 register_name = "VPEConf0";
6018 break;
6019 case CP0_REG01__VPECONF1:
6020 CP0_CHECK(ctx->insn_flags & ASE_MT);
6021 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
6022 register_name = "VPEConf1";
6023 break;
6024 case CP0_REG01__YQMASK:
6025 CP0_CHECK(ctx->insn_flags & ASE_MT);
6026 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
6027 register_name = "YQMask";
6028 break;
6029 case CP0_REG01__VPESCHEDULE:
6030 CP0_CHECK(ctx->insn_flags & ASE_MT);
6031 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
6032 register_name = "VPESchedule";
6033 break;
6034 case CP0_REG01__VPESCHEFBACK:
6035 CP0_CHECK(ctx->insn_flags & ASE_MT);
6036 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
6037 register_name = "VPEScheFBack";
6038 break;
6039 case CP0_REG01__VPEOPT:
6040 CP0_CHECK(ctx->insn_flags & ASE_MT);
6041 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
6042 register_name = "VPEOpt";
6043 break;
6044 default:
6045 goto cp0_unimplemented;
6046 }
6047 break;
6048 case CP0_REGISTER_02:
6049 switch (sel) {
6050 case CP0_REG02__ENTRYLO0:
6051 {
6052 TCGv_i64 tmp = tcg_temp_new_i64();
6053 tcg_gen_ld_i64(tmp, cpu_env,
6054 offsetof(CPUMIPSState, CP0_EntryLo0));
6055 #if defined(TARGET_MIPS64)
6056 if (ctx->rxi) {
6057 /* Move RI/XI fields to bits 31:30 */
6058 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI);
6059 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2);
6060 }
6061 #endif
6062 gen_move_low32(arg, tmp);
6063 tcg_temp_free_i64(tmp);
6064 }
6065 register_name = "EntryLo0";
6066 break;
6067 case CP0_REG02__TCSTATUS:
6068 CP0_CHECK(ctx->insn_flags & ASE_MT);
6069 gen_helper_mfc0_tcstatus(arg, cpu_env);
6070 register_name = "TCStatus";
6071 break;
6072 case CP0_REG02__TCBIND:
6073 CP0_CHECK(ctx->insn_flags & ASE_MT);
6074 gen_helper_mfc0_tcbind(arg, cpu_env);
6075 register_name = "TCBind";
6076 break;
6077 case CP0_REG02__TCRESTART:
6078 CP0_CHECK(ctx->insn_flags & ASE_MT);
6079 gen_helper_mfc0_tcrestart(arg, cpu_env);
6080 register_name = "TCRestart";
6081 break;
6082 case CP0_REG02__TCHALT:
6083 CP0_CHECK(ctx->insn_flags & ASE_MT);
6084 gen_helper_mfc0_tchalt(arg, cpu_env);
6085 register_name = "TCHalt";
6086 break;
6087 case CP0_REG02__TCCONTEXT:
6088 CP0_CHECK(ctx->insn_flags & ASE_MT);
6089 gen_helper_mfc0_tccontext(arg, cpu_env);
6090 register_name = "TCContext";
6091 break;
6092 case CP0_REG02__TCSCHEDULE:
6093 CP0_CHECK(ctx->insn_flags & ASE_MT);
6094 gen_helper_mfc0_tcschedule(arg, cpu_env);
6095 register_name = "TCSchedule";
6096 break;
6097 case CP0_REG02__TCSCHEFBACK:
6098 CP0_CHECK(ctx->insn_flags & ASE_MT);
6099 gen_helper_mfc0_tcschefback(arg, cpu_env);
6100 register_name = "TCScheFBack";
6101 break;
6102 default:
6103 goto cp0_unimplemented;
6104 }
6105 break;
6106 case CP0_REGISTER_03:
6107 switch (sel) {
6108 case CP0_REG03__ENTRYLO1:
6109 {
6110 TCGv_i64 tmp = tcg_temp_new_i64();
6111 tcg_gen_ld_i64(tmp, cpu_env,
6112 offsetof(CPUMIPSState, CP0_EntryLo1));
6113 #if defined(TARGET_MIPS64)
6114 if (ctx->rxi) {
6115 /* Move RI/XI fields to bits 31:30 */
6116 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI);
6117 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2);
6118 }
6119 #endif
6120 gen_move_low32(arg, tmp);
6121 tcg_temp_free_i64(tmp);
6122 }
6123 register_name = "EntryLo1";
6124 break;
6125 case CP0_REG03__GLOBALNUM:
6126 CP0_CHECK(ctx->vp);
6127 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
6128 register_name = "GlobalNumber";
6129 break;
6130 default:
6131 goto cp0_unimplemented;
6132 }
6133 break;
6134 case CP0_REGISTER_04:
6135 switch (sel) {
6136 case CP0_REG04__CONTEXT:
6137 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
6138 tcg_gen_ext32s_tl(arg, arg);
6139 register_name = "Context";
6140 break;
6141 case CP0_REG04__CONTEXTCONFIG:
6142 /* SmartMIPS ASE */
6143 /* gen_helper_mfc0_contextconfig(arg); */
6144 register_name = "ContextConfig";
6145 goto cp0_unimplemented;
6146 case CP0_REG04__USERLOCAL:
6147 CP0_CHECK(ctx->ulri);
6148 tcg_gen_ld_tl(arg, cpu_env,
6149 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
6150 tcg_gen_ext32s_tl(arg, arg);
6151 register_name = "UserLocal";
6152 break;
6153 case CP0_REG04__MMID:
6154 CP0_CHECK(ctx->mi);
6155 gen_helper_mtc0_memorymapid(cpu_env, arg);
6156 register_name = "MMID";
6157 break;
6158 default:
6159 goto cp0_unimplemented;
6160 }
6161 break;
6162 case CP0_REGISTER_05:
6163 switch (sel) {
6164 case CP0_REG05__PAGEMASK:
6165 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
6166 register_name = "PageMask";
6167 break;
6168 case CP0_REG05__PAGEGRAIN:
6169 check_insn(ctx, ISA_MIPS_R2);
6170 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
6171 register_name = "PageGrain";
6172 break;
6173 case CP0_REG05__SEGCTL0:
6174 CP0_CHECK(ctx->sc);
6175 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
6176 tcg_gen_ext32s_tl(arg, arg);
6177 register_name = "SegCtl0";
6178 break;
6179 case CP0_REG05__SEGCTL1:
6180 CP0_CHECK(ctx->sc);
6181 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
6182 tcg_gen_ext32s_tl(arg, arg);
6183 register_name = "SegCtl1";
6184 break;
6185 case CP0_REG05__SEGCTL2:
6186 CP0_CHECK(ctx->sc);
6187 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
6188 tcg_gen_ext32s_tl(arg, arg);
6189 register_name = "SegCtl2";
6190 break;
6191 case CP0_REG05__PWBASE:
6192 check_pw(ctx);
6193 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
6194 register_name = "PWBase";
6195 break;
6196 case CP0_REG05__PWFIELD:
6197 check_pw(ctx);
6198 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));
6199 register_name = "PWField";
6200 break;
6201 case CP0_REG05__PWSIZE:
6202 check_pw(ctx);
6203 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize));
6204 register_name = "PWSize";
6205 break;
6206 default:
6207 goto cp0_unimplemented;
6208 }
6209 break;
6210 case CP0_REGISTER_06:
6211 switch (sel) {
6212 case CP0_REG06__WIRED:
6213 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
6214 register_name = "Wired";
6215 break;
6216 case CP0_REG06__SRSCONF0:
6217 check_insn(ctx, ISA_MIPS_R2);
6218 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
6219 register_name = "SRSConf0";
6220 break;
6221 case CP0_REG06__SRSCONF1:
6222 check_insn(ctx, ISA_MIPS_R2);
6223 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
6224 register_name = "SRSConf1";
6225 break;
6226 case CP0_REG06__SRSCONF2:
6227 check_insn(ctx, ISA_MIPS_R2);
6228 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
6229 register_name = "SRSConf2";
6230 break;
6231 case CP0_REG06__SRSCONF3:
6232 check_insn(ctx, ISA_MIPS_R2);
6233 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
6234 register_name = "SRSConf3";
6235 break;
6236 case CP0_REG06__SRSCONF4:
6237 check_insn(ctx, ISA_MIPS_R2);
6238 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
6239 register_name = "SRSConf4";
6240 break;
6241 case CP0_REG06__PWCTL:
6242 check_pw(ctx);
6243 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
6244 register_name = "PWCtl";
6245 break;
6246 default:
6247 goto cp0_unimplemented;
6248 }
6249 break;
6250 case CP0_REGISTER_07:
6251 switch (sel) {
6252 case CP0_REG07__HWRENA:
6253 check_insn(ctx, ISA_MIPS_R2);
6254 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
6255 register_name = "HWREna";
6256 break;
6257 default:
6258 goto cp0_unimplemented;
6259 }
6260 break;
6261 case CP0_REGISTER_08:
6262 switch (sel) {
6263 case CP0_REG08__BADVADDR:
6264 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
6265 tcg_gen_ext32s_tl(arg, arg);
6266 register_name = "BadVAddr";
6267 break;
6268 case CP0_REG08__BADINSTR:
6269 CP0_CHECK(ctx->bi);
6270 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
6271 register_name = "BadInstr";
6272 break;
6273 case CP0_REG08__BADINSTRP:
6274 CP0_CHECK(ctx->bp);
6275 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
6276 register_name = "BadInstrP";
6277 break;
6278 case CP0_REG08__BADINSTRX:
6279 CP0_CHECK(ctx->bi);
6280 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
6281 tcg_gen_andi_tl(arg, arg, ~0xffff);
6282 register_name = "BadInstrX";
6283 break;
6284 default:
6285 goto cp0_unimplemented;
6286 }
6287 break;
6288 case CP0_REGISTER_09:
6289 switch (sel) {
6290 case CP0_REG09__COUNT:
6291 /* Mark as an IO operation because we read the time. */
6292 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
6293 gen_io_start();
6294 }
6295 gen_helper_mfc0_count(arg, cpu_env);
6296 /*
6297 * Break the TB to be able to take timer interrupts immediately
6298 * after reading count. DISAS_STOP isn't sufficient, we need to
6299 * ensure we break completely out of translated code.
6300 */
6301 gen_save_pc(ctx->base.pc_next + 4);
6302 ctx->base.is_jmp = DISAS_EXIT;
6303 register_name = "Count";
6304 break;
6305 case CP0_REG09__SAARI:
6306 CP0_CHECK(ctx->saar);
6307 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
6308 register_name = "SAARI";
6309 break;
6310 case CP0_REG09__SAAR:
6311 CP0_CHECK(ctx->saar);
6312 gen_helper_mfc0_saar(arg, cpu_env);
6313 register_name = "SAAR";
6314 break;
6315 default:
6316 goto cp0_unimplemented;
6317 }
6318 break;
6319 case CP0_REGISTER_10:
6320 switch (sel) {
6321 case CP0_REG10__ENTRYHI:
6322 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
6323 tcg_gen_ext32s_tl(arg, arg);
6324 register_name = "EntryHi";
6325 break;
6326 default:
6327 goto cp0_unimplemented;
6328 }
6329 break;
6330 case CP0_REGISTER_11:
6331 switch (sel) {
6332 case CP0_REG11__COMPARE:
6333 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
6334 register_name = "Compare";
6335 break;
6336 /* 6,7 are implementation dependent */
6337 default:
6338 goto cp0_unimplemented;
6339 }
6340 break;
6341 case CP0_REGISTER_12:
6342 switch (sel) {
6343 case CP0_REG12__STATUS:
6344 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
6345 register_name = "Status";
6346 break;
6347 case CP0_REG12__INTCTL:
6348 check_insn(ctx, ISA_MIPS_R2);
6349 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
6350 register_name = "IntCtl";
6351 break;
6352 case CP0_REG12__SRSCTL:
6353 check_insn(ctx, ISA_MIPS_R2);
6354 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
6355 register_name = "SRSCtl";
6356 break;
6357 case CP0_REG12__SRSMAP:
6358 check_insn(ctx, ISA_MIPS_R2);
6359 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
6360 register_name = "SRSMap";
6361 break;
6362 default:
6363 goto cp0_unimplemented;
6364 }
6365 break;
6366 case CP0_REGISTER_13:
6367 switch (sel) {
6368 case CP0_REG13__CAUSE:
6369 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
6370 register_name = "Cause";
6371 break;
6372 default:
6373 goto cp0_unimplemented;
6374 }
6375 break;
6376 case CP0_REGISTER_14:
6377 switch (sel) {
6378 case CP0_REG14__EPC:
6379 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
6380 tcg_gen_ext32s_tl(arg, arg);
6381 register_name = "EPC";
6382 break;
6383 default:
6384 goto cp0_unimplemented;
6385 }
6386 break;
6387 case CP0_REGISTER_15:
6388 switch (sel) {
6389 case CP0_REG15__PRID:
6390 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
6391 register_name = "PRid";
6392 break;
6393 case CP0_REG15__EBASE:
6394 check_insn(ctx, ISA_MIPS_R2);
6395 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
6396 tcg_gen_ext32s_tl(arg, arg);
6397 register_name = "EBase";
6398 break;
6399 case CP0_REG15__CMGCRBASE:
6400 check_insn(ctx, ISA_MIPS_R2);
6401 CP0_CHECK(ctx->cmgcr);
6402 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
6403 tcg_gen_ext32s_tl(arg, arg);
6404 register_name = "CMGCRBase";
6405 break;
6406 default:
6407 goto cp0_unimplemented;
6408 }
6409 break;
6410 case CP0_REGISTER_16:
6411 switch (sel) {
6412 case CP0_REG16__CONFIG:
6413 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
6414 register_name = "Config";
6415 break;
6416 case CP0_REG16__CONFIG1:
6417 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
6418 register_name = "Config1";
6419 break;
6420 case CP0_REG16__CONFIG2:
6421 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
6422 register_name = "Config2";
6423 break;
6424 case CP0_REG16__CONFIG3:
6425 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
6426 register_name = "Config3";
6427 break;
6428 case CP0_REG16__CONFIG4:
6429 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
6430 register_name = "Config4";
6431 break;
6432 case CP0_REG16__CONFIG5:
6433 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
6434 register_name = "Config5";
6435 break;
6436 /* 6,7 are implementation dependent */
6437 case CP0_REG16__CONFIG6:
6438 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
6439 register_name = "Config6";
6440 break;
6441 case CP0_REG16__CONFIG7:
6442 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
6443 register_name = "Config7";
6444 break;
6445 default:
6446 goto cp0_unimplemented;
6447 }
6448 break;
6449 case CP0_REGISTER_17:
6450 switch (sel) {
6451 case CP0_REG17__LLADDR:
6452 gen_helper_mfc0_lladdr(arg, cpu_env);
6453 register_name = "LLAddr";
6454 break;
6455 case CP0_REG17__MAAR:
6456 CP0_CHECK(ctx->mrp);
6457 gen_helper_mfc0_maar(arg, cpu_env);
6458 register_name = "MAAR";
6459 break;
6460 case CP0_REG17__MAARI:
6461 CP0_CHECK(ctx->mrp);
6462 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
6463 register_name = "MAARI";
6464 break;
6465 default:
6466 goto cp0_unimplemented;
6467 }
6468 break;
6469 case CP0_REGISTER_18:
6470 switch (sel) {
6471 case CP0_REG18__WATCHLO0:
6472 case CP0_REG18__WATCHLO1:
6473 case CP0_REG18__WATCHLO2:
6474 case CP0_REG18__WATCHLO3:
6475 case CP0_REG18__WATCHLO4:
6476 case CP0_REG18__WATCHLO5:
6477 case CP0_REG18__WATCHLO6:
6478 case CP0_REG18__WATCHLO7:
6479 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
6480 gen_helper_1e0i(mfc0_watchlo, arg, sel);
6481 register_name = "WatchLo";
6482 break;
6483 default:
6484 goto cp0_unimplemented;
6485 }
6486 break;
6487 case CP0_REGISTER_19:
6488 switch (sel) {
6489 case CP0_REG19__WATCHHI0:
6490 case CP0_REG19__WATCHHI1:
6491 case CP0_REG19__WATCHHI2:
6492 case CP0_REG19__WATCHHI3:
6493 case CP0_REG19__WATCHHI4:
6494 case CP0_REG19__WATCHHI5:
6495 case CP0_REG19__WATCHHI6:
6496 case CP0_REG19__WATCHHI7:
6497 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
6498 gen_helper_1e0i(mfc0_watchhi, arg, sel);
6499 register_name = "WatchHi";
6500 break;
6501 default:
6502 goto cp0_unimplemented;
6503 }
6504 break;
6505 case CP0_REGISTER_20:
6506 switch (sel) {
6507 case CP0_REG20__XCONTEXT:
6508 #if defined(TARGET_MIPS64)
6509 check_insn(ctx, ISA_MIPS3);
6510 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
6511 tcg_gen_ext32s_tl(arg, arg);
6512 register_name = "XContext";
6513 break;
6514 #endif
6515 default:
6516 goto cp0_unimplemented;
6517 }
6518 break;
6519 case CP0_REGISTER_21:
6520 /* Officially reserved, but sel 0 is used for R1x000 framemask */
6521 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
6522 switch (sel) {
6523 case 0:
6524 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
6525 register_name = "Framemask";
6526 break;
6527 default:
6528 goto cp0_unimplemented;
6529 }
6530 break;
6531 case CP0_REGISTER_22:
6532 tcg_gen_movi_tl(arg, 0); /* unimplemented */
6533 register_name = "'Diagnostic"; /* implementation dependent */
6534 break;
6535 case CP0_REGISTER_23:
6536 switch (sel) {
6537 case CP0_REG23__DEBUG:
6538 gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
6539 register_name = "Debug";
6540 break;
6541 case CP0_REG23__TRACECONTROL:
6542 /* PDtrace support */
6543 /* gen_helper_mfc0_tracecontrol(arg); */
6544 register_name = "TraceControl";
6545 goto cp0_unimplemented;
6546 case CP0_REG23__TRACECONTROL2:
6547 /* PDtrace support */
6548 /* gen_helper_mfc0_tracecontrol2(arg); */
6549 register_name = "TraceControl2";
6550 goto cp0_unimplemented;
6551 case CP0_REG23__USERTRACEDATA1:
6552 /* PDtrace support */
6553 /* gen_helper_mfc0_usertracedata1(arg);*/
6554 register_name = "UserTraceData1";
6555 goto cp0_unimplemented;
6556 case CP0_REG23__TRACEIBPC:
6557 /* PDtrace support */
6558 /* gen_helper_mfc0_traceibpc(arg); */
6559 register_name = "TraceIBPC";
6560 goto cp0_unimplemented;
6561 case CP0_REG23__TRACEDBPC:
6562 /* PDtrace support */
6563 /* gen_helper_mfc0_tracedbpc(arg); */
6564 register_name = "TraceDBPC";
6565 goto cp0_unimplemented;
6566 default:
6567 goto cp0_unimplemented;
6568 }
6569 break;
6570 case CP0_REGISTER_24:
6571 switch (sel) {
6572 case CP0_REG24__DEPC:
6573 /* EJTAG support */
6574 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
6575 tcg_gen_ext32s_tl(arg, arg);
6576 register_name = "DEPC";
6577 break;
6578 default:
6579 goto cp0_unimplemented;
6580 }
6581 break;
6582 case CP0_REGISTER_25:
6583 switch (sel) {
6584 case CP0_REG25__PERFCTL0:
6585 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
6586 register_name = "Performance0";
6587 break;
6588 case CP0_REG25__PERFCNT0:
6589 /* gen_helper_mfc0_performance1(arg); */
6590 register_name = "Performance1";
6591 goto cp0_unimplemented;
6592 case CP0_REG25__PERFCTL1:
6593 /* gen_helper_mfc0_performance2(arg); */
6594 register_name = "Performance2";
6595 goto cp0_unimplemented;
6596 case CP0_REG25__PERFCNT1:
6597 /* gen_helper_mfc0_performance3(arg); */
6598 register_name = "Performance3";
6599 goto cp0_unimplemented;
6600 case CP0_REG25__PERFCTL2:
6601 /* gen_helper_mfc0_performance4(arg); */
6602 register_name = "Performance4";
6603 goto cp0_unimplemented;
6604 case CP0_REG25__PERFCNT2:
6605 /* gen_helper_mfc0_performance5(arg); */
6606 register_name = "Performance5";
6607 goto cp0_unimplemented;
6608 case CP0_REG25__PERFCTL3:
6609 /* gen_helper_mfc0_performance6(arg); */
6610 register_name = "Performance6";
6611 goto cp0_unimplemented;
6612 case CP0_REG25__PERFCNT3:
6613 /* gen_helper_mfc0_performance7(arg); */
6614 register_name = "Performance7";
6615 goto cp0_unimplemented;
6616 default:
6617 goto cp0_unimplemented;
6618 }
6619 break;
6620 case CP0_REGISTER_26:
6621 switch (sel) {
6622 case CP0_REG26__ERRCTL:
6623 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
6624 register_name = "ErrCtl";
6625 break;
6626 default:
6627 goto cp0_unimplemented;
6628 }
6629 break;
6630 case CP0_REGISTER_27:
6631 switch (sel) {
6632 case CP0_REG27__CACHERR:
6633 tcg_gen_movi_tl(arg, 0); /* unimplemented */
6634 register_name = "CacheErr";
6635 break;
6636 default:
6637 goto cp0_unimplemented;
6638 }
6639 break;
6640 case CP0_REGISTER_28:
6641 switch (sel) {
6642 case CP0_REG28__TAGLO:
6643 case CP0_REG28__TAGLO1:
6644 case CP0_REG28__TAGLO2:
6645 case CP0_REG28__TAGLO3:
6646 {
6647 TCGv_i64 tmp = tcg_temp_new_i64();
6648 tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_TagLo));
6649 gen_move_low32(arg, tmp);
6650 tcg_temp_free_i64(tmp);
6651 }
6652 register_name = "TagLo";
6653 break;
6654 case CP0_REG28__DATALO:
6655 case CP0_REG28__DATALO1:
6656 case CP0_REG28__DATALO2:
6657 case CP0_REG28__DATALO3:
6658 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
6659 register_name = "DataLo";
6660 break;
6661 default:
6662 goto cp0_unimplemented;
6663 }
6664 break;
6665 case CP0_REGISTER_29:
6666 switch (sel) {
6667 case CP0_REG29__TAGHI:
6668 case CP0_REG29__TAGHI1:
6669 case CP0_REG29__TAGHI2:
6670 case CP0_REG29__TAGHI3:
6671 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
6672 register_name = "TagHi";
6673 break;
6674 case CP0_REG29__DATAHI:
6675 case CP0_REG29__DATAHI1:
6676 case CP0_REG29__DATAHI2:
6677 case CP0_REG29__DATAHI3:
6678 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
6679 register_name = "DataHi";
6680 break;
6681 default:
6682 goto cp0_unimplemented;
6683 }
6684 break;
6685 case CP0_REGISTER_30:
6686 switch (sel) {
6687 case CP0_REG30__ERROREPC:
6688 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
6689 tcg_gen_ext32s_tl(arg, arg);
6690 register_name = "ErrorEPC";
6691 break;
6692 default:
6693 goto cp0_unimplemented;
6694 }
6695 break;
6696 case CP0_REGISTER_31:
6697 switch (sel) {
6698 case CP0_REG31__DESAVE:
6699 /* EJTAG support */
6700 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
6701 register_name = "DESAVE";
6702 break;
6703 case CP0_REG31__KSCRATCH1:
6704 case CP0_REG31__KSCRATCH2:
6705 case CP0_REG31__KSCRATCH3:
6706 case CP0_REG31__KSCRATCH4:
6707 case CP0_REG31__KSCRATCH5:
6708 case CP0_REG31__KSCRATCH6:
6709 CP0_CHECK(ctx->kscrexist & (1 << sel));
6710 tcg_gen_ld_tl(arg, cpu_env,
6711 offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
6712 tcg_gen_ext32s_tl(arg, arg);
6713 register_name = "KScratch";
6714 break;
6715 default:
6716 goto cp0_unimplemented;
6717 }
6718 break;
6719 default:
6720 goto cp0_unimplemented;
6721 }
6722 trace_mips_translate_c0("mfc0", register_name, reg, sel);
6723 return;
6724
6725 cp0_unimplemented:
6726 qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n",
6727 register_name, reg, sel);
6728 gen_mfc0_unimplemented(ctx, arg);
6729 }
6730
6731 static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
6732 {
6733 const char *register_name = "invalid";
6734
6735 if (sel != 0) {
6736 check_insn(ctx, ISA_MIPS_R1);
6737 }
6738
6739 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
6740 gen_io_start();
6741 }
6742
6743 switch (reg) {
6744 case CP0_REGISTER_00:
6745 switch (sel) {
6746 case CP0_REG00__INDEX:
6747 gen_helper_mtc0_index(cpu_env, arg);
6748 register_name = "Index";
6749 break;
6750 case CP0_REG00__MVPCONTROL:
6751 CP0_CHECK(ctx->insn_flags & ASE_MT);
6752 gen_helper_mtc0_mvpcontrol(cpu_env, arg);
6753 register_name = "MVPControl";
6754 break;
6755 case CP0_REG00__MVPCONF0:
6756 CP0_CHECK(ctx->insn_flags & ASE_MT);
6757 /* ignored */
6758 register_name = "MVPConf0";
6759 break;
6760 case CP0_REG00__MVPCONF1:
6761 CP0_CHECK(ctx->insn_flags & ASE_MT);
6762 /* ignored */
6763 register_name = "MVPConf1";
6764 break;
6765 case CP0_REG00__VPCONTROL:
6766 CP0_CHECK(ctx->vp);
6767 /* ignored */
6768 register_name = "VPControl";
6769 break;
6770 default:
6771 goto cp0_unimplemented;
6772 }
6773 break;
6774 case CP0_REGISTER_01:
6775 switch (sel) {
6776 case CP0_REG01__RANDOM:
6777 /* ignored */
6778 register_name = "Random";
6779 break;
6780 case CP0_REG01__VPECONTROL:
6781 CP0_CHECK(ctx->insn_flags & ASE_MT);
6782 gen_helper_mtc0_vpecontrol(cpu_env, arg);
6783 register_name = "VPEControl";
6784 break;
6785 case CP0_REG01__VPECONF0:
6786 CP0_CHECK(ctx->insn_flags & ASE_MT);
6787 gen_helper_mtc0_vpeconf0(cpu_env, arg);
6788 register_name = "VPEConf0";
6789 break;
6790 case CP0_REG01__VPECONF1:
6791 CP0_CHECK(ctx->insn_flags & ASE_MT);
6792 gen_helper_mtc0_vpeconf1(cpu_env, arg);
6793 register_name = "VPEConf1";
6794 break;
6795 case CP0_REG01__YQMASK:
6796 CP0_CHECK(ctx->insn_flags & ASE_MT);
6797 gen_helper_mtc0_yqmask(cpu_env, arg);
6798 register_name = "YQMask";
6799 break;
6800 case CP0_REG01__VPESCHEDULE:
6801 CP0_CHECK(ctx->insn_flags & ASE_MT);
6802 tcg_gen_st_tl(arg, cpu_env,
6803 offsetof(CPUMIPSState, CP0_VPESchedule));
6804 register_name = "VPESchedule";
6805 break;
6806 case CP0_REG01__VPESCHEFBACK:
6807 CP0_CHECK(ctx->insn_flags & ASE_MT);
6808 tcg_gen_st_tl(arg, cpu_env,
6809 offsetof(CPUMIPSState, CP0_VPEScheFBack));
6810 register_name = "VPEScheFBack";
6811 break;
6812 case CP0_REG01__VPEOPT:
6813 CP0_CHECK(ctx->insn_flags & ASE_MT);
6814 gen_helper_mtc0_vpeopt(cpu_env, arg);
6815 register_name = "VPEOpt";
6816 break;
6817 default:
6818 goto cp0_unimplemented;
6819 }
6820 break;
6821 case CP0_REGISTER_02:
6822 switch (sel) {
6823 case CP0_REG02__ENTRYLO0:
6824 gen_helper_mtc0_entrylo0(cpu_env, arg);
6825 register_name = "EntryLo0";
6826 break;
6827 case CP0_REG02__TCSTATUS:
6828 CP0_CHECK(ctx->insn_flags & ASE_MT);
6829 gen_helper_mtc0_tcstatus(cpu_env, arg);
6830 register_name = "TCStatus";
6831 break;
6832 case CP0_REG02__TCBIND:
6833 CP0_CHECK(ctx->insn_flags & ASE_MT);
6834 gen_helper_mtc0_tcbind(cpu_env, arg);
6835 register_name = "TCBind";
6836 break;
6837 case CP0_REG02__TCRESTART:
6838 CP0_CHECK(ctx->insn_flags & ASE_MT);
6839 gen_helper_mtc0_tcrestart(cpu_env, arg);
6840 register_name = "TCRestart";
6841 break;
6842 case CP0_REG02__TCHALT:
6843 CP0_CHECK(ctx->insn_flags & ASE_MT);
6844 gen_helper_mtc0_tchalt(cpu_env, arg);
6845 register_name = "TCHalt";
6846 break;
6847 case CP0_REG02__TCCONTEXT:
6848 CP0_CHECK(ctx->insn_flags & ASE_MT);
6849 gen_helper_mtc0_tccontext(cpu_env, arg);
6850 register_name = "TCContext";
6851 break;
6852 case CP0_REG02__TCSCHEDULE:
6853 CP0_CHECK(ctx->insn_flags & ASE_MT);
6854 gen_helper_mtc0_tcschedule(cpu_env, arg);
6855 register_name = "TCSchedule";
6856 break;
6857 case CP0_REG02__TCSCHEFBACK:
6858 CP0_CHECK(ctx->insn_flags & ASE_MT);
6859 gen_helper_mtc0_tcschefback(cpu_env, arg);
6860 register_name = "TCScheFBack";
6861 break;
6862 default:
6863 goto cp0_unimplemented;
6864 }
6865 break;
6866 case CP0_REGISTER_03:
6867 switch (sel) {
6868 case CP0_REG03__ENTRYLO1:
6869 gen_helper_mtc0_entrylo1(cpu_env, arg);
6870 register_name = "EntryLo1";
6871 break;
6872 case CP0_REG03__GLOBALNUM:
6873 CP0_CHECK(ctx->vp);
6874 /* ignored */
6875 register_name = "GlobalNumber";
6876 break;
6877 default:
6878 goto cp0_unimplemented;
6879 }
6880 break;
6881 case CP0_REGISTER_04:
6882 switch (sel) {
6883 case CP0_REG04__CONTEXT:
6884 gen_helper_mtc0_context(cpu_env, arg);
6885 register_name = "Context";
6886 break;
6887 case CP0_REG04__CONTEXTCONFIG:
6888 /* SmartMIPS ASE */
6889 /* gen_helper_mtc0_contextconfig(arg); */
6890 register_name = "ContextConfig";
6891 goto cp0_unimplemented;
6892 case CP0_REG04__USERLOCAL:
6893 CP0_CHECK(ctx->ulri);
6894 tcg_gen_st_tl(arg, cpu_env,
6895 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
6896 register_name = "UserLocal";
6897 break;
6898 case CP0_REG04__MMID:
6899 CP0_CHECK(ctx->mi);
6900 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID));
6901 register_name = "MMID";
6902 break;
6903 default:
6904 goto cp0_unimplemented;
6905 }
6906 break;
6907 case CP0_REGISTER_05:
6908 switch (sel) {
6909 case CP0_REG05__PAGEMASK:
6910 gen_helper_mtc0_pagemask(cpu_env, arg);
6911 register_name = "PageMask";
6912 break;
6913 case CP0_REG05__PAGEGRAIN:
6914 check_insn(ctx, ISA_MIPS_R2);
6915 gen_helper_mtc0_pagegrain(cpu_env, arg);
6916 register_name = "PageGrain";
6917 ctx->base.is_jmp = DISAS_STOP;
6918 break;
6919 case CP0_REG05__SEGCTL0:
6920 CP0_CHECK(ctx->sc);
6921 gen_helper_mtc0_segctl0(cpu_env, arg);
6922 register_name = "SegCtl0";
6923 break;
6924 case CP0_REG05__SEGCTL1:
6925 CP0_CHECK(ctx->sc);
6926 gen_helper_mtc0_segctl1(cpu_env, arg);
6927 register_name = "SegCtl1";
6928 break;
6929 case CP0_REG05__SEGCTL2:
6930 CP0_CHECK(ctx->sc);
6931 gen_helper_mtc0_segctl2(cpu_env, arg);
6932 register_name = "SegCtl2";
6933 break;
6934 case CP0_REG05__PWBASE:
6935 check_pw(ctx);
6936 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
6937 register_name = "PWBase";
6938 break;
6939 case CP0_REG05__PWFIELD:
6940 check_pw(ctx);
6941 gen_helper_mtc0_pwfield(cpu_env, arg);
6942 register_name = "PWField";
6943 break;
6944 case CP0_REG05__PWSIZE:
6945 check_pw(ctx);
6946 gen_helper_mtc0_pwsize(cpu_env, arg);
6947 register_name = "PWSize";
6948 break;
6949 default:
6950 goto cp0_unimplemented;
6951 }
6952 break;
6953 case CP0_REGISTER_06:
6954 switch (sel) {
6955 case CP0_REG06__WIRED:
6956 gen_helper_mtc0_wired(cpu_env, arg);
6957 register_name = "Wired";
6958 break;
6959 case CP0_REG06__SRSCONF0:
6960 check_insn(ctx, ISA_MIPS_R2);
6961 gen_helper_mtc0_srsconf0(cpu_env, arg);
6962 register_name = "SRSConf0";
6963 break;
6964 case CP0_REG06__SRSCONF1:
6965 check_insn(ctx, ISA_MIPS_R2);
6966 gen_helper_mtc0_srsconf1(cpu_env, arg);
6967 register_name = "SRSConf1";
6968 break;
6969 case CP0_REG06__SRSCONF2:
6970 check_insn(ctx, ISA_MIPS_R2);
6971 gen_helper_mtc0_srsconf2(cpu_env, arg);
6972 register_name = "SRSConf2";
6973 break;
6974 case CP0_REG06__SRSCONF3:
6975 check_insn(ctx, ISA_MIPS_R2);
6976 gen_helper_mtc0_srsconf3(cpu_env, arg);
6977 register_name = "SRSConf3";
6978 break;
6979 case CP0_REG06__SRSCONF4:
6980 check_insn(ctx, ISA_MIPS_R2);
6981 gen_helper_mtc0_srsconf4(cpu_env, arg);
6982 register_name = "SRSConf4";
6983 break;
6984 case CP0_REG06__PWCTL:
6985 check_pw(ctx);
6986 gen_helper_mtc0_pwctl(cpu_env, arg);
6987 register_name = "PWCtl";
6988 break;
6989 default:
6990 goto cp0_unimplemented;
6991 }
6992 break;
6993 case CP0_REGISTER_07:
6994 switch (sel) {
6995 case CP0_REG07__HWRENA:
6996 check_insn(ctx, ISA_MIPS_R2);
6997 gen_helper_mtc0_hwrena(cpu_env, arg);
6998 ctx->base.is_jmp = DISAS_STOP;
6999 register_name = "HWREna";
7000 break;
7001 default:
7002 goto cp0_unimplemented;
7003 }
7004 break;
7005 case CP0_REGISTER_08:
7006 switch (sel) {
7007 case CP0_REG08__BADVADDR:
7008 /* ignored */
7009 register_name = "BadVAddr";
7010 break;
7011 case CP0_REG08__BADINSTR:
7012 /* ignored */
7013 register_name = "BadInstr";
7014 break;
7015 case CP0_REG08__BADINSTRP:
7016 /* ignored */
7017 register_name = "BadInstrP";
7018 break;
7019 case CP0_REG08__BADINSTRX:
7020 /* ignored */
7021 register_name = "BadInstrX";
7022 break;
7023 default:
7024 goto cp0_unimplemented;
7025 }
7026 break;
7027 case CP0_REGISTER_09:
7028 switch (sel) {
7029 case CP0_REG09__COUNT:
7030 gen_helper_mtc0_count(cpu_env, arg);
7031 register_name = "Count";
7032 break;
7033 case CP0_REG09__SAARI:
7034 CP0_CHECK(ctx->saar);
7035 gen_helper_mtc0_saari(cpu_env, arg);
7036 register_name = "SAARI";
7037 break;
7038 case CP0_REG09__SAAR:
7039 CP0_CHECK(ctx->saar);
7040 gen_helper_mtc0_saar(cpu_env, arg);
7041 register_name = "SAAR";
7042 break;
7043 default:
7044 goto cp0_unimplemented;
7045 }
7046 break;
7047 case CP0_REGISTER_10:
7048 switch (sel) {
7049 case CP0_REG10__ENTRYHI:
7050 gen_helper_mtc0_entryhi(cpu_env, arg);
7051 register_name = "EntryHi";
7052 break;
7053 default:
7054 goto cp0_unimplemented;
7055 }
7056 break;
7057 case CP0_REGISTER_11:
7058 switch (sel) {
7059 case CP0_REG11__COMPARE:
7060 gen_helper_mtc0_compare(cpu_env, arg);
7061 register_name = "Compare";
7062 break;
7063 /* 6,7 are implementation dependent */
7064 default:
7065 goto cp0_unimplemented;
7066 }
7067 break;
7068 case CP0_REGISTER_12:
7069 switch (sel) {
7070 case CP0_REG12__STATUS:
7071 save_cpu_state(ctx, 1);
7072 gen_helper_mtc0_status(cpu_env, arg);
7073 /* DISAS_STOP isn't good enough here, hflags may have changed. */
7074 gen_save_pc(ctx->base.pc_next + 4);
7075 ctx->base.is_jmp = DISAS_EXIT;
7076 register_name = "Status";
7077 break;
7078 case CP0_REG12__INTCTL:
7079 check_insn(ctx, ISA_MIPS_R2);
7080 gen_helper_mtc0_intctl(cpu_env, arg);
7081 /* Stop translation as we may have switched the execution mode */
7082 ctx->base.is_jmp = DISAS_STOP;
7083 register_name = "IntCtl";
7084 break;
7085 case CP0_REG12__SRSCTL:
7086 check_insn(ctx, ISA_MIPS_R2);
7087 gen_helper_mtc0_srsctl(cpu_env, arg);
7088 /* Stop translation as we may have switched the execution mode */
7089 ctx->base.is_jmp = DISAS_STOP;
7090 register_name = "SRSCtl";
7091 break;
7092 case CP0_REG12__SRSMAP:
7093 check_insn(ctx, ISA_MIPS_R2);
7094 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
7095 /* Stop translation as we may have switched the execution mode */
7096 ctx->base.is_jmp = DISAS_STOP;
7097 register_name = "SRSMap";
7098 break;
7099 default:
7100 goto cp0_unimplemented;
7101 }
7102 break;
7103 case CP0_REGISTER_13:
7104 switch (sel) {
7105 case CP0_REG13__CAUSE:
7106 save_cpu_state(ctx, 1);
7107 gen_helper_mtc0_cause(cpu_env, arg);
7108 /*
7109 * Stop translation as we may have triggered an interrupt.
7110 * DISAS_STOP isn't sufficient, we need to ensure we break out of
7111 * translated code to check for pending interrupts.
7112 */
7113 gen_save_pc(ctx->base.pc_next + 4);
7114 ctx->base.is_jmp = DISAS_EXIT;
7115 register_name = "Cause";
7116 break;
7117 default:
7118 goto cp0_unimplemented;
7119 }
7120 break;
7121 case CP0_REGISTER_14:
7122 switch (sel) {
7123 case CP0_REG14__EPC:
7124 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
7125 register_name = "EPC";
7126 break;
7127 default:
7128 goto cp0_unimplemented;
7129 }
7130 break;
7131 case CP0_REGISTER_15:
7132 switch (sel) {
7133 case CP0_REG15__PRID:
7134 /* ignored */
7135 register_name = "PRid";
7136 break;
7137 case CP0_REG15__EBASE:
7138 check_insn(ctx, ISA_MIPS_R2);
7139 gen_helper_mtc0_ebase(cpu_env, arg);
7140 register_name = "EBase";
7141 break;
7142 default:
7143 goto cp0_unimplemented;
7144 }
7145 break;
7146 case CP0_REGISTER_16:
7147 switch (sel) {
7148 case CP0_REG16__CONFIG:
7149 gen_helper_mtc0_config0(cpu_env, arg);
7150 register_name = "Config";
7151 /* Stop translation as we may have switched the execution mode */
7152 ctx->base.is_jmp = DISAS_STOP;
7153 break;
7154 case CP0_REG16__CONFIG1:
7155 /* ignored, read only */
7156 register_name = "Config1";
7157 break;
7158 case CP0_REG16__CONFIG2:
7159 gen_helper_mtc0_config2(cpu_env, arg);
7160 register_name = "Config2";
7161 /* Stop translation as we may have switched the execution mode */
7162 ctx->base.is_jmp = DISAS_STOP;
7163 break;
7164 case CP0_REG16__CONFIG3:
7165 gen_helper_mtc0_config3(cpu_env, arg);
7166 register_name = "Config3";
7167 /* Stop translation as we may have switched the execution mode */
7168 ctx->base.is_jmp = DISAS_STOP;
7169 break;
7170 case CP0_REG16__CONFIG4:
7171 gen_helper_mtc0_config4(cpu_env, arg);
7172 register_name = "Config4";
7173 ctx->base.is_jmp = DISAS_STOP;
7174 break;
7175 case CP0_REG16__CONFIG5:
7176 gen_helper_mtc0_config5(cpu_env, arg);
7177 register_name = "Config5";
7178 /* Stop translation as we may have switched the execution mode */
7179 ctx->base.is_jmp = DISAS_STOP;
7180 break;
7181 /* 6,7 are implementation dependent */
7182 case CP0_REG16__CONFIG6:
7183 /* ignored */
7184 register_name = "Config6";
7185 break;
7186 case CP0_REG16__CONFIG7:
7187 /* ignored */
7188 register_name = "Config7";
7189 break;
7190 default:
7191 register_name = "Invalid config selector";
7192 goto cp0_unimplemented;
7193 }
7194 break;
7195 case CP0_REGISTER_17:
7196 switch (sel) {
7197 case CP0_REG17__LLADDR:
7198 gen_helper_mtc0_lladdr(cpu_env, arg);
7199 register_name = "LLAddr";
7200 break;
7201 case CP0_REG17__MAAR:
7202 CP0_CHECK(ctx->mrp);
7203 gen_helper_mtc0_maar(cpu_env, arg);
7204 register_name = "MAAR";
7205 break;
7206 case CP0_REG17__MAARI:
7207 CP0_CHECK(ctx->mrp);
7208 gen_helper_mtc0_maari(cpu_env, arg);
7209 register_name = "MAARI";
7210 break;
7211 default:
7212 goto cp0_unimplemented;
7213 }
7214 break;
7215 case CP0_REGISTER_18:
7216 switch (sel) {
7217 case CP0_REG18__WATCHLO0:
7218 case CP0_REG18__WATCHLO1:
7219 case CP0_REG18__WATCHLO2:
7220 case CP0_REG18__WATCHLO3:
7221 case CP0_REG18__WATCHLO4:
7222 case CP0_REG18__WATCHLO5:
7223 case CP0_REG18__WATCHLO6:
7224 case CP0_REG18__WATCHLO7:
7225 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
7226 gen_helper_0e1i(mtc0_watchlo, arg, sel);
7227 register_name = "WatchLo";
7228 break;
7229 default:
7230 goto cp0_unimplemented;
7231 }
7232 break;
7233 case CP0_REGISTER_19:
7234 switch (sel) {
7235 case CP0_REG19__WATCHHI0:
7236 case CP0_REG19__WATCHHI1:
7237 case CP0_REG19__WATCHHI2:
7238 case CP0_REG19__WATCHHI3:
7239 case CP0_REG19__WATCHHI4:
7240 case CP0_REG19__WATCHHI5:
7241 case CP0_REG19__WATCHHI6:
7242 case CP0_REG19__WATCHHI7:
7243 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
7244 gen_helper_0e1i(mtc0_watchhi, arg, sel);
7245 register_name = "WatchHi";
7246 break;
7247 default:
7248 goto cp0_unimplemented;
7249 }
7250 break;
7251 case CP0_REGISTER_20:
7252 switch (sel) {
7253 case CP0_REG20__XCONTEXT:
7254 #if defined(TARGET_MIPS64)
7255 check_insn(ctx, ISA_MIPS3);
7256 gen_helper_mtc0_xcontext(cpu_env, arg);
7257 register_name = "XContext";
7258 break;
7259 #endif
7260 default:
7261 goto cp0_unimplemented;
7262 }
7263 break;
7264 case CP0_REGISTER_21:
7265 /* Officially reserved, but sel 0 is used for R1x000 framemask */
7266 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
7267 switch (sel) {
7268 case 0:
7269 gen_helper_mtc0_framemask(cpu_env, arg);
7270 register_name = "Framemask";
7271 break;
7272 default:
7273 goto cp0_unimplemented;
7274 }
7275 break;
7276 case CP0_REGISTER_22:
7277 /* ignored */
7278 register_name = "Diagnostic"; /* implementation dependent */
7279 break;
7280 case CP0_REGISTER_23:
7281 switch (sel) {
7282 case CP0_REG23__DEBUG:
7283 gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
7284 /* DISAS_STOP isn't good enough here, hflags may have changed. */
7285 gen_save_pc(ctx->base.pc_next + 4);
7286 ctx->base.is_jmp = DISAS_EXIT;
7287 register_name = "Debug";
7288 break;
7289 case CP0_REG23__TRACECONTROL:
7290 /* PDtrace support */
7291 /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
7292 register_name = "TraceControl";
7293 /* Stop translation as we may have switched the execution mode */
7294 ctx->base.is_jmp = DISAS_STOP;
7295 goto cp0_unimplemented;
7296 case CP0_REG23__TRACECONTROL2:
7297 /* PDtrace support */
7298 /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
7299 register_name = "TraceControl2";
7300 /* Stop translation as we may have switched the execution mode */
7301 ctx->base.is_jmp = DISAS_STOP;
7302 goto cp0_unimplemented;
7303 case CP0_REG23__USERTRACEDATA1:
7304 /* Stop translation as we may have switched the execution mode */
7305 ctx->base.is_jmp = DISAS_STOP;
7306 /* PDtrace support */
7307 /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
7308 register_name = "UserTraceData";
7309 /* Stop translation as we may have switched the execution mode */
7310 ctx->base.is_jmp = DISAS_STOP;
7311 goto cp0_unimplemented;
7312 case CP0_REG23__TRACEIBPC:
7313 /* PDtrace support */
7314 /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
7315 /* Stop translation as we may have switched the execution mode */
7316 ctx->base.is_jmp = DISAS_STOP;
7317 register_name = "TraceIBPC";
7318 goto cp0_unimplemented;
7319 case CP0_REG23__TRACEDBPC:
7320 /* PDtrace support */
7321 /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
7322 /* Stop translation as we may have switched the execution mode */
7323 ctx->base.is_jmp = DISAS_STOP;
7324 register_name = "TraceDBPC";
7325 goto cp0_unimplemented;
7326 default:
7327 goto cp0_unimplemented;
7328 }
7329 break;
7330 case CP0_REGISTER_24:
7331 switch (sel) {
7332 case CP0_REG24__DEPC:
7333 /* EJTAG support */
7334 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
7335 register_name = "DEPC";
7336 break;
7337 default:
7338 goto cp0_unimplemented;
7339 }
7340 break;
7341 case CP0_REGISTER_25:
7342 switch (sel) {
7343 case CP0_REG25__PERFCTL0:
7344 gen_helper_mtc0_performance0(cpu_env, arg);
7345 register_name = "Performance0";
7346 break;
7347 case CP0_REG25__PERFCNT0:
7348 /* gen_helper_mtc0_performance1(arg); */
7349 register_name = "Performance1";
7350 goto cp0_unimplemented;
7351 case CP0_REG25__PERFCTL1:
7352 /* gen_helper_mtc0_performance2(arg); */
7353 register_name = "Performance2";
7354 goto cp0_unimplemented;
7355 case CP0_REG25__PERFCNT1:
7356 /* gen_helper_mtc0_performance3(arg); */
7357 register_name = "Performance3";
7358 goto cp0_unimplemented;
7359 case CP0_REG25__PERFCTL2:
7360 /* gen_helper_mtc0_performance4(arg); */
7361 register_name = "Performance4";
7362 goto cp0_unimplemented;
7363 case CP0_REG25__PERFCNT2:
7364 /* gen_helper_mtc0_performance5(arg); */
7365 register_name = "Performance5";
7366 goto cp0_unimplemented;
7367 case CP0_REG25__PERFCTL3:
7368 /* gen_helper_mtc0_performance6(arg); */
7369 register_name = "Performance6";
7370 goto cp0_unimplemented;
7371 case CP0_REG25__PERFCNT3:
7372 /* gen_helper_mtc0_performance7(arg); */
7373 register_name = "Performance7";
7374 goto cp0_unimplemented;
7375 default:
7376 goto cp0_unimplemented;
7377 }
7378 break;
7379 case CP0_REGISTER_26:
7380 switch (sel) {
7381 case CP0_REG26__ERRCTL:
7382 gen_helper_mtc0_errctl(cpu_env, arg);
7383 ctx->base.is_jmp = DISAS_STOP;
7384 register_name = "ErrCtl";
7385 break;
7386 default:
7387 goto cp0_unimplemented;
7388 }
7389 break;
7390 case CP0_REGISTER_27:
7391 switch (sel) {
7392 case CP0_REG27__CACHERR:
7393 /* ignored */
7394 register_name = "CacheErr";
7395 break;
7396 default:
7397 goto cp0_unimplemented;
7398 }
7399 break;
7400 case CP0_REGISTER_28:
7401 switch (sel) {
7402 case CP0_REG28__TAGLO:
7403 case CP0_REG28__TAGLO1:
7404 case CP0_REG28__TAGLO2:
7405 case CP0_REG28__TAGLO3:
7406 gen_helper_mtc0_taglo(cpu_env, arg);
7407 register_name = "TagLo";
7408 break;
7409 case CP0_REG28__DATALO:
7410 case CP0_REG28__DATALO1:
7411 case CP0_REG28__DATALO2:
7412 case CP0_REG28__DATALO3:
7413 gen_helper_mtc0_datalo(cpu_env, arg);
7414 register_name = "DataLo";
7415 break;
7416 default:
7417 goto cp0_unimplemented;
7418 }
7419 break;
7420 case CP0_REGISTER_29:
7421 switch (sel) {
7422 case CP0_REG29__TAGHI:
7423 case CP0_REG29__TAGHI1:
7424 case CP0_REG29__TAGHI2:
7425 case CP0_REG29__TAGHI3:
7426 gen_helper_mtc0_taghi(cpu_env, arg);
7427 register_name = "TagHi";
7428 break;
7429 case CP0_REG29__DATAHI:
7430 case CP0_REG29__DATAHI1:
7431 case CP0_REG29__DATAHI2:
7432 case CP0_REG29__DATAHI3:
7433 gen_helper_mtc0_datahi(cpu_env, arg);
7434 register_name = "DataHi";
7435 break;
7436 default:
7437 register_name = "invalid sel";
7438 goto cp0_unimplemented;
7439 }
7440 break;
7441 case CP0_REGISTER_30:
7442 switch (sel) {
7443 case CP0_REG30__ERROREPC:
7444 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
7445 register_name = "ErrorEPC";
7446 break;
7447 default:
7448 goto cp0_unimplemented;
7449 }
7450 break;
7451 case CP0_REGISTER_31:
7452 switch (sel) {
7453 case CP0_REG31__DESAVE:
7454 /* EJTAG support */
7455 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
7456 register_name = "DESAVE";
7457 break;
7458 case CP0_REG31__KSCRATCH1:
7459 case CP0_REG31__KSCRATCH2:
7460 case CP0_REG31__KSCRATCH3:
7461 case CP0_REG31__KSCRATCH4:
7462 case CP0_REG31__KSCRATCH5:
7463 case CP0_REG31__KSCRATCH6:
7464 CP0_CHECK(ctx->kscrexist & (1 << sel));
7465 tcg_gen_st_tl(arg, cpu_env,
7466 offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
7467 register_name = "KScratch";
7468 break;
7469 default:
7470 goto cp0_unimplemented;
7471 }
7472 break;
7473 default:
7474 goto cp0_unimplemented;
7475 }
7476 trace_mips_translate_c0("mtc0", register_name, reg, sel);
7477
7478 /* For simplicity assume that all writes can cause interrupts. */
7479 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
7480 /*
7481 * DISAS_STOP isn't sufficient, we need to ensure we break out of
7482 * translated code to check for pending interrupts.
7483 */
7484 gen_save_pc(ctx->base.pc_next + 4);
7485 ctx->base.is_jmp = DISAS_EXIT;
7486 }
7487 return;
7488
7489 cp0_unimplemented:
7490 qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n",
7491 register_name, reg, sel);
7492 }
7493
7494 #if defined(TARGET_MIPS64)
7495 static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
7496 {
7497 const char *register_name = "invalid";
7498
7499 if (sel != 0) {
7500 check_insn(ctx, ISA_MIPS_R1);
7501 }
7502
7503 switch (reg) {
7504 case CP0_REGISTER_00:
7505 switch (sel) {
7506 case CP0_REG00__INDEX:
7507 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
7508 register_name = "Index";
7509 break;
7510 case CP0_REG00__MVPCONTROL:
7511 CP0_CHECK(ctx->insn_flags & ASE_MT);
7512 gen_helper_mfc0_mvpcontrol(arg, cpu_env);
7513 register_name = "MVPControl";
7514 break;
7515 case CP0_REG00__MVPCONF0:
7516 CP0_CHECK(ctx->insn_flags & ASE_MT);
7517 gen_helper_mfc0_mvpconf0(arg, cpu_env);
7518 register_name = "MVPConf0";
7519 break;
7520 case CP0_REG00__MVPCONF1:
7521 CP0_CHECK(ctx->insn_flags & ASE_MT);
7522 gen_helper_mfc0_mvpconf1(arg, cpu_env);
7523 register_name = "MVPConf1";
7524 break;
7525 case CP0_REG00__VPCONTROL:
7526 CP0_CHECK(ctx->vp);
7527 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
7528 register_name = "VPControl";
7529 break;
7530 default:
7531 goto cp0_unimplemented;
7532 }
7533 break;
7534 case CP0_REGISTER_01:
7535 switch (sel) {
7536 case CP0_REG01__RANDOM:
7537 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
7538 gen_helper_mfc0_random(arg, cpu_env);
7539 register_name = "Random";
7540 break;
7541 case CP0_REG01__VPECONTROL:
7542 CP0_CHECK(ctx->insn_flags & ASE_MT);
7543 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
7544 register_name = "VPEControl";
7545 break;
7546 case CP0_REG01__VPECONF0:
7547 CP0_CHECK(ctx->insn_flags & ASE_MT);
7548 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
7549 register_name = "VPEConf0";
7550 break;
7551 case CP0_REG01__VPECONF1:
7552 CP0_CHECK(ctx->insn_flags & ASE_MT);
7553 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
7554 register_name = "VPEConf1";
7555 break;
7556 case CP0_REG01__YQMASK:
7557 CP0_CHECK(ctx->insn_flags & ASE_MT);
7558 tcg_gen_ld_tl(arg, cpu_env,
7559 offsetof(CPUMIPSState, CP0_YQMask));
7560 register_name = "YQMask";
7561 break;
7562 case CP0_REG01__VPESCHEDULE:
7563 CP0_CHECK(ctx->insn_flags & ASE_MT);
7564 tcg_gen_ld_tl(arg, cpu_env,
7565 offsetof(CPUMIPSState, CP0_VPESchedule));
7566 register_name = "VPESchedule";
7567 break;
7568 case CP0_REG01__VPESCHEFBACK:
7569 CP0_CHECK(ctx->insn_flags & ASE_MT);
7570 tcg_gen_ld_tl(arg, cpu_env,
7571 offsetof(CPUMIPSState, CP0_VPEScheFBack));
7572 register_name = "VPEScheFBack";
7573 break;
7574 case CP0_REG01__VPEOPT:
7575 CP0_CHECK(ctx->insn_flags & ASE_MT);
7576 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
7577 register_name = "VPEOpt";
7578 break;
7579 default:
7580 goto cp0_unimplemented;
7581 }
7582 break;
7583 case CP0_REGISTER_02:
7584 switch (sel) {
7585 case CP0_REG02__ENTRYLO0:
7586 tcg_gen_ld_tl(arg, cpu_env,
7587 offsetof(CPUMIPSState, CP0_EntryLo0));
7588 register_name = "EntryLo0";
7589 break;
7590 case CP0_REG02__TCSTATUS:
7591 CP0_CHECK(ctx->insn_flags & ASE_MT);
7592 gen_helper_mfc0_tcstatus(arg, cpu_env);
7593 register_name = "TCStatus";
7594 break;
7595 case CP0_REG02__TCBIND:
7596 CP0_CHECK(ctx->insn_flags & ASE_MT);
7597 gen_helper_mfc0_tcbind(arg, cpu_env);
7598 register_name = "TCBind";
7599 break;
7600 case CP0_REG02__TCRESTART:
7601 CP0_CHECK(ctx->insn_flags & ASE_MT);
7602 gen_helper_dmfc0_tcrestart(arg, cpu_env);
7603 register_name = "TCRestart";
7604 break;
7605 case CP0_REG02__TCHALT:
7606 CP0_CHECK(ctx->insn_flags & ASE_MT);
7607 gen_helper_dmfc0_tchalt(arg, cpu_env);
7608 register_name = "TCHalt";
7609 break;
7610 case CP0_REG02__TCCONTEXT:
7611 CP0_CHECK(ctx->insn_flags & ASE_MT);
7612 gen_helper_dmfc0_tccontext(arg, cpu_env);
7613 register_name = "TCContext";
7614 break;
7615 case CP0_REG02__TCSCHEDULE:
7616 CP0_CHECK(ctx->insn_flags & ASE_MT);
7617 gen_helper_dmfc0_tcschedule(arg, cpu_env);
7618 register_name = "TCSchedule";
7619 break;
7620 case CP0_REG02__TCSCHEFBACK:
7621 CP0_CHECK(ctx->insn_flags & ASE_MT);
7622 gen_helper_dmfc0_tcschefback(arg, cpu_env);
7623 register_name = "TCScheFBack";
7624 break;
7625 default:
7626 goto cp0_unimplemented;
7627 }
7628 break;
7629 case CP0_REGISTER_03:
7630 switch (sel) {
7631 case CP0_REG03__ENTRYLO1:
7632 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
7633 register_name = "EntryLo1";
7634 break;
7635 case CP0_REG03__GLOBALNUM:
7636 CP0_CHECK(ctx->vp);
7637 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
7638 register_name = "GlobalNumber";
7639 break;
7640 default:
7641 goto cp0_unimplemented;
7642 }
7643 break;
7644 case CP0_REGISTER_04:
7645 switch (sel) {
7646 case CP0_REG04__CONTEXT:
7647 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
7648 register_name = "Context";
7649 break;
7650 case CP0_REG04__CONTEXTCONFIG:
7651 /* SmartMIPS ASE */
7652 /* gen_helper_dmfc0_contextconfig(arg); */
7653 register_name = "ContextConfig";
7654 goto cp0_unimplemented;
7655 case CP0_REG04__USERLOCAL:
7656 CP0_CHECK(ctx->ulri);
7657 tcg_gen_ld_tl(arg, cpu_env,
7658 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
7659 register_name = "UserLocal";
7660 break;
7661 case CP0_REG04__MMID:
7662 CP0_CHECK(ctx->mi);
7663 gen_helper_mtc0_memorymapid(cpu_env, arg);
7664 register_name = "MMID";
7665 break;
7666 default:
7667 goto cp0_unimplemented;
7668 }
7669 break;
7670 case CP0_REGISTER_05:
7671 switch (sel) {
7672 case CP0_REG05__PAGEMASK:
7673 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
7674 register_name = "PageMask";
7675 break;
7676 case CP0_REG05__PAGEGRAIN:
7677 check_insn(ctx, ISA_MIPS_R2);
7678 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
7679 register_name = "PageGrain";
7680 break;
7681 case CP0_REG05__SEGCTL0:
7682 CP0_CHECK(ctx->sc);
7683 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
7684 register_name = "SegCtl0";
7685 break;
7686 case CP0_REG05__SEGCTL1:
7687 CP0_CHECK(ctx->sc);
7688 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
7689 register_name = "SegCtl1";
7690 break;
7691 case CP0_REG05__SEGCTL2:
7692 CP0_CHECK(ctx->sc);
7693 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
7694 register_name = "SegCtl2";
7695 break;
7696 case CP0_REG05__PWBASE:
7697 check_pw(ctx);
7698 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
7699 register_name = "PWBase";
7700 break;
7701 case CP0_REG05__PWFIELD:
7702 check_pw(ctx);
7703 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));
7704 register_name = "PWField";
7705 break;
7706 case CP0_REG05__PWSIZE:
7707 check_pw(ctx);
7708 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
7709 register_name = "PWSize";
7710 break;
7711 default:
7712 goto cp0_unimplemented;
7713 }
7714 break;
7715 case CP0_REGISTER_06:
7716 switch (sel) {
7717 case CP0_REG06__WIRED:
7718 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
7719 register_name = "Wired";
7720 break;
7721 case CP0_REG06__SRSCONF0:
7722 check_insn(ctx, ISA_MIPS_R2);
7723 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
7724 register_name = "SRSConf0";
7725 break;
7726 case CP0_REG06__SRSCONF1:
7727 check_insn(ctx, ISA_MIPS_R2);
7728 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
7729 register_name = "SRSConf1";
7730 break;
7731 case CP0_REG06__SRSCONF2:
7732 check_insn(ctx, ISA_MIPS_R2);
7733 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
7734 register_name = "SRSConf2";
7735 break;
7736 case CP0_REG06__SRSCONF3:
7737 check_insn(ctx, ISA_MIPS_R2);
7738 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
7739 register_name = "SRSConf3";
7740 break;
7741 case CP0_REG06__SRSCONF4:
7742 check_insn(ctx, ISA_MIPS_R2);
7743 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
7744 register_name = "SRSConf4";
7745 break;
7746 case CP0_REG06__PWCTL:
7747 check_pw(ctx);
7748 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
7749 register_name = "PWCtl";
7750 break;
7751 default:
7752 goto cp0_unimplemented;
7753 }
7754 break;
7755 case CP0_REGISTER_07:
7756 switch (sel) {
7757 case CP0_REG07__HWRENA:
7758 check_insn(ctx, ISA_MIPS_R2);
7759 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
7760 register_name = "HWREna";
7761 break;
7762 default:
7763 goto cp0_unimplemented;
7764 }
7765 break;
7766 case CP0_REGISTER_08:
7767 switch (sel) {
7768 case CP0_REG08__BADVADDR:
7769 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
7770 register_name = "BadVAddr";
7771 break;
7772 case CP0_REG08__BADINSTR:
7773 CP0_CHECK(ctx->bi);
7774 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
7775 register_name = "BadInstr";
7776 break;
7777 case CP0_REG08__BADINSTRP:
7778 CP0_CHECK(ctx->bp);
7779 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
7780 register_name = "BadInstrP";
7781 break;
7782 case CP0_REG08__BADINSTRX:
7783 CP0_CHECK(ctx->bi);
7784 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
7785 tcg_gen_andi_tl(arg, arg, ~0xffff);
7786 register_name = "BadInstrX";
7787 break;
7788 default:
7789 goto cp0_unimplemented;
7790 }
7791 break;
7792 case CP0_REGISTER_09:
7793 switch (sel) {
7794 case CP0_REG09__COUNT:
7795 /* Mark as an IO operation because we read the time. */
7796 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
7797 gen_io_start();
7798 }
7799 gen_helper_mfc0_count(arg, cpu_env);
7800 /*
7801 * Break the TB to be able to take timer interrupts immediately
7802 * after reading count. DISAS_STOP isn't sufficient, we need to
7803 * ensure we break completely out of translated code.
7804 */
7805 gen_save_pc(ctx->base.pc_next + 4);
7806 ctx->base.is_jmp = DISAS_EXIT;
7807 register_name = "Count";
7808 break;
7809 case CP0_REG09__SAARI:
7810 CP0_CHECK(ctx->saar);
7811 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
7812 register_name = "SAARI";
7813 break;
7814 case CP0_REG09__SAAR:
7815 CP0_CHECK(ctx->saar);
7816 gen_helper_dmfc0_saar(arg, cpu_env);
7817 register_name = "SAAR";
7818 break;
7819 default:
7820 goto cp0_unimplemented;
7821 }
7822 break;
7823 case CP0_REGISTER_10:
7824 switch (sel) {
7825 case CP0_REG10__ENTRYHI:
7826 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
7827 register_name = "EntryHi";
7828 break;
7829 default:
7830 goto cp0_unimplemented;
7831 }
7832 break;
7833 case CP0_REGISTER_11:
7834 switch (sel) {
7835 case CP0_REG11__COMPARE:
7836 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
7837 register_name = "Compare";
7838 break;
7839 /* 6,7 are implementation dependent */
7840 default:
7841 goto cp0_unimplemented;
7842 }
7843 break;
7844 case CP0_REGISTER_12:
7845 switch (sel) {
7846 case CP0_REG12__STATUS:
7847 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
7848 register_name = "Status";
7849 break;
7850 case CP0_REG12__INTCTL:
7851 check_insn(ctx, ISA_MIPS_R2);
7852 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
7853 register_name = "IntCtl";
7854 break;
7855 case CP0_REG12__SRSCTL:
7856 check_insn(ctx, ISA_MIPS_R2);
7857 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
7858 register_name = "SRSCtl";
7859 break;
7860 case CP0_REG12__SRSMAP:
7861 check_insn(ctx, ISA_MIPS_R2);
7862 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
7863 register_name = "SRSMap";
7864 break;
7865 default:
7866 goto cp0_unimplemented;
7867 }
7868 break;
7869 case CP0_REGISTER_13:
7870 switch (sel) {
7871 case CP0_REG13__CAUSE:
7872 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
7873 register_name = "Cause";
7874 break;
7875 default:
7876 goto cp0_unimplemented;
7877 }
7878 break;
7879 case CP0_REGISTER_14:
7880 switch (sel) {
7881 case CP0_REG14__EPC:
7882 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
7883 register_name = "EPC";
7884 break;
7885 default:
7886 goto cp0_unimplemented;
7887 }
7888 break;
7889 case CP0_REGISTER_15:
7890 switch (sel) {
7891 case CP0_REG15__PRID:
7892 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
7893 register_name = "PRid";
7894 break;
7895 case CP0_REG15__EBASE:
7896 check_insn(ctx, ISA_MIPS_R2);
7897 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
7898 register_name = "EBase";
7899 break;
7900 case CP0_REG15__CMGCRBASE:
7901 check_insn(ctx, ISA_MIPS_R2);
7902 CP0_CHECK(ctx->cmgcr);
7903 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
7904 register_name = "CMGCRBase";
7905 break;
7906 default:
7907 goto cp0_unimplemented;
7908 }
7909 break;
7910 case CP0_REGISTER_16:
7911 switch (sel) {
7912 case CP0_REG16__CONFIG:
7913 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
7914 register_name = "Config";
7915 break;
7916 case CP0_REG16__CONFIG1:
7917 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
7918 register_name = "Config1";
7919 break;
7920 case CP0_REG16__CONFIG2:
7921 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
7922 register_name = "Config2";
7923 break;
7924 case CP0_REG16__CONFIG3:
7925 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
7926 register_name = "Config3";
7927 break;
7928 case CP0_REG16__CONFIG4:
7929 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
7930 register_name = "Config4";
7931 break;
7932 case CP0_REG16__CONFIG5:
7933 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
7934 register_name = "Config5";
7935 break;
7936 /* 6,7 are implementation dependent */
7937 case CP0_REG16__CONFIG6:
7938 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
7939 register_name = "Config6";
7940 break;
7941 case CP0_REG16__CONFIG7:
7942 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
7943 register_name = "Config7";
7944 break;
7945 default:
7946 goto cp0_unimplemented;
7947 }
7948 break;
7949 case CP0_REGISTER_17:
7950 switch (sel) {
7951 case CP0_REG17__LLADDR:
7952 gen_helper_dmfc0_lladdr(arg, cpu_env);
7953 register_name = "LLAddr";
7954 break;
7955 case CP0_REG17__MAAR:
7956 CP0_CHECK(ctx->mrp);
7957 gen_helper_dmfc0_maar(arg, cpu_env);
7958 register_name = "MAAR";
7959 break;
7960 case CP0_REG17__MAARI:
7961 CP0_CHECK(ctx->mrp);
7962 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
7963 register_name = "MAARI";
7964 break;
7965 default:
7966 goto cp0_unimplemented;
7967 }
7968 break;
7969 case CP0_REGISTER_18:
7970 switch (sel) {
7971 case CP0_REG18__WATCHLO0:
7972 case CP0_REG18__WATCHLO1:
7973 case CP0_REG18__WATCHLO2:
7974 case CP0_REG18__WATCHLO3:
7975 case CP0_REG18__WATCHLO4:
7976 case CP0_REG18__WATCHLO5:
7977 case CP0_REG18__WATCHLO6:
7978 case CP0_REG18__WATCHLO7:
7979 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
7980 gen_helper_1e0i(dmfc0_watchlo, arg, sel);
7981 register_name = "WatchLo";
7982 break;
7983 default:
7984 goto cp0_unimplemented;
7985 }
7986 break;
7987 case CP0_REGISTER_19:
7988 switch (sel) {
7989 case CP0_REG19__WATCHHI0:
7990 case CP0_REG19__WATCHHI1:
7991 case CP0_REG19__WATCHHI2:
7992 case CP0_REG19__WATCHHI3:
7993 case CP0_REG19__WATCHHI4:
7994 case CP0_REG19__WATCHHI5:
7995 case CP0_REG19__WATCHHI6:
7996 case CP0_REG19__WATCHHI7:
7997 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
7998 gen_helper_1e0i(dmfc0_watchhi, arg, sel);
7999 register_name = "WatchHi";
8000 break;
8001 default:
8002 goto cp0_unimplemented;
8003 }
8004 break;
8005 case CP0_REGISTER_20:
8006 switch (sel) {
8007 case CP0_REG20__XCONTEXT:
8008 check_insn(ctx, ISA_MIPS3);
8009 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
8010 register_name = "XContext";
8011 break;
8012 default:
8013 goto cp0_unimplemented;
8014 }
8015 break;
8016 case CP0_REGISTER_21:
8017 /* Officially reserved, but sel 0 is used for R1x000 framemask */
8018 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
8019 switch (sel) {
8020 case 0:
8021 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
8022 register_name = "Framemask";
8023 break;
8024 default:
8025 goto cp0_unimplemented;
8026 }
8027 break;
8028 case CP0_REGISTER_22:
8029 tcg_gen_movi_tl(arg, 0); /* unimplemented */
8030 register_name = "'Diagnostic"; /* implementation dependent */
8031 break;
8032 case CP0_REGISTER_23:
8033 switch (sel) {
8034 case CP0_REG23__DEBUG:
8035 gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
8036 register_name = "Debug";
8037 break;
8038 case CP0_REG23__TRACECONTROL:
8039 /* PDtrace support */
8040 /* gen_helper_dmfc0_tracecontrol(arg, cpu_env); */
8041 register_name = "TraceControl";
8042 goto cp0_unimplemented;
8043 case CP0_REG23__TRACECONTROL2:
8044 /* PDtrace support */
8045 /* gen_helper_dmfc0_tracecontrol2(arg, cpu_env); */
8046 register_name = "TraceControl2";
8047 goto cp0_unimplemented;
8048 case CP0_REG23__USERTRACEDATA1:
8049 /* PDtrace support */
8050 /* gen_helper_dmfc0_usertracedata1(arg, cpu_env);*/
8051 register_name = "UserTraceData1";
8052 goto cp0_unimplemented;
8053 case CP0_REG23__TRACEIBPC:
8054 /* PDtrace support */
8055 /* gen_helper_dmfc0_traceibpc(arg, cpu_env); */
8056 register_name = "TraceIBPC";
8057 goto cp0_unimplemented;
8058 case CP0_REG23__TRACEDBPC:
8059 /* PDtrace support */
8060 /* gen_helper_dmfc0_tracedbpc(arg, cpu_env); */
8061 register_name = "TraceDBPC";
8062 goto cp0_unimplemented;
8063 default:
8064 goto cp0_unimplemented;
8065 }
8066 break;
8067 case CP0_REGISTER_24:
8068 switch (sel) {
8069 case CP0_REG24__DEPC:
8070 /* EJTAG support */
8071 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
8072 register_name = "DEPC";
8073 break;
8074 default:
8075 goto cp0_unimplemented;
8076 }
8077 break;
8078 case CP0_REGISTER_25:
8079 switch (sel) {
8080 case CP0_REG25__PERFCTL0:
8081 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
8082 register_name = "Performance0";
8083 break;
8084 case CP0_REG25__PERFCNT0:
8085 /* gen_helper_dmfc0_performance1(arg); */
8086 register_name = "Performance1";
8087 goto cp0_unimplemented;
8088 case CP0_REG25__PERFCTL1:
8089 /* gen_helper_dmfc0_performance2(arg); */
8090 register_name = "Performance2";
8091 goto cp0_unimplemented;
8092 case CP0_REG25__PERFCNT1:
8093 /* gen_helper_dmfc0_performance3(arg); */
8094 register_name = "Performance3";
8095 goto cp0_unimplemented;
8096 case CP0_REG25__PERFCTL2:
8097 /* gen_helper_dmfc0_performance4(arg); */
8098 register_name = "Performance4";
8099 goto cp0_unimplemented;
8100 case CP0_REG25__PERFCNT2:
8101 /* gen_helper_dmfc0_performance5(arg); */
8102 register_name = "Performance5";
8103 goto cp0_unimplemented;
8104 case CP0_REG25__PERFCTL3:
8105 /* gen_helper_dmfc0_performance6(arg); */
8106 register_name = "Performance6";
8107 goto cp0_unimplemented;
8108 case CP0_REG25__PERFCNT3:
8109 /* gen_helper_dmfc0_performance7(arg); */
8110 register_name = "Performance7";
8111 goto cp0_unimplemented;
8112 default:
8113 goto cp0_unimplemented;
8114 }
8115 break;
8116 case CP0_REGISTER_26:
8117 switch (sel) {
8118 case CP0_REG26__ERRCTL:
8119 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
8120 register_name = "ErrCtl";
8121 break;
8122 default:
8123 goto cp0_unimplemented;
8124 }
8125 break;
8126 case CP0_REGISTER_27:
8127 switch (sel) {
8128 /* ignored */
8129 case CP0_REG27__CACHERR:
8130 tcg_gen_movi_tl(arg, 0); /* unimplemented */
8131 register_name = "CacheErr";
8132 break;
8133 default:
8134 goto cp0_unimplemented;
8135 }
8136 break;
8137 case CP0_REGISTER_28:
8138 switch (sel) {
8139 case CP0_REG28__TAGLO:
8140 case CP0_REG28__TAGLO1:
8141 case CP0_REG28__TAGLO2:
8142 case CP0_REG28__TAGLO3:
8143 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
8144 register_name = "TagLo";
8145 break;
8146 case CP0_REG28__DATALO:
8147 case CP0_REG28__DATALO1:
8148 case CP0_REG28__DATALO2:
8149 case CP0_REG28__DATALO3:
8150 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
8151 register_name = "DataLo";
8152 break;
8153 default:
8154 goto cp0_unimplemented;
8155 }
8156 break;
8157 case CP0_REGISTER_29:
8158 switch (sel) {
8159 case CP0_REG29__TAGHI:
8160 case CP0_REG29__TAGHI1:
8161 case CP0_REG29__TAGHI2:
8162 case CP0_REG29__TAGHI3:
8163 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
8164 register_name = "TagHi";
8165 break;
8166 case CP0_REG29__DATAHI:
8167 case CP0_REG29__DATAHI1:
8168 case CP0_REG29__DATAHI2:
8169 case CP0_REG29__DATAHI3:
8170 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
8171 register_name = "DataHi";
8172 break;
8173 default:
8174 goto cp0_unimplemented;
8175 }
8176 break;
8177 case CP0_REGISTER_30:
8178 switch (sel) {
8179 case CP0_REG30__ERROREPC:
8180 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
8181 register_name = "ErrorEPC";
8182 break;
8183 default:
8184 goto cp0_unimplemented;
8185 }
8186 break;
8187 case CP0_REGISTER_31:
8188 switch (sel) {
8189 case CP0_REG31__DESAVE:
8190 /* EJTAG support */
8191 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
8192 register_name = "DESAVE";
8193 break;
8194 case CP0_REG31__KSCRATCH1:
8195 case CP0_REG31__KSCRATCH2:
8196 case CP0_REG31__KSCRATCH3:
8197 case CP0_REG31__KSCRATCH4:
8198 case CP0_REG31__KSCRATCH5:
8199 case CP0_REG31__KSCRATCH6:
8200 CP0_CHECK(ctx->kscrexist & (1 << sel));
8201 tcg_gen_ld_tl(arg, cpu_env,
8202 offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
8203 register_name = "KScratch";
8204 break;
8205 default:
8206 goto cp0_unimplemented;
8207 }
8208 break;
8209 default:
8210 goto cp0_unimplemented;
8211 }
8212 trace_mips_translate_c0("dmfc0", register_name, reg, sel);
8213 return;
8214
8215 cp0_unimplemented:
8216 qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n",
8217 register_name, reg, sel);
8218 gen_mfc0_unimplemented(ctx, arg);
8219 }
8220
8221 static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
8222 {
8223 const char *register_name = "invalid";
8224
8225 if (sel != 0) {
8226 check_insn(ctx, ISA_MIPS_R1);
8227 }
8228
8229 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
8230 gen_io_start();
8231 }
8232
8233 switch (reg) {
8234 case CP0_REGISTER_00:
8235 switch (sel) {
8236 case CP0_REG00__INDEX:
8237 gen_helper_mtc0_index(cpu_env, arg);
8238 register_name = "Index";
8239 break;
8240 case CP0_REG00__MVPCONTROL:
8241 CP0_CHECK(ctx->insn_flags & ASE_MT);
8242 gen_helper_mtc0_mvpcontrol(cpu_env, arg);
8243 register_name = "MVPControl";
8244 break;
8245 case CP0_REG00__MVPCONF0:
8246 CP0_CHECK(ctx->insn_flags & ASE_MT);
8247 /* ignored */
8248 register_name = "MVPConf0";
8249 break;
8250 case CP0_REG00__MVPCONF1:
8251 CP0_CHECK(ctx->insn_flags & ASE_MT);
8252 /* ignored */
8253 register_name = "MVPConf1";
8254 break;
8255 case CP0_REG00__VPCONTROL:
8256 CP0_CHECK(ctx->vp);
8257 /* ignored */
8258 register_name = "VPControl";
8259 break;
8260 default:
8261 goto cp0_unimplemented;
8262 }
8263 break;
8264 case CP0_REGISTER_01:
8265 switch (sel) {
8266 case CP0_REG01__RANDOM:
8267 /* ignored */
8268 register_name = "Random";
8269 break;
8270 case CP0_REG01__VPECONTROL:
8271 CP0_CHECK(ctx->insn_flags & ASE_MT);
8272 gen_helper_mtc0_vpecontrol(cpu_env, arg);
8273 register_name = "VPEControl";
8274 break;
8275 case CP0_REG01__VPECONF0:
8276 CP0_CHECK(ctx->insn_flags & ASE_MT);
8277 gen_helper_mtc0_vpeconf0(cpu_env, arg);
8278 register_name = "VPEConf0";
8279 break;
8280 case CP0_REG01__VPECONF1:
8281 CP0_CHECK(ctx->insn_flags & ASE_MT);
8282 gen_helper_mtc0_vpeconf1(cpu_env, arg);
8283 register_name = "VPEConf1";
8284 break;
8285 case CP0_REG01__YQMASK:
8286 CP0_CHECK(ctx->insn_flags & ASE_MT);
8287 gen_helper_mtc0_yqmask(cpu_env, arg);
8288 register_name = "YQMask";
8289 break;
8290 case CP0_REG01__VPESCHEDULE:
8291 CP0_CHECK(ctx->insn_flags & ASE_MT);
8292 tcg_gen_st_tl(arg, cpu_env,
8293 offsetof(CPUMIPSState, CP0_VPESchedule));
8294 register_name = "VPESchedule";
8295 break;
8296 case CP0_REG01__VPESCHEFBACK:
8297 CP0_CHECK(ctx->insn_flags & ASE_MT);
8298 tcg_gen_st_tl(arg, cpu_env,
8299 offsetof(CPUMIPSState, CP0_VPEScheFBack));
8300 register_name = "VPEScheFBack";
8301 break;
8302 case CP0_REG01__VPEOPT:
8303 CP0_CHECK(ctx->insn_flags & ASE_MT);
8304 gen_helper_mtc0_vpeopt(cpu_env, arg);
8305 register_name = "VPEOpt";
8306 break;
8307 default:
8308 goto cp0_unimplemented;
8309 }
8310 break;
8311 case CP0_REGISTER_02:
8312 switch (sel) {
8313 case CP0_REG02__ENTRYLO0:
8314 gen_helper_dmtc0_entrylo0(cpu_env, arg);
8315 register_name = "EntryLo0";
8316 break;
8317 case CP0_REG02__TCSTATUS:
8318 CP0_CHECK(ctx->insn_flags & ASE_MT);
8319 gen_helper_mtc0_tcstatus(cpu_env, arg);
8320 register_name = "TCStatus";
8321 break;
8322 case CP0_REG02__TCBIND:
8323 CP0_CHECK(ctx->insn_flags & ASE_MT);
8324 gen_helper_mtc0_tcbind(cpu_env, arg);
8325 register_name = "TCBind";
8326 break;
8327 case CP0_REG02__TCRESTART:
8328 CP0_CHECK(ctx->insn_flags & ASE_MT);
8329 gen_helper_mtc0_tcrestart(cpu_env, arg);
8330 register_name = "TCRestart";
8331 break;
8332 case CP0_REG02__TCHALT:
8333 CP0_CHECK(ctx->insn_flags & ASE_MT);
8334 gen_helper_mtc0_tchalt(cpu_env, arg);
8335 register_name = "TCHalt";
8336 break;
8337 case CP0_REG02__TCCONTEXT:
8338 CP0_CHECK(ctx->insn_flags & ASE_MT);
8339 gen_helper_mtc0_tccontext(cpu_env, arg);
8340 register_name = "TCContext";
8341 break;
8342 case CP0_REG02__TCSCHEDULE:
8343 CP0_CHECK(ctx->insn_flags & ASE_MT);
8344 gen_helper_mtc0_tcschedule(cpu_env, arg);
8345 register_name = "TCSchedule";
8346 break;
8347 case CP0_REG02__TCSCHEFBACK:
8348 CP0_CHECK(ctx->insn_flags & ASE_MT);
8349 gen_helper_mtc0_tcschefback(cpu_env, arg);
8350 register_name = "TCScheFBack";
8351 break;
8352 default:
8353 goto cp0_unimplemented;
8354 }
8355 break;
8356 case CP0_REGISTER_03:
8357 switch (sel) {
8358 case CP0_REG03__ENTRYLO1:
8359 gen_helper_dmtc0_entrylo1(cpu_env, arg);
8360 register_name = "EntryLo1";
8361 break;
8362 case CP0_REG03__GLOBALNUM:
8363 CP0_CHECK(ctx->vp);
8364 /* ignored */
8365 register_name = "GlobalNumber";
8366 break;
8367 default:
8368 goto cp0_unimplemented;
8369 }
8370 break;
8371 case CP0_REGISTER_04:
8372 switch (sel) {
8373 case CP0_REG04__CONTEXT:
8374 gen_helper_mtc0_context(cpu_env, arg);
8375 register_name = "Context";
8376 break;
8377 case CP0_REG04__CONTEXTCONFIG:
8378 /* SmartMIPS ASE */
8379 /* gen_helper_dmtc0_contextconfig(arg); */
8380 register_name = "ContextConfig";
8381 goto cp0_unimplemented;
8382 case CP0_REG04__USERLOCAL:
8383 CP0_CHECK(ctx->ulri);
8384 tcg_gen_st_tl(arg, cpu_env,
8385 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
8386 register_name = "UserLocal";
8387 break;
8388 case CP0_REG04__MMID:
8389 CP0_CHECK(ctx->mi);
8390 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID));
8391 register_name = "MMID";
8392 break;
8393 default:
8394 goto cp0_unimplemented;
8395 }
8396 break;
8397 case CP0_REGISTER_05:
8398 switch (sel) {
8399 case CP0_REG05__PAGEMASK:
8400 gen_helper_mtc0_pagemask(cpu_env, arg);
8401 register_name = "PageMask";
8402 break;
8403 case CP0_REG05__PAGEGRAIN:
8404 check_insn(ctx, ISA_MIPS_R2);
8405 gen_helper_mtc0_pagegrain(cpu_env, arg);
8406 register_name = "PageGrain";
8407 break;
8408 case CP0_REG05__SEGCTL0:
8409 CP0_CHECK(ctx->sc);
8410 gen_helper_mtc0_segctl0(cpu_env, arg);
8411 register_name = "SegCtl0";
8412 break;
8413 case CP0_REG05__SEGCTL1:
8414 CP0_CHECK(ctx->sc);
8415 gen_helper_mtc0_segctl1(cpu_env, arg);
8416 register_name = "SegCtl1";
8417 break;
8418 case CP0_REG05__SEGCTL2:
8419 CP0_CHECK(ctx->sc);
8420 gen_helper_mtc0_segctl2(cpu_env, arg);
8421 register_name = "SegCtl2";
8422 break;
8423 case CP0_REG05__PWBASE:
8424 check_pw(ctx);
8425 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
8426 register_name = "PWBase";
8427 break;
8428 case CP0_REG05__PWFIELD:
8429 check_pw(ctx);
8430 gen_helper_mtc0_pwfield(cpu_env, arg);
8431 register_name = "PWField";
8432 break;
8433 case CP0_REG05__PWSIZE:
8434 check_pw(ctx);
8435 gen_helper_mtc0_pwsize(cpu_env, arg);
8436 register_name = "PWSize";
8437 break;
8438 default:
8439 goto cp0_unimplemented;
8440 }
8441 break;
8442 case CP0_REGISTER_06:
8443 switch (sel) {
8444 case CP0_REG06__WIRED:
8445 gen_helper_mtc0_wired(cpu_env, arg);
8446 register_name = "Wired";
8447 break;
8448 case CP0_REG06__SRSCONF0:
8449 check_insn(ctx, ISA_MIPS_R2);
8450 gen_helper_mtc0_srsconf0(cpu_env, arg);
8451 register_name = "SRSConf0";
8452 break;
8453 case CP0_REG06__SRSCONF1:
8454 check_insn(ctx, ISA_MIPS_R2);
8455 gen_helper_mtc0_srsconf1(cpu_env, arg);
8456 register_name = "SRSConf1";
8457 break;
8458 case CP0_REG06__SRSCONF2:
8459 check_insn(ctx, ISA_MIPS_R2);
8460 gen_helper_mtc0_srsconf2(cpu_env, arg);
8461 register_name = "SRSConf2";
8462 break;
8463 case CP0_REG06__SRSCONF3:
8464 check_insn(ctx, ISA_MIPS_R2);
8465 gen_helper_mtc0_srsconf3(cpu_env, arg);
8466 register_name = "SRSConf3";
8467 break;
8468 case CP0_REG06__SRSCONF4:
8469 check_insn(ctx, ISA_MIPS_R2);
8470 gen_helper_mtc0_srsconf4(cpu_env, arg);
8471 register_name = "SRSConf4";
8472 break;
8473 case CP0_REG06__PWCTL:
8474 check_pw(ctx);
8475 gen_helper_mtc0_pwctl(cpu_env, arg);
8476 register_name = "PWCtl";
8477 break;
8478 default:
8479 goto cp0_unimplemented;
8480 }
8481 break;
8482 case CP0_REGISTER_07:
8483 switch (sel) {
8484 case CP0_REG07__HWRENA:
8485 check_insn(ctx, ISA_MIPS_R2);
8486 gen_helper_mtc0_hwrena(cpu_env, arg);
8487 ctx->base.is_jmp = DISAS_STOP;
8488 register_name = "HWREna";
8489 break;
8490 default:
8491 goto cp0_unimplemented;
8492 }
8493 break;
8494 case CP0_REGISTER_08:
8495 switch (sel) {
8496 case CP0_REG08__BADVADDR:
8497 /* ignored */
8498 register_name = "BadVAddr";
8499 break;
8500 case CP0_REG08__BADINSTR:
8501 /* ignored */
8502 register_name = "BadInstr";
8503 break;
8504 case CP0_REG08__BADINSTRP:
8505 /* ignored */
8506 register_name = "BadInstrP";
8507 break;
8508 case CP0_REG08__BADINSTRX:
8509 /* ignored */
8510 register_name = "BadInstrX";
8511 break;
8512 default:
8513 goto cp0_unimplemented;
8514 }
8515 break;
8516 case CP0_REGISTER_09:
8517 switch (sel) {
8518 case CP0_REG09__COUNT:
8519 gen_helper_mtc0_count(cpu_env, arg);
8520 register_name = "Count";
8521 break;
8522 case CP0_REG09__SAARI:
8523 CP0_CHECK(ctx->saar);
8524 gen_helper_mtc0_saari(cpu_env, arg);
8525 register_name = "SAARI";
8526 break;
8527 case CP0_REG09__SAAR:
8528 CP0_CHECK(ctx->saar);
8529 gen_helper_mtc0_saar(cpu_env, arg);
8530 register_name = "SAAR";
8531 break;
8532 default:
8533 goto cp0_unimplemented;
8534 }
8535 /* Stop translation as we may have switched the execution mode */
8536 ctx->base.is_jmp = DISAS_STOP;
8537 break;
8538 case CP0_REGISTER_10:
8539 switch (sel) {
8540 case CP0_REG10__ENTRYHI:
8541 gen_helper_mtc0_entryhi(cpu_env, arg);
8542 register_name = "EntryHi";
8543 break;
8544 default:
8545 goto cp0_unimplemented;
8546 }
8547 break;
8548 case CP0_REGISTER_11:
8549 switch (sel) {
8550 case CP0_REG11__COMPARE:
8551 gen_helper_mtc0_compare(cpu_env, arg);
8552 register_name = "Compare";
8553 break;
8554 /* 6,7 are implementation dependent */
8555 default:
8556 goto cp0_unimplemented;
8557 }
8558 /* Stop translation as we may have switched the execution mode */
8559 ctx->base.is_jmp = DISAS_STOP;
8560 break;
8561 case CP0_REGISTER_12:
8562 switch (sel) {
8563 case CP0_REG12__STATUS:
8564 save_cpu_state(ctx, 1);
8565 gen_helper_mtc0_status(cpu_env, arg);
8566 /* DISAS_STOP isn't good enough here, hflags may have changed. */
8567 gen_save_pc(ctx->base.pc_next + 4);
8568 ctx->base.is_jmp = DISAS_EXIT;
8569 register_name = "Status";
8570 break;
8571 case CP0_REG12__INTCTL:
8572 check_insn(ctx, ISA_MIPS_R2);
8573 gen_helper_mtc0_intctl(cpu_env, arg);
8574 /* Stop translation as we may have switched the execution mode */
8575 ctx->base.is_jmp = DISAS_STOP;
8576 register_name = "IntCtl";
8577 break;
8578 case CP0_REG12__SRSCTL:
8579 check_insn(ctx, ISA_MIPS_R2);
8580 gen_helper_mtc0_srsctl(cpu_env, arg);
8581 /* Stop translation as we may have switched the execution mode */
8582 ctx->base.is_jmp = DISAS_STOP;
8583 register_name = "SRSCtl";
8584 break;
8585 case CP0_REG12__SRSMAP:
8586 check_insn(ctx, ISA_MIPS_R2);
8587 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
8588 /* Stop translation as we may have switched the execution mode */
8589 ctx->base.is_jmp = DISAS_STOP;
8590 register_name = "SRSMap";
8591 break;
8592 default:
8593 goto cp0_unimplemented;
8594 }
8595 break;
8596 case CP0_REGISTER_13:
8597 switch (sel) {
8598 case CP0_REG13__CAUSE:
8599 save_cpu_state(ctx, 1);
8600 gen_helper_mtc0_cause(cpu_env, arg);
8601 /*
8602 * Stop translation as we may have triggered an interrupt.
8603 * DISAS_STOP isn't sufficient, we need to ensure we break out of
8604 * translated code to check for pending interrupts.
8605 */
8606 gen_save_pc(ctx->base.pc_next + 4);
8607 ctx->base.is_jmp = DISAS_EXIT;
8608 register_name = "Cause";
8609 break;
8610 default:
8611 goto cp0_unimplemented;
8612 }
8613 break;
8614 case CP0_REGISTER_14:
8615 switch (sel) {
8616 case CP0_REG14__EPC:
8617 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
8618 register_name = "EPC";
8619 break;
8620 default:
8621 goto cp0_unimplemented;
8622 }
8623 break;
8624 case CP0_REGISTER_15:
8625 switch (sel) {
8626 case CP0_REG15__PRID:
8627 /* ignored */
8628 register_name = "PRid";
8629 break;
8630 case CP0_REG15__EBASE:
8631 check_insn(ctx, ISA_MIPS_R2);
8632 gen_helper_mtc0_ebase(cpu_env, arg);
8633 register_name = "EBase";
8634 break;
8635 default:
8636 goto cp0_unimplemented;
8637 }
8638 break;
8639 case CP0_REGISTER_16:
8640 switch (sel) {
8641 case CP0_REG16__CONFIG:
8642 gen_helper_mtc0_config0(cpu_env, arg);
8643 register_name = "Config";
8644 /* Stop translation as we may have switched the execution mode */
8645 ctx->base.is_jmp = DISAS_STOP;
8646 break;
8647 case CP0_REG16__CONFIG1:
8648 /* ignored, read only */
8649 register_name = "Config1";
8650 break;
8651 case CP0_REG16__CONFIG2:
8652 gen_helper_mtc0_config2(cpu_env, arg);
8653 register_name = "Config2";
8654 /* Stop translation as we may have switched the execution mode */
8655 ctx->base.is_jmp = DISAS_STOP;
8656 break;
8657 case CP0_REG16__CONFIG3:
8658 gen_helper_mtc0_config3(cpu_env, arg);
8659 register_name = "Config3";
8660 /* Stop translation as we may have switched the execution mode */
8661 ctx->base.is_jmp = DISAS_STOP;
8662 break;
8663 case CP0_REG16__CONFIG4:
8664 /* currently ignored */
8665 register_name = "Config4";
8666 break;
8667 case CP0_REG16__CONFIG5:
8668 gen_helper_mtc0_config5(cpu_env, arg);
8669 register_name = "Config5";
8670 /* Stop translation as we may have switched the execution mode */
8671 ctx->base.is_jmp = DISAS_STOP;
8672 break;
8673 /* 6,7 are implementation dependent */
8674 default:
8675 register_name = "Invalid config selector";
8676 goto cp0_unimplemented;
8677 }
8678 break;
8679 case CP0_REGISTER_17:
8680 switch (sel) {
8681 case CP0_REG17__LLADDR:
8682 gen_helper_mtc0_lladdr(cpu_env, arg);
8683 register_name = "LLAddr";
8684 break;
8685 case CP0_REG17__MAAR:
8686 CP0_CHECK(ctx->mrp);
8687 gen_helper_mtc0_maar(cpu_env, arg);
8688 register_name = "MAAR";
8689 break;
8690 case CP0_REG17__MAARI:
8691 CP0_CHECK(ctx->mrp);
8692 gen_helper_mtc0_maari(cpu_env, arg);
8693 register_name = "MAARI";
8694 break;
8695 default:
8696 goto cp0_unimplemented;
8697 }
8698 break;
8699 case CP0_REGISTER_18:
8700 switch (sel) {
8701 case CP0_REG18__WATCHLO0:
8702 case CP0_REG18__WATCHLO1:
8703 case CP0_REG18__WATCHLO2:
8704 case CP0_REG18__WATCHLO3:
8705 case CP0_REG18__WATCHLO4:
8706 case CP0_REG18__WATCHLO5:
8707 case CP0_REG18__WATCHLO6:
8708 case CP0_REG18__WATCHLO7:
8709 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
8710 gen_helper_0e1i(mtc0_watchlo, arg, sel);
8711 register_name = "WatchLo";
8712 break;
8713 default:
8714 goto cp0_unimplemented;
8715 }
8716 break;
8717 case CP0_REGISTER_19:
8718 switch (sel) {
8719 case CP0_REG19__WATCHHI0:
8720 case CP0_REG19__WATCHHI1:
8721 case CP0_REG19__WATCHHI2:
8722 case CP0_REG19__WATCHHI3:
8723 case CP0_REG19__WATCHHI4:
8724 case CP0_REG19__WATCHHI5:
8725 case CP0_REG19__WATCHHI6:
8726 case CP0_REG19__WATCHHI7:
8727 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
8728 gen_helper_0e1i(mtc0_watchhi, arg, sel);
8729 register_name = "WatchHi";
8730 break;
8731 default:
8732 goto cp0_unimplemented;
8733 }
8734 break;
8735 case CP0_REGISTER_20:
8736 switch (sel) {
8737 case CP0_REG20__XCONTEXT:
8738 check_insn(ctx, ISA_MIPS3);
8739 gen_helper_mtc0_xcontext(cpu_env, arg);
8740 register_name = "XContext";
8741 break;
8742 default:
8743 goto cp0_unimplemented;
8744 }
8745 break;
8746 case CP0_REGISTER_21:
8747 /* Officially reserved, but sel 0 is used for R1x000 framemask */
8748 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
8749 switch (sel) {
8750 case 0:
8751 gen_helper_mtc0_framemask(cpu_env, arg);
8752 register_name = "Framemask";
8753 break;
8754 default:
8755 goto cp0_unimplemented;
8756 }
8757 break;
8758 case CP0_REGISTER_22:
8759 /* ignored */
8760 register_name = "Diagnostic"; /* implementation dependent */
8761 break;
8762 case CP0_REGISTER_23:
8763 switch (sel) {
8764 case CP0_REG23__DEBUG:
8765 gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
8766 /* DISAS_STOP isn't good enough here, hflags may have changed. */
8767 gen_save_pc(ctx->base.pc_next + 4);
8768 ctx->base.is_jmp = DISAS_EXIT;
8769 register_name = "Debug";
8770 break;
8771 case CP0_REG23__TRACECONTROL:
8772 /* PDtrace support */
8773 /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
8774 /* Stop translation as we may have switched the execution mode */
8775 ctx->base.is_jmp = DISAS_STOP;
8776 register_name = "TraceControl";
8777 goto cp0_unimplemented;
8778 case CP0_REG23__TRACECONTROL2:
8779 /* PDtrace support */
8780 /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
8781 /* Stop translation as we may have switched the execution mode */
8782 ctx->base.is_jmp = DISAS_STOP;
8783 register_name = "TraceControl2";
8784 goto cp0_unimplemented;
8785 case CP0_REG23__USERTRACEDATA1:
8786 /* PDtrace support */
8787 /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
8788 /* Stop translation as we may have switched the execution mode */
8789 ctx->base.is_jmp = DISAS_STOP;
8790 register_name = "UserTraceData1";
8791 goto cp0_unimplemented;
8792 case CP0_REG23__TRACEIBPC:
8793 /* PDtrace support */
8794 /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
8795 /* Stop translation as we may have switched the execution mode */
8796 ctx->base.is_jmp = DISAS_STOP;
8797 register_name = "TraceIBPC";
8798 goto cp0_unimplemented;
8799 case CP0_REG23__TRACEDBPC:
8800 /* PDtrace support */
8801 /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
8802 /* Stop translation as we may have switched the execution mode */
8803 ctx->base.is_jmp = DISAS_STOP;
8804 register_name = "TraceDBPC";
8805 goto cp0_unimplemented;
8806 default:
8807 goto cp0_unimplemented;
8808 }
8809 break;
8810 case CP0_REGISTER_24:
8811 switch (sel) {
8812 case CP0_REG24__DEPC:
8813 /* EJTAG support */
8814 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
8815 register_name = "DEPC";
8816 break;
8817 default:
8818 goto cp0_unimplemented;
8819 }
8820 break;
8821 case CP0_REGISTER_25:
8822 switch (sel) {
8823 case CP0_REG25__PERFCTL0:
8824 gen_helper_mtc0_performance0(cpu_env, arg);
8825 register_name = "Performance0";
8826 break;
8827 case CP0_REG25__PERFCNT0:
8828 /* gen_helper_mtc0_performance1(cpu_env, arg); */
8829 register_name = "Performance1";
8830 goto cp0_unimplemented;
8831 case CP0_REG25__PERFCTL1:
8832 /* gen_helper_mtc0_performance2(cpu_env, arg); */
8833 register_name = "Performance2";
8834 goto cp0_unimplemented;
8835 case CP0_REG25__PERFCNT1:
8836 /* gen_helper_mtc0_performance3(cpu_env, arg); */
8837 register_name = "Performance3";
8838 goto cp0_unimplemented;
8839 case CP0_REG25__PERFCTL2:
8840 /* gen_helper_mtc0_performance4(cpu_env, arg); */
8841 register_name = "Performance4";
8842 goto cp0_unimplemented;
8843 case CP0_REG25__PERFCNT2:
8844 /* gen_helper_mtc0_performance5(cpu_env, arg); */
8845 register_name = "Performance5";
8846 goto cp0_unimplemented;
8847 case CP0_REG25__PERFCTL3:
8848 /* gen_helper_mtc0_performance6(cpu_env, arg); */
8849 register_name = "Performance6";
8850 goto cp0_unimplemented;
8851 case CP0_REG25__PERFCNT3:
8852 /* gen_helper_mtc0_performance7(cpu_env, arg); */
8853 register_name = "Performance7";
8854 goto cp0_unimplemented;
8855 default:
8856 goto cp0_unimplemented;
8857 }
8858 break;
8859 case CP0_REGISTER_26:
8860 switch (sel) {
8861 case CP0_REG26__ERRCTL:
8862 gen_helper_mtc0_errctl(cpu_env, arg);
8863 ctx->base.is_jmp = DISAS_STOP;
8864 register_name = "ErrCtl";
8865 break;
8866 default:
8867 goto cp0_unimplemented;
8868 }
8869 break;
8870 case CP0_REGISTER_27:
8871 switch (sel) {
8872 case CP0_REG27__CACHERR:
8873 /* ignored */
8874 register_name = "CacheErr";
8875 break;
8876 default:
8877 goto cp0_unimplemented;
8878 }
8879 break;
8880 case CP0_REGISTER_28:
8881 switch (sel) {
8882 case CP0_REG28__TAGLO:
8883 case CP0_REG28__TAGLO1:
8884 case CP0_REG28__TAGLO2:
8885 case CP0_REG28__TAGLO3:
8886 gen_helper_mtc0_taglo(cpu_env, arg);
8887 register_name = "TagLo";
8888 break;
8889 case CP0_REG28__DATALO:
8890 case CP0_REG28__DATALO1:
8891 case CP0_REG28__DATALO2:
8892 case CP0_REG28__DATALO3:
8893 gen_helper_mtc0_datalo(cpu_env, arg);
8894 register_name = "DataLo";
8895 break;
8896 default:
8897 goto cp0_unimplemented;
8898 }
8899 break;
8900 case CP0_REGISTER_29:
8901 switch (sel) {
8902 case CP0_REG29__TAGHI:
8903 case CP0_REG29__TAGHI1:
8904 case CP0_REG29__TAGHI2:
8905 case CP0_REG29__TAGHI3:
8906 gen_helper_mtc0_taghi(cpu_env, arg);
8907 register_name = "TagHi";
8908 break;
8909 case CP0_REG29__DATAHI:
8910 case CP0_REG29__DATAHI1:
8911 case CP0_REG29__DATAHI2:
8912 case CP0_REG29__DATAHI3:
8913 gen_helper_mtc0_datahi(cpu_env, arg);
8914 register_name = "DataHi";
8915 break;
8916 default:
8917 register_name = "invalid sel";
8918 goto cp0_unimplemented;
8919 }
8920 break;
8921 case CP0_REGISTER_30:
8922 switch (sel) {
8923 case CP0_REG30__ERROREPC:
8924 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
8925 register_name = "ErrorEPC";
8926 break;
8927 default:
8928 goto cp0_unimplemented;
8929 }
8930 break;
8931 case CP0_REGISTER_31:
8932 switch (sel) {
8933 case CP0_REG31__DESAVE:
8934 /* EJTAG support */
8935 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
8936 register_name = "DESAVE";
8937 break;
8938 case CP0_REG31__KSCRATCH1:
8939 case CP0_REG31__KSCRATCH2:
8940 case CP0_REG31__KSCRATCH3:
8941 case CP0_REG31__KSCRATCH4:
8942 case CP0_REG31__KSCRATCH5:
8943 case CP0_REG31__KSCRATCH6:
8944 CP0_CHECK(ctx->kscrexist & (1 << sel));
8945 tcg_gen_st_tl(arg, cpu_env,
8946 offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
8947 register_name = "KScratch";
8948 break;
8949 default:
8950 goto cp0_unimplemented;
8951 }
8952 break;
8953 default:
8954 goto cp0_unimplemented;
8955 }
8956 trace_mips_translate_c0("dmtc0", register_name, reg, sel);
8957
8958 /* For simplicity assume that all writes can cause interrupts. */
8959 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
8960 /*
8961 * DISAS_STOP isn't sufficient, we need to ensure we break out of
8962 * translated code to check for pending interrupts.
8963 */
8964 gen_save_pc(ctx->base.pc_next + 4);
8965 ctx->base.is_jmp = DISAS_EXIT;
8966 }
8967 return;
8968
8969 cp0_unimplemented:
8970 qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n",
8971 register_name, reg, sel);
8972 }
8973 #endif /* TARGET_MIPS64 */
8974
8975 static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
8976 int u, int sel, int h)
8977 {
8978 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
8979 TCGv t0 = tcg_temp_local_new();
8980
8981 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
8982 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
8983 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {
8984 tcg_gen_movi_tl(t0, -1);
8985 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
8986 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {
8987 tcg_gen_movi_tl(t0, -1);
8988 } else if (u == 0) {
8989 switch (rt) {
8990 case 1:
8991 switch (sel) {
8992 case 1:
8993 gen_helper_mftc0_vpecontrol(t0, cpu_env);
8994 break;
8995 case 2:
8996 gen_helper_mftc0_vpeconf0(t0, cpu_env);
8997 break;
8998 default:
8999 goto die;
9000 break;
9001 }
9002 break;
9003 case 2:
9004 switch (sel) {
9005 case 1:
9006 gen_helper_mftc0_tcstatus(t0, cpu_env);
9007 break;
9008 case 2:
9009 gen_helper_mftc0_tcbind(t0, cpu_env);
9010 break;
9011 case 3:
9012 gen_helper_mftc0_tcrestart(t0, cpu_env);
9013 break;
9014 case 4:
9015 gen_helper_mftc0_tchalt(t0, cpu_env);
9016 break;
9017 case 5:
9018 gen_helper_mftc0_tccontext(t0, cpu_env);
9019 break;
9020 case 6:
9021 gen_helper_mftc0_tcschedule(t0, cpu_env);
9022 break;
9023 case 7:
9024 gen_helper_mftc0_tcschefback(t0, cpu_env);
9025 break;
9026 default:
9027 gen_mfc0(ctx, t0, rt, sel);
9028 break;
9029 }
9030 break;
9031 case 10:
9032 switch (sel) {
9033 case 0:
9034 gen_helper_mftc0_entryhi(t0, cpu_env);
9035 break;
9036 default:
9037 gen_mfc0(ctx, t0, rt, sel);
9038 break;
9039 }
9040 break;
9041 case 12:
9042 switch (sel) {
9043 case 0:
9044 gen_helper_mftc0_status(t0, cpu_env);
9045 break;
9046 default:
9047 gen_mfc0(ctx, t0, rt, sel);
9048 break;
9049 }
9050 break;
9051 case 13:
9052 switch (sel) {
9053 case 0:
9054 gen_helper_mftc0_cause(t0, cpu_env);
9055 break;
9056 default:
9057 goto die;
9058 break;
9059 }
9060 break;
9061 case 14:
9062 switch (sel) {
9063 case 0:
9064 gen_helper_mftc0_epc(t0, cpu_env);
9065 break;
9066 default:
9067 goto die;
9068 break;
9069 }
9070 break;
9071 case 15:
9072 switch (sel) {
9073 case 1:
9074 gen_helper_mftc0_ebase(t0, cpu_env);
9075 break;
9076 default:
9077 goto die;
9078 break;
9079 }
9080 break;
9081 case 16:
9082 switch (sel) {
9083 case 0:
9084 case 1:
9085 case 2:
9086 case 3:
9087 case 4:
9088 case 5:
9089 case 6:
9090 case 7:
9091 gen_helper_mftc0_configx(t0, cpu_env, tcg_const_tl(sel));
9092 break;
9093 default:
9094 goto die;
9095 break;
9096 }
9097 break;
9098 case 23:
9099 switch (sel) {
9100 case 0:
9101 gen_helper_mftc0_debug(t0, cpu_env);
9102 break;
9103 default:
9104 gen_mfc0(ctx, t0, rt, sel);
9105 break;
9106 }
9107 break;
9108 default:
9109 gen_mfc0(ctx, t0, rt, sel);
9110 }
9111 } else {
9112 switch (sel) {
9113 /* GPR registers. */
9114 case 0:
9115 gen_helper_1e0i(mftgpr, t0, rt);
9116 break;
9117 /* Auxiliary CPU registers */
9118 case 1:
9119 switch (rt) {
9120 case 0:
9121 gen_helper_1e0i(mftlo, t0, 0);
9122 break;
9123 case 1:
9124 gen_helper_1e0i(mfthi, t0, 0);
9125 break;
9126 case 2:
9127 gen_helper_1e0i(mftacx, t0, 0);
9128 break;
9129 case 4:
9130 gen_helper_1e0i(mftlo, t0, 1);
9131 break;
9132 case 5:
9133 gen_helper_1e0i(mfthi, t0, 1);
9134 break;
9135 case 6:
9136 gen_helper_1e0i(mftacx, t0, 1);
9137 break;
9138 case 8:
9139 gen_helper_1e0i(mftlo, t0, 2);
9140 break;
9141 case 9:
9142 gen_helper_1e0i(mfthi, t0, 2);
9143 break;
9144 case 10:
9145 gen_helper_1e0i(mftacx, t0, 2);
9146 break;
9147 case 12:
9148 gen_helper_1e0i(mftlo, t0, 3);
9149 break;
9150 case 13:
9151 gen_helper_1e0i(mfthi, t0, 3);
9152 break;
9153 case 14:
9154 gen_helper_1e0i(mftacx, t0, 3);
9155 break;
9156 case 16:
9157 gen_helper_mftdsp(t0, cpu_env);
9158 break;
9159 default:
9160 goto die;
9161 }
9162 break;
9163 /* Floating point (COP1). */
9164 case 2:
9165 /* XXX: For now we support only a single FPU context. */
9166 if (h == 0) {
9167 TCGv_i32 fp0 = tcg_temp_new_i32();
9168
9169 gen_load_fpr32(ctx, fp0, rt);
9170 tcg_gen_ext_i32_tl(t0, fp0);
9171 tcg_temp_free_i32(fp0);
9172 } else {
9173 TCGv_i32 fp0 = tcg_temp_new_i32();
9174
9175 gen_load_fpr32h(ctx, fp0, rt);
9176 tcg_gen_ext_i32_tl(t0, fp0);
9177 tcg_temp_free_i32(fp0);
9178 }
9179 break;
9180 case 3:
9181 /* XXX: For now we support only a single FPU context. */
9182 gen_helper_1e0i(cfc1, t0, rt);
9183 break;
9184 /* COP2: Not implemented. */
9185 case 4:
9186 case 5:
9187 /* fall through */
9188 default:
9189 goto die;
9190 }
9191 }
9192 trace_mips_translate_tr("mftr", rt, u, sel, h);
9193 gen_store_gpr(t0, rd);
9194 tcg_temp_free(t0);
9195 return;
9196
9197 die:
9198 tcg_temp_free(t0);
9199 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
9200 gen_reserved_instruction(ctx);
9201 }
9202
9203 static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
9204 int u, int sel, int h)
9205 {
9206 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
9207 TCGv t0 = tcg_temp_local_new();
9208
9209 gen_load_gpr(t0, rt);
9210 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
9211 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
9212 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {
9213 /* NOP */
9214 ;
9215 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
9216 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {
9217 /* NOP */
9218 ;
9219 } else if (u == 0) {
9220 switch (rd) {
9221 case 1:
9222 switch (sel) {
9223 case 1:
9224 gen_helper_mttc0_vpecontrol(cpu_env, t0);
9225 break;
9226 case 2:
9227 gen_helper_mttc0_vpeconf0(cpu_env, t0);
9228 break;
9229 default:
9230 goto die;
9231 break;
9232 }
9233 break;
9234 case 2:
9235 switch (sel) {
9236 case 1:
9237 gen_helper_mttc0_tcstatus(cpu_env, t0);
9238 break;
9239 case 2:
9240 gen_helper_mttc0_tcbind(cpu_env, t0);
9241 break;
9242 case 3:
9243 gen_helper_mttc0_tcrestart(cpu_env, t0);
9244 break;
9245 case 4:
9246 gen_helper_mttc0_tchalt(cpu_env, t0);
9247 break;
9248 case 5:
9249 gen_helper_mttc0_tccontext(cpu_env, t0);
9250 break;
9251 case 6:
9252 gen_helper_mttc0_tcschedule(cpu_env, t0);
9253 break;
9254 case 7:
9255 gen_helper_mttc0_tcschefback(cpu_env, t0);
9256 break;
9257 default:
9258 gen_mtc0(ctx, t0, rd, sel);
9259 break;
9260 }
9261 break;
9262 case 10:
9263 switch (sel) {
9264 case 0:
9265 gen_helper_mttc0_entryhi(cpu_env, t0);
9266 break;
9267 default:
9268 gen_mtc0(ctx, t0, rd, sel);
9269 break;
9270 }
9271 break;
9272 case 12:
9273 switch (sel) {
9274 case 0:
9275 gen_helper_mttc0_status(cpu_env, t0);
9276 break;
9277 default:
9278 gen_mtc0(ctx, t0, rd, sel);
9279 break;
9280 }
9281 break;
9282 case 13:
9283 switch (sel) {
9284 case 0:
9285 gen_helper_mttc0_cause(cpu_env, t0);
9286 break;
9287 default:
9288 goto die;
9289 break;
9290 }
9291 break;
9292 case 15:
9293 switch (sel) {
9294 case 1:
9295 gen_helper_mttc0_ebase(cpu_env, t0);
9296 break;
9297 default:
9298 goto die;
9299 break;
9300 }
9301 break;
9302 case 23:
9303 switch (sel) {
9304 case 0:
9305 gen_helper_mttc0_debug(cpu_env, t0);
9306 break;
9307 default:
9308 gen_mtc0(ctx, t0, rd, sel);
9309 break;
9310 }
9311 break;
9312 default:
9313 gen_mtc0(ctx, t0, rd, sel);
9314 }
9315 } else {
9316 switch (sel) {
9317 /* GPR registers. */
9318 case 0:
9319 gen_helper_0e1i(mttgpr, t0, rd);
9320 break;
9321 /* Auxiliary CPU registers */
9322 case 1:
9323 switch (rd) {
9324 case 0:
9325 gen_helper_0e1i(mttlo, t0, 0);
9326 break;
9327 case 1:
9328 gen_helper_0e1i(mtthi, t0, 0);
9329 break;
9330 case 2:
9331 gen_helper_0e1i(mttacx, t0, 0);
9332 break;
9333 case 4:
9334 gen_helper_0e1i(mttlo, t0, 1);
9335 break;
9336 case 5:
9337 gen_helper_0e1i(mtthi, t0, 1);
9338 break;
9339 case 6:
9340 gen_helper_0e1i(mttacx, t0, 1);
9341 break;
9342 case 8:
9343 gen_helper_0e1i(mttlo, t0, 2);
9344 break;
9345 case 9:
9346 gen_helper_0e1i(mtthi, t0, 2);
9347 break;
9348 case 10:
9349 gen_helper_0e1i(mttacx, t0, 2);
9350 break;
9351 case 12:
9352 gen_helper_0e1i(mttlo, t0, 3);
9353 break;
9354 case 13:
9355 gen_helper_0e1i(mtthi, t0, 3);
9356 break;
9357 case 14:
9358 gen_helper_0e1i(mttacx, t0, 3);
9359 break;
9360 case 16:
9361 gen_helper_mttdsp(cpu_env, t0);
9362 break;
9363 default:
9364 goto die;
9365 }
9366 break;
9367 /* Floating point (COP1). */
9368 case 2:
9369 /* XXX: For now we support only a single FPU context. */
9370 if (h == 0) {
9371 TCGv_i32 fp0 = tcg_temp_new_i32();
9372
9373 tcg_gen_trunc_tl_i32(fp0, t0);
9374 gen_store_fpr32(ctx, fp0, rd);
9375 tcg_temp_free_i32(fp0);
9376 } else {
9377 TCGv_i32 fp0 = tcg_temp_new_i32();
9378
9379 tcg_gen_trunc_tl_i32(fp0, t0);
9380 gen_store_fpr32h(ctx, fp0, rd);
9381 tcg_temp_free_i32(fp0);
9382 }
9383 break;
9384 case 3:
9385 /* XXX: For now we support only a single FPU context. */
9386 {
9387 TCGv_i32 fs_tmp = tcg_const_i32(rd);
9388
9389 gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
9390 tcg_temp_free_i32(fs_tmp);
9391 }
9392 /* Stop translation as we may have changed hflags */
9393 ctx->base.is_jmp = DISAS_STOP;
9394 break;
9395 /* COP2: Not implemented. */
9396 case 4:
9397 case 5:
9398 /* fall through */
9399 default:
9400 goto die;
9401 }
9402 }
9403 trace_mips_translate_tr("mttr", rd, u, sel, h);
9404 tcg_temp_free(t0);
9405 return;
9406
9407 die:
9408 tcg_temp_free(t0);
9409 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
9410 gen_reserved_instruction(ctx);
9411 }
9412
9413 static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
9414 int rt, int rd)
9415 {
9416 const char *opn = "ldst";
9417
9418 check_cp0_enabled(ctx);
9419 switch (opc) {
9420 case OPC_MFC0:
9421 if (rt == 0) {
9422 /* Treat as NOP. */
9423 return;
9424 }
9425 gen_mfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
9426 opn = "mfc0";
9427 break;
9428 case OPC_MTC0:
9429 {
9430 TCGv t0 = tcg_temp_new();
9431
9432 gen_load_gpr(t0, rt);
9433 gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7);
9434 tcg_temp_free(t0);
9435 }
9436 opn = "mtc0";
9437 break;
9438 #if defined(TARGET_MIPS64)
9439 case OPC_DMFC0:
9440 check_insn(ctx, ISA_MIPS3);
9441 if (rt == 0) {
9442 /* Treat as NOP. */
9443 return;
9444 }
9445 gen_dmfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
9446 opn = "dmfc0";
9447 break;
9448 case OPC_DMTC0:
9449 check_insn(ctx, ISA_MIPS3);
9450 {
9451 TCGv t0 = tcg_temp_new();
9452
9453 gen_load_gpr(t0, rt);
9454 gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7);
9455 tcg_temp_free(t0);
9456 }
9457 opn = "dmtc0";
9458 break;
9459 #endif
9460 case OPC_MFHC0:
9461 check_mvh(ctx);
9462 if (rt == 0) {
9463 /* Treat as NOP. */
9464 return;
9465 }
9466 gen_mfhc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
9467 opn = "mfhc0";
9468 break;
9469 case OPC_MTHC0:
9470 check_mvh(ctx);
9471 {
9472 TCGv t0 = tcg_temp_new();
9473 gen_load_gpr(t0, rt);
9474 gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7);
9475 tcg_temp_free(t0);
9476 }
9477 opn = "mthc0";
9478 break;
9479 case OPC_MFTR:
9480 check_cp0_enabled(ctx);
9481 if (rd == 0) {
9482 /* Treat as NOP. */
9483 return;
9484 }
9485 gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1,
9486 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
9487 opn = "mftr";
9488 break;
9489 case OPC_MTTR:
9490 check_cp0_enabled(ctx);
9491 gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
9492 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
9493 opn = "mttr";
9494 break;
9495 case OPC_TLBWI:
9496 opn = "tlbwi";
9497 if (!env->tlb->helper_tlbwi) {
9498 goto die;
9499 }
9500 gen_helper_tlbwi(cpu_env);
9501 break;
9502 case OPC_TLBINV:
9503 opn = "tlbinv";
9504 if (ctx->ie >= 2) {
9505 if (!env->tlb->helper_tlbinv) {
9506 goto die;
9507 }
9508 gen_helper_tlbinv(cpu_env);
9509 } /* treat as nop if TLBINV not supported */
9510 break;
9511 case OPC_TLBINVF:
9512 opn = "tlbinvf";
9513 if (ctx->ie >= 2) {
9514 if (!env->tlb->helper_tlbinvf) {
9515 goto die;
9516 }
9517 gen_helper_tlbinvf(cpu_env);
9518 } /* treat as nop if TLBINV not supported */
9519 break;
9520 case OPC_TLBWR:
9521 opn = "tlbwr";
9522 if (!env->tlb->helper_tlbwr) {
9523 goto die;
9524 }
9525 gen_helper_tlbwr(cpu_env);
9526 break;
9527 case OPC_TLBP:
9528 opn = "tlbp";
9529 if (!env->tlb->helper_tlbp) {
9530 goto die;
9531 }
9532 gen_helper_tlbp(cpu_env);
9533 break;
9534 case OPC_TLBR:
9535 opn = "tlbr";
9536 if (!env->tlb->helper_tlbr) {
9537 goto die;
9538 }
9539 gen_helper_tlbr(cpu_env);
9540 break;
9541 case OPC_ERET: /* OPC_ERETNC */
9542 if ((ctx->insn_flags & ISA_MIPS_R6) &&
9543 (ctx->hflags & MIPS_HFLAG_BMASK)) {
9544 goto die;
9545 } else {
9546 int bit_shift = (ctx->hflags & MIPS_HFLAG_M16) ? 16 : 6;
9547 if (ctx->opcode & (1 << bit_shift)) {
9548 /* OPC_ERETNC */
9549 opn = "eretnc";
9550 check_insn(ctx, ISA_MIPS_R5);
9551 gen_helper_eretnc(cpu_env);
9552 } else {
9553 /* OPC_ERET */
9554 opn = "eret";
9555 check_insn(ctx, ISA_MIPS2);
9556 gen_helper_eret(cpu_env);
9557 }
9558 ctx->base.is_jmp = DISAS_EXIT;
9559 }
9560 break;
9561 case OPC_DERET:
9562 opn = "deret";
9563 check_insn(ctx, ISA_MIPS_R1);
9564 if ((ctx->insn_flags & ISA_MIPS_R6) &&
9565 (ctx->hflags & MIPS_HFLAG_BMASK)) {
9566 goto die;
9567 }
9568 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
9569 MIPS_INVAL(opn);
9570 gen_reserved_instruction(ctx);
9571 } else {
9572 gen_helper_deret(cpu_env);
9573 ctx->base.is_jmp = DISAS_EXIT;
9574 }
9575 break;
9576 case OPC_WAIT:
9577 opn = "wait";
9578 check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
9579 if ((ctx->insn_flags & ISA_MIPS_R6) &&
9580 (ctx->hflags & MIPS_HFLAG_BMASK)) {
9581 goto die;
9582 }
9583 /* If we get an exception, we want to restart at next instruction */
9584 ctx->base.pc_next += 4;
9585 save_cpu_state(ctx, 1);
9586 ctx->base.pc_next -= 4;
9587 gen_helper_wait(cpu_env);
9588 ctx->base.is_jmp = DISAS_NORETURN;
9589 break;
9590 default:
9591 die:
9592 MIPS_INVAL(opn);
9593 gen_reserved_instruction(ctx);
9594 return;
9595 }
9596 (void)opn; /* avoid a compiler warning */
9597 }
9598 #endif /* !CONFIG_USER_ONLY */
9599
9600 /* CP1 Branches (before delay slot) */
9601 static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
9602 int32_t cc, int32_t offset)
9603 {
9604 target_ulong btarget;
9605 TCGv_i32 t0 = tcg_temp_new_i32();
9606
9607 if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) {
9608 gen_reserved_instruction(ctx);
9609 goto out;
9610 }
9611
9612 if (cc != 0) {
9613 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
9614 }
9615
9616 btarget = ctx->base.pc_next + 4 + offset;
9617
9618 switch (op) {
9619 case OPC_BC1F:
9620 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9621 tcg_gen_not_i32(t0, t0);
9622 tcg_gen_andi_i32(t0, t0, 1);
9623 tcg_gen_extu_i32_tl(bcond, t0);
9624 goto not_likely;
9625 case OPC_BC1FL:
9626 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9627 tcg_gen_not_i32(t0, t0);
9628 tcg_gen_andi_i32(t0, t0, 1);
9629 tcg_gen_extu_i32_tl(bcond, t0);
9630 goto likely;
9631 case OPC_BC1T:
9632 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9633 tcg_gen_andi_i32(t0, t0, 1);
9634 tcg_gen_extu_i32_tl(bcond, t0);
9635 goto not_likely;
9636 case OPC_BC1TL:
9637 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9638 tcg_gen_andi_i32(t0, t0, 1);
9639 tcg_gen_extu_i32_tl(bcond, t0);
9640 likely:
9641 ctx->hflags |= MIPS_HFLAG_BL;
9642 break;
9643 case OPC_BC1FANY2:
9644 {
9645 TCGv_i32 t1 = tcg_temp_new_i32();
9646 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9647 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
9648 tcg_gen_nand_i32(t0, t0, t1);
9649 tcg_temp_free_i32(t1);
9650 tcg_gen_andi_i32(t0, t0, 1);
9651 tcg_gen_extu_i32_tl(bcond, t0);
9652 }
9653 goto not_likely;
9654 case OPC_BC1TANY2:
9655 {
9656 TCGv_i32 t1 = tcg_temp_new_i32();
9657 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9658 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
9659 tcg_gen_or_i32(t0, t0, t1);
9660 tcg_temp_free_i32(t1);
9661 tcg_gen_andi_i32(t0, t0, 1);
9662 tcg_gen_extu_i32_tl(bcond, t0);
9663 }
9664 goto not_likely;
9665 case OPC_BC1FANY4:
9666 {
9667 TCGv_i32 t1 = tcg_temp_new_i32();
9668 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9669 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
9670 tcg_gen_and_i32(t0, t0, t1);
9671 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2));
9672 tcg_gen_and_i32(t0, t0, t1);
9673 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3));
9674 tcg_gen_nand_i32(t0, t0, t1);
9675 tcg_temp_free_i32(t1);
9676 tcg_gen_andi_i32(t0, t0, 1);
9677 tcg_gen_extu_i32_tl(bcond, t0);
9678 }
9679 goto not_likely;
9680 case OPC_BC1TANY4:
9681 {
9682 TCGv_i32 t1 = tcg_temp_new_i32();
9683 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9684 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
9685 tcg_gen_or_i32(t0, t0, t1);
9686 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2));
9687 tcg_gen_or_i32(t0, t0, t1);
9688 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3));
9689 tcg_gen_or_i32(t0, t0, t1);
9690 tcg_temp_free_i32(t1);
9691 tcg_gen_andi_i32(t0, t0, 1);
9692 tcg_gen_extu_i32_tl(bcond, t0);
9693 }
9694 not_likely:
9695 ctx->hflags |= MIPS_HFLAG_BC;
9696 break;
9697 default:
9698 MIPS_INVAL("cp1 cond branch");
9699 gen_reserved_instruction(ctx);
9700 goto out;
9701 }
9702 ctx->btarget = btarget;
9703 ctx->hflags |= MIPS_HFLAG_BDS32;
9704 out:
9705 tcg_temp_free_i32(t0);
9706 }
9707
9708 /* R6 CP1 Branches */
9709 static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
9710 int32_t ft, int32_t offset,
9711 int delayslot_size)
9712 {
9713 target_ulong btarget;
9714 TCGv_i64 t0 = tcg_temp_new_i64();
9715
9716 if (ctx->hflags & MIPS_HFLAG_BMASK) {
9717 #ifdef MIPS_DEBUG_DISAS
9718 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
9719 "\n", ctx->base.pc_next);
9720 #endif
9721 gen_reserved_instruction(ctx);
9722 goto out;
9723 }
9724
9725 gen_load_fpr64(ctx, t0, ft);
9726 tcg_gen_andi_i64(t0, t0, 1);
9727
9728 btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
9729
9730 switch (op) {
9731 case OPC_BC1EQZ:
9732 tcg_gen_xori_i64(t0, t0, 1);
9733 ctx->hflags |= MIPS_HFLAG_BC;
9734 break;
9735 case OPC_BC1NEZ:
9736 /* t0 already set */
9737 ctx->hflags |= MIPS_HFLAG_BC;
9738 break;
9739 default:
9740 MIPS_INVAL("cp1 cond branch");
9741 gen_reserved_instruction(ctx);
9742 goto out;
9743 }
9744
9745 tcg_gen_trunc_i64_tl(bcond, t0);
9746
9747 ctx->btarget = btarget;
9748
9749 switch (delayslot_size) {
9750 case 2:
9751 ctx->hflags |= MIPS_HFLAG_BDS16;
9752 break;
9753 case 4:
9754 ctx->hflags |= MIPS_HFLAG_BDS32;
9755 break;
9756 }
9757
9758 out:
9759 tcg_temp_free_i64(t0);
9760 }
9761
9762 /* Coprocessor 1 (FPU) */
9763
9764 #define FOP(func, fmt) (((fmt) << 21) | (func))
9765
9766 enum fopcode {
9767 OPC_ADD_S = FOP(0, FMT_S),
9768 OPC_SUB_S = FOP(1, FMT_S),
9769 OPC_MUL_S = FOP(2, FMT_S),
9770 OPC_DIV_S = FOP(3, FMT_S),
9771 OPC_SQRT_S = FOP(4, FMT_S),
9772 OPC_ABS_S = FOP(5, FMT_S),
9773 OPC_MOV_S = FOP(6, FMT_S),
9774 OPC_NEG_S = FOP(7, FMT_S),
9775 OPC_ROUND_L_S = FOP(8, FMT_S),
9776 OPC_TRUNC_L_S = FOP(9, FMT_S),
9777 OPC_CEIL_L_S = FOP(10, FMT_S),
9778 OPC_FLOOR_L_S = FOP(11, FMT_S),
9779 OPC_ROUND_W_S = FOP(12, FMT_S),
9780 OPC_TRUNC_W_S = FOP(13, FMT_S),
9781 OPC_CEIL_W_S = FOP(14, FMT_S),
9782 OPC_FLOOR_W_S = FOP(15, FMT_S),
9783 OPC_SEL_S = FOP(16, FMT_S),
9784 OPC_MOVCF_S = FOP(17, FMT_S),
9785 OPC_MOVZ_S = FOP(18, FMT_S),
9786 OPC_MOVN_S = FOP(19, FMT_S),
9787 OPC_SELEQZ_S = FOP(20, FMT_S),
9788 OPC_RECIP_S = FOP(21, FMT_S),
9789 OPC_RSQRT_S = FOP(22, FMT_S),
9790 OPC_SELNEZ_S = FOP(23, FMT_S),
9791 OPC_MADDF_S = FOP(24, FMT_S),
9792 OPC_MSUBF_S = FOP(25, FMT_S),
9793 OPC_RINT_S = FOP(26, FMT_S),
9794 OPC_CLASS_S = FOP(27, FMT_S),
9795 OPC_MIN_S = FOP(28, FMT_S),
9796 OPC_RECIP2_S = FOP(28, FMT_S),
9797 OPC_MINA_S = FOP(29, FMT_S),
9798 OPC_RECIP1_S = FOP(29, FMT_S),
9799 OPC_MAX_S = FOP(30, FMT_S),
9800 OPC_RSQRT1_S = FOP(30, FMT_S),
9801 OPC_MAXA_S = FOP(31, FMT_S),
9802 OPC_RSQRT2_S = FOP(31, FMT_S),
9803 OPC_CVT_D_S = FOP(33, FMT_S),
9804 OPC_CVT_W_S = FOP(36, FMT_S),
9805 OPC_CVT_L_S = FOP(37, FMT_S),
9806 OPC_CVT_PS_S = FOP(38, FMT_S),
9807 OPC_CMP_F_S = FOP(48, FMT_S),
9808 OPC_CMP_UN_S = FOP(49, FMT_S),
9809 OPC_CMP_EQ_S = FOP(50, FMT_S),
9810 OPC_CMP_UEQ_S = FOP(51, FMT_S),
9811 OPC_CMP_OLT_S = FOP(52, FMT_S),
9812 OPC_CMP_ULT_S = FOP(53, FMT_S),
9813 OPC_CMP_OLE_S = FOP(54, FMT_S),
9814 OPC_CMP_ULE_S = FOP(55, FMT_S),
9815 OPC_CMP_SF_S = FOP(56, FMT_S),
9816 OPC_CMP_NGLE_S = FOP(57, FMT_S),
9817 OPC_CMP_SEQ_S = FOP(58, FMT_S),
9818 OPC_CMP_NGL_S = FOP(59, FMT_S),
9819 OPC_CMP_LT_S = FOP(60, FMT_S),
9820 OPC_CMP_NGE_S = FOP(61, FMT_S),
9821 OPC_CMP_LE_S = FOP(62, FMT_S),
9822 OPC_CMP_NGT_S = FOP(63, FMT_S),
9823
9824 OPC_ADD_D = FOP(0, FMT_D),
9825 OPC_SUB_D = FOP(1, FMT_D),
9826 OPC_MUL_D = FOP(2, FMT_D),
9827 OPC_DIV_D = FOP(3, FMT_D),
9828 OPC_SQRT_D = FOP(4, FMT_D),
9829 OPC_ABS_D = FOP(5, FMT_D),
9830 OPC_MOV_D = FOP(6, FMT_D),
9831 OPC_NEG_D = FOP(7, FMT_D),
9832 OPC_ROUND_L_D = FOP(8, FMT_D),
9833 OPC_TRUNC_L_D = FOP(9, FMT_D),
9834 OPC_CEIL_L_D = FOP(10, FMT_D),
9835 OPC_FLOOR_L_D = FOP(11, FMT_D),
9836 OPC_ROUND_W_D = FOP(12, FMT_D),
9837 OPC_TRUNC_W_D = FOP(13, FMT_D),
9838 OPC_CEIL_W_D = FOP(14, FMT_D),
9839 OPC_FLOOR_W_D = FOP(15, FMT_D),
9840 OPC_SEL_D = FOP(16, FMT_D),
9841 OPC_MOVCF_D = FOP(17, FMT_D),
9842 OPC_MOVZ_D = FOP(18, FMT_D),
9843 OPC_MOVN_D = FOP(19, FMT_D),
9844 OPC_SELEQZ_D = FOP(20, FMT_D),
9845 OPC_RECIP_D = FOP(21, FMT_D),
9846 OPC_RSQRT_D = FOP(22, FMT_D),
9847 OPC_SELNEZ_D = FOP(23, FMT_D),
9848 OPC_MADDF_D = FOP(24, FMT_D),
9849 OPC_MSUBF_D = FOP(25, FMT_D),
9850 OPC_RINT_D = FOP(26, FMT_D),
9851 OPC_CLASS_D = FOP(27, FMT_D),
9852 OPC_MIN_D = FOP(28, FMT_D),
9853 OPC_RECIP2_D = FOP(28, FMT_D),
9854 OPC_MINA_D = FOP(29, FMT_D),
9855 OPC_RECIP1_D = FOP(29, FMT_D),
9856 OPC_MAX_D = FOP(30, FMT_D),
9857 OPC_RSQRT1_D = FOP(30, FMT_D),
9858 OPC_MAXA_D = FOP(31, FMT_D),
9859 OPC_RSQRT2_D = FOP(31, FMT_D),
9860 OPC_CVT_S_D = FOP(32, FMT_D),
9861 OPC_CVT_W_D = FOP(36, FMT_D),
9862 OPC_CVT_L_D = FOP(37, FMT_D),
9863 OPC_CMP_F_D = FOP(48, FMT_D),
9864 OPC_CMP_UN_D = FOP(49, FMT_D),
9865 OPC_CMP_EQ_D = FOP(50, FMT_D),
9866 OPC_CMP_UEQ_D = FOP(51, FMT_D),
9867 OPC_CMP_OLT_D = FOP(52, FMT_D),
9868 OPC_CMP_ULT_D = FOP(53, FMT_D),
9869 OPC_CMP_OLE_D = FOP(54, FMT_D),
9870 OPC_CMP_ULE_D = FOP(55, FMT_D),
9871 OPC_CMP_SF_D = FOP(56, FMT_D),
9872 OPC_CMP_NGLE_D = FOP(57, FMT_D),
9873 OPC_CMP_SEQ_D = FOP(58, FMT_D),
9874 OPC_CMP_NGL_D = FOP(59, FMT_D),
9875 OPC_CMP_LT_D = FOP(60, FMT_D),
9876 OPC_CMP_NGE_D = FOP(61, FMT_D),
9877 OPC_CMP_LE_D = FOP(62, FMT_D),
9878 OPC_CMP_NGT_D = FOP(63, FMT_D),
9879
9880 OPC_CVT_S_W = FOP(32, FMT_W),
9881 OPC_CVT_D_W = FOP(33, FMT_W),
9882 OPC_CVT_S_L = FOP(32, FMT_L),
9883 OPC_CVT_D_L = FOP(33, FMT_L),
9884 OPC_CVT_PS_PW = FOP(38, FMT_W),
9885
9886 OPC_ADD_PS = FOP(0, FMT_PS),
9887 OPC_SUB_PS = FOP(1, FMT_PS),
9888 OPC_MUL_PS = FOP(2, FMT_PS),
9889 OPC_DIV_PS = FOP(3, FMT_PS),
9890 OPC_ABS_PS = FOP(5, FMT_PS),
9891 OPC_MOV_PS = FOP(6, FMT_PS),
9892 OPC_NEG_PS = FOP(7, FMT_PS),
9893 OPC_MOVCF_PS = FOP(17, FMT_PS),
9894 OPC_MOVZ_PS = FOP(18, FMT_PS),
9895 OPC_MOVN_PS = FOP(19, FMT_PS),
9896 OPC_ADDR_PS = FOP(24, FMT_PS),
9897 OPC_MULR_PS = FOP(26, FMT_PS),
9898 OPC_RECIP2_PS = FOP(28, FMT_PS),
9899 OPC_RECIP1_PS = FOP(29, FMT_PS),
9900 OPC_RSQRT1_PS = FOP(30, FMT_PS),
9901 OPC_RSQRT2_PS = FOP(31, FMT_PS),
9902
9903 OPC_CVT_S_PU = FOP(32, FMT_PS),
9904 OPC_CVT_PW_PS = FOP(36, FMT_PS),
9905 OPC_CVT_S_PL = FOP(40, FMT_PS),
9906 OPC_PLL_PS = FOP(44, FMT_PS),
9907 OPC_PLU_PS = FOP(45, FMT_PS),
9908 OPC_PUL_PS = FOP(46, FMT_PS),
9909 OPC_PUU_PS = FOP(47, FMT_PS),
9910 OPC_CMP_F_PS = FOP(48, FMT_PS),
9911 OPC_CMP_UN_PS = FOP(49, FMT_PS),
9912 OPC_CMP_EQ_PS = FOP(50, FMT_PS),
9913 OPC_CMP_UEQ_PS = FOP(51, FMT_PS),
9914 OPC_CMP_OLT_PS = FOP(52, FMT_PS),
9915 OPC_CMP_ULT_PS = FOP(53, FMT_PS),
9916 OPC_CMP_OLE_PS = FOP(54, FMT_PS),
9917 OPC_CMP_ULE_PS = FOP(55, FMT_PS),
9918 OPC_CMP_SF_PS = FOP(56, FMT_PS),
9919 OPC_CMP_NGLE_PS = FOP(57, FMT_PS),
9920 OPC_CMP_SEQ_PS = FOP(58, FMT_PS),
9921 OPC_CMP_NGL_PS = FOP(59, FMT_PS),
9922 OPC_CMP_LT_PS = FOP(60, FMT_PS),
9923 OPC_CMP_NGE_PS = FOP(61, FMT_PS),
9924 OPC_CMP_LE_PS = FOP(62, FMT_PS),
9925 OPC_CMP_NGT_PS = FOP(63, FMT_PS),
9926 };
9927
9928 enum r6_f_cmp_op {
9929 R6_OPC_CMP_AF_S = FOP(0, FMT_W),
9930 R6_OPC_CMP_UN_S = FOP(1, FMT_W),
9931 R6_OPC_CMP_EQ_S = FOP(2, FMT_W),
9932 R6_OPC_CMP_UEQ_S = FOP(3, FMT_W),
9933 R6_OPC_CMP_LT_S = FOP(4, FMT_W),
9934 R6_OPC_CMP_ULT_S = FOP(5, FMT_W),
9935 R6_OPC_CMP_LE_S = FOP(6, FMT_W),
9936 R6_OPC_CMP_ULE_S = FOP(7, FMT_W),
9937 R6_OPC_CMP_SAF_S = FOP(8, FMT_W),
9938 R6_OPC_CMP_SUN_S = FOP(9, FMT_W),
9939 R6_OPC_CMP_SEQ_S = FOP(10, FMT_W),
9940 R6_OPC_CMP_SEUQ_S = FOP(11, FMT_W),
9941 R6_OPC_CMP_SLT_S = FOP(12, FMT_W),
9942 R6_OPC_CMP_SULT_S = FOP(13, FMT_W),
9943 R6_OPC_CMP_SLE_S = FOP(14, FMT_W),
9944 R6_OPC_CMP_SULE_S = FOP(15, FMT_W),
9945 R6_OPC_CMP_OR_S = FOP(17, FMT_W),
9946 R6_OPC_CMP_UNE_S = FOP(18, FMT_W),
9947 R6_OPC_CMP_NE_S = FOP(19, FMT_W),
9948 R6_OPC_CMP_SOR_S = FOP(25, FMT_W),
9949 R6_OPC_CMP_SUNE_S = FOP(26, FMT_W),
9950 R6_OPC_CMP_SNE_S = FOP(27, FMT_W),
9951
9952 R6_OPC_CMP_AF_D = FOP(0, FMT_L),
9953 R6_OPC_CMP_UN_D = FOP(1, FMT_L),
9954 R6_OPC_CMP_EQ_D = FOP(2, FMT_L),
9955 R6_OPC_CMP_UEQ_D = FOP(3, FMT_L),
9956 R6_OPC_CMP_LT_D = FOP(4, FMT_L),
9957 R6_OPC_CMP_ULT_D = FOP(5, FMT_L),
9958 R6_OPC_CMP_LE_D = FOP(6, FMT_L),
9959 R6_OPC_CMP_ULE_D = FOP(7, FMT_L),
9960 R6_OPC_CMP_SAF_D = FOP(8, FMT_L),
9961 R6_OPC_CMP_SUN_D = FOP(9, FMT_L),
9962 R6_OPC_CMP_SEQ_D = FOP(10, FMT_L),
9963 R6_OPC_CMP_SEUQ_D = FOP(11, FMT_L),
9964 R6_OPC_CMP_SLT_D = FOP(12, FMT_L),
9965 R6_OPC_CMP_SULT_D = FOP(13, FMT_L),
9966 R6_OPC_CMP_SLE_D = FOP(14, FMT_L),
9967 R6_OPC_CMP_SULE_D = FOP(15, FMT_L),
9968 R6_OPC_CMP_OR_D = FOP(17, FMT_L),
9969 R6_OPC_CMP_UNE_D = FOP(18, FMT_L),
9970 R6_OPC_CMP_NE_D = FOP(19, FMT_L),
9971 R6_OPC_CMP_SOR_D = FOP(25, FMT_L),
9972 R6_OPC_CMP_SUNE_D = FOP(26, FMT_L),
9973 R6_OPC_CMP_SNE_D = FOP(27, FMT_L),
9974 };
9975
9976 static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs)
9977 {
9978 TCGv t0 = tcg_temp_new();
9979
9980 switch (opc) {
9981 case OPC_MFC1:
9982 {
9983 TCGv_i32 fp0 = tcg_temp_new_i32();
9984
9985 gen_load_fpr32(ctx, fp0, fs);
9986 tcg_gen_ext_i32_tl(t0, fp0);
9987 tcg_temp_free_i32(fp0);
9988 }
9989 gen_store_gpr(t0, rt);
9990 break;
9991 case OPC_MTC1:
9992 gen_load_gpr(t0, rt);
9993 {
9994 TCGv_i32 fp0 = tcg_temp_new_i32();
9995
9996 tcg_gen_trunc_tl_i32(fp0, t0);
9997 gen_store_fpr32(ctx, fp0, fs);
9998 tcg_temp_free_i32(fp0);
9999 }
10000 break;
10001 case OPC_CFC1:
10002 gen_helper_1e0i(cfc1, t0, fs);
10003 gen_store_gpr(t0, rt);
10004 break;
10005 case OPC_CTC1:
10006 gen_load_gpr(t0, rt);
10007 save_cpu_state(ctx, 0);
10008 {
10009 TCGv_i32 fs_tmp = tcg_const_i32(fs);
10010
10011 gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
10012 tcg_temp_free_i32(fs_tmp);
10013 }
10014 /* Stop translation as we may have changed hflags */
10015 ctx->base.is_jmp = DISAS_STOP;
10016 break;
10017 #if defined(TARGET_MIPS64)
10018 case OPC_DMFC1:
10019 gen_load_fpr64(ctx, t0, fs);
10020 gen_store_gpr(t0, rt);
10021 break;
10022 case OPC_DMTC1:
10023 gen_load_gpr(t0, rt);
10024 gen_store_fpr64(ctx, t0, fs);
10025 break;
10026 #endif
10027 case OPC_MFHC1:
10028 {
10029 TCGv_i32 fp0 = tcg_temp_new_i32();
10030
10031 gen_load_fpr32h(ctx, fp0, fs);
10032 tcg_gen_ext_i32_tl(t0, fp0);
10033 tcg_temp_free_i32(fp0);
10034 }
10035 gen_store_gpr(t0, rt);
10036 break;
10037 case OPC_MTHC1:
10038 gen_load_gpr(t0, rt);
10039 {
10040 TCGv_i32 fp0 = tcg_temp_new_i32();
10041
10042 tcg_gen_trunc_tl_i32(fp0, t0);
10043 gen_store_fpr32h(ctx, fp0, fs);
10044 tcg_temp_free_i32(fp0);
10045 }
10046 break;
10047 default:
10048 MIPS_INVAL("cp1 move");
10049 gen_reserved_instruction(ctx);
10050 goto out;
10051 }
10052
10053 out:
10054 tcg_temp_free(t0);
10055 }
10056
10057 static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf)
10058 {
10059 TCGLabel *l1;
10060 TCGCond cond;
10061 TCGv_i32 t0;
10062
10063 if (rd == 0) {
10064 /* Treat as NOP. */
10065 return;
10066 }
10067
10068 if (tf) {
10069 cond = TCG_COND_EQ;
10070 } else {
10071 cond = TCG_COND_NE;
10072 }
10073
10074 l1 = gen_new_label();
10075 t0 = tcg_temp_new_i32();
10076 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
10077 tcg_gen_brcondi_i32(cond, t0, 0, l1);
10078 tcg_temp_free_i32(t0);
10079 gen_load_gpr(cpu_gpr[rd], rs);
10080 gen_set_label(l1);
10081 }
10082
10083 static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc,
10084 int tf)
10085 {
10086 int cond;
10087 TCGv_i32 t0 = tcg_temp_new_i32();
10088 TCGLabel *l1 = gen_new_label();
10089
10090 if (tf) {
10091 cond = TCG_COND_EQ;
10092 } else {
10093 cond = TCG_COND_NE;
10094 }
10095
10096 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
10097 tcg_gen_brcondi_i32(cond, t0, 0, l1);
10098 gen_load_fpr32(ctx, t0, fs);
10099 gen_store_fpr32(ctx, t0, fd);
10100 gen_set_label(l1);
10101 tcg_temp_free_i32(t0);
10102 }
10103
10104 static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc,
10105 int tf)
10106 {
10107 int cond;
10108 TCGv_i32 t0 = tcg_temp_new_i32();
10109 TCGv_i64 fp0;
10110 TCGLabel *l1 = gen_new_label();
10111
10112 if (tf) {
10113 cond = TCG_COND_EQ;
10114 } else {
10115 cond = TCG_COND_NE;
10116 }
10117
10118 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
10119 tcg_gen_brcondi_i32(cond, t0, 0, l1);
10120 tcg_temp_free_i32(t0);
10121 fp0 = tcg_temp_new_i64();
10122 gen_load_fpr64(ctx, fp0, fs);
10123 gen_store_fpr64(ctx, fp0, fd);
10124 tcg_temp_free_i64(fp0);
10125 gen_set_label(l1);
10126 }
10127
10128 static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
10129 int cc, int tf)
10130 {
10131 int cond;
10132 TCGv_i32 t0 = tcg_temp_new_i32();
10133 TCGLabel *l1 = gen_new_label();
10134 TCGLabel *l2 = gen_new_label();
10135
10136 if (tf) {
10137 cond = TCG_COND_EQ;
10138 } else {
10139 cond = TCG_COND_NE;
10140 }
10141
10142 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
10143 tcg_gen_brcondi_i32(cond, t0, 0, l1);
10144 gen_load_fpr32(ctx, t0, fs);
10145 gen_store_fpr32(ctx, t0, fd);
10146 gen_set_label(l1);
10147
10148 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc + 1));
10149 tcg_gen_brcondi_i32(cond, t0, 0, l2);
10150 gen_load_fpr32h(ctx, t0, fs);
10151 gen_store_fpr32h(ctx, t0, fd);
10152 tcg_temp_free_i32(t0);
10153 gen_set_label(l2);
10154 }
10155
10156 static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
10157 int fs)
10158 {
10159 TCGv_i32 t1 = tcg_const_i32(0);
10160 TCGv_i32 fp0 = tcg_temp_new_i32();
10161 TCGv_i32 fp1 = tcg_temp_new_i32();
10162 TCGv_i32 fp2 = tcg_temp_new_i32();
10163 gen_load_fpr32(ctx, fp0, fd);
10164 gen_load_fpr32(ctx, fp1, ft);
10165 gen_load_fpr32(ctx, fp2, fs);
10166
10167 switch (op1) {
10168 case OPC_SEL_S:
10169 tcg_gen_andi_i32(fp0, fp0, 1);
10170 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp0, t1, fp1, fp2);
10171 break;
10172 case OPC_SELEQZ_S:
10173 tcg_gen_andi_i32(fp1, fp1, 1);
10174 tcg_gen_movcond_i32(TCG_COND_EQ, fp0, fp1, t1, fp2, t1);
10175 break;
10176 case OPC_SELNEZ_S:
10177 tcg_gen_andi_i32(fp1, fp1, 1);
10178 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp1, t1, fp2, t1);
10179 break;
10180 default:
10181 MIPS_INVAL("gen_sel_s");
10182 gen_reserved_instruction(ctx);
10183 break;
10184 }
10185
10186 gen_store_fpr32(ctx, fp0, fd);
10187 tcg_temp_free_i32(fp2);
10188 tcg_temp_free_i32(fp1);
10189 tcg_temp_free_i32(fp0);
10190 tcg_temp_free_i32(t1);
10191 }
10192
10193 static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft,
10194 int fs)
10195 {
10196 TCGv_i64 t1 = tcg_const_i64(0);
10197 TCGv_i64 fp0 = tcg_temp_new_i64();
10198 TCGv_i64 fp1 = tcg_temp_new_i64();
10199 TCGv_i64 fp2 = tcg_temp_new_i64();
10200 gen_load_fpr64(ctx, fp0, fd);
10201 gen_load_fpr64(ctx, fp1, ft);
10202 gen_load_fpr64(ctx, fp2, fs);
10203
10204 switch (op1) {
10205 case OPC_SEL_D:
10206 tcg_gen_andi_i64(fp0, fp0, 1);
10207 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp0, t1, fp1, fp2);
10208 break;
10209 case OPC_SELEQZ_D:
10210 tcg_gen_andi_i64(fp1, fp1, 1);
10211 tcg_gen_movcond_i64(TCG_COND_EQ, fp0, fp1, t1, fp2, t1);
10212 break;
10213 case OPC_SELNEZ_D:
10214 tcg_gen_andi_i64(fp1, fp1, 1);
10215 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp1, t1, fp2, t1);
10216 break;
10217 default:
10218 MIPS_INVAL("gen_sel_d");
10219 gen_reserved_instruction(ctx);
10220 break;
10221 }
10222
10223 gen_store_fpr64(ctx, fp0, fd);
10224 tcg_temp_free_i64(fp2);
10225 tcg_temp_free_i64(fp1);
10226 tcg_temp_free_i64(fp0);
10227 tcg_temp_free_i64(t1);
10228 }
10229
10230 static void gen_farith(DisasContext *ctx, enum fopcode op1,
10231 int ft, int fs, int fd, int cc)
10232 {
10233 uint32_t func = ctx->opcode & 0x3f;
10234 switch (op1) {
10235 case OPC_ADD_S:
10236 {
10237 TCGv_i32 fp0 = tcg_temp_new_i32();
10238 TCGv_i32 fp1 = tcg_temp_new_i32();
10239
10240 gen_load_fpr32(ctx, fp0, fs);
10241 gen_load_fpr32(ctx, fp1, ft);
10242 gen_helper_float_add_s(fp0, cpu_env, fp0, fp1);
10243 tcg_temp_free_i32(fp1);
10244 gen_store_fpr32(ctx, fp0, fd);
10245 tcg_temp_free_i32(fp0);
10246 }
10247 break;
10248 case OPC_SUB_S:
10249 {
10250 TCGv_i32 fp0 = tcg_temp_new_i32();
10251 TCGv_i32 fp1 = tcg_temp_new_i32();
10252
10253 gen_load_fpr32(ctx, fp0, fs);
10254 gen_load_fpr32(ctx, fp1, ft);
10255 gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1);
10256 tcg_temp_free_i32(fp1);
10257 gen_store_fpr32(ctx, fp0, fd);
10258 tcg_temp_free_i32(fp0);
10259 }
10260 break;
10261 case OPC_MUL_S:
10262 {
10263 TCGv_i32 fp0 = tcg_temp_new_i32();
10264 TCGv_i32 fp1 = tcg_temp_new_i32();
10265
10266 gen_load_fpr32(ctx, fp0, fs);
10267 gen_load_fpr32(ctx, fp1, ft);
10268 gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1);
10269 tcg_temp_free_i32(fp1);
10270 gen_store_fpr32(ctx, fp0, fd);
10271 tcg_temp_free_i32(fp0);
10272 }
10273 break;
10274 case OPC_DIV_S:
10275 {
10276 TCGv_i32 fp0 = tcg_temp_new_i32();
10277 TCGv_i32 fp1 = tcg_temp_new_i32();
10278
10279 gen_load_fpr32(ctx, fp0, fs);
10280 gen_load_fpr32(ctx, fp1, ft);
10281 gen_helper_float_div_s(fp0, cpu_env, fp0, fp1);
10282 tcg_temp_free_i32(fp1);
10283 gen_store_fpr32(ctx, fp0, fd);
10284 tcg_temp_free_i32(fp0);
10285 }
10286 break;
10287 case OPC_SQRT_S:
10288 {
10289 TCGv_i32 fp0 = tcg_temp_new_i32();
10290
10291 gen_load_fpr32(ctx, fp0, fs);
10292 gen_helper_float_sqrt_s(fp0, cpu_env, fp0);
10293 gen_store_fpr32(ctx, fp0, fd);
10294 tcg_temp_free_i32(fp0);
10295 }
10296 break;
10297 case OPC_ABS_S:
10298 {
10299 TCGv_i32 fp0 = tcg_temp_new_i32();
10300
10301 gen_load_fpr32(ctx, fp0, fs);
10302 if (ctx->abs2008) {
10303 tcg_gen_andi_i32(fp0, fp0, 0x7fffffffUL);
10304 } else {
10305 gen_helper_float_abs_s(fp0, fp0);
10306 }
10307 gen_store_fpr32(ctx, fp0, fd);
10308 tcg_temp_free_i32(fp0);
10309 }
10310 break;
10311 case OPC_MOV_S:
10312 {
10313 TCGv_i32 fp0 = tcg_temp_new_i32();
10314
10315 gen_load_fpr32(ctx, fp0, fs);
10316 gen_store_fpr32(ctx, fp0, fd);
10317 tcg_temp_free_i32(fp0);
10318 }
10319 break;
10320 case OPC_NEG_S:
10321 {
10322 TCGv_i32 fp0 = tcg_temp_new_i32();
10323
10324 gen_load_fpr32(ctx, fp0, fs);
10325 if (ctx->abs2008) {
10326 tcg_gen_xori_i32(fp0, fp0, 1UL << 31);
10327 } else {
10328 gen_helper_float_chs_s(fp0, fp0);
10329 }
10330 gen_store_fpr32(ctx, fp0, fd);
10331 tcg_temp_free_i32(fp0);
10332 }
10333 break;
10334 case OPC_ROUND_L_S:
10335 check_cp1_64bitmode(ctx);
10336 {
10337 TCGv_i32 fp32 = tcg_temp_new_i32();
10338 TCGv_i64 fp64 = tcg_temp_new_i64();
10339
10340 gen_load_fpr32(ctx, fp32, fs);
10341 if (ctx->nan2008) {
10342 gen_helper_float_round_2008_l_s(fp64, cpu_env, fp32);
10343 } else {
10344 gen_helper_float_round_l_s(fp64, cpu_env, fp32);
10345 }
10346 tcg_temp_free_i32(fp32);
10347 gen_store_fpr64(ctx, fp64, fd);
10348 tcg_temp_free_i64(fp64);
10349 }
10350 break;
10351 case OPC_TRUNC_L_S:
10352 check_cp1_64bitmode(ctx);
10353 {
10354 TCGv_i32 fp32 = tcg_temp_new_i32();
10355 TCGv_i64 fp64 = tcg_temp_new_i64();
10356
10357 gen_load_fpr32(ctx, fp32, fs);
10358 if (ctx->nan2008) {
10359 gen_helper_float_trunc_2008_l_s(fp64, cpu_env, fp32);
10360 } else {
10361 gen_helper_float_trunc_l_s(fp64, cpu_env, fp32);
10362 }
10363 tcg_temp_free_i32(fp32);
10364 gen_store_fpr64(ctx, fp64, fd);
10365 tcg_temp_free_i64(fp64);
10366 }
10367 break;
10368 case OPC_CEIL_L_S:
10369 check_cp1_64bitmode(ctx);
10370 {
10371 TCGv_i32 fp32 = tcg_temp_new_i32();
10372 TCGv_i64 fp64 = tcg_temp_new_i64();
10373
10374 gen_load_fpr32(ctx, fp32, fs);
10375 if (ctx->nan2008) {
10376 gen_helper_float_ceil_2008_l_s(fp64, cpu_env, fp32);
10377 } else {
10378 gen_helper_float_ceil_l_s(fp64, cpu_env, fp32);
10379 }
10380 tcg_temp_free_i32(fp32);
10381 gen_store_fpr64(ctx, fp64, fd);
10382 tcg_temp_free_i64(fp64);
10383 }
10384 break;
10385 case OPC_FLOOR_L_S:
10386 check_cp1_64bitmode(ctx);
10387 {
10388 TCGv_i32 fp32 = tcg_temp_new_i32();
10389 TCGv_i64 fp64 = tcg_temp_new_i64();
10390
10391 gen_load_fpr32(ctx, fp32, fs);
10392 if (ctx->nan2008) {
10393 gen_helper_float_floor_2008_l_s(fp64, cpu_env, fp32);
10394 } else {
10395 gen_helper_float_floor_l_s(fp64, cpu_env, fp32);
10396 }
10397 tcg_temp_free_i32(fp32);
10398 gen_store_fpr64(ctx, fp64, fd);
10399 tcg_temp_free_i64(fp64);
10400 }
10401 break;
10402 case OPC_ROUND_W_S:
10403 {
10404 TCGv_i32 fp0 = tcg_temp_new_i32();
10405
10406 gen_load_fpr32(ctx, fp0, fs);
10407 if (ctx->nan2008) {
10408 gen_helper_float_round_2008_w_s(fp0, cpu_env, fp0);
10409 } else {
10410 gen_helper_float_round_w_s(fp0, cpu_env, fp0);
10411 }
10412 gen_store_fpr32(ctx, fp0, fd);
10413 tcg_temp_free_i32(fp0);
10414 }
10415 break;
10416 case OPC_TRUNC_W_S:
10417 {
10418 TCGv_i32 fp0 = tcg_temp_new_i32();
10419
10420 gen_load_fpr32(ctx, fp0, fs);
10421 if (ctx->nan2008) {
10422 gen_helper_float_trunc_2008_w_s(fp0, cpu_env, fp0);
10423 } else {
10424 gen_helper_float_trunc_w_s(fp0, cpu_env, fp0);
10425 }
10426 gen_store_fpr32(ctx, fp0, fd);
10427 tcg_temp_free_i32(fp0);
10428 }
10429 break;
10430 case OPC_CEIL_W_S:
10431 {
10432 TCGv_i32 fp0 = tcg_temp_new_i32();
10433
10434 gen_load_fpr32(ctx, fp0, fs);
10435 if (ctx->nan2008) {
10436 gen_helper_float_ceil_2008_w_s(fp0, cpu_env, fp0);
10437 } else {
10438 gen_helper_float_ceil_w_s(fp0, cpu_env, fp0);
10439 }
10440 gen_store_fpr32(ctx, fp0, fd);
10441 tcg_temp_free_i32(fp0);
10442 }
10443 break;
10444 case OPC_FLOOR_W_S:
10445 {
10446 TCGv_i32 fp0 = tcg_temp_new_i32();
10447
10448 gen_load_fpr32(ctx, fp0, fs);
10449 if (ctx->nan2008) {
10450 gen_helper_float_floor_2008_w_s(fp0, cpu_env, fp0);
10451 } else {
10452 gen_helper_float_floor_w_s(fp0, cpu_env, fp0);
10453 }
10454 gen_store_fpr32(ctx, fp0, fd);
10455 tcg_temp_free_i32(fp0);
10456 }
10457 break;
10458 case OPC_SEL_S:
10459 check_insn(ctx, ISA_MIPS_R6);
10460 gen_sel_s(ctx, op1, fd, ft, fs);
10461 break;
10462 case OPC_SELEQZ_S:
10463 check_insn(ctx, ISA_MIPS_R6);
10464 gen_sel_s(ctx, op1, fd, ft, fs);
10465 break;
10466 case OPC_SELNEZ_S:
10467 check_insn(ctx, ISA_MIPS_R6);
10468 gen_sel_s(ctx, op1, fd, ft, fs);
10469 break;
10470 case OPC_MOVCF_S:
10471 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10472 gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
10473 break;
10474 case OPC_MOVZ_S:
10475 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10476 {
10477 TCGLabel *l1 = gen_new_label();
10478 TCGv_i32 fp0;
10479
10480 if (ft != 0) {
10481 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
10482 }
10483 fp0 = tcg_temp_new_i32();
10484 gen_load_fpr32(ctx, fp0, fs);
10485 gen_store_fpr32(ctx, fp0, fd);
10486 tcg_temp_free_i32(fp0);
10487 gen_set_label(l1);
10488 }
10489 break;
10490 case OPC_MOVN_S:
10491 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10492 {
10493 TCGLabel *l1 = gen_new_label();
10494 TCGv_i32 fp0;
10495
10496 if (ft != 0) {
10497 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
10498 fp0 = tcg_temp_new_i32();
10499 gen_load_fpr32(ctx, fp0, fs);
10500 gen_store_fpr32(ctx, fp0, fd);
10501 tcg_temp_free_i32(fp0);
10502 gen_set_label(l1);
10503 }
10504 }
10505 break;
10506 case OPC_RECIP_S:
10507 {
10508 TCGv_i32 fp0 = tcg_temp_new_i32();
10509
10510 gen_load_fpr32(ctx, fp0, fs);
10511 gen_helper_float_recip_s(fp0, cpu_env, fp0);
10512 gen_store_fpr32(ctx, fp0, fd);
10513 tcg_temp_free_i32(fp0);
10514 }
10515 break;
10516 case OPC_RSQRT_S:
10517 {
10518 TCGv_i32 fp0 = tcg_temp_new_i32();
10519
10520 gen_load_fpr32(ctx, fp0, fs);
10521 gen_helper_float_rsqrt_s(fp0, cpu_env, fp0);
10522 gen_store_fpr32(ctx, fp0, fd);
10523 tcg_temp_free_i32(fp0);
10524 }
10525 break;
10526 case OPC_MADDF_S:
10527 check_insn(ctx, ISA_MIPS_R6);
10528 {
10529 TCGv_i32 fp0 = tcg_temp_new_i32();
10530 TCGv_i32 fp1 = tcg_temp_new_i32();
10531 TCGv_i32 fp2 = tcg_temp_new_i32();
10532 gen_load_fpr32(ctx, fp0, fs);
10533 gen_load_fpr32(ctx, fp1, ft);
10534 gen_load_fpr32(ctx, fp2, fd);
10535 gen_helper_float_maddf_s(fp2, cpu_env, fp0, fp1, fp2);
10536 gen_store_fpr32(ctx, fp2, fd);
10537 tcg_temp_free_i32(fp2);
10538 tcg_temp_free_i32(fp1);
10539 tcg_temp_free_i32(fp0);
10540 }
10541 break;
10542 case OPC_MSUBF_S:
10543 check_insn(ctx, ISA_MIPS_R6);
10544 {
10545 TCGv_i32 fp0 = tcg_temp_new_i32();
10546 TCGv_i32 fp1 = tcg_temp_new_i32();
10547 TCGv_i32 fp2 = tcg_temp_new_i32();
10548 gen_load_fpr32(ctx, fp0, fs);
10549 gen_load_fpr32(ctx, fp1, ft);
10550 gen_load_fpr32(ctx, fp2, fd);
10551 gen_helper_float_msubf_s(fp2, cpu_env, fp0, fp1, fp2);
10552 gen_store_fpr32(ctx, fp2, fd);
10553 tcg_temp_free_i32(fp2);
10554 tcg_temp_free_i32(fp1);
10555 tcg_temp_free_i32(fp0);
10556 }
10557 break;
10558 case OPC_RINT_S:
10559 check_insn(ctx, ISA_MIPS_R6);
10560 {
10561 TCGv_i32 fp0 = tcg_temp_new_i32();
10562 gen_load_fpr32(ctx, fp0, fs);
10563 gen_helper_float_rint_s(fp0, cpu_env, fp0);
10564 gen_store_fpr32(ctx, fp0, fd);
10565 tcg_temp_free_i32(fp0);
10566 }
10567 break;
10568 case OPC_CLASS_S:
10569 check_insn(ctx, ISA_MIPS_R6);
10570 {
10571 TCGv_i32 fp0 = tcg_temp_new_i32();
10572 gen_load_fpr32(ctx, fp0, fs);
10573 gen_helper_float_class_s(fp0, cpu_env, fp0);
10574 gen_store_fpr32(ctx, fp0, fd);
10575 tcg_temp_free_i32(fp0);
10576 }
10577 break;
10578 case OPC_MIN_S: /* OPC_RECIP2_S */
10579 if (ctx->insn_flags & ISA_MIPS_R6) {
10580 /* OPC_MIN_S */
10581 TCGv_i32 fp0 = tcg_temp_new_i32();
10582 TCGv_i32 fp1 = tcg_temp_new_i32();
10583 TCGv_i32 fp2 = tcg_temp_new_i32();
10584 gen_load_fpr32(ctx, fp0, fs);
10585 gen_load_fpr32(ctx, fp1, ft);
10586 gen_helper_float_min_s(fp2, cpu_env, fp0, fp1);
10587 gen_store_fpr32(ctx, fp2, fd);
10588 tcg_temp_free_i32(fp2);
10589 tcg_temp_free_i32(fp1);
10590 tcg_temp_free_i32(fp0);
10591 } else {
10592 /* OPC_RECIP2_S */
10593 check_cp1_64bitmode(ctx);
10594 {
10595 TCGv_i32 fp0 = tcg_temp_new_i32();
10596 TCGv_i32 fp1 = tcg_temp_new_i32();
10597
10598 gen_load_fpr32(ctx, fp0, fs);
10599 gen_load_fpr32(ctx, fp1, ft);
10600 gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1);
10601 tcg_temp_free_i32(fp1);
10602 gen_store_fpr32(ctx, fp0, fd);
10603 tcg_temp_free_i32(fp0);
10604 }
10605 }
10606 break;
10607 case OPC_MINA_S: /* OPC_RECIP1_S */
10608 if (ctx->insn_flags & ISA_MIPS_R6) {
10609 /* OPC_MINA_S */
10610 TCGv_i32 fp0 = tcg_temp_new_i32();
10611 TCGv_i32 fp1 = tcg_temp_new_i32();
10612 TCGv_i32 fp2 = tcg_temp_new_i32();
10613 gen_load_fpr32(ctx, fp0, fs);
10614 gen_load_fpr32(ctx, fp1, ft);
10615 gen_helper_float_mina_s(fp2, cpu_env, fp0, fp1);
10616 gen_store_fpr32(ctx, fp2, fd);
10617 tcg_temp_free_i32(fp2);
10618 tcg_temp_free_i32(fp1);
10619 tcg_temp_free_i32(fp0);
10620 } else {
10621 /* OPC_RECIP1_S */
10622 check_cp1_64bitmode(ctx);
10623 {
10624 TCGv_i32 fp0 = tcg_temp_new_i32();
10625
10626 gen_load_fpr32(ctx, fp0, fs);
10627 gen_helper_float_recip1_s(fp0, cpu_env, fp0);
10628 gen_store_fpr32(ctx, fp0, fd);
10629 tcg_temp_free_i32(fp0);
10630 }
10631 }
10632 break;
10633 case OPC_MAX_S: /* OPC_RSQRT1_S */
10634 if (ctx->insn_flags & ISA_MIPS_R6) {
10635 /* OPC_MAX_S */
10636 TCGv_i32 fp0 = tcg_temp_new_i32();
10637 TCGv_i32 fp1 = tcg_temp_new_i32();
10638 gen_load_fpr32(ctx, fp0, fs);
10639 gen_load_fpr32(ctx, fp1, ft);
10640 gen_helper_float_max_s(fp1, cpu_env, fp0, fp1);
10641 gen_store_fpr32(ctx, fp1, fd);
10642 tcg_temp_free_i32(fp1);
10643 tcg_temp_free_i32(fp0);
10644 } else {
10645 /* OPC_RSQRT1_S */
10646 check_cp1_64bitmode(ctx);
10647 {
10648 TCGv_i32 fp0 = tcg_temp_new_i32();
10649
10650 gen_load_fpr32(ctx, fp0, fs);
10651 gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0);
10652 gen_store_fpr32(ctx, fp0, fd);
10653 tcg_temp_free_i32(fp0);
10654 }
10655 }
10656 break;
10657 case OPC_MAXA_S: /* OPC_RSQRT2_S */
10658 if (ctx->insn_flags & ISA_MIPS_R6) {
10659 /* OPC_MAXA_S */
10660 TCGv_i32 fp0 = tcg_temp_new_i32();
10661 TCGv_i32 fp1 = tcg_temp_new_i32();
10662 gen_load_fpr32(ctx, fp0, fs);
10663 gen_load_fpr32(ctx, fp1, ft);
10664 gen_helper_float_maxa_s(fp1, cpu_env, fp0, fp1);
10665 gen_store_fpr32(ctx, fp1, fd);
10666 tcg_temp_free_i32(fp1);
10667 tcg_temp_free_i32(fp0);
10668 } else {
10669 /* OPC_RSQRT2_S */
10670 check_cp1_64bitmode(ctx);
10671 {
10672 TCGv_i32 fp0 = tcg_temp_new_i32();
10673 TCGv_i32 fp1 = tcg_temp_new_i32();
10674
10675 gen_load_fpr32(ctx, fp0, fs);
10676 gen_load_fpr32(ctx, fp1, ft);
10677 gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1);
10678 tcg_temp_free_i32(fp1);
10679 gen_store_fpr32(ctx, fp0, fd);
10680 tcg_temp_free_i32(fp0);
10681 }
10682 }
10683 break;
10684 case OPC_CVT_D_S:
10685 check_cp1_registers(ctx, fd);
10686 {
10687 TCGv_i32 fp32 = tcg_temp_new_i32();
10688 TCGv_i64 fp64 = tcg_temp_new_i64();
10689
10690 gen_load_fpr32(ctx, fp32, fs);
10691 gen_helper_float_cvtd_s(fp64, cpu_env, fp32);
10692 tcg_temp_free_i32(fp32);
10693 gen_store_fpr64(ctx, fp64, fd);
10694 tcg_temp_free_i64(fp64);
10695 }
10696 break;
10697 case OPC_CVT_W_S:
10698 {
10699 TCGv_i32 fp0 = tcg_temp_new_i32();
10700
10701 gen_load_fpr32(ctx, fp0, fs);
10702 if (ctx->nan2008) {
10703 gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0);
10704 } else {
10705 gen_helper_float_cvt_w_s(fp0, cpu_env, fp0);
10706 }
10707 gen_store_fpr32(ctx, fp0, fd);
10708 tcg_temp_free_i32(fp0);
10709 }
10710 break;
10711 case OPC_CVT_L_S:
10712 check_cp1_64bitmode(ctx);
10713 {
10714 TCGv_i32 fp32 = tcg_temp_new_i32();
10715 TCGv_i64 fp64 = tcg_temp_new_i64();
10716
10717 gen_load_fpr32(ctx, fp32, fs);
10718 if (ctx->nan2008) {
10719 gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32);
10720 } else {
10721 gen_helper_float_cvt_l_s(fp64, cpu_env, fp32);
10722 }
10723 tcg_temp_free_i32(fp32);
10724 gen_store_fpr64(ctx, fp64, fd);
10725 tcg_temp_free_i64(fp64);
10726 }
10727 break;
10728 case OPC_CVT_PS_S:
10729 check_ps(ctx);
10730 {
10731 TCGv_i64 fp64 = tcg_temp_new_i64();
10732 TCGv_i32 fp32_0 = tcg_temp_new_i32();
10733 TCGv_i32 fp32_1 = tcg_temp_new_i32();
10734
10735 gen_load_fpr32(ctx, fp32_0, fs);
10736 gen_load_fpr32(ctx, fp32_1, ft);
10737 tcg_gen_concat_i32_i64(fp64, fp32_1, fp32_0);
10738 tcg_temp_free_i32(fp32_1);
10739 tcg_temp_free_i32(fp32_0);
10740 gen_store_fpr64(ctx, fp64, fd);
10741 tcg_temp_free_i64(fp64);
10742 }
10743 break;
10744 case OPC_CMP_F_S:
10745 case OPC_CMP_UN_S:
10746 case OPC_CMP_EQ_S:
10747 case OPC_CMP_UEQ_S:
10748 case OPC_CMP_OLT_S:
10749 case OPC_CMP_ULT_S:
10750 case OPC_CMP_OLE_S:
10751 case OPC_CMP_ULE_S:
10752 case OPC_CMP_SF_S:
10753 case OPC_CMP_NGLE_S:
10754 case OPC_CMP_SEQ_S:
10755 case OPC_CMP_NGL_S:
10756 case OPC_CMP_LT_S:
10757 case OPC_CMP_NGE_S:
10758 case OPC_CMP_LE_S:
10759 case OPC_CMP_NGT_S:
10760 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10761 if (ctx->opcode & (1 << 6)) {
10762 gen_cmpabs_s(ctx, func - 48, ft, fs, cc);
10763 } else {
10764 gen_cmp_s(ctx, func - 48, ft, fs, cc);
10765 }
10766 break;
10767 case OPC_ADD_D:
10768 check_cp1_registers(ctx, fs | ft | fd);
10769 {
10770 TCGv_i64 fp0 = tcg_temp_new_i64();
10771 TCGv_i64 fp1 = tcg_temp_new_i64();
10772
10773 gen_load_fpr64(ctx, fp0, fs);
10774 gen_load_fpr64(ctx, fp1, ft);
10775 gen_helper_float_add_d(fp0, cpu_env, fp0, fp1);
10776 tcg_temp_free_i64(fp1);
10777 gen_store_fpr64(ctx, fp0, fd);
10778 tcg_temp_free_i64(fp0);
10779 }
10780 break;
10781 case OPC_SUB_D:
10782 check_cp1_registers(ctx, fs | ft | fd);
10783 {
10784 TCGv_i64 fp0 = tcg_temp_new_i64();
10785 TCGv_i64 fp1 = tcg_temp_new_i64();
10786
10787 gen_load_fpr64(ctx, fp0, fs);
10788 gen_load_fpr64(ctx, fp1, ft);
10789 gen_helper_float_sub_d(fp0, cpu_env, fp0, fp1);
10790 tcg_temp_free_i64(fp1);
10791 gen_store_fpr64(ctx, fp0, fd);
10792 tcg_temp_free_i64(fp0);
10793 }
10794 break;
10795 case OPC_MUL_D:
10796 check_cp1_registers(ctx, fs | ft | fd);
10797 {
10798 TCGv_i64 fp0 = tcg_temp_new_i64();
10799 TCGv_i64 fp1 = tcg_temp_new_i64();
10800
10801 gen_load_fpr64(ctx, fp0, fs);
10802 gen_load_fpr64(ctx, fp1, ft);
10803 gen_helper_float_mul_d(fp0, cpu_env, fp0, fp1);
10804 tcg_temp_free_i64(fp1);
10805 gen_store_fpr64(ctx, fp0, fd);
10806 tcg_temp_free_i64(fp0);
10807 }
10808 break;
10809 case OPC_DIV_D:
10810 check_cp1_registers(ctx, fs | ft | fd);
10811 {
10812 TCGv_i64 fp0 = tcg_temp_new_i64();
10813 TCGv_i64 fp1 = tcg_temp_new_i64();
10814
10815 gen_load_fpr64(ctx, fp0, fs);
10816 gen_load_fpr64(ctx, fp1, ft);
10817 gen_helper_float_div_d(fp0, cpu_env, fp0, fp1);
10818 tcg_temp_free_i64(fp1);
10819 gen_store_fpr64(ctx, fp0, fd);
10820 tcg_temp_free_i64(fp0);
10821 }
10822 break;
10823 case OPC_SQRT_D:
10824 check_cp1_registers(ctx, fs | fd);
10825 {
10826 TCGv_i64 fp0 = tcg_temp_new_i64();
10827
10828 gen_load_fpr64(ctx, fp0, fs);
10829 gen_helper_float_sqrt_d(fp0, cpu_env, fp0);
10830 gen_store_fpr64(ctx, fp0, fd);
10831 tcg_temp_free_i64(fp0);
10832 }
10833 break;
10834 case OPC_ABS_D:
10835 check_cp1_registers(ctx, fs | fd);
10836 {
10837 TCGv_i64 fp0 = tcg_temp_new_i64();
10838
10839 gen_load_fpr64(ctx, fp0, fs);
10840 if (ctx->abs2008) {
10841 tcg_gen_andi_i64(fp0, fp0, 0x7fffffffffffffffULL);
10842 } else {
10843 gen_helper_float_abs_d(fp0, fp0);
10844 }
10845 gen_store_fpr64(ctx, fp0, fd);
10846 tcg_temp_free_i64(fp0);
10847 }
10848 break;
10849 case OPC_MOV_D:
10850 check_cp1_registers(ctx, fs | fd);
10851 {
10852 TCGv_i64 fp0 = tcg_temp_new_i64();
10853
10854 gen_load_fpr64(ctx, fp0, fs);
10855 gen_store_fpr64(ctx, fp0, fd);
10856 tcg_temp_free_i64(fp0);
10857 }
10858 break;
10859 case OPC_NEG_D:
10860 check_cp1_registers(ctx, fs | fd);
10861 {
10862 TCGv_i64 fp0 = tcg_temp_new_i64();
10863
10864 gen_load_fpr64(ctx, fp0, fs);
10865 if (ctx->abs2008) {
10866 tcg_gen_xori_i64(fp0, fp0, 1ULL << 63);
10867 } else {
10868 gen_helper_float_chs_d(fp0, fp0);
10869 }
10870 gen_store_fpr64(ctx, fp0, fd);
10871 tcg_temp_free_i64(fp0);
10872 }
10873 break;
10874 case OPC_ROUND_L_D:
10875 check_cp1_64bitmode(ctx);
10876 {
10877 TCGv_i64 fp0 = tcg_temp_new_i64();
10878
10879 gen_load_fpr64(ctx, fp0, fs);
10880 if (ctx->nan2008) {
10881 gen_helper_float_round_2008_l_d(fp0, cpu_env, fp0);
10882 } else {
10883 gen_helper_float_round_l_d(fp0, cpu_env, fp0);
10884 }
10885 gen_store_fpr64(ctx, fp0, fd);
10886 tcg_temp_free_i64(fp0);
10887 }
10888 break;
10889 case OPC_TRUNC_L_D:
10890 check_cp1_64bitmode(ctx);
10891 {
10892 TCGv_i64 fp0 = tcg_temp_new_i64();
10893
10894 gen_load_fpr64(ctx, fp0, fs);
10895 if (ctx->nan2008) {
10896 gen_helper_float_trunc_2008_l_d(fp0, cpu_env, fp0);
10897 } else {
10898 gen_helper_float_trunc_l_d(fp0, cpu_env, fp0);
10899 }
10900 gen_store_fpr64(ctx, fp0, fd);
10901 tcg_temp_free_i64(fp0);
10902 }
10903 break;
10904 case OPC_CEIL_L_D:
10905 check_cp1_64bitmode(ctx);
10906 {
10907 TCGv_i64 fp0 = tcg_temp_new_i64();
10908
10909 gen_load_fpr64(ctx, fp0, fs);
10910 if (ctx->nan2008) {
10911 gen_helper_float_ceil_2008_l_d(fp0, cpu_env, fp0);
10912 } else {
10913 gen_helper_float_ceil_l_d(fp0, cpu_env, fp0);
10914 }
10915 gen_store_fpr64(ctx, fp0, fd);
10916 tcg_temp_free_i64(fp0);
10917 }
10918 break;
10919 case OPC_FLOOR_L_D:
10920 check_cp1_64bitmode(ctx);
10921 {
10922 TCGv_i64 fp0 = tcg_temp_new_i64();
10923
10924 gen_load_fpr64(ctx, fp0, fs);
10925 if (ctx->nan2008) {
10926 gen_helper_float_floor_2008_l_d(fp0, cpu_env, fp0);
10927 } else {
10928 gen_helper_float_floor_l_d(fp0, cpu_env, fp0);
10929 }
10930 gen_store_fpr64(ctx, fp0, fd);
10931 tcg_temp_free_i64(fp0);
10932 }
10933 break;
10934 case OPC_ROUND_W_D:
10935 check_cp1_registers(ctx, fs);
10936 {
10937 TCGv_i32 fp32 = tcg_temp_new_i32();
10938 TCGv_i64 fp64 = tcg_temp_new_i64();
10939
10940 gen_load_fpr64(ctx, fp64, fs);
10941 if (ctx->nan2008) {
10942 gen_helper_float_round_2008_w_d(fp32, cpu_env, fp64);
10943 } else {
10944 gen_helper_float_round_w_d(fp32, cpu_env, fp64);
10945 }
10946 tcg_temp_free_i64(fp64);
10947 gen_store_fpr32(ctx, fp32, fd);
10948 tcg_temp_free_i32(fp32);
10949 }
10950 break;
10951 case OPC_TRUNC_W_D:
10952 check_cp1_registers(ctx, fs);
10953 {
10954 TCGv_i32 fp32 = tcg_temp_new_i32();
10955 TCGv_i64 fp64 = tcg_temp_new_i64();
10956
10957 gen_load_fpr64(ctx, fp64, fs);
10958 if (ctx->nan2008) {
10959 gen_helper_float_trunc_2008_w_d(fp32, cpu_env, fp64);
10960 } else {
10961 gen_helper_float_trunc_w_d(fp32, cpu_env, fp64);
10962 }
10963 tcg_temp_free_i64(fp64);
10964 gen_store_fpr32(ctx, fp32, fd);
10965 tcg_temp_free_i32(fp32);
10966 }
10967 break;
10968 case OPC_CEIL_W_D:
10969 check_cp1_registers(ctx, fs);
10970 {
10971 TCGv_i32 fp32 = tcg_temp_new_i32();
10972 TCGv_i64 fp64 = tcg_temp_new_i64();
10973
10974 gen_load_fpr64(ctx, fp64, fs);
10975 if (ctx->nan2008) {
10976 gen_helper_float_ceil_2008_w_d(fp32, cpu_env, fp64);
10977 } else {
10978 gen_helper_float_ceil_w_d(fp32, cpu_env, fp64);
10979 }
10980 tcg_temp_free_i64(fp64);
10981 gen_store_fpr32(ctx, fp32, fd);
10982 tcg_temp_free_i32(fp32);
10983 }
10984 break;
10985 case OPC_FLOOR_W_D:
10986 check_cp1_registers(ctx, fs);
10987 {
10988 TCGv_i32 fp32 = tcg_temp_new_i32();
10989 TCGv_i64 fp64 = tcg_temp_new_i64();
10990
10991 gen_load_fpr64(ctx, fp64, fs);
10992 if (ctx->nan2008) {
10993 gen_helper_float_floor_2008_w_d(fp32, cpu_env, fp64);
10994 } else {
10995 gen_helper_float_floor_w_d(fp32, cpu_env, fp64);
10996 }
10997 tcg_temp_free_i64(fp64);
10998 gen_store_fpr32(ctx, fp32, fd);
10999 tcg_temp_free_i32(fp32);
11000 }
11001 break;
11002 case OPC_SEL_D:
11003 check_insn(ctx, ISA_MIPS_R6);
11004 gen_sel_d(ctx, op1, fd, ft, fs);
11005 break;
11006 case OPC_SELEQZ_D:
11007 check_insn(ctx, ISA_MIPS_R6);
11008 gen_sel_d(ctx, op1, fd, ft, fs);
11009 break;
11010 case OPC_SELNEZ_D:
11011 check_insn(ctx, ISA_MIPS_R6);
11012 gen_sel_d(ctx, op1, fd, ft, fs);
11013 break;
11014 case OPC_MOVCF_D:
11015 check_insn_opc_removed(ctx, ISA_MIPS_R6);
11016 gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
11017 break;
11018 case OPC_MOVZ_D:
11019 check_insn_opc_removed(ctx, ISA_MIPS_R6);
11020 {
11021 TCGLabel *l1 = gen_new_label();
11022 TCGv_i64 fp0;
11023
11024 if (ft != 0) {
11025 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
11026 }
11027 fp0 = tcg_temp_new_i64();
11028 gen_load_fpr64(ctx, fp0, fs);
11029 gen_store_fpr64(ctx, fp0, fd);
11030 tcg_temp_free_i64(fp0);
11031 gen_set_label(l1);
11032 }
11033 break;
11034 case OPC_MOVN_D:
11035 check_insn_opc_removed(ctx, ISA_MIPS_R6);
11036 {
11037 TCGLabel *l1 = gen_new_label();
11038 TCGv_i64 fp0;
11039
11040 if (ft != 0) {
11041 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
11042 fp0 = tcg_temp_new_i64();
11043 gen_load_fpr64(ctx, fp0, fs);
11044 gen_store_fpr64(ctx, fp0, fd);
11045 tcg_temp_free_i64(fp0);
11046 gen_set_label(l1);
11047 }
11048 }
11049 break;
11050 case OPC_RECIP_D:
11051 check_cp1_registers(ctx, fs | fd);
11052 {
11053 TCGv_i64 fp0 = tcg_temp_new_i64();
11054
11055 gen_load_fpr64(ctx, fp0, fs);
11056 gen_helper_float_recip_d(fp0, cpu_env, fp0);
11057 gen_store_fpr64(ctx, fp0, fd);
11058 tcg_temp_free_i64(fp0);
11059 }
11060 break;
11061 case OPC_RSQRT_D:
11062 check_cp1_registers(ctx, fs | fd);
11063 {
11064 TCGv_i64 fp0 = tcg_temp_new_i64();
11065
11066 gen_load_fpr64(ctx, fp0, fs);
11067 gen_helper_float_rsqrt_d(fp0, cpu_env, fp0);
11068 gen_store_fpr64(ctx, fp0, fd);
11069 tcg_temp_free_i64(fp0);
11070 }
11071 break;
11072 case OPC_MADDF_D:
11073 check_insn(ctx, ISA_MIPS_R6);
11074 {
11075 TCGv_i64 fp0 = tcg_temp_new_i64();
11076 TCGv_i64 fp1 = tcg_temp_new_i64();
11077 TCGv_i64 fp2 = tcg_temp_new_i64();
11078 gen_load_fpr64(ctx, fp0, fs);
11079 gen_load_fpr64(ctx, fp1, ft);
11080 gen_load_fpr64(ctx, fp2, fd);
11081 gen_helper_float_maddf_d(fp2, cpu_env, fp0, fp1, fp2);
11082 gen_store_fpr64(ctx, fp2, fd);
11083 tcg_temp_free_i64(fp2);
11084 tcg_temp_free_i64(fp1);
11085 tcg_temp_free_i64(fp0);
11086 }
11087 break;
11088 case OPC_MSUBF_D:
11089 check_insn(ctx, ISA_MIPS_R6);
11090 {
11091 TCGv_i64 fp0 = tcg_temp_new_i64();
11092 TCGv_i64 fp1 = tcg_temp_new_i64();
11093 TCGv_i64 fp2 = tcg_temp_new_i64();
11094 gen_load_fpr64(ctx, fp0, fs);
11095 gen_load_fpr64(ctx, fp1, ft);
11096 gen_load_fpr64(ctx, fp2, fd);
11097 gen_helper_float_msubf_d(fp2, cpu_env, fp0, fp1, fp2);
11098 gen_store_fpr64(ctx, fp2, fd);
11099 tcg_temp_free_i64(fp2);
11100 tcg_temp_free_i64(fp1);
11101 tcg_temp_free_i64(fp0);
11102 }
11103 break;
11104 case OPC_RINT_D:
11105 check_insn(ctx, ISA_MIPS_R6);
11106 {
11107 TCGv_i64 fp0 = tcg_temp_new_i64();
11108 gen_load_fpr64(ctx, fp0, fs);
11109 gen_helper_float_rint_d(fp0, cpu_env, fp0);
11110 gen_store_fpr64(ctx, fp0, fd);
11111 tcg_temp_free_i64(fp0);
11112 }
11113 break;
11114 case OPC_CLASS_D:
11115 check_insn(ctx, ISA_MIPS_R6);
11116 {
11117 TCGv_i64 fp0 = tcg_temp_new_i64();
11118 gen_load_fpr64(ctx, fp0, fs);
11119 gen_helper_float_class_d(fp0, cpu_env, fp0);
11120 gen_store_fpr64(ctx, fp0, fd);
11121 tcg_temp_free_i64(fp0);
11122 }
11123 break;
11124 case OPC_MIN_D: /* OPC_RECIP2_D */
11125 if (ctx->insn_flags & ISA_MIPS_R6) {
11126 /* OPC_MIN_D */
11127 TCGv_i64 fp0 = tcg_temp_new_i64();
11128 TCGv_i64 fp1 = tcg_temp_new_i64();
11129 gen_load_fpr64(ctx, fp0, fs);
11130 gen_load_fpr64(ctx, fp1, ft);
11131 gen_helper_float_min_d(fp1, cpu_env, fp0, fp1);
11132 gen_store_fpr64(ctx, fp1, fd);
11133 tcg_temp_free_i64(fp1);
11134 tcg_temp_free_i64(fp0);
11135 } else {
11136 /* OPC_RECIP2_D */
11137 check_cp1_64bitmode(ctx);
11138 {
11139 TCGv_i64 fp0 = tcg_temp_new_i64();
11140 TCGv_i64 fp1 = tcg_temp_new_i64();
11141
11142 gen_load_fpr64(ctx, fp0, fs);
11143 gen_load_fpr64(ctx, fp1, ft);
11144 gen_helper_float_recip2_d(fp0, cpu_env, fp0, fp1);
11145 tcg_temp_free_i64(fp1);
11146 gen_store_fpr64(ctx, fp0, fd);
11147 tcg_temp_free_i64(fp0);
11148 }
11149 }
11150 break;
11151 case OPC_MINA_D: /* OPC_RECIP1_D */
11152 if (ctx->insn_flags & ISA_MIPS_R6) {
11153 /* OPC_MINA_D */
11154 TCGv_i64 fp0 = tcg_temp_new_i64();
11155 TCGv_i64 fp1 = tcg_temp_new_i64();
11156 gen_load_fpr64(ctx, fp0, fs);
11157 gen_load_fpr64(ctx, fp1, ft);
11158 gen_helper_float_mina_d(fp1, cpu_env, fp0, fp1);
11159 gen_store_fpr64(ctx, fp1, fd);
11160 tcg_temp_free_i64(fp1);
11161 tcg_temp_free_i64(fp0);
11162 } else {
11163 /* OPC_RECIP1_D */
11164 check_cp1_64bitmode(ctx);
11165 {
11166 TCGv_i64 fp0 = tcg_temp_new_i64();
11167
11168 gen_load_fpr64(ctx, fp0, fs);
11169 gen_helper_float_recip1_d(fp0, cpu_env, fp0);
11170 gen_store_fpr64(ctx, fp0, fd);
11171 tcg_temp_free_i64(fp0);
11172 }
11173 }
11174 break;
11175 case OPC_MAX_D: /* OPC_RSQRT1_D */
11176 if (ctx->insn_flags & ISA_MIPS_R6) {
11177 /* OPC_MAX_D */
11178 TCGv_i64 fp0 = tcg_temp_new_i64();
11179 TCGv_i64 fp1 = tcg_temp_new_i64();
11180 gen_load_fpr64(ctx, fp0, fs);
11181 gen_load_fpr64(ctx, fp1, ft);
11182 gen_helper_float_max_d(fp1, cpu_env, fp0, fp1);
11183 gen_store_fpr64(ctx, fp1, fd);
11184 tcg_temp_free_i64(fp1);
11185 tcg_temp_free_i64(fp0);
11186 } else {
11187 /* OPC_RSQRT1_D */
11188 check_cp1_64bitmode(ctx);
11189 {
11190 TCGv_i64 fp0 = tcg_temp_new_i64();
11191
11192 gen_load_fpr64(ctx, fp0, fs);
11193 gen_helper_float_rsqrt1_d(fp0, cpu_env, fp0);
11194 gen_store_fpr64(ctx, fp0, fd);
11195 tcg_temp_free_i64(fp0);
11196 }
11197 }
11198 break;
11199 case OPC_MAXA_D: /* OPC_RSQRT2_D */
11200 if (ctx->insn_flags & ISA_MIPS_R6) {
11201 /* OPC_MAXA_D */
11202 TCGv_i64 fp0 = tcg_temp_new_i64();
11203 TCGv_i64 fp1 = tcg_temp_new_i64();
11204 gen_load_fpr64(ctx, fp0, fs);
11205 gen_load_fpr64(ctx, fp1, ft);
11206 gen_helper_float_maxa_d(fp1, cpu_env, fp0, fp1);
11207 gen_store_fpr64(ctx, fp1, fd);
11208 tcg_temp_free_i64(fp1);
11209 tcg_temp_free_i64(fp0);
11210 } else {
11211 /* OPC_RSQRT2_D */
11212 check_cp1_64bitmode(ctx);
11213 {
11214 TCGv_i64 fp0 = tcg_temp_new_i64();
11215 TCGv_i64 fp1 = tcg_temp_new_i64();
11216
11217 gen_load_fpr64(ctx, fp0, fs);
11218 gen_load_fpr64(ctx, fp1, ft);
11219 gen_helper_float_rsqrt2_d(fp0, cpu_env, fp0, fp1);
11220 tcg_temp_free_i64(fp1);
11221 gen_store_fpr64(ctx, fp0, fd);
11222 tcg_temp_free_i64(fp0);
11223 }
11224 }
11225 break;
11226 case OPC_CMP_F_D:
11227 case OPC_CMP_UN_D:
11228 case OPC_CMP_EQ_D:
11229 case OPC_CMP_UEQ_D:
11230 case OPC_CMP_OLT_D:
11231 case OPC_CMP_ULT_D:
11232 case OPC_CMP_OLE_D:
11233 case OPC_CMP_ULE_D:
11234 case OPC_CMP_SF_D:
11235 case OPC_CMP_NGLE_D:
11236 case OPC_CMP_SEQ_D:
11237 case OPC_CMP_NGL_D:
11238 case OPC_CMP_LT_D:
11239 case OPC_CMP_NGE_D:
11240 case OPC_CMP_LE_D:
11241 case OPC_CMP_NGT_D:
11242 check_insn_opc_removed(ctx, ISA_MIPS_R6);
11243 if (ctx->opcode & (1 << 6)) {
11244 gen_cmpabs_d(ctx, func - 48, ft, fs, cc);
11245 } else {
11246 gen_cmp_d(ctx, func - 48, ft, fs, cc);
11247 }
11248 break;
11249 case OPC_CVT_S_D:
11250 check_cp1_registers(ctx, fs);
11251 {
11252 TCGv_i32 fp32 = tcg_temp_new_i32();
11253 TCGv_i64 fp64 = tcg_temp_new_i64();
11254
11255 gen_load_fpr64(ctx, fp64, fs);
11256 gen_helper_float_cvts_d(fp32, cpu_env, fp64);
11257 tcg_temp_free_i64(fp64);
11258 gen_store_fpr32(ctx, fp32, fd);
11259 tcg_temp_free_i32(fp32);
11260 }
11261 break;
11262 case OPC_CVT_W_D:
11263 check_cp1_registers(ctx, fs);
11264 {
11265 TCGv_i32 fp32 = tcg_temp_new_i32();
11266 TCGv_i64 fp64 = tcg_temp_new_i64();
11267
11268 gen_load_fpr64(ctx, fp64, fs);
11269 if (ctx->nan2008) {
11270 gen_helper_float_cvt_2008_w_d(fp32, cpu_env, fp64);
11271 } else {
11272 gen_helper_float_cvt_w_d(fp32, cpu_env, fp64);
11273 }
11274 tcg_temp_free_i64(fp64);
11275 gen_store_fpr32(ctx, fp32, fd);
11276 tcg_temp_free_i32(fp32);
11277 }
11278 break;
11279 case OPC_CVT_L_D:
11280 check_cp1_64bitmode(ctx);
11281 {
11282 TCGv_i64 fp0 = tcg_temp_new_i64();
11283
11284 gen_load_fpr64(ctx, fp0, fs);
11285 if (ctx->nan2008) {
11286 gen_helper_float_cvt_2008_l_d(fp0, cpu_env, fp0);
11287 } else {
11288 gen_helper_float_cvt_l_d(fp0, cpu_env, fp0);
11289 }
11290 gen_store_fpr64(ctx, fp0, fd);
11291 tcg_temp_free_i64(fp0);
11292 }
11293 break;
11294 case OPC_CVT_S_W:
11295 {
11296 TCGv_i32 fp0 = tcg_temp_new_i32();
11297
11298 gen_load_fpr32(ctx, fp0, fs);
11299 gen_helper_float_cvts_w(fp0, cpu_env, fp0);
11300 gen_store_fpr32(ctx, fp0, fd);
11301 tcg_temp_free_i32(fp0);
11302 }
11303 break;
11304 case OPC_CVT_D_W:
11305 check_cp1_registers(ctx, fd);
11306 {
11307 TCGv_i32 fp32 = tcg_temp_new_i32();
11308 TCGv_i64 fp64 = tcg_temp_new_i64();
11309
11310 gen_load_fpr32(ctx, fp32, fs);
11311 gen_helper_float_cvtd_w(fp64, cpu_env, fp32);
11312 tcg_temp_free_i32(fp32);
11313 gen_store_fpr64(ctx, fp64, fd);
11314 tcg_temp_free_i64(fp64);
11315 }
11316 break;
11317 case OPC_CVT_S_L:
11318 check_cp1_64bitmode(ctx);
11319 {
11320 TCGv_i32 fp32 = tcg_temp_new_i32();
11321 TCGv_i64 fp64 = tcg_temp_new_i64();
11322
11323 gen_load_fpr64(ctx, fp64, fs);
11324 gen_helper_float_cvts_l(fp32, cpu_env, fp64);
11325 tcg_temp_free_i64(fp64);
11326 gen_store_fpr32(ctx, fp32, fd);
11327 tcg_temp_free_i32(fp32);
11328 }
11329 break;
11330 case OPC_CVT_D_L:
11331 check_cp1_64bitmode(ctx);
11332 {
11333 TCGv_i64 fp0 = tcg_temp_new_i64();
11334
11335 gen_load_fpr64(ctx, fp0, fs);
11336 gen_helper_float_cvtd_l(fp0, cpu_env, fp0);
11337 gen_store_fpr64(ctx, fp0, fd);
11338 tcg_temp_free_i64(fp0);
11339 }
11340 break;
11341 case OPC_CVT_PS_PW:
11342 check_ps(ctx);
11343 {
11344 TCGv_i64 fp0 = tcg_temp_new_i64();
11345
11346 gen_load_fpr64(ctx, fp0, fs);
11347 gen_helper_float_cvtps_pw(fp0, cpu_env, fp0);
11348 gen_store_fpr64(ctx, fp0, fd);
11349 tcg_temp_free_i64(fp0);
11350 }
11351 break;
11352 case OPC_ADD_PS:
11353 check_ps(ctx);
11354 {
11355 TCGv_i64 fp0 = tcg_temp_new_i64();
11356 TCGv_i64 fp1 = tcg_temp_new_i64();
11357
11358 gen_load_fpr64(ctx, fp0, fs);
11359 gen_load_fpr64(ctx, fp1, ft);
11360 gen_helper_float_add_ps(fp0, cpu_env, fp0, fp1);
11361 tcg_temp_free_i64(fp1);
11362 gen_store_fpr64(ctx, fp0, fd);
11363 tcg_temp_free_i64(fp0);
11364 }
11365 break;
11366 case OPC_SUB_PS:
11367 check_ps(ctx);
11368 {
11369 TCGv_i64 fp0 = tcg_temp_new_i64();
11370 TCGv_i64 fp1 = tcg_temp_new_i64();
11371
11372 gen_load_fpr64(ctx, fp0, fs);
11373 gen_load_fpr64(ctx, fp1, ft);
11374 gen_helper_float_sub_ps(fp0, cpu_env, fp0, fp1);
11375 tcg_temp_free_i64(fp1);
11376 gen_store_fpr64(ctx, fp0, fd);
11377 tcg_temp_free_i64(fp0);
11378 }
11379 break;
11380 case OPC_MUL_PS:
11381 check_ps(ctx);
11382 {
11383 TCGv_i64 fp0 = tcg_temp_new_i64();
11384 TCGv_i64 fp1 = tcg_temp_new_i64();
11385
11386 gen_load_fpr64(ctx, fp0, fs);
11387 gen_load_fpr64(ctx, fp1, ft);
11388 gen_helper_float_mul_ps(fp0, cpu_env, fp0, fp1);
11389 tcg_temp_free_i64(fp1);
11390 gen_store_fpr64(ctx, fp0, fd);
11391 tcg_temp_free_i64(fp0);
11392 }
11393 break;
11394 case OPC_ABS_PS:
11395 check_ps(ctx);
11396 {
11397 TCGv_i64 fp0 = tcg_temp_new_i64();
11398
11399 gen_load_fpr64(ctx, fp0, fs);
11400 gen_helper_float_abs_ps(fp0, fp0);
11401 gen_store_fpr64(ctx, fp0, fd);
11402 tcg_temp_free_i64(fp0);
11403 }
11404 break;
11405 case OPC_MOV_PS:
11406 check_ps(ctx);
11407 {
11408 TCGv_i64 fp0 = tcg_temp_new_i64();
11409
11410 gen_load_fpr64(ctx, fp0, fs);
11411 gen_store_fpr64(ctx, fp0, fd);
11412 tcg_temp_free_i64(fp0);
11413 }
11414 break;
11415 case OPC_NEG_PS:
11416 check_ps(ctx);
11417 {
11418 TCGv_i64 fp0 = tcg_temp_new_i64();
11419
11420 gen_load_fpr64(ctx, fp0, fs);
11421 gen_helper_float_chs_ps(fp0, fp0);
11422 gen_store_fpr64(ctx, fp0, fd);
11423 tcg_temp_free_i64(fp0);
11424 }
11425 break;
11426 case OPC_MOVCF_PS:
11427 check_ps(ctx);
11428 gen_movcf_ps(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
11429 break;
11430 case OPC_MOVZ_PS:
11431 check_ps(ctx);
11432 {
11433 TCGLabel *l1 = gen_new_label();
11434 TCGv_i64 fp0;
11435
11436 if (ft != 0) {
11437 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
11438 }
11439 fp0 = tcg_temp_new_i64();
11440 gen_load_fpr64(ctx, fp0, fs);
11441 gen_store_fpr64(ctx, fp0, fd);
11442 tcg_temp_free_i64(fp0);
11443 gen_set_label(l1);
11444 }
11445 break;
11446 case OPC_MOVN_PS:
11447 check_ps(ctx);
11448 {
11449 TCGLabel *l1 = gen_new_label();
11450 TCGv_i64 fp0;
11451
11452 if (ft != 0) {
11453 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
11454 fp0 = tcg_temp_new_i64();
11455 gen_load_fpr64(ctx, fp0, fs);
11456 gen_store_fpr64(ctx, fp0, fd);
11457 tcg_temp_free_i64(fp0);
11458 gen_set_label(l1);
11459 }
11460 }
11461 break;
11462 case OPC_ADDR_PS:
11463 check_ps(ctx);
11464 {
11465 TCGv_i64 fp0 = tcg_temp_new_i64();
11466 TCGv_i64 fp1 = tcg_temp_new_i64();
11467
11468 gen_load_fpr64(ctx, fp0, ft);
11469 gen_load_fpr64(ctx, fp1, fs);
11470 gen_helper_float_addr_ps(fp0, cpu_env, fp0, fp1);
11471 tcg_temp_free_i64(fp1);
11472 gen_store_fpr64(ctx, fp0, fd);
11473 tcg_temp_free_i64(fp0);
11474 }
11475 break;
11476 case OPC_MULR_PS:
11477 check_ps(ctx);
11478 {
11479 TCGv_i64 fp0 = tcg_temp_new_i64();
11480 TCGv_i64 fp1 = tcg_temp_new_i64();
11481
11482 gen_load_fpr64(ctx, fp0, ft);
11483 gen_load_fpr64(ctx, fp1, fs);
11484 gen_helper_float_mulr_ps(fp0, cpu_env, fp0, fp1);
11485 tcg_temp_free_i64(fp1);
11486 gen_store_fpr64(ctx, fp0, fd);
11487 tcg_temp_free_i64(fp0);
11488 }
11489 break;
11490 case OPC_RECIP2_PS:
11491 check_ps(ctx);
11492 {
11493 TCGv_i64 fp0 = tcg_temp_new_i64();
11494 TCGv_i64 fp1 = tcg_temp_new_i64();
11495
11496 gen_load_fpr64(ctx, fp0, fs);
11497 gen_load_fpr64(ctx, fp1, ft);
11498 gen_helper_float_recip2_ps(fp0, cpu_env, fp0, fp1);
11499 tcg_temp_free_i64(fp1);
11500 gen_store_fpr64(ctx, fp0, fd);
11501 tcg_temp_free_i64(fp0);
11502 }
11503 break;
11504 case OPC_RECIP1_PS:
11505 check_ps(ctx);
11506 {
11507 TCGv_i64 fp0 = tcg_temp_new_i64();
11508
11509 gen_load_fpr64(ctx, fp0, fs);
11510 gen_helper_float_recip1_ps(fp0, cpu_env, fp0);
11511 gen_store_fpr64(ctx, fp0, fd);
11512 tcg_temp_free_i64(fp0);
11513 }
11514 break;
11515 case OPC_RSQRT1_PS:
11516 check_ps(ctx);
11517 {
11518 TCGv_i64 fp0 = tcg_temp_new_i64();
11519
11520 gen_load_fpr64(ctx, fp0, fs);
11521 gen_helper_float_rsqrt1_ps(fp0, cpu_env, fp0);
11522 gen_store_fpr64(ctx, fp0, fd);
11523 tcg_temp_free_i64(fp0);
11524 }
11525 break;
11526 case OPC_RSQRT2_PS:
11527 check_ps(ctx);
11528 {
11529 TCGv_i64 fp0 = tcg_temp_new_i64();
11530 TCGv_i64 fp1 = tcg_temp_new_i64();
11531
11532 gen_load_fpr64(ctx, fp0, fs);
11533 gen_load_fpr64(ctx, fp1, ft);
11534 gen_helper_float_rsqrt2_ps(fp0, cpu_env, fp0, fp1);
11535 tcg_temp_free_i64(fp1);
11536 gen_store_fpr64(ctx, fp0, fd);
11537 tcg_temp_free_i64(fp0);
11538 }
11539 break;
11540 case OPC_CVT_S_PU:
11541 check_cp1_64bitmode(ctx);
11542 {
11543 TCGv_i32 fp0 = tcg_temp_new_i32();
11544
11545 gen_load_fpr32h(ctx, fp0, fs);
11546 gen_helper_float_cvts_pu(fp0, cpu_env, fp0);
11547 gen_store_fpr32(ctx, fp0, fd);
11548 tcg_temp_free_i32(fp0);
11549 }
11550 break;
11551 case OPC_CVT_PW_PS:
11552 check_ps(ctx);
11553 {
11554 TCGv_i64 fp0 = tcg_temp_new_i64();
11555
11556 gen_load_fpr64(ctx, fp0, fs);
11557 gen_helper_float_cvtpw_ps(fp0, cpu_env, fp0);
11558 gen_store_fpr64(ctx, fp0, fd);
11559 tcg_temp_free_i64(fp0);
11560 }
11561 break;
11562 case OPC_CVT_S_PL:
11563 check_cp1_64bitmode(ctx);
11564 {
11565 TCGv_i32 fp0 = tcg_temp_new_i32();
11566
11567 gen_load_fpr32(ctx, fp0, fs);
11568 gen_helper_float_cvts_pl(fp0, cpu_env, fp0);
11569 gen_store_fpr32(ctx, fp0, fd);
11570 tcg_temp_free_i32(fp0);
11571 }
11572 break;
11573 case OPC_PLL_PS:
11574 check_ps(ctx);
11575 {
11576 TCGv_i32 fp0 = tcg_temp_new_i32();
11577 TCGv_i32 fp1 = tcg_temp_new_i32();
11578
11579 gen_load_fpr32(ctx, fp0, fs);
11580 gen_load_fpr32(ctx, fp1, ft);
11581 gen_store_fpr32h(ctx, fp0, fd);
11582 gen_store_fpr32(ctx, fp1, fd);
11583 tcg_temp_free_i32(fp0);
11584 tcg_temp_free_i32(fp1);
11585 }
11586 break;
11587 case OPC_PLU_PS:
11588 check_ps(ctx);
11589 {
11590 TCGv_i32 fp0 = tcg_temp_new_i32();
11591 TCGv_i32 fp1 = tcg_temp_new_i32();
11592
11593 gen_load_fpr32(ctx, fp0, fs);
11594 gen_load_fpr32h(ctx, fp1, ft);
11595 gen_store_fpr32(ctx, fp1, fd);
11596 gen_store_fpr32h(ctx, fp0, fd);
11597 tcg_temp_free_i32(fp0);
11598 tcg_temp_free_i32(fp1);
11599 }
11600 break;
11601 case OPC_PUL_PS:
11602 check_ps(ctx);
11603 {
11604 TCGv_i32 fp0 = tcg_temp_new_i32();
11605 TCGv_i32 fp1 = tcg_temp_new_i32();
11606
11607 gen_load_fpr32h(ctx, fp0, fs);
11608 gen_load_fpr32(ctx, fp1, ft);
11609 gen_store_fpr32(ctx, fp1, fd);
11610 gen_store_fpr32h(ctx, fp0, fd);
11611 tcg_temp_free_i32(fp0);
11612 tcg_temp_free_i32(fp1);
11613 }
11614 break;
11615 case OPC_PUU_PS:
11616 check_ps(ctx);
11617 {
11618 TCGv_i32 fp0 = tcg_temp_new_i32();
11619 TCGv_i32 fp1 = tcg_temp_new_i32();
11620
11621 gen_load_fpr32h(ctx, fp0, fs);
11622 gen_load_fpr32h(ctx, fp1, ft);
11623 gen_store_fpr32(ctx, fp1, fd);
11624 gen_store_fpr32h(ctx, fp0, fd);
11625 tcg_temp_free_i32(fp0);
11626 tcg_temp_free_i32(fp1);
11627 }
11628 break;
11629 case OPC_CMP_F_PS:
11630 case OPC_CMP_UN_PS:
11631 case OPC_CMP_EQ_PS:
11632 case OPC_CMP_UEQ_PS:
11633 case OPC_CMP_OLT_PS:
11634 case OPC_CMP_ULT_PS:
11635 case OPC_CMP_OLE_PS:
11636 case OPC_CMP_ULE_PS:
11637 case OPC_CMP_SF_PS:
11638 case OPC_CMP_NGLE_PS:
11639 case OPC_CMP_SEQ_PS:
11640 case OPC_CMP_NGL_PS:
11641 case OPC_CMP_LT_PS:
11642 case OPC_CMP_NGE_PS:
11643 case OPC_CMP_LE_PS:
11644 case OPC_CMP_NGT_PS:
11645 if (ctx->opcode & (1 << 6)) {
11646 gen_cmpabs_ps(ctx, func - 48, ft, fs, cc);
11647 } else {
11648 gen_cmp_ps(ctx, func - 48, ft, fs, cc);
11649 }
11650 break;
11651 default:
11652 MIPS_INVAL("farith");
11653 gen_reserved_instruction(ctx);
11654 return;
11655 }
11656 }
11657
11658 /* Coprocessor 3 (FPU) */
11659 static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
11660 int fd, int fs, int base, int index)
11661 {
11662 TCGv t0 = tcg_temp_new();
11663
11664 if (base == 0) {
11665 gen_load_gpr(t0, index);
11666 } else if (index == 0) {
11667 gen_load_gpr(t0, base);
11668 } else {
11669 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
11670 }
11671 /*
11672 * Don't do NOP if destination is zero: we must perform the actual
11673 * memory access.
11674 */
11675 switch (opc) {
11676 case OPC_LWXC1:
11677 check_cop1x(ctx);
11678 {
11679 TCGv_i32 fp0 = tcg_temp_new_i32();
11680
11681 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
11682 tcg_gen_trunc_tl_i32(fp0, t0);
11683 gen_store_fpr32(ctx, fp0, fd);
11684 tcg_temp_free_i32(fp0);
11685 }
11686 break;
11687 case OPC_LDXC1:
11688 check_cop1x(ctx);
11689 check_cp1_registers(ctx, fd);
11690 {
11691 TCGv_i64 fp0 = tcg_temp_new_i64();
11692 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
11693 gen_store_fpr64(ctx, fp0, fd);
11694 tcg_temp_free_i64(fp0);
11695 }
11696 break;
11697 case OPC_LUXC1:
11698 check_cp1_64bitmode(ctx);
11699 tcg_gen_andi_tl(t0, t0, ~0x7);
11700 {
11701 TCGv_i64 fp0 = tcg_temp_new_i64();
11702
11703 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
11704 gen_store_fpr64(ctx, fp0, fd);
11705 tcg_temp_free_i64(fp0);
11706 }
11707 break;
11708 case OPC_SWXC1:
11709 check_cop1x(ctx);
11710 {
11711 TCGv_i32 fp0 = tcg_temp_new_i32();
11712 gen_load_fpr32(ctx, fp0, fs);
11713 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL);
11714 tcg_temp_free_i32(fp0);
11715 }
11716 break;
11717 case OPC_SDXC1:
11718 check_cop1x(ctx);
11719 check_cp1_registers(ctx, fs);
11720 {
11721 TCGv_i64 fp0 = tcg_temp_new_i64();
11722 gen_load_fpr64(ctx, fp0, fs);
11723 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
11724 tcg_temp_free_i64(fp0);
11725 }
11726 break;
11727 case OPC_SUXC1:
11728 check_cp1_64bitmode(ctx);
11729 tcg_gen_andi_tl(t0, t0, ~0x7);
11730 {
11731 TCGv_i64 fp0 = tcg_temp_new_i64();
11732 gen_load_fpr64(ctx, fp0, fs);
11733 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
11734 tcg_temp_free_i64(fp0);
11735 }
11736 break;
11737 }
11738 tcg_temp_free(t0);
11739 }
11740
11741 static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
11742 int fd, int fr, int fs, int ft)
11743 {
11744 switch (opc) {
11745 case OPC_ALNV_PS:
11746 check_ps(ctx);
11747 {
11748 TCGv t0 = tcg_temp_local_new();
11749 TCGv_i32 fp = tcg_temp_new_i32();
11750 TCGv_i32 fph = tcg_temp_new_i32();
11751 TCGLabel *l1 = gen_new_label();
11752 TCGLabel *l2 = gen_new_label();
11753
11754 gen_load_gpr(t0, fr);
11755 tcg_gen_andi_tl(t0, t0, 0x7);
11756
11757 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
11758 gen_load_fpr32(ctx, fp, fs);
11759 gen_load_fpr32h(ctx, fph, fs);
11760 gen_store_fpr32(ctx, fp, fd);
11761 gen_store_fpr32h(ctx, fph, fd);
11762 tcg_gen_br(l2);
11763 gen_set_label(l1);
11764 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
11765 tcg_temp_free(t0);
11766 #ifdef TARGET_WORDS_BIGENDIAN
11767 gen_load_fpr32(ctx, fp, fs);
11768 gen_load_fpr32h(ctx, fph, ft);
11769 gen_store_fpr32h(ctx, fp, fd);
11770 gen_store_fpr32(ctx, fph, fd);
11771 #else
11772 gen_load_fpr32h(ctx, fph, fs);
11773 gen_load_fpr32(ctx, fp, ft);
11774 gen_store_fpr32(ctx, fph, fd);
11775 gen_store_fpr32h(ctx, fp, fd);
11776 #endif
11777 gen_set_label(l2);
11778 tcg_temp_free_i32(fp);
11779 tcg_temp_free_i32(fph);
11780 }
11781 break;
11782 case OPC_MADD_S:
11783 check_cop1x(ctx);
11784 {
11785 TCGv_i32 fp0 = tcg_temp_new_i32();
11786 TCGv_i32 fp1 = tcg_temp_new_i32();
11787 TCGv_i32 fp2 = tcg_temp_new_i32();
11788
11789 gen_load_fpr32(ctx, fp0, fs);
11790 gen_load_fpr32(ctx, fp1, ft);
11791 gen_load_fpr32(ctx, fp2, fr);
11792 gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2);
11793 tcg_temp_free_i32(fp0);
11794 tcg_temp_free_i32(fp1);
11795 gen_store_fpr32(ctx, fp2, fd);
11796 tcg_temp_free_i32(fp2);
11797 }
11798 break;
11799 case OPC_MADD_D:
11800 check_cop1x(ctx);
11801 check_cp1_registers(ctx, fd | fs | ft | fr);
11802 {
11803 TCGv_i64 fp0 = tcg_temp_new_i64();
11804 TCGv_i64 fp1 = tcg_temp_new_i64();
11805 TCGv_i64 fp2 = tcg_temp_new_i64();
11806
11807 gen_load_fpr64(ctx, fp0, fs);
11808 gen_load_fpr64(ctx, fp1, ft);
11809 gen_load_fpr64(ctx, fp2, fr);
11810 gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2);
11811 tcg_temp_free_i64(fp0);
11812 tcg_temp_free_i64(fp1);
11813 gen_store_fpr64(ctx, fp2, fd);
11814 tcg_temp_free_i64(fp2);
11815 }
11816 break;
11817 case OPC_MADD_PS:
11818 check_ps(ctx);
11819 {
11820 TCGv_i64 fp0 = tcg_temp_new_i64();
11821 TCGv_i64 fp1 = tcg_temp_new_i64();
11822 TCGv_i64 fp2 = tcg_temp_new_i64();
11823
11824 gen_load_fpr64(ctx, fp0, fs);
11825 gen_load_fpr64(ctx, fp1, ft);
11826 gen_load_fpr64(ctx, fp2, fr);
11827 gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2);
11828 tcg_temp_free_i64(fp0);
11829 tcg_temp_free_i64(fp1);
11830 gen_store_fpr64(ctx, fp2, fd);
11831 tcg_temp_free_i64(fp2);
11832 }
11833 break;
11834 case OPC_MSUB_S:
11835 check_cop1x(ctx);
11836 {
11837 TCGv_i32 fp0 = tcg_temp_new_i32();
11838 TCGv_i32 fp1 = tcg_temp_new_i32();
11839 TCGv_i32 fp2 = tcg_temp_new_i32();
11840
11841 gen_load_fpr32(ctx, fp0, fs);
11842 gen_load_fpr32(ctx, fp1, ft);
11843 gen_load_fpr32(ctx, fp2, fr);
11844 gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2);
11845 tcg_temp_free_i32(fp0);
11846 tcg_temp_free_i32(fp1);
11847 gen_store_fpr32(ctx, fp2, fd);
11848 tcg_temp_free_i32(fp2);
11849 }
11850 break;
11851 case OPC_MSUB_D:
11852 check_cop1x(ctx);
11853 check_cp1_registers(ctx, fd | fs | ft | fr);
11854 {
11855 TCGv_i64 fp0 = tcg_temp_new_i64();
11856 TCGv_i64 fp1 = tcg_temp_new_i64();
11857 TCGv_i64 fp2 = tcg_temp_new_i64();
11858
11859 gen_load_fpr64(ctx, fp0, fs);
11860 gen_load_fpr64(ctx, fp1, ft);
11861 gen_load_fpr64(ctx, fp2, fr);
11862 gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2);
11863 tcg_temp_free_i64(fp0);
11864 tcg_temp_free_i64(fp1);
11865 gen_store_fpr64(ctx, fp2, fd);
11866 tcg_temp_free_i64(fp2);
11867 }
11868 break;
11869 case OPC_MSUB_PS:
11870 check_ps(ctx);
11871 {
11872 TCGv_i64 fp0 = tcg_temp_new_i64();
11873 TCGv_i64 fp1 = tcg_temp_new_i64();
11874 TCGv_i64 fp2 = tcg_temp_new_i64();
11875
11876 gen_load_fpr64(ctx, fp0, fs);
11877 gen_load_fpr64(ctx, fp1, ft);
11878 gen_load_fpr64(ctx, fp2, fr);
11879 gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2);
11880 tcg_temp_free_i64(fp0);
11881 tcg_temp_free_i64(fp1);
11882 gen_store_fpr64(ctx, fp2, fd);
11883 tcg_temp_free_i64(fp2);
11884 }
11885 break;
11886 case OPC_NMADD_S:
11887 check_cop1x(ctx);
11888 {
11889 TCGv_i32 fp0 = tcg_temp_new_i32();
11890 TCGv_i32 fp1 = tcg_temp_new_i32();
11891 TCGv_i32 fp2 = tcg_temp_new_i32();
11892
11893 gen_load_fpr32(ctx, fp0, fs);
11894 gen_load_fpr32(ctx, fp1, ft);
11895 gen_load_fpr32(ctx, fp2, fr);
11896 gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2);
11897 tcg_temp_free_i32(fp0);
11898 tcg_temp_free_i32(fp1);
11899 gen_store_fpr32(ctx, fp2, fd);
11900 tcg_temp_free_i32(fp2);
11901 }
11902 break;
11903 case OPC_NMADD_D:
11904 check_cop1x(ctx);
11905 check_cp1_registers(ctx, fd | fs | ft | fr);
11906 {
11907 TCGv_i64 fp0 = tcg_temp_new_i64();
11908 TCGv_i64 fp1 = tcg_temp_new_i64();
11909 TCGv_i64 fp2 = tcg_temp_new_i64();
11910
11911 gen_load_fpr64(ctx, fp0, fs);
11912 gen_load_fpr64(ctx, fp1, ft);
11913 gen_load_fpr64(ctx, fp2, fr);
11914 gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2);
11915 tcg_temp_free_i64(fp0);
11916 tcg_temp_free_i64(fp1);
11917 gen_store_fpr64(ctx, fp2, fd);
11918 tcg_temp_free_i64(fp2);
11919 }
11920 break;
11921 case OPC_NMADD_PS:
11922 check_ps(ctx);
11923 {
11924 TCGv_i64 fp0 = tcg_temp_new_i64();
11925 TCGv_i64 fp1 = tcg_temp_new_i64();
11926 TCGv_i64 fp2 = tcg_temp_new_i64();
11927
11928 gen_load_fpr64(ctx, fp0, fs);
11929 gen_load_fpr64(ctx, fp1, ft);
11930 gen_load_fpr64(ctx, fp2, fr);
11931 gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2);
11932 tcg_temp_free_i64(fp0);
11933 tcg_temp_free_i64(fp1);
11934 gen_store_fpr64(ctx, fp2, fd);
11935 tcg_temp_free_i64(fp2);
11936 }
11937 break;
11938 case OPC_NMSUB_S:
11939 check_cop1x(ctx);
11940 {
11941 TCGv_i32 fp0 = tcg_temp_new_i32();
11942 TCGv_i32 fp1 = tcg_temp_new_i32();
11943 TCGv_i32 fp2 = tcg_temp_new_i32();
11944
11945 gen_load_fpr32(ctx, fp0, fs);
11946 gen_load_fpr32(ctx, fp1, ft);
11947 gen_load_fpr32(ctx, fp2, fr);
11948 gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2);
11949 tcg_temp_free_i32(fp0);
11950 tcg_temp_free_i32(fp1);
11951 gen_store_fpr32(ctx, fp2, fd);
11952 tcg_temp_free_i32(fp2);
11953 }
11954 break;
11955 case OPC_NMSUB_D:
11956 check_cop1x(ctx);
11957 check_cp1_registers(ctx, fd | fs | ft | fr);
11958 {
11959 TCGv_i64 fp0 = tcg_temp_new_i64();
11960 TCGv_i64 fp1 = tcg_temp_new_i64();
11961 TCGv_i64 fp2 = tcg_temp_new_i64();
11962
11963 gen_load_fpr64(ctx, fp0, fs);
11964 gen_load_fpr64(ctx, fp1, ft);
11965 gen_load_fpr64(ctx, fp2, fr);
11966 gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2);
11967 tcg_temp_free_i64(fp0);
11968 tcg_temp_free_i64(fp1);
11969 gen_store_fpr64(ctx, fp2, fd);
11970 tcg_temp_free_i64(fp2);
11971 }
11972 break;
11973 case OPC_NMSUB_PS:
11974 check_ps(ctx);
11975 {
11976 TCGv_i64 fp0 = tcg_temp_new_i64();
11977 TCGv_i64 fp1 = tcg_temp_new_i64();
11978 TCGv_i64 fp2 = tcg_temp_new_i64();
11979
11980 gen_load_fpr64(ctx, fp0, fs);
11981 gen_load_fpr64(ctx, fp1, ft);
11982 gen_load_fpr64(ctx, fp2, fr);
11983 gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2);
11984 tcg_temp_free_i64(fp0);
11985 tcg_temp_free_i64(fp1);
11986 gen_store_fpr64(ctx, fp2, fd);
11987 tcg_temp_free_i64(fp2);
11988 }
11989 break;
11990 default:
11991 MIPS_INVAL("flt3_arith");
11992 gen_reserved_instruction(ctx);
11993 return;
11994 }
11995 }
11996
11997 void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
11998 {
11999 TCGv t0;
12000
12001 #if !defined(CONFIG_USER_ONLY)
12002 /*
12003 * The Linux kernel will emulate rdhwr if it's not supported natively.
12004 * Therefore only check the ISA in system mode.
12005 */
12006 check_insn(ctx, ISA_MIPS_R2);
12007 #endif
12008 t0 = tcg_temp_new();
12009
12010 switch (rd) {
12011 case 0:
12012 gen_helper_rdhwr_cpunum(t0, cpu_env);
12013 gen_store_gpr(t0, rt);
12014 break;
12015 case 1:
12016 gen_helper_rdhwr_synci_step(t0, cpu_env);
12017 gen_store_gpr(t0, rt);
12018 break;
12019 case 2:
12020 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
12021 gen_io_start();
12022 }
12023 gen_helper_rdhwr_cc(t0, cpu_env);
12024 gen_store_gpr(t0, rt);
12025 /*
12026 * Break the TB to be able to take timer interrupts immediately
12027 * after reading count. DISAS_STOP isn't sufficient, we need to ensure
12028 * we break completely out of translated code.
12029 */
12030 gen_save_pc(ctx->base.pc_next + 4);
12031 ctx->base.is_jmp = DISAS_EXIT;
12032 break;
12033 case 3:
12034 gen_helper_rdhwr_ccres(t0, cpu_env);
12035 gen_store_gpr(t0, rt);
12036 break;
12037 case 4:
12038 check_insn(ctx, ISA_MIPS_R6);
12039 if (sel != 0) {
12040 /*
12041 * Performance counter registers are not implemented other than
12042 * control register 0.
12043 */
12044 generate_exception(ctx, EXCP_RI);
12045 }
12046 gen_helper_rdhwr_performance(t0, cpu_env);
12047 gen_store_gpr(t0, rt);
12048 break;
12049 case 5:
12050 check_insn(ctx, ISA_MIPS_R6);
12051 gen_helper_rdhwr_xnp(t0, cpu_env);
12052 gen_store_gpr(t0, rt);
12053 break;
12054 case 29:
12055 #if defined(CONFIG_USER_ONLY)
12056 tcg_gen_ld_tl(t0, cpu_env,
12057 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
12058 gen_store_gpr(t0, rt);
12059 break;
12060 #else
12061 if ((ctx->hflags & MIPS_HFLAG_CP0) ||
12062 (ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) {
12063 tcg_gen_ld_tl(t0, cpu_env,
12064 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
12065 gen_store_gpr(t0, rt);
12066 } else {
12067 gen_reserved_instruction(ctx);
12068 }
12069 break;
12070 #endif
12071 default: /* Invalid */
12072 MIPS_INVAL("rdhwr");
12073 gen_reserved_instruction(ctx);
12074 break;
12075 }
12076 tcg_temp_free(t0);
12077 }
12078
12079 static inline void clear_branch_hflags(DisasContext *ctx)
12080 {
12081 ctx->hflags &= ~MIPS_HFLAG_BMASK;
12082 if (ctx->base.is_jmp == DISAS_NEXT) {
12083 save_cpu_state(ctx, 0);
12084 } else {
12085 /*
12086 * It is not safe to save ctx->hflags as hflags may be changed
12087 * in execution time by the instruction in delay / forbidden slot.
12088 */
12089 tcg_gen_andi_i32(hflags, hflags, ~MIPS_HFLAG_BMASK);
12090 }
12091 }
12092
12093 static void gen_branch(DisasContext *ctx, int insn_bytes)
12094 {
12095 if (ctx->hflags & MIPS_HFLAG_BMASK) {
12096 int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK;
12097 /* Branches completion */
12098 clear_branch_hflags(ctx);
12099 ctx->base.is_jmp = DISAS_NORETURN;
12100 /* FIXME: Need to clear can_do_io. */
12101 switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) {
12102 case MIPS_HFLAG_FBNSLOT:
12103 gen_goto_tb(ctx, 0, ctx->base.pc_next + insn_bytes);
12104 break;
12105 case MIPS_HFLAG_B:
12106 /* unconditional branch */
12107 if (proc_hflags & MIPS_HFLAG_BX) {
12108 tcg_gen_xori_i32(hflags, hflags, MIPS_HFLAG_M16);
12109 }
12110 gen_goto_tb(ctx, 0, ctx->btarget);
12111 break;
12112 case MIPS_HFLAG_BL:
12113 /* blikely taken case */
12114 gen_goto_tb(ctx, 0, ctx->btarget);
12115 break;
12116 case MIPS_HFLAG_BC:
12117 /* Conditional branch */
12118 {
12119 TCGLabel *l1 = gen_new_label();
12120
12121 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
12122 gen_goto_tb(ctx, 1, ctx->base.pc_next + insn_bytes);
12123 gen_set_label(l1);
12124 gen_goto_tb(ctx, 0, ctx->btarget);
12125 }
12126 break;
12127 case MIPS_HFLAG_BR:
12128 /* unconditional branch to register */
12129 if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) {
12130 TCGv t0 = tcg_temp_new();
12131 TCGv_i32 t1 = tcg_temp_new_i32();
12132
12133 tcg_gen_andi_tl(t0, btarget, 0x1);
12134 tcg_gen_trunc_tl_i32(t1, t0);
12135 tcg_temp_free(t0);
12136 tcg_gen_andi_i32(hflags, hflags, ~(uint32_t)MIPS_HFLAG_M16);
12137 tcg_gen_shli_i32(t1, t1, MIPS_HFLAG_M16_SHIFT);
12138 tcg_gen_or_i32(hflags, hflags, t1);
12139 tcg_temp_free_i32(t1);
12140
12141 tcg_gen_andi_tl(cpu_PC, btarget, ~(target_ulong)0x1);
12142 } else {
12143 tcg_gen_mov_tl(cpu_PC, btarget);
12144 }
12145 if (ctx->base.singlestep_enabled) {
12146 save_cpu_state(ctx, 0);
12147 gen_helper_raise_exception_debug(cpu_env);
12148 }
12149 tcg_gen_lookup_and_goto_ptr();
12150 break;
12151 default:
12152 fprintf(stderr, "unknown branch 0x%x\n", proc_hflags);
12153 abort();
12154 }
12155 }
12156 }
12157
12158 /* Compact Branches */
12159 static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
12160 int rs, int rt, int32_t offset)
12161 {
12162 int bcond_compute = 0;
12163 TCGv t0 = tcg_temp_new();
12164 TCGv t1 = tcg_temp_new();
12165 int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0;
12166
12167 if (ctx->hflags & MIPS_HFLAG_BMASK) {
12168 #ifdef MIPS_DEBUG_DISAS
12169 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
12170 "\n", ctx->base.pc_next);
12171 #endif
12172 gen_reserved_instruction(ctx);
12173 goto out;
12174 }
12175
12176 /* Load needed operands and calculate btarget */
12177 switch (opc) {
12178 /* compact branch */
12179 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */
12180 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
12181 gen_load_gpr(t0, rs);
12182 gen_load_gpr(t1, rt);
12183 bcond_compute = 1;
12184 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
12185 if (rs <= rt && rs == 0) {
12186 /* OPC_BEQZALC, OPC_BNEZALC */
12187 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
12188 }
12189 break;
12190 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
12191 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */
12192 gen_load_gpr(t0, rs);
12193 gen_load_gpr(t1, rt);
12194 bcond_compute = 1;
12195 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
12196 break;
12197 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
12198 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
12199 if (rs == 0 || rs == rt) {
12200 /* OPC_BLEZALC, OPC_BGEZALC */
12201 /* OPC_BGTZALC, OPC_BLTZALC */
12202 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
12203 }
12204 gen_load_gpr(t0, rs);
12205 gen_load_gpr(t1, rt);
12206 bcond_compute = 1;
12207 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
12208 break;
12209 case OPC_BC:
12210 case OPC_BALC:
12211 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
12212 break;
12213 case OPC_BEQZC:
12214 case OPC_BNEZC:
12215 if (rs != 0) {
12216 /* OPC_BEQZC, OPC_BNEZC */
12217 gen_load_gpr(t0, rs);
12218 bcond_compute = 1;
12219 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
12220 } else {
12221 /* OPC_JIC, OPC_JIALC */
12222 TCGv tbase = tcg_temp_new();
12223 TCGv toffset = tcg_temp_new();
12224
12225 gen_load_gpr(tbase, rt);
12226 tcg_gen_movi_tl(toffset, offset);
12227 gen_op_addr_add(ctx, btarget, tbase, toffset);
12228 tcg_temp_free(tbase);
12229 tcg_temp_free(toffset);
12230 }
12231 break;
12232 default:
12233 MIPS_INVAL("Compact branch/jump");
12234 gen_reserved_instruction(ctx);
12235 goto out;
12236 }
12237
12238 if (bcond_compute == 0) {
12239 /* Uncoditional compact branch */
12240 switch (opc) {
12241 case OPC_JIALC:
12242 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
12243 /* Fallthrough */
12244 case OPC_JIC:
12245 ctx->hflags |= MIPS_HFLAG_BR;
12246 break;
12247 case OPC_BALC:
12248 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
12249 /* Fallthrough */
12250 case OPC_BC:
12251 ctx->hflags |= MIPS_HFLAG_B;
12252 break;
12253 default:
12254 MIPS_INVAL("Compact branch/jump");
12255 gen_reserved_instruction(ctx);
12256 goto out;
12257 }
12258
12259 /* Generating branch here as compact branches don't have delay slot */
12260 gen_branch(ctx, 4);
12261 } else {
12262 /* Conditional compact branch */
12263 TCGLabel *fs = gen_new_label();
12264 save_cpu_state(ctx, 0);
12265
12266 switch (opc) {
12267 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
12268 if (rs == 0 && rt != 0) {
12269 /* OPC_BLEZALC */
12270 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
12271 } else if (rs != 0 && rt != 0 && rs == rt) {
12272 /* OPC_BGEZALC */
12273 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
12274 } else {
12275 /* OPC_BGEUC */
12276 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs);
12277 }
12278 break;
12279 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
12280 if (rs == 0 && rt != 0) {
12281 /* OPC_BGTZALC */
12282 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
12283 } else if (rs != 0 && rt != 0 && rs == rt) {
12284 /* OPC_BLTZALC */
12285 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
12286 } else {
12287 /* OPC_BLTUC */
12288 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs);
12289 }
12290 break;
12291 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
12292 if (rs == 0 && rt != 0) {
12293 /* OPC_BLEZC */
12294 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
12295 } else if (rs != 0 && rt != 0 && rs == rt) {
12296 /* OPC_BGEZC */
12297 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
12298 } else {
12299 /* OPC_BGEC */
12300 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs);
12301 }
12302 break;
12303 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */
12304 if (rs == 0 && rt != 0) {
12305 /* OPC_BGTZC */
12306 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
12307 } else if (rs != 0 && rt != 0 && rs == rt) {
12308 /* OPC_BLTZC */
12309 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
12310 } else {
12311 /* OPC_BLTC */
12312 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs);
12313 }
12314 break;
12315 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */
12316 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
12317 if (rs >= rt) {
12318 /* OPC_BOVC, OPC_BNVC */
12319 TCGv t2 = tcg_temp_new();
12320 TCGv t3 = tcg_temp_new();
12321 TCGv t4 = tcg_temp_new();
12322 TCGv input_overflow = tcg_temp_new();
12323
12324 gen_load_gpr(t0, rs);
12325 gen_load_gpr(t1, rt);
12326 tcg_gen_ext32s_tl(t2, t0);
12327 tcg_gen_setcond_tl(TCG_COND_NE, input_overflow, t2, t0);
12328 tcg_gen_ext32s_tl(t3, t1);
12329 tcg_gen_setcond_tl(TCG_COND_NE, t4, t3, t1);
12330 tcg_gen_or_tl(input_overflow, input_overflow, t4);
12331
12332 tcg_gen_add_tl(t4, t2, t3);
12333 tcg_gen_ext32s_tl(t4, t4);
12334 tcg_gen_xor_tl(t2, t2, t3);
12335 tcg_gen_xor_tl(t3, t4, t3);
12336 tcg_gen_andc_tl(t2, t3, t2);
12337 tcg_gen_setcondi_tl(TCG_COND_LT, t4, t2, 0);
12338 tcg_gen_or_tl(t4, t4, input_overflow);
12339 if (opc == OPC_BOVC) {
12340 /* OPC_BOVC */
12341 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t4, 0, fs);
12342 } else {
12343 /* OPC_BNVC */
12344 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t4, 0, fs);
12345 }
12346 tcg_temp_free(input_overflow);
12347 tcg_temp_free(t4);
12348 tcg_temp_free(t3);
12349 tcg_temp_free(t2);
12350 } else if (rs < rt && rs == 0) {
12351 /* OPC_BEQZALC, OPC_BNEZALC */
12352 if (opc == OPC_BEQZALC) {
12353 /* OPC_BEQZALC */
12354 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t1, 0, fs);
12355 } else {
12356 /* OPC_BNEZALC */
12357 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t1, 0, fs);
12358 }
12359 } else {
12360 /* OPC_BEQC, OPC_BNEC */
12361 if (opc == OPC_BEQC) {
12362 /* OPC_BEQC */
12363 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs);
12364 } else {
12365 /* OPC_BNEC */
12366 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs);
12367 }
12368 }
12369 break;
12370 case OPC_BEQZC:
12371 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t0, 0, fs);
12372 break;
12373 case OPC_BNEZC:
12374 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t0, 0, fs);
12375 break;
12376 default:
12377 MIPS_INVAL("Compact conditional branch/jump");
12378 gen_reserved_instruction(ctx);
12379 goto out;
12380 }
12381
12382 /* Generating branch here as compact branches don't have delay slot */
12383 gen_goto_tb(ctx, 1, ctx->btarget);
12384 gen_set_label(fs);
12385
12386 ctx->hflags |= MIPS_HFLAG_FBNSLOT;
12387 }
12388
12389 out:
12390 tcg_temp_free(t0);
12391 tcg_temp_free(t1);
12392 }
12393
12394 /* ISA extensions (ASEs) */
12395 /* MIPS16 extension to MIPS32 */
12396
12397 /* MIPS16 major opcodes */
12398 enum {
12399 M16_OPC_ADDIUSP = 0x00,
12400 M16_OPC_ADDIUPC = 0x01,
12401 M16_OPC_B = 0x02,
12402 M16_OPC_JAL = 0x03,
12403 M16_OPC_BEQZ = 0x04,
12404 M16_OPC_BNEQZ = 0x05,
12405 M16_OPC_SHIFT = 0x06,
12406 M16_OPC_LD = 0x07,
12407 M16_OPC_RRIA = 0x08,
12408 M16_OPC_ADDIU8 = 0x09,
12409 M16_OPC_SLTI = 0x0a,
12410 M16_OPC_SLTIU = 0x0b,
12411 M16_OPC_I8 = 0x0c,
12412 M16_OPC_LI = 0x0d,
12413 M16_OPC_CMPI = 0x0e,
12414 M16_OPC_SD = 0x0f,
12415 M16_OPC_LB = 0x10,
12416 M16_OPC_LH = 0x11,
12417 M16_OPC_LWSP = 0x12,
12418 M16_OPC_LW = 0x13,
12419 M16_OPC_LBU = 0x14,
12420 M16_OPC_LHU = 0x15,
12421 M16_OPC_LWPC = 0x16,
12422 M16_OPC_LWU = 0x17,
12423 M16_OPC_SB = 0x18,
12424 M16_OPC_SH = 0x19,
12425 M16_OPC_SWSP = 0x1a,
12426 M16_OPC_SW = 0x1b,
12427 M16_OPC_RRR = 0x1c,
12428 M16_OPC_RR = 0x1d,
12429 M16_OPC_EXTEND = 0x1e,
12430 M16_OPC_I64 = 0x1f
12431 };
12432
12433 /* I8 funct field */
12434 enum {
12435 I8_BTEQZ = 0x0,
12436 I8_BTNEZ = 0x1,
12437 I8_SWRASP = 0x2,
12438 I8_ADJSP = 0x3,
12439 I8_SVRS = 0x4,
12440 I8_MOV32R = 0x5,
12441 I8_MOVR32 = 0x7
12442 };
12443
12444 /* RRR f field */
12445 enum {
12446 RRR_DADDU = 0x0,
12447 RRR_ADDU = 0x1,
12448 RRR_DSUBU = 0x2,
12449 RRR_SUBU = 0x3
12450 };
12451
12452 /* RR funct field */
12453 enum {
12454 RR_JR = 0x00,
12455 RR_SDBBP = 0x01,
12456 RR_SLT = 0x02,
12457 RR_SLTU = 0x03,
12458 RR_SLLV = 0x04,
12459 RR_BREAK = 0x05,
12460 RR_SRLV = 0x06,
12461 RR_SRAV = 0x07,
12462 RR_DSRL = 0x08,
12463 RR_CMP = 0x0a,
12464 RR_NEG = 0x0b,
12465 RR_AND = 0x0c,
12466 RR_OR = 0x0d,
12467 RR_XOR = 0x0e,
12468 RR_NOT = 0x0f,
12469 RR_MFHI = 0x10,
12470 RR_CNVT = 0x11,
12471 RR_MFLO = 0x12,
12472 RR_DSRA = 0x13,
12473 RR_DSLLV = 0x14,
12474 RR_DSRLV = 0x16,
12475 RR_DSRAV = 0x17,
12476 RR_MULT = 0x18,
12477 RR_MULTU = 0x19,
12478 RR_DIV = 0x1a,
12479 RR_DIVU = 0x1b,
12480 RR_DMULT = 0x1c,
12481 RR_DMULTU = 0x1d,
12482 RR_DDIV = 0x1e,
12483 RR_DDIVU = 0x1f
12484 };
12485
12486 /* I64 funct field */
12487 enum {
12488 I64_LDSP = 0x0,
12489 I64_SDSP = 0x1,
12490 I64_SDRASP = 0x2,
12491 I64_DADJSP = 0x3,
12492 I64_LDPC = 0x4,
12493 I64_DADDIU5 = 0x5,
12494 I64_DADDIUPC = 0x6,
12495 I64_DADDIUSP = 0x7
12496 };
12497
12498 /* RR ry field for CNVT */
12499 enum {
12500 RR_RY_CNVT_ZEB = 0x0,
12501 RR_RY_CNVT_ZEH = 0x1,
12502 RR_RY_CNVT_ZEW = 0x2,
12503 RR_RY_CNVT_SEB = 0x4,
12504 RR_RY_CNVT_SEH = 0x5,
12505 RR_RY_CNVT_SEW = 0x6,
12506 };
12507
12508 static int xlat(int r)
12509 {
12510 static int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
12511
12512 return map[r];
12513 }
12514
12515 static void gen_mips16_save(DisasContext *ctx,
12516 int xsregs, int aregs,
12517 int do_ra, int do_s0, int do_s1,
12518 int framesize)
12519 {
12520 TCGv t0 = tcg_temp_new();
12521 TCGv t1 = tcg_temp_new();
12522 TCGv t2 = tcg_temp_new();
12523 int args, astatic;
12524
12525 switch (aregs) {
12526 case 0:
12527 case 1:
12528 case 2:
12529 case 3:
12530 case 11:
12531 args = 0;
12532 break;
12533 case 4:
12534 case 5:
12535 case 6:
12536 case 7:
12537 args = 1;
12538 break;
12539 case 8:
12540 case 9:
12541 case 10:
12542 args = 2;
12543 break;
12544 case 12:
12545 case 13:
12546 args = 3;
12547 break;
12548 case 14:
12549 args = 4;
12550 break;
12551 default:
12552 gen_reserved_instruction(ctx);
12553 return;
12554 }
12555
12556 switch (args) {
12557 case 4:
12558 gen_base_offset_addr(ctx, t0, 29, 12);
12559 gen_load_gpr(t1, 7);
12560 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
12561 /* Fall through */
12562 case 3:
12563 gen_base_offset_addr(ctx, t0, 29, 8);
12564 gen_load_gpr(t1, 6);
12565 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
12566 /* Fall through */
12567 case 2:
12568 gen_base_offset_addr(ctx, t0, 29, 4);
12569 gen_load_gpr(t1, 5);
12570 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
12571 /* Fall through */
12572 case 1:
12573 gen_base_offset_addr(ctx, t0, 29, 0);
12574 gen_load_gpr(t1, 4);
12575 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
12576 }
12577
12578 gen_load_gpr(t0, 29);
12579
12580 #define DECR_AND_STORE(reg) do { \
12581 tcg_gen_movi_tl(t2, -4); \
12582 gen_op_addr_add(ctx, t0, t0, t2); \
12583 gen_load_gpr(t1, reg); \
12584 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); \
12585 } while (0)
12586
12587 if (do_ra) {
12588 DECR_AND_STORE(31);
12589 }
12590
12591 switch (xsregs) {
12592 case 7:
12593 DECR_AND_STORE(30);
12594 /* Fall through */
12595 case 6:
12596 DECR_AND_STORE(23);
12597 /* Fall through */
12598 case 5:
12599 DECR_AND_STORE(22);
12600 /* Fall through */
12601 case 4:
12602 DECR_AND_STORE(21);
12603 /* Fall through */
12604 case 3:
12605 DECR_AND_STORE(20);
12606 /* Fall through */
12607 case 2:
12608 DECR_AND_STORE(19);
12609 /* Fall through */
12610 case 1:
12611 DECR_AND_STORE(18);
12612 }
12613
12614 if (do_s1) {
12615 DECR_AND_STORE(17);
12616 }
12617 if (do_s0) {
12618 DECR_AND_STORE(16);
12619 }
12620
12621 switch (aregs) {
12622 case 0:
12623 case 4:
12624 case 8:
12625 case 12:
12626 case 14:
12627 astatic = 0;
12628 break;
12629 case 1:
12630 case 5:
12631 case 9:
12632 case 13:
12633 astatic = 1;
12634 break;
12635 case 2:
12636 case 6:
12637 case 10:
12638 astatic = 2;
12639 break;
12640 case 3:
12641 case 7:
12642 astatic = 3;
12643 break;
12644 case 11:
12645 astatic = 4;
12646 break;
12647 default:
12648 gen_reserved_instruction(ctx);
12649 return;
12650 }
12651
12652 if (astatic > 0) {
12653 DECR_AND_STORE(7);
12654 if (astatic > 1) {
12655 DECR_AND_STORE(6);
12656 if (astatic > 2) {
12657 DECR_AND_STORE(5);
12658 if (astatic > 3) {
12659 DECR_AND_STORE(4);
12660 }
12661 }
12662 }
12663 }
12664 #undef DECR_AND_STORE
12665
12666 tcg_gen_movi_tl(t2, -framesize);
12667 gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
12668 tcg_temp_free(t0);
12669 tcg_temp_free(t1);
12670 tcg_temp_free(t2);
12671 }
12672
12673 static void gen_mips16_restore(DisasContext *ctx,
12674 int xsregs, int aregs,
12675 int do_ra, int do_s0, int do_s1,
12676 int framesize)
12677 {
12678 int astatic;
12679 TCGv t0 = tcg_temp_new();
12680 TCGv t1 = tcg_temp_new();
12681 TCGv t2 = tcg_temp_new();
12682
12683 tcg_gen_movi_tl(t2, framesize);
12684 gen_op_addr_add(ctx, t0, cpu_gpr[29], t2);
12685
12686 #define DECR_AND_LOAD(reg) do { \
12687 tcg_gen_movi_tl(t2, -4); \
12688 gen_op_addr_add(ctx, t0, t0, t2); \
12689 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); \
12690 gen_store_gpr(t1, reg); \
12691 } while (0)
12692
12693 if (do_ra) {
12694 DECR_AND_LOAD(31);
12695 }
12696
12697 switch (xsregs) {
12698 case 7:
12699 DECR_AND_LOAD(30);
12700 /* Fall through */
12701 case 6:
12702 DECR_AND_LOAD(23);
12703 /* Fall through */
12704 case 5:
12705 DECR_AND_LOAD(22);
12706 /* Fall through */
12707 case 4:
12708 DECR_AND_LOAD(21);
12709 /* Fall through */
12710 case 3:
12711 DECR_AND_LOAD(20);
12712 /* Fall through */
12713 case 2:
12714 DECR_AND_LOAD(19);
12715 /* Fall through */
12716 case 1:
12717 DECR_AND_LOAD(18);
12718 }
12719
12720 if (do_s1) {
12721 DECR_AND_LOAD(17);
12722 }
12723 if (do_s0) {
12724 DECR_AND_LOAD(16);
12725 }
12726
12727 switch (aregs) {
12728 case 0:
12729 case 4:
12730 case 8:
12731 case 12:
12732 case 14:
12733 astatic = 0;
12734 break;
12735 case 1:
12736 case 5:
12737 case 9:
12738 case 13:
12739 astatic = 1;
12740 break;
12741 case 2:
12742 case 6:
12743 case 10:
12744 astatic = 2;
12745 break;
12746 case 3:
12747 case 7:
12748 astatic = 3;
12749 break;
12750 case 11:
12751 astatic = 4;
12752 break;
12753 default:
12754 gen_reserved_instruction(ctx);
12755 return;
12756 }
12757
12758 if (astatic > 0) {
12759 DECR_AND_LOAD(7);
12760 if (astatic > 1) {
12761 DECR_AND_LOAD(6);
12762 if (astatic > 2) {
12763 DECR_AND_LOAD(5);
12764 if (astatic > 3) {
12765 DECR_AND_LOAD(4);
12766 }
12767 }
12768 }
12769 }
12770 #undef DECR_AND_LOAD
12771
12772 tcg_gen_movi_tl(t2, framesize);
12773 gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
12774 tcg_temp_free(t0);
12775 tcg_temp_free(t1);
12776 tcg_temp_free(t2);
12777 }
12778
12779 static void gen_addiupc(DisasContext *ctx, int rx, int imm,
12780 int is_64_bit, int extended)
12781 {
12782 TCGv t0;
12783
12784 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
12785 gen_reserved_instruction(ctx);
12786 return;
12787 }
12788
12789 t0 = tcg_temp_new();
12790
12791 tcg_gen_movi_tl(t0, pc_relative_pc(ctx));
12792 tcg_gen_addi_tl(cpu_gpr[rx], t0, imm);
12793 if (!is_64_bit) {
12794 tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
12795 }
12796
12797 tcg_temp_free(t0);
12798 }
12799
12800 static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
12801 int16_t offset)
12802 {
12803 TCGv_i32 t0 = tcg_const_i32(op);
12804 TCGv t1 = tcg_temp_new();
12805 gen_base_offset_addr(ctx, t1, base, offset);
12806 gen_helper_cache(cpu_env, t1, t0);
12807 }
12808
12809 #if defined(TARGET_MIPS64)
12810 static void decode_i64_mips16(DisasContext *ctx,
12811 int ry, int funct, int16_t offset,
12812 int extended)
12813 {
12814 switch (funct) {
12815 case I64_LDSP:
12816 check_insn(ctx, ISA_MIPS3);
12817 check_mips_64(ctx);
12818 offset = extended ? offset : offset << 3;
12819 gen_ld(ctx, OPC_LD, ry, 29, offset);
12820 break;
12821 case I64_SDSP:
12822 check_insn(ctx, ISA_MIPS3);
12823 check_mips_64(ctx);
12824 offset = extended ? offset : offset << 3;
12825 gen_st(ctx, OPC_SD, ry, 29, offset);
12826 break;
12827 case I64_SDRASP:
12828 check_insn(ctx, ISA_MIPS3);
12829 check_mips_64(ctx);
12830 offset = extended ? offset : (ctx->opcode & 0xff) << 3;
12831 gen_st(ctx, OPC_SD, 31, 29, offset);
12832 break;
12833 case I64_DADJSP:
12834 check_insn(ctx, ISA_MIPS3);
12835 check_mips_64(ctx);
12836 offset = extended ? offset : ((int8_t)ctx->opcode) << 3;
12837 gen_arith_imm(ctx, OPC_DADDIU, 29, 29, offset);
12838 break;
12839 case I64_LDPC:
12840 check_insn(ctx, ISA_MIPS3);
12841 check_mips_64(ctx);
12842 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
12843 gen_reserved_instruction(ctx);
12844 } else {
12845 offset = extended ? offset : offset << 3;
12846 gen_ld(ctx, OPC_LDPC, ry, 0, offset);
12847 }
12848 break;
12849 case I64_DADDIU5:
12850 check_insn(ctx, ISA_MIPS3);
12851 check_mips_64(ctx);
12852 offset = extended ? offset : ((int8_t)(offset << 3)) >> 3;
12853 gen_arith_imm(ctx, OPC_DADDIU, ry, ry, offset);
12854 break;
12855 case I64_DADDIUPC:
12856 check_insn(ctx, ISA_MIPS3);
12857 check_mips_64(ctx);
12858 offset = extended ? offset : offset << 2;
12859 gen_addiupc(ctx, ry, offset, 1, extended);
12860 break;
12861 case I64_DADDIUSP:
12862 check_insn(ctx, ISA_MIPS3);
12863 check_mips_64(ctx);
12864 offset = extended ? offset : offset << 2;
12865 gen_arith_imm(ctx, OPC_DADDIU, ry, 29, offset);
12866 break;
12867 }
12868 }
12869 #endif
12870
12871 static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
12872 {
12873 int extend = translator_lduw(env, ctx->base.pc_next + 2);
12874 int op, rx, ry, funct, sa;
12875 int16_t imm, offset;
12876
12877 ctx->opcode = (ctx->opcode << 16) | extend;
12878 op = (ctx->opcode >> 11) & 0x1f;
12879 sa = (ctx->opcode >> 22) & 0x1f;
12880 funct = (ctx->opcode >> 8) & 0x7;
12881 rx = xlat((ctx->opcode >> 8) & 0x7);
12882 ry = xlat((ctx->opcode >> 5) & 0x7);
12883 offset = imm = (int16_t) (((ctx->opcode >> 16) & 0x1f) << 11
12884 | ((ctx->opcode >> 21) & 0x3f) << 5
12885 | (ctx->opcode & 0x1f));
12886
12887 /*
12888 * The extended opcodes cleverly reuse the opcodes from their 16-bit
12889 * counterparts.
12890 */
12891 switch (op) {
12892 case M16_OPC_ADDIUSP:
12893 gen_arith_imm(ctx, OPC_ADDIU, rx, 29, imm);
12894 break;
12895 case M16_OPC_ADDIUPC:
12896 gen_addiupc(ctx, rx, imm, 0, 1);
12897 break;
12898 case M16_OPC_B:
12899 gen_compute_branch(ctx, OPC_BEQ, 4, 0, 0, offset << 1, 0);
12900 /* No delay slot, so just process as a normal instruction */
12901 break;
12902 case M16_OPC_BEQZ:
12903 gen_compute_branch(ctx, OPC_BEQ, 4, rx, 0, offset << 1, 0);
12904 /* No delay slot, so just process as a normal instruction */
12905 break;
12906 case M16_OPC_BNEQZ:
12907 gen_compute_branch(ctx, OPC_BNE, 4, rx, 0, offset << 1, 0);
12908 /* No delay slot, so just process as a normal instruction */
12909 break;
12910 case M16_OPC_SHIFT:
12911 switch (ctx->opcode & 0x3) {
12912 case 0x0:
12913 gen_shift_imm(ctx, OPC_SLL, rx, ry, sa);
12914 break;
12915 case 0x1:
12916 #if defined(TARGET_MIPS64)
12917 check_mips_64(ctx);
12918 gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa);
12919 #else
12920 gen_reserved_instruction(ctx);
12921 #endif
12922 break;
12923 case 0x2:
12924 gen_shift_imm(ctx, OPC_SRL, rx, ry, sa);
12925 break;
12926 case 0x3:
12927 gen_shift_imm(ctx, OPC_SRA, rx, ry, sa);
12928 break;
12929 }
12930 break;
12931 #if defined(TARGET_MIPS64)
12932 case M16_OPC_LD:
12933 check_insn(ctx, ISA_MIPS3);
12934 check_mips_64(ctx);
12935 gen_ld(ctx, OPC_LD, ry, rx, offset);
12936 break;
12937 #endif
12938 case M16_OPC_RRIA:
12939 imm = ctx->opcode & 0xf;
12940 imm = imm | ((ctx->opcode >> 20) & 0x7f) << 4;
12941 imm = imm | ((ctx->opcode >> 16) & 0xf) << 11;
12942 imm = (int16_t) (imm << 1) >> 1;
12943 if ((ctx->opcode >> 4) & 0x1) {
12944 #if defined(TARGET_MIPS64)
12945 check_mips_64(ctx);
12946 gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm);
12947 #else
12948 gen_reserved_instruction(ctx);
12949 #endif
12950 } else {
12951 gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm);
12952 }
12953 break;
12954 case M16_OPC_ADDIU8:
12955 gen_arith_imm(ctx, OPC_ADDIU, rx, rx, imm);
12956 break;
12957 case M16_OPC_SLTI:
12958 gen_slt_imm(ctx, OPC_SLTI, 24, rx, imm);
12959 break;
12960 case M16_OPC_SLTIU:
12961 gen_slt_imm(ctx, OPC_SLTIU, 24, rx, imm);
12962 break;
12963 case M16_OPC_I8:
12964 switch (funct) {
12965 case I8_BTEQZ:
12966 gen_compute_branch(ctx, OPC_BEQ, 4, 24, 0, offset << 1, 0);
12967 break;
12968 case I8_BTNEZ:
12969 gen_compute_branch(ctx, OPC_BNE, 4, 24, 0, offset << 1, 0);
12970 break;
12971 case I8_SWRASP:
12972 gen_st(ctx, OPC_SW, 31, 29, imm);
12973 break;
12974 case I8_ADJSP:
12975 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm);
12976 break;
12977 case I8_SVRS:
12978 check_insn(ctx, ISA_MIPS_R1);
12979 {
12980 int xsregs = (ctx->opcode >> 24) & 0x7;
12981 int aregs = (ctx->opcode >> 16) & 0xf;
12982 int do_ra = (ctx->opcode >> 6) & 0x1;
12983 int do_s0 = (ctx->opcode >> 5) & 0x1;
12984 int do_s1 = (ctx->opcode >> 4) & 0x1;
12985 int framesize = (((ctx->opcode >> 20) & 0xf) << 4
12986 | (ctx->opcode & 0xf)) << 3;
12987
12988 if (ctx->opcode & (1 << 7)) {
12989 gen_mips16_save(ctx, xsregs, aregs,
12990 do_ra, do_s0, do_s1,
12991 framesize);
12992 } else {
12993 gen_mips16_restore(ctx, xsregs, aregs,
12994 do_ra, do_s0, do_s1,
12995 framesize);
12996 }
12997 }
12998 break;
12999 default:
13000 gen_reserved_instruction(ctx);
13001 break;
13002 }
13003 break;
13004 case M16_OPC_LI:
13005 tcg_gen_movi_tl(cpu_gpr[rx], (uint16_t) imm);
13006 break;
13007 case M16_OPC_CMPI:
13008 tcg_gen_xori_tl(cpu_gpr[24], cpu_gpr[rx], (uint16_t) imm);
13009 break;
13010 #if defined(TARGET_MIPS64)
13011 case M16_OPC_SD:
13012 check_insn(ctx, ISA_MIPS3);
13013 check_mips_64(ctx);
13014 gen_st(ctx, OPC_SD, ry, rx, offset);
13015 break;
13016 #endif
13017 case M16_OPC_LB:
13018 gen_ld(ctx, OPC_LB, ry, rx, offset);
13019 break;
13020 case M16_OPC_LH:
13021 gen_ld(ctx, OPC_LH, ry, rx, offset);
13022 break;
13023 case M16_OPC_LWSP:
13024 gen_ld(ctx, OPC_LW, rx, 29, offset);
13025 break;
13026 case M16_OPC_LW:
13027 gen_ld(ctx, OPC_LW, ry, rx, offset);
13028 break;
13029 case M16_OPC_LBU:
13030 gen_ld(ctx, OPC_LBU, ry, rx, offset);
13031 break;
13032 case M16_OPC_LHU:
13033 gen_ld(ctx, OPC_LHU, ry, rx, offset);
13034 break;
13035 case M16_OPC_LWPC:
13036 gen_ld(ctx, OPC_LWPC, rx, 0, offset);
13037 break;
13038 #if defined(TARGET_MIPS64)
13039 case M16_OPC_LWU:
13040 check_insn(ctx, ISA_MIPS3);
13041 check_mips_64(ctx);
13042 gen_ld(ctx, OPC_LWU, ry, rx, offset);
13043 break;
13044 #endif
13045 case M16_OPC_SB:
13046 gen_st(ctx, OPC_SB, ry, rx, offset);
13047 break;
13048 case M16_OPC_SH:
13049 gen_st(ctx, OPC_SH, ry, rx, offset);
13050 break;
13051 case M16_OPC_SWSP:
13052 gen_st(ctx, OPC_SW, rx, 29, offset);
13053 break;
13054 case M16_OPC_SW:
13055 gen_st(ctx, OPC_SW, ry, rx, offset);
13056 break;
13057 #if defined(TARGET_MIPS64)
13058 case M16_OPC_I64:
13059 decode_i64_mips16(ctx, ry, funct, offset, 1);
13060 break;
13061 #endif
13062 default:
13063 gen_reserved_instruction(ctx);
13064 break;
13065 }
13066
13067 return 4;
13068 }
13069
13070 static inline bool is_uhi(int sdbbp_code)
13071 {
13072 #ifdef CONFIG_USER_ONLY
13073 return false;
13074 #else
13075 return semihosting_enabled() && sdbbp_code == 1;
13076 #endif
13077 }
13078
13079 #ifdef CONFIG_USER_ONLY
13080 /* The above should dead-code away any calls to this..*/
13081 static inline void gen_helper_do_semihosting(void *env)
13082 {
13083 g_assert_not_reached();
13084 }
13085 #endif
13086
13087 static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
13088 {
13089 int rx, ry;
13090 int sa;
13091 int op, cnvt_op, op1, offset;
13092 int funct;
13093 int n_bytes;
13094
13095 op = (ctx->opcode >> 11) & 0x1f;
13096 sa = (ctx->opcode >> 2) & 0x7;
13097 sa = sa == 0 ? 8 : sa;
13098 rx = xlat((ctx->opcode >> 8) & 0x7);
13099 cnvt_op = (ctx->opcode >> 5) & 0x7;
13100 ry = xlat((ctx->opcode >> 5) & 0x7);
13101 op1 = offset = ctx->opcode & 0x1f;
13102
13103 n_bytes = 2;
13104
13105 switch (op) {
13106 case M16_OPC_ADDIUSP:
13107 {
13108 int16_t imm = ((uint8_t) ctx->opcode) << 2;
13109
13110 gen_arith_imm(ctx, OPC_ADDIU, rx, 29, imm);
13111 }
13112 break;
13113 case M16_OPC_ADDIUPC:
13114 gen_addiupc(ctx, rx, ((uint8_t) ctx->opcode) << 2, 0, 0);
13115 break;
13116 case M16_OPC_B:
13117 offset = (ctx->opcode & 0x7ff) << 1;
13118 offset = (int16_t)(offset << 4) >> 4;
13119 gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, offset, 0);
13120 /* No delay slot, so just process as a normal instruction */
13121 break;
13122 case M16_OPC_JAL:
13123 offset = translator_lduw(env, ctx->base.pc_next + 2);
13124 offset = (((ctx->opcode & 0x1f) << 21)
13125 | ((ctx->opcode >> 5) & 0x1f) << 16
13126 | offset) << 2;
13127 op = ((ctx->opcode >> 10) & 0x1) ? OPC_JALX : OPC_JAL;
13128 gen_compute_branch(ctx, op, 4, rx, ry, offset, 2);
13129 n_bytes = 4;
13130 break;
13131 case M16_OPC_BEQZ:
13132 gen_compute_branch(ctx, OPC_BEQ, 2, rx, 0,
13133 ((int8_t)ctx->opcode) << 1, 0);
13134 /* No delay slot, so just process as a normal instruction */
13135 break;
13136 case M16_OPC_BNEQZ:
13137 gen_compute_branch(ctx, OPC_BNE, 2, rx, 0,
13138 ((int8_t)ctx->opcode) << 1, 0);
13139 /* No delay slot, so just process as a normal instruction */
13140 break;
13141 case M16_OPC_SHIFT:
13142 switch (ctx->opcode & 0x3) {
13143 case 0x0:
13144 gen_shift_imm(ctx, OPC_SLL, rx, ry, sa);
13145 break;
13146 case 0x1:
13147 #if defined(TARGET_MIPS64)
13148 check_insn(ctx, ISA_MIPS3);
13149 check_mips_64(ctx);
13150 gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa);
13151 #else
13152 gen_reserved_instruction(ctx);
13153 #endif
13154 break;
13155 case 0x2:
13156 gen_shift_imm(ctx, OPC_SRL, rx, ry, sa);
13157 break;
13158 case 0x3:
13159 gen_shift_imm(ctx, OPC_SRA, rx, ry, sa);
13160 break;
13161 }
13162 break;
13163 #if defined(TARGET_MIPS64)
13164 case M16_OPC_LD:
13165 check_insn(ctx, ISA_MIPS3);
13166 check_mips_64(ctx);
13167 gen_ld(ctx, OPC_LD, ry, rx, offset << 3);
13168 break;
13169 #endif
13170 case M16_OPC_RRIA:
13171 {
13172 int16_t imm = (int8_t)((ctx->opcode & 0xf) << 4) >> 4;
13173
13174 if ((ctx->opcode >> 4) & 1) {
13175 #if defined(TARGET_MIPS64)
13176 check_insn(ctx, ISA_MIPS3);
13177 check_mips_64(ctx);
13178 gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm);
13179 #else
13180 gen_reserved_instruction(ctx);
13181 #endif
13182 } else {
13183 gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm);
13184 }
13185 }
13186 break;
13187 case M16_OPC_ADDIU8:
13188 {
13189 int16_t imm = (int8_t) ctx->opcode;
13190
13191 gen_arith_imm(ctx, OPC_ADDIU, rx, rx, imm);
13192 }
13193 break;
13194 case M16_OPC_SLTI:
13195 {
13196 int16_t imm = (uint8_t) ctx->opcode;
13197 gen_slt_imm(ctx, OPC_SLTI, 24, rx, imm);
13198 }
13199 break;
13200 case M16_OPC_SLTIU:
13201 {
13202 int16_t imm = (uint8_t) ctx->opcode;
13203 gen_slt_imm(ctx, OPC_SLTIU, 24, rx, imm);
13204 }
13205 break;
13206 case M16_OPC_I8:
13207 {
13208 int reg32;
13209
13210 funct = (ctx->opcode >> 8) & 0x7;
13211 switch (funct) {
13212 case I8_BTEQZ:
13213 gen_compute_branch(ctx, OPC_BEQ, 2, 24, 0,
13214 ((int8_t)ctx->opcode) << 1, 0);
13215 break;
13216 case I8_BTNEZ:
13217 gen_compute_branch(ctx, OPC_BNE, 2, 24, 0,
13218 ((int8_t)ctx->opcode) << 1, 0);
13219 break;
13220 case I8_SWRASP:
13221 gen_st(ctx, OPC_SW, 31, 29, (ctx->opcode & 0xff) << 2);
13222 break;
13223 case I8_ADJSP:
13224 gen_arith_imm(ctx, OPC_ADDIU, 29, 29,
13225 ((int8_t)ctx->opcode) << 3);
13226 break;
13227 case I8_SVRS:
13228 check_insn(ctx, ISA_MIPS_R1);
13229 {
13230 int do_ra = ctx->opcode & (1 << 6);
13231 int do_s0 = ctx->opcode & (1 << 5);
13232 int do_s1 = ctx->opcode & (1 << 4);
13233 int framesize = ctx->opcode & 0xf;
13234
13235 if (framesize == 0) {
13236 framesize = 128;
13237 } else {
13238 framesize = framesize << 3;
13239 }
13240
13241 if (ctx->opcode & (1 << 7)) {
13242 gen_mips16_save(ctx, 0, 0,
13243 do_ra, do_s0, do_s1, framesize);
13244 } else {
13245 gen_mips16_restore(ctx, 0, 0,
13246 do_ra, do_s0, do_s1, framesize);
13247 }
13248 }
13249 break;
13250 case I8_MOV32R:
13251 {
13252 int rz = xlat(ctx->opcode & 0x7);
13253
13254 reg32 = (((ctx->opcode >> 3) & 0x3) << 3) |
13255 ((ctx->opcode >> 5) & 0x7);
13256 gen_arith(ctx, OPC_ADDU, reg32, rz, 0);
13257 }
13258 break;
13259 case I8_MOVR32:
13260 reg32 = ctx->opcode & 0x1f;
13261 gen_arith(ctx, OPC_ADDU, ry, reg32, 0);
13262 break;
13263 default:
13264 gen_reserved_instruction(ctx);
13265 break;
13266 }
13267 }
13268 break;
13269 case M16_OPC_LI:
13270 {
13271 int16_t imm = (uint8_t) ctx->opcode;
13272
13273 gen_arith_imm(ctx, OPC_ADDIU, rx, 0, imm);
13274 }
13275 break;
13276 case M16_OPC_CMPI:
13277 {
13278 int16_t imm = (uint8_t) ctx->opcode;
13279 gen_logic_imm(ctx, OPC_XORI, 24, rx, imm);
13280 }
13281 break;
13282 #if defined(TARGET_MIPS64)
13283 case M16_OPC_SD:
13284 check_insn(ctx, ISA_MIPS3);
13285 check_mips_64(ctx);
13286 gen_st(ctx, OPC_SD, ry, rx, offset << 3);
13287 break;
13288 #endif
13289 case M16_OPC_LB:
13290 gen_ld(ctx, OPC_LB, ry, rx, offset);
13291 break;
13292 case M16_OPC_LH:
13293 gen_ld(ctx, OPC_LH, ry, rx, offset << 1);
13294 break;
13295 case M16_OPC_LWSP:
13296 gen_ld(ctx, OPC_LW, rx, 29, ((uint8_t)ctx->opcode) << 2);
13297 break;
13298 case M16_OPC_LW:
13299 gen_ld(ctx, OPC_LW, ry, rx, offset << 2);
13300 break;
13301 case M16_OPC_LBU:
13302 gen_ld(ctx, OPC_LBU, ry, rx, offset);
13303 break;
13304 case M16_OPC_LHU:
13305 gen_ld(ctx, OPC_LHU, ry, rx, offset << 1);
13306 break;
13307 case M16_OPC_LWPC:
13308 gen_ld(ctx, OPC_LWPC, rx, 0, ((uint8_t)ctx->opcode) << 2);
13309 break;
13310 #if defined(TARGET_MIPS64)
13311 case M16_OPC_LWU:
13312 check_insn(ctx, ISA_MIPS3);
13313 check_mips_64(ctx);
13314 gen_ld(ctx, OPC_LWU, ry, rx, offset << 2);
13315 break;
13316 #endif
13317 case M16_OPC_SB:
13318 gen_st(ctx, OPC_SB, ry, rx, offset);
13319 break;
13320 case M16_OPC_SH:
13321 gen_st(ctx, OPC_SH, ry, rx, offset << 1);
13322 break;
13323 case M16_OPC_SWSP:
13324 gen_st(ctx, OPC_SW, rx, 29, ((uint8_t)ctx->opcode) << 2);
13325 break;
13326 case M16_OPC_SW:
13327 gen_st(ctx, OPC_SW, ry, rx, offset << 2);
13328 break;
13329 case M16_OPC_RRR:
13330 {
13331 int rz = xlat((ctx->opcode >> 2) & 0x7);
13332 int mips32_op;
13333
13334 switch (ctx->opcode & 0x3) {
13335 case RRR_ADDU:
13336 mips32_op = OPC_ADDU;
13337 break;
13338 case RRR_SUBU:
13339 mips32_op = OPC_SUBU;
13340 break;
13341 #if defined(TARGET_MIPS64)
13342 case RRR_DADDU:
13343 mips32_op = OPC_DADDU;
13344 check_insn(ctx, ISA_MIPS3);
13345 check_mips_64(ctx);
13346 break;
13347 case RRR_DSUBU:
13348 mips32_op = OPC_DSUBU;
13349 check_insn(ctx, ISA_MIPS3);
13350 check_mips_64(ctx);
13351 break;
13352 #endif
13353 default:
13354 gen_reserved_instruction(ctx);
13355 goto done;
13356 }
13357
13358 gen_arith(ctx, mips32_op, rz, rx, ry);
13359 done:
13360 ;
13361 }
13362 break;
13363 case M16_OPC_RR:
13364 switch (op1) {
13365 case RR_JR:
13366 {
13367 int nd = (ctx->opcode >> 7) & 0x1;
13368 int link = (ctx->opcode >> 6) & 0x1;
13369 int ra = (ctx->opcode >> 5) & 0x1;
13370
13371 if (nd) {
13372 check_insn(ctx, ISA_MIPS_R1);
13373 }
13374
13375 if (link) {
13376 op = OPC_JALR;
13377 } else {
13378 op = OPC_JR;
13379 }
13380
13381 gen_compute_branch(ctx, op, 2, ra ? 31 : rx, 31, 0,
13382 (nd ? 0 : 2));
13383 }
13384 break;
13385 case RR_SDBBP:
13386 if (is_uhi(extract32(ctx->opcode, 5, 6))) {
13387 gen_helper_do_semihosting(cpu_env);
13388 } else {
13389 /*
13390 * XXX: not clear which exception should be raised
13391 * when in debug mode...
13392 */
13393 check_insn(ctx, ISA_MIPS_R1);
13394 generate_exception_end(ctx, EXCP_DBp);
13395 }
13396 break;
13397 case RR_SLT:
13398 gen_slt(ctx, OPC_SLT, 24, rx, ry);
13399 break;
13400 case RR_SLTU:
13401 gen_slt(ctx, OPC_SLTU, 24, rx, ry);
13402 break;
13403 case RR_BREAK:
13404 generate_exception_end(ctx, EXCP_BREAK);
13405 break;
13406 case RR_SLLV:
13407 gen_shift(ctx, OPC_SLLV, ry, rx, ry);
13408 break;
13409 case RR_SRLV:
13410 gen_shift(ctx, OPC_SRLV, ry, rx, ry);
13411 break;
13412 case RR_SRAV:
13413 gen_shift(ctx, OPC_SRAV, ry, rx, ry);
13414 break;
13415 #if defined(TARGET_MIPS64)
13416 case RR_DSRL:
13417 check_insn(ctx, ISA_MIPS3);
13418 check_mips_64(ctx);
13419 gen_shift_imm(ctx, OPC_DSRL, ry, ry, sa);
13420 break;
13421 #endif
13422 case RR_CMP:
13423 gen_logic(ctx, OPC_XOR, 24, rx, ry);
13424 break;
13425 case RR_NEG:
13426 gen_arith(ctx, OPC_SUBU, rx, 0, ry);
13427 break;
13428 case RR_AND:
13429 gen_logic(ctx, OPC_AND, rx, rx, ry);
13430 break;
13431 case RR_OR:
13432 gen_logic(ctx, OPC_OR, rx, rx, ry);
13433 break;
13434 case RR_XOR:
13435 gen_logic(ctx, OPC_XOR, rx, rx, ry);
13436 break;
13437 case RR_NOT:
13438 gen_logic(ctx, OPC_NOR, rx, ry, 0);
13439 break;
13440 case RR_MFHI:
13441 gen_HILO(ctx, OPC_MFHI, 0, rx);
13442 break;
13443 case RR_CNVT:
13444 check_insn(ctx, ISA_MIPS_R1);
13445 switch (cnvt_op) {
13446 case RR_RY_CNVT_ZEB:
13447 tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]);
13448 break;
13449 case RR_RY_CNVT_ZEH:
13450 tcg_gen_ext16u_tl(cpu_gpr[rx], cpu_gpr[rx]);
13451 break;
13452 case RR_RY_CNVT_SEB:
13453 tcg_gen_ext8s_tl(cpu_gpr[rx], cpu_gpr[rx]);
13454 break;
13455 case RR_RY_CNVT_SEH:
13456 tcg_gen_ext16s_tl(cpu_gpr[rx], cpu_gpr[rx]);
13457 break;
13458 #if defined(TARGET_MIPS64)
13459 case RR_RY_CNVT_ZEW:
13460 check_insn(ctx, ISA_MIPS_R1);
13461 check_mips_64(ctx);
13462 tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]);
13463 break;
13464 case RR_RY_CNVT_SEW:
13465 check_insn(ctx, ISA_MIPS_R1);
13466 check_mips_64(ctx);
13467 tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
13468 break;
13469 #endif
13470 default:
13471 gen_reserved_instruction(ctx);
13472 break;
13473 }
13474 break;
13475 case RR_MFLO:
13476 gen_HILO(ctx, OPC_MFLO, 0, rx);
13477 break;
13478 #if defined(TARGET_MIPS64)
13479 case RR_DSRA:
13480 check_insn(ctx, ISA_MIPS3);
13481 check_mips_64(ctx);
13482 gen_shift_imm(ctx, OPC_DSRA, ry, ry, sa);
13483 break;
13484 case RR_DSLLV:
13485 check_insn(ctx, ISA_MIPS3);
13486 check_mips_64(ctx);
13487 gen_shift(ctx, OPC_DSLLV, ry, rx, ry);
13488 break;
13489 case RR_DSRLV:
13490 check_insn(ctx, ISA_MIPS3);
13491 check_mips_64(ctx);
13492 gen_shift(ctx, OPC_DSRLV, ry, rx, ry);
13493 break;
13494 case RR_DSRAV:
13495 check_insn(ctx, ISA_MIPS3);
13496 check_mips_64(ctx);
13497 gen_shift(ctx, OPC_DSRAV, ry, rx, ry);
13498 break;
13499 #endif
13500 case RR_MULT:
13501 gen_muldiv(ctx, OPC_MULT, 0, rx, ry);
13502 break;
13503 case RR_MULTU:
13504 gen_muldiv(ctx, OPC_MULTU, 0, rx, ry);
13505 break;
13506 case RR_DIV:
13507 gen_muldiv(ctx, OPC_DIV, 0, rx, ry);
13508 break;
13509 case RR_DIVU:
13510 gen_muldiv(ctx, OPC_DIVU, 0, rx, ry);
13511 break;
13512 #if defined(TARGET_MIPS64)
13513 case RR_DMULT:
13514 check_insn(ctx, ISA_MIPS3);
13515 check_mips_64(ctx);
13516 gen_muldiv(ctx, OPC_DMULT, 0, rx, ry);
13517 break;
13518 case RR_DMULTU:
13519 check_insn(ctx, ISA_MIPS3);
13520 check_mips_64(ctx);
13521 gen_muldiv(ctx, OPC_DMULTU, 0, rx, ry);
13522 break;
13523 case RR_DDIV:
13524 check_insn(ctx, ISA_MIPS3);
13525 check_mips_64(ctx);
13526 gen_muldiv(ctx, OPC_DDIV, 0, rx, ry);
13527 break;
13528 case RR_DDIVU:
13529 check_insn(ctx, ISA_MIPS3);
13530 check_mips_64(ctx);
13531 gen_muldiv(ctx, OPC_DDIVU, 0, rx, ry);
13532 break;
13533 #endif
13534 default:
13535 gen_reserved_instruction(ctx);
13536 break;
13537 }
13538 break;
13539 case M16_OPC_EXTEND:
13540 decode_extended_mips16_opc(env, ctx);
13541 n_bytes = 4;
13542 break;
13543 #if defined(TARGET_MIPS64)
13544 case M16_OPC_I64:
13545 funct = (ctx->opcode >> 8) & 0x7;
13546 decode_i64_mips16(ctx, ry, funct, offset, 0);
13547 break;
13548 #endif
13549 default:
13550 gen_reserved_instruction(ctx);
13551 break;
13552 }
13553
13554 return n_bytes;
13555 }
13556
13557 /* microMIPS extension to MIPS32/MIPS64 */
13558
13559 /*
13560 * microMIPS32/microMIPS64 major opcodes
13561 *
13562 * 1. MIPS Architecture for Programmers Volume II-B:
13563 * The microMIPS32 Instruction Set (Revision 3.05)
13564 *
13565 * Table 6.2 microMIPS32 Encoding of Major Opcode Field
13566 *
13567 * 2. MIPS Architecture For Programmers Volume II-A:
13568 * The MIPS64 Instruction Set (Revision 3.51)
13569 */
13570
13571 enum {
13572 POOL32A = 0x00,
13573 POOL16A = 0x01,
13574 LBU16 = 0x02,
13575 MOVE16 = 0x03,
13576 ADDI32 = 0x04,
13577 R6_LUI = 0x04,
13578 AUI = 0x04,
13579 LBU32 = 0x05,
13580 SB32 = 0x06,
13581 LB32 = 0x07,
13582
13583 POOL32B = 0x08,
13584 POOL16B = 0x09,
13585 LHU16 = 0x0a,
13586 ANDI16 = 0x0b,
13587 ADDIU32 = 0x0c,
13588 LHU32 = 0x0d,
13589 SH32 = 0x0e,
13590 LH32 = 0x0f,
13591
13592 POOL32I = 0x10,
13593 POOL16C = 0x11,
13594 LWSP16 = 0x12,
13595 POOL16D = 0x13,
13596 ORI32 = 0x14,
13597 POOL32F = 0x15,
13598 POOL32S = 0x16, /* MIPS64 */
13599 DADDIU32 = 0x17, /* MIPS64 */
13600
13601 POOL32C = 0x18,
13602 LWGP16 = 0x19,
13603 LW16 = 0x1a,
13604 POOL16E = 0x1b,
13605 XORI32 = 0x1c,
13606 JALS32 = 0x1d,
13607 BOVC = 0x1d,
13608 BEQC = 0x1d,
13609 BEQZALC = 0x1d,
13610 ADDIUPC = 0x1e,
13611 PCREL = 0x1e,
13612 BNVC = 0x1f,
13613 BNEC = 0x1f,
13614 BNEZALC = 0x1f,
13615
13616 R6_BEQZC = 0x20,
13617 JIC = 0x20,
13618 POOL16F = 0x21,
13619 SB16 = 0x22,
13620 BEQZ16 = 0x23,
13621 BEQZC16 = 0x23,
13622 SLTI32 = 0x24,
13623 BEQ32 = 0x25,
13624 BC = 0x25,
13625 SWC132 = 0x26,
13626 LWC132 = 0x27,
13627
13628 /* 0x29 is reserved */
13629 RES_29 = 0x29,
13630 R6_BNEZC = 0x28,
13631 JIALC = 0x28,
13632 SH16 = 0x2a,
13633 BNEZ16 = 0x2b,
13634 BNEZC16 = 0x2b,
13635 SLTIU32 = 0x2c,
13636 BNE32 = 0x2d,
13637 BALC = 0x2d,
13638 SDC132 = 0x2e,
13639 LDC132 = 0x2f,
13640
13641 /* 0x31 is reserved */
13642 RES_31 = 0x31,
13643 BLEZALC = 0x30,
13644 BGEZALC = 0x30,
13645 BGEUC = 0x30,
13646 SWSP16 = 0x32,
13647 B16 = 0x33,
13648 BC16 = 0x33,
13649 ANDI32 = 0x34,
13650 J32 = 0x35,
13651 BGTZC = 0x35,
13652 BLTZC = 0x35,
13653 BLTC = 0x35,
13654 SD32 = 0x36, /* MIPS64 */
13655 LD32 = 0x37, /* MIPS64 */
13656
13657 /* 0x39 is reserved */
13658 RES_39 = 0x39,
13659 BGTZALC = 0x38,
13660 BLTZALC = 0x38,
13661 BLTUC = 0x38,
13662 SW16 = 0x3a,
13663 LI16 = 0x3b,
13664 JALX32 = 0x3c,
13665 JAL32 = 0x3d,
13666 BLEZC = 0x3d,
13667 BGEZC = 0x3d,
13668 BGEC = 0x3d,
13669 SW32 = 0x3e,
13670 LW32 = 0x3f
13671 };
13672
13673 /* PCREL Instructions perform PC-Relative address calculation. bits 20..16 */
13674 enum {
13675 ADDIUPC_00 = 0x00,
13676 ADDIUPC_01 = 0x01,
13677 ADDIUPC_02 = 0x02,
13678 ADDIUPC_03 = 0x03,
13679 ADDIUPC_04 = 0x04,
13680 ADDIUPC_05 = 0x05,
13681 ADDIUPC_06 = 0x06,
13682 ADDIUPC_07 = 0x07,
13683 AUIPC = 0x1e,
13684 ALUIPC = 0x1f,
13685 LWPC_08 = 0x08,
13686 LWPC_09 = 0x09,
13687 LWPC_0A = 0x0A,
13688 LWPC_0B = 0x0B,
13689 LWPC_0C = 0x0C,
13690 LWPC_0D = 0x0D,
13691 LWPC_0E = 0x0E,
13692 LWPC_0F = 0x0F,
13693 };
13694
13695 /* POOL32A encoding of minor opcode field */
13696
13697 enum {
13698 /*
13699 * These opcodes are distinguished only by bits 9..6; those bits are
13700 * what are recorded below.
13701 */
13702 SLL32 = 0x0,
13703 SRL32 = 0x1,
13704 SRA = 0x2,
13705 ROTR = 0x3,
13706 SELEQZ = 0x5,
13707 SELNEZ = 0x6,
13708 R6_RDHWR = 0x7,
13709
13710 SLLV = 0x0,
13711 SRLV = 0x1,
13712 SRAV = 0x2,
13713 ROTRV = 0x3,
13714 ADD = 0x4,
13715 ADDU32 = 0x5,
13716 SUB = 0x6,
13717 SUBU32 = 0x7,
13718 MUL = 0x8,
13719 AND = 0x9,
13720 OR32 = 0xa,
13721 NOR = 0xb,
13722 XOR32 = 0xc,
13723 SLT = 0xd,
13724 SLTU = 0xe,
13725
13726 MOVN = 0x0,
13727 R6_MUL = 0x0,
13728 MOVZ = 0x1,
13729 MUH = 0x1,
13730 MULU = 0x2,
13731 MUHU = 0x3,
13732 LWXS = 0x4,
13733 R6_DIV = 0x4,
13734 MOD = 0x5,
13735 R6_DIVU = 0x6,
13736 MODU = 0x7,
13737
13738 /* The following can be distinguished by their lower 6 bits. */
13739 BREAK32 = 0x07,
13740 INS = 0x0c,
13741 LSA = 0x0f,
13742 ALIGN = 0x1f,
13743 EXT = 0x2c,
13744 POOL32AXF = 0x3c,
13745 SIGRIE = 0x3f
13746 };
13747
13748 /* POOL32AXF encoding of minor opcode field extension */
13749
13750 /*
13751 * 1. MIPS Architecture for Programmers Volume II-B:
13752 * The microMIPS32 Instruction Set (Revision 3.05)
13753 *
13754 * Table 6.5 POOL32Axf Encoding of Minor Opcode Extension Field
13755 *
13756 * 2. MIPS Architecture for Programmers VolumeIV-e:
13757 * The MIPS DSP Application-Specific Extension
13758 * to the microMIPS32 Architecture (Revision 2.34)
13759 *
13760 * Table 5.5 POOL32Axf Encoding of Minor Opcode Extension Field
13761 */
13762
13763 enum {
13764 /* bits 11..6 */
13765 TEQ = 0x00,
13766 TGE = 0x08,
13767 TGEU = 0x10,
13768 TLT = 0x20,
13769 TLTU = 0x28,
13770 TNE = 0x30,
13771
13772 MFC0 = 0x03,
13773 MTC0 = 0x0b,
13774
13775 /* begin of microMIPS32 DSP */
13776
13777 /* bits 13..12 for 0x01 */
13778 MFHI_ACC = 0x0,
13779 MFLO_ACC = 0x1,
13780 MTHI_ACC = 0x2,
13781 MTLO_ACC = 0x3,
13782
13783 /* bits 13..12 for 0x2a */
13784 MADD_ACC = 0x0,
13785 MADDU_ACC = 0x1,
13786 MSUB_ACC = 0x2,
13787 MSUBU_ACC = 0x3,
13788
13789 /* bits 13..12 for 0x32 */
13790 MULT_ACC = 0x0,
13791 MULTU_ACC = 0x1,
13792
13793 /* end of microMIPS32 DSP */
13794
13795 /* bits 15..12 for 0x2c */
13796 BITSWAP = 0x0,
13797 SEB = 0x2,
13798 SEH = 0x3,
13799 CLO = 0x4,
13800 CLZ = 0x5,
13801 RDHWR = 0x6,
13802 WSBH = 0x7,
13803 MULT = 0x8,
13804 MULTU = 0x9,
13805 DIV = 0xa,
13806 DIVU = 0xb,
13807 MADD = 0xc,
13808 MADDU = 0xd,
13809 MSUB = 0xe,
13810 MSUBU = 0xf,
13811
13812 /* bits 15..12 for 0x34 */
13813 MFC2 = 0x4,
13814 MTC2 = 0x5,
13815 MFHC2 = 0x8,
13816 MTHC2 = 0x9,
13817 CFC2 = 0xc,
13818 CTC2 = 0xd,
13819
13820 /* bits 15..12 for 0x3c */
13821 JALR = 0x0,
13822 JR = 0x0, /* alias */
13823 JALRC = 0x0,
13824 JRC = 0x0,
13825 JALR_HB = 0x1,
13826 JALRC_HB = 0x1,
13827 JALRS = 0x4,
13828 JALRS_HB = 0x5,
13829
13830 /* bits 15..12 for 0x05 */
13831 RDPGPR = 0xe,
13832 WRPGPR = 0xf,
13833
13834 /* bits 15..12 for 0x0d */
13835 TLBP = 0x0,
13836 TLBR = 0x1,
13837 TLBWI = 0x2,
13838 TLBWR = 0x3,
13839 TLBINV = 0x4,
13840 TLBINVF = 0x5,
13841 WAIT = 0x9,
13842 IRET = 0xd,
13843 DERET = 0xe,
13844 ERET = 0xf,
13845
13846 /* bits 15..12 for 0x15 */
13847 DMT = 0x0,
13848 DVPE = 0x1,
13849 EMT = 0x2,
13850 EVPE = 0x3,
13851
13852 /* bits 15..12 for 0x1d */
13853 DI = 0x4,
13854 EI = 0x5,
13855
13856 /* bits 15..12 for 0x2d */
13857 SYNC = 0x6,
13858 SYSCALL = 0x8,
13859 SDBBP = 0xd,
13860
13861 /* bits 15..12 for 0x35 */
13862 MFHI32 = 0x0,
13863 MFLO32 = 0x1,
13864 MTHI32 = 0x2,
13865 MTLO32 = 0x3,
13866 };
13867
13868 /* POOL32B encoding of minor opcode field (bits 15..12) */
13869
13870 enum {
13871 LWC2 = 0x0,
13872 LWP = 0x1,
13873 LDP = 0x4,
13874 LWM32 = 0x5,
13875 CACHE = 0x6,
13876 LDM = 0x7,
13877 SWC2 = 0x8,
13878 SWP = 0x9,
13879 SDP = 0xc,
13880 SWM32 = 0xd,
13881 SDM = 0xf
13882 };
13883
13884 /* POOL32C encoding of minor opcode field (bits 15..12) */
13885
13886 enum {
13887 LWL = 0x0,
13888 SWL = 0x8,
13889 LWR = 0x1,
13890 SWR = 0x9,
13891 PREF = 0x2,
13892 ST_EVA = 0xa,
13893 LL = 0x3,
13894 SC = 0xb,
13895 LDL = 0x4,
13896 SDL = 0xc,
13897 LDR = 0x5,
13898 SDR = 0xd,
13899 LD_EVA = 0x6,
13900 LWU = 0xe,
13901 LLD = 0x7,
13902 SCD = 0xf
13903 };
13904
13905 /* POOL32C LD-EVA encoding of minor opcode field (bits 11..9) */
13906
13907 enum {
13908 LBUE = 0x0,
13909 LHUE = 0x1,
13910 LWLE = 0x2,
13911 LWRE = 0x3,
13912 LBE = 0x4,
13913 LHE = 0x5,
13914 LLE = 0x6,
13915 LWE = 0x7,
13916 };
13917
13918 /* POOL32C ST-EVA encoding of minor opcode field (bits 11..9) */
13919
13920 enum {
13921 SWLE = 0x0,
13922 SWRE = 0x1,
13923 PREFE = 0x2,
13924 CACHEE = 0x3,
13925 SBE = 0x4,
13926 SHE = 0x5,
13927 SCE = 0x6,
13928 SWE = 0x7,
13929 };
13930
13931 /* POOL32F encoding of minor opcode field (bits 5..0) */
13932
13933 enum {
13934 /* These are the bit 7..6 values */
13935 ADD_FMT = 0x0,
13936
13937 SUB_FMT = 0x1,
13938
13939 MUL_FMT = 0x2,
13940
13941 DIV_FMT = 0x3,
13942
13943 /* These are the bit 8..6 values */
13944 MOVN_FMT = 0x0,
13945 RSQRT2_FMT = 0x0,
13946 MOVF_FMT = 0x0,
13947 RINT_FMT = 0x0,
13948 SELNEZ_FMT = 0x0,
13949
13950 MOVZ_FMT = 0x1,
13951 LWXC1 = 0x1,
13952 MOVT_FMT = 0x1,
13953 CLASS_FMT = 0x1,
13954 SELEQZ_FMT = 0x1,
13955
13956 PLL_PS = 0x2,
13957 SWXC1 = 0x2,
13958 SEL_FMT = 0x2,
13959
13960 PLU_PS = 0x3,
13961 LDXC1 = 0x3,
13962
13963 MOVN_FMT_04 = 0x4,
13964 PUL_PS = 0x4,
13965 SDXC1 = 0x4,
13966 RECIP2_FMT = 0x4,
13967
13968 MOVZ_FMT_05 = 0x05,
13969 PUU_PS = 0x5,
13970 LUXC1 = 0x5,
13971
13972 CVT_PS_S = 0x6,
13973 SUXC1 = 0x6,
13974 ADDR_PS = 0x6,
13975 PREFX = 0x6,
13976 MADDF_FMT = 0x6,
13977
13978 MULR_PS = 0x7,
13979 MSUBF_FMT = 0x7,
13980
13981 MADD_S = 0x01,
13982 MADD_D = 0x09,
13983 MADD_PS = 0x11,
13984 ALNV_PS = 0x19,
13985 MSUB_S = 0x21,
13986 MSUB_D = 0x29,
13987 MSUB_PS = 0x31,
13988
13989 NMADD_S = 0x02,
13990 NMADD_D = 0x0a,
13991 NMADD_PS = 0x12,
13992 NMSUB_S = 0x22,
13993 NMSUB_D = 0x2a,
13994 NMSUB_PS = 0x32,
13995
13996 MIN_FMT = 0x3,
13997 MAX_FMT = 0xb,
13998 MINA_FMT = 0x23,
13999 MAXA_FMT = 0x2b,
14000 POOL32FXF = 0x3b,
14001
14002 CABS_COND_FMT = 0x1c, /* MIPS3D */
14003 C_COND_FMT = 0x3c,
14004
14005 CMP_CONDN_S = 0x5,
14006 CMP_CONDN_D = 0x15
14007 };
14008
14009 /* POOL32Fxf encoding of minor opcode extension field */
14010
14011 enum {
14012 CVT_L = 0x04,
14013 RSQRT_FMT = 0x08,
14014 FLOOR_L = 0x0c,
14015 CVT_PW_PS = 0x1c,
14016 CVT_W = 0x24,
14017 SQRT_FMT = 0x28,
14018 FLOOR_W = 0x2c,
14019 CVT_PS_PW = 0x3c,
14020 CFC1 = 0x40,
14021 RECIP_FMT = 0x48,
14022 CEIL_L = 0x4c,
14023 CTC1 = 0x60,
14024 CEIL_W = 0x6c,
14025 MFC1 = 0x80,
14026 CVT_S_PL = 0x84,
14027 TRUNC_L = 0x8c,
14028 MTC1 = 0xa0,
14029 CVT_S_PU = 0xa4,
14030 TRUNC_W = 0xac,
14031 MFHC1 = 0xc0,
14032 ROUND_L = 0xcc,
14033 MTHC1 = 0xe0,
14034 ROUND_W = 0xec,
14035
14036 MOV_FMT = 0x01,
14037 MOVF = 0x05,
14038 ABS_FMT = 0x0d,
14039 RSQRT1_FMT = 0x1d,
14040 MOVT = 0x25,
14041 NEG_FMT = 0x2d,
14042 CVT_D = 0x4d,
14043 RECIP1_FMT = 0x5d,
14044 CVT_S = 0x6d
14045 };
14046
14047 /* POOL32I encoding of minor opcode field (bits 25..21) */
14048
14049 enum {
14050 BLTZ = 0x00,
14051 BLTZAL = 0x01,
14052 BGEZ = 0x02,
14053 BGEZAL = 0x03,
14054 BLEZ = 0x04,
14055 BNEZC = 0x05,
14056 BGTZ = 0x06,
14057 BEQZC = 0x07,
14058 TLTI = 0x08,
14059 BC1EQZC = 0x08,
14060 TGEI = 0x09,
14061 BC1NEZC = 0x09,
14062 TLTIU = 0x0a,
14063 BC2EQZC = 0x0a,
14064 TGEIU = 0x0b,
14065 BC2NEZC = 0x0a,
14066 TNEI = 0x0c,
14067 R6_SYNCI = 0x0c,
14068 LUI = 0x0d,
14069 TEQI = 0x0e,
14070 SYNCI = 0x10,
14071 BLTZALS = 0x11,
14072 BGEZALS = 0x13,
14073 BC2F = 0x14,
14074 BC2T = 0x15,
14075 BPOSGE64 = 0x1a,
14076 BPOSGE32 = 0x1b,
14077 /* These overlap and are distinguished by bit16 of the instruction */
14078 BC1F = 0x1c,
14079 BC1T = 0x1d,
14080 BC1ANY2F = 0x1c,
14081 BC1ANY2T = 0x1d,
14082 BC1ANY4F = 0x1e,
14083 BC1ANY4T = 0x1f
14084 };
14085
14086 /* POOL16A encoding of minor opcode field */
14087
14088 enum {
14089 ADDU16 = 0x0,
14090 SUBU16 = 0x1
14091 };
14092
14093 /* POOL16B encoding of minor opcode field */
14094
14095 enum {
14096 SLL16 = 0x0,
14097 SRL16 = 0x1
14098 };
14099
14100 /* POOL16C encoding of minor opcode field */
14101
14102 enum {
14103 NOT16 = 0x00,
14104 XOR16 = 0x04,
14105 AND16 = 0x08,
14106 OR16 = 0x0c,
14107 LWM16 = 0x10,
14108 SWM16 = 0x14,
14109 JR16 = 0x18,
14110 JRC16 = 0x1a,
14111 JALR16 = 0x1c,
14112 JALR16S = 0x1e,
14113 MFHI16 = 0x20,
14114 MFLO16 = 0x24,
14115 BREAK16 = 0x28,
14116 SDBBP16 = 0x2c,
14117 JRADDIUSP = 0x30
14118 };
14119
14120 /* R6 POOL16C encoding of minor opcode field (bits 0..5) */
14121
14122 enum {
14123 R6_NOT16 = 0x00,
14124 R6_AND16 = 0x01,
14125 R6_LWM16 = 0x02,
14126 R6_JRC16 = 0x03,
14127 MOVEP = 0x04,
14128 MOVEP_05 = 0x05,
14129 MOVEP_06 = 0x06,
14130 MOVEP_07 = 0x07,
14131 R6_XOR16 = 0x08,
14132 R6_OR16 = 0x09,
14133 R6_SWM16 = 0x0a,
14134 JALRC16 = 0x0b,
14135 MOVEP_0C = 0x0c,
14136 MOVEP_0D = 0x0d,
14137 MOVEP_0E = 0x0e,
14138 MOVEP_0F = 0x0f,
14139 JRCADDIUSP = 0x13,
14140 R6_BREAK16 = 0x1b,
14141 R6_SDBBP16 = 0x3b
14142 };
14143
14144 /* POOL16D encoding of minor opcode field */
14145
14146 enum {
14147 ADDIUS5 = 0x0,
14148 ADDIUSP = 0x1
14149 };
14150
14151 /* POOL16E encoding of minor opcode field */
14152
14153 enum {
14154 ADDIUR2 = 0x0,
14155 ADDIUR1SP = 0x1
14156 };
14157
14158 static int mmreg(int r)
14159 {
14160 static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
14161
14162 return map[r];
14163 }
14164
14165 /* Used for 16-bit store instructions. */
14166 static int mmreg2(int r)
14167 {
14168 static const int map[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
14169
14170 return map[r];
14171 }
14172
14173 #define uMIPS_RD(op) ((op >> 7) & 0x7)
14174 #define uMIPS_RS(op) ((op >> 4) & 0x7)
14175 #define uMIPS_RS2(op) uMIPS_RS(op)
14176 #define uMIPS_RS1(op) ((op >> 1) & 0x7)
14177 #define uMIPS_RD5(op) ((op >> 5) & 0x1f)
14178 #define uMIPS_RS5(op) (op & 0x1f)
14179
14180 /* Signed immediate */
14181 #define SIMM(op, start, width) \
14182 ((int32_t)(((op >> start) & ((~0U) >> (32 - width))) \
14183 << (32 - width)) \
14184 >> (32 - width))
14185 /* Zero-extended immediate */
14186 #define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32 - width)))
14187
14188 static void gen_addiur1sp(DisasContext *ctx)
14189 {
14190 int rd = mmreg(uMIPS_RD(ctx->opcode));
14191
14192 gen_arith_imm(ctx, OPC_ADDIU, rd, 29, ((ctx->opcode >> 1) & 0x3f) << 2);
14193 }
14194
14195 static void gen_addiur2(DisasContext *ctx)
14196 {
14197 static const int decoded_imm[] = { 1, 4, 8, 12, 16, 20, 24, -1 };
14198 int rd = mmreg(uMIPS_RD(ctx->opcode));
14199 int rs = mmreg(uMIPS_RS(ctx->opcode));
14200
14201 gen_arith_imm(ctx, OPC_ADDIU, rd, rs, decoded_imm[ZIMM(ctx->opcode, 1, 3)]);
14202 }
14203
14204 static void gen_addiusp(DisasContext *ctx)
14205 {
14206 int encoded = ZIMM(ctx->opcode, 1, 9);
14207 int decoded;
14208
14209 if (encoded <= 1) {
14210 decoded = 256 + encoded;
14211 } else if (encoded <= 255) {
14212 decoded = encoded;
14213 } else if (encoded <= 509) {
14214 decoded = encoded - 512;
14215 } else {
14216 decoded = encoded - 768;
14217 }
14218
14219 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, decoded << 2);
14220 }
14221
14222 static void gen_addius5(DisasContext *ctx)
14223 {
14224 int imm = SIMM(ctx->opcode, 1, 4);
14225 int rd = (ctx->opcode >> 5) & 0x1f;
14226
14227 gen_arith_imm(ctx, OPC_ADDIU, rd, rd, imm);
14228 }
14229
14230 static void gen_andi16(DisasContext *ctx)
14231 {
14232 static const int decoded_imm[] = { 128, 1, 2, 3, 4, 7, 8, 15, 16,
14233 31, 32, 63, 64, 255, 32768, 65535 };
14234 int rd = mmreg(uMIPS_RD(ctx->opcode));
14235 int rs = mmreg(uMIPS_RS(ctx->opcode));
14236 int encoded = ZIMM(ctx->opcode, 0, 4);
14237
14238 gen_logic_imm(ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]);
14239 }
14240
14241 static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
14242 int base, int16_t offset)
14243 {
14244 TCGv t0, t1;
14245 TCGv_i32 t2;
14246
14247 if (ctx->hflags & MIPS_HFLAG_BMASK) {
14248 gen_reserved_instruction(ctx);
14249 return;
14250 }
14251
14252 t0 = tcg_temp_new();
14253
14254 gen_base_offset_addr(ctx, t0, base, offset);
14255
14256 t1 = tcg_const_tl(reglist);
14257 t2 = tcg_const_i32(ctx->mem_idx);
14258
14259 save_cpu_state(ctx, 1);
14260 switch (opc) {
14261 case LWM32:
14262 gen_helper_lwm(cpu_env, t0, t1, t2);
14263 break;
14264 case SWM32:
14265 gen_helper_swm(cpu_env, t0, t1, t2);
14266 break;
14267 #ifdef TARGET_MIPS64
14268 case LDM:
14269 gen_helper_ldm(cpu_env, t0, t1, t2);
14270 break;
14271 case SDM:
14272 gen_helper_sdm(cpu_env, t0, t1, t2);
14273 break;
14274 #endif
14275 }
14276 tcg_temp_free(t0);
14277 tcg_temp_free(t1);
14278 tcg_temp_free_i32(t2);
14279 }
14280
14281
14282 static void gen_pool16c_insn(DisasContext *ctx)
14283 {
14284 int rd = mmreg((ctx->opcode >> 3) & 0x7);
14285 int rs = mmreg(ctx->opcode & 0x7);
14286
14287 switch (((ctx->opcode) >> 4) & 0x3f) {
14288 case NOT16 + 0:
14289 case NOT16 + 1:
14290 case NOT16 + 2:
14291 case NOT16 + 3:
14292 gen_logic(ctx, OPC_NOR, rd, rs, 0);
14293 break;
14294 case XOR16 + 0:
14295 case XOR16 + 1:
14296 case XOR16 + 2:
14297 case XOR16 + 3:
14298 gen_logic(ctx, OPC_XOR, rd, rd, rs);
14299 break;
14300 case AND16 + 0:
14301 case AND16 + 1:
14302 case AND16 + 2:
14303 case AND16 + 3:
14304 gen_logic(ctx, OPC_AND, rd, rd, rs);
14305 break;
14306 case OR16 + 0:
14307 case OR16 + 1:
14308 case OR16 + 2:
14309 case OR16 + 3:
14310 gen_logic(ctx, OPC_OR, rd, rd, rs);
14311 break;
14312 case LWM16 + 0:
14313 case LWM16 + 1:
14314 case LWM16 + 2:
14315 case LWM16 + 3:
14316 {
14317 static const int lwm_convert[] = { 0x11, 0x12, 0x13, 0x14 };
14318 int offset = ZIMM(ctx->opcode, 0, 4);
14319
14320 gen_ldst_multiple(ctx, LWM32, lwm_convert[(ctx->opcode >> 4) & 0x3],
14321 29, offset << 2);
14322 }
14323 break;
14324 case SWM16 + 0:
14325 case SWM16 + 1:
14326 case SWM16 + 2:
14327 case SWM16 + 3:
14328 {
14329 static const int swm_convert[] = { 0x11, 0x12, 0x13, 0x14 };
14330 int offset = ZIMM(ctx->opcode, 0, 4);
14331
14332 gen_ldst_multiple(ctx, SWM32, swm_convert[(ctx->opcode >> 4) & 0x3],
14333 29, offset << 2);
14334 }
14335 break;
14336 case JR16 + 0:
14337 case JR16 + 1:
14338 {
14339 int reg = ctx->opcode & 0x1f;
14340
14341 gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0, 4);
14342 }
14343 break;
14344 case JRC16 + 0:
14345 case JRC16 + 1:
14346 {
14347 int reg = ctx->opcode & 0x1f;
14348 gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0, 0);
14349 /*
14350 * Let normal delay slot handling in our caller take us
14351 * to the branch target.
14352 */
14353 }
14354 break;
14355 case JALR16 + 0:
14356 case JALR16 + 1:
14357 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 4);
14358 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14359 break;
14360 case JALR16S + 0:
14361 case JALR16S + 1:
14362 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 2);
14363 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14364 break;
14365 case MFHI16 + 0:
14366 case MFHI16 + 1:
14367 gen_HILO(ctx, OPC_MFHI, 0, uMIPS_RS5(ctx->opcode));
14368 break;
14369 case MFLO16 + 0:
14370 case MFLO16 + 1:
14371 gen_HILO(ctx, OPC_MFLO, 0, uMIPS_RS5(ctx->opcode));
14372 break;
14373 case BREAK16:
14374 generate_exception_end(ctx, EXCP_BREAK);
14375 break;
14376 case SDBBP16:
14377 if (is_uhi(extract32(ctx->opcode, 0, 4))) {
14378 gen_helper_do_semihosting(cpu_env);
14379 } else {
14380 /*
14381 * XXX: not clear which exception should be raised
14382 * when in debug mode...
14383 */
14384 check_insn(ctx, ISA_MIPS_R1);
14385 generate_exception_end(ctx, EXCP_DBp);
14386 }
14387 break;
14388 case JRADDIUSP + 0:
14389 case JRADDIUSP + 1:
14390 {
14391 int imm = ZIMM(ctx->opcode, 0, 5);
14392 gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0);
14393 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2);
14394 /*
14395 * Let normal delay slot handling in our caller take us
14396 * to the branch target.
14397 */
14398 }
14399 break;
14400 default:
14401 gen_reserved_instruction(ctx);
14402 break;
14403 }
14404 }
14405
14406 static inline void gen_movep(DisasContext *ctx, int enc_dest, int enc_rt,
14407 int enc_rs)
14408 {
14409 int rd, re;
14410 static const int rd_enc[] = { 5, 5, 6, 4, 4, 4, 4, 4 };
14411 static const int re_enc[] = { 6, 7, 7, 21, 22, 5, 6, 7 };
14412 static const int rs_rt_enc[] = { 0, 17, 2, 3, 16, 18, 19, 20 };
14413
14414 rd = rd_enc[enc_dest];
14415 re = re_enc[enc_dest];
14416 gen_load_gpr(cpu_gpr[rd], rs_rt_enc[enc_rs]);
14417 gen_load_gpr(cpu_gpr[re], rs_rt_enc[enc_rt]);
14418 }
14419
14420 static void gen_pool16c_r6_insn(DisasContext *ctx)
14421 {
14422 int rt = mmreg((ctx->opcode >> 7) & 0x7);
14423 int rs = mmreg((ctx->opcode >> 4) & 0x7);
14424
14425 switch (ctx->opcode & 0xf) {
14426 case R6_NOT16:
14427 gen_logic(ctx, OPC_NOR, rt, rs, 0);
14428 break;
14429 case R6_AND16:
14430 gen_logic(ctx, OPC_AND, rt, rt, rs);
14431 break;
14432 case R6_LWM16:
14433 {
14434 int lwm_converted = 0x11 + extract32(ctx->opcode, 8, 2);
14435 int offset = extract32(ctx->opcode, 4, 4);
14436 gen_ldst_multiple(ctx, LWM32, lwm_converted, 29, offset << 2);
14437 }
14438 break;
14439 case R6_JRC16: /* JRCADDIUSP */
14440 if ((ctx->opcode >> 4) & 1) {
14441 /* JRCADDIUSP */
14442 int imm = extract32(ctx->opcode, 5, 5);
14443 gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0);
14444 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2);
14445 } else {
14446 /* JRC16 */
14447 rs = extract32(ctx->opcode, 5, 5);
14448 gen_compute_branch(ctx, OPC_JR, 2, rs, 0, 0, 0);
14449 }
14450 break;
14451 case MOVEP:
14452 case MOVEP_05:
14453 case MOVEP_06:
14454 case MOVEP_07:
14455 case MOVEP_0C:
14456 case MOVEP_0D:
14457 case MOVEP_0E:
14458 case MOVEP_0F:
14459 {
14460 int enc_dest = uMIPS_RD(ctx->opcode);
14461 int enc_rt = uMIPS_RS2(ctx->opcode);
14462 int enc_rs = (ctx->opcode & 3) | ((ctx->opcode >> 1) & 4);
14463 gen_movep(ctx, enc_dest, enc_rt, enc_rs);
14464 }
14465 break;
14466 case R6_XOR16:
14467 gen_logic(ctx, OPC_XOR, rt, rt, rs);
14468 break;
14469 case R6_OR16:
14470 gen_logic(ctx, OPC_OR, rt, rt, rs);
14471 break;
14472 case R6_SWM16:
14473 {
14474 int swm_converted = 0x11 + extract32(ctx->opcode, 8, 2);
14475 int offset = extract32(ctx->opcode, 4, 4);
14476 gen_ldst_multiple(ctx, SWM32, swm_converted, 29, offset << 2);
14477 }
14478 break;
14479 case JALRC16: /* BREAK16, SDBBP16 */
14480 switch (ctx->opcode & 0x3f) {
14481 case JALRC16:
14482 case JALRC16 + 0x20:
14483 /* JALRC16 */
14484 gen_compute_branch(ctx, OPC_JALR, 2, (ctx->opcode >> 5) & 0x1f,
14485 31, 0, 0);
14486 break;
14487 case R6_BREAK16:
14488 /* BREAK16 */
14489 generate_exception(ctx, EXCP_BREAK);
14490 break;
14491 case R6_SDBBP16:
14492 /* SDBBP16 */
14493 if (is_uhi(extract32(ctx->opcode, 6, 4))) {
14494 gen_helper_do_semihosting(cpu_env);
14495 } else {
14496 if (ctx->hflags & MIPS_HFLAG_SBRI) {
14497 generate_exception(ctx, EXCP_RI);
14498 } else {
14499 generate_exception(ctx, EXCP_DBp);
14500 }
14501 }
14502 break;
14503 }
14504 break;
14505 default:
14506 generate_exception(ctx, EXCP_RI);
14507 break;
14508 }
14509 }
14510
14511 static void gen_ldxs(DisasContext *ctx, int base, int index, int rd)
14512 {
14513 TCGv t0 = tcg_temp_new();
14514 TCGv t1 = tcg_temp_new();
14515
14516 gen_load_gpr(t0, base);
14517
14518 if (index != 0) {
14519 gen_load_gpr(t1, index);
14520 tcg_gen_shli_tl(t1, t1, 2);
14521 gen_op_addr_add(ctx, t0, t1, t0);
14522 }
14523
14524 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
14525 gen_store_gpr(t1, rd);
14526
14527 tcg_temp_free(t0);
14528 tcg_temp_free(t1);
14529 }
14530
14531 static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
14532 int base, int16_t offset)
14533 {
14534 TCGv t0, t1;
14535
14536 if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) {
14537 gen_reserved_instruction(ctx);
14538 return;
14539 }
14540
14541 t0 = tcg_temp_new();
14542 t1 = tcg_temp_new();
14543
14544 gen_base_offset_addr(ctx, t0, base, offset);
14545
14546 switch (opc) {
14547 case LWP:
14548 if (rd == base) {
14549 gen_reserved_instruction(ctx);
14550 return;
14551 }
14552 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
14553 gen_store_gpr(t1, rd);
14554 tcg_gen_movi_tl(t1, 4);
14555 gen_op_addr_add(ctx, t0, t0, t1);
14556 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
14557 gen_store_gpr(t1, rd + 1);
14558 break;
14559 case SWP:
14560 gen_load_gpr(t1, rd);
14561 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
14562 tcg_gen_movi_tl(t1, 4);
14563 gen_op_addr_add(ctx, t0, t0, t1);
14564 gen_load_gpr(t1, rd + 1);
14565 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
14566 break;
14567 #ifdef TARGET_MIPS64
14568 case LDP:
14569 if (rd == base) {
14570 gen_reserved_instruction(ctx);
14571 return;
14572 }
14573 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ);
14574 gen_store_gpr(t1, rd);
14575 tcg_gen_movi_tl(t1, 8);
14576 gen_op_addr_add(ctx, t0, t0, t1);
14577 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ);
14578 gen_store_gpr(t1, rd + 1);
14579 break;
14580 case SDP:
14581 gen_load_gpr(t1, rd);
14582 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ);
14583 tcg_gen_movi_tl(t1, 8);
14584 gen_op_addr_add(ctx, t0, t0, t1);
14585 gen_load_gpr(t1, rd + 1);
14586 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ);
14587 break;
14588 #endif
14589 }
14590 tcg_temp_free(t0);
14591 tcg_temp_free(t1);
14592 }
14593
14594 static void gen_sync(int stype)
14595 {
14596 TCGBar tcg_mo = TCG_BAR_SC;
14597
14598 switch (stype) {
14599 case 0x4: /* SYNC_WMB */
14600 tcg_mo |= TCG_MO_ST_ST;
14601 break;
14602 case 0x10: /* SYNC_MB */
14603 tcg_mo |= TCG_MO_ALL;
14604 break;
14605 case 0x11: /* SYNC_ACQUIRE */
14606 tcg_mo |= TCG_MO_LD_LD | TCG_MO_LD_ST;
14607 break;
14608 case 0x12: /* SYNC_RELEASE */
14609 tcg_mo |= TCG_MO_ST_ST | TCG_MO_LD_ST;
14610 break;
14611 case 0x13: /* SYNC_RMB */
14612 tcg_mo |= TCG_MO_LD_LD;
14613 break;
14614 default:
14615 tcg_mo |= TCG_MO_ALL;
14616 break;
14617 }
14618
14619 tcg_gen_mb(tcg_mo);
14620 }
14621
14622 static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
14623 {
14624 int extension = (ctx->opcode >> 6) & 0x3f;
14625 int minor = (ctx->opcode >> 12) & 0xf;
14626 uint32_t mips32_op;
14627
14628 switch (extension) {
14629 case TEQ:
14630 mips32_op = OPC_TEQ;
14631 goto do_trap;
14632 case TGE:
14633 mips32_op = OPC_TGE;
14634 goto do_trap;
14635 case TGEU:
14636 mips32_op = OPC_TGEU;
14637 goto do_trap;
14638 case TLT:
14639 mips32_op = OPC_TLT;
14640 goto do_trap;
14641 case TLTU:
14642 mips32_op = OPC_TLTU;
14643 goto do_trap;
14644 case TNE:
14645 mips32_op = OPC_TNE;
14646 do_trap:
14647 gen_trap(ctx, mips32_op, rs, rt, -1);
14648 break;
14649 #ifndef CONFIG_USER_ONLY
14650 case MFC0:
14651 case MFC0 + 32:
14652 check_cp0_enabled(ctx);
14653 if (rt == 0) {
14654 /* Treat as NOP. */
14655 break;
14656 }
14657 gen_mfc0(ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7);
14658 break;
14659 case MTC0:
14660 case MTC0 + 32:
14661 check_cp0_enabled(ctx);
14662 {
14663 TCGv t0 = tcg_temp_new();
14664
14665 gen_load_gpr(t0, rt);
14666 gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7);
14667 tcg_temp_free(t0);
14668 }
14669 break;
14670 #endif
14671 case 0x2a:
14672 switch (minor & 3) {
14673 case MADD_ACC:
14674 gen_muldiv(ctx, OPC_MADD, (ctx->opcode >> 14) & 3, rs, rt);
14675 break;
14676 case MADDU_ACC:
14677 gen_muldiv(ctx, OPC_MADDU, (ctx->opcode >> 14) & 3, rs, rt);
14678 break;
14679 case MSUB_ACC:
14680 gen_muldiv(ctx, OPC_MSUB, (ctx->opcode >> 14) & 3, rs, rt);
14681 break;
14682 case MSUBU_ACC:
14683 gen_muldiv(ctx, OPC_MSUBU, (ctx->opcode >> 14) & 3, rs, rt);
14684 break;
14685 default:
14686 goto pool32axf_invalid;
14687 }
14688 break;
14689 case 0x32:
14690 switch (minor & 3) {
14691 case MULT_ACC:
14692 gen_muldiv(ctx, OPC_MULT, (ctx->opcode >> 14) & 3, rs, rt);
14693 break;
14694 case MULTU_ACC:
14695 gen_muldiv(ctx, OPC_MULTU, (ctx->opcode >> 14) & 3, rs, rt);
14696 break;
14697 default:
14698 goto pool32axf_invalid;
14699 }
14700 break;
14701 case 0x2c:
14702 switch (minor) {
14703 case BITSWAP:
14704 check_insn(ctx, ISA_MIPS_R6);
14705 gen_bitswap(ctx, OPC_BITSWAP, rs, rt);
14706 break;
14707 case SEB:
14708 gen_bshfl(ctx, OPC_SEB, rs, rt);
14709 break;
14710 case SEH:
14711 gen_bshfl(ctx, OPC_SEH, rs, rt);
14712 break;
14713 case CLO:
14714 mips32_op = OPC_CLO;
14715 goto do_cl;
14716 case CLZ:
14717 mips32_op = OPC_CLZ;
14718 do_cl:
14719 check_insn(ctx, ISA_MIPS_R1);
14720 gen_cl(ctx, mips32_op, rt, rs);
14721 break;
14722 case RDHWR:
14723 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14724 gen_rdhwr(ctx, rt, rs, 0);
14725 break;
14726 case WSBH:
14727 gen_bshfl(ctx, OPC_WSBH, rs, rt);
14728 break;
14729 case MULT:
14730 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14731 mips32_op = OPC_MULT;
14732 goto do_mul;
14733 case MULTU:
14734 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14735 mips32_op = OPC_MULTU;
14736 goto do_mul;
14737 case DIV:
14738 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14739 mips32_op = OPC_DIV;
14740 goto do_div;
14741 case DIVU:
14742 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14743 mips32_op = OPC_DIVU;
14744 goto do_div;
14745 do_div:
14746 check_insn(ctx, ISA_MIPS_R1);
14747 gen_muldiv(ctx, mips32_op, 0, rs, rt);
14748 break;
14749 case MADD:
14750 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14751 mips32_op = OPC_MADD;
14752 goto do_mul;
14753 case MADDU:
14754 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14755 mips32_op = OPC_MADDU;
14756 goto do_mul;
14757 case MSUB:
14758 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14759 mips32_op = OPC_MSUB;
14760 goto do_mul;
14761 case MSUBU:
14762 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14763 mips32_op = OPC_MSUBU;
14764 do_mul:
14765 check_insn(ctx, ISA_MIPS_R1);
14766 gen_muldiv(ctx, mips32_op, 0, rs, rt);
14767 break;
14768 default:
14769 goto pool32axf_invalid;
14770 }
14771 break;
14772 case 0x34:
14773 switch (minor) {
14774 case MFC2:
14775 case MTC2:
14776 case MFHC2:
14777 case MTHC2:
14778 case CFC2:
14779 case CTC2:
14780 generate_exception_err(ctx, EXCP_CpU, 2);
14781 break;
14782 default:
14783 goto pool32axf_invalid;
14784 }
14785 break;
14786 case 0x3c:
14787 switch (minor) {
14788 case JALR: /* JALRC */
14789 case JALR_HB: /* JALRC_HB */
14790 if (ctx->insn_flags & ISA_MIPS_R6) {
14791 /* JALRC, JALRC_HB */
14792 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0);
14793 } else {
14794 /* JALR, JALR_HB */
14795 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 4);
14796 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14797 }
14798 break;
14799 case JALRS:
14800 case JALRS_HB:
14801 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14802 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2);
14803 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14804 break;
14805 default:
14806 goto pool32axf_invalid;
14807 }
14808 break;
14809 case 0x05:
14810 switch (minor) {
14811 case RDPGPR:
14812 check_cp0_enabled(ctx);
14813 check_insn(ctx, ISA_MIPS_R2);
14814 gen_load_srsgpr(rs, rt);
14815 break;
14816 case WRPGPR:
14817 check_cp0_enabled(ctx);
14818 check_insn(ctx, ISA_MIPS_R2);
14819 gen_store_srsgpr(rs, rt);
14820 break;
14821 default:
14822 goto pool32axf_invalid;
14823 }
14824 break;
14825 #ifndef CONFIG_USER_ONLY
14826 case 0x0d:
14827 switch (minor) {
14828 case TLBP:
14829 mips32_op = OPC_TLBP;
14830 goto do_cp0;
14831 case TLBR:
14832 mips32_op = OPC_TLBR;
14833 goto do_cp0;
14834 case TLBWI:
14835 mips32_op = OPC_TLBWI;
14836 goto do_cp0;
14837 case TLBWR:
14838 mips32_op = OPC_TLBWR;
14839 goto do_cp0;
14840 case TLBINV:
14841 mips32_op = OPC_TLBINV;
14842 goto do_cp0;
14843 case TLBINVF:
14844 mips32_op = OPC_TLBINVF;
14845 goto do_cp0;
14846 case WAIT:
14847 mips32_op = OPC_WAIT;
14848 goto do_cp0;
14849 case DERET:
14850 mips32_op = OPC_DERET;
14851 goto do_cp0;
14852 case ERET:
14853 mips32_op = OPC_ERET;
14854 do_cp0:
14855 gen_cp0(env, ctx, mips32_op, rt, rs);
14856 break;
14857 default:
14858 goto pool32axf_invalid;
14859 }
14860 break;
14861 case 0x1d:
14862 switch (minor) {
14863 case DI:
14864 check_cp0_enabled(ctx);
14865 {
14866 TCGv t0 = tcg_temp_new();
14867
14868 save_cpu_state(ctx, 1);
14869 gen_helper_di(t0, cpu_env);
14870 gen_store_gpr(t0, rs);
14871 /*
14872 * Stop translation as we may have switched the execution
14873 * mode.
14874 */
14875 ctx->base.is_jmp = DISAS_STOP;
14876 tcg_temp_free(t0);
14877 }
14878 break;
14879 case EI:
14880 check_cp0_enabled(ctx);
14881 {
14882 TCGv t0 = tcg_temp_new();
14883
14884 save_cpu_state(ctx, 1);
14885 gen_helper_ei(t0, cpu_env);
14886 gen_store_gpr(t0, rs);
14887 /*
14888 * DISAS_STOP isn't sufficient, we need to ensure we break out
14889 * of translated code to check for pending interrupts.
14890 */
14891 gen_save_pc(ctx->base.pc_next + 4);
14892 ctx->base.is_jmp = DISAS_EXIT;
14893 tcg_temp_free(t0);
14894 }
14895 break;
14896 default:
14897 goto pool32axf_invalid;
14898 }
14899 break;
14900 #endif
14901 case 0x2d:
14902 switch (minor) {
14903 case SYNC:
14904 gen_sync(extract32(ctx->opcode, 16, 5));
14905 break;
14906 case SYSCALL:
14907 generate_exception_end(ctx, EXCP_SYSCALL);
14908 break;
14909 case SDBBP:
14910 if (is_uhi(extract32(ctx->opcode, 16, 10))) {
14911 gen_helper_do_semihosting(cpu_env);
14912 } else {
14913 check_insn(ctx, ISA_MIPS_R1);
14914 if (ctx->hflags & MIPS_HFLAG_SBRI) {
14915 gen_reserved_instruction(ctx);
14916 } else {
14917 generate_exception_end(ctx, EXCP_DBp);
14918 }
14919 }
14920 break;
14921 default:
14922 goto pool32axf_invalid;
14923 }
14924 break;
14925 case 0x01:
14926 switch (minor & 3) {
14927 case MFHI_ACC:
14928 gen_HILO(ctx, OPC_MFHI, minor >> 2, rs);
14929 break;
14930 case MFLO_ACC:
14931 gen_HILO(ctx, OPC_MFLO, minor >> 2, rs);
14932 break;
14933 case MTHI_ACC:
14934 gen_HILO(ctx, OPC_MTHI, minor >> 2, rs);
14935 break;
14936 case MTLO_ACC:
14937 gen_HILO(ctx, OPC_MTLO, minor >> 2, rs);
14938 break;
14939 default:
14940 goto pool32axf_invalid;
14941 }
14942 break;
14943 case 0x35:
14944 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14945 switch (minor) {
14946 case MFHI32:
14947 gen_HILO(ctx, OPC_MFHI, 0, rs);
14948 break;
14949 case MFLO32:
14950 gen_HILO(ctx, OPC_MFLO, 0, rs);
14951 break;
14952 case MTHI32:
14953 gen_HILO(ctx, OPC_MTHI, 0, rs);
14954 break;
14955 case MTLO32:
14956 gen_HILO(ctx, OPC_MTLO, 0, rs);
14957 break;
14958 default:
14959 goto pool32axf_invalid;
14960 }
14961 break;
14962 default:
14963 pool32axf_invalid:
14964 MIPS_INVAL("pool32axf");
14965 gen_reserved_instruction(ctx);
14966 break;
14967 }
14968 }
14969
14970 /*
14971 * Values for microMIPS fmt field. Variable-width, depending on which
14972 * formats the instruction supports.
14973 */
14974 enum {
14975 FMT_SD_S = 0,
14976 FMT_SD_D = 1,
14977
14978 FMT_SDPS_S = 0,
14979 FMT_SDPS_D = 1,
14980 FMT_SDPS_PS = 2,
14981
14982 FMT_SWL_S = 0,
14983 FMT_SWL_W = 1,
14984 FMT_SWL_L = 2,
14985
14986 FMT_DWL_D = 0,
14987 FMT_DWL_W = 1,
14988 FMT_DWL_L = 2
14989 };
14990
14991 static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
14992 {
14993 int extension = (ctx->opcode >> 6) & 0x3ff;
14994 uint32_t mips32_op;
14995
14996 #define FLOAT_1BIT_FMT(opc, fmt) ((fmt << 8) | opc)
14997 #define FLOAT_2BIT_FMT(opc, fmt) ((fmt << 7) | opc)
14998 #define COND_FLOAT_MOV(opc, cond) ((cond << 7) | opc)
14999
15000 switch (extension) {
15001 case FLOAT_1BIT_FMT(CFC1, 0):
15002 mips32_op = OPC_CFC1;
15003 goto do_cp1;
15004 case FLOAT_1BIT_FMT(CTC1, 0):
15005 mips32_op = OPC_CTC1;
15006 goto do_cp1;
15007 case FLOAT_1BIT_FMT(MFC1, 0):
15008 mips32_op = OPC_MFC1;
15009 goto do_cp1;
15010 case FLOAT_1BIT_FMT(MTC1, 0):
15011 mips32_op = OPC_MTC1;
15012 goto do_cp1;
15013 case FLOAT_1BIT_FMT(MFHC1, 0):
15014 mips32_op = OPC_MFHC1;
15015 goto do_cp1;
15016 case FLOAT_1BIT_FMT(MTHC1, 0):
15017 mips32_op = OPC_MTHC1;
15018 do_cp1:
15019 gen_cp1(ctx, mips32_op, rt, rs);
15020 break;
15021
15022 /* Reciprocal square root */
15023 case FLOAT_1BIT_FMT(RSQRT_FMT, FMT_SD_S):
15024 mips32_op = OPC_RSQRT_S;
15025 goto do_unaryfp;
15026 case FLOAT_1BIT_FMT(RSQRT_FMT, FMT_SD_D):
15027 mips32_op = OPC_RSQRT_D;
15028 goto do_unaryfp;
15029
15030 /* Square root */
15031 case FLOAT_1BIT_FMT(SQRT_FMT, FMT_SD_S):
15032 mips32_op = OPC_SQRT_S;
15033 goto do_unaryfp;
15034 case FLOAT_1BIT_FMT(SQRT_FMT, FMT_SD_D):
15035 mips32_op = OPC_SQRT_D;
15036 goto do_unaryfp;
15037
15038 /* Reciprocal */
15039 case FLOAT_1BIT_FMT(RECIP_FMT, FMT_SD_S):
15040 mips32_op = OPC_RECIP_S;
15041 goto do_unaryfp;
15042 case FLOAT_1BIT_FMT(RECIP_FMT, FMT_SD_D):
15043 mips32_op = OPC_RECIP_D;
15044 goto do_unaryfp;
15045
15046 /* Floor */
15047 case FLOAT_1BIT_FMT(FLOOR_L, FMT_SD_S):
15048 mips32_op = OPC_FLOOR_L_S;
15049 goto do_unaryfp;
15050 case FLOAT_1BIT_FMT(FLOOR_L, FMT_SD_D):
15051 mips32_op = OPC_FLOOR_L_D;
15052 goto do_unaryfp;
15053 case FLOAT_1BIT_FMT(FLOOR_W, FMT_SD_S):
15054 mips32_op = OPC_FLOOR_W_S;
15055 goto do_unaryfp;
15056 case FLOAT_1BIT_FMT(FLOOR_W, FMT_SD_D):
15057 mips32_op = OPC_FLOOR_W_D;
15058 goto do_unaryfp;
15059
15060 /* Ceiling */
15061 case FLOAT_1BIT_FMT(CEIL_L, FMT_SD_S):
15062 mips32_op = OPC_CEIL_L_S;
15063 goto do_unaryfp;
15064 case FLOAT_1BIT_FMT(CEIL_L, FMT_SD_D):
15065 mips32_op = OPC_CEIL_L_D;
15066 goto do_unaryfp;
15067 case FLOAT_1BIT_FMT(CEIL_W, FMT_SD_S):
15068 mips32_op = OPC_CEIL_W_S;
15069 goto do_unaryfp;
15070 case FLOAT_1BIT_FMT(CEIL_W, FMT_SD_D):
15071 mips32_op = OPC_CEIL_W_D;
15072 goto do_unaryfp;
15073
15074 /* Truncation */
15075 case FLOAT_1BIT_FMT(TRUNC_L, FMT_SD_S):
15076 mips32_op = OPC_TRUNC_L_S;
15077 goto do_unaryfp;
15078 case FLOAT_1BIT_FMT(TRUNC_L, FMT_SD_D):
15079 mips32_op = OPC_TRUNC_L_D;
15080 goto do_unaryfp;
15081 case FLOAT_1BIT_FMT(TRUNC_W, FMT_SD_S):
15082 mips32_op = OPC_TRUNC_W_S;
15083 goto do_unaryfp;
15084 case FLOAT_1BIT_FMT(TRUNC_W, FMT_SD_D):
15085 mips32_op = OPC_TRUNC_W_D;
15086 goto do_unaryfp;
15087
15088 /* Round */
15089 case FLOAT_1BIT_FMT(ROUND_L, FMT_SD_S):
15090 mips32_op = OPC_ROUND_L_S;
15091 goto do_unaryfp;
15092 case FLOAT_1BIT_FMT(ROUND_L, FMT_SD_D):
15093 mips32_op = OPC_ROUND_L_D;
15094 goto do_unaryfp;
15095 case FLOAT_1BIT_FMT(ROUND_W, FMT_SD_S):
15096 mips32_op = OPC_ROUND_W_S;
15097 goto do_unaryfp;
15098 case FLOAT_1BIT_FMT(ROUND_W, FMT_SD_D):
15099 mips32_op = OPC_ROUND_W_D;
15100 goto do_unaryfp;
15101
15102 /* Integer to floating-point conversion */
15103 case FLOAT_1BIT_FMT(CVT_L, FMT_SD_S):
15104 mips32_op = OPC_CVT_L_S;
15105 goto do_unaryfp;
15106 case FLOAT_1BIT_FMT(CVT_L, FMT_SD_D):
15107 mips32_op = OPC_CVT_L_D;
15108 goto do_unaryfp;
15109 case FLOAT_1BIT_FMT(CVT_W, FMT_SD_S):
15110 mips32_op = OPC_CVT_W_S;
15111 goto do_unaryfp;
15112 case FLOAT_1BIT_FMT(CVT_W, FMT_SD_D):
15113 mips32_op = OPC_CVT_W_D;
15114 goto do_unaryfp;
15115
15116 /* Paired-foo conversions */
15117 case FLOAT_1BIT_FMT(CVT_S_PL, 0):
15118 mips32_op = OPC_CVT_S_PL;
15119 goto do_unaryfp;
15120 case FLOAT_1BIT_FMT(CVT_S_PU, 0):
15121 mips32_op = OPC_CVT_S_PU;
15122 goto do_unaryfp;
15123 case FLOAT_1BIT_FMT(CVT_PW_PS, 0):
15124 mips32_op = OPC_CVT_PW_PS;
15125 goto do_unaryfp;
15126 case FLOAT_1BIT_FMT(CVT_PS_PW, 0):
15127 mips32_op = OPC_CVT_PS_PW;
15128 goto do_unaryfp;
15129
15130 /* Floating-point moves */
15131 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_S):
15132 mips32_op = OPC_MOV_S;
15133 goto do_unaryfp;
15134 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_D):
15135 mips32_op = OPC_MOV_D;
15136 goto do_unaryfp;
15137 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_PS):
15138 mips32_op = OPC_MOV_PS;
15139 goto do_unaryfp;
15140
15141 /* Absolute value */
15142 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_S):
15143 mips32_op = OPC_ABS_S;
15144 goto do_unaryfp;
15145 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_D):
15146 mips32_op = OPC_ABS_D;
15147 goto do_unaryfp;
15148 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_PS):
15149 mips32_op = OPC_ABS_PS;
15150 goto do_unaryfp;
15151
15152 /* Negation */
15153 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_S):
15154 mips32_op = OPC_NEG_S;
15155 goto do_unaryfp;
15156 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_D):
15157 mips32_op = OPC_NEG_D;
15158 goto do_unaryfp;
15159 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_PS):
15160 mips32_op = OPC_NEG_PS;
15161 goto do_unaryfp;
15162
15163 /* Reciprocal square root step */
15164 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_S):
15165 mips32_op = OPC_RSQRT1_S;
15166 goto do_unaryfp;
15167 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_D):
15168 mips32_op = OPC_RSQRT1_D;
15169 goto do_unaryfp;
15170 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_PS):
15171 mips32_op = OPC_RSQRT1_PS;
15172 goto do_unaryfp;
15173
15174 /* Reciprocal step */
15175 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_S):
15176 mips32_op = OPC_RECIP1_S;
15177 goto do_unaryfp;
15178 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_D):
15179 mips32_op = OPC_RECIP1_S;
15180 goto do_unaryfp;
15181 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_PS):
15182 mips32_op = OPC_RECIP1_PS;
15183 goto do_unaryfp;
15184
15185 /* Conversions from double */
15186 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_S):
15187 mips32_op = OPC_CVT_D_S;
15188 goto do_unaryfp;
15189 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_W):
15190 mips32_op = OPC_CVT_D_W;
15191 goto do_unaryfp;
15192 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_L):
15193 mips32_op = OPC_CVT_D_L;
15194 goto do_unaryfp;
15195
15196 /* Conversions from single */
15197 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_D):
15198 mips32_op = OPC_CVT_S_D;
15199 goto do_unaryfp;
15200 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_W):
15201 mips32_op = OPC_CVT_S_W;
15202 goto do_unaryfp;
15203 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_L):
15204 mips32_op = OPC_CVT_S_L;
15205 do_unaryfp:
15206 gen_farith(ctx, mips32_op, -1, rs, rt, 0);
15207 break;
15208
15209 /* Conditional moves on floating-point codes */
15210 case COND_FLOAT_MOV(MOVT, 0):
15211 case COND_FLOAT_MOV(MOVT, 1):
15212 case COND_FLOAT_MOV(MOVT, 2):
15213 case COND_FLOAT_MOV(MOVT, 3):
15214 case COND_FLOAT_MOV(MOVT, 4):
15215 case COND_FLOAT_MOV(MOVT, 5):
15216 case COND_FLOAT_MOV(MOVT, 6):
15217 case COND_FLOAT_MOV(MOVT, 7):
15218 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15219 gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 1);
15220 break;
15221 case COND_FLOAT_MOV(MOVF, 0):
15222 case COND_FLOAT_MOV(MOVF, 1):
15223 case COND_FLOAT_MOV(MOVF, 2):
15224 case COND_FLOAT_MOV(MOVF, 3):
15225 case COND_FLOAT_MOV(MOVF, 4):
15226 case COND_FLOAT_MOV(MOVF, 5):
15227 case COND_FLOAT_MOV(MOVF, 6):
15228 case COND_FLOAT_MOV(MOVF, 7):
15229 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15230 gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 0);
15231 break;
15232 default:
15233 MIPS_INVAL("pool32fxf");
15234 gen_reserved_instruction(ctx);
15235 break;
15236 }
15237 }
15238
15239 static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
15240 {
15241 int32_t offset;
15242 uint16_t insn;
15243 int rt, rs, rd, rr;
15244 int16_t imm;
15245 uint32_t op, minor, minor2, mips32_op;
15246 uint32_t cond, fmt, cc;
15247
15248 insn = translator_lduw(env, ctx->base.pc_next + 2);
15249 ctx->opcode = (ctx->opcode << 16) | insn;
15250
15251 rt = (ctx->opcode >> 21) & 0x1f;
15252 rs = (ctx->opcode >> 16) & 0x1f;
15253 rd = (ctx->opcode >> 11) & 0x1f;
15254 rr = (ctx->opcode >> 6) & 0x1f;
15255 imm = (int16_t) ctx->opcode;
15256
15257 op = (ctx->opcode >> 26) & 0x3f;
15258 switch (op) {
15259 case POOL32A:
15260 minor = ctx->opcode & 0x3f;
15261 switch (minor) {
15262 case 0x00:
15263 minor = (ctx->opcode >> 6) & 0xf;
15264 switch (minor) {
15265 case SLL32:
15266 mips32_op = OPC_SLL;
15267 goto do_shifti;
15268 case SRA:
15269 mips32_op = OPC_SRA;
15270 goto do_shifti;
15271 case SRL32:
15272 mips32_op = OPC_SRL;
15273 goto do_shifti;
15274 case ROTR:
15275 mips32_op = OPC_ROTR;
15276 do_shifti:
15277 gen_shift_imm(ctx, mips32_op, rt, rs, rd);
15278 break;
15279 case SELEQZ:
15280 check_insn(ctx, ISA_MIPS_R6);
15281 gen_cond_move(ctx, OPC_SELEQZ, rd, rs, rt);
15282 break;
15283 case SELNEZ:
15284 check_insn(ctx, ISA_MIPS_R6);
15285 gen_cond_move(ctx, OPC_SELNEZ, rd, rs, rt);
15286 break;
15287 case R6_RDHWR:
15288 check_insn(ctx, ISA_MIPS_R6);
15289 gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3));
15290 break;
15291 default:
15292 goto pool32a_invalid;
15293 }
15294 break;
15295 case 0x10:
15296 minor = (ctx->opcode >> 6) & 0xf;
15297 switch (minor) {
15298 /* Arithmetic */
15299 case ADD:
15300 mips32_op = OPC_ADD;
15301 goto do_arith;
15302 case ADDU32:
15303 mips32_op = OPC_ADDU;
15304 goto do_arith;
15305 case SUB:
15306 mips32_op = OPC_SUB;
15307 goto do_arith;
15308 case SUBU32:
15309 mips32_op = OPC_SUBU;
15310 goto do_arith;
15311 case MUL:
15312 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15313 mips32_op = OPC_MUL;
15314 do_arith:
15315 gen_arith(ctx, mips32_op, rd, rs, rt);
15316 break;
15317 /* Shifts */
15318 case SLLV:
15319 mips32_op = OPC_SLLV;
15320 goto do_shift;
15321 case SRLV:
15322 mips32_op = OPC_SRLV;
15323 goto do_shift;
15324 case SRAV:
15325 mips32_op = OPC_SRAV;
15326 goto do_shift;
15327 case ROTRV:
15328 mips32_op = OPC_ROTRV;
15329 do_shift:
15330 gen_shift(ctx, mips32_op, rd, rs, rt);
15331 break;
15332 /* Logical operations */
15333 case AND:
15334 mips32_op = OPC_AND;
15335 goto do_logic;
15336 case OR32:
15337 mips32_op = OPC_OR;
15338 goto do_logic;
15339 case NOR:
15340 mips32_op = OPC_NOR;
15341 goto do_logic;
15342 case XOR32:
15343 mips32_op = OPC_XOR;
15344 do_logic:
15345 gen_logic(ctx, mips32_op, rd, rs, rt);
15346 break;
15347 /* Set less than */
15348 case SLT:
15349 mips32_op = OPC_SLT;
15350 goto do_slt;
15351 case SLTU:
15352 mips32_op = OPC_SLTU;
15353 do_slt:
15354 gen_slt(ctx, mips32_op, rd, rs, rt);
15355 break;
15356 default:
15357 goto pool32a_invalid;
15358 }
15359 break;
15360 case 0x18:
15361 minor = (ctx->opcode >> 6) & 0xf;
15362 switch (minor) {
15363 /* Conditional moves */
15364 case MOVN: /* MUL */
15365 if (ctx->insn_flags & ISA_MIPS_R6) {
15366 /* MUL */
15367 gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt);
15368 } else {
15369 /* MOVN */
15370 gen_cond_move(ctx, OPC_MOVN, rd, rs, rt);
15371 }
15372 break;
15373 case MOVZ: /* MUH */
15374 if (ctx->insn_flags & ISA_MIPS_R6) {
15375 /* MUH */
15376 gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt);
15377 } else {
15378 /* MOVZ */
15379 gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt);
15380 }
15381 break;
15382 case MULU:
15383 check_insn(ctx, ISA_MIPS_R6);
15384 gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt);
15385 break;
15386 case MUHU:
15387 check_insn(ctx, ISA_MIPS_R6);
15388 gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt);
15389 break;
15390 case LWXS: /* DIV */
15391 if (ctx->insn_flags & ISA_MIPS_R6) {
15392 /* DIV */
15393 gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt);
15394 } else {
15395 /* LWXS */
15396 gen_ldxs(ctx, rs, rt, rd);
15397 }
15398 break;
15399 case MOD:
15400 check_insn(ctx, ISA_MIPS_R6);
15401 gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt);
15402 break;
15403 case R6_DIVU:
15404 check_insn(ctx, ISA_MIPS_R6);
15405 gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt);
15406 break;
15407 case MODU:
15408 check_insn(ctx, ISA_MIPS_R6);
15409 gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt);
15410 break;
15411 default:
15412 goto pool32a_invalid;
15413 }
15414 break;
15415 case INS:
15416 gen_bitops(ctx, OPC_INS, rt, rs, rr, rd);
15417 return;
15418 case LSA:
15419 check_insn(ctx, ISA_MIPS_R6);
15420 gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2));
15421 break;
15422 case ALIGN:
15423 check_insn(ctx, ISA_MIPS_R6);
15424 gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2));
15425 break;
15426 case EXT:
15427 gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd);
15428 return;
15429 case POOL32AXF:
15430 gen_pool32axf(env, ctx, rt, rs);
15431 break;
15432 case BREAK32:
15433 generate_exception_end(ctx, EXCP_BREAK);
15434 break;
15435 case SIGRIE:
15436 check_insn(ctx, ISA_MIPS_R6);
15437 gen_reserved_instruction(ctx);
15438 break;
15439 default:
15440 pool32a_invalid:
15441 MIPS_INVAL("pool32a");
15442 gen_reserved_instruction(ctx);
15443 break;
15444 }
15445 break;
15446 case POOL32B:
15447 minor = (ctx->opcode >> 12) & 0xf;
15448 switch (minor) {
15449 case CACHE:
15450 check_cp0_enabled(ctx);
15451 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
15452 gen_cache_operation(ctx, rt, rs, imm);
15453 }
15454 break;
15455 case LWC2:
15456 case SWC2:
15457 /* COP2: Not implemented. */
15458 generate_exception_err(ctx, EXCP_CpU, 2);
15459 break;
15460 #ifdef TARGET_MIPS64
15461 case LDP:
15462 case SDP:
15463 check_insn(ctx, ISA_MIPS3);
15464 check_mips_64(ctx);
15465 #endif
15466 /* fall through */
15467 case LWP:
15468 case SWP:
15469 gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
15470 break;
15471 #ifdef TARGET_MIPS64
15472 case LDM:
15473 case SDM:
15474 check_insn(ctx, ISA_MIPS3);
15475 check_mips_64(ctx);
15476 #endif
15477 /* fall through */
15478 case LWM32:
15479 case SWM32:
15480 gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
15481 break;
15482 default:
15483 MIPS_INVAL("pool32b");
15484 gen_reserved_instruction(ctx);
15485 break;
15486 }
15487 break;
15488 case POOL32F:
15489 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
15490 minor = ctx->opcode & 0x3f;
15491 check_cp1_enabled(ctx);
15492 switch (minor) {
15493 case ALNV_PS:
15494 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15495 mips32_op = OPC_ALNV_PS;
15496 goto do_madd;
15497 case MADD_S:
15498 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15499 mips32_op = OPC_MADD_S;
15500 goto do_madd;
15501 case MADD_D:
15502 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15503 mips32_op = OPC_MADD_D;
15504 goto do_madd;
15505 case MADD_PS:
15506 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15507 mips32_op = OPC_MADD_PS;
15508 goto do_madd;
15509 case MSUB_S:
15510 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15511 mips32_op = OPC_MSUB_S;
15512 goto do_madd;
15513 case MSUB_D:
15514 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15515 mips32_op = OPC_MSUB_D;
15516 goto do_madd;
15517 case MSUB_PS:
15518 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15519 mips32_op = OPC_MSUB_PS;
15520 goto do_madd;
15521 case NMADD_S:
15522 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15523 mips32_op = OPC_NMADD_S;
15524 goto do_madd;
15525 case NMADD_D:
15526 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15527 mips32_op = OPC_NMADD_D;
15528 goto do_madd;
15529 case NMADD_PS:
15530 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15531 mips32_op = OPC_NMADD_PS;
15532 goto do_madd;
15533 case NMSUB_S:
15534 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15535 mips32_op = OPC_NMSUB_S;
15536 goto do_madd;
15537 case NMSUB_D:
15538 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15539 mips32_op = OPC_NMSUB_D;
15540 goto do_madd;
15541 case NMSUB_PS:
15542 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15543 mips32_op = OPC_NMSUB_PS;
15544 do_madd:
15545 gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt);
15546 break;
15547 case CABS_COND_FMT:
15548 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15549 cond = (ctx->opcode >> 6) & 0xf;
15550 cc = (ctx->opcode >> 13) & 0x7;
15551 fmt = (ctx->opcode >> 10) & 0x3;
15552 switch (fmt) {
15553 case 0x0:
15554 gen_cmpabs_s(ctx, cond, rt, rs, cc);
15555 break;
15556 case 0x1:
15557 gen_cmpabs_d(ctx, cond, rt, rs, cc);
15558 break;
15559 case 0x2:
15560 gen_cmpabs_ps(ctx, cond, rt, rs, cc);
15561 break;
15562 default:
15563 goto pool32f_invalid;
15564 }
15565 break;
15566 case C_COND_FMT:
15567 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15568 cond = (ctx->opcode >> 6) & 0xf;
15569 cc = (ctx->opcode >> 13) & 0x7;
15570 fmt = (ctx->opcode >> 10) & 0x3;
15571 switch (fmt) {
15572 case 0x0:
15573 gen_cmp_s(ctx, cond, rt, rs, cc);
15574 break;
15575 case 0x1:
15576 gen_cmp_d(ctx, cond, rt, rs, cc);
15577 break;
15578 case 0x2:
15579 gen_cmp_ps(ctx, cond, rt, rs, cc);
15580 break;
15581 default:
15582 goto pool32f_invalid;
15583 }
15584 break;
15585 case CMP_CONDN_S:
15586 check_insn(ctx, ISA_MIPS_R6);
15587 gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
15588 break;
15589 case CMP_CONDN_D:
15590 check_insn(ctx, ISA_MIPS_R6);
15591 gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
15592 break;
15593 case POOL32FXF:
15594 gen_pool32fxf(ctx, rt, rs);
15595 break;
15596 case 0x00:
15597 /* PLL foo */
15598 switch ((ctx->opcode >> 6) & 0x7) {
15599 case PLL_PS:
15600 mips32_op = OPC_PLL_PS;
15601 goto do_ps;
15602 case PLU_PS:
15603 mips32_op = OPC_PLU_PS;
15604 goto do_ps;
15605 case PUL_PS:
15606 mips32_op = OPC_PUL_PS;
15607 goto do_ps;
15608 case PUU_PS:
15609 mips32_op = OPC_PUU_PS;
15610 goto do_ps;
15611 case CVT_PS_S:
15612 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15613 mips32_op = OPC_CVT_PS_S;
15614 do_ps:
15615 gen_farith(ctx, mips32_op, rt, rs, rd, 0);
15616 break;
15617 default:
15618 goto pool32f_invalid;
15619 }
15620 break;
15621 case MIN_FMT:
15622 check_insn(ctx, ISA_MIPS_R6);
15623 switch ((ctx->opcode >> 9) & 0x3) {
15624 case FMT_SDPS_S:
15625 gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0);
15626 break;
15627 case FMT_SDPS_D:
15628 gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0);
15629 break;
15630 default:
15631 goto pool32f_invalid;
15632 }
15633 break;
15634 case 0x08:
15635 /* [LS][WDU]XC1 */
15636 switch ((ctx->opcode >> 6) & 0x7) {
15637 case LWXC1:
15638 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15639 mips32_op = OPC_LWXC1;
15640 goto do_ldst_cp1;
15641 case SWXC1:
15642 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15643 mips32_op = OPC_SWXC1;
15644 goto do_ldst_cp1;
15645 case LDXC1:
15646 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15647 mips32_op = OPC_LDXC1;
15648 goto do_ldst_cp1;
15649 case SDXC1:
15650 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15651 mips32_op = OPC_SDXC1;
15652 goto do_ldst_cp1;
15653 case LUXC1:
15654 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15655 mips32_op = OPC_LUXC1;
15656 goto do_ldst_cp1;
15657 case SUXC1:
15658 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15659 mips32_op = OPC_SUXC1;
15660 do_ldst_cp1:
15661 gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs);
15662 break;
15663 default:
15664 goto pool32f_invalid;
15665 }
15666 break;
15667 case MAX_FMT:
15668 check_insn(ctx, ISA_MIPS_R6);
15669 switch ((ctx->opcode >> 9) & 0x3) {
15670 case FMT_SDPS_S:
15671 gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0);
15672 break;
15673 case FMT_SDPS_D:
15674 gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0);
15675 break;
15676 default:
15677 goto pool32f_invalid;
15678 }
15679 break;
15680 case 0x18:
15681 /* 3D insns */
15682 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15683 fmt = (ctx->opcode >> 9) & 0x3;
15684 switch ((ctx->opcode >> 6) & 0x7) {
15685 case RSQRT2_FMT:
15686 switch (fmt) {
15687 case FMT_SDPS_S:
15688 mips32_op = OPC_RSQRT2_S;
15689 goto do_3d;
15690 case FMT_SDPS_D:
15691 mips32_op = OPC_RSQRT2_D;
15692 goto do_3d;
15693 case FMT_SDPS_PS:
15694 mips32_op = OPC_RSQRT2_PS;
15695 goto do_3d;
15696 default:
15697 goto pool32f_invalid;
15698 }
15699 break;
15700 case RECIP2_FMT:
15701 switch (fmt) {
15702 case FMT_SDPS_S:
15703 mips32_op = OPC_RECIP2_S;
15704 goto do_3d;
15705 case FMT_SDPS_D:
15706 mips32_op = OPC_RECIP2_D;
15707 goto do_3d;
15708 case FMT_SDPS_PS:
15709 mips32_op = OPC_RECIP2_PS;
15710 goto do_3d;
15711 default:
15712 goto pool32f_invalid;
15713 }
15714 break;
15715 case ADDR_PS:
15716 mips32_op = OPC_ADDR_PS;
15717 goto do_3d;
15718 case MULR_PS:
15719 mips32_op = OPC_MULR_PS;
15720 do_3d:
15721 gen_farith(ctx, mips32_op, rt, rs, rd, 0);
15722 break;
15723 default:
15724 goto pool32f_invalid;
15725 }
15726 break;
15727 case 0x20:
15728 /* MOV[FT].fmt, PREFX, RINT.fmt, CLASS.fmt*/
15729 cc = (ctx->opcode >> 13) & 0x7;
15730 fmt = (ctx->opcode >> 9) & 0x3;
15731 switch ((ctx->opcode >> 6) & 0x7) {
15732 case MOVF_FMT: /* RINT_FMT */
15733 if (ctx->insn_flags & ISA_MIPS_R6) {
15734 /* RINT_FMT */
15735 switch (fmt) {
15736 case FMT_SDPS_S:
15737 gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0);
15738 break;
15739 case FMT_SDPS_D:
15740 gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0);
15741 break;
15742 default:
15743 goto pool32f_invalid;
15744 }
15745 } else {
15746 /* MOVF_FMT */
15747 switch (fmt) {
15748 case FMT_SDPS_S:
15749 gen_movcf_s(ctx, rs, rt, cc, 0);
15750 break;
15751 case FMT_SDPS_D:
15752 gen_movcf_d(ctx, rs, rt, cc, 0);
15753 break;
15754 case FMT_SDPS_PS:
15755 check_ps(ctx);
15756 gen_movcf_ps(ctx, rs, rt, cc, 0);
15757 break;
15758 default:
15759 goto pool32f_invalid;
15760 }
15761 }
15762 break;
15763 case MOVT_FMT: /* CLASS_FMT */
15764 if (ctx->insn_flags & ISA_MIPS_R6) {
15765 /* CLASS_FMT */
15766 switch (fmt) {
15767 case FMT_SDPS_S:
15768 gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0);
15769 break;
15770 case FMT_SDPS_D:
15771 gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0);
15772 break;
15773 default:
15774 goto pool32f_invalid;
15775 }
15776 } else {
15777 /* MOVT_FMT */
15778 switch (fmt) {
15779 case FMT_SDPS_S:
15780 gen_movcf_s(ctx, rs, rt, cc, 1);
15781 break;
15782 case FMT_SDPS_D:
15783 gen_movcf_d(ctx, rs, rt, cc, 1);
15784 break;
15785 case FMT_SDPS_PS:
15786 check_ps(ctx);
15787 gen_movcf_ps(ctx, rs, rt, cc, 1);
15788 break;
15789 default:
15790 goto pool32f_invalid;
15791 }
15792 }
15793 break;
15794 case PREFX:
15795 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15796 break;
15797 default:
15798 goto pool32f_invalid;
15799 }
15800 break;
15801 #define FINSN_3ARG_SDPS(prfx) \
15802 switch ((ctx->opcode >> 8) & 0x3) { \
15803 case FMT_SDPS_S: \
15804 mips32_op = OPC_##prfx##_S; \
15805 goto do_fpop; \
15806 case FMT_SDPS_D: \
15807 mips32_op = OPC_##prfx##_D; \
15808 goto do_fpop; \
15809 case FMT_SDPS_PS: \
15810 check_ps(ctx); \
15811 mips32_op = OPC_##prfx##_PS; \
15812 goto do_fpop; \
15813 default: \
15814 goto pool32f_invalid; \
15815 }
15816 case MINA_FMT:
15817 check_insn(ctx, ISA_MIPS_R6);
15818 switch ((ctx->opcode >> 9) & 0x3) {
15819 case FMT_SDPS_S:
15820 gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0);
15821 break;
15822 case FMT_SDPS_D:
15823 gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0);
15824 break;
15825 default:
15826 goto pool32f_invalid;
15827 }
15828 break;
15829 case MAXA_FMT:
15830 check_insn(ctx, ISA_MIPS_R6);
15831 switch ((ctx->opcode >> 9) & 0x3) {
15832 case FMT_SDPS_S:
15833 gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0);
15834 break;
15835 case FMT_SDPS_D:
15836 gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0);
15837 break;
15838 default:
15839 goto pool32f_invalid;
15840 }
15841 break;
15842 case 0x30:
15843 /* regular FP ops */
15844 switch ((ctx->opcode >> 6) & 0x3) {
15845 case ADD_FMT:
15846 FINSN_3ARG_SDPS(ADD);
15847 break;
15848 case SUB_FMT:
15849 FINSN_3ARG_SDPS(SUB);
15850 break;
15851 case MUL_FMT:
15852 FINSN_3ARG_SDPS(MUL);
15853 break;
15854 case DIV_FMT:
15855 fmt = (ctx->opcode >> 8) & 0x3;
15856 if (fmt == 1) {
15857 mips32_op = OPC_DIV_D;
15858 } else if (fmt == 0) {
15859 mips32_op = OPC_DIV_S;
15860 } else {
15861 goto pool32f_invalid;
15862 }
15863 goto do_fpop;
15864 default:
15865 goto pool32f_invalid;
15866 }
15867 break;
15868 case 0x38:
15869 /* cmovs */
15870 switch ((ctx->opcode >> 6) & 0x7) {
15871 case MOVN_FMT: /* SELEQZ_FMT */
15872 if (ctx->insn_flags & ISA_MIPS_R6) {
15873 /* SELEQZ_FMT */
15874 switch ((ctx->opcode >> 9) & 0x3) {
15875 case FMT_SDPS_S:
15876 gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
15877 break;
15878 case FMT_SDPS_D:
15879 gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
15880 break;
15881 default:
15882 goto pool32f_invalid;
15883 }
15884 } else {
15885 /* MOVN_FMT */
15886 FINSN_3ARG_SDPS(MOVN);
15887 }
15888 break;
15889 case MOVN_FMT_04:
15890 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15891 FINSN_3ARG_SDPS(MOVN);
15892 break;
15893 case MOVZ_FMT: /* SELNEZ_FMT */
15894 if (ctx->insn_flags & ISA_MIPS_R6) {
15895 /* SELNEZ_FMT */
15896 switch ((ctx->opcode >> 9) & 0x3) {
15897 case FMT_SDPS_S:
15898 gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
15899 break;
15900 case FMT_SDPS_D:
15901 gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
15902 break;
15903 default:
15904 goto pool32f_invalid;
15905 }
15906 } else {
15907 /* MOVZ_FMT */
15908 FINSN_3ARG_SDPS(MOVZ);
15909 }
15910 break;
15911 case MOVZ_FMT_05:
15912 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15913 FINSN_3ARG_SDPS(MOVZ);
15914 break;
15915 case SEL_FMT:
15916 check_insn(ctx, ISA_MIPS_R6);
15917 switch ((ctx->opcode >> 9) & 0x3) {
15918 case FMT_SDPS_S:
15919 gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs);
15920 break;
15921 case FMT_SDPS_D:
15922 gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs);
15923 break;
15924 default:
15925 goto pool32f_invalid;
15926 }
15927 break;
15928 case MADDF_FMT:
15929 check_insn(ctx, ISA_MIPS_R6);
15930 switch ((ctx->opcode >> 9) & 0x3) {
15931 case FMT_SDPS_S:
15932 mips32_op = OPC_MADDF_S;
15933 goto do_fpop;
15934 case FMT_SDPS_D:
15935 mips32_op = OPC_MADDF_D;
15936 goto do_fpop;
15937 default:
15938 goto pool32f_invalid;
15939 }
15940 break;
15941 case MSUBF_FMT:
15942 check_insn(ctx, ISA_MIPS_R6);
15943 switch ((ctx->opcode >> 9) & 0x3) {
15944 case FMT_SDPS_S:
15945 mips32_op = OPC_MSUBF_S;
15946 goto do_fpop;
15947 case FMT_SDPS_D:
15948 mips32_op = OPC_MSUBF_D;
15949 goto do_fpop;
15950 default:
15951 goto pool32f_invalid;
15952 }
15953 break;
15954 default:
15955 goto pool32f_invalid;
15956 }
15957 break;
15958 do_fpop:
15959 gen_farith(ctx, mips32_op, rt, rs, rd, 0);
15960 break;
15961 default:
15962 pool32f_invalid:
15963 MIPS_INVAL("pool32f");
15964 gen_reserved_instruction(ctx);
15965 break;
15966 }
15967 } else {
15968 generate_exception_err(ctx, EXCP_CpU, 1);
15969 }
15970 break;
15971 case POOL32I:
15972 minor = (ctx->opcode >> 21) & 0x1f;
15973 switch (minor) {
15974 case BLTZ:
15975 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15976 gen_compute_branch(ctx, OPC_BLTZ, 4, rs, -1, imm << 1, 4);
15977 break;
15978 case BLTZAL:
15979 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15980 gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 4);
15981 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
15982 break;
15983 case BLTZALS:
15984 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15985 gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 2);
15986 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
15987 break;
15988 case BGEZ:
15989 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15990 gen_compute_branch(ctx, OPC_BGEZ, 4, rs, -1, imm << 1, 4);
15991 break;
15992 case BGEZAL:
15993 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15994 gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 4);
15995 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
15996 break;
15997 case BGEZALS:
15998 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15999 gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 2);
16000 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
16001 break;
16002 case BLEZ:
16003 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16004 gen_compute_branch(ctx, OPC_BLEZ, 4, rs, -1, imm << 1, 4);
16005 break;
16006 case BGTZ:
16007 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16008 gen_compute_branch(ctx, OPC_BGTZ, 4, rs, -1, imm << 1, 4);
16009 break;
16010
16011 /* Traps */
16012 case TLTI: /* BC1EQZC */
16013 if (ctx->insn_flags & ISA_MIPS_R6) {
16014 /* BC1EQZC */
16015 check_cp1_enabled(ctx);
16016 gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rs, imm << 1, 0);
16017 } else {
16018 /* TLTI */
16019 mips32_op = OPC_TLTI;
16020 goto do_trapi;
16021 }
16022 break;
16023 case TGEI: /* BC1NEZC */
16024 if (ctx->insn_flags & ISA_MIPS_R6) {
16025 /* BC1NEZC */
16026 check_cp1_enabled(ctx);
16027 gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rs, imm << 1, 0);
16028 } else {
16029 /* TGEI */
16030 mips32_op = OPC_TGEI;
16031 goto do_trapi;
16032 }
16033 break;
16034 case TLTIU:
16035 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16036 mips32_op = OPC_TLTIU;
16037 goto do_trapi;
16038 case TGEIU:
16039 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16040 mips32_op = OPC_TGEIU;
16041 goto do_trapi;
16042 case TNEI: /* SYNCI */
16043 if (ctx->insn_flags & ISA_MIPS_R6) {
16044 /* SYNCI */
16045 /*
16046 * Break the TB to be able to sync copied instructions
16047 * immediately.
16048 */
16049 ctx->base.is_jmp = DISAS_STOP;
16050 } else {
16051 /* TNEI */
16052 mips32_op = OPC_TNEI;
16053 goto do_trapi;
16054 }
16055 break;
16056 case TEQI:
16057 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16058 mips32_op = OPC_TEQI;
16059 do_trapi:
16060 gen_trap(ctx, mips32_op, rs, -1, imm);
16061 break;
16062
16063 case BNEZC:
16064 case BEQZC:
16065 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16066 gen_compute_branch(ctx, minor == BNEZC ? OPC_BNE : OPC_BEQ,
16067 4, rs, 0, imm << 1, 0);
16068 /*
16069 * Compact branches don't have a delay slot, so just let
16070 * the normal delay slot handling take us to the branch
16071 * target.
16072 */
16073 break;
16074 case LUI:
16075 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16076 gen_logic_imm(ctx, OPC_LUI, rs, 0, imm);
16077 break;
16078 case SYNCI:
16079 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16080 /*
16081 * Break the TB to be able to sync copied instructions
16082 * immediately.
16083 */
16084 ctx->base.is_jmp = DISAS_STOP;
16085 break;
16086 case BC2F:
16087 case BC2T:
16088 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16089 /* COP2: Not implemented. */
16090 generate_exception_err(ctx, EXCP_CpU, 2);
16091 break;
16092 case BC1F:
16093 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16094 mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 : OPC_BC1F;
16095 goto do_cp1branch;
16096 case BC1T:
16097 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16098 mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 : OPC_BC1T;
16099 goto do_cp1branch;
16100 case BC1ANY4F:
16101 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16102 mips32_op = OPC_BC1FANY4;
16103 goto do_cp1mips3d;
16104 case BC1ANY4T:
16105 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16106 mips32_op = OPC_BC1TANY4;
16107 do_cp1mips3d:
16108 check_cop1x(ctx);
16109 check_insn(ctx, ASE_MIPS3D);
16110 /* Fall through */
16111 do_cp1branch:
16112 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
16113 check_cp1_enabled(ctx);
16114 gen_compute_branch1(ctx, mips32_op,
16115 (ctx->opcode >> 18) & 0x7, imm << 1);
16116 } else {
16117 generate_exception_err(ctx, EXCP_CpU, 1);
16118 }
16119 break;
16120 case BPOSGE64:
16121 case BPOSGE32:
16122 /* MIPS DSP: not implemented */
16123 /* Fall through */
16124 default:
16125 MIPS_INVAL("pool32i");
16126 gen_reserved_instruction(ctx);
16127 break;
16128 }
16129 break;
16130 case POOL32C:
16131 minor = (ctx->opcode >> 12) & 0xf;
16132 offset = sextract32(ctx->opcode, 0,
16133 (ctx->insn_flags & ISA_MIPS_R6) ? 9 : 12);
16134 switch (minor) {
16135 case LWL:
16136 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16137 mips32_op = OPC_LWL;
16138 goto do_ld_lr;
16139 case SWL:
16140 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16141 mips32_op = OPC_SWL;
16142 goto do_st_lr;
16143 case LWR:
16144 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16145 mips32_op = OPC_LWR;
16146 goto do_ld_lr;
16147 case SWR:
16148 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16149 mips32_op = OPC_SWR;
16150 goto do_st_lr;
16151 #if defined(TARGET_MIPS64)
16152 case LDL:
16153 check_insn(ctx, ISA_MIPS3);
16154 check_mips_64(ctx);
16155 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16156 mips32_op = OPC_LDL;
16157 goto do_ld_lr;
16158 case SDL:
16159 check_insn(ctx, ISA_MIPS3);
16160 check_mips_64(ctx);
16161 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16162 mips32_op = OPC_SDL;
16163 goto do_st_lr;
16164 case LDR:
16165 check_insn(ctx, ISA_MIPS3);
16166 check_mips_64(ctx);
16167 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16168 mips32_op = OPC_LDR;
16169 goto do_ld_lr;
16170 case SDR:
16171 check_insn(ctx, ISA_MIPS3);
16172 check_mips_64(ctx);
16173 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16174 mips32_op = OPC_SDR;
16175 goto do_st_lr;
16176 case LWU:
16177 check_insn(ctx, ISA_MIPS3);
16178 check_mips_64(ctx);
16179 mips32_op = OPC_LWU;
16180 goto do_ld_lr;
16181 case LLD:
16182 check_insn(ctx, ISA_MIPS3);
16183 check_mips_64(ctx);
16184 mips32_op = OPC_LLD;
16185 goto do_ld_lr;
16186 #endif
16187 case LL:
16188 mips32_op = OPC_LL;
16189 goto do_ld_lr;
16190 do_ld_lr:
16191 gen_ld(ctx, mips32_op, rt, rs, offset);
16192 break;
16193 do_st_lr:
16194 gen_st(ctx, mips32_op, rt, rs, offset);
16195 break;
16196 case SC:
16197 gen_st_cond(ctx, rt, rs, offset, MO_TESL, false);
16198 break;
16199 #if defined(TARGET_MIPS64)
16200 case SCD:
16201 check_insn(ctx, ISA_MIPS3);
16202 check_mips_64(ctx);
16203 gen_st_cond(ctx, rt, rs, offset, MO_TEQ, false);
16204 break;
16205 #endif
16206 case LD_EVA:
16207 if (!ctx->eva) {
16208 MIPS_INVAL("pool32c ld-eva");
16209 gen_reserved_instruction(ctx);
16210 break;
16211 }
16212 check_cp0_enabled(ctx);
16213
16214 minor2 = (ctx->opcode >> 9) & 0x7;
16215 offset = sextract32(ctx->opcode, 0, 9);
16216 switch (minor2) {
16217 case LBUE:
16218 mips32_op = OPC_LBUE;
16219 goto do_ld_lr;
16220 case LHUE:
16221 mips32_op = OPC_LHUE;
16222 goto do_ld_lr;
16223 case LWLE:
16224 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16225 mips32_op = OPC_LWLE;
16226 goto do_ld_lr;
16227 case LWRE:
16228 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16229 mips32_op = OPC_LWRE;
16230 goto do_ld_lr;
16231 case LBE:
16232 mips32_op = OPC_LBE;
16233 goto do_ld_lr;
16234 case LHE:
16235 mips32_op = OPC_LHE;
16236 goto do_ld_lr;
16237 case LLE:
16238 mips32_op = OPC_LLE;
16239 goto do_ld_lr;
16240 case LWE:
16241 mips32_op = OPC_LWE;
16242 goto do_ld_lr;
16243 };
16244 break;
16245 case ST_EVA:
16246 if (!ctx->eva) {
16247 MIPS_INVAL("pool32c st-eva");
16248 gen_reserved_instruction(ctx);
16249 break;
16250 }
16251 check_cp0_enabled(ctx);
16252
16253 minor2 = (ctx->opcode >> 9) & 0x7;
16254 offset = sextract32(ctx->opcode, 0, 9);
16255 switch (minor2) {
16256 case SWLE:
16257 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16258 mips32_op = OPC_SWLE;
16259 goto do_st_lr;
16260 case SWRE:
16261 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16262 mips32_op = OPC_SWRE;
16263 goto do_st_lr;
16264 case PREFE:
16265 /* Treat as no-op */
16266 if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) {
16267 /* hint codes 24-31 are reserved and signal RI */
16268 generate_exception(ctx, EXCP_RI);
16269 }
16270 break;
16271 case CACHEE:
16272 /* Treat as no-op */
16273 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
16274 gen_cache_operation(ctx, rt, rs, offset);
16275 }
16276 break;
16277 case SBE:
16278 mips32_op = OPC_SBE;
16279 goto do_st_lr;
16280 case SHE:
16281 mips32_op = OPC_SHE;
16282 goto do_st_lr;
16283 case SCE:
16284 gen_st_cond(ctx, rt, rs, offset, MO_TESL, true);
16285 break;
16286 case SWE:
16287 mips32_op = OPC_SWE;
16288 goto do_st_lr;
16289 };
16290 break;
16291 case PREF:
16292 /* Treat as no-op */
16293 if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) {
16294 /* hint codes 24-31 are reserved and signal RI */
16295 generate_exception(ctx, EXCP_RI);
16296 }
16297 break;
16298 default:
16299 MIPS_INVAL("pool32c");
16300 gen_reserved_instruction(ctx);
16301 break;
16302 }
16303 break;
16304 case ADDI32: /* AUI, LUI */
16305 if (ctx->insn_flags & ISA_MIPS_R6) {
16306 /* AUI, LUI */
16307 gen_logic_imm(ctx, OPC_LUI, rt, rs, imm);
16308 } else {
16309 /* ADDI32 */
16310 mips32_op = OPC_ADDI;
16311 goto do_addi;
16312 }
16313 break;
16314 case ADDIU32:
16315 mips32_op = OPC_ADDIU;
16316 do_addi:
16317 gen_arith_imm(ctx, mips32_op, rt, rs, imm);
16318 break;
16319
16320 /* Logical operations */
16321 case ORI32:
16322 mips32_op = OPC_ORI;
16323 goto do_logici;
16324 case XORI32:
16325 mips32_op = OPC_XORI;
16326 goto do_logici;
16327 case ANDI32:
16328 mips32_op = OPC_ANDI;
16329 do_logici:
16330 gen_logic_imm(ctx, mips32_op, rt, rs, imm);
16331 break;
16332
16333 /* Set less than immediate */
16334 case SLTI32:
16335 mips32_op = OPC_SLTI;
16336 goto do_slti;
16337 case SLTIU32:
16338 mips32_op = OPC_SLTIU;
16339 do_slti:
16340 gen_slt_imm(ctx, mips32_op, rt, rs, imm);
16341 break;
16342 case JALX32:
16343 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16344 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
16345 gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset, 4);
16346 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
16347 break;
16348 case JALS32: /* BOVC, BEQC, BEQZALC */
16349 if (ctx->insn_flags & ISA_MIPS_R6) {
16350 if (rs >= rt) {
16351 /* BOVC */
16352 mips32_op = OPC_BOVC;
16353 } else if (rs < rt && rs == 0) {
16354 /* BEQZALC */
16355 mips32_op = OPC_BEQZALC;
16356 } else {
16357 /* BEQC */
16358 mips32_op = OPC_BEQC;
16359 }
16360 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
16361 } else {
16362 /* JALS32 */
16363 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 1;
16364 gen_compute_branch(ctx, OPC_JAL, 4, rt, rs, offset, 2);
16365 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
16366 }
16367 break;
16368 case BEQ32: /* BC */
16369 if (ctx->insn_flags & ISA_MIPS_R6) {
16370 /* BC */
16371 gen_compute_compact_branch(ctx, OPC_BC, 0, 0,
16372 sextract32(ctx->opcode << 1, 0, 27));
16373 } else {
16374 /* BEQ32 */
16375 gen_compute_branch(ctx, OPC_BEQ, 4, rt, rs, imm << 1, 4);
16376 }
16377 break;
16378 case BNE32: /* BALC */
16379 if (ctx->insn_flags & ISA_MIPS_R6) {
16380 /* BALC */
16381 gen_compute_compact_branch(ctx, OPC_BALC, 0, 0,
16382 sextract32(ctx->opcode << 1, 0, 27));
16383 } else {
16384 /* BNE32 */
16385 gen_compute_branch(ctx, OPC_BNE, 4, rt, rs, imm << 1, 4);
16386 }
16387 break;
16388 case J32: /* BGTZC, BLTZC, BLTC */
16389 if (ctx->insn_flags & ISA_MIPS_R6) {
16390 if (rs == 0 && rt != 0) {
16391 /* BGTZC */
16392 mips32_op = OPC_BGTZC;
16393 } else if (rs != 0 && rt != 0 && rs == rt) {
16394 /* BLTZC */
16395 mips32_op = OPC_BLTZC;
16396 } else {
16397 /* BLTC */
16398 mips32_op = OPC_BLTC;
16399 }
16400 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
16401 } else {
16402 /* J32 */
16403 gen_compute_branch(ctx, OPC_J, 4, rt, rs,
16404 (int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4);
16405 }
16406 break;
16407 case JAL32: /* BLEZC, BGEZC, BGEC */
16408 if (ctx->insn_flags & ISA_MIPS_R6) {
16409 if (rs == 0 && rt != 0) {
16410 /* BLEZC */
16411 mips32_op = OPC_BLEZC;
16412 } else if (rs != 0 && rt != 0 && rs == rt) {
16413 /* BGEZC */
16414 mips32_op = OPC_BGEZC;
16415 } else {
16416 /* BGEC */
16417 mips32_op = OPC_BGEC;
16418 }
16419 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
16420 } else {
16421 /* JAL32 */
16422 gen_compute_branch(ctx, OPC_JAL, 4, rt, rs,
16423 (int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4);
16424 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
16425 }
16426 break;
16427 /* Floating point (COP1) */
16428 case LWC132:
16429 mips32_op = OPC_LWC1;
16430 goto do_cop1;
16431 case LDC132:
16432 mips32_op = OPC_LDC1;
16433 goto do_cop1;
16434 case SWC132:
16435 mips32_op = OPC_SWC1;
16436 goto do_cop1;
16437 case SDC132:
16438 mips32_op = OPC_SDC1;
16439 do_cop1:
16440 gen_cop1_ldst(ctx, mips32_op, rt, rs, imm);
16441 break;
16442 case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
16443 if (ctx->insn_flags & ISA_MIPS_R6) {
16444 /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
16445 switch ((ctx->opcode >> 16) & 0x1f) {
16446 case ADDIUPC_00:
16447 case ADDIUPC_01:
16448 case ADDIUPC_02:
16449 case ADDIUPC_03:
16450 case ADDIUPC_04:
16451 case ADDIUPC_05:
16452 case ADDIUPC_06:
16453 case ADDIUPC_07:
16454 gen_pcrel(ctx, OPC_ADDIUPC, ctx->base.pc_next & ~0x3, rt);
16455 break;
16456 case AUIPC:
16457 gen_pcrel(ctx, OPC_AUIPC, ctx->base.pc_next, rt);
16458 break;
16459 case ALUIPC:
16460 gen_pcrel(ctx, OPC_ALUIPC, ctx->base.pc_next, rt);
16461 break;
16462 case LWPC_08:
16463 case LWPC_09:
16464 case LWPC_0A:
16465 case LWPC_0B:
16466 case LWPC_0C:
16467 case LWPC_0D:
16468 case LWPC_0E:
16469 case LWPC_0F:
16470 gen_pcrel(ctx, R6_OPC_LWPC, ctx->base.pc_next & ~0x3, rt);
16471 break;
16472 default:
16473 generate_exception(ctx, EXCP_RI);
16474 break;
16475 }
16476 } else {
16477 /* ADDIUPC */
16478 int reg = mmreg(ZIMM(ctx->opcode, 23, 3));
16479 offset = SIMM(ctx->opcode, 0, 23) << 2;
16480
16481 gen_addiupc(ctx, reg, offset, 0, 0);
16482 }
16483 break;
16484 case BNVC: /* BNEC, BNEZALC */
16485 check_insn(ctx, ISA_MIPS_R6);
16486 if (rs >= rt) {
16487 /* BNVC */
16488 mips32_op = OPC_BNVC;
16489 } else if (rs < rt && rs == 0) {
16490 /* BNEZALC */
16491 mips32_op = OPC_BNEZALC;
16492 } else {
16493 /* BNEC */
16494 mips32_op = OPC_BNEC;
16495 }
16496 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
16497 break;
16498 case R6_BNEZC: /* JIALC */
16499 check_insn(ctx, ISA_MIPS_R6);
16500 if (rt != 0) {
16501 /* BNEZC */
16502 gen_compute_compact_branch(ctx, OPC_BNEZC, rt, 0,
16503 sextract32(ctx->opcode << 1, 0, 22));
16504 } else {
16505 /* JIALC */
16506 gen_compute_compact_branch(ctx, OPC_JIALC, 0, rs, imm);
16507 }
16508 break;
16509 case R6_BEQZC: /* JIC */
16510 check_insn(ctx, ISA_MIPS_R6);
16511 if (rt != 0) {
16512 /* BEQZC */
16513 gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0,
16514 sextract32(ctx->opcode << 1, 0, 22));
16515 } else {
16516 /* JIC */
16517 gen_compute_compact_branch(ctx, OPC_JIC, 0, rs, imm);
16518 }
16519 break;
16520 case BLEZALC: /* BGEZALC, BGEUC */
16521 check_insn(ctx, ISA_MIPS_R6);
16522 if (rs == 0 && rt != 0) {
16523 /* BLEZALC */
16524 mips32_op = OPC_BLEZALC;
16525 } else if (rs != 0 && rt != 0 && rs == rt) {
16526 /* BGEZALC */
16527 mips32_op = OPC_BGEZALC;
16528 } else {
16529 /* BGEUC */
16530 mips32_op = OPC_BGEUC;
16531 }
16532 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
16533 break;
16534 case BGTZALC: /* BLTZALC, BLTUC */
16535 check_insn(ctx, ISA_MIPS_R6);
16536 if (rs == 0 && rt != 0) {
16537 /* BGTZALC */
16538 mips32_op = OPC_BGTZALC;
16539 } else if (rs != 0 && rt != 0 && rs == rt) {
16540 /* BLTZALC */
16541 mips32_op = OPC_BLTZALC;
16542 } else {
16543 /* BLTUC */
16544 mips32_op = OPC_BLTUC;
16545 }
16546 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
16547 break;
16548 /* Loads and stores */
16549 case LB32:
16550 mips32_op = OPC_LB;
16551 goto do_ld;
16552 case LBU32:
16553 mips32_op = OPC_LBU;
16554 goto do_ld;
16555 case LH32:
16556 mips32_op = OPC_LH;
16557 goto do_ld;
16558 case LHU32:
16559 mips32_op = OPC_LHU;
16560 goto do_ld;
16561 case LW32:
16562 mips32_op = OPC_LW;
16563 goto do_ld;
16564 #ifdef TARGET_MIPS64
16565 case LD32:
16566 check_insn(ctx, ISA_MIPS3);
16567 check_mips_64(ctx);
16568 mips32_op = OPC_LD;
16569 goto do_ld;
16570 case SD32:
16571 check_insn(ctx, ISA_MIPS3);
16572 check_mips_64(ctx);
16573 mips32_op = OPC_SD;
16574 goto do_st;
16575 #endif
16576 case SB32:
16577 mips32_op = OPC_SB;
16578 goto do_st;
16579 case SH32:
16580 mips32_op = OPC_SH;
16581 goto do_st;
16582 case SW32:
16583 mips32_op = OPC_SW;
16584 goto do_st;
16585 do_ld:
16586 gen_ld(ctx, mips32_op, rt, rs, imm);
16587 break;
16588 do_st:
16589 gen_st(ctx, mips32_op, rt, rs, imm);
16590 break;
16591 default:
16592 gen_reserved_instruction(ctx);
16593 break;
16594 }
16595 }
16596
16597 static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx)
16598 {
16599 uint32_t op;
16600
16601 /* make sure instructions are on a halfword boundary */
16602 if (ctx->base.pc_next & 0x1) {
16603 env->CP0_BadVAddr = ctx->base.pc_next;
16604 generate_exception_end(ctx, EXCP_AdEL);
16605 return 2;
16606 }
16607
16608 op = (ctx->opcode >> 10) & 0x3f;
16609 /* Enforce properly-sized instructions in a delay slot */
16610 if (ctx->hflags & MIPS_HFLAG_BDS_STRICT) {
16611 switch (op & 0x7) { /* MSB-3..MSB-5 */
16612 case 0:
16613 /* POOL32A, POOL32B, POOL32I, POOL32C */
16614 case 4:
16615 /* ADDI32, ADDIU32, ORI32, XORI32, SLTI32, SLTIU32, ANDI32, JALX32 */
16616 case 5:
16617 /* LBU32, LHU32, POOL32F, JALS32, BEQ32, BNE32, J32, JAL32 */
16618 case 6:
16619 /* SB32, SH32, ADDIUPC, SWC132, SDC132, SW32 */
16620 case 7:
16621 /* LB32, LH32, LWC132, LDC132, LW32 */
16622 if (ctx->hflags & MIPS_HFLAG_BDS16) {
16623 gen_reserved_instruction(ctx);
16624 return 2;
16625 }
16626 break;
16627 case 1:
16628 /* POOL16A, POOL16B, POOL16C, LWGP16, POOL16F */
16629 case 2:
16630 /* LBU16, LHU16, LWSP16, LW16, SB16, SH16, SWSP16, SW16 */
16631 case 3:
16632 /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */
16633 if (ctx->hflags & MIPS_HFLAG_BDS32) {
16634 gen_reserved_instruction(ctx);
16635 return 2;
16636 }
16637 break;
16638 }
16639 }
16640
16641 switch (op) {
16642 case POOL16A:
16643 {
16644 int rd = mmreg(uMIPS_RD(ctx->opcode));
16645 int rs1 = mmreg(uMIPS_RS1(ctx->opcode));
16646 int rs2 = mmreg(uMIPS_RS2(ctx->opcode));
16647 uint32_t opc = 0;
16648
16649 switch (ctx->opcode & 0x1) {
16650 case ADDU16:
16651 opc = OPC_ADDU;
16652 break;
16653 case SUBU16:
16654 opc = OPC_SUBU;
16655 break;
16656 }
16657 if (ctx->insn_flags & ISA_MIPS_R6) {
16658 /*
16659 * In the Release 6, the register number location in
16660 * the instruction encoding has changed.
16661 */
16662 gen_arith(ctx, opc, rs1, rd, rs2);
16663 } else {
16664 gen_arith(ctx, opc, rd, rs1, rs2);
16665 }
16666 }
16667 break;
16668 case POOL16B:
16669 {
16670 int rd = mmreg(uMIPS_RD(ctx->opcode));
16671 int rs = mmreg(uMIPS_RS(ctx->opcode));
16672 int amount = (ctx->opcode >> 1) & 0x7;
16673 uint32_t opc = 0;
16674 amount = amount == 0 ? 8 : amount;
16675
16676 switch (ctx->opcode & 0x1) {
16677 case SLL16:
16678 opc = OPC_SLL;
16679 break;
16680 case SRL16:
16681 opc = OPC_SRL;
16682 break;
16683 }
16684
16685 gen_shift_imm(ctx, opc, rd, rs, amount);
16686 }
16687 break;
16688 case POOL16C:
16689 if (ctx->insn_flags & ISA_MIPS_R6) {
16690 gen_pool16c_r6_insn(ctx);
16691 } else {
16692 gen_pool16c_insn(ctx);
16693 }
16694 break;
16695 case LWGP16:
16696 {
16697 int rd = mmreg(uMIPS_RD(ctx->opcode));
16698 int rb = 28; /* GP */
16699 int16_t offset = SIMM(ctx->opcode, 0, 7) << 2;
16700
16701 gen_ld(ctx, OPC_LW, rd, rb, offset);
16702 }
16703 break;
16704 case POOL16F:
16705 check_insn_opc_removed(ctx, ISA_MIPS_R6);
16706 if (ctx->opcode & 1) {
16707 gen_reserved_instruction(ctx);
16708 } else {
16709 /* MOVEP */
16710 int enc_dest = uMIPS_RD(ctx->opcode);
16711 int enc_rt = uMIPS_RS2(ctx->opcode);
16712 int enc_rs = uMIPS_RS1(ctx->opcode);
16713 gen_movep(ctx, enc_dest, enc_rt, enc_rs);
16714 }
16715 break;
16716 case LBU16:
16717 {
16718 int rd = mmreg(uMIPS_RD(ctx->opcode));
16719 int rb = mmreg(uMIPS_RS(ctx->opcode));
16720 int16_t offset = ZIMM(ctx->opcode, 0, 4);
16721 offset = (offset == 0xf ? -1 : offset);
16722
16723 gen_ld(ctx, OPC_LBU, rd, rb, offset);
16724 }
16725 break;
16726 case LHU16:
16727 {
16728 int rd = mmreg(uMIPS_RD(ctx->opcode));
16729 int rb = mmreg(uMIPS_RS(ctx->opcode));
16730 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1;
16731
16732 gen_ld(ctx, OPC_LHU, rd, rb, offset);
16733 }
16734 break;
16735 case LWSP16:
16736 {
16737 int rd = (ctx->opcode >> 5) & 0x1f;
16738 int rb = 29; /* SP */
16739 int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2;
16740
16741 gen_ld(ctx, OPC_LW, rd, rb, offset);
16742 }
16743 break;
16744 case LW16:
16745 {
16746 int rd = mmreg(uMIPS_RD(ctx->opcode));
16747 int rb = mmreg(uMIPS_RS(ctx->opcode));
16748 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2;
16749
16750 gen_ld(ctx, OPC_LW, rd, rb, offset);
16751 }
16752 break;
16753 case SB16:
16754 {
16755 int rd = mmreg2(uMIPS_RD(ctx->opcode));
16756 int rb = mmreg(uMIPS_RS(ctx->opcode));
16757 int16_t offset = ZIMM(ctx->opcode, 0, 4);
16758
16759 gen_st(ctx, OPC_SB, rd, rb, offset);
16760 }
16761 break;
16762 case SH16:
16763 {
16764 int rd = mmreg2(uMIPS_RD(ctx->opcode));
16765 int rb = mmreg(uMIPS_RS(ctx->opcode));
16766 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1;
16767
16768 gen_st(ctx, OPC_SH, rd, rb, offset);
16769 }
16770 break;
16771 case SWSP16:
16772 {
16773 int rd = (ctx->opcode >> 5) & 0x1f;
16774 int rb = 29; /* SP */
16775 int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2;
16776
16777 gen_st(ctx, OPC_SW, rd, rb, offset);
16778 }
16779 break;
16780 case SW16:
16781 {
16782 int rd = mmreg2(uMIPS_RD(ctx->opcode));
16783 int rb = mmreg(uMIPS_RS(ctx->opcode));
16784 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2;
16785
16786 gen_st(ctx, OPC_SW, rd, rb, offset);
16787 }
16788 break;
16789 case MOVE16:
16790 {
16791 int rd = uMIPS_RD5(ctx->opcode);
16792 int rs = uMIPS_RS5(ctx->opcode);
16793
16794 gen_arith(ctx, OPC_ADDU, rd, rs, 0);
16795 }
16796 break;
16797 case ANDI16:
16798 gen_andi16(ctx);
16799 break;
16800 case POOL16D:
16801 switch (ctx->opcode & 0x1) {
16802 case ADDIUS5:
16803 gen_addius5(ctx);
16804 break;
16805 case ADDIUSP:
16806 gen_addiusp(ctx);
16807 break;
16808 }
16809 break;
16810 case POOL16E:
16811 switch (ctx->opcode & 0x1) {
16812 case ADDIUR2:
16813 gen_addiur2(ctx);
16814 break;
16815 case ADDIUR1SP:
16816 gen_addiur1sp(ctx);
16817 break;
16818 }
16819 break;
16820 case B16: /* BC16 */
16821 gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0,
16822 sextract32(ctx->opcode, 0, 10) << 1,
16823 (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4);
16824 break;
16825 case BNEZ16: /* BNEZC16 */
16826 case BEQZ16: /* BEQZC16 */
16827 gen_compute_branch(ctx, op == BNEZ16 ? OPC_BNE : OPC_BEQ, 2,
16828 mmreg(uMIPS_RD(ctx->opcode)),
16829 0, sextract32(ctx->opcode, 0, 7) << 1,
16830 (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4);
16831
16832 break;
16833 case LI16:
16834 {
16835 int reg = mmreg(uMIPS_RD(ctx->opcode));
16836 int imm = ZIMM(ctx->opcode, 0, 7);
16837
16838 imm = (imm == 0x7f ? -1 : imm);
16839 tcg_gen_movi_tl(cpu_gpr[reg], imm);
16840 }
16841 break;
16842 case RES_29:
16843 case RES_31:
16844 case RES_39:
16845 gen_reserved_instruction(ctx);
16846 break;
16847 default:
16848 decode_micromips32_opc(env, ctx);
16849 return 4;
16850 }
16851
16852 return 2;
16853 }
16854
16855 /*
16856 *
16857 * nanoMIPS opcodes
16858 *
16859 */
16860
16861 /* MAJOR, P16, and P32 pools opcodes */
16862 enum {
16863 NM_P_ADDIU = 0x00,
16864 NM_ADDIUPC = 0x01,
16865 NM_MOVE_BALC = 0x02,
16866 NM_P16_MV = 0x04,
16867 NM_LW16 = 0x05,
16868 NM_BC16 = 0x06,
16869 NM_P16_SR = 0x07,
16870
16871 NM_POOL32A = 0x08,
16872 NM_P_BAL = 0x0a,
16873 NM_P16_SHIFT = 0x0c,
16874 NM_LWSP16 = 0x0d,
16875 NM_BALC16 = 0x0e,
16876 NM_P16_4X4 = 0x0f,
16877
16878 NM_P_GP_W = 0x10,
16879 NM_P_GP_BH = 0x11,
16880 NM_P_J = 0x12,
16881 NM_P16C = 0x14,
16882 NM_LWGP16 = 0x15,
16883 NM_P16_LB = 0x17,
16884
16885 NM_P48I = 0x18,
16886 NM_P16_A1 = 0x1c,
16887 NM_LW4X4 = 0x1d,
16888 NM_P16_LH = 0x1f,
16889
16890 NM_P_U12 = 0x20,
16891 NM_P_LS_U12 = 0x21,
16892 NM_P_BR1 = 0x22,
16893 NM_P16_A2 = 0x24,
16894 NM_SW16 = 0x25,
16895 NM_BEQZC16 = 0x26,
16896
16897 NM_POOL32F = 0x28,
16898 NM_P_LS_S9 = 0x29,
16899 NM_P_BR2 = 0x2a,
16900
16901 NM_P16_ADDU = 0x2c,
16902 NM_SWSP16 = 0x2d,
16903 NM_BNEZC16 = 0x2e,
16904 NM_MOVEP = 0x2f,
16905
16906 NM_POOL32S = 0x30,
16907 NM_P_BRI = 0x32,
16908 NM_LI16 = 0x34,
16909 NM_SWGP16 = 0x35,
16910 NM_P16_BR = 0x36,
16911
16912 NM_P_LUI = 0x38,
16913 NM_ANDI16 = 0x3c,
16914 NM_SW4X4 = 0x3d,
16915 NM_MOVEPREV = 0x3f,
16916 };
16917
16918 /* POOL32A instruction pool */
16919 enum {
16920 NM_POOL32A0 = 0x00,
16921 NM_SPECIAL2 = 0x01,
16922 NM_COP2_1 = 0x02,
16923 NM_UDI = 0x03,
16924 NM_POOL32A5 = 0x05,
16925 NM_POOL32A7 = 0x07,
16926 };
16927
16928 /* P.GP.W instruction pool */
16929 enum {
16930 NM_ADDIUGP_W = 0x00,
16931 NM_LWGP = 0x02,
16932 NM_SWGP = 0x03,
16933 };
16934
16935 /* P48I instruction pool */
16936 enum {
16937 NM_LI48 = 0x00,
16938 NM_ADDIU48 = 0x01,
16939 NM_ADDIUGP48 = 0x02,
16940 NM_ADDIUPC48 = 0x03,
16941 NM_LWPC48 = 0x0b,
16942 NM_SWPC48 = 0x0f,
16943 };
16944
16945 /* P.U12 instruction pool */
16946 enum {
16947 NM_ORI = 0x00,
16948 NM_XORI = 0x01,
16949 NM_ANDI = 0x02,
16950 NM_P_SR = 0x03,
16951 NM_SLTI = 0x04,
16952 NM_SLTIU = 0x05,
16953 NM_SEQI = 0x06,
16954 NM_ADDIUNEG = 0x08,
16955 NM_P_SHIFT = 0x0c,
16956 NM_P_ROTX = 0x0d,
16957 NM_P_INS = 0x0e,
16958 NM_P_EXT = 0x0f,
16959 };
16960
16961 /* POOL32F instruction pool */
16962 enum {
16963 NM_POOL32F_0 = 0x00,
16964 NM_POOL32F_3 = 0x03,
16965 NM_POOL32F_5 = 0x05,
16966 };
16967
16968 /* POOL32S instruction pool */
16969 enum {
16970 NM_POOL32S_0 = 0x00,
16971 NM_POOL32S_4 = 0x04,
16972 };
16973
16974 /* P.LUI instruction pool */
16975 enum {
16976 NM_LUI = 0x00,
16977 NM_ALUIPC = 0x01,
16978 };
16979
16980 /* P.GP.BH instruction pool */
16981 enum {
16982 NM_LBGP = 0x00,
16983 NM_SBGP = 0x01,
16984 NM_LBUGP = 0x02,
16985 NM_ADDIUGP_B = 0x03,
16986 NM_P_GP_LH = 0x04,
16987 NM_P_GP_SH = 0x05,
16988 NM_P_GP_CP1 = 0x06,
16989 };
16990
16991 /* P.LS.U12 instruction pool */
16992 enum {
16993 NM_LB = 0x00,
16994 NM_SB = 0x01,
16995 NM_LBU = 0x02,
16996 NM_P_PREFU12 = 0x03,
16997 NM_LH = 0x04,
16998 NM_SH = 0x05,
16999 NM_LHU = 0x06,
17000 NM_LWU = 0x07,
17001 NM_LW = 0x08,
17002 NM_SW = 0x09,
17003 NM_LWC1 = 0x0a,
17004 NM_SWC1 = 0x0b,
17005 NM_LDC1 = 0x0e,
17006 NM_SDC1 = 0x0f,
17007 };
17008
17009 /* P.LS.S9 instruction pool */
17010 enum {
17011 NM_P_LS_S0 = 0x00,
17012 NM_P_LS_S1 = 0x01,
17013 NM_P_LS_E0 = 0x02,
17014 NM_P_LS_WM = 0x04,
17015 NM_P_LS_UAWM = 0x05,
17016 };
17017
17018 /* P.BAL instruction pool */
17019 enum {
17020 NM_BC = 0x00,
17021 NM_BALC = 0x01,
17022 };
17023
17024 /* P.J instruction pool */
17025 enum {
17026 NM_JALRC = 0x00,
17027 NM_JALRC_HB = 0x01,
17028 NM_P_BALRSC = 0x08,
17029 };
17030
17031 /* P.BR1 instruction pool */
17032 enum {
17033 NM_BEQC = 0x00,
17034 NM_P_BR3A = 0x01,
17035 NM_BGEC = 0x02,
17036 NM_BGEUC = 0x03,
17037 };
17038
17039 /* P.BR2 instruction pool */
17040 enum {
17041 NM_BNEC = 0x00,
17042 NM_BLTC = 0x02,
17043 NM_BLTUC = 0x03,
17044 };
17045
17046 /* P.BRI instruction pool */
17047 enum {
17048 NM_BEQIC = 0x00,
17049 NM_BBEQZC = 0x01,
17050 NM_BGEIC = 0x02,
17051 NM_BGEIUC = 0x03,
17052 NM_BNEIC = 0x04,
17053 NM_BBNEZC = 0x05,
17054 NM_BLTIC = 0x06,
17055 NM_BLTIUC = 0x07,
17056 };
17057
17058 /* P16.SHIFT instruction pool */
17059 enum {
17060 NM_SLL16 = 0x00,
17061 NM_SRL16 = 0x01,
17062 };
17063
17064 /* POOL16C instruction pool */
17065 enum {
17066 NM_POOL16C_0 = 0x00,
17067 NM_LWXS16 = 0x01,
17068 };
17069
17070 /* P16.A1 instruction pool */
17071 enum {
17072 NM_ADDIUR1SP = 0x01,
17073 };
17074
17075 /* P16.A2 instruction pool */
17076 enum {
17077 NM_ADDIUR2 = 0x00,
17078 NM_P_ADDIURS5 = 0x01,
17079 };
17080
17081 /* P16.ADDU instruction pool */
17082 enum {
17083 NM_ADDU16 = 0x00,
17084 NM_SUBU16 = 0x01,
17085 };
17086
17087 /* P16.SR instruction pool */
17088 enum {
17089 NM_SAVE16 = 0x00,
17090 NM_RESTORE_JRC16 = 0x01,
17091 };
17092
17093 /* P16.4X4 instruction pool */
17094 enum {
17095 NM_ADDU4X4 = 0x00,
17096 NM_MUL4X4 = 0x01,
17097 };
17098
17099 /* P16.LB instruction pool */
17100 enum {
17101 NM_LB16 = 0x00,
17102 NM_SB16 = 0x01,
17103 NM_LBU16 = 0x02,
17104 };
17105
17106 /* P16.LH instruction pool */
17107 enum {
17108 NM_LH16 = 0x00,
17109 NM_SH16 = 0x01,
17110 NM_LHU16 = 0x02,
17111 };
17112
17113 /* P.RI instruction pool */
17114 enum {
17115 NM_SIGRIE = 0x00,
17116 NM_P_SYSCALL = 0x01,
17117 NM_BREAK = 0x02,
17118 NM_SDBBP = 0x03,
17119 };
17120
17121 /* POOL32A0 instruction pool */
17122 enum {
17123 NM_P_TRAP = 0x00,
17124 NM_SEB = 0x01,
17125 NM_SLLV = 0x02,
17126 NM_MUL = 0x03,
17127 NM_MFC0 = 0x06,
17128 NM_MFHC0 = 0x07,
17129 NM_SEH = 0x09,
17130 NM_SRLV = 0x0a,
17131 NM_MUH = 0x0b,
17132 NM_MTC0 = 0x0e,
17133 NM_MTHC0 = 0x0f,
17134 NM_SRAV = 0x12,
17135 NM_MULU = 0x13,
17136 NM_ROTRV = 0x1a,
17137 NM_MUHU = 0x1b,
17138 NM_ADD = 0x22,
17139 NM_DIV = 0x23,
17140 NM_ADDU = 0x2a,
17141 NM_MOD = 0x2b,
17142 NM_SUB = 0x32,
17143 NM_DIVU = 0x33,
17144 NM_RDHWR = 0x38,
17145 NM_SUBU = 0x3a,
17146 NM_MODU = 0x3b,
17147 NM_P_CMOVE = 0x42,
17148 NM_FORK = 0x45,
17149 NM_MFTR = 0x46,
17150 NM_MFHTR = 0x47,
17151 NM_AND = 0x4a,
17152 NM_YIELD = 0x4d,
17153 NM_MTTR = 0x4e,
17154 NM_MTHTR = 0x4f,
17155 NM_OR = 0x52,
17156 NM_D_E_MT_VPE = 0x56,
17157 NM_NOR = 0x5a,
17158 NM_XOR = 0x62,
17159 NM_SLT = 0x6a,
17160 NM_P_SLTU = 0x72,
17161 NM_SOV = 0x7a,
17162 };
17163
17164 /* CRC32 instruction pool */
17165 enum {
17166 NM_CRC32B = 0x00,
17167 NM_CRC32H = 0x01,
17168 NM_CRC32W = 0x02,
17169 NM_CRC32CB = 0x04,
17170 NM_CRC32CH = 0x05,
17171 NM_CRC32CW = 0x06,
17172 };
17173
17174 /* POOL32A5 instruction pool */
17175 enum {
17176 NM_CMP_EQ_PH = 0x00,
17177 NM_CMP_LT_PH = 0x08,
17178 NM_CMP_LE_PH = 0x10,
17179 NM_CMPGU_EQ_QB = 0x18,
17180 NM_CMPGU_LT_QB = 0x20,
17181 NM_CMPGU_LE_QB = 0x28,
17182 NM_CMPGDU_EQ_QB = 0x30,
17183 NM_CMPGDU_LT_QB = 0x38,
17184 NM_CMPGDU_LE_QB = 0x40,
17185 NM_CMPU_EQ_QB = 0x48,
17186 NM_CMPU_LT_QB = 0x50,
17187 NM_CMPU_LE_QB = 0x58,
17188 NM_ADDQ_S_W = 0x60,
17189 NM_SUBQ_S_W = 0x68,
17190 NM_ADDSC = 0x70,
17191 NM_ADDWC = 0x78,
17192
17193 NM_ADDQ_S_PH = 0x01,
17194 NM_ADDQH_R_PH = 0x09,
17195 NM_ADDQH_R_W = 0x11,
17196 NM_ADDU_S_QB = 0x19,
17197 NM_ADDU_S_PH = 0x21,
17198 NM_ADDUH_R_QB = 0x29,
17199 NM_SHRAV_R_PH = 0x31,
17200 NM_SHRAV_R_QB = 0x39,
17201 NM_SUBQ_S_PH = 0x41,
17202 NM_SUBQH_R_PH = 0x49,
17203 NM_SUBQH_R_W = 0x51,
17204 NM_SUBU_S_QB = 0x59,
17205 NM_SUBU_S_PH = 0x61,
17206 NM_SUBUH_R_QB = 0x69,
17207 NM_SHLLV_S_PH = 0x71,
17208 NM_PRECR_SRA_R_PH_W = 0x79,
17209
17210 NM_MULEU_S_PH_QBL = 0x12,
17211 NM_MULEU_S_PH_QBR = 0x1a,
17212 NM_MULQ_RS_PH = 0x22,
17213 NM_MULQ_S_PH = 0x2a,
17214 NM_MULQ_RS_W = 0x32,
17215 NM_MULQ_S_W = 0x3a,
17216 NM_APPEND = 0x42,
17217 NM_MODSUB = 0x52,
17218 NM_SHRAV_R_W = 0x5a,
17219 NM_SHRLV_PH = 0x62,
17220 NM_SHRLV_QB = 0x6a,
17221 NM_SHLLV_QB = 0x72,
17222 NM_SHLLV_S_W = 0x7a,
17223
17224 NM_SHILO = 0x03,
17225
17226 NM_MULEQ_S_W_PHL = 0x04,
17227 NM_MULEQ_S_W_PHR = 0x0c,
17228
17229 NM_MUL_S_PH = 0x05,
17230 NM_PRECR_QB_PH = 0x0d,
17231 NM_PRECRQ_QB_PH = 0x15,
17232 NM_PRECRQ_PH_W = 0x1d,
17233 NM_PRECRQ_RS_PH_W = 0x25,
17234 NM_PRECRQU_S_QB_PH = 0x2d,
17235 NM_PACKRL_PH = 0x35,
17236 NM_PICK_QB = 0x3d,
17237 NM_PICK_PH = 0x45,
17238
17239 NM_SHRA_R_W = 0x5e,
17240 NM_SHRA_R_PH = 0x66,
17241 NM_SHLL_S_PH = 0x76,
17242 NM_SHLL_S_W = 0x7e,
17243
17244 NM_REPL_PH = 0x07
17245 };
17246
17247 /* POOL32A7 instruction pool */
17248 enum {
17249 NM_P_LSX = 0x00,
17250 NM_LSA = 0x01,
17251 NM_EXTW = 0x03,
17252 NM_POOL32AXF = 0x07,
17253 };
17254
17255 /* P.SR instruction pool */
17256 enum {
17257 NM_PP_SR = 0x00,
17258 NM_P_SR_F = 0x01,
17259 };
17260
17261 /* P.SHIFT instruction pool */
17262 enum {
17263 NM_P_SLL = 0x00,
17264 NM_SRL = 0x02,
17265 NM_SRA = 0x04,
17266 NM_ROTR = 0x06,
17267 };
17268
17269 /* P.ROTX instruction pool */
17270 enum {
17271 NM_ROTX = 0x00,
17272 };
17273
17274 /* P.INS instruction pool */
17275 enum {
17276 NM_INS = 0x00,
17277 };
17278
17279 /* P.EXT instruction pool */
17280 enum {
17281 NM_EXT = 0x00,
17282 };
17283
17284 /* POOL32F_0 (fmt) instruction pool */
17285 enum {
17286 NM_RINT_S = 0x04,
17287 NM_RINT_D = 0x44,
17288 NM_ADD_S = 0x06,
17289 NM_SELEQZ_S = 0x07,
17290 NM_SELEQZ_D = 0x47,
17291 NM_CLASS_S = 0x0c,
17292 NM_CLASS_D = 0x4c,
17293 NM_SUB_S = 0x0e,
17294 NM_SELNEZ_S = 0x0f,
17295 NM_SELNEZ_D = 0x4f,
17296 NM_MUL_S = 0x16,
17297 NM_SEL_S = 0x17,
17298 NM_SEL_D = 0x57,
17299 NM_DIV_S = 0x1e,
17300 NM_ADD_D = 0x26,
17301 NM_SUB_D = 0x2e,
17302 NM_MUL_D = 0x36,
17303 NM_MADDF_S = 0x37,
17304 NM_MADDF_D = 0x77,
17305 NM_DIV_D = 0x3e,
17306 NM_MSUBF_S = 0x3f,
17307 NM_MSUBF_D = 0x7f,
17308 };
17309
17310 /* POOL32F_3 instruction pool */
17311 enum {
17312 NM_MIN_FMT = 0x00,
17313 NM_MAX_FMT = 0x01,
17314 NM_MINA_FMT = 0x04,
17315 NM_MAXA_FMT = 0x05,
17316 NM_POOL32FXF = 0x07,
17317 };
17318
17319 /* POOL32F_5 instruction pool */
17320 enum {
17321 NM_CMP_CONDN_S = 0x00,
17322 NM_CMP_CONDN_D = 0x02,
17323 };
17324
17325 /* P.GP.LH instruction pool */
17326 enum {
17327 NM_LHGP = 0x00,
17328 NM_LHUGP = 0x01,
17329 };
17330
17331 /* P.GP.SH instruction pool */
17332 enum {
17333 NM_SHGP = 0x00,
17334 };
17335
17336 /* P.GP.CP1 instruction pool */
17337 enum {
17338 NM_LWC1GP = 0x00,
17339 NM_SWC1GP = 0x01,
17340 NM_LDC1GP = 0x02,
17341 NM_SDC1GP = 0x03,
17342 };
17343
17344 /* P.LS.S0 instruction pool */
17345 enum {
17346 NM_LBS9 = 0x00,
17347 NM_LHS9 = 0x04,
17348 NM_LWS9 = 0x08,
17349 NM_LDS9 = 0x0c,
17350
17351 NM_SBS9 = 0x01,
17352 NM_SHS9 = 0x05,
17353 NM_SWS9 = 0x09,
17354 NM_SDS9 = 0x0d,
17355
17356 NM_LBUS9 = 0x02,
17357 NM_LHUS9 = 0x06,
17358 NM_LWC1S9 = 0x0a,
17359 NM_LDC1S9 = 0x0e,
17360
17361 NM_P_PREFS9 = 0x03,
17362 NM_LWUS9 = 0x07,
17363 NM_SWC1S9 = 0x0b,
17364 NM_SDC1S9 = 0x0f,
17365 };
17366
17367 /* P.LS.S1 instruction pool */
17368 enum {
17369 NM_ASET_ACLR = 0x02,
17370 NM_UALH = 0x04,
17371 NM_UASH = 0x05,
17372 NM_CACHE = 0x07,
17373 NM_P_LL = 0x0a,
17374 NM_P_SC = 0x0b,
17375 };
17376
17377 /* P.LS.E0 instruction pool */
17378 enum {
17379 NM_LBE = 0x00,
17380 NM_SBE = 0x01,
17381 NM_LBUE = 0x02,
17382 NM_P_PREFE = 0x03,
17383 NM_LHE = 0x04,
17384 NM_SHE = 0x05,
17385 NM_LHUE = 0x06,
17386 NM_CACHEE = 0x07,
17387 NM_LWE = 0x08,
17388 NM_SWE = 0x09,
17389 NM_P_LLE = 0x0a,
17390 NM_P_SCE = 0x0b,
17391 };
17392
17393 /* P.PREFE instruction pool */
17394 enum {
17395 NM_SYNCIE = 0x00,
17396 NM_PREFE = 0x01,
17397 };
17398
17399 /* P.LLE instruction pool */
17400 enum {
17401 NM_LLE = 0x00,
17402 NM_LLWPE = 0x01,
17403 };
17404
17405 /* P.SCE instruction pool */
17406 enum {
17407 NM_SCE = 0x00,
17408 NM_SCWPE = 0x01,
17409 };
17410
17411 /* P.LS.WM instruction pool */
17412 enum {
17413 NM_LWM = 0x00,
17414 NM_SWM = 0x01,
17415 };
17416
17417 /* P.LS.UAWM instruction pool */
17418 enum {
17419 NM_UALWM = 0x00,
17420 NM_UASWM = 0x01,
17421 };
17422
17423 /* P.BR3A instruction pool */
17424 enum {
17425 NM_BC1EQZC = 0x00,
17426 NM_BC1NEZC = 0x01,
17427 NM_BC2EQZC = 0x02,
17428 NM_BC2NEZC = 0x03,
17429 NM_BPOSGE32C = 0x04,
17430 };
17431
17432 /* P16.RI instruction pool */
17433 enum {
17434 NM_P16_SYSCALL = 0x01,
17435 NM_BREAK16 = 0x02,
17436 NM_SDBBP16 = 0x03,
17437 };
17438
17439 /* POOL16C_0 instruction pool */
17440 enum {
17441 NM_POOL16C_00 = 0x00,
17442 };
17443
17444 /* P16.JRC instruction pool */
17445 enum {
17446 NM_JRC = 0x00,
17447 NM_JALRC16 = 0x01,
17448 };
17449
17450 /* P.SYSCALL instruction pool */
17451 enum {
17452 NM_SYSCALL = 0x00,
17453 NM_HYPCALL = 0x01,
17454 };
17455
17456 /* P.TRAP instruction pool */
17457 enum {
17458 NM_TEQ = 0x00,
17459 NM_TNE = 0x01,
17460 };
17461
17462 /* P.CMOVE instruction pool */
17463 enum {
17464 NM_MOVZ = 0x00,
17465 NM_MOVN = 0x01,
17466 };
17467
17468 /* POOL32Axf instruction pool */
17469 enum {
17470 NM_POOL32AXF_1 = 0x01,
17471 NM_POOL32AXF_2 = 0x02,
17472 NM_POOL32AXF_4 = 0x04,
17473 NM_POOL32AXF_5 = 0x05,
17474 NM_POOL32AXF_7 = 0x07,
17475 };
17476
17477 /* POOL32Axf_1 instruction pool */
17478 enum {
17479 NM_POOL32AXF_1_0 = 0x00,
17480 NM_POOL32AXF_1_1 = 0x01,
17481 NM_POOL32AXF_1_3 = 0x03,
17482 NM_POOL32AXF_1_4 = 0x04,
17483 NM_POOL32AXF_1_5 = 0x05,
17484 NM_POOL32AXF_1_7 = 0x07,
17485 };
17486
17487 /* POOL32Axf_2 instruction pool */
17488 enum {
17489 NM_POOL32AXF_2_0_7 = 0x00,
17490 NM_POOL32AXF_2_8_15 = 0x01,
17491 NM_POOL32AXF_2_16_23 = 0x02,
17492 NM_POOL32AXF_2_24_31 = 0x03,
17493 };
17494
17495 /* POOL32Axf_7 instruction pool */
17496 enum {
17497 NM_SHRA_R_QB = 0x0,
17498 NM_SHRL_PH = 0x1,
17499 NM_REPL_QB = 0x2,
17500 };
17501
17502 /* POOL32Axf_1_0 instruction pool */
17503 enum {
17504 NM_MFHI = 0x0,
17505 NM_MFLO = 0x1,
17506 NM_MTHI = 0x2,
17507 NM_MTLO = 0x3,
17508 };
17509
17510 /* POOL32Axf_1_1 instruction pool */
17511 enum {
17512 NM_MTHLIP = 0x0,
17513 NM_SHILOV = 0x1,
17514 };
17515
17516 /* POOL32Axf_1_3 instruction pool */
17517 enum {
17518 NM_RDDSP = 0x0,
17519 NM_WRDSP = 0x1,
17520 NM_EXTP = 0x2,
17521 NM_EXTPDP = 0x3,
17522 };
17523
17524 /* POOL32Axf_1_4 instruction pool */
17525 enum {
17526 NM_SHLL_QB = 0x0,
17527 NM_SHRL_QB = 0x1,
17528 };
17529
17530 /* POOL32Axf_1_5 instruction pool */
17531 enum {
17532 NM_MAQ_S_W_PHR = 0x0,
17533 NM_MAQ_S_W_PHL = 0x1,
17534 NM_MAQ_SA_W_PHR = 0x2,
17535 NM_MAQ_SA_W_PHL = 0x3,
17536 };
17537
17538 /* POOL32Axf_1_7 instruction pool */
17539 enum {
17540 NM_EXTR_W = 0x0,
17541 NM_EXTR_R_W = 0x1,
17542 NM_EXTR_RS_W = 0x2,
17543 NM_EXTR_S_H = 0x3,
17544 };
17545
17546 /* POOL32Axf_2_0_7 instruction pool */
17547 enum {
17548 NM_DPA_W_PH = 0x0,
17549 NM_DPAQ_S_W_PH = 0x1,
17550 NM_DPS_W_PH = 0x2,
17551 NM_DPSQ_S_W_PH = 0x3,
17552 NM_BALIGN = 0x4,
17553 NM_MADD = 0x5,
17554 NM_MULT = 0x6,
17555 NM_EXTRV_W = 0x7,
17556 };
17557
17558 /* POOL32Axf_2_8_15 instruction pool */
17559 enum {
17560 NM_DPAX_W_PH = 0x0,
17561 NM_DPAQ_SA_L_W = 0x1,
17562 NM_DPSX_W_PH = 0x2,
17563 NM_DPSQ_SA_L_W = 0x3,
17564 NM_MADDU = 0x5,
17565 NM_MULTU = 0x6,
17566 NM_EXTRV_R_W = 0x7,
17567 };
17568
17569 /* POOL32Axf_2_16_23 instruction pool */
17570 enum {
17571 NM_DPAU_H_QBL = 0x0,
17572 NM_DPAQX_S_W_PH = 0x1,
17573 NM_DPSU_H_QBL = 0x2,
17574 NM_DPSQX_S_W_PH = 0x3,
17575 NM_EXTPV = 0x4,
17576 NM_MSUB = 0x5,
17577 NM_MULSA_W_PH = 0x6,
17578 NM_EXTRV_RS_W = 0x7,
17579 };
17580
17581 /* POOL32Axf_2_24_31 instruction pool */
17582 enum {
17583 NM_DPAU_H_QBR = 0x0,
17584 NM_DPAQX_SA_W_PH = 0x1,
17585 NM_DPSU_H_QBR = 0x2,
17586 NM_DPSQX_SA_W_PH = 0x3,
17587 NM_EXTPDPV = 0x4,
17588 NM_MSUBU = 0x5,
17589 NM_MULSAQ_S_W_PH = 0x6,
17590 NM_EXTRV_S_H = 0x7,
17591 };
17592
17593 /* POOL32Axf_{4, 5} instruction pool */
17594 enum {
17595 NM_CLO = 0x25,
17596 NM_CLZ = 0x2d,
17597
17598 NM_TLBP = 0x01,
17599 NM_TLBR = 0x09,
17600 NM_TLBWI = 0x11,
17601 NM_TLBWR = 0x19,
17602 NM_TLBINV = 0x03,
17603 NM_TLBINVF = 0x0b,
17604 NM_DI = 0x23,
17605 NM_EI = 0x2b,
17606 NM_RDPGPR = 0x70,
17607 NM_WRPGPR = 0x78,
17608 NM_WAIT = 0x61,
17609 NM_DERET = 0x71,
17610 NM_ERETX = 0x79,
17611
17612 /* nanoMIPS DSP instructions */
17613 NM_ABSQ_S_QB = 0x00,
17614 NM_ABSQ_S_PH = 0x08,
17615 NM_ABSQ_S_W = 0x10,
17616 NM_PRECEQ_W_PHL = 0x28,
17617 NM_PRECEQ_W_PHR = 0x30,
17618 NM_PRECEQU_PH_QBL = 0x38,
17619 NM_PRECEQU_PH_QBR = 0x48,
17620 NM_PRECEU_PH_QBL = 0x58,
17621 NM_PRECEU_PH_QBR = 0x68,
17622 NM_PRECEQU_PH_QBLA = 0x39,
17623 NM_PRECEQU_PH_QBRA = 0x49,
17624 NM_PRECEU_PH_QBLA = 0x59,
17625 NM_PRECEU_PH_QBRA = 0x69,
17626 NM_REPLV_PH = 0x01,
17627 NM_REPLV_QB = 0x09,
17628 NM_BITREV = 0x18,
17629 NM_INSV = 0x20,
17630 NM_RADDU_W_QB = 0x78,
17631
17632 NM_BITSWAP = 0x05,
17633 NM_WSBH = 0x3d,
17634 };
17635
17636 /* PP.SR instruction pool */
17637 enum {
17638 NM_SAVE = 0x00,
17639 NM_RESTORE = 0x02,
17640 NM_RESTORE_JRC = 0x03,
17641 };
17642
17643 /* P.SR.F instruction pool */
17644 enum {
17645 NM_SAVEF = 0x00,
17646 NM_RESTOREF = 0x01,
17647 };
17648
17649 /* P16.SYSCALL instruction pool */
17650 enum {
17651 NM_SYSCALL16 = 0x00,
17652 NM_HYPCALL16 = 0x01,
17653 };
17654
17655 /* POOL16C_00 instruction pool */
17656 enum {
17657 NM_NOT16 = 0x00,
17658 NM_XOR16 = 0x01,
17659 NM_AND16 = 0x02,
17660 NM_OR16 = 0x03,
17661 };
17662
17663 /* PP.LSX and PP.LSXS instruction pool */
17664 enum {
17665 NM_LBX = 0x00,
17666 NM_LHX = 0x04,
17667 NM_LWX = 0x08,
17668 NM_LDX = 0x0c,
17669
17670 NM_SBX = 0x01,
17671 NM_SHX = 0x05,
17672 NM_SWX = 0x09,
17673 NM_SDX = 0x0d,
17674
17675 NM_LBUX = 0x02,
17676 NM_LHUX = 0x06,
17677 NM_LWC1X = 0x0a,
17678 NM_LDC1X = 0x0e,
17679
17680 NM_LWUX = 0x07,
17681 NM_SWC1X = 0x0b,
17682 NM_SDC1X = 0x0f,
17683
17684 NM_LHXS = 0x04,
17685 NM_LWXS = 0x08,
17686 NM_LDXS = 0x0c,
17687
17688 NM_SHXS = 0x05,
17689 NM_SWXS = 0x09,
17690 NM_SDXS = 0x0d,
17691
17692 NM_LHUXS = 0x06,
17693 NM_LWC1XS = 0x0a,
17694 NM_LDC1XS = 0x0e,
17695
17696 NM_LWUXS = 0x07,
17697 NM_SWC1XS = 0x0b,
17698 NM_SDC1XS = 0x0f,
17699 };
17700
17701 /* ERETx instruction pool */
17702 enum {
17703 NM_ERET = 0x00,
17704 NM_ERETNC = 0x01,
17705 };
17706
17707 /* POOL32FxF_{0, 1} insturction pool */
17708 enum {
17709 NM_CFC1 = 0x40,
17710 NM_CTC1 = 0x60,
17711 NM_MFC1 = 0x80,
17712 NM_MTC1 = 0xa0,
17713 NM_MFHC1 = 0xc0,
17714 NM_MTHC1 = 0xe0,
17715
17716 NM_CVT_S_PL = 0x84,
17717 NM_CVT_S_PU = 0xa4,
17718
17719 NM_CVT_L_S = 0x004,
17720 NM_CVT_L_D = 0x104,
17721 NM_CVT_W_S = 0x024,
17722 NM_CVT_W_D = 0x124,
17723
17724 NM_RSQRT_S = 0x008,
17725 NM_RSQRT_D = 0x108,
17726
17727 NM_SQRT_S = 0x028,
17728 NM_SQRT_D = 0x128,
17729
17730 NM_RECIP_S = 0x048,
17731 NM_RECIP_D = 0x148,
17732
17733 NM_FLOOR_L_S = 0x00c,
17734 NM_FLOOR_L_D = 0x10c,
17735
17736 NM_FLOOR_W_S = 0x02c,
17737 NM_FLOOR_W_D = 0x12c,
17738
17739 NM_CEIL_L_S = 0x04c,
17740 NM_CEIL_L_D = 0x14c,
17741 NM_CEIL_W_S = 0x06c,
17742 NM_CEIL_W_D = 0x16c,
17743 NM_TRUNC_L_S = 0x08c,
17744 NM_TRUNC_L_D = 0x18c,
17745 NM_TRUNC_W_S = 0x0ac,
17746 NM_TRUNC_W_D = 0x1ac,
17747 NM_ROUND_L_S = 0x0cc,
17748 NM_ROUND_L_D = 0x1cc,
17749 NM_ROUND_W_S = 0x0ec,
17750 NM_ROUND_W_D = 0x1ec,
17751
17752 NM_MOV_S = 0x01,
17753 NM_MOV_D = 0x81,
17754 NM_ABS_S = 0x0d,
17755 NM_ABS_D = 0x8d,
17756 NM_NEG_S = 0x2d,
17757 NM_NEG_D = 0xad,
17758 NM_CVT_D_S = 0x04d,
17759 NM_CVT_D_W = 0x0cd,
17760 NM_CVT_D_L = 0x14d,
17761 NM_CVT_S_D = 0x06d,
17762 NM_CVT_S_W = 0x0ed,
17763 NM_CVT_S_L = 0x16d,
17764 };
17765
17766 /* P.LL instruction pool */
17767 enum {
17768 NM_LL = 0x00,
17769 NM_LLWP = 0x01,
17770 };
17771
17772 /* P.SC instruction pool */
17773 enum {
17774 NM_SC = 0x00,
17775 NM_SCWP = 0x01,
17776 };
17777
17778 /* P.DVP instruction pool */
17779 enum {
17780 NM_DVP = 0x00,
17781 NM_EVP = 0x01,
17782 };
17783
17784
17785 /*
17786 *
17787 * nanoMIPS decoding engine
17788 *
17789 */
17790
17791
17792 /* extraction utilities */
17793
17794 #define NANOMIPS_EXTRACT_RT3(op) ((op >> 7) & 0x7)
17795 #define NANOMIPS_EXTRACT_RS3(op) ((op >> 4) & 0x7)
17796 #define NANOMIPS_EXTRACT_RD3(op) ((op >> 1) & 0x7)
17797 #define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
17798 #define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
17799
17800 /* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr3'). */
17801 static inline int decode_gpr_gpr3(int r)
17802 {
17803 static const int map[] = { 16, 17, 18, 19, 4, 5, 6, 7 };
17804
17805 return map[r & 0x7];
17806 }
17807
17808 /* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr3.src.store'). */
17809 static inline int decode_gpr_gpr3_src_store(int r)
17810 {
17811 static const int map[] = { 0, 17, 18, 19, 4, 5, 6, 7 };
17812
17813 return map[r & 0x7];
17814 }
17815
17816 /* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr4'). */
17817 static inline int decode_gpr_gpr4(int r)
17818 {
17819 static const int map[] = { 8, 9, 10, 11, 4, 5, 6, 7,
17820 16, 17, 18, 19, 20, 21, 22, 23 };
17821
17822 return map[r & 0xf];
17823 }
17824
17825 /* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr4.zero'). */
17826 static inline int decode_gpr_gpr4_zero(int r)
17827 {
17828 static const int map[] = { 8, 9, 10, 0, 4, 5, 6, 7,
17829 16, 17, 18, 19, 20, 21, 22, 23 };
17830
17831 return map[r & 0xf];
17832 }
17833
17834
17835 static void gen_adjust_sp(DisasContext *ctx, int u)
17836 {
17837 gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], u);
17838 }
17839
17840 static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count,
17841 uint8_t gp, uint16_t u)
17842 {
17843 int counter = 0;
17844 TCGv va = tcg_temp_new();
17845 TCGv t0 = tcg_temp_new();
17846
17847 while (counter != count) {
17848 bool use_gp = gp && (counter == count - 1);
17849 int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f);
17850 int this_offset = -((counter + 1) << 2);
17851 gen_base_offset_addr(ctx, va, 29, this_offset);
17852 gen_load_gpr(t0, this_rt);
17853 tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx,
17854 (MO_TEUL | ctx->default_tcg_memop_mask));
17855 counter++;
17856 }
17857
17858 /* adjust stack pointer */
17859 gen_adjust_sp(ctx, -u);
17860
17861 tcg_temp_free(t0);
17862 tcg_temp_free(va);
17863 }
17864
17865 static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
17866 uint8_t gp, uint16_t u)
17867 {
17868 int counter = 0;
17869 TCGv va = tcg_temp_new();
17870 TCGv t0 = tcg_temp_new();
17871
17872 while (counter != count) {
17873 bool use_gp = gp && (counter == count - 1);
17874 int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f);
17875 int this_offset = u - ((counter + 1) << 2);
17876 gen_base_offset_addr(ctx, va, 29, this_offset);
17877 tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TESL |
17878 ctx->default_tcg_memop_mask);
17879 tcg_gen_ext32s_tl(t0, t0);
17880 gen_store_gpr(t0, this_rt);
17881 counter++;
17882 }
17883
17884 /* adjust stack pointer */
17885 gen_adjust_sp(ctx, u);
17886
17887 tcg_temp_free(t0);
17888 tcg_temp_free(va);
17889 }
17890
17891 static void gen_pool16c_nanomips_insn(DisasContext *ctx)
17892 {
17893 int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
17894 int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
17895
17896 switch (extract32(ctx->opcode, 2, 2)) {
17897 case NM_NOT16:
17898 gen_logic(ctx, OPC_NOR, rt, rs, 0);
17899 break;
17900 case NM_AND16:
17901 gen_logic(ctx, OPC_AND, rt, rt, rs);
17902 break;
17903 case NM_XOR16:
17904 gen_logic(ctx, OPC_XOR, rt, rt, rs);
17905 break;
17906 case NM_OR16:
17907 gen_logic(ctx, OPC_OR, rt, rt, rs);
17908 break;
17909 }
17910 }
17911
17912 static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
17913 {
17914 int rt = extract32(ctx->opcode, 21, 5);
17915 int rs = extract32(ctx->opcode, 16, 5);
17916 int rd = extract32(ctx->opcode, 11, 5);
17917
17918 switch (extract32(ctx->opcode, 3, 7)) {
17919 case NM_P_TRAP:
17920 switch (extract32(ctx->opcode, 10, 1)) {
17921 case NM_TEQ:
17922 check_nms(ctx);
17923 gen_trap(ctx, OPC_TEQ, rs, rt, -1);
17924 break;
17925 case NM_TNE:
17926 check_nms(ctx);
17927 gen_trap(ctx, OPC_TNE, rs, rt, -1);
17928 break;
17929 }
17930 break;
17931 case NM_RDHWR:
17932 check_nms(ctx);
17933 gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3));
17934 break;
17935 case NM_SEB:
17936 check_nms(ctx);
17937 gen_bshfl(ctx, OPC_SEB, rs, rt);
17938 break;
17939 case NM_SEH:
17940 gen_bshfl(ctx, OPC_SEH, rs, rt);
17941 break;
17942 case NM_SLLV:
17943 gen_shift(ctx, OPC_SLLV, rd, rt, rs);
17944 break;
17945 case NM_SRLV:
17946 gen_shift(ctx, OPC_SRLV, rd, rt, rs);
17947 break;
17948 case NM_SRAV:
17949 gen_shift(ctx, OPC_SRAV, rd, rt, rs);
17950 break;
17951 case NM_ROTRV:
17952 gen_shift(ctx, OPC_ROTRV, rd, rt, rs);
17953 break;
17954 case NM_ADD:
17955 gen_arith(ctx, OPC_ADD, rd, rs, rt);
17956 break;
17957 case NM_ADDU:
17958 gen_arith(ctx, OPC_ADDU, rd, rs, rt);
17959 break;
17960 case NM_SUB:
17961 check_nms(ctx);
17962 gen_arith(ctx, OPC_SUB, rd, rs, rt);
17963 break;
17964 case NM_SUBU:
17965 gen_arith(ctx, OPC_SUBU, rd, rs, rt);
17966 break;
17967 case NM_P_CMOVE:
17968 switch (extract32(ctx->opcode, 10, 1)) {
17969 case NM_MOVZ:
17970 gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt);
17971 break;
17972 case NM_MOVN:
17973 gen_cond_move(ctx, OPC_MOVN, rd, rs, rt);
17974 break;
17975 }
17976 break;
17977 case NM_AND:
17978 gen_logic(ctx, OPC_AND, rd, rs, rt);
17979 break;
17980 case NM_OR:
17981 gen_logic(ctx, OPC_OR, rd, rs, rt);
17982 break;
17983 case NM_NOR:
17984 gen_logic(ctx, OPC_NOR, rd, rs, rt);
17985 break;
17986 case NM_XOR:
17987 gen_logic(ctx, OPC_XOR, rd, rs, rt);
17988 break;
17989 case NM_SLT:
17990 gen_slt(ctx, OPC_SLT, rd, rs, rt);
17991 break;
17992 case NM_P_SLTU:
17993 if (rd == 0) {
17994 /* P_DVP */
17995 #ifndef CONFIG_USER_ONLY
17996 TCGv t0 = tcg_temp_new();
17997 switch (extract32(ctx->opcode, 10, 1)) {
17998 case NM_DVP:
17999 if (ctx->vp) {
18000 check_cp0_enabled(ctx);
18001 gen_helper_dvp(t0, cpu_env);
18002 gen_store_gpr(t0, rt);
18003 }
18004 break;
18005 case NM_EVP:
18006 if (ctx->vp) {
18007 check_cp0_enabled(ctx);
18008 gen_helper_evp(t0, cpu_env);
18009 gen_store_gpr(t0, rt);
18010 }
18011 break;
18012 }
18013 tcg_temp_free(t0);
18014 #endif
18015 } else {
18016 gen_slt(ctx, OPC_SLTU, rd, rs, rt);
18017 }
18018 break;
18019 case NM_SOV:
18020 {
18021 TCGv t0 = tcg_temp_new();
18022 TCGv t1 = tcg_temp_new();
18023 TCGv t2 = tcg_temp_new();
18024
18025 gen_load_gpr(t1, rs);
18026 gen_load_gpr(t2, rt);
18027 tcg_gen_add_tl(t0, t1, t2);
18028 tcg_gen_ext32s_tl(t0, t0);
18029 tcg_gen_xor_tl(t1, t1, t2);
18030 tcg_gen_xor_tl(t2, t0, t2);
18031 tcg_gen_andc_tl(t1, t2, t1);
18032
18033 /* operands of same sign, result different sign */
18034 tcg_gen_setcondi_tl(TCG_COND_LT, t0, t1, 0);
18035 gen_store_gpr(t0, rd);
18036
18037 tcg_temp_free(t0);
18038 tcg_temp_free(t1);
18039 tcg_temp_free(t2);
18040 }
18041 break;
18042 case NM_MUL:
18043 gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt);
18044 break;
18045 case NM_MUH:
18046 gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt);
18047 break;
18048 case NM_MULU:
18049 gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt);
18050 break;
18051 case NM_MUHU:
18052 gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt);
18053 break;
18054 case NM_DIV:
18055 gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt);
18056 break;
18057 case NM_MOD:
18058 gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt);
18059 break;
18060 case NM_DIVU:
18061 gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt);
18062 break;
18063 case NM_MODU:
18064 gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt);
18065 break;
18066 #ifndef CONFIG_USER_ONLY
18067 case NM_MFC0:
18068 check_cp0_enabled(ctx);
18069 if (rt == 0) {
18070 /* Treat as NOP. */
18071 break;
18072 }
18073 gen_mfc0(ctx, cpu_gpr[rt], rs, extract32(ctx->opcode, 11, 3));
18074 break;
18075 case NM_MTC0:
18076 check_cp0_enabled(ctx);
18077 {
18078 TCGv t0 = tcg_temp_new();
18079
18080 gen_load_gpr(t0, rt);
18081 gen_mtc0(ctx, t0, rs, extract32(ctx->opcode, 11, 3));
18082 tcg_temp_free(t0);
18083 }
18084 break;
18085 case NM_D_E_MT_VPE:
18086 {
18087 uint8_t sc = extract32(ctx->opcode, 10, 1);
18088 TCGv t0 = tcg_temp_new();
18089
18090 switch (sc) {
18091 case 0:
18092 if (rs == 1) {
18093 /* DMT */
18094 check_cp0_mt(ctx);
18095 gen_helper_dmt(t0);
18096 gen_store_gpr(t0, rt);
18097 } else if (rs == 0) {
18098 /* DVPE */
18099 check_cp0_mt(ctx);
18100 gen_helper_dvpe(t0, cpu_env);
18101 gen_store_gpr(t0, rt);
18102 } else {
18103 gen_reserved_instruction(ctx);
18104 }
18105 break;
18106 case 1:
18107 if (rs == 1) {
18108 /* EMT */
18109 check_cp0_mt(ctx);
18110 gen_helper_emt(t0);
18111 gen_store_gpr(t0, rt);
18112 } else if (rs == 0) {
18113 /* EVPE */
18114 check_cp0_mt(ctx);
18115 gen_helper_evpe(t0, cpu_env);
18116 gen_store_gpr(t0, rt);
18117 } else {
18118 gen_reserved_instruction(ctx);
18119 }
18120 break;
18121 }
18122
18123 tcg_temp_free(t0);
18124 }
18125 break;
18126 case NM_FORK:
18127 check_mt(ctx);
18128 {
18129 TCGv t0 = tcg_temp_new();
18130 TCGv t1 = tcg_temp_new();
18131
18132 gen_load_gpr(t0, rt);
18133 gen_load_gpr(t1, rs);
18134 gen_helper_fork(t0, t1);
18135 tcg_temp_free(t0);
18136 tcg_temp_free(t1);
18137 }
18138 break;
18139 case NM_MFTR:
18140 case NM_MFHTR:
18141 check_cp0_enabled(ctx);
18142 if (rd == 0) {
18143 /* Treat as NOP. */
18144 return;
18145 }
18146 gen_mftr(env, ctx, rs, rt, extract32(ctx->opcode, 10, 1),
18147 extract32(ctx->opcode, 11, 5), extract32(ctx->opcode, 3, 1));
18148 break;
18149 case NM_MTTR:
18150 case NM_MTHTR:
18151 check_cp0_enabled(ctx);
18152 gen_mttr(env, ctx, rs, rt, extract32(ctx->opcode, 10, 1),
18153 extract32(ctx->opcode, 11, 5), extract32(ctx->opcode, 3, 1));
18154 break;
18155 case NM_YIELD:
18156 check_mt(ctx);
18157 {
18158 TCGv t0 = tcg_temp_new();
18159
18160 gen_load_gpr(t0, rs);
18161 gen_helper_yield(t0, cpu_env, t0);
18162 gen_store_gpr(t0, rt);
18163 tcg_temp_free(t0);
18164 }
18165 break;
18166 #endif
18167 default:
18168 gen_reserved_instruction(ctx);
18169 break;
18170 }
18171 }
18172
18173 /* dsp */
18174 static void gen_pool32axf_1_5_nanomips_insn(DisasContext *ctx, uint32_t opc,
18175 int ret, int v1, int v2)
18176 {
18177 TCGv_i32 t0;
18178 TCGv v0_t;
18179 TCGv v1_t;
18180
18181 t0 = tcg_temp_new_i32();
18182
18183 v0_t = tcg_temp_new();
18184 v1_t = tcg_temp_new();
18185
18186 tcg_gen_movi_i32(t0, v2 >> 3);
18187
18188 gen_load_gpr(v0_t, ret);
18189 gen_load_gpr(v1_t, v1);
18190
18191 switch (opc) {
18192 case NM_MAQ_S_W_PHR:
18193 check_dsp(ctx);
18194 gen_helper_maq_s_w_phr(t0, v1_t, v0_t, cpu_env);
18195 break;
18196 case NM_MAQ_S_W_PHL:
18197 check_dsp(ctx);
18198 gen_helper_maq_s_w_phl(t0, v1_t, v0_t, cpu_env);
18199 break;
18200 case NM_MAQ_SA_W_PHR:
18201 check_dsp(ctx);
18202 gen_helper_maq_sa_w_phr(t0, v1_t, v0_t, cpu_env);
18203 break;
18204 case NM_MAQ_SA_W_PHL:
18205 check_dsp(ctx);
18206 gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, cpu_env);
18207 break;
18208 default:
18209 gen_reserved_instruction(ctx);
18210 break;
18211 }
18212
18213 tcg_temp_free_i32(t0);
18214
18215 tcg_temp_free(v0_t);
18216 tcg_temp_free(v1_t);
18217 }
18218
18219
18220 static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
18221 int ret, int v1, int v2)
18222 {
18223 int16_t imm;
18224 TCGv t0 = tcg_temp_new();
18225 TCGv t1 = tcg_temp_new();
18226 TCGv v0_t = tcg_temp_new();
18227
18228 gen_load_gpr(v0_t, v1);
18229
18230 switch (opc) {
18231 case NM_POOL32AXF_1_0:
18232 check_dsp(ctx);
18233 switch (extract32(ctx->opcode, 12, 2)) {
18234 case NM_MFHI:
18235 gen_HILO(ctx, OPC_MFHI, v2 >> 3, ret);
18236 break;
18237 case NM_MFLO:
18238 gen_HILO(ctx, OPC_MFLO, v2 >> 3, ret);
18239 break;
18240 case NM_MTHI:
18241 gen_HILO(ctx, OPC_MTHI, v2 >> 3, v1);
18242 break;
18243 case NM_MTLO:
18244 gen_HILO(ctx, OPC_MTLO, v2 >> 3, v1);
18245 break;
18246 }
18247 break;
18248 case NM_POOL32AXF_1_1:
18249 check_dsp(ctx);
18250 switch (extract32(ctx->opcode, 12, 2)) {
18251 case NM_MTHLIP:
18252 tcg_gen_movi_tl(t0, v2);
18253 gen_helper_mthlip(t0, v0_t, cpu_env);
18254 break;
18255 case NM_SHILOV:
18256 tcg_gen_movi_tl(t0, v2 >> 3);
18257 gen_helper_shilo(t0, v0_t, cpu_env);
18258 break;
18259 default:
18260 gen_reserved_instruction(ctx);
18261 break;
18262 }
18263 break;
18264 case NM_POOL32AXF_1_3:
18265 check_dsp(ctx);
18266 imm = extract32(ctx->opcode, 14, 7);
18267 switch (extract32(ctx->opcode, 12, 2)) {
18268 case NM_RDDSP:
18269 tcg_gen_movi_tl(t0, imm);
18270 gen_helper_rddsp(t0, t0, cpu_env);
18271 gen_store_gpr(t0, ret);
18272 break;
18273 case NM_WRDSP:
18274 gen_load_gpr(t0, ret);
18275 tcg_gen_movi_tl(t1, imm);
18276 gen_helper_wrdsp(t0, t1, cpu_env);
18277 break;
18278 case NM_EXTP:
18279 tcg_gen_movi_tl(t0, v2 >> 3);
18280 tcg_gen_movi_tl(t1, v1);
18281 gen_helper_extp(t0, t0, t1, cpu_env);
18282 gen_store_gpr(t0, ret);
18283 break;
18284 case NM_EXTPDP:
18285 tcg_gen_movi_tl(t0, v2 >> 3);
18286 tcg_gen_movi_tl(t1, v1);
18287 gen_helper_extpdp(t0, t0, t1, cpu_env);
18288 gen_store_gpr(t0, ret);
18289 break;
18290 }
18291 break;
18292 case NM_POOL32AXF_1_4:
18293 check_dsp(ctx);
18294 tcg_gen_movi_tl(t0, v2 >> 2);
18295 switch (extract32(ctx->opcode, 12, 1)) {
18296 case NM_SHLL_QB:
18297 gen_helper_shll_qb(t0, t0, v0_t, cpu_env);
18298 gen_store_gpr(t0, ret);
18299 break;
18300 case NM_SHRL_QB:
18301 gen_helper_shrl_qb(t0, t0, v0_t);
18302 gen_store_gpr(t0, ret);
18303 break;
18304 }
18305 break;
18306 case NM_POOL32AXF_1_5:
18307 opc = extract32(ctx->opcode, 12, 2);
18308 gen_pool32axf_1_5_nanomips_insn(ctx, opc, ret, v1, v2);
18309 break;
18310 case NM_POOL32AXF_1_7:
18311 check_dsp(ctx);
18312 tcg_gen_movi_tl(t0, v2 >> 3);
18313 tcg_gen_movi_tl(t1, v1);
18314 switch (extract32(ctx->opcode, 12, 2)) {
18315 case NM_EXTR_W:
18316 gen_helper_extr_w(t0, t0, t1, cpu_env);
18317 gen_store_gpr(t0, ret);
18318 break;
18319 case NM_EXTR_R_W:
18320 gen_helper_extr_r_w(t0, t0, t1, cpu_env);
18321 gen_store_gpr(t0, ret);
18322 break;
18323 case NM_EXTR_RS_W:
18324 gen_helper_extr_rs_w(t0, t0, t1, cpu_env);
18325 gen_store_gpr(t0, ret);
18326 break;
18327 case NM_EXTR_S_H:
18328 gen_helper_extr_s_h(t0, t0, t1, cpu_env);
18329 gen_store_gpr(t0, ret);
18330 break;
18331 }
18332 break;
18333 default:
18334 gen_reserved_instruction(ctx);
18335 break;
18336 }
18337
18338 tcg_temp_free(t0);
18339 tcg_temp_free(t1);
18340 tcg_temp_free(v0_t);
18341 }
18342
18343 static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
18344 TCGv v0, TCGv v1, int rd)
18345 {
18346 TCGv_i32 t0;
18347
18348 t0 = tcg_temp_new_i32();
18349
18350 tcg_gen_movi_i32(t0, rd >> 3);
18351
18352 switch (opc) {
18353 case NM_POOL32AXF_2_0_7:
18354 switch (extract32(ctx->opcode, 9, 3)) {
18355 case NM_DPA_W_PH:
18356 check_dsp_r2(ctx);
18357 gen_helper_dpa_w_ph(t0, v1, v0, cpu_env);
18358 break;
18359 case NM_DPAQ_S_W_PH:
18360 check_dsp(ctx);
18361 gen_helper_dpaq_s_w_ph(t0, v1, v0, cpu_env);
18362 break;
18363 case NM_DPS_W_PH:
18364 check_dsp_r2(ctx);
18365 gen_helper_dps_w_ph(t0, v1, v0, cpu_env);
18366 break;
18367 case NM_DPSQ_S_W_PH:
18368 check_dsp(ctx);
18369 gen_helper_dpsq_s_w_ph(t0, v1, v0, cpu_env);
18370 break;
18371 default:
18372 gen_reserved_instruction(ctx);
18373 break;
18374 }
18375 break;
18376 case NM_POOL32AXF_2_8_15:
18377 switch (extract32(ctx->opcode, 9, 3)) {
18378 case NM_DPAX_W_PH:
18379 check_dsp_r2(ctx);
18380 gen_helper_dpax_w_ph(t0, v0, v1, cpu_env);
18381 break;
18382 case NM_DPAQ_SA_L_W:
18383 check_dsp(ctx);
18384 gen_helper_dpaq_sa_l_w(t0, v0, v1, cpu_env);
18385 break;
18386 case NM_DPSX_W_PH:
18387 check_dsp_r2(ctx);
18388 gen_helper_dpsx_w_ph(t0, v0, v1, cpu_env);
18389 break;
18390 case NM_DPSQ_SA_L_W:
18391 check_dsp(ctx);
18392 gen_helper_dpsq_sa_l_w(t0, v0, v1, cpu_env);
18393 break;
18394 default:
18395 gen_reserved_instruction(ctx);
18396 break;
18397 }
18398 break;
18399 case NM_POOL32AXF_2_16_23:
18400 switch (extract32(ctx->opcode, 9, 3)) {
18401 case NM_DPAU_H_QBL:
18402 check_dsp(ctx);
18403 gen_helper_dpau_h_qbl(t0, v0, v1, cpu_env);
18404 break;
18405 case NM_DPAQX_S_W_PH:
18406 check_dsp_r2(ctx);
18407 gen_helper_dpaqx_s_w_ph(t0, v0, v1, cpu_env);
18408 break;
18409 case NM_DPSU_H_QBL:
18410 check_dsp(ctx);
18411 gen_helper_dpsu_h_qbl(t0, v0, v1, cpu_env);
18412 break;
18413 case NM_DPSQX_S_W_PH:
18414 check_dsp_r2(ctx);
18415 gen_helper_dpsqx_s_w_ph(t0, v0, v1, cpu_env);
18416 break;
18417 case NM_MULSA_W_PH:
18418 check_dsp_r2(ctx);
18419 gen_helper_mulsa_w_ph(t0, v0, v1, cpu_env);
18420 break;
18421 default:
18422 gen_reserved_instruction(ctx);
18423 break;
18424 }
18425 break;
18426 case NM_POOL32AXF_2_24_31:
18427 switch (extract32(ctx->opcode, 9, 3)) {
18428 case NM_DPAU_H_QBR:
18429 check_dsp(ctx);
18430 gen_helper_dpau_h_qbr(t0, v1, v0, cpu_env);
18431 break;
18432 case NM_DPAQX_SA_W_PH:
18433 check_dsp_r2(ctx);
18434 gen_helper_dpaqx_sa_w_ph(t0, v1, v0, cpu_env);
18435 break;
18436 case NM_DPSU_H_QBR:
18437 check_dsp(ctx);
18438 gen_helper_dpsu_h_qbr(t0, v1, v0, cpu_env);
18439 break;
18440 case NM_DPSQX_SA_W_PH:
18441 check_dsp_r2(ctx);
18442 gen_helper_dpsqx_sa_w_ph(t0, v1, v0, cpu_env);
18443 break;
18444 case NM_MULSAQ_S_W_PH:
18445 check_dsp(ctx);
18446 gen_helper_mulsaq_s_w_ph(t0, v1, v0, cpu_env);
18447 break;
18448 default:
18449 gen_reserved_instruction(ctx);
18450 break;
18451 }
18452 break;
18453 default:
18454 gen_reserved_instruction(ctx);
18455 break;
18456 }
18457
18458 tcg_temp_free_i32(t0);
18459 }
18460
18461 static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
18462 int rt, int rs, int rd)
18463 {
18464 int ret = rt;
18465 TCGv t0 = tcg_temp_new();
18466 TCGv t1 = tcg_temp_new();
18467 TCGv v0_t = tcg_temp_new();
18468 TCGv v1_t = tcg_temp_new();
18469
18470 gen_load_gpr(v0_t, rt);
18471 gen_load_gpr(v1_t, rs);
18472
18473 switch (opc) {
18474 case NM_POOL32AXF_2_0_7:
18475 switch (extract32(ctx->opcode, 9, 3)) {
18476 case NM_DPA_W_PH:
18477 case NM_DPAQ_S_W_PH:
18478 case NM_DPS_W_PH:
18479 case NM_DPSQ_S_W_PH:
18480 gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);
18481 break;
18482 case NM_BALIGN:
18483 check_dsp_r2(ctx);
18484 if (rt != 0) {
18485 gen_load_gpr(t0, rs);
18486 rd &= 3;
18487 if (rd != 0 && rd != 2) {
18488 tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 8 * rd);
18489 tcg_gen_ext32u_tl(t0, t0);
18490 tcg_gen_shri_tl(t0, t0, 8 * (4 - rd));
18491 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
18492 }
18493 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
18494 }
18495 break;
18496 case NM_MADD:
18497 check_dsp(ctx);
18498 {
18499 int acc = extract32(ctx->opcode, 14, 2);
18500 TCGv_i64 t2 = tcg_temp_new_i64();
18501 TCGv_i64 t3 = tcg_temp_new_i64();
18502
18503 gen_load_gpr(t0, rt);
18504 gen_load_gpr(t1, rs);
18505 tcg_gen_ext_tl_i64(t2, t0);
18506 tcg_gen_ext_tl_i64(t3, t1);
18507 tcg_gen_mul_i64(t2, t2, t3);
18508 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
18509 tcg_gen_add_i64(t2, t2, t3);
18510 tcg_temp_free_i64(t3);
18511 gen_move_low32(cpu_LO[acc], t2);
18512 gen_move_high32(cpu_HI[acc], t2);
18513 tcg_temp_free_i64(t2);
18514 }
18515 break;
18516 case NM_MULT:
18517 check_dsp(ctx);
18518 {
18519 int acc = extract32(ctx->opcode, 14, 2);
18520 TCGv_i32 t2 = tcg_temp_new_i32();
18521 TCGv_i32 t3 = tcg_temp_new_i32();
18522
18523 gen_load_gpr(t0, rs);
18524 gen_load_gpr(t1, rt);
18525 tcg_gen_trunc_tl_i32(t2, t0);
18526 tcg_gen_trunc_tl_i32(t3, t1);
18527 tcg_gen_muls2_i32(t2, t3, t2, t3);
18528 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
18529 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
18530 tcg_temp_free_i32(t2);
18531 tcg_temp_free_i32(t3);
18532 }
18533 break;
18534 case NM_EXTRV_W:
18535 check_dsp(ctx);
18536 gen_load_gpr(v1_t, rs);
18537 tcg_gen_movi_tl(t0, rd >> 3);
18538 gen_helper_extr_w(t0, t0, v1_t, cpu_env);
18539 gen_store_gpr(t0, ret);
18540 break;
18541 }
18542 break;
18543 case NM_POOL32AXF_2_8_15:
18544 switch (extract32(ctx->opcode, 9, 3)) {
18545 case NM_DPAX_W_PH:
18546 case NM_DPAQ_SA_L_W:
18547 case NM_DPSX_W_PH:
18548 case NM_DPSQ_SA_L_W:
18549 gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);
18550 break;
18551 case NM_MADDU:
18552 check_dsp(ctx);
18553 {
18554 int acc = extract32(ctx->opcode, 14, 2);
18555 TCGv_i64 t2 = tcg_temp_new_i64();
18556 TCGv_i64 t3 = tcg_temp_new_i64();
18557
18558 gen_load_gpr(t0, rs);
18559 gen_load_gpr(t1, rt);
18560 tcg_gen_ext32u_tl(t0, t0);
18561 tcg_gen_ext32u_tl(t1, t1);
18562 tcg_gen_extu_tl_i64(t2, t0);
18563 tcg_gen_extu_tl_i64(t3, t1);
18564 tcg_gen_mul_i64(t2, t2, t3);
18565 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
18566 tcg_gen_add_i64(t2, t2, t3);
18567 tcg_temp_free_i64(t3);
18568 gen_move_low32(cpu_LO[acc], t2);
18569 gen_move_high32(cpu_HI[acc], t2);
18570 tcg_temp_free_i64(t2);
18571 }
18572 break;
18573 case NM_MULTU:
18574 check_dsp(ctx);
18575 {
18576 int acc = extract32(ctx->opcode, 14, 2);
18577 TCGv_i32 t2 = tcg_temp_new_i32();
18578 TCGv_i32 t3 = tcg_temp_new_i32();
18579
18580 gen_load_gpr(t0, rs);
18581 gen_load_gpr(t1, rt);
18582 tcg_gen_trunc_tl_i32(t2, t0);
18583 tcg_gen_trunc_tl_i32(t3, t1);
18584 tcg_gen_mulu2_i32(t2, t3, t2, t3);
18585 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
18586 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
18587 tcg_temp_free_i32(t2);
18588 tcg_temp_free_i32(t3);
18589 }
18590 break;
18591 case NM_EXTRV_R_W:
18592 check_dsp(ctx);
18593 tcg_gen_movi_tl(t0, rd >> 3);
18594 gen_helper_extr_r_w(t0, t0, v1_t, cpu_env);
18595 gen_store_gpr(t0, ret);
18596 break;
18597 default:
18598 gen_reserved_instruction(ctx);
18599 break;
18600 }
18601 break;
18602 case NM_POOL32AXF_2_16_23:
18603 switch (extract32(ctx->opcode, 9, 3)) {
18604 case NM_DPAU_H_QBL:
18605 case NM_DPAQX_S_W_PH:
18606 case NM_DPSU_H_QBL:
18607 case NM_DPSQX_S_W_PH:
18608 case NM_MULSA_W_PH:
18609 gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);
18610 break;
18611 case NM_EXTPV:
18612 check_dsp(ctx);
18613 tcg_gen_movi_tl(t0, rd >> 3);
18614 gen_helper_extp(t0, t0, v1_t, cpu_env);
18615 gen_store_gpr(t0, ret);
18616 break;
18617 case NM_MSUB:
18618 check_dsp(ctx);
18619 {
18620 int acc = extract32(ctx->opcode, 14, 2);
18621 TCGv_i64 t2 = tcg_temp_new_i64();
18622 TCGv_i64 t3 = tcg_temp_new_i64();
18623
18624 gen_load_gpr(t0, rs);
18625 gen_load_gpr(t1, rt);
18626 tcg_gen_ext_tl_i64(t2, t0);
18627 tcg_gen_ext_tl_i64(t3, t1);
18628 tcg_gen_mul_i64(t2, t2, t3);
18629 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
18630 tcg_gen_sub_i64(t2, t3, t2);
18631 tcg_temp_free_i64(t3);
18632 gen_move_low32(cpu_LO[acc], t2);
18633 gen_move_high32(cpu_HI[acc], t2);
18634 tcg_temp_free_i64(t2);
18635 }
18636 break;
18637 case NM_EXTRV_RS_W:
18638 check_dsp(ctx);
18639 tcg_gen_movi_tl(t0, rd >> 3);
18640 gen_helper_extr_rs_w(t0, t0, v1_t, cpu_env);
18641 gen_store_gpr(t0, ret);
18642 break;
18643 }
18644 break;
18645 case NM_POOL32AXF_2_24_31:
18646 switch (extract32(ctx->opcode, 9, 3)) {
18647 case NM_DPAU_H_QBR:
18648 case NM_DPAQX_SA_W_PH:
18649 case NM_DPSU_H_QBR:
18650 case NM_DPSQX_SA_W_PH:
18651 case NM_MULSAQ_S_W_PH:
18652 gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);
18653 break;
18654 case NM_EXTPDPV:
18655 check_dsp(ctx);
18656 tcg_gen_movi_tl(t0, rd >> 3);
18657 gen_helper_extpdp(t0, t0, v1_t, cpu_env);
18658 gen_store_gpr(t0, ret);
18659 break;
18660 case NM_MSUBU:
18661 check_dsp(ctx);
18662 {
18663 int acc = extract32(ctx->opcode, 14, 2);
18664 TCGv_i64 t2 = tcg_temp_new_i64();
18665 TCGv_i64 t3 = tcg_temp_new_i64();
18666
18667 gen_load_gpr(t0, rs);
18668 gen_load_gpr(t1, rt);
18669 tcg_gen_ext32u_tl(t0, t0);
18670 tcg_gen_ext32u_tl(t1, t1);
18671 tcg_gen_extu_tl_i64(t2, t0);
18672 tcg_gen_extu_tl_i64(t3, t1);
18673 tcg_gen_mul_i64(t2, t2, t3);
18674 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
18675 tcg_gen_sub_i64(t2, t3, t2);
18676 tcg_temp_free_i64(t3);
18677 gen_move_low32(cpu_LO[acc], t2);
18678 gen_move_high32(cpu_HI[acc], t2);
18679 tcg_temp_free_i64(t2);
18680 }
18681 break;
18682 case NM_EXTRV_S_H:
18683 check_dsp(ctx);
18684 tcg_gen_movi_tl(t0, rd >> 3);
18685 gen_helper_extr_s_h(t0, t0, v0_t, cpu_env);
18686 gen_store_gpr(t0, ret);
18687 break;
18688 }
18689 break;
18690 default:
18691 gen_reserved_instruction(ctx);
18692 break;
18693 }
18694
18695 tcg_temp_free(t0);
18696 tcg_temp_free(t1);
18697
18698 tcg_temp_free(v0_t);
18699 tcg_temp_free(v1_t);
18700 }
18701
18702 static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
18703 int rt, int rs)
18704 {
18705 int ret = rt;
18706 TCGv t0 = tcg_temp_new();
18707 TCGv v0_t = tcg_temp_new();
18708
18709 gen_load_gpr(v0_t, rs);
18710
18711 switch (opc) {
18712 case NM_ABSQ_S_QB:
18713 check_dsp_r2(ctx);
18714 gen_helper_absq_s_qb(v0_t, v0_t, cpu_env);
18715 gen_store_gpr(v0_t, ret);
18716 break;
18717 case NM_ABSQ_S_PH:
18718 check_dsp(ctx);
18719 gen_helper_absq_s_ph(v0_t, v0_t, cpu_env);
18720 gen_store_gpr(v0_t, ret);
18721 break;
18722 case NM_ABSQ_S_W:
18723 check_dsp(ctx);
18724 gen_helper_absq_s_w(v0_t, v0_t, cpu_env);
18725 gen_store_gpr(v0_t, ret);
18726 break;
18727 case NM_PRECEQ_W_PHL:
18728 check_dsp(ctx);
18729 tcg_gen_andi_tl(v0_t, v0_t, 0xFFFF0000);
18730 tcg_gen_ext32s_tl(v0_t, v0_t);
18731 gen_store_gpr(v0_t, ret);
18732 break;
18733 case NM_PRECEQ_W_PHR:
18734 check_dsp(ctx);
18735 tcg_gen_andi_tl(v0_t, v0_t, 0x0000FFFF);
18736 tcg_gen_shli_tl(v0_t, v0_t, 16);
18737 tcg_gen_ext32s_tl(v0_t, v0_t);
18738 gen_store_gpr(v0_t, ret);
18739 break;
18740 case NM_PRECEQU_PH_QBL:
18741 check_dsp(ctx);
18742 gen_helper_precequ_ph_qbl(v0_t, v0_t);
18743 gen_store_gpr(v0_t, ret);
18744 break;
18745 case NM_PRECEQU_PH_QBR:
18746 check_dsp(ctx);
18747 gen_helper_precequ_ph_qbr(v0_t, v0_t);
18748 gen_store_gpr(v0_t, ret);
18749 break;
18750 case NM_PRECEQU_PH_QBLA:
18751 check_dsp(ctx);
18752 gen_helper_precequ_ph_qbla(v0_t, v0_t);
18753 gen_store_gpr(v0_t, ret);
18754 break;
18755 case NM_PRECEQU_PH_QBRA:
18756 check_dsp(ctx);
18757 gen_helper_precequ_ph_qbra(v0_t, v0_t);
18758 gen_store_gpr(v0_t, ret);
18759 break;
18760 case NM_PRECEU_PH_QBL:
18761 check_dsp(ctx);
18762 gen_helper_preceu_ph_qbl(v0_t, v0_t);
18763 gen_store_gpr(v0_t, ret);
18764 break;
18765 case NM_PRECEU_PH_QBR:
18766 check_dsp(ctx);
18767 gen_helper_preceu_ph_qbr(v0_t, v0_t);
18768 gen_store_gpr(v0_t, ret);
18769 break;
18770 case NM_PRECEU_PH_QBLA:
18771 check_dsp(ctx);
18772 gen_helper_preceu_ph_qbla(v0_t, v0_t);
18773 gen_store_gpr(v0_t, ret);
18774 break;
18775 case NM_PRECEU_PH_QBRA:
18776 check_dsp(ctx);
18777 gen_helper_preceu_ph_qbra(v0_t, v0_t);
18778 gen_store_gpr(v0_t, ret);
18779 break;
18780 case NM_REPLV_PH:
18781 check_dsp(ctx);
18782 tcg_gen_ext16u_tl(v0_t, v0_t);
18783 tcg_gen_shli_tl(t0, v0_t, 16);
18784 tcg_gen_or_tl(v0_t, v0_t, t0);
18785 tcg_gen_ext32s_tl(v0_t, v0_t);
18786 gen_store_gpr(v0_t, ret);
18787 break;
18788 case NM_REPLV_QB:
18789 check_dsp(ctx);
18790 tcg_gen_ext8u_tl(v0_t, v0_t);
18791 tcg_gen_shli_tl(t0, v0_t, 8);
18792 tcg_gen_or_tl(v0_t, v0_t, t0);
18793 tcg_gen_shli_tl(t0, v0_t, 16);
18794 tcg_gen_or_tl(v0_t, v0_t, t0);
18795 tcg_gen_ext32s_tl(v0_t, v0_t);
18796 gen_store_gpr(v0_t, ret);
18797 break;
18798 case NM_BITREV:
18799 check_dsp(ctx);
18800 gen_helper_bitrev(v0_t, v0_t);
18801 gen_store_gpr(v0_t, ret);
18802 break;
18803 case NM_INSV:
18804 check_dsp(ctx);
18805 {
18806 TCGv tv0 = tcg_temp_new();
18807
18808 gen_load_gpr(tv0, rt);
18809 gen_helper_insv(v0_t, cpu_env, v0_t, tv0);
18810 gen_store_gpr(v0_t, ret);
18811 tcg_temp_free(tv0);
18812 }
18813 break;
18814 case NM_RADDU_W_QB:
18815 check_dsp(ctx);
18816 gen_helper_raddu_w_qb(v0_t, v0_t);
18817 gen_store_gpr(v0_t, ret);
18818 break;
18819 case NM_BITSWAP:
18820 gen_bitswap(ctx, OPC_BITSWAP, ret, rs);
18821 break;
18822 case NM_CLO:
18823 check_nms(ctx);
18824 gen_cl(ctx, OPC_CLO, ret, rs);
18825 break;
18826 case NM_CLZ:
18827 check_nms(ctx);
18828 gen_cl(ctx, OPC_CLZ, ret, rs);
18829 break;
18830 case NM_WSBH:
18831 gen_bshfl(ctx, OPC_WSBH, ret, rs);
18832 break;
18833 default:
18834 gen_reserved_instruction(ctx);
18835 break;
18836 }
18837
18838 tcg_temp_free(v0_t);
18839 tcg_temp_free(t0);
18840 }
18841
18842 static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
18843 int rt, int rs, int rd)
18844 {
18845 TCGv t0 = tcg_temp_new();
18846 TCGv rs_t = tcg_temp_new();
18847
18848 gen_load_gpr(rs_t, rs);
18849
18850 switch (opc) {
18851 case NM_SHRA_R_QB:
18852 check_dsp_r2(ctx);
18853 tcg_gen_movi_tl(t0, rd >> 2);
18854 switch (extract32(ctx->opcode, 12, 1)) {
18855 case 0:
18856 /* NM_SHRA_QB */
18857 gen_helper_shra_qb(t0, t0, rs_t);
18858 gen_store_gpr(t0, rt);
18859 break;
18860 case 1:
18861 /* NM_SHRA_R_QB */
18862 gen_helper_shra_r_qb(t0, t0, rs_t);
18863 gen_store_gpr(t0, rt);
18864 break;
18865 }
18866 break;
18867 case NM_SHRL_PH:
18868 check_dsp_r2(ctx);
18869 tcg_gen_movi_tl(t0, rd >> 1);
18870 gen_helper_shrl_ph(t0, t0, rs_t);
18871 gen_store_gpr(t0, rt);
18872 break;
18873 case NM_REPL_QB:
18874 check_dsp(ctx);
18875 {
18876 int16_t imm;
18877 target_long result;
18878 imm = extract32(ctx->opcode, 13, 8);
18879 result = (uint32_t)imm << 24 |
18880 (uint32_t)imm << 16 |
18881 (uint32_t)imm << 8 |
18882 (uint32_t)imm;
18883 result = (int32_t)result;
18884 tcg_gen_movi_tl(t0, result);
18885 gen_store_gpr(t0, rt);
18886 }
18887 break;
18888 default:
18889 gen_reserved_instruction(ctx);
18890 break;
18891 }
18892 tcg_temp_free(t0);
18893 tcg_temp_free(rs_t);
18894 }
18895
18896
18897 static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
18898 {
18899 int rt = extract32(ctx->opcode, 21, 5);
18900 int rs = extract32(ctx->opcode, 16, 5);
18901 int rd = extract32(ctx->opcode, 11, 5);
18902
18903 switch (extract32(ctx->opcode, 6, 3)) {
18904 case NM_POOL32AXF_1:
18905 {
18906 int32_t op1 = extract32(ctx->opcode, 9, 3);
18907 gen_pool32axf_1_nanomips_insn(ctx, op1, rt, rs, rd);
18908 }
18909 break;
18910 case NM_POOL32AXF_2:
18911 {
18912 int32_t op1 = extract32(ctx->opcode, 12, 2);
18913 gen_pool32axf_2_nanomips_insn(ctx, op1, rt, rs, rd);
18914 }
18915 break;
18916 case NM_POOL32AXF_4:
18917 {
18918 int32_t op1 = extract32(ctx->opcode, 9, 7);
18919 gen_pool32axf_4_nanomips_insn(ctx, op1, rt, rs);
18920 }
18921 break;
18922 case NM_POOL32AXF_5:
18923 switch (extract32(ctx->opcode, 9, 7)) {
18924 #ifndef CONFIG_USER_ONLY
18925 case NM_TLBP:
18926 gen_cp0(env, ctx, OPC_TLBP, 0, 0);
18927 break;
18928 case NM_TLBR:
18929 gen_cp0(env, ctx, OPC_TLBR, 0, 0);
18930 break;
18931 case NM_TLBWI:
18932 gen_cp0(env, ctx, OPC_TLBWI, 0, 0);
18933 break;
18934 case NM_TLBWR:
18935 gen_cp0(env, ctx, OPC_TLBWR, 0, 0);
18936 break;
18937 case NM_TLBINV:
18938 gen_cp0(env, ctx, OPC_TLBINV, 0, 0);
18939 break;
18940 case NM_TLBINVF:
18941 gen_cp0(env, ctx, OPC_TLBINVF, 0, 0);
18942 break;
18943 case NM_DI:
18944 check_cp0_enabled(ctx);
18945 {
18946 TCGv t0 = tcg_temp_new();
18947
18948 save_cpu_state(ctx, 1);
18949 gen_helper_di(t0, cpu_env);
18950 gen_store_gpr(t0, rt);
18951 /* Stop translation as we may have switched the execution mode */
18952 ctx->base.is_jmp = DISAS_STOP;
18953 tcg_temp_free(t0);
18954 }
18955 break;
18956 case NM_EI:
18957 check_cp0_enabled(ctx);
18958 {
18959 TCGv t0 = tcg_temp_new();
18960
18961 save_cpu_state(ctx, 1);
18962 gen_helper_ei(t0, cpu_env);
18963 gen_store_gpr(t0, rt);
18964 /* Stop translation as we may have switched the execution mode */
18965 ctx->base.is_jmp = DISAS_STOP;
18966 tcg_temp_free(t0);
18967 }
18968 break;
18969 case NM_RDPGPR:
18970 gen_load_srsgpr(rs, rt);
18971 break;
18972 case NM_WRPGPR:
18973 gen_store_srsgpr(rs, rt);
18974 break;
18975 case NM_WAIT:
18976 gen_cp0(env, ctx, OPC_WAIT, 0, 0);
18977 break;
18978 case NM_DERET:
18979 gen_cp0(env, ctx, OPC_DERET, 0, 0);
18980 break;
18981 case NM_ERETX:
18982 gen_cp0(env, ctx, OPC_ERET, 0, 0);
18983 break;
18984 #endif
18985 default:
18986 gen_reserved_instruction(ctx);
18987 break;
18988 }
18989 break;
18990 case NM_POOL32AXF_7:
18991 {
18992 int32_t op1 = extract32(ctx->opcode, 9, 3);
18993 gen_pool32axf_7_nanomips_insn(ctx, op1, rt, rs, rd);
18994 }
18995 break;
18996 default:
18997 gen_reserved_instruction(ctx);
18998 break;
18999 }
19000 }
19001
19002 /* Immediate Value Compact Branches */
19003 static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
19004 int rt, int32_t imm, int32_t offset)
19005 {
19006 TCGCond cond = TCG_COND_ALWAYS;
19007 TCGv t0 = tcg_temp_new();
19008 TCGv t1 = tcg_temp_new();
19009
19010 gen_load_gpr(t0, rt);
19011 tcg_gen_movi_tl(t1, imm);
19012 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
19013
19014 /* Load needed operands and calculate btarget */
19015 switch (opc) {
19016 case NM_BEQIC:
19017 if (rt == 0 && imm == 0) {
19018 /* Unconditional branch */
19019 } else if (rt == 0 && imm != 0) {
19020 /* Treat as NOP */
19021 goto out;
19022 } else {
19023 cond = TCG_COND_EQ;
19024 }
19025 break;
19026 case NM_BBEQZC:
19027 case NM_BBNEZC:
19028 check_nms(ctx);
19029 if (imm >= 32 && !(ctx->hflags & MIPS_HFLAG_64)) {
19030 gen_reserved_instruction(ctx);
19031 goto out;
19032 } else if (rt == 0 && opc == NM_BBEQZC) {
19033 /* Unconditional branch */
19034 } else if (rt == 0 && opc == NM_BBNEZC) {
19035 /* Treat as NOP */
19036 goto out;
19037 } else {
19038 tcg_gen_shri_tl(t0, t0, imm);
19039 tcg_gen_andi_tl(t0, t0, 1);
19040 tcg_gen_movi_tl(t1, 0);
19041 if (opc == NM_BBEQZC) {
19042 cond = TCG_COND_EQ;
19043 } else {
19044 cond = TCG_COND_NE;
19045 }
19046 }
19047 break;
19048 case NM_BNEIC:
19049 if (rt == 0 && imm == 0) {
19050 /* Treat as NOP */
19051 goto out;
19052 } else if (rt == 0 && imm != 0) {
19053 /* Unconditional branch */
19054 } else {
19055 cond = TCG_COND_NE;
19056 }
19057 break;
19058 case NM_BGEIC:
19059 if (rt == 0 && imm == 0) {
19060 /* Unconditional branch */
19061 } else {
19062 cond = TCG_COND_GE;
19063 }
19064 break;
19065 case NM_BLTIC:
19066 cond = TCG_COND_LT;
19067 break;
19068 case NM_BGEIUC:
19069 if (rt == 0 && imm == 0) {
19070 /* Unconditional branch */
19071 } else {
19072 cond = TCG_COND_GEU;
19073 }
19074 break;
19075 case NM_BLTIUC:
19076 cond = TCG_COND_LTU;
19077 break;
19078 default:
19079 MIPS_INVAL("Immediate Value Compact branch");
19080 gen_reserved_instruction(ctx);
19081 goto out;
19082 }
19083
19084 /* branch completion */
19085 clear_branch_hflags(ctx);
19086 ctx->base.is_jmp = DISAS_NORETURN;
19087
19088 if (cond == TCG_COND_ALWAYS) {
19089 /* Uncoditional compact branch */
19090 gen_goto_tb(ctx, 0, ctx->btarget);
19091 } else {
19092 /* Conditional compact branch */
19093 TCGLabel *fs = gen_new_label();
19094
19095 tcg_gen_brcond_tl(tcg_invert_cond(cond), t0, t1, fs);
19096
19097 gen_goto_tb(ctx, 1, ctx->btarget);
19098 gen_set_label(fs);
19099
19100 gen_goto_tb(ctx, 0, ctx->base.pc_next + 4);
19101 }
19102
19103 out:
19104 tcg_temp_free(t0);
19105 tcg_temp_free(t1);
19106 }
19107
19108 /* P.BALRSC type nanoMIPS R6 branches: BALRSC and BRSC */
19109 static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs,
19110 int rt)
19111 {
19112 TCGv t0 = tcg_temp_new();
19113 TCGv t1 = tcg_temp_new();
19114
19115 /* load rs */
19116 gen_load_gpr(t0, rs);
19117
19118 /* link */
19119 if (rt != 0) {
19120 tcg_gen_movi_tl(cpu_gpr[rt], ctx->base.pc_next + 4);
19121 }
19122
19123 /* calculate btarget */
19124 tcg_gen_shli_tl(t0, t0, 1);
19125 tcg_gen_movi_tl(t1, ctx->base.pc_next + 4);
19126 gen_op_addr_add(ctx, btarget, t1, t0);
19127
19128 /* branch completion */
19129 clear_branch_hflags(ctx);
19130 ctx->base.is_jmp = DISAS_NORETURN;
19131
19132 /* unconditional branch to register */
19133 tcg_gen_mov_tl(cpu_PC, btarget);
19134 tcg_gen_lookup_and_goto_ptr();
19135
19136 tcg_temp_free(t0);
19137 tcg_temp_free(t1);
19138 }
19139
19140 /* nanoMIPS Branches */
19141 static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
19142 int rs, int rt, int32_t offset)
19143 {
19144 int bcond_compute = 0;
19145 TCGv t0 = tcg_temp_new();
19146 TCGv t1 = tcg_temp_new();
19147
19148 /* Load needed operands and calculate btarget */
19149 switch (opc) {
19150 /* compact branch */
19151 case OPC_BGEC:
19152 case OPC_BLTC:
19153 gen_load_gpr(t0, rs);
19154 gen_load_gpr(t1, rt);
19155 bcond_compute = 1;
19156 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
19157 break;
19158 case OPC_BGEUC:
19159 case OPC_BLTUC:
19160 if (rs == 0 || rs == rt) {
19161 /* OPC_BLEZALC, OPC_BGEZALC */
19162 /* OPC_BGTZALC, OPC_BLTZALC */
19163 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4);
19164 }
19165 gen_load_gpr(t0, rs);
19166 gen_load_gpr(t1, rt);
19167 bcond_compute = 1;
19168 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
19169 break;
19170 case OPC_BC:
19171 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
19172 break;
19173 case OPC_BEQZC:
19174 if (rs != 0) {
19175 /* OPC_BEQZC, OPC_BNEZC */
19176 gen_load_gpr(t0, rs);
19177 bcond_compute = 1;
19178 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
19179 } else {
19180 /* OPC_JIC, OPC_JIALC */
19181 TCGv tbase = tcg_temp_new();
19182 TCGv toffset = tcg_temp_new();
19183
19184 gen_load_gpr(tbase, rt);
19185 tcg_gen_movi_tl(toffset, offset);
19186 gen_op_addr_add(ctx, btarget, tbase, toffset);
19187 tcg_temp_free(tbase);
19188 tcg_temp_free(toffset);
19189 }
19190 break;
19191 default:
19192 MIPS_INVAL("Compact branch/jump");
19193 gen_reserved_instruction(ctx);
19194 goto out;
19195 }
19196
19197 if (bcond_compute == 0) {
19198 /* Uncoditional compact branch */
19199 switch (opc) {
19200 case OPC_BC:
19201 gen_goto_tb(ctx, 0, ctx->btarget);
19202 break;
19203 default:
19204 MIPS_INVAL("Compact branch/jump");
19205 gen_reserved_instruction(ctx);
19206 goto out;
19207 }
19208 } else {
19209 /* Conditional compact branch */
19210 TCGLabel *fs = gen_new_label();
19211
19212 switch (opc) {
19213 case OPC_BGEUC:
19214 if (rs == 0 && rt != 0) {
19215 /* OPC_BLEZALC */
19216 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
19217 } else if (rs != 0 && rt != 0 && rs == rt) {
19218 /* OPC_BGEZALC */
19219 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
19220 } else {
19221 /* OPC_BGEUC */
19222 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs);
19223 }
19224 break;
19225 case OPC_BLTUC:
19226 if (rs == 0 && rt != 0) {
19227 /* OPC_BGTZALC */
19228 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
19229 } else if (rs != 0 && rt != 0 && rs == rt) {
19230 /* OPC_BLTZALC */
19231 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
19232 } else {
19233 /* OPC_BLTUC */
19234 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs);
19235 }
19236 break;
19237 case OPC_BGEC:
19238 if (rs == 0 && rt != 0) {
19239 /* OPC_BLEZC */
19240 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
19241 } else if (rs != 0 && rt != 0 && rs == rt) {
19242 /* OPC_BGEZC */
19243 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
19244 } else {
19245 /* OPC_BGEC */
19246 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs);
19247 }
19248 break;
19249 case OPC_BLTC:
19250 if (rs == 0 && rt != 0) {
19251 /* OPC_BGTZC */
19252 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
19253 } else if (rs != 0 && rt != 0 && rs == rt) {
19254 /* OPC_BLTZC */
19255 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
19256 } else {
19257 /* OPC_BLTC */
19258 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs);
19259 }
19260 break;
19261 case OPC_BEQZC:
19262 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t0, 0, fs);
19263 break;
19264 default:
19265 MIPS_INVAL("Compact conditional branch/jump");
19266 gen_reserved_instruction(ctx);
19267 goto out;
19268 }
19269
19270 /* branch completion */
19271 clear_branch_hflags(ctx);
19272 ctx->base.is_jmp = DISAS_NORETURN;
19273
19274 /* Generating branch here as compact branches don't have delay slot */
19275 gen_goto_tb(ctx, 1, ctx->btarget);
19276 gen_set_label(fs);
19277
19278 gen_goto_tb(ctx, 0, ctx->base.pc_next + 4);
19279 }
19280
19281 out:
19282 tcg_temp_free(t0);
19283 tcg_temp_free(t1);
19284 }
19285
19286
19287 /* nanoMIPS CP1 Branches */
19288 static void gen_compute_branch_cp1_nm(DisasContext *ctx, uint32_t op,
19289 int32_t ft, int32_t offset)
19290 {
19291 target_ulong btarget;
19292 TCGv_i64 t0 = tcg_temp_new_i64();
19293
19294 gen_load_fpr64(ctx, t0, ft);
19295 tcg_gen_andi_i64(t0, t0, 1);
19296
19297 btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
19298
19299 switch (op) {
19300 case NM_BC1EQZC:
19301 tcg_gen_xori_i64(t0, t0, 1);
19302 ctx->hflags |= MIPS_HFLAG_BC;
19303 break;
19304 case NM_BC1NEZC:
19305 /* t0 already set */
19306 ctx->hflags |= MIPS_HFLAG_BC;
19307 break;
19308 default:
19309 MIPS_INVAL("cp1 cond branch");
19310 gen_reserved_instruction(ctx);
19311 goto out;
19312 }
19313
19314 tcg_gen_trunc_i64_tl(bcond, t0);
19315
19316 ctx->btarget = btarget;
19317
19318 out:
19319 tcg_temp_free_i64(t0);
19320 }
19321
19322
19323 static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
19324 {
19325 TCGv t0, t1;
19326 t0 = tcg_temp_new();
19327 t1 = tcg_temp_new();
19328
19329 gen_load_gpr(t0, rs);
19330 gen_load_gpr(t1, rt);
19331
19332 if ((extract32(ctx->opcode, 6, 1)) == 1) {
19333 /* PP.LSXS instructions require shifting */
19334 switch (extract32(ctx->opcode, 7, 4)) {
19335 case NM_SHXS:
19336 check_nms(ctx);
19337 /* fall through */
19338 case NM_LHXS:
19339 case NM_LHUXS:
19340 tcg_gen_shli_tl(t0, t0, 1);
19341 break;
19342 case NM_SWXS:
19343 check_nms(ctx);
19344 /* fall through */
19345 case NM_LWXS:
19346 case NM_LWC1XS:
19347 case NM_SWC1XS:
19348 tcg_gen_shli_tl(t0, t0, 2);
19349 break;
19350 case NM_LDC1XS:
19351 case NM_SDC1XS:
19352 tcg_gen_shli_tl(t0, t0, 3);
19353 break;
19354 }
19355 }
19356 gen_op_addr_add(ctx, t0, t0, t1);
19357
19358 switch (extract32(ctx->opcode, 7, 4)) {
19359 case NM_LBX:
19360 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
19361 MO_SB);
19362 gen_store_gpr(t0, rd);
19363 break;
19364 case NM_LHX:
19365 /*case NM_LHXS:*/
19366 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
19367 MO_TESW);
19368 gen_store_gpr(t0, rd);
19369 break;
19370 case NM_LWX:
19371 /*case NM_LWXS:*/
19372 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
19373 MO_TESL);
19374 gen_store_gpr(t0, rd);
19375 break;
19376 case NM_LBUX:
19377 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
19378 MO_UB);
19379 gen_store_gpr(t0, rd);
19380 break;
19381 case NM_LHUX:
19382 /*case NM_LHUXS:*/
19383 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
19384 MO_TEUW);
19385 gen_store_gpr(t0, rd);
19386 break;
19387 case NM_SBX:
19388 check_nms(ctx);
19389 gen_load_gpr(t1, rd);
19390 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
19391 MO_8);
19392 break;
19393 case NM_SHX:
19394 /*case NM_SHXS:*/
19395 check_nms(ctx);
19396 gen_load_gpr(t1, rd);
19397 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
19398 MO_TEUW);
19399 break;
19400 case NM_SWX:
19401 /*case NM_SWXS:*/
19402 check_nms(ctx);
19403 gen_load_gpr(t1, rd);
19404 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
19405 MO_TEUL);
19406 break;
19407 case NM_LWC1X:
19408 /*case NM_LWC1XS:*/
19409 case NM_LDC1X:
19410 /*case NM_LDC1XS:*/
19411 case NM_SWC1X:
19412 /*case NM_SWC1XS:*/
19413 case NM_SDC1X:
19414 /*case NM_SDC1XS:*/
19415 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
19416 check_cp1_enabled(ctx);
19417 switch (extract32(ctx->opcode, 7, 4)) {
19418 case NM_LWC1X:
19419 /*case NM_LWC1XS:*/
19420 gen_flt_ldst(ctx, OPC_LWC1, rd, t0);
19421 break;
19422 case NM_LDC1X:
19423 /*case NM_LDC1XS:*/
19424 gen_flt_ldst(ctx, OPC_LDC1, rd, t0);
19425 break;
19426 case NM_SWC1X:
19427 /*case NM_SWC1XS:*/
19428 gen_flt_ldst(ctx, OPC_SWC1, rd, t0);
19429 break;
19430 case NM_SDC1X:
19431 /*case NM_SDC1XS:*/
19432 gen_flt_ldst(ctx, OPC_SDC1, rd, t0);
19433 break;
19434 }
19435 } else {
19436 generate_exception_err(ctx, EXCP_CpU, 1);
19437 }
19438 break;
19439 default:
19440 gen_reserved_instruction(ctx);
19441 break;
19442 }
19443
19444 tcg_temp_free(t0);
19445 tcg_temp_free(t1);
19446 }
19447
19448 static void gen_pool32f_nanomips_insn(DisasContext *ctx)
19449 {
19450 int rt, rs, rd;
19451
19452 rt = extract32(ctx->opcode, 21, 5);
19453 rs = extract32(ctx->opcode, 16, 5);
19454 rd = extract32(ctx->opcode, 11, 5);
19455
19456 if (!(ctx->CP0_Config1 & (1 << CP0C1_FP))) {
19457 gen_reserved_instruction(ctx);
19458 return;
19459 }
19460 check_cp1_enabled(ctx);
19461 switch (extract32(ctx->opcode, 0, 3)) {
19462 case NM_POOL32F_0:
19463 switch (extract32(ctx->opcode, 3, 7)) {
19464 case NM_RINT_S:
19465 gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0);
19466 break;
19467 case NM_RINT_D:
19468 gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0);
19469 break;
19470 case NM_CLASS_S:
19471 gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0);
19472 break;
19473 case NM_CLASS_D:
19474 gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0);
19475 break;
19476 case NM_ADD_S:
19477 gen_farith(ctx, OPC_ADD_S, rt, rs, rd, 0);
19478 break;
19479 case NM_ADD_D:
19480 gen_farith(ctx, OPC_ADD_D, rt, rs, rd, 0);
19481 break;
19482 case NM_SUB_S:
19483 gen_farith(ctx, OPC_SUB_S, rt, rs, rd, 0);
19484 break;
19485 case NM_SUB_D:
19486 gen_farith(ctx, OPC_SUB_D, rt, rs, rd, 0);
19487 break;
19488 case NM_MUL_S:
19489 gen_farith(ctx, OPC_MUL_S, rt, rs, rd, 0);
19490 break;
19491 case NM_MUL_D:
19492 gen_farith(ctx, OPC_MUL_D, rt, rs, rd, 0);
19493 break;
19494 case NM_DIV_S:
19495 gen_farith(ctx, OPC_DIV_S, rt, rs, rd, 0);
19496 break;
19497 case NM_DIV_D:
19498 gen_farith(ctx, OPC_DIV_D, rt, rs, rd, 0);
19499 break;
19500 case NM_SELEQZ_S:
19501 gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
19502 break;
19503 case NM_SELEQZ_D:
19504 gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
19505 break;
19506 case NM_SELNEZ_S:
19507 gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
19508 break;
19509 case NM_SELNEZ_D:
19510 gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
19511 break;
19512 case NM_SEL_S:
19513 gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs);
19514 break;
19515 case NM_SEL_D:
19516 gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs);
19517 break;
19518 case NM_MADDF_S:
19519 gen_farith(ctx, OPC_MADDF_S, rt, rs, rd, 0);
19520 break;
19521 case NM_MADDF_D:
19522 gen_farith(ctx, OPC_MADDF_D, rt, rs, rd, 0);
19523 break;
19524 case NM_MSUBF_S:
19525 gen_farith(ctx, OPC_MSUBF_S, rt, rs, rd, 0);
19526 break;
19527 case NM_MSUBF_D:
19528 gen_farith(ctx, OPC_MSUBF_D, rt, rs, rd, 0);
19529 break;
19530 default:
19531 gen_reserved_instruction(ctx);
19532 break;
19533 }
19534 break;
19535 case NM_POOL32F_3:
19536 switch (extract32(ctx->opcode, 3, 3)) {
19537 case NM_MIN_FMT:
19538 switch (extract32(ctx->opcode, 9, 1)) {
19539 case FMT_SDPS_S:
19540 gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0);
19541 break;
19542 case FMT_SDPS_D:
19543 gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0);
19544 break;
19545 }
19546 break;
19547 case NM_MAX_FMT:
19548 switch (extract32(ctx->opcode, 9, 1)) {
19549 case FMT_SDPS_S:
19550 gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0);
19551 break;
19552 case FMT_SDPS_D:
19553 gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0);
19554 break;
19555 }
19556 break;
19557 case NM_MINA_FMT:
19558 switch (extract32(ctx->opcode, 9, 1)) {
19559 case FMT_SDPS_S:
19560 gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0);
19561 break;
19562 case FMT_SDPS_D:
19563 gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0);
19564 break;
19565 }
19566 break;
19567 case NM_MAXA_FMT:
19568 switch (extract32(ctx->opcode, 9, 1)) {
19569 case FMT_SDPS_S:
19570 gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0);
19571 break;
19572 case FMT_SDPS_D:
19573 gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0);
19574 break;
19575 }
19576 break;
19577 case NM_POOL32FXF:
19578 switch (extract32(ctx->opcode, 6, 8)) {
19579 case NM_CFC1:
19580 gen_cp1(ctx, OPC_CFC1, rt, rs);
19581 break;
19582 case NM_CTC1:
19583 gen_cp1(ctx, OPC_CTC1, rt, rs);
19584 break;
19585 case NM_MFC1:
19586 gen_cp1(ctx, OPC_MFC1, rt, rs);
19587 break;
19588 case NM_MTC1:
19589 gen_cp1(ctx, OPC_MTC1, rt, rs);
19590 break;
19591 case NM_MFHC1:
19592 gen_cp1(ctx, OPC_MFHC1, rt, rs);
19593 break;
19594 case NM_MTHC1:
19595 gen_cp1(ctx, OPC_MTHC1, rt, rs);
19596 break;
19597 case NM_CVT_S_PL:
19598 gen_farith(ctx, OPC_CVT_S_PL, -1, rs, rt, 0);
19599 break;
19600 case NM_CVT_S_PU:
19601 gen_farith(ctx, OPC_CVT_S_PU, -1, rs, rt, 0);
19602 break;
19603 default:
19604 switch (extract32(ctx->opcode, 6, 9)) {
19605 case NM_CVT_L_S:
19606 gen_farith(ctx, OPC_CVT_L_S, -1, rs, rt, 0);
19607 break;
19608 case NM_CVT_L_D:
19609 gen_farith(ctx, OPC_CVT_L_D, -1, rs, rt, 0);
19610 break;
19611 case NM_CVT_W_S:
19612 gen_farith(ctx, OPC_CVT_W_S, -1, rs, rt, 0);
19613 break;
19614 case NM_CVT_W_D:
19615 gen_farith(ctx, OPC_CVT_W_D, -1, rs, rt, 0);
19616 break;
19617 case NM_RSQRT_S:
19618 gen_farith(ctx, OPC_RSQRT_S, -1, rs, rt, 0);
19619 break;
19620 case NM_RSQRT_D:
19621 gen_farith(ctx, OPC_RSQRT_D, -1, rs, rt, 0);
19622 break;
19623 case NM_SQRT_S:
19624 gen_farith(ctx, OPC_SQRT_S, -1, rs, rt, 0);
19625 break;
19626 case NM_SQRT_D:
19627 gen_farith(ctx, OPC_SQRT_D, -1, rs, rt, 0);
19628 break;
19629 case NM_RECIP_S:
19630 gen_farith(ctx, OPC_RECIP_S, -1, rs, rt, 0);
19631 break;
19632 case NM_RECIP_D:
19633 gen_farith(ctx, OPC_RECIP_D, -1, rs, rt, 0);
19634 break;
19635 case NM_FLOOR_L_S:
19636 gen_farith(ctx, OPC_FLOOR_L_S, -1, rs, rt, 0);
19637 break;
19638 case NM_FLOOR_L_D:
19639 gen_farith(ctx, OPC_FLOOR_L_D, -1, rs, rt, 0);
19640 break;
19641 case NM_FLOOR_W_S:
19642 gen_farith(ctx, OPC_FLOOR_W_S, -1, rs, rt, 0);
19643 break;
19644 case NM_FLOOR_W_D:
19645 gen_farith(ctx, OPC_FLOOR_W_D, -1, rs, rt, 0);
19646 break;
19647 case NM_CEIL_L_S:
19648 gen_farith(ctx, OPC_CEIL_L_S, -1, rs, rt, 0);
19649 break;
19650 case NM_CEIL_L_D:
19651 gen_farith(ctx, OPC_CEIL_L_D, -1, rs, rt, 0);
19652 break;
19653 case NM_CEIL_W_S:
19654 gen_farith(ctx, OPC_CEIL_W_S, -1, rs, rt, 0);
19655 break;
19656 case NM_CEIL_W_D:
19657 gen_farith(ctx, OPC_CEIL_W_D, -1, rs, rt, 0);
19658 break;
19659 case NM_TRUNC_L_S:
19660 gen_farith(ctx, OPC_TRUNC_L_S, -1, rs, rt, 0);
19661 break;
19662 case NM_TRUNC_L_D:
19663 gen_farith(ctx, OPC_TRUNC_L_D, -1, rs, rt, 0);
19664 break;
19665 case NM_TRUNC_W_S:
19666 gen_farith(ctx, OPC_TRUNC_W_S, -1, rs, rt, 0);
19667 break;
19668 case NM_TRUNC_W_D:
19669 gen_farith(ctx, OPC_TRUNC_W_D, -1, rs, rt, 0);
19670 break;
19671 case NM_ROUND_L_S:
19672 gen_farith(ctx, OPC_ROUND_L_S, -1, rs, rt, 0);
19673 break;
19674 case NM_ROUND_L_D:
19675 gen_farith(ctx, OPC_ROUND_L_D, -1, rs, rt, 0);
19676 break;
19677 case NM_ROUND_W_S:
19678 gen_farith(ctx, OPC_ROUND_W_S, -1, rs, rt, 0);
19679 break;
19680 case NM_ROUND_W_D:
19681 gen_farith(ctx, OPC_ROUND_W_D, -1, rs, rt, 0);
19682 break;
19683 case NM_MOV_S:
19684 gen_farith(ctx, OPC_MOV_S, -1, rs, rt, 0);
19685 break;
19686 case NM_MOV_D:
19687 gen_farith(ctx, OPC_MOV_D, -1, rs, rt, 0);
19688 break;
19689 case NM_ABS_S:
19690 gen_farith(ctx, OPC_ABS_S, -1, rs, rt, 0);
19691 break;
19692 case NM_ABS_D:
19693 gen_farith(ctx, OPC_ABS_D, -1, rs, rt, 0);
19694 break;
19695 case NM_NEG_S:
19696 gen_farith(ctx, OPC_NEG_S, -1, rs, rt, 0);
19697 break;
19698 case NM_NEG_D:
19699 gen_farith(ctx, OPC_NEG_D, -1, rs, rt, 0);
19700 break;
19701 case NM_CVT_D_S:
19702 gen_farith(ctx, OPC_CVT_D_S, -1, rs, rt, 0);
19703 break;
19704 case NM_CVT_D_W:
19705 gen_farith(ctx, OPC_CVT_D_W, -1, rs, rt, 0);
19706 break;
19707 case NM_CVT_D_L:
19708 gen_farith(ctx, OPC_CVT_D_L, -1, rs, rt, 0);
19709 break;
19710 case NM_CVT_S_D:
19711 gen_farith(ctx, OPC_CVT_S_D, -1, rs, rt, 0);
19712 break;
19713 case NM_CVT_S_W:
19714 gen_farith(ctx, OPC_CVT_S_W, -1, rs, rt, 0);
19715 break;
19716 case NM_CVT_S_L:
19717 gen_farith(ctx, OPC_CVT_S_L, -1, rs, rt, 0);
19718 break;
19719 default:
19720 gen_reserved_instruction(ctx);
19721 break;
19722 }
19723 break;
19724 }
19725 break;
19726 }
19727 break;
19728 case NM_POOL32F_5:
19729 switch (extract32(ctx->opcode, 3, 3)) {
19730 case NM_CMP_CONDN_S:
19731 gen_r6_cmp_s(ctx, extract32(ctx->opcode, 6, 5), rt, rs, rd);
19732 break;
19733 case NM_CMP_CONDN_D:
19734 gen_r6_cmp_d(ctx, extract32(ctx->opcode, 6, 5), rt, rs, rd);
19735 break;
19736 default:
19737 gen_reserved_instruction(ctx);
19738 break;
19739 }
19740 break;
19741 default:
19742 gen_reserved_instruction(ctx);
19743 break;
19744 }
19745 }
19746
19747 static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
19748 int rd, int rs, int rt)
19749 {
19750 int ret = rd;
19751 TCGv t0 = tcg_temp_new();
19752 TCGv v1_t = tcg_temp_new();
19753 TCGv v2_t = tcg_temp_new();
19754
19755 gen_load_gpr(v1_t, rs);
19756 gen_load_gpr(v2_t, rt);
19757
19758 switch (opc) {
19759 case NM_CMP_EQ_PH:
19760 check_dsp(ctx);
19761 gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env);
19762 break;
19763 case NM_CMP_LT_PH:
19764 check_dsp(ctx);
19765 gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env);
19766 break;
19767 case NM_CMP_LE_PH:
19768 check_dsp(ctx);
19769 gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env);
19770 break;
19771 case NM_CMPU_EQ_QB:
19772 check_dsp(ctx);
19773 gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env);
19774 break;
19775 case NM_CMPU_LT_QB:
19776 check_dsp(ctx);
19777 gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env);
19778 break;
19779 case NM_CMPU_LE_QB:
19780 check_dsp(ctx);
19781 gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env);
19782 break;
19783 case NM_CMPGU_EQ_QB:
19784 check_dsp(ctx);
19785 gen_helper_cmpgu_eq_qb(v1_t, v1_t, v2_t);
19786 gen_store_gpr(v1_t, ret);
19787 break;
19788 case NM_CMPGU_LT_QB:
19789 check_dsp(ctx);
19790 gen_helper_cmpgu_lt_qb(v1_t, v1_t, v2_t);
19791 gen_store_gpr(v1_t, ret);
19792 break;
19793 case NM_CMPGU_LE_QB:
19794 check_dsp(ctx);
19795 gen_helper_cmpgu_le_qb(v1_t, v1_t, v2_t);
19796 gen_store_gpr(v1_t, ret);
19797 break;
19798 case NM_CMPGDU_EQ_QB:
19799 check_dsp_r2(ctx);
19800 gen_helper_cmpgu_eq_qb(v1_t, v1_t, v2_t);
19801 tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4);
19802 gen_store_gpr(v1_t, ret);
19803 break;
19804 case NM_CMPGDU_LT_QB:
19805 check_dsp_r2(ctx);
19806 gen_helper_cmpgu_lt_qb(v1_t, v1_t, v2_t);
19807 tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4);
19808 gen_store_gpr(v1_t, ret);
19809 break;
19810 case NM_CMPGDU_LE_QB:
19811 check_dsp_r2(ctx);
19812 gen_helper_cmpgu_le_qb(v1_t, v1_t, v2_t);
19813 tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4);
19814 gen_store_gpr(v1_t, ret);
19815 break;
19816 case NM_PACKRL_PH:
19817 check_dsp(ctx);
19818 gen_helper_packrl_ph(v1_t, v1_t, v2_t);
19819 gen_store_gpr(v1_t, ret);
19820 break;
19821 case NM_PICK_QB:
19822 check_dsp(ctx);
19823 gen_helper_pick_qb(v1_t, v1_t, v2_t, cpu_env);
19824 gen_store_gpr(v1_t, ret);
19825 break;
19826 case NM_PICK_PH:
19827 check_dsp(ctx);
19828 gen_helper_pick_ph(v1_t, v1_t, v2_t, cpu_env);
19829 gen_store_gpr(v1_t, ret);
19830 break;
19831 case NM_ADDQ_S_W:
19832 check_dsp(ctx);
19833 gen_helper_addq_s_w(v1_t, v1_t, v2_t, cpu_env);
19834 gen_store_gpr(v1_t, ret);
19835 break;
19836 case NM_SUBQ_S_W:
19837 check_dsp(ctx);
19838 gen_helper_subq_s_w(v1_t, v1_t, v2_t, cpu_env);
19839 gen_store_gpr(v1_t, ret);
19840 break;
19841 case NM_ADDSC:
19842 check_dsp(ctx);
19843 gen_helper_addsc(v1_t, v1_t, v2_t, cpu_env);
19844 gen_store_gpr(v1_t, ret);
19845 break;
19846 case NM_ADDWC:
19847 check_dsp(ctx);
19848 gen_helper_addwc(v1_t, v1_t, v2_t, cpu_env);
19849 gen_store_gpr(v1_t, ret);
19850 break;
19851 case NM_ADDQ_S_PH:
19852 check_dsp(ctx);
19853 switch (extract32(ctx->opcode, 10, 1)) {
19854 case 0:
19855 /* ADDQ_PH */
19856 gen_helper_addq_ph(v1_t, v1_t, v2_t, cpu_env);
19857 gen_store_gpr(v1_t, ret);
19858 break;
19859 case 1:
19860 /* ADDQ_S_PH */
19861 gen_helper_addq_s_ph(v1_t, v1_t, v2_t, cpu_env);
19862 gen_store_gpr(v1_t, ret);
19863 break;
19864 }
19865 break;
19866 case NM_ADDQH_R_PH:
19867 check_dsp_r2(ctx);
19868 switch (extract32(ctx->opcode, 10, 1)) {
19869 case 0:
19870 /* ADDQH_PH */
19871 gen_helper_addqh_ph(v1_t, v1_t, v2_t);
19872 gen_store_gpr(v1_t, ret);
19873 break;
19874 case 1:
19875 /* ADDQH_R_PH */
19876 gen_helper_addqh_r_ph(v1_t, v1_t, v2_t);
19877 gen_store_gpr(v1_t, ret);
19878 break;
19879 }
19880 break;
19881 case NM_ADDQH_R_W:
19882 check_dsp_r2(ctx);
19883 switch (extract32(ctx->opcode, 10, 1)) {
19884 case 0:
19885 /* ADDQH_W */
19886 gen_helper_addqh_w(v1_t, v1_t, v2_t);
19887 gen_store_gpr(v1_t, ret);
19888 break;
19889 case 1:
19890 /* ADDQH_R_W */
19891 gen_helper_addqh_r_w(v1_t, v1_t, v2_t);
19892 gen_store_gpr(v1_t, ret);
19893 break;
19894 }
19895 break;
19896 case NM_ADDU_S_QB:
19897 check_dsp(ctx);
19898 switch (extract32(ctx->opcode, 10, 1)) {
19899 case 0:
19900 /* ADDU_QB */
19901 gen_helper_addu_qb(v1_t, v1_t, v2_t, cpu_env);
19902 gen_store_gpr(v1_t, ret);
19903 break;
19904 case 1:
19905 /* ADDU_S_QB */
19906 gen_helper_addu_s_qb(v1_t, v1_t, v2_t, cpu_env);
19907 gen_store_gpr(v1_t, ret);
19908 break;
19909 }
19910 break;
19911 case NM_ADDU_S_PH:
19912 check_dsp_r2(ctx);
19913 switch (extract32(ctx->opcode, 10, 1)) {
19914 case 0:
19915 /* ADDU_PH */
19916 gen_helper_addu_ph(v1_t, v1_t, v2_t, cpu_env);
19917 gen_store_gpr(v1_t, ret);
19918 break;
19919 case 1:
19920 /* ADDU_S_PH */
19921 gen_helper_addu_s_ph(v1_t, v1_t, v2_t, cpu_env);
19922 gen_store_gpr(v1_t, ret);
19923 break;
19924 }
19925 break;
19926 case NM_ADDUH_R_QB:
19927 check_dsp_r2(ctx);
19928 switch (extract32(ctx->opcode, 10, 1)) {
19929 case 0:
19930 /* ADDUH_QB */
19931 gen_helper_adduh_qb(v1_t, v1_t, v2_t);
19932 gen_store_gpr(v1_t, ret);
19933 break;
19934 case 1:
19935 /* ADDUH_R_QB */
19936 gen_helper_adduh_r_qb(v1_t, v1_t, v2_t);
19937 gen_store_gpr(v1_t, ret);
19938 break;
19939 }
19940 break;
19941 case NM_SHRAV_R_PH:
19942 check_dsp(ctx);
19943 switch (extract32(ctx->opcode, 10, 1)) {
19944 case 0:
19945 /* SHRAV_PH */
19946 gen_helper_shra_ph(v1_t, v1_t, v2_t);
19947 gen_store_gpr(v1_t, ret);
19948 break;
19949 case 1:
19950 /* SHRAV_R_PH */
19951 gen_helper_shra_r_ph(v1_t, v1_t, v2_t);
19952 gen_store_gpr(v1_t, ret);
19953 break;
19954 }
19955 break;
19956 case NM_SHRAV_R_QB:
19957 check_dsp_r2(ctx);
19958 switch (extract32(ctx->opcode, 10, 1)) {
19959 case 0:
19960 /* SHRAV_QB */
19961 gen_helper_shra_qb(v1_t, v1_t, v2_t);
19962 gen_store_gpr(v1_t, ret);
19963 break;
19964 case 1:
19965 /* SHRAV_R_QB */
19966 gen_helper_shra_r_qb(v1_t, v1_t, v2_t);
19967 gen_store_gpr(v1_t, ret);
19968 break;
19969 }
19970 break;
19971 case NM_SUBQ_S_PH:
19972 check_dsp(ctx);
19973 switch (extract32(ctx->opcode, 10, 1)) {
19974 case 0:
19975 /* SUBQ_PH */
19976 gen_helper_subq_ph(v1_t, v1_t, v2_t, cpu_env);
19977 gen_store_gpr(v1_t, ret);
19978 break;
19979 case 1:
19980 /* SUBQ_S_PH */
19981 gen_helper_subq_s_ph(v1_t, v1_t, v2_t, cpu_env);
19982 gen_store_gpr(v1_t, ret);
19983 break;
19984 }
19985 break;
19986 case NM_SUBQH_R_PH:
19987 check_dsp_r2(ctx);
19988 switch (extract32(ctx->opcode, 10, 1)) {
19989 case 0:
19990 /* SUBQH_PH */
19991 gen_helper_subqh_ph(v1_t, v1_t, v2_t);
19992 gen_store_gpr(v1_t, ret);
19993 break;
19994 case 1:
19995 /* SUBQH_R_PH */
19996 gen_helper_subqh_r_ph(v1_t, v1_t, v2_t);
19997 gen_store_gpr(v1_t, ret);
19998 break;
19999 }
20000 break;
20001 case NM_SUBQH_R_W:
20002 check_dsp_r2(ctx);
20003 switch (extract32(ctx->opcode, 10, 1)) {
20004 case 0:
20005 /* SUBQH_W */
20006 gen_helper_subqh_w(v1_t, v1_t, v2_t);
20007 gen_store_gpr(v1_t, ret);
20008 break;
20009 case 1:
20010 /* SUBQH_R_W */
20011 gen_helper_subqh_r_w(v1_t, v1_t, v2_t);
20012 gen_store_gpr(v1_t, ret);
20013 break;
20014 }
20015 break;
20016 case NM_SUBU_S_QB:
20017 check_dsp(ctx);
20018 switch (extract32(ctx->opcode, 10, 1)) {
20019 case 0:
20020 /* SUBU_QB */
20021 gen_helper_subu_qb(v1_t, v1_t, v2_t, cpu_env);
20022 gen_store_gpr(v1_t, ret);
20023 break;
20024 case 1:
20025 /* SUBU_S_QB */
20026 gen_helper_subu_s_qb(v1_t, v1_t, v2_t, cpu_env);
20027 gen_store_gpr(v1_t, ret);
20028 break;
20029 }
20030 break;
20031 case NM_SUBU_S_PH:
20032 check_dsp_r2(ctx);
20033 switch (extract32(ctx->opcode, 10, 1)) {
20034 case 0:
20035 /* SUBU_PH */
20036 gen_helper_subu_ph(v1_t, v1_t, v2_t, cpu_env);
20037 gen_store_gpr(v1_t, ret);
20038 break;
20039 case 1:
20040 /* SUBU_S_PH */
20041 gen_helper_subu_s_ph(v1_t, v1_t, v2_t, cpu_env);
20042 gen_store_gpr(v1_t, ret);
20043 break;
20044 }
20045 break;
20046 case NM_SUBUH_R_QB:
20047 check_dsp_r2(ctx);
20048 switch (extract32(ctx->opcode, 10, 1)) {
20049 case 0:
20050 /* SUBUH_QB */
20051 gen_helper_subuh_qb(v1_t, v1_t, v2_t);
20052 gen_store_gpr(v1_t, ret);
20053 break;
20054 case 1:
20055 /* SUBUH_R_QB */
20056 gen_helper_subuh_r_qb(v1_t, v1_t, v2_t);
20057 gen_store_gpr(v1_t, ret);
20058 break;
20059 }
20060 break;
20061 case NM_SHLLV_S_PH:
20062 check_dsp(ctx);
20063 switch (extract32(ctx->opcode, 10, 1)) {
20064 case 0:
20065 /* SHLLV_PH */
20066 gen_helper_shll_ph(v1_t, v1_t, v2_t, cpu_env);
20067 gen_store_gpr(v1_t, ret);
20068 break;
20069 case 1:
20070 /* SHLLV_S_PH */
20071 gen_helper_shll_s_ph(v1_t, v1_t, v2_t, cpu_env);
20072 gen_store_gpr(v1_t, ret);
20073 break;
20074 }
20075 break;
20076 case NM_PRECR_SRA_R_PH_W:
20077 check_dsp_r2(ctx);
20078 switch (extract32(ctx->opcode, 10, 1)) {
20079 case 0:
20080 /* PRECR_SRA_PH_W */
20081 {
20082 TCGv_i32 sa_t = tcg_const_i32(rd);
20083 gen_helper_precr_sra_ph_w(v1_t, sa_t, v1_t,
20084 cpu_gpr[rt]);
20085 gen_store_gpr(v1_t, rt);
20086 tcg_temp_free_i32(sa_t);
20087 }
20088 break;
20089 case 1:
20090 /* PRECR_SRA_R_PH_W */
20091 {
20092 TCGv_i32 sa_t = tcg_const_i32(rd);
20093 gen_helper_precr_sra_r_ph_w(v1_t, sa_t, v1_t,
20094 cpu_gpr[rt]);
20095 gen_store_gpr(v1_t, rt);
20096 tcg_temp_free_i32(sa_t);
20097 }
20098 break;
20099 }
20100 break;
20101 case NM_MULEU_S_PH_QBL:
20102 check_dsp(ctx);
20103 gen_helper_muleu_s_ph_qbl(v1_t, v1_t, v2_t, cpu_env);
20104 gen_store_gpr(v1_t, ret);
20105 break;
20106 case NM_MULEU_S_PH_QBR:
20107 check_dsp(ctx);
20108 gen_helper_muleu_s_ph_qbr(v1_t, v1_t, v2_t, cpu_env);
20109 gen_store_gpr(v1_t, ret);
20110 break;
20111 case NM_MULQ_RS_PH:
20112 check_dsp(ctx);
20113 gen_helper_mulq_rs_ph(v1_t, v1_t, v2_t, cpu_env);
20114 gen_store_gpr(v1_t, ret);
20115 break;
20116 case NM_MULQ_S_PH:
20117 check_dsp_r2(ctx);
20118 gen_helper_mulq_s_ph(v1_t, v1_t, v2_t, cpu_env);
20119 gen_store_gpr(v1_t, ret);
20120 break;
20121 case NM_MULQ_RS_W:
20122 check_dsp_r2(ctx);
20123 gen_helper_mulq_rs_w(v1_t, v1_t, v2_t, cpu_env);
20124 gen_store_gpr(v1_t, ret);
20125 break;
20126 case NM_MULQ_S_W:
20127 check_dsp_r2(ctx);
20128 gen_helper_mulq_s_w(v1_t, v1_t, v2_t, cpu_env);
20129 gen_store_gpr(v1_t, ret);
20130 break;
20131 case NM_APPEND:
20132 check_dsp_r2(ctx);
20133 gen_load_gpr(t0, rs);
20134 if (rd != 0) {
20135 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], rd, 32 - rd);
20136 }
20137 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
20138 break;
20139 case NM_MODSUB:
20140 check_dsp(ctx);
20141 gen_helper_modsub(v1_t, v1_t, v2_t);
20142 gen_store_gpr(v1_t, ret);
20143 break;
20144 case NM_SHRAV_R_W:
20145 check_dsp(ctx);
20146 gen_helper_shra_r_w(v1_t, v1_t, v2_t);
20147 gen_store_gpr(v1_t, ret);
20148 break;
20149 case NM_SHRLV_PH:
20150 check_dsp_r2(ctx);
20151 gen_helper_shrl_ph(v1_t, v1_t, v2_t);
20152 gen_store_gpr(v1_t, ret);
20153 break;
20154 case NM_SHRLV_QB:
20155 check_dsp(ctx);
20156 gen_helper_shrl_qb(v1_t, v1_t, v2_t);
20157 gen_store_gpr(v1_t, ret);
20158 break;
20159 case NM_SHLLV_QB:
20160 check_dsp(ctx);
20161 gen_helper_shll_qb(v1_t, v1_t, v2_t, cpu_env);
20162 gen_store_gpr(v1_t, ret);
20163 break;
20164 case NM_SHLLV_S_W:
20165 check_dsp(ctx);
20166 gen_helper_shll_s_w(v1_t, v1_t, v2_t, cpu_env);
20167 gen_store_gpr(v1_t, ret);
20168 break;
20169 case NM_SHILO:
20170 check_dsp(ctx);
20171 {
20172 TCGv tv0 = tcg_temp_new();
20173 TCGv tv1 = tcg_temp_new();
20174 int16_t imm = extract32(ctx->opcode, 16, 7);
20175
20176 tcg_gen_movi_tl(tv0, rd >> 3);
20177 tcg_gen_movi_tl(tv1, imm);
20178 gen_helper_shilo(tv0, tv1, cpu_env);
20179 }
20180 break;
20181 case NM_MULEQ_S_W_PHL:
20182 check_dsp(ctx);
20183 gen_helper_muleq_s_w_phl(v1_t, v1_t, v2_t, cpu_env);
20184 gen_store_gpr(v1_t, ret);
20185 break;
20186 case NM_MULEQ_S_W_PHR:
20187 check_dsp(ctx);
20188 gen_helper_muleq_s_w_phr(v1_t, v1_t, v2_t, cpu_env);
20189 gen_store_gpr(v1_t, ret);
20190 break;
20191 case NM_MUL_S_PH:
20192 check_dsp_r2(ctx);
20193 switch (extract32(ctx->opcode, 10, 1)) {
20194 case 0:
20195 /* MUL_PH */
20196 gen_helper_mul_ph(v1_t, v1_t, v2_t, cpu_env);
20197 gen_store_gpr(v1_t, ret);
20198 break;
20199 case 1:
20200 /* MUL_S_PH */
20201 gen_helper_mul_s_ph(v1_t, v1_t, v2_t, cpu_env);
20202 gen_store_gpr(v1_t, ret);
20203 break;
20204 }
20205 break;
20206 case NM_PRECR_QB_PH:
20207 check_dsp_r2(ctx);
20208 gen_helper_precr_qb_ph(v1_t, v1_t, v2_t);
20209 gen_store_gpr(v1_t, ret);
20210 break;
20211 case NM_PRECRQ_QB_PH:
20212 check_dsp(ctx);
20213 gen_helper_precrq_qb_ph(v1_t, v1_t, v2_t);
20214 gen_store_gpr(v1_t, ret);
20215 break;
20216 case NM_PRECRQ_PH_W:
20217 check_dsp(ctx);
20218 gen_helper_precrq_ph_w(v1_t, v1_t, v2_t);
20219 gen_store_gpr(v1_t, ret);
20220 break;
20221 case NM_PRECRQ_RS_PH_W:
20222 check_dsp(ctx);
20223 gen_helper_precrq_rs_ph_w(v1_t, v1_t, v2_t, cpu_env);
20224 gen_store_gpr(v1_t, ret);
20225 break;
20226 case NM_PRECRQU_S_QB_PH:
20227 check_dsp(ctx);
20228 gen_helper_precrqu_s_qb_ph(v1_t, v1_t, v2_t, cpu_env);
20229 gen_store_gpr(v1_t, ret);
20230 break;
20231 case NM_SHRA_R_W:
20232 check_dsp(ctx);
20233 tcg_gen_movi_tl(t0, rd);
20234 gen_helper_shra_r_w(v1_t, t0, v1_t);
20235 gen_store_gpr(v1_t, rt);
20236 break;
20237 case NM_SHRA_R_PH:
20238 check_dsp(ctx);
20239 tcg_gen_movi_tl(t0, rd >> 1);
20240 switch (extract32(ctx->opcode, 10, 1)) {
20241 case 0:
20242 /* SHRA_PH */
20243 gen_helper_shra_ph(v1_t, t0, v1_t);
20244 gen_store_gpr(v1_t, rt);
20245 break;
20246 case 1:
20247 /* SHRA_R_PH */
20248 gen_helper_shra_r_ph(v1_t, t0, v1_t);
20249 gen_store_gpr(v1_t, rt);
20250 break;
20251 }
20252 break;
20253 case NM_SHLL_S_PH:
20254 check_dsp(ctx);
20255 tcg_gen_movi_tl(t0, rd >> 1);
20256 switch (extract32(ctx->opcode, 10, 2)) {
20257 case 0:
20258 /* SHLL_PH */
20259 gen_helper_shll_ph(v1_t, t0, v1_t, cpu_env);
20260 gen_store_gpr(v1_t, rt);
20261 break;
20262 case 2:
20263 /* SHLL_S_PH */
20264 gen_helper_shll_s_ph(v1_t, t0, v1_t, cpu_env);
20265 gen_store_gpr(v1_t, rt);
20266 break;
20267 default:
20268 gen_reserved_instruction(ctx);
20269 break;
20270 }
20271 break;
20272 case NM_SHLL_S_W:
20273 check_dsp(ctx);
20274 tcg_gen_movi_tl(t0, rd);
20275 gen_helper_shll_s_w(v1_t, t0, v1_t, cpu_env);
20276 gen_store_gpr(v1_t, rt);
20277 break;
20278 case NM_REPL_PH:
20279 check_dsp(ctx);
20280 {
20281 int16_t imm;
20282 imm = sextract32(ctx->opcode, 11, 11);
20283 imm = (int16_t)(imm << 6) >> 6;
20284 if (rt != 0) {
20285 tcg_gen_movi_tl(cpu_gpr[rt], dup_const(MO_16, imm));
20286 }
20287 }
20288 break;
20289 default:
20290 gen_reserved_instruction(ctx);
20291 break;
20292 }
20293 }
20294
20295 static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
20296 {
20297 uint16_t insn;
20298 uint32_t op;
20299 int rt, rs, rd;
20300 int offset;
20301 int imm;
20302
20303 insn = translator_lduw(env, ctx->base.pc_next + 2);
20304 ctx->opcode = (ctx->opcode << 16) | insn;
20305
20306 rt = extract32(ctx->opcode, 21, 5);
20307 rs = extract32(ctx->opcode, 16, 5);
20308 rd = extract32(ctx->opcode, 11, 5);
20309
20310 op = extract32(ctx->opcode, 26, 6);
20311 switch (op) {
20312 case NM_P_ADDIU:
20313 if (rt == 0) {
20314 /* P.RI */
20315 switch (extract32(ctx->opcode, 19, 2)) {
20316 case NM_SIGRIE:
20317 default:
20318 gen_reserved_instruction(ctx);
20319 break;
20320 case NM_P_SYSCALL:
20321 if ((extract32(ctx->opcode, 18, 1)) == NM_SYSCALL) {
20322 generate_exception_end(ctx, EXCP_SYSCALL);
20323 } else {
20324 gen_reserved_instruction(ctx);
20325 }
20326 break;
20327 case NM_BREAK:
20328 generate_exception_end(ctx, EXCP_BREAK);
20329 break;
20330 case NM_SDBBP:
20331 if (is_uhi(extract32(ctx->opcode, 0, 19))) {
20332 gen_helper_do_semihosting(cpu_env);
20333 } else {
20334 if (ctx->hflags & MIPS_HFLAG_SBRI) {
20335 gen_reserved_instruction(ctx);
20336 } else {
20337 generate_exception_end(ctx, EXCP_DBp);
20338 }
20339 }
20340 break;
20341 }
20342 } else {
20343 /* NM_ADDIU */
20344 imm = extract32(ctx->opcode, 0, 16);
20345 if (rs != 0) {
20346 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm);
20347 } else {
20348 tcg_gen_movi_tl(cpu_gpr[rt], imm);
20349 }
20350 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
20351 }
20352 break;
20353 case NM_ADDIUPC:
20354 if (rt != 0) {
20355 offset = sextract32(ctx->opcode, 0, 1) << 21 |
20356 extract32(ctx->opcode, 1, 20) << 1;
20357 target_long addr = addr_add(ctx, ctx->base.pc_next + 4, offset);
20358 tcg_gen_movi_tl(cpu_gpr[rt], addr);
20359 }
20360 break;
20361 case NM_POOL32A:
20362 switch (ctx->opcode & 0x07) {
20363 case NM_POOL32A0:
20364 gen_pool32a0_nanomips_insn(env, ctx);
20365 break;
20366 case NM_POOL32A5:
20367 {
20368 int32_t op1 = extract32(ctx->opcode, 3, 7);
20369 gen_pool32a5_nanomips_insn(ctx, op1, rd, rs, rt);
20370 }
20371 break;
20372 case NM_POOL32A7:
20373 switch (extract32(ctx->opcode, 3, 3)) {
20374 case NM_P_LSX:
20375 gen_p_lsx(ctx, rd, rs, rt);
20376 break;
20377 case NM_LSA:
20378 /*
20379 * In nanoMIPS, the shift field directly encodes the shift
20380 * amount, meaning that the supported shift values are in
20381 * the range 0 to 3 (instead of 1 to 4 in MIPSR6).
20382 */
20383 gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) - 1);
20384 break;
20385 case NM_EXTW:
20386 gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));
20387 break;
20388 case NM_POOL32AXF:
20389 gen_pool32axf_nanomips_insn(env, ctx);
20390 break;
20391 default:
20392 gen_reserved_instruction(ctx);
20393 break;
20394 }
20395 break;
20396 default:
20397 gen_reserved_instruction(ctx);
20398 break;
20399 }
20400 break;
20401 case NM_P_GP_W:
20402 switch (ctx->opcode & 0x03) {
20403 case NM_ADDIUGP_W:
20404 if (rt != 0) {
20405 offset = extract32(ctx->opcode, 0, 21);
20406 gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], offset);
20407 }
20408 break;
20409 case NM_LWGP:
20410 gen_ld(ctx, OPC_LW, rt, 28, extract32(ctx->opcode, 2, 19) << 2);
20411 break;
20412 case NM_SWGP:
20413 gen_st(ctx, OPC_SW, rt, 28, extract32(ctx->opcode, 2, 19) << 2);
20414 break;
20415 default:
20416 gen_reserved_instruction(ctx);
20417 break;
20418 }
20419 break;
20420 case NM_P48I:
20421 {
20422 insn = translator_lduw(env, ctx->base.pc_next + 4);
20423 target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;
20424 switch (extract32(ctx->opcode, 16, 5)) {
20425 case NM_LI48:
20426 check_nms(ctx);
20427 if (rt != 0) {
20428 tcg_gen_movi_tl(cpu_gpr[rt], addr_off);
20429 }
20430 break;
20431 case NM_ADDIU48:
20432 check_nms(ctx);
20433 if (rt != 0) {
20434 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rt], addr_off);
20435 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
20436 }
20437 break;
20438 case NM_ADDIUGP48:
20439 check_nms(ctx);
20440 if (rt != 0) {
20441 gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], addr_off);
20442 }
20443 break;
20444 case NM_ADDIUPC48:
20445 check_nms(ctx);
20446 if (rt != 0) {
20447 target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
20448 addr_off);
20449
20450 tcg_gen_movi_tl(cpu_gpr[rt], addr);
20451 }
20452 break;
20453 case NM_LWPC48:
20454 check_nms(ctx);
20455 if (rt != 0) {
20456 TCGv t0;
20457 t0 = tcg_temp_new();
20458
20459 target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
20460 addr_off);
20461
20462 tcg_gen_movi_tl(t0, addr);
20463 tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL);
20464 tcg_temp_free(t0);
20465 }
20466 break;
20467 case NM_SWPC48:
20468 check_nms(ctx);
20469 {
20470 TCGv t0, t1;
20471 t0 = tcg_temp_new();
20472 t1 = tcg_temp_new();
20473
20474 target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
20475 addr_off);
20476
20477 tcg_gen_movi_tl(t0, addr);
20478 gen_load_gpr(t1, rt);
20479
20480 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
20481
20482 tcg_temp_free(t0);
20483 tcg_temp_free(t1);
20484 }
20485 break;
20486 default:
20487 gen_reserved_instruction(ctx);
20488 break;
20489 }
20490 return 6;
20491 }
20492 case NM_P_U12:
20493 switch (extract32(ctx->opcode, 12, 4)) {
20494 case NM_ORI:
20495 gen_logic_imm(ctx, OPC_ORI, rt, rs, extract32(ctx->opcode, 0, 12));
20496 break;
20497 case NM_XORI:
20498 gen_logic_imm(ctx, OPC_XORI, rt, rs, extract32(ctx->opcode, 0, 12));
20499 break;
20500 case NM_ANDI:
20501 gen_logic_imm(ctx, OPC_ANDI, rt, rs, extract32(ctx->opcode, 0, 12));
20502 break;
20503 case NM_P_SR:
20504 switch (extract32(ctx->opcode, 20, 1)) {
20505 case NM_PP_SR:
20506 switch (ctx->opcode & 3) {
20507 case NM_SAVE:
20508 gen_save(ctx, rt, extract32(ctx->opcode, 16, 4),
20509 extract32(ctx->opcode, 2, 1),
20510 extract32(ctx->opcode, 3, 9) << 3);
20511 break;
20512 case NM_RESTORE:
20513 case NM_RESTORE_JRC:
20514 gen_restore(ctx, rt, extract32(ctx->opcode, 16, 4),
20515 extract32(ctx->opcode, 2, 1),
20516 extract32(ctx->opcode, 3, 9) << 3);
20517 if ((ctx->opcode & 3) == NM_RESTORE_JRC) {
20518 gen_compute_branch_nm(ctx, OPC_JR, 2, 31, 0, 0);
20519 }
20520 break;
20521 default:
20522 gen_reserved_instruction(ctx);
20523 break;
20524 }
20525 break;
20526 case NM_P_SR_F:
20527 gen_reserved_instruction(ctx);
20528 break;
20529 }
20530 break;
20531 case NM_SLTI:
20532 gen_slt_imm(ctx, OPC_SLTI, rt, rs, extract32(ctx->opcode, 0, 12));
20533 break;
20534 case NM_SLTIU:
20535 gen_slt_imm(ctx, OPC_SLTIU, rt, rs, extract32(ctx->opcode, 0, 12));
20536 break;
20537 case NM_SEQI:
20538 {
20539 TCGv t0 = tcg_temp_new();
20540
20541 imm = extract32(ctx->opcode, 0, 12);
20542 gen_load_gpr(t0, rs);
20543 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, imm);
20544 gen_store_gpr(t0, rt);
20545
20546 tcg_temp_free(t0);
20547 }
20548 break;
20549 case NM_ADDIUNEG:
20550 imm = (int16_t) extract32(ctx->opcode, 0, 12);
20551 gen_arith_imm(ctx, OPC_ADDIU, rt, rs, -imm);
20552 break;
20553 case NM_P_SHIFT:
20554 {
20555 int shift = extract32(ctx->opcode, 0, 5);
20556 switch (extract32(ctx->opcode, 5, 4)) {
20557 case NM_P_SLL:
20558 if (rt == 0 && shift == 0) {
20559 /* NOP */
20560 } else if (rt == 0 && shift == 3) {
20561 /* EHB - treat as NOP */
20562 } else if (rt == 0 && shift == 5) {
20563 /* PAUSE - treat as NOP */
20564 } else if (rt == 0 && shift == 6) {
20565 /* SYNC */
20566 gen_sync(extract32(ctx->opcode, 16, 5));
20567 } else {
20568 /* SLL */
20569 gen_shift_imm(ctx, OPC_SLL, rt, rs,
20570 extract32(ctx->opcode, 0, 5));
20571 }
20572 break;
20573 case NM_SRL:
20574 gen_shift_imm(ctx, OPC_SRL, rt, rs,
20575 extract32(ctx->opcode, 0, 5));
20576 break;
20577 case NM_SRA:
20578 gen_shift_imm(ctx, OPC_SRA, rt, rs,
20579 extract32(ctx->opcode, 0, 5));
20580 break;
20581 case NM_ROTR:
20582 gen_shift_imm(ctx, OPC_ROTR, rt, rs,
20583 extract32(ctx->opcode, 0, 5));
20584 break;
20585 }
20586 }
20587 break;
20588 case NM_P_ROTX:
20589 check_nms(ctx);
20590 if (rt != 0) {
20591 TCGv t0 = tcg_temp_new();
20592 TCGv_i32 shift = tcg_const_i32(extract32(ctx->opcode, 0, 5));
20593 TCGv_i32 shiftx = tcg_const_i32(extract32(ctx->opcode, 7, 4)
20594 << 1);
20595 TCGv_i32 stripe = tcg_const_i32(extract32(ctx->opcode, 6, 1));
20596
20597 gen_load_gpr(t0, rs);
20598 gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe);
20599 tcg_temp_free(t0);
20600
20601 tcg_temp_free_i32(shift);
20602 tcg_temp_free_i32(shiftx);
20603 tcg_temp_free_i32(stripe);
20604 }
20605 break;
20606 case NM_P_INS:
20607 switch (((ctx->opcode >> 10) & 2) |
20608 (extract32(ctx->opcode, 5, 1))) {
20609 case NM_INS:
20610 check_nms(ctx);
20611 gen_bitops(ctx, OPC_INS, rt, rs, extract32(ctx->opcode, 0, 5),
20612 extract32(ctx->opcode, 6, 5));
20613 break;
20614 default:
20615 gen_reserved_instruction(ctx);
20616 break;
20617 }
20618 break;
20619 case NM_P_EXT:
20620 switch (((ctx->opcode >> 10) & 2) |
20621 (extract32(ctx->opcode, 5, 1))) {
20622 case NM_EXT:
20623 check_nms(ctx);
20624 gen_bitops(ctx, OPC_EXT, rt, rs, extract32(ctx->opcode, 0, 5),
20625 extract32(ctx->opcode, 6, 5));
20626 break;
20627 default:
20628 gen_reserved_instruction(ctx);
20629 break;
20630 }
20631 break;
20632 default:
20633 gen_reserved_instruction(ctx);
20634 break;
20635 }
20636 break;
20637 case NM_POOL32F:
20638 gen_pool32f_nanomips_insn(ctx);
20639 break;
20640 case NM_POOL32S:
20641 break;
20642 case NM_P_LUI:
20643 switch (extract32(ctx->opcode, 1, 1)) {
20644 case NM_LUI:
20645 if (rt != 0) {
20646 tcg_gen_movi_tl(cpu_gpr[rt],
20647 sextract32(ctx->opcode, 0, 1) << 31 |
20648 extract32(ctx->opcode, 2, 10) << 21 |
20649 extract32(ctx->opcode, 12, 9) << 12);
20650 }
20651 break;
20652 case NM_ALUIPC:
20653 if (rt != 0) {
20654 offset = sextract32(ctx->opcode, 0, 1) << 31 |
20655 extract32(ctx->opcode, 2, 10) << 21 |
20656 extract32(ctx->opcode, 12, 9) << 12;
20657 target_long addr;
20658 addr = ~0xFFF & addr_add(ctx, ctx->base.pc_next + 4, offset);
20659 tcg_gen_movi_tl(cpu_gpr[rt], addr);
20660 }
20661 break;
20662 }
20663 break;
20664 case NM_P_GP_BH:
20665 {
20666 uint32_t u = extract32(ctx->opcode, 0, 18);
20667
20668 switch (extract32(ctx->opcode, 18, 3)) {
20669 case NM_LBGP:
20670 gen_ld(ctx, OPC_LB, rt, 28, u);
20671 break;
20672 case NM_SBGP:
20673 gen_st(ctx, OPC_SB, rt, 28, u);
20674 break;
20675 case NM_LBUGP:
20676 gen_ld(ctx, OPC_LBU, rt, 28, u);
20677 break;
20678 case NM_ADDIUGP_B:
20679 if (rt != 0) {
20680 gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], u);
20681 }
20682 break;
20683 case NM_P_GP_LH:
20684 u &= ~1;
20685 switch (ctx->opcode & 1) {
20686 case NM_LHGP:
20687 gen_ld(ctx, OPC_LH, rt, 28, u);
20688 break;
20689 case NM_LHUGP:
20690 gen_ld(ctx, OPC_LHU, rt, 28, u);
20691 break;
20692 }
20693 break;
20694 case NM_P_GP_SH:
20695 u &= ~1;
20696 switch (ctx->opcode & 1) {
20697 case NM_SHGP:
20698 gen_st(ctx, OPC_SH, rt, 28, u);
20699 break;
20700 default:
20701 gen_reserved_instruction(ctx);
20702 break;
20703 }
20704 break;
20705 case NM_P_GP_CP1:
20706 u &= ~0x3;
20707 switch (ctx->opcode & 0x3) {
20708 case NM_LWC1GP:
20709 gen_cop1_ldst(ctx, OPC_LWC1, rt, 28, u);
20710 break;
20711 case NM_LDC1GP:
20712 gen_cop1_ldst(ctx, OPC_LDC1, rt, 28, u);
20713 break;
20714 case NM_SWC1GP:
20715 gen_cop1_ldst(ctx, OPC_SWC1, rt, 28, u);
20716 break;
20717 case NM_SDC1GP:
20718 gen_cop1_ldst(ctx, OPC_SDC1, rt, 28, u);
20719 break;
20720 }
20721 break;
20722 default:
20723 gen_reserved_instruction(ctx);
20724 break;
20725 }
20726 }
20727 break;
20728 case NM_P_LS_U12:
20729 {
20730 uint32_t u = extract32(ctx->opcode, 0, 12);
20731
20732 switch (extract32(ctx->opcode, 12, 4)) {
20733 case NM_P_PREFU12:
20734 if (rt == 31) {
20735 /* SYNCI */
20736 /*
20737 * Break the TB to be able to sync copied instructions
20738 * immediately.
20739 */
20740 ctx->base.is_jmp = DISAS_STOP;
20741 } else {
20742 /* PREF */
20743 /* Treat as NOP. */
20744 }
20745 break;
20746 case NM_LB:
20747 gen_ld(ctx, OPC_LB, rt, rs, u);
20748 break;
20749 case NM_LH:
20750 gen_ld(ctx, OPC_LH, rt, rs, u);
20751 break;
20752 case NM_LW:
20753 gen_ld(ctx, OPC_LW, rt, rs, u);
20754 break;
20755 case NM_LBU:
20756 gen_ld(ctx, OPC_LBU, rt, rs, u);
20757 break;
20758 case NM_LHU:
20759 gen_ld(ctx, OPC_LHU, rt, rs, u);
20760 break;
20761 case NM_SB:
20762 gen_st(ctx, OPC_SB, rt, rs, u);
20763 break;
20764 case NM_SH:
20765 gen_st(ctx, OPC_SH, rt, rs, u);
20766 break;
20767 case NM_SW:
20768 gen_st(ctx, OPC_SW, rt, rs, u);
20769 break;
20770 case NM_LWC1:
20771 gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, u);
20772 break;
20773 case NM_LDC1:
20774 gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, u);
20775 break;
20776 case NM_SWC1:
20777 gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, u);
20778 break;
20779 case NM_SDC1:
20780 gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, u);
20781 break;
20782 default:
20783 gen_reserved_instruction(ctx);
20784 break;
20785 }
20786 }
20787 break;
20788 case NM_P_LS_S9:
20789 {
20790 int32_t s = (sextract32(ctx->opcode, 15, 1) << 8) |
20791 extract32(ctx->opcode, 0, 8);
20792
20793 switch (extract32(ctx->opcode, 8, 3)) {
20794 case NM_P_LS_S0:
20795 switch (extract32(ctx->opcode, 11, 4)) {
20796 case NM_LBS9:
20797 gen_ld(ctx, OPC_LB, rt, rs, s);
20798 break;
20799 case NM_LHS9:
20800 gen_ld(ctx, OPC_LH, rt, rs, s);
20801 break;
20802 case NM_LWS9:
20803 gen_ld(ctx, OPC_LW, rt, rs, s);
20804 break;
20805 case NM_LBUS9:
20806 gen_ld(ctx, OPC_LBU, rt, rs, s);
20807 break;
20808 case NM_LHUS9:
20809 gen_ld(ctx, OPC_LHU, rt, rs, s);
20810 break;
20811 case NM_SBS9:
20812 gen_st(ctx, OPC_SB, rt, rs, s);
20813 break;
20814 case NM_SHS9:
20815 gen_st(ctx, OPC_SH, rt, rs, s);
20816 break;
20817 case NM_SWS9:
20818 gen_st(ctx, OPC_SW, rt, rs, s);
20819 break;
20820 case NM_LWC1S9:
20821 gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, s);
20822 break;
20823 case NM_LDC1S9:
20824 gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, s);
20825 break;
20826 case NM_SWC1S9:
20827 gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, s);
20828 break;
20829 case NM_SDC1S9:
20830 gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, s);
20831 break;
20832 case NM_P_PREFS9:
20833 if (rt == 31) {
20834 /* SYNCI */
20835 /*
20836 * Break the TB to be able to sync copied instructions
20837 * immediately.
20838 */
20839 ctx->base.is_jmp = DISAS_STOP;
20840 } else {
20841 /* PREF */
20842 /* Treat as NOP. */
20843 }
20844 break;
20845 default:
20846 gen_reserved_instruction(ctx);
20847 break;
20848 }
20849 break;
20850 case NM_P_LS_S1:
20851 switch (extract32(ctx->opcode, 11, 4)) {
20852 case NM_UALH:
20853 case NM_UASH:
20854 check_nms(ctx);
20855 {
20856 TCGv t0 = tcg_temp_new();
20857 TCGv t1 = tcg_temp_new();
20858
20859 gen_base_offset_addr(ctx, t0, rs, s);
20860
20861 switch (extract32(ctx->opcode, 11, 4)) {
20862 case NM_UALH:
20863 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
20864 MO_UNALN);
20865 gen_store_gpr(t0, rt);
20866 break;
20867 case NM_UASH:
20868 gen_load_gpr(t1, rt);
20869 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
20870 MO_UNALN);
20871 break;
20872 }
20873 tcg_temp_free(t0);
20874 tcg_temp_free(t1);
20875 }
20876 break;
20877 case NM_P_LL:
20878 switch (ctx->opcode & 0x03) {
20879 case NM_LL:
20880 gen_ld(ctx, OPC_LL, rt, rs, s);
20881 break;
20882 case NM_LLWP:
20883 check_xnp(ctx);
20884 gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
20885 break;
20886 }
20887 break;
20888 case NM_P_SC:
20889 switch (ctx->opcode & 0x03) {
20890 case NM_SC:
20891 gen_st_cond(ctx, rt, rs, s, MO_TESL, false);
20892 break;
20893 case NM_SCWP:
20894 check_xnp(ctx);
20895 gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
20896 false);
20897 break;
20898 }
20899 break;
20900 case NM_CACHE:
20901 check_cp0_enabled(ctx);
20902 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
20903 gen_cache_operation(ctx, rt, rs, s);
20904 }
20905 break;
20906 }
20907 break;
20908 case NM_P_LS_E0:
20909 switch (extract32(ctx->opcode, 11, 4)) {
20910 case NM_LBE:
20911 check_eva(ctx);
20912 check_cp0_enabled(ctx);
20913 gen_ld(ctx, OPC_LBE, rt, rs, s);
20914 break;
20915 case NM_SBE:
20916 check_eva(ctx);
20917 check_cp0_enabled(ctx);
20918 gen_st(ctx, OPC_SBE, rt, rs, s);
20919 break;
20920 case NM_LBUE:
20921 check_eva(ctx);
20922 check_cp0_enabled(ctx);
20923 gen_ld(ctx, OPC_LBUE, rt, rs, s);
20924 break;
20925 case NM_P_PREFE:
20926 if (rt == 31) {
20927 /* case NM_SYNCIE */
20928 check_eva(ctx);
20929 check_cp0_enabled(ctx);
20930 /*
20931 * Break the TB to be able to sync copied instructions
20932 * immediately.
20933 */
20934 ctx->base.is_jmp = DISAS_STOP;
20935 } else {
20936 /* case NM_PREFE */
20937 check_eva(ctx);
20938 check_cp0_enabled(ctx);
20939 /* Treat as NOP. */
20940 }
20941 break;
20942 case NM_LHE:
20943 check_eva(ctx);
20944 check_cp0_enabled(ctx);
20945 gen_ld(ctx, OPC_LHE, rt, rs, s);
20946 break;
20947 case NM_SHE:
20948 check_eva(ctx);
20949 check_cp0_enabled(ctx);
20950 gen_st(ctx, OPC_SHE, rt, rs, s);
20951 break;
20952 case NM_LHUE:
20953 check_eva(ctx);
20954 check_cp0_enabled(ctx);
20955 gen_ld(ctx, OPC_LHUE, rt, rs, s);
20956 break;
20957 case NM_CACHEE:
20958 check_nms_dl_il_sl_tl_l2c(ctx);
20959 gen_cache_operation(ctx, rt, rs, s);
20960 break;
20961 case NM_LWE:
20962 check_eva(ctx);
20963 check_cp0_enabled(ctx);
20964 gen_ld(ctx, OPC_LWE, rt, rs, s);
20965 break;
20966 case NM_SWE:
20967 check_eva(ctx);
20968 check_cp0_enabled(ctx);
20969 gen_st(ctx, OPC_SWE, rt, rs, s);
20970 break;
20971 case NM_P_LLE:
20972 switch (extract32(ctx->opcode, 2, 2)) {
20973 case NM_LLE:
20974 check_xnp(ctx);
20975 check_eva(ctx);
20976 check_cp0_enabled(ctx);
20977 gen_ld(ctx, OPC_LLE, rt, rs, s);
20978 break;
20979 case NM_LLWPE:
20980 check_xnp(ctx);
20981 check_eva(ctx);
20982 check_cp0_enabled(ctx);
20983 gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
20984 break;
20985 default:
20986 gen_reserved_instruction(ctx);
20987 break;
20988 }
20989 break;
20990 case NM_P_SCE:
20991 switch (extract32(ctx->opcode, 2, 2)) {
20992 case NM_SCE:
20993 check_xnp(ctx);
20994 check_eva(ctx);
20995 check_cp0_enabled(ctx);
20996 gen_st_cond(ctx, rt, rs, s, MO_TESL, true);
20997 break;
20998 case NM_SCWPE:
20999 check_xnp(ctx);
21000 check_eva(ctx);
21001 check_cp0_enabled(ctx);
21002 gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
21003 true);
21004 break;
21005 default:
21006 gen_reserved_instruction(ctx);
21007 break;
21008 }
21009 break;
21010 }
21011 break;
21012 case NM_P_LS_WM:
21013 case NM_P_LS_UAWM:
21014 check_nms(ctx);
21015 {
21016 int count = extract32(ctx->opcode, 12, 3);
21017 int counter = 0;
21018
21019 offset = sextract32(ctx->opcode, 15, 1) << 8 |
21020 extract32(ctx->opcode, 0, 8);
21021 TCGv va = tcg_temp_new();
21022 TCGv t1 = tcg_temp_new();
21023 MemOp memop = (extract32(ctx->opcode, 8, 3)) ==
21024 NM_P_LS_UAWM ? MO_UNALN : 0;
21025
21026 count = (count == 0) ? 8 : count;
21027 while (counter != count) {
21028 int this_rt = ((rt + counter) & 0x1f) | (rt & 0x10);
21029 int this_offset = offset + (counter << 2);
21030
21031 gen_base_offset_addr(ctx, va, rs, this_offset);
21032
21033 switch (extract32(ctx->opcode, 11, 1)) {
21034 case NM_LWM:
21035 tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx,
21036 memop | MO_TESL);
21037 gen_store_gpr(t1, this_rt);
21038 if ((this_rt == rs) &&
21039 (counter != (count - 1))) {
21040 /* UNPREDICTABLE */
21041 }
21042 break;
21043 case NM_SWM:
21044 this_rt = (rt == 0) ? 0 : this_rt;
21045 gen_load_gpr(t1, this_rt);
21046 tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx,
21047 memop | MO_TEUL);
21048 break;
21049 }
21050 counter++;
21051 }
21052 tcg_temp_free(va);
21053 tcg_temp_free(t1);
21054 }
21055 break;
21056 default:
21057 gen_reserved_instruction(ctx);
21058 break;
21059 }
21060 }
21061 break;
21062 case NM_MOVE_BALC:
21063 check_nms(ctx);
21064 {
21065 TCGv t0 = tcg_temp_new();
21066 int32_t s = sextract32(ctx->opcode, 0, 1) << 21 |
21067 extract32(ctx->opcode, 1, 20) << 1;
21068 rd = (extract32(ctx->opcode, 24, 1)) == 0 ? 4 : 5;
21069 rt = decode_gpr_gpr4_zero(extract32(ctx->opcode, 25, 1) << 3 |
21070 extract32(ctx->opcode, 21, 3));
21071 gen_load_gpr(t0, rt);
21072 tcg_gen_mov_tl(cpu_gpr[rd], t0);
21073 gen_compute_branch_nm(ctx, OPC_BGEZAL, 4, 0, 0, s);
21074 tcg_temp_free(t0);
21075 }
21076 break;
21077 case NM_P_BAL:
21078 {
21079 int32_t s = sextract32(ctx->opcode, 0, 1) << 25 |
21080 extract32(ctx->opcode, 1, 24) << 1;
21081
21082 if ((extract32(ctx->opcode, 25, 1)) == 0) {
21083 /* BC */
21084 gen_compute_branch_nm(ctx, OPC_BEQ, 4, 0, 0, s);
21085 } else {
21086 /* BALC */
21087 gen_compute_branch_nm(ctx, OPC_BGEZAL, 4, 0, 0, s);
21088 }
21089 }
21090 break;
21091 case NM_P_J:
21092 switch (extract32(ctx->opcode, 12, 4)) {
21093 case NM_JALRC:
21094 case NM_JALRC_HB:
21095 gen_compute_branch_nm(ctx, OPC_JALR, 4, rs, rt, 0);
21096 break;
21097 case NM_P_BALRSC:
21098 gen_compute_nanomips_pbalrsc_branch(ctx, rs, rt);
21099 break;
21100 default:
21101 gen_reserved_instruction(ctx);
21102 break;
21103 }
21104 break;
21105 case NM_P_BR1:
21106 {
21107 int32_t s = sextract32(ctx->opcode, 0, 1) << 14 |
21108 extract32(ctx->opcode, 1, 13) << 1;
21109 switch (extract32(ctx->opcode, 14, 2)) {
21110 case NM_BEQC:
21111 check_nms(ctx);
21112 gen_compute_branch_nm(ctx, OPC_BEQ, 4, rs, rt, s);
21113 break;
21114 case NM_P_BR3A:
21115 s = sextract32(ctx->opcode, 0, 1) << 14 |
21116 extract32(ctx->opcode, 1, 13) << 1;
21117 check_cp1_enabled(ctx);
21118 switch (extract32(ctx->opcode, 16, 5)) {
21119 case NM_BC1EQZC:
21120 gen_compute_branch_cp1_nm(ctx, OPC_BC1EQZ, rt, s);
21121 break;
21122 case NM_BC1NEZC:
21123 gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s);
21124 break;
21125 case NM_BPOSGE32C:
21126 check_dsp_r3(ctx);
21127 {
21128 int32_t imm = extract32(ctx->opcode, 1, 13) |
21129 extract32(ctx->opcode, 0, 1) << 13;
21130
21131 gen_compute_branch_nm(ctx, OPC_BPOSGE32, 4, -1, -2,
21132 imm);
21133 }
21134 break;
21135 default:
21136 gen_reserved_instruction(ctx);
21137 break;
21138 }
21139 break;
21140 case NM_BGEC:
21141 if (rs == rt) {
21142 gen_compute_compact_branch_nm(ctx, OPC_BC, rs, rt, s);
21143 } else {
21144 gen_compute_compact_branch_nm(ctx, OPC_BGEC, rs, rt, s);
21145 }
21146 break;
21147 case NM_BGEUC:
21148 if (rs == rt || rt == 0) {
21149 gen_compute_compact_branch_nm(ctx, OPC_BC, 0, 0, s);
21150 } else if (rs == 0) {
21151 gen_compute_compact_branch_nm(ctx, OPC_BEQZC, rt, 0, s);
21152 } else {
21153 gen_compute_compact_branch_nm(ctx, OPC_BGEUC, rs, rt, s);
21154 }
21155 break;
21156 }
21157 }
21158 break;
21159 case NM_P_BR2:
21160 {
21161 int32_t s = sextract32(ctx->opcode, 0, 1) << 14 |
21162 extract32(ctx->opcode, 1, 13) << 1;
21163 switch (extract32(ctx->opcode, 14, 2)) {
21164 case NM_BNEC:
21165 check_nms(ctx);
21166 gen_compute_branch_nm(ctx, OPC_BNE, 4, rs, rt, s);
21167 break;
21168 case NM_BLTC:
21169 if (rs != 0 && rt != 0 && rs == rt) {
21170 /* NOP */
21171 ctx->hflags |= MIPS_HFLAG_FBNSLOT;
21172 } else {
21173 gen_compute_compact_branch_nm(ctx, OPC_BLTC, rs, rt, s);
21174 }
21175 break;
21176 case NM_BLTUC:
21177 if (rs == 0 || rs == rt) {
21178 /* NOP */
21179 ctx->hflags |= MIPS_HFLAG_FBNSLOT;
21180 } else {
21181 gen_compute_compact_branch_nm(ctx, OPC_BLTUC, rs, rt, s);
21182 }
21183 break;
21184 default:
21185 gen_reserved_instruction(ctx);
21186 break;
21187 }
21188 }
21189 break;
21190 case NM_P_BRI:
21191 {
21192 int32_t s = sextract32(ctx->opcode, 0, 1) << 11 |
21193 extract32(ctx->opcode, 1, 10) << 1;
21194 uint32_t u = extract32(ctx->opcode, 11, 7);
21195
21196 gen_compute_imm_branch(ctx, extract32(ctx->opcode, 18, 3),
21197 rt, u, s);
21198 }
21199 break;
21200 default:
21201 gen_reserved_instruction(ctx);
21202 break;
21203 }
21204 return 4;
21205 }
21206
21207 static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
21208 {
21209 uint32_t op;
21210 int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
21211 int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
21212 int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode));
21213 int offset;
21214 int imm;
21215
21216 /* make sure instructions are on a halfword boundary */
21217 if (ctx->base.pc_next & 0x1) {
21218 TCGv tmp = tcg_const_tl(ctx->base.pc_next);
21219 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
21220 tcg_temp_free(tmp);
21221 generate_exception_end(ctx, EXCP_AdEL);
21222 return 2;
21223 }
21224
21225 op = extract32(ctx->opcode, 10, 6);
21226 switch (op) {
21227 case NM_P16_MV:
21228 rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
21229 if (rt != 0) {
21230 /* MOVE */
21231 rs = NANOMIPS_EXTRACT_RS5(ctx->opcode);
21232 gen_arith(ctx, OPC_ADDU, rt, rs, 0);
21233 } else {
21234 /* P16.RI */
21235 switch (extract32(ctx->opcode, 3, 2)) {
21236 case NM_P16_SYSCALL:
21237 if (extract32(ctx->opcode, 2, 1) == 0) {
21238 generate_exception_end(ctx, EXCP_SYSCALL);
21239 } else {
21240 gen_reserved_instruction(ctx);
21241 }
21242 break;
21243 case NM_BREAK16:
21244 generate_exception_end(ctx, EXCP_BREAK);
21245 break;
21246 case NM_SDBBP16:
21247 if (is_uhi(extract32(ctx->opcode, 0, 3))) {
21248 gen_helper_do_semihosting(cpu_env);
21249 } else {
21250 if (ctx->hflags & MIPS_HFLAG_SBRI) {
21251 gen_reserved_instruction(ctx);
21252 } else {
21253 generate_exception_end(ctx, EXCP_DBp);
21254 }
21255 }
21256 break;
21257 default:
21258 gen_reserved_instruction(ctx);
21259 break;
21260 }
21261 }
21262 break;
21263 case NM_P16_SHIFT:
21264 {
21265 int shift = extract32(ctx->opcode, 0, 3);
21266 uint32_t opc = 0;
21267 shift = (shift == 0) ? 8 : shift;
21268
21269 switch (extract32(ctx->opcode, 3, 1)) {
21270 case NM_SLL16:
21271 opc = OPC_SLL;
21272 break;
21273 case NM_SRL16:
21274 opc = OPC_SRL;
21275 break;
21276 }
21277 gen_shift_imm(ctx, opc, rt, rs, shift);
21278 }
21279 break;
21280 case NM_P16C:
21281 switch (ctx->opcode & 1) {
21282 case NM_POOL16C_0:
21283 gen_pool16c_nanomips_insn(ctx);
21284 break;
21285 case NM_LWXS16:
21286 gen_ldxs(ctx, rt, rs, rd);
21287 break;
21288 }
21289 break;
21290 case NM_P16_A1:
21291 switch (extract32(ctx->opcode, 6, 1)) {
21292 case NM_ADDIUR1SP:
21293 imm = extract32(ctx->opcode, 0, 6) << 2;
21294 gen_arith_imm(ctx, OPC_ADDIU, rt, 29, imm);
21295 break;
21296 default:
21297 gen_reserved_instruction(ctx);
21298 break;
21299 }
21300 break;
21301 case NM_P16_A2:
21302 switch (extract32(ctx->opcode, 3, 1)) {
21303 case NM_ADDIUR2:
21304 imm = extract32(ctx->opcode, 0, 3) << 2;
21305 gen_arith_imm(ctx, OPC_ADDIU, rt, rs, imm);
21306 break;
21307 case NM_P_ADDIURS5:
21308 rt = extract32(ctx->opcode, 5, 5);
21309 if (rt != 0) {
21310 /* imm = sign_extend(s[3] . s[2:0] , from_nbits = 4) */
21311 imm = (sextract32(ctx->opcode, 4, 1) << 3) |
21312 (extract32(ctx->opcode, 0, 3));
21313 gen_arith_imm(ctx, OPC_ADDIU, rt, rt, imm);
21314 }
21315 break;
21316 }
21317 break;
21318 case NM_P16_ADDU:
21319 switch (ctx->opcode & 0x1) {
21320 case NM_ADDU16:
21321 gen_arith(ctx, OPC_ADDU, rd, rs, rt);
21322 break;
21323 case NM_SUBU16:
21324 gen_arith(ctx, OPC_SUBU, rd, rs, rt);
21325 break;
21326 }
21327 break;
21328 case NM_P16_4X4:
21329 rt = (extract32(ctx->opcode, 9, 1) << 3) |
21330 extract32(ctx->opcode, 5, 3);
21331 rs = (extract32(ctx->opcode, 4, 1) << 3) |
21332 extract32(ctx->opcode, 0, 3);
21333 rt = decode_gpr_gpr4(rt);
21334 rs = decode_gpr_gpr4(rs);
21335 switch ((extract32(ctx->opcode, 7, 2) & 0x2) |
21336 (extract32(ctx->opcode, 3, 1))) {
21337 case NM_ADDU4X4:
21338 check_nms(ctx);
21339 gen_arith(ctx, OPC_ADDU, rt, rs, rt);
21340 break;
21341 case NM_MUL4X4:
21342 check_nms(ctx);
21343 gen_r6_muldiv(ctx, R6_OPC_MUL, rt, rs, rt);
21344 break;
21345 default:
21346 gen_reserved_instruction(ctx);
21347 break;
21348 }
21349 break;
21350 case NM_LI16:
21351 {
21352 int imm = extract32(ctx->opcode, 0, 7);
21353 imm = (imm == 0x7f ? -1 : imm);
21354 if (rt != 0) {
21355 tcg_gen_movi_tl(cpu_gpr[rt], imm);
21356 }
21357 }
21358 break;
21359 case NM_ANDI16:
21360 {
21361 uint32_t u = extract32(ctx->opcode, 0, 4);
21362 u = (u == 12) ? 0xff :
21363 (u == 13) ? 0xffff : u;
21364 gen_logic_imm(ctx, OPC_ANDI, rt, rs, u);
21365 }
21366 break;
21367 case NM_P16_LB:
21368 offset = extract32(ctx->opcode, 0, 2);
21369 switch (extract32(ctx->opcode, 2, 2)) {
21370 case NM_LB16:
21371 gen_ld(ctx, OPC_LB, rt, rs, offset);
21372 break;
21373 case NM_SB16:
21374 rt = decode_gpr_gpr3_src_store(
21375 NANOMIPS_EXTRACT_RT3(ctx->opcode));
21376 gen_st(ctx, OPC_SB, rt, rs, offset);
21377 break;
21378 case NM_LBU16:
21379 gen_ld(ctx, OPC_LBU, rt, rs, offset);
21380 break;
21381 default:
21382 gen_reserved_instruction(ctx);
21383 break;
21384 }
21385 break;
21386 case NM_P16_LH:
21387 offset = extract32(ctx->opcode, 1, 2) << 1;
21388 switch ((extract32(ctx->opcode, 3, 1) << 1) | (ctx->opcode & 1)) {
21389 case NM_LH16:
21390 gen_ld(ctx, OPC_LH, rt, rs, offset);
21391 break;
21392 case NM_SH16:
21393 rt = decode_gpr_gpr3_src_store(
21394 NANOMIPS_EXTRACT_RT3(ctx->opcode));
21395 gen_st(ctx, OPC_SH, rt, rs, offset);
21396 break;
21397 case NM_LHU16:
21398 gen_ld(ctx, OPC_LHU, rt, rs, offset);
21399 break;
21400 default:
21401 gen_reserved_instruction(ctx);
21402 break;
21403 }
21404 break;
21405 case NM_LW16:
21406 offset = extract32(ctx->opcode, 0, 4) << 2;
21407 gen_ld(ctx, OPC_LW, rt, rs, offset);
21408 break;
21409 case NM_LWSP16:
21410 rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
21411 offset = extract32(ctx->opcode, 0, 5) << 2;
21412 gen_ld(ctx, OPC_LW, rt, 29, offset);
21413 break;
21414 case NM_LW4X4:
21415 check_nms(ctx);
21416 rt = (extract32(ctx->opcode, 9, 1) << 3) |
21417 extract32(ctx->opcode, 5, 3);
21418 rs = (extract32(ctx->opcode, 4, 1) << 3) |
21419 extract32(ctx->opcode, 0, 3);
21420 offset = (extract32(ctx->opcode, 3, 1) << 3) |
21421 (extract32(ctx->opcode, 8, 1) << 2);
21422 rt = decode_gpr_gpr4(rt);
21423 rs = decode_gpr_gpr4(rs);
21424 gen_ld(ctx, OPC_LW, rt, rs, offset);
21425 break;
21426 case NM_SW4X4:
21427 check_nms(ctx);
21428 rt = (extract32(ctx->opcode, 9, 1) << 3) |
21429 extract32(ctx->opcode, 5, 3);
21430 rs = (extract32(ctx->opcode, 4, 1) << 3) |
21431 extract32(ctx->opcode, 0, 3);
21432 offset = (extract32(ctx->opcode, 3, 1) << 3) |
21433 (extract32(ctx->opcode, 8, 1) << 2);
21434 rt = decode_gpr_gpr4_zero(rt);
21435 rs = decode_gpr_gpr4(rs);
21436 gen_st(ctx, OPC_SW, rt, rs, offset);
21437 break;
21438 case NM_LWGP16:
21439 offset = extract32(ctx->opcode, 0, 7) << 2;
21440 gen_ld(ctx, OPC_LW, rt, 28, offset);
21441 break;
21442 case NM_SWSP16:
21443 rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
21444 offset = extract32(ctx->opcode, 0, 5) << 2;
21445 gen_st(ctx, OPC_SW, rt, 29, offset);
21446 break;
21447 case NM_SW16:
21448 rt = decode_gpr_gpr3_src_store(
21449 NANOMIPS_EXTRACT_RT3(ctx->opcode));
21450 rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
21451 offset = extract32(ctx->opcode, 0, 4) << 2;
21452 gen_st(ctx, OPC_SW, rt, rs, offset);
21453 break;
21454 case NM_SWGP16:
21455 rt = decode_gpr_gpr3_src_store(
21456 NANOMIPS_EXTRACT_RT3(ctx->opcode));
21457 offset = extract32(ctx->opcode, 0, 7) << 2;
21458 gen_st(ctx, OPC_SW, rt, 28, offset);
21459 break;
21460 case NM_BC16:
21461 gen_compute_branch_nm(ctx, OPC_BEQ, 2, 0, 0,
21462 (sextract32(ctx->opcode, 0, 1) << 10) |
21463 (extract32(ctx->opcode, 1, 9) << 1));
21464 break;
21465 case NM_BALC16:
21466 gen_compute_branch_nm(ctx, OPC_BGEZAL, 2, 0, 0,
21467 (sextract32(ctx->opcode, 0, 1) << 10) |
21468 (extract32(ctx->opcode, 1, 9) << 1));
21469 break;
21470 case NM_BEQZC16:
21471 gen_compute_branch_nm(ctx, OPC_BEQ, 2, rt, 0,
21472 (sextract32(ctx->opcode, 0, 1) << 7) |
21473 (extract32(ctx->opcode, 1, 6) << 1));
21474 break;
21475 case NM_BNEZC16:
21476 gen_compute_branch_nm(ctx, OPC_BNE, 2, rt, 0,
21477 (sextract32(ctx->opcode, 0, 1) << 7) |
21478 (extract32(ctx->opcode, 1, 6) << 1));
21479 break;
21480 case NM_P16_BR:
21481 switch (ctx->opcode & 0xf) {
21482 case 0:
21483 /* P16.JRC */
21484 switch (extract32(ctx->opcode, 4, 1)) {
21485 case NM_JRC:
21486 gen_compute_branch_nm(ctx, OPC_JR, 2,
21487 extract32(ctx->opcode, 5, 5), 0, 0);
21488 break;
21489 case NM_JALRC16:
21490 gen_compute_branch_nm(ctx, OPC_JALR, 2,
21491 extract32(ctx->opcode, 5, 5), 31, 0);
21492 break;
21493 }
21494 break;
21495 default:
21496 {
21497 /* P16.BRI */
21498 uint32_t opc = extract32(ctx->opcode, 4, 3) <
21499 extract32(ctx->opcode, 7, 3) ? OPC_BEQ : OPC_BNE;
21500 gen_compute_branch_nm(ctx, opc, 2, rs, rt,
21501 extract32(ctx->opcode, 0, 4) << 1);
21502 }
21503 break;
21504 }
21505 break;
21506 case NM_P16_SR:
21507 {
21508 int count = extract32(ctx->opcode, 0, 4);
21509 int u = extract32(ctx->opcode, 4, 4) << 4;
21510
21511 rt = 30 + extract32(ctx->opcode, 9, 1);
21512 switch (extract32(ctx->opcode, 8, 1)) {
21513 case NM_SAVE16:
21514 gen_save(ctx, rt, count, 0, u);
21515 break;
21516 case NM_RESTORE_JRC16:
21517 gen_restore(ctx, rt, count, 0, u);
21518 gen_compute_branch_nm(ctx, OPC_JR, 2, 31, 0, 0);
21519 break;
21520 }
21521 }
21522 break;
21523 case NM_MOVEP:
21524 case NM_MOVEPREV:
21525 check_nms(ctx);
21526 {
21527 static const int gpr2reg1[] = {4, 5, 6, 7};
21528 static const int gpr2reg2[] = {5, 6, 7, 8};
21529 int re;
21530 int rd2 = extract32(ctx->opcode, 3, 1) << 1 |
21531 extract32(ctx->opcode, 8, 1);
21532 int r1 = gpr2reg1[rd2];
21533 int r2 = gpr2reg2[rd2];
21534 int r3 = extract32(ctx->opcode, 4, 1) << 3 |
21535 extract32(ctx->opcode, 0, 3);
21536 int r4 = extract32(ctx->opcode, 9, 1) << 3 |
21537 extract32(ctx->opcode, 5, 3);
21538 TCGv t0 = tcg_temp_new();
21539 TCGv t1 = tcg_temp_new();
21540 if (op == NM_MOVEP) {
21541 rd = r1;
21542 re = r2;
21543 rs = decode_gpr_gpr4_zero(r3);
21544 rt = decode_gpr_gpr4_zero(r4);
21545 } else {
21546 rd = decode_gpr_gpr4(r3);
21547 re = decode_gpr_gpr4(r4);
21548 rs = r1;
21549 rt = r2;
21550 }
21551 gen_load_gpr(t0, rs);
21552 gen_load_gpr(t1, rt);
21553 tcg_gen_mov_tl(cpu_gpr[rd], t0);
21554 tcg_gen_mov_tl(cpu_gpr[re], t1);
21555 tcg_temp_free(t0);
21556 tcg_temp_free(t1);
21557 }
21558 break;
21559 default:
21560 return decode_nanomips_32_48_opc(env, ctx);
21561 }
21562
21563 return 2;
21564 }
21565
21566
21567 /* SmartMIPS extension to MIPS32 */
21568
21569 #if defined(TARGET_MIPS64)
21570
21571 /* MDMX extension to MIPS64 */
21572
21573 #endif
21574
21575 /* MIPSDSP functions. */
21576 static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc,
21577 int rd, int base, int offset)
21578 {
21579 TCGv t0;
21580
21581 check_dsp(ctx);
21582 t0 = tcg_temp_new();
21583
21584 if (base == 0) {
21585 gen_load_gpr(t0, offset);
21586 } else if (offset == 0) {
21587 gen_load_gpr(t0, base);
21588 } else {
21589 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]);
21590 }
21591
21592 switch (opc) {
21593 case OPC_LBUX:
21594 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
21595 gen_store_gpr(t0, rd);
21596 break;
21597 case OPC_LHX:
21598 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW);
21599 gen_store_gpr(t0, rd);
21600 break;
21601 case OPC_LWX:
21602 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
21603 gen_store_gpr(t0, rd);
21604 break;
21605 #if defined(TARGET_MIPS64)
21606 case OPC_LDX:
21607 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
21608 gen_store_gpr(t0, rd);
21609 break;
21610 #endif
21611 }
21612 tcg_temp_free(t0);
21613 }
21614
21615 static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
21616 int ret, int v1, int v2)
21617 {
21618 TCGv v1_t;
21619 TCGv v2_t;
21620
21621 if (ret == 0) {
21622 /* Treat as NOP. */
21623 return;
21624 }
21625
21626 v1_t = tcg_temp_new();
21627 v2_t = tcg_temp_new();
21628
21629 gen_load_gpr(v1_t, v1);
21630 gen_load_gpr(v2_t, v2);
21631
21632 switch (op1) {
21633 /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */
21634 case OPC_MULT_G_2E:
21635 check_dsp_r2(ctx);
21636 switch (op2) {
21637 case OPC_ADDUH_QB:
21638 gen_helper_adduh_qb(cpu_gpr[ret], v1_t, v2_t);
21639 break;
21640 case OPC_ADDUH_R_QB:
21641 gen_helper_adduh_r_qb(cpu_gpr[ret], v1_t, v2_t);
21642 break;
21643 case OPC_ADDQH_PH:
21644 gen_helper_addqh_ph(cpu_gpr[ret], v1_t, v2_t);
21645 break;
21646 case OPC_ADDQH_R_PH:
21647 gen_helper_addqh_r_ph(cpu_gpr[ret], v1_t, v2_t);
21648 break;
21649 case OPC_ADDQH_W:
21650 gen_helper_addqh_w(cpu_gpr[ret], v1_t, v2_t);
21651 break;
21652 case OPC_ADDQH_R_W:
21653 gen_helper_addqh_r_w(cpu_gpr[ret], v1_t, v2_t);
21654 break;
21655 case OPC_SUBUH_QB:
21656 gen_helper_subuh_qb(cpu_gpr[ret], v1_t, v2_t);
21657 break;
21658 case OPC_SUBUH_R_QB:
21659 gen_helper_subuh_r_qb(cpu_gpr[ret], v1_t, v2_t);
21660 break;
21661 case OPC_SUBQH_PH:
21662 gen_helper_subqh_ph(cpu_gpr[ret], v1_t, v2_t);
21663 break;
21664 case OPC_SUBQH_R_PH:
21665 gen_helper_subqh_r_ph(cpu_gpr[ret], v1_t, v2_t);
21666 break;
21667 case OPC_SUBQH_W:
21668 gen_helper_subqh_w(cpu_gpr[ret], v1_t, v2_t);
21669 break;
21670 case OPC_SUBQH_R_W:
21671 gen_helper_subqh_r_w(cpu_gpr[ret], v1_t, v2_t);
21672 break;
21673 }
21674 break;
21675 case OPC_ABSQ_S_PH_DSP:
21676 switch (op2) {
21677 case OPC_ABSQ_S_QB:
21678 check_dsp_r2(ctx);
21679 gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, cpu_env);
21680 break;
21681 case OPC_ABSQ_S_PH:
21682 check_dsp(ctx);
21683 gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, cpu_env);
21684 break;
21685 case OPC_ABSQ_S_W:
21686 check_dsp(ctx);
21687 gen_helper_absq_s_w(cpu_gpr[ret], v2_t, cpu_env);
21688 break;
21689 case OPC_PRECEQ_W_PHL:
21690 check_dsp(ctx);
21691 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFF0000);
21692 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
21693 break;
21694 case OPC_PRECEQ_W_PHR:
21695 check_dsp(ctx);
21696 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0x0000FFFF);
21697 tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 16);
21698 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
21699 break;
21700 case OPC_PRECEQU_PH_QBL:
21701 check_dsp(ctx);
21702 gen_helper_precequ_ph_qbl(cpu_gpr[ret], v2_t);
21703 break;
21704 case OPC_PRECEQU_PH_QBR:
21705 check_dsp(ctx);
21706 gen_helper_precequ_ph_qbr(cpu_gpr[ret], v2_t);
21707 break;
21708 case OPC_PRECEQU_PH_QBLA:
21709 check_dsp(ctx);
21710 gen_helper_precequ_ph_qbla(cpu_gpr[ret], v2_t);
21711 break;
21712 case OPC_PRECEQU_PH_QBRA:
21713 check_dsp(ctx);
21714 gen_helper_precequ_ph_qbra(cpu_gpr[ret], v2_t);
21715 break;
21716 case OPC_PRECEU_PH_QBL:
21717 check_dsp(ctx);
21718 gen_helper_preceu_ph_qbl(cpu_gpr[ret], v2_t);
21719 break;
21720 case OPC_PRECEU_PH_QBR:
21721 check_dsp(ctx);
21722 gen_helper_preceu_ph_qbr(cpu_gpr[ret], v2_t);
21723 break;
21724 case OPC_PRECEU_PH_QBLA:
21725 check_dsp(ctx);
21726 gen_helper_preceu_ph_qbla(cpu_gpr[ret], v2_t);
21727 break;
21728 case OPC_PRECEU_PH_QBRA:
21729 check_dsp(ctx);
21730 gen_helper_preceu_ph_qbra(cpu_gpr[ret], v2_t);
21731 break;
21732 }
21733 break;
21734 case OPC_ADDU_QB_DSP:
21735 switch (op2) {
21736 case OPC_ADDQ_PH:
21737 check_dsp(ctx);
21738 gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21739 break;
21740 case OPC_ADDQ_S_PH:
21741 check_dsp(ctx);
21742 gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21743 break;
21744 case OPC_ADDQ_S_W:
21745 check_dsp(ctx);
21746 gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21747 break;
21748 case OPC_ADDU_QB:
21749 check_dsp(ctx);
21750 gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21751 break;
21752 case OPC_ADDU_S_QB:
21753 check_dsp(ctx);
21754 gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21755 break;
21756 case OPC_ADDU_PH:
21757 check_dsp_r2(ctx);
21758 gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21759 break;
21760 case OPC_ADDU_S_PH:
21761 check_dsp_r2(ctx);
21762 gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21763 break;
21764 case OPC_SUBQ_PH:
21765 check_dsp(ctx);
21766 gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21767 break;
21768 case OPC_SUBQ_S_PH:
21769 check_dsp(ctx);
21770 gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21771 break;
21772 case OPC_SUBQ_S_W:
21773 check_dsp(ctx);
21774 gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21775 break;
21776 case OPC_SUBU_QB:
21777 check_dsp(ctx);
21778 gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21779 break;
21780 case OPC_SUBU_S_QB:
21781 check_dsp(ctx);
21782 gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21783 break;
21784 case OPC_SUBU_PH:
21785 check_dsp_r2(ctx);
21786 gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21787 break;
21788 case OPC_SUBU_S_PH:
21789 check_dsp_r2(ctx);
21790 gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21791 break;
21792 case OPC_ADDSC:
21793 check_dsp(ctx);
21794 gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21795 break;
21796 case OPC_ADDWC:
21797 check_dsp(ctx);
21798 gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21799 break;
21800 case OPC_MODSUB:
21801 check_dsp(ctx);
21802 gen_helper_modsub(cpu_gpr[ret], v1_t, v2_t);
21803 break;
21804 case OPC_RADDU_W_QB:
21805 check_dsp(ctx);
21806 gen_helper_raddu_w_qb(cpu_gpr[ret], v1_t);
21807 break;
21808 }
21809 break;
21810 case OPC_CMPU_EQ_QB_DSP:
21811 switch (op2) {
21812 case OPC_PRECR_QB_PH:
21813 check_dsp_r2(ctx);
21814 gen_helper_precr_qb_ph(cpu_gpr[ret], v1_t, v2_t);
21815 break;
21816 case OPC_PRECRQ_QB_PH:
21817 check_dsp(ctx);
21818 gen_helper_precrq_qb_ph(cpu_gpr[ret], v1_t, v2_t);
21819 break;
21820 case OPC_PRECR_SRA_PH_W:
21821 check_dsp_r2(ctx);
21822 {
21823 TCGv_i32 sa_t = tcg_const_i32(v2);
21824 gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t,
21825 cpu_gpr[ret]);
21826 tcg_temp_free_i32(sa_t);
21827 break;
21828 }
21829 case OPC_PRECR_SRA_R_PH_W:
21830 check_dsp_r2(ctx);
21831 {
21832 TCGv_i32 sa_t = tcg_const_i32(v2);
21833 gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t,
21834 cpu_gpr[ret]);
21835 tcg_temp_free_i32(sa_t);
21836 break;
21837 }
21838 case OPC_PRECRQ_PH_W:
21839 check_dsp(ctx);
21840 gen_helper_precrq_ph_w(cpu_gpr[ret], v1_t, v2_t);
21841 break;
21842 case OPC_PRECRQ_RS_PH_W:
21843 check_dsp(ctx);
21844 gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21845 break;
21846 case OPC_PRECRQU_S_QB_PH:
21847 check_dsp(ctx);
21848 gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21849 break;
21850 }
21851 break;
21852 #ifdef TARGET_MIPS64
21853 case OPC_ABSQ_S_QH_DSP:
21854 switch (op2) {
21855 case OPC_PRECEQ_L_PWL:
21856 check_dsp(ctx);
21857 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFFFFFF00000000ull);
21858 break;
21859 case OPC_PRECEQ_L_PWR:
21860 check_dsp(ctx);
21861 tcg_gen_shli_tl(cpu_gpr[ret], v2_t, 32);
21862 break;
21863 case OPC_PRECEQ_PW_QHL:
21864 check_dsp(ctx);
21865 gen_helper_preceq_pw_qhl(cpu_gpr[ret], v2_t);
21866 break;
21867 case OPC_PRECEQ_PW_QHR:
21868 check_dsp(ctx);
21869 gen_helper_preceq_pw_qhr(cpu_gpr[ret], v2_t);
21870 break;
21871 case OPC_PRECEQ_PW_QHLA:
21872 check_dsp(ctx);
21873 gen_helper_preceq_pw_qhla(cpu_gpr[ret], v2_t);
21874 break;
21875 case OPC_PRECEQ_PW_QHRA:
21876 check_dsp(ctx);
21877 gen_helper_preceq_pw_qhra(cpu_gpr[ret], v2_t);
21878 break;
21879 case OPC_PRECEQU_QH_OBL:
21880 check_dsp(ctx);
21881 gen_helper_precequ_qh_obl(cpu_gpr[ret], v2_t);
21882 break;
21883 case OPC_PRECEQU_QH_OBR:
21884 check_dsp(ctx);
21885 gen_helper_precequ_qh_obr(cpu_gpr[ret], v2_t);
21886 break;
21887 case OPC_PRECEQU_QH_OBLA:
21888 check_dsp(ctx);
21889 gen_helper_precequ_qh_obla(cpu_gpr[ret], v2_t);
21890 break;
21891 case OPC_PRECEQU_QH_OBRA:
21892 check_dsp(ctx);
21893 gen_helper_precequ_qh_obra(cpu_gpr[ret], v2_t);
21894 break;
21895 case OPC_PRECEU_QH_OBL:
21896 check_dsp(ctx);
21897 gen_helper_preceu_qh_obl(cpu_gpr[ret], v2_t);
21898 break;
21899 case OPC_PRECEU_QH_OBR:
21900 check_dsp(ctx);
21901 gen_helper_preceu_qh_obr(cpu_gpr[ret], v2_t);
21902 break;
21903 case OPC_PRECEU_QH_OBLA:
21904 check_dsp(ctx);
21905 gen_helper_preceu_qh_obla(cpu_gpr[ret], v2_t);
21906 break;
21907 case OPC_PRECEU_QH_OBRA:
21908 check_dsp(ctx);
21909 gen_helper_preceu_qh_obra(cpu_gpr[ret], v2_t);
21910 break;
21911 case OPC_ABSQ_S_OB:
21912 check_dsp_r2(ctx);
21913 gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, cpu_env);
21914 break;
21915 case OPC_ABSQ_S_PW:
21916 check_dsp(ctx);
21917 gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, cpu_env);
21918 break;
21919 case OPC_ABSQ_S_QH:
21920 check_dsp(ctx);
21921 gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, cpu_env);
21922 break;
21923 }
21924 break;
21925 case OPC_ADDU_OB_DSP:
21926 switch (op2) {
21927 case OPC_RADDU_L_OB:
21928 check_dsp(ctx);
21929 gen_helper_raddu_l_ob(cpu_gpr[ret], v1_t);
21930 break;
21931 case OPC_SUBQ_PW:
21932 check_dsp(ctx);
21933 gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21934 break;
21935 case OPC_SUBQ_S_PW:
21936 check_dsp(ctx);
21937 gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21938 break;
21939 case OPC_SUBQ_QH:
21940 check_dsp(ctx);
21941 gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21942 break;
21943 case OPC_SUBQ_S_QH:
21944 check_dsp(ctx);
21945 gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21946 break;
21947 case OPC_SUBU_OB:
21948 check_dsp(ctx);
21949 gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21950 break;
21951 case OPC_SUBU_S_OB:
21952 check_dsp(ctx);
21953 gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21954 break;
21955 case OPC_SUBU_QH:
21956 check_dsp_r2(ctx);
21957 gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21958 break;
21959 case OPC_SUBU_S_QH:
21960 check_dsp_r2(ctx);
21961 gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21962 break;
21963 case OPC_SUBUH_OB:
21964 check_dsp_r2(ctx);
21965 gen_helper_subuh_ob(cpu_gpr[ret], v1_t, v2_t);
21966 break;
21967 case OPC_SUBUH_R_OB:
21968 check_dsp_r2(ctx);
21969 gen_helper_subuh_r_ob(cpu_gpr[ret], v1_t, v2_t);
21970 break;
21971 case OPC_ADDQ_PW:
21972 check_dsp(ctx);
21973 gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21974 break;
21975 case OPC_ADDQ_S_PW:
21976 check_dsp(ctx);
21977 gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21978 break;
21979 case OPC_ADDQ_QH:
21980 check_dsp(ctx);
21981 gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21982 break;
21983 case OPC_ADDQ_S_QH:
21984 check_dsp(ctx);
21985 gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21986 break;
21987 case OPC_ADDU_OB:
21988 check_dsp(ctx);
21989 gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21990 break;
21991 case OPC_ADDU_S_OB:
21992 check_dsp(ctx);
21993 gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21994 break;
21995 case OPC_ADDU_QH:
21996 check_dsp_r2(ctx);
21997 gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
21998 break;
21999 case OPC_ADDU_S_QH:
22000 check_dsp_r2(ctx);
22001 gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22002 break;
22003 case OPC_ADDUH_OB:
22004 check_dsp_r2(ctx);
22005 gen_helper_adduh_ob(cpu_gpr[ret], v1_t, v2_t);
22006 break;
22007 case OPC_ADDUH_R_OB:
22008 check_dsp_r2(ctx);
22009 gen_helper_adduh_r_ob(cpu_gpr[ret], v1_t, v2_t);
22010 break;
22011 }
22012 break;
22013 case OPC_CMPU_EQ_OB_DSP:
22014 switch (op2) {
22015 case OPC_PRECR_OB_QH:
22016 check_dsp_r2(ctx);
22017 gen_helper_precr_ob_qh(cpu_gpr[ret], v1_t, v2_t);
22018 break;
22019 case OPC_PRECR_SRA_QH_PW:
22020 check_dsp_r2(ctx);
22021 {
22022 TCGv_i32 ret_t = tcg_const_i32(ret);
22023 gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t);
22024 tcg_temp_free_i32(ret_t);
22025 break;
22026 }
22027 case OPC_PRECR_SRA_R_QH_PW:
22028 check_dsp_r2(ctx);
22029 {
22030 TCGv_i32 sa_v = tcg_const_i32(ret);
22031 gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v);
22032 tcg_temp_free_i32(sa_v);
22033 break;
22034 }
22035 case OPC_PRECRQ_OB_QH:
22036 check_dsp(ctx);
22037 gen_helper_precrq_ob_qh(cpu_gpr[ret], v1_t, v2_t);
22038 break;
22039 case OPC_PRECRQ_PW_L:
22040 check_dsp(ctx);
22041 gen_helper_precrq_pw_l(cpu_gpr[ret], v1_t, v2_t);
22042 break;
22043 case OPC_PRECRQ_QH_PW:
22044 check_dsp(ctx);
22045 gen_helper_precrq_qh_pw(cpu_gpr[ret], v1_t, v2_t);
22046 break;
22047 case OPC_PRECRQ_RS_QH_PW:
22048 check_dsp(ctx);
22049 gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22050 break;
22051 case OPC_PRECRQU_S_OB_QH:
22052 check_dsp(ctx);
22053 gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22054 break;
22055 }
22056 break;
22057 #endif
22058 }
22059
22060 tcg_temp_free(v1_t);
22061 tcg_temp_free(v2_t);
22062 }
22063
22064 static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
22065 int ret, int v1, int v2)
22066 {
22067 uint32_t op2;
22068 TCGv t0;
22069 TCGv v1_t;
22070 TCGv v2_t;
22071
22072 if (ret == 0) {
22073 /* Treat as NOP. */
22074 return;
22075 }
22076
22077 t0 = tcg_temp_new();
22078 v1_t = tcg_temp_new();
22079 v2_t = tcg_temp_new();
22080
22081 tcg_gen_movi_tl(t0, v1);
22082 gen_load_gpr(v1_t, v1);
22083 gen_load_gpr(v2_t, v2);
22084
22085 switch (opc) {
22086 case OPC_SHLL_QB_DSP:
22087 {
22088 op2 = MASK_SHLL_QB(ctx->opcode);
22089 switch (op2) {
22090 case OPC_SHLL_QB:
22091 check_dsp(ctx);
22092 gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, cpu_env);
22093 break;
22094 case OPC_SHLLV_QB:
22095 check_dsp(ctx);
22096 gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22097 break;
22098 case OPC_SHLL_PH:
22099 check_dsp(ctx);
22100 gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, cpu_env);
22101 break;
22102 case OPC_SHLLV_PH:
22103 check_dsp(ctx);
22104 gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22105 break;
22106 case OPC_SHLL_S_PH:
22107 check_dsp(ctx);
22108 gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, cpu_env);
22109 break;
22110 case OPC_SHLLV_S_PH:
22111 check_dsp(ctx);
22112 gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22113 break;
22114 case OPC_SHLL_S_W:
22115 check_dsp(ctx);
22116 gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, cpu_env);
22117 break;
22118 case OPC_SHLLV_S_W:
22119 check_dsp(ctx);
22120 gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22121 break;
22122 case OPC_SHRL_QB:
22123 check_dsp(ctx);
22124 gen_helper_shrl_qb(cpu_gpr[ret], t0, v2_t);
22125 break;
22126 case OPC_SHRLV_QB:
22127 check_dsp(ctx);
22128 gen_helper_shrl_qb(cpu_gpr[ret], v1_t, v2_t);
22129 break;
22130 case OPC_SHRL_PH:
22131 check_dsp_r2(ctx);
22132 gen_helper_shrl_ph(cpu_gpr[ret], t0, v2_t);
22133 break;
22134 case OPC_SHRLV_PH:
22135 check_dsp_r2(ctx);
22136 gen_helper_shrl_ph(cpu_gpr[ret], v1_t, v2_t);
22137 break;
22138 case OPC_SHRA_QB:
22139 check_dsp_r2(ctx);
22140 gen_helper_shra_qb(cpu_gpr[ret], t0, v2_t);
22141 break;
22142 case OPC_SHRA_R_QB:
22143 check_dsp_r2(ctx);
22144 gen_helper_shra_r_qb(cpu_gpr[ret], t0, v2_t);
22145 break;
22146 case OPC_SHRAV_QB:
22147 check_dsp_r2(ctx);
22148 gen_helper_shra_qb(cpu_gpr[ret], v1_t, v2_t);
22149 break;
22150 case OPC_SHRAV_R_QB:
22151 check_dsp_r2(ctx);
22152 gen_helper_shra_r_qb(cpu_gpr[ret], v1_t, v2_t);
22153 break;
22154 case OPC_SHRA_PH:
22155 check_dsp(ctx);
22156 gen_helper_shra_ph(cpu_gpr[ret], t0, v2_t);
22157 break;
22158 case OPC_SHRA_R_PH:
22159 check_dsp(ctx);
22160 gen_helper_shra_r_ph(cpu_gpr[ret], t0, v2_t);
22161 break;
22162 case OPC_SHRAV_PH:
22163 check_dsp(ctx);
22164 gen_helper_shra_ph(cpu_gpr[ret], v1_t, v2_t);
22165 break;
22166 case OPC_SHRAV_R_PH:
22167 check_dsp(ctx);
22168 gen_helper_shra_r_ph(cpu_gpr[ret], v1_t, v2_t);
22169 break;
22170 case OPC_SHRA_R_W:
22171 check_dsp(ctx);
22172 gen_helper_shra_r_w(cpu_gpr[ret], t0, v2_t);
22173 break;
22174 case OPC_SHRAV_R_W:
22175 check_dsp(ctx);
22176 gen_helper_shra_r_w(cpu_gpr[ret], v1_t, v2_t);
22177 break;
22178 default: /* Invalid */
22179 MIPS_INVAL("MASK SHLL.QB");
22180 gen_reserved_instruction(ctx);
22181 break;
22182 }
22183 break;
22184 }
22185 #ifdef TARGET_MIPS64
22186 case OPC_SHLL_OB_DSP:
22187 op2 = MASK_SHLL_OB(ctx->opcode);
22188 switch (op2) {
22189 case OPC_SHLL_PW:
22190 check_dsp(ctx);
22191 gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, cpu_env);
22192 break;
22193 case OPC_SHLLV_PW:
22194 check_dsp(ctx);
22195 gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env);
22196 break;
22197 case OPC_SHLL_S_PW:
22198 check_dsp(ctx);
22199 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, cpu_env);
22200 break;
22201 case OPC_SHLLV_S_PW:
22202 check_dsp(ctx);
22203 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env);
22204 break;
22205 case OPC_SHLL_OB:
22206 check_dsp(ctx);
22207 gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, cpu_env);
22208 break;
22209 case OPC_SHLLV_OB:
22210 check_dsp(ctx);
22211 gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, cpu_env);
22212 break;
22213 case OPC_SHLL_QH:
22214 check_dsp(ctx);
22215 gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, cpu_env);
22216 break;
22217 case OPC_SHLLV_QH:
22218 check_dsp(ctx);
22219 gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env);
22220 break;
22221 case OPC_SHLL_S_QH:
22222 check_dsp(ctx);
22223 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, cpu_env);
22224 break;
22225 case OPC_SHLLV_S_QH:
22226 check_dsp(ctx);
22227 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env);
22228 break;
22229 case OPC_SHRA_OB:
22230 check_dsp_r2(ctx);
22231 gen_helper_shra_ob(cpu_gpr[ret], v2_t, t0);
22232 break;
22233 case OPC_SHRAV_OB:
22234 check_dsp_r2(ctx);
22235 gen_helper_shra_ob(cpu_gpr[ret], v2_t, v1_t);
22236 break;
22237 case OPC_SHRA_R_OB:
22238 check_dsp_r2(ctx);
22239 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, t0);
22240 break;
22241 case OPC_SHRAV_R_OB:
22242 check_dsp_r2(ctx);
22243 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, v1_t);
22244 break;
22245 case OPC_SHRA_PW:
22246 check_dsp(ctx);
22247 gen_helper_shra_pw(cpu_gpr[ret], v2_t, t0);
22248 break;
22249 case OPC_SHRAV_PW:
22250 check_dsp(ctx);
22251 gen_helper_shra_pw(cpu_gpr[ret], v2_t, v1_t);
22252 break;
22253 case OPC_SHRA_R_PW:
22254 check_dsp(ctx);
22255 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, t0);
22256 break;
22257 case OPC_SHRAV_R_PW:
22258 check_dsp(ctx);
22259 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, v1_t);
22260 break;
22261 case OPC_SHRA_QH:
22262 check_dsp(ctx);
22263 gen_helper_shra_qh(cpu_gpr[ret], v2_t, t0);
22264 break;
22265 case OPC_SHRAV_QH:
22266 check_dsp(ctx);
22267 gen_helper_shra_qh(cpu_gpr[ret], v2_t, v1_t);
22268 break;
22269 case OPC_SHRA_R_QH:
22270 check_dsp(ctx);
22271 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, t0);
22272 break;
22273 case OPC_SHRAV_R_QH:
22274 check_dsp(ctx);
22275 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, v1_t);
22276 break;
22277 case OPC_SHRL_OB:
22278 check_dsp(ctx);
22279 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, t0);
22280 break;
22281 case OPC_SHRLV_OB:
22282 check_dsp(ctx);
22283 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, v1_t);
22284 break;
22285 case OPC_SHRL_QH:
22286 check_dsp_r2(ctx);
22287 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, t0);
22288 break;
22289 case OPC_SHRLV_QH:
22290 check_dsp_r2(ctx);
22291 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, v1_t);
22292 break;
22293 default: /* Invalid */
22294 MIPS_INVAL("MASK SHLL.OB");
22295 gen_reserved_instruction(ctx);
22296 break;
22297 }
22298 break;
22299 #endif
22300 }
22301
22302 tcg_temp_free(t0);
22303 tcg_temp_free(v1_t);
22304 tcg_temp_free(v2_t);
22305 }
22306
22307 static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
22308 int ret, int v1, int v2, int check_ret)
22309 {
22310 TCGv_i32 t0;
22311 TCGv v1_t;
22312 TCGv v2_t;
22313
22314 if ((ret == 0) && (check_ret == 1)) {
22315 /* Treat as NOP. */
22316 return;
22317 }
22318
22319 t0 = tcg_temp_new_i32();
22320 v1_t = tcg_temp_new();
22321 v2_t = tcg_temp_new();
22322
22323 tcg_gen_movi_i32(t0, ret);
22324 gen_load_gpr(v1_t, v1);
22325 gen_load_gpr(v2_t, v2);
22326
22327 switch (op1) {
22328 /*
22329 * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
22330 * the same mask and op1.
22331 */
22332 case OPC_MULT_G_2E:
22333 check_dsp_r2(ctx);
22334 switch (op2) {
22335 case OPC_MUL_PH:
22336 gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22337 break;
22338 case OPC_MUL_S_PH:
22339 gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22340 break;
22341 case OPC_MULQ_S_W:
22342 gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22343 break;
22344 case OPC_MULQ_RS_W:
22345 gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22346 break;
22347 }
22348 break;
22349 case OPC_DPA_W_PH_DSP:
22350 switch (op2) {
22351 case OPC_DPAU_H_QBL:
22352 check_dsp(ctx);
22353 gen_helper_dpau_h_qbl(t0, v1_t, v2_t, cpu_env);
22354 break;
22355 case OPC_DPAU_H_QBR:
22356 check_dsp(ctx);
22357 gen_helper_dpau_h_qbr(t0, v1_t, v2_t, cpu_env);
22358 break;
22359 case OPC_DPSU_H_QBL:
22360 check_dsp(ctx);
22361 gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, cpu_env);
22362 break;
22363 case OPC_DPSU_H_QBR:
22364 check_dsp(ctx);
22365 gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, cpu_env);
22366 break;
22367 case OPC_DPA_W_PH:
22368 check_dsp_r2(ctx);
22369 gen_helper_dpa_w_ph(t0, v1_t, v2_t, cpu_env);
22370 break;
22371 case OPC_DPAX_W_PH:
22372 check_dsp_r2(ctx);
22373 gen_helper_dpax_w_ph(t0, v1_t, v2_t, cpu_env);
22374 break;
22375 case OPC_DPAQ_S_W_PH:
22376 check_dsp(ctx);
22377 gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, cpu_env);
22378 break;
22379 case OPC_DPAQX_S_W_PH:
22380 check_dsp_r2(ctx);
22381 gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, cpu_env);
22382 break;
22383 case OPC_DPAQX_SA_W_PH:
22384 check_dsp_r2(ctx);
22385 gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, cpu_env);
22386 break;
22387 case OPC_DPS_W_PH:
22388 check_dsp_r2(ctx);
22389 gen_helper_dps_w_ph(t0, v1_t, v2_t, cpu_env);
22390 break;
22391 case OPC_DPSX_W_PH:
22392 check_dsp_r2(ctx);
22393 gen_helper_dpsx_w_ph(t0, v1_t, v2_t, cpu_env);
22394 break;
22395 case OPC_DPSQ_S_W_PH:
22396 check_dsp(ctx);
22397 gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, cpu_env);
22398 break;
22399 case OPC_DPSQX_S_W_PH:
22400 check_dsp_r2(ctx);
22401 gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, cpu_env);
22402 break;
22403 case OPC_DPSQX_SA_W_PH:
22404 check_dsp_r2(ctx);
22405 gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, cpu_env);
22406 break;
22407 case OPC_MULSAQ_S_W_PH:
22408 check_dsp(ctx);
22409 gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, cpu_env);
22410 break;
22411 case OPC_DPAQ_SA_L_W:
22412 check_dsp(ctx);
22413 gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, cpu_env);
22414 break;
22415 case OPC_DPSQ_SA_L_W:
22416 check_dsp(ctx);
22417 gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, cpu_env);
22418 break;
22419 case OPC_MAQ_S_W_PHL:
22420 check_dsp(ctx);
22421 gen_helper_maq_s_w_phl(t0, v1_t, v2_t, cpu_env);
22422 break;
22423 case OPC_MAQ_S_W_PHR:
22424 check_dsp(ctx);
22425 gen_helper_maq_s_w_phr(t0, v1_t, v2_t, cpu_env);
22426 break;
22427 case OPC_MAQ_SA_W_PHL:
22428 check_dsp(ctx);
22429 gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, cpu_env);
22430 break;
22431 case OPC_MAQ_SA_W_PHR:
22432 check_dsp(ctx);
22433 gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, cpu_env);
22434 break;
22435 case OPC_MULSA_W_PH:
22436 check_dsp_r2(ctx);
22437 gen_helper_mulsa_w_ph(t0, v1_t, v2_t, cpu_env);
22438 break;
22439 }
22440 break;
22441 #ifdef TARGET_MIPS64
22442 case OPC_DPAQ_W_QH_DSP:
22443 {
22444 int ac = ret & 0x03;
22445 tcg_gen_movi_i32(t0, ac);
22446
22447 switch (op2) {
22448 case OPC_DMADD:
22449 check_dsp(ctx);
22450 gen_helper_dmadd(v1_t, v2_t, t0, cpu_env);
22451 break;
22452 case OPC_DMADDU:
22453 check_dsp(ctx);
22454 gen_helper_dmaddu(v1_t, v2_t, t0, cpu_env);
22455 break;
22456 case OPC_DMSUB:
22457 check_dsp(ctx);
22458 gen_helper_dmsub(v1_t, v2_t, t0, cpu_env);
22459 break;
22460 case OPC_DMSUBU:
22461 check_dsp(ctx);
22462 gen_helper_dmsubu(v1_t, v2_t, t0, cpu_env);
22463 break;
22464 case OPC_DPA_W_QH:
22465 check_dsp_r2(ctx);
22466 gen_helper_dpa_w_qh(v1_t, v2_t, t0, cpu_env);
22467 break;
22468 case OPC_DPAQ_S_W_QH:
22469 check_dsp(ctx);
22470 gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, cpu_env);
22471 break;
22472 case OPC_DPAQ_SA_L_PW:
22473 check_dsp(ctx);
22474 gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, cpu_env);
22475 break;
22476 case OPC_DPAU_H_OBL:
22477 check_dsp(ctx);
22478 gen_helper_dpau_h_obl(v1_t, v2_t, t0, cpu_env);
22479 break;
22480 case OPC_DPAU_H_OBR:
22481 check_dsp(ctx);
22482 gen_helper_dpau_h_obr(v1_t, v2_t, t0, cpu_env);
22483 break;
22484 case OPC_DPS_W_QH:
22485 check_dsp_r2(ctx);
22486 gen_helper_dps_w_qh(v1_t, v2_t, t0, cpu_env);
22487 break;
22488 case OPC_DPSQ_S_W_QH:
22489 check_dsp(ctx);
22490 gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, cpu_env);
22491 break;
22492 case OPC_DPSQ_SA_L_PW:
22493 check_dsp(ctx);
22494 gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, cpu_env);
22495 break;
22496 case OPC_DPSU_H_OBL:
22497 check_dsp(ctx);
22498 gen_helper_dpsu_h_obl(v1_t, v2_t, t0, cpu_env);
22499 break;
22500 case OPC_DPSU_H_OBR:
22501 check_dsp(ctx);
22502 gen_helper_dpsu_h_obr(v1_t, v2_t, t0, cpu_env);
22503 break;
22504 case OPC_MAQ_S_L_PWL:
22505 check_dsp(ctx);
22506 gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, cpu_env);
22507 break;
22508 case OPC_MAQ_S_L_PWR:
22509 check_dsp(ctx);
22510 gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, cpu_env);
22511 break;
22512 case OPC_MAQ_S_W_QHLL:
22513 check_dsp(ctx);
22514 gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, cpu_env);
22515 break;
22516 case OPC_MAQ_SA_W_QHLL:
22517 check_dsp(ctx);
22518 gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, cpu_env);
22519 break;
22520 case OPC_MAQ_S_W_QHLR:
22521 check_dsp(ctx);
22522 gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, cpu_env);
22523 break;
22524 case OPC_MAQ_SA_W_QHLR:
22525 check_dsp(ctx);
22526 gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, cpu_env);
22527 break;
22528 case OPC_MAQ_S_W_QHRL:
22529 check_dsp(ctx);
22530 gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, cpu_env);
22531 break;
22532 case OPC_MAQ_SA_W_QHRL:
22533 check_dsp(ctx);
22534 gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, cpu_env);
22535 break;
22536 case OPC_MAQ_S_W_QHRR:
22537 check_dsp(ctx);
22538 gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, cpu_env);
22539 break;
22540 case OPC_MAQ_SA_W_QHRR:
22541 check_dsp(ctx);
22542 gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, cpu_env);
22543 break;
22544 case OPC_MULSAQ_S_L_PW:
22545 check_dsp(ctx);
22546 gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, cpu_env);
22547 break;
22548 case OPC_MULSAQ_S_W_QH:
22549 check_dsp(ctx);
22550 gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, cpu_env);
22551 break;
22552 }
22553 }
22554 break;
22555 #endif
22556 case OPC_ADDU_QB_DSP:
22557 switch (op2) {
22558 case OPC_MULEU_S_PH_QBL:
22559 check_dsp(ctx);
22560 gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22561 break;
22562 case OPC_MULEU_S_PH_QBR:
22563 check_dsp(ctx);
22564 gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22565 break;
22566 case OPC_MULQ_RS_PH:
22567 check_dsp(ctx);
22568 gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22569 break;
22570 case OPC_MULEQ_S_W_PHL:
22571 check_dsp(ctx);
22572 gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22573 break;
22574 case OPC_MULEQ_S_W_PHR:
22575 check_dsp(ctx);
22576 gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22577 break;
22578 case OPC_MULQ_S_PH:
22579 check_dsp_r2(ctx);
22580 gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22581 break;
22582 }
22583 break;
22584 #ifdef TARGET_MIPS64
22585 case OPC_ADDU_OB_DSP:
22586 switch (op2) {
22587 case OPC_MULEQ_S_PW_QHL:
22588 check_dsp(ctx);
22589 gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22590 break;
22591 case OPC_MULEQ_S_PW_QHR:
22592 check_dsp(ctx);
22593 gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22594 break;
22595 case OPC_MULEU_S_QH_OBL:
22596 check_dsp(ctx);
22597 gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22598 break;
22599 case OPC_MULEU_S_QH_OBR:
22600 check_dsp(ctx);
22601 gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22602 break;
22603 case OPC_MULQ_RS_QH:
22604 check_dsp(ctx);
22605 gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22606 break;
22607 }
22608 break;
22609 #endif
22610 }
22611
22612 tcg_temp_free_i32(t0);
22613 tcg_temp_free(v1_t);
22614 tcg_temp_free(v2_t);
22615 }
22616
22617 static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
22618 int ret, int val)
22619 {
22620 int16_t imm;
22621 TCGv t0;
22622 TCGv val_t;
22623
22624 if (ret == 0) {
22625 /* Treat as NOP. */
22626 return;
22627 }
22628
22629 t0 = tcg_temp_new();
22630 val_t = tcg_temp_new();
22631 gen_load_gpr(val_t, val);
22632
22633 switch (op1) {
22634 case OPC_ABSQ_S_PH_DSP:
22635 switch (op2) {
22636 case OPC_BITREV:
22637 check_dsp(ctx);
22638 gen_helper_bitrev(cpu_gpr[ret], val_t);
22639 break;
22640 case OPC_REPL_QB:
22641 check_dsp(ctx);
22642 {
22643 target_long result;
22644 imm = (ctx->opcode >> 16) & 0xFF;
22645 result = (uint32_t)imm << 24 |
22646 (uint32_t)imm << 16 |
22647 (uint32_t)imm << 8 |
22648 (uint32_t)imm;
22649 result = (int32_t)result;
22650 tcg_gen_movi_tl(cpu_gpr[ret], result);
22651 }
22652 break;
22653 case OPC_REPLV_QB:
22654 check_dsp(ctx);
22655 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
22656 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
22657 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
22658 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
22659 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
22660 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
22661 break;
22662 case OPC_REPL_PH:
22663 check_dsp(ctx);
22664 {
22665 imm = (ctx->opcode >> 16) & 0x03FF;
22666 imm = (int16_t)(imm << 6) >> 6;
22667 tcg_gen_movi_tl(cpu_gpr[ret], \
22668 (target_long)((int32_t)imm << 16 | \
22669 (uint16_t)imm));
22670 }
22671 break;
22672 case OPC_REPLV_PH:
22673 check_dsp(ctx);
22674 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
22675 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
22676 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
22677 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
22678 break;
22679 }
22680 break;
22681 #ifdef TARGET_MIPS64
22682 case OPC_ABSQ_S_QH_DSP:
22683 switch (op2) {
22684 case OPC_REPL_OB:
22685 check_dsp(ctx);
22686 {
22687 target_long temp;
22688
22689 imm = (ctx->opcode >> 16) & 0xFF;
22690 temp = ((uint64_t)imm << 8) | (uint64_t)imm;
22691 temp = (temp << 16) | temp;
22692 temp = (temp << 32) | temp;
22693 tcg_gen_movi_tl(cpu_gpr[ret], temp);
22694 break;
22695 }
22696 case OPC_REPL_PW:
22697 check_dsp(ctx);
22698 {
22699 target_long temp;
22700
22701 imm = (ctx->opcode >> 16) & 0x03FF;
22702 imm = (int16_t)(imm << 6) >> 6;
22703 temp = ((target_long)imm << 32) \
22704 | ((target_long)imm & 0xFFFFFFFF);
22705 tcg_gen_movi_tl(cpu_gpr[ret], temp);
22706 break;
22707 }
22708 case OPC_REPL_QH:
22709 check_dsp(ctx);
22710 {
22711 target_long temp;
22712
22713 imm = (ctx->opcode >> 16) & 0x03FF;
22714 imm = (int16_t)(imm << 6) >> 6;
22715
22716 temp = ((uint64_t)(uint16_t)imm << 48) |
22717 ((uint64_t)(uint16_t)imm << 32) |
22718 ((uint64_t)(uint16_t)imm << 16) |
22719 (uint64_t)(uint16_t)imm;
22720 tcg_gen_movi_tl(cpu_gpr[ret], temp);
22721 break;
22722 }
22723 case OPC_REPLV_OB:
22724 check_dsp(ctx);
22725 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
22726 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
22727 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
22728 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
22729 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
22730 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
22731 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
22732 break;
22733 case OPC_REPLV_PW:
22734 check_dsp(ctx);
22735 tcg_gen_ext32u_i64(cpu_gpr[ret], val_t);
22736 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
22737 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
22738 break;
22739 case OPC_REPLV_QH:
22740 check_dsp(ctx);
22741 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
22742 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
22743 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
22744 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
22745 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
22746 break;
22747 }
22748 break;
22749 #endif
22750 }
22751 tcg_temp_free(t0);
22752 tcg_temp_free(val_t);
22753 }
22754
22755 static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
22756 uint32_t op1, uint32_t op2,
22757 int ret, int v1, int v2, int check_ret)
22758 {
22759 TCGv t1;
22760 TCGv v1_t;
22761 TCGv v2_t;
22762
22763 if ((ret == 0) && (check_ret == 1)) {
22764 /* Treat as NOP. */
22765 return;
22766 }
22767
22768 t1 = tcg_temp_new();
22769 v1_t = tcg_temp_new();
22770 v2_t = tcg_temp_new();
22771
22772 gen_load_gpr(v1_t, v1);
22773 gen_load_gpr(v2_t, v2);
22774
22775 switch (op1) {
22776 case OPC_CMPU_EQ_QB_DSP:
22777 switch (op2) {
22778 case OPC_CMPU_EQ_QB:
22779 check_dsp(ctx);
22780 gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env);
22781 break;
22782 case OPC_CMPU_LT_QB:
22783 check_dsp(ctx);
22784 gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env);
22785 break;
22786 case OPC_CMPU_LE_QB:
22787 check_dsp(ctx);
22788 gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env);
22789 break;
22790 case OPC_CMPGU_EQ_QB:
22791 check_dsp(ctx);
22792 gen_helper_cmpgu_eq_qb(cpu_gpr[ret], v1_t, v2_t);
22793 break;
22794 case OPC_CMPGU_LT_QB:
22795 check_dsp(ctx);
22796 gen_helper_cmpgu_lt_qb(cpu_gpr[ret], v1_t, v2_t);
22797 break;
22798 case OPC_CMPGU_LE_QB:
22799 check_dsp(ctx);
22800 gen_helper_cmpgu_le_qb(cpu_gpr[ret], v1_t, v2_t);
22801 break;
22802 case OPC_CMPGDU_EQ_QB:
22803 check_dsp_r2(ctx);
22804 gen_helper_cmpgu_eq_qb(t1, v1_t, v2_t);
22805 tcg_gen_mov_tl(cpu_gpr[ret], t1);
22806 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
22807 tcg_gen_shli_tl(t1, t1, 24);
22808 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
22809 break;
22810 case OPC_CMPGDU_LT_QB:
22811 check_dsp_r2(ctx);
22812 gen_helper_cmpgu_lt_qb(t1, v1_t, v2_t);
22813 tcg_gen_mov_tl(cpu_gpr[ret], t1);
22814 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
22815 tcg_gen_shli_tl(t1, t1, 24);
22816 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
22817 break;
22818 case OPC_CMPGDU_LE_QB:
22819 check_dsp_r2(ctx);
22820 gen_helper_cmpgu_le_qb(t1, v1_t, v2_t);
22821 tcg_gen_mov_tl(cpu_gpr[ret], t1);
22822 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
22823 tcg_gen_shli_tl(t1, t1, 24);
22824 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
22825 break;
22826 case OPC_CMP_EQ_PH:
22827 check_dsp(ctx);
22828 gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env);
22829 break;
22830 case OPC_CMP_LT_PH:
22831 check_dsp(ctx);
22832 gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env);
22833 break;
22834 case OPC_CMP_LE_PH:
22835 check_dsp(ctx);
22836 gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env);
22837 break;
22838 case OPC_PICK_QB:
22839 check_dsp(ctx);
22840 gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22841 break;
22842 case OPC_PICK_PH:
22843 check_dsp(ctx);
22844 gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22845 break;
22846 case OPC_PACKRL_PH:
22847 check_dsp(ctx);
22848 gen_helper_packrl_ph(cpu_gpr[ret], v1_t, v2_t);
22849 break;
22850 }
22851 break;
22852 #ifdef TARGET_MIPS64
22853 case OPC_CMPU_EQ_OB_DSP:
22854 switch (op2) {
22855 case OPC_CMP_EQ_PW:
22856 check_dsp(ctx);
22857 gen_helper_cmp_eq_pw(v1_t, v2_t, cpu_env);
22858 break;
22859 case OPC_CMP_LT_PW:
22860 check_dsp(ctx);
22861 gen_helper_cmp_lt_pw(v1_t, v2_t, cpu_env);
22862 break;
22863 case OPC_CMP_LE_PW:
22864 check_dsp(ctx);
22865 gen_helper_cmp_le_pw(v1_t, v2_t, cpu_env);
22866 break;
22867 case OPC_CMP_EQ_QH:
22868 check_dsp(ctx);
22869 gen_helper_cmp_eq_qh(v1_t, v2_t, cpu_env);
22870 break;
22871 case OPC_CMP_LT_QH:
22872 check_dsp(ctx);
22873 gen_helper_cmp_lt_qh(v1_t, v2_t, cpu_env);
22874 break;
22875 case OPC_CMP_LE_QH:
22876 check_dsp(ctx);
22877 gen_helper_cmp_le_qh(v1_t, v2_t, cpu_env);
22878 break;
22879 case OPC_CMPGDU_EQ_OB:
22880 check_dsp_r2(ctx);
22881 gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22882 break;
22883 case OPC_CMPGDU_LT_OB:
22884 check_dsp_r2(ctx);
22885 gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22886 break;
22887 case OPC_CMPGDU_LE_OB:
22888 check_dsp_r2(ctx);
22889 gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22890 break;
22891 case OPC_CMPGU_EQ_OB:
22892 check_dsp(ctx);
22893 gen_helper_cmpgu_eq_ob(cpu_gpr[ret], v1_t, v2_t);
22894 break;
22895 case OPC_CMPGU_LT_OB:
22896 check_dsp(ctx);
22897 gen_helper_cmpgu_lt_ob(cpu_gpr[ret], v1_t, v2_t);
22898 break;
22899 case OPC_CMPGU_LE_OB:
22900 check_dsp(ctx);
22901 gen_helper_cmpgu_le_ob(cpu_gpr[ret], v1_t, v2_t);
22902 break;
22903 case OPC_CMPU_EQ_OB:
22904 check_dsp(ctx);
22905 gen_helper_cmpu_eq_ob(v1_t, v2_t, cpu_env);
22906 break;
22907 case OPC_CMPU_LT_OB:
22908 check_dsp(ctx);
22909 gen_helper_cmpu_lt_ob(v1_t, v2_t, cpu_env);
22910 break;
22911 case OPC_CMPU_LE_OB:
22912 check_dsp(ctx);
22913 gen_helper_cmpu_le_ob(v1_t, v2_t, cpu_env);
22914 break;
22915 case OPC_PACKRL_PW:
22916 check_dsp(ctx);
22917 gen_helper_packrl_pw(cpu_gpr[ret], v1_t, v2_t);
22918 break;
22919 case OPC_PICK_OB:
22920 check_dsp(ctx);
22921 gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22922 break;
22923 case OPC_PICK_PW:
22924 check_dsp(ctx);
22925 gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22926 break;
22927 case OPC_PICK_QH:
22928 check_dsp(ctx);
22929 gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
22930 break;
22931 }
22932 break;
22933 #endif
22934 }
22935
22936 tcg_temp_free(t1);
22937 tcg_temp_free(v1_t);
22938 tcg_temp_free(v2_t);
22939 }
22940
22941 static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx,
22942 uint32_t op1, int rt, int rs, int sa)
22943 {
22944 TCGv t0;
22945
22946 check_dsp_r2(ctx);
22947
22948 if (rt == 0) {
22949 /* Treat as NOP. */
22950 return;
22951 }
22952
22953 t0 = tcg_temp_new();
22954 gen_load_gpr(t0, rs);
22955
22956 switch (op1) {
22957 case OPC_APPEND_DSP:
22958 switch (MASK_APPEND(ctx->opcode)) {
22959 case OPC_APPEND:
22960 if (sa != 0) {
22961 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 32 - sa);
22962 }
22963 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
22964 break;
22965 case OPC_PREPEND:
22966 if (sa != 0) {
22967 tcg_gen_ext32u_tl(cpu_gpr[rt], cpu_gpr[rt]);
22968 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa);
22969 tcg_gen_shli_tl(t0, t0, 32 - sa);
22970 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
22971 }
22972 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
22973 break;
22974 case OPC_BALIGN:
22975 sa &= 3;
22976 if (sa != 0 && sa != 2) {
22977 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa);
22978 tcg_gen_ext32u_tl(t0, t0);
22979 tcg_gen_shri_tl(t0, t0, 8 * (4 - sa));
22980 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
22981 }
22982 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
22983 break;
22984 default: /* Invalid */
22985 MIPS_INVAL("MASK APPEND");
22986 gen_reserved_instruction(ctx);
22987 break;
22988 }
22989 break;
22990 #ifdef TARGET_MIPS64
22991 case OPC_DAPPEND_DSP:
22992 switch (MASK_DAPPEND(ctx->opcode)) {
22993 case OPC_DAPPEND:
22994 if (sa != 0) {
22995 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 64 - sa);
22996 }
22997 break;
22998 case OPC_PREPENDD:
22999 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], 0x20 | sa);
23000 tcg_gen_shli_tl(t0, t0, 64 - (0x20 | sa));
23001 tcg_gen_or_tl(cpu_gpr[rt], t0, t0);
23002 break;
23003 case OPC_PREPENDW:
23004 if (sa != 0) {
23005 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa);
23006 tcg_gen_shli_tl(t0, t0, 64 - sa);
23007 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
23008 }
23009 break;
23010 case OPC_DBALIGN:
23011 sa &= 7;
23012 if (sa != 0 && sa != 2 && sa != 4) {
23013 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa);
23014 tcg_gen_shri_tl(t0, t0, 8 * (8 - sa));
23015 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
23016 }
23017 break;
23018 default: /* Invalid */
23019 MIPS_INVAL("MASK DAPPEND");
23020 gen_reserved_instruction(ctx);
23021 break;
23022 }
23023 break;
23024 #endif
23025 }
23026 tcg_temp_free(t0);
23027 }
23028
23029 static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
23030 int ret, int v1, int v2, int check_ret)
23031
23032 {
23033 TCGv t0;
23034 TCGv t1;
23035 TCGv v1_t;
23036 TCGv v2_t;
23037 int16_t imm;
23038
23039 if ((ret == 0) && (check_ret == 1)) {
23040 /* Treat as NOP. */
23041 return;
23042 }
23043
23044 t0 = tcg_temp_new();
23045 t1 = tcg_temp_new();
23046 v1_t = tcg_temp_new();
23047 v2_t = tcg_temp_new();
23048
23049 gen_load_gpr(v1_t, v1);
23050 gen_load_gpr(v2_t, v2);
23051
23052 switch (op1) {
23053 case OPC_EXTR_W_DSP:
23054 check_dsp(ctx);
23055 switch (op2) {
23056 case OPC_EXTR_W:
23057 tcg_gen_movi_tl(t0, v2);
23058 tcg_gen_movi_tl(t1, v1);
23059 gen_helper_extr_w(cpu_gpr[ret], t0, t1, cpu_env);
23060 break;
23061 case OPC_EXTR_R_W:
23062 tcg_gen_movi_tl(t0, v2);
23063 tcg_gen_movi_tl(t1, v1);
23064 gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, cpu_env);
23065 break;
23066 case OPC_EXTR_RS_W:
23067 tcg_gen_movi_tl(t0, v2);
23068 tcg_gen_movi_tl(t1, v1);
23069 gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, cpu_env);
23070 break;
23071 case OPC_EXTR_S_H:
23072 tcg_gen_movi_tl(t0, v2);
23073 tcg_gen_movi_tl(t1, v1);
23074 gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
23075 break;
23076 case OPC_EXTRV_S_H:
23077 tcg_gen_movi_tl(t0, v2);
23078 gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env);
23079 break;
23080 case OPC_EXTRV_W:
23081 tcg_gen_movi_tl(t0, v2);
23082 gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, cpu_env);
23083 break;
23084 case OPC_EXTRV_R_W:
23085 tcg_gen_movi_tl(t0, v2);
23086 gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env);
23087 break;
23088 case OPC_EXTRV_RS_W:
23089 tcg_gen_movi_tl(t0, v2);
23090 gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env);
23091 break;
23092 case OPC_EXTP:
23093 tcg_gen_movi_tl(t0, v2);
23094 tcg_gen_movi_tl(t1, v1);
23095 gen_helper_extp(cpu_gpr[ret], t0, t1, cpu_env);
23096 break;
23097 case OPC_EXTPV:
23098 tcg_gen_movi_tl(t0, v2);
23099 gen_helper_extp(cpu_gpr[ret], t0, v1_t, cpu_env);
23100 break;
23101 case OPC_EXTPDP:
23102 tcg_gen_movi_tl(t0, v2);
23103 tcg_gen_movi_tl(t1, v1);
23104 gen_helper_extpdp(cpu_gpr[ret], t0, t1, cpu_env);
23105 break;
23106 case OPC_EXTPDPV:
23107 tcg_gen_movi_tl(t0, v2);
23108 gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, cpu_env);
23109 break;
23110 case OPC_SHILO:
23111 imm = (ctx->opcode >> 20) & 0x3F;
23112 tcg_gen_movi_tl(t0, ret);
23113 tcg_gen_movi_tl(t1, imm);
23114 gen_helper_shilo(t0, t1, cpu_env);
23115 break;
23116 case OPC_SHILOV:
23117 tcg_gen_movi_tl(t0, ret);
23118 gen_helper_shilo(t0, v1_t, cpu_env);
23119 break;
23120 case OPC_MTHLIP:
23121 tcg_gen_movi_tl(t0, ret);
23122 gen_helper_mthlip(t0, v1_t, cpu_env);
23123 break;
23124 case OPC_WRDSP:
23125 imm = (ctx->opcode >> 11) & 0x3FF;
23126 tcg_gen_movi_tl(t0, imm);
23127 gen_helper_wrdsp(v1_t, t0, cpu_env);
23128 break;
23129 case OPC_RDDSP:
23130 imm = (ctx->opcode >> 16) & 0x03FF;
23131 tcg_gen_movi_tl(t0, imm);
23132 gen_helper_rddsp(cpu_gpr[ret], t0, cpu_env);
23133 break;
23134 }
23135 break;
23136 #ifdef TARGET_MIPS64
23137 case OPC_DEXTR_W_DSP:
23138 check_dsp(ctx);
23139 switch (op2) {
23140 case OPC_DMTHLIP:
23141 tcg_gen_movi_tl(t0, ret);
23142 gen_helper_dmthlip(v1_t, t0, cpu_env);
23143 break;
23144 case OPC_DSHILO:
23145 {
23146 int shift = (ctx->opcode >> 19) & 0x7F;
23147 int ac = (ctx->opcode >> 11) & 0x03;
23148 tcg_gen_movi_tl(t0, shift);
23149 tcg_gen_movi_tl(t1, ac);
23150 gen_helper_dshilo(t0, t1, cpu_env);
23151 break;
23152 }
23153 case OPC_DSHILOV:
23154 {
23155 int ac = (ctx->opcode >> 11) & 0x03;
23156 tcg_gen_movi_tl(t0, ac);
23157 gen_helper_dshilo(v1_t, t0, cpu_env);
23158 break;
23159 }
23160 case OPC_DEXTP:
23161 tcg_gen_movi_tl(t0, v2);
23162 tcg_gen_movi_tl(t1, v1);
23163
23164 gen_helper_dextp(cpu_gpr[ret], t0, t1, cpu_env);
23165 break;
23166 case OPC_DEXTPV:
23167 tcg_gen_movi_tl(t0, v2);
23168 gen_helper_dextp(cpu_gpr[ret], t0, v1_t, cpu_env);
23169 break;
23170 case OPC_DEXTPDP:
23171 tcg_gen_movi_tl(t0, v2);
23172 tcg_gen_movi_tl(t1, v1);
23173 gen_helper_dextpdp(cpu_gpr[ret], t0, t1, cpu_env);
23174 break;
23175 case OPC_DEXTPDPV:
23176 tcg_gen_movi_tl(t0, v2);
23177 gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, cpu_env);
23178 break;
23179 case OPC_DEXTR_L:
23180 tcg_gen_movi_tl(t0, v2);
23181 tcg_gen_movi_tl(t1, v1);
23182 gen_helper_dextr_l(cpu_gpr[ret], t0, t1, cpu_env);
23183 break;
23184 case OPC_DEXTR_R_L:
23185 tcg_gen_movi_tl(t0, v2);
23186 tcg_gen_movi_tl(t1, v1);
23187 gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, cpu_env);
23188 break;
23189 case OPC_DEXTR_RS_L:
23190 tcg_gen_movi_tl(t0, v2);
23191 tcg_gen_movi_tl(t1, v1);
23192 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, cpu_env);
23193 break;
23194 case OPC_DEXTR_W:
23195 tcg_gen_movi_tl(t0, v2);
23196 tcg_gen_movi_tl(t1, v1);
23197 gen_helper_dextr_w(cpu_gpr[ret], t0, t1, cpu_env);
23198 break;
23199 case OPC_DEXTR_R_W:
23200 tcg_gen_movi_tl(t0, v2);
23201 tcg_gen_movi_tl(t1, v1);
23202 gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, cpu_env);
23203 break;
23204 case OPC_DEXTR_RS_W:
23205 tcg_gen_movi_tl(t0, v2);
23206 tcg_gen_movi_tl(t1, v1);
23207 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, cpu_env);
23208 break;
23209 case OPC_DEXTR_S_H:
23210 tcg_gen_movi_tl(t0, v2);
23211 tcg_gen_movi_tl(t1, v1);
23212 gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
23213 break;
23214 case OPC_DEXTRV_S_H:
23215 tcg_gen_movi_tl(t0, v2);
23216 tcg_gen_movi_tl(t1, v1);
23217 gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
23218 break;
23219 case OPC_DEXTRV_L:
23220 tcg_gen_movi_tl(t0, v2);
23221 gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, cpu_env);
23222 break;
23223 case OPC_DEXTRV_R_L:
23224 tcg_gen_movi_tl(t0, v2);
23225 gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, cpu_env);
23226 break;
23227 case OPC_DEXTRV_RS_L:
23228 tcg_gen_movi_tl(t0, v2);
23229 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, cpu_env);
23230 break;
23231 case OPC_DEXTRV_W:
23232 tcg_gen_movi_tl(t0, v2);
23233 gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, cpu_env);
23234 break;
23235 case OPC_DEXTRV_R_W:
23236 tcg_gen_movi_tl(t0, v2);
23237 gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env);
23238 break;
23239 case OPC_DEXTRV_RS_W:
23240 tcg_gen_movi_tl(t0, v2);
23241 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env);
23242 break;
23243 }
23244 break;
23245 #endif
23246 }
23247
23248 tcg_temp_free(t0);
23249 tcg_temp_free(t1);
23250 tcg_temp_free(v1_t);
23251 tcg_temp_free(v2_t);
23252 }
23253
23254 /* End MIPSDSP functions. */
23255
23256 static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
23257 {
23258 int rs, rt, rd, sa;
23259 uint32_t op1, op2;
23260
23261 rs = (ctx->opcode >> 21) & 0x1f;
23262 rt = (ctx->opcode >> 16) & 0x1f;
23263 rd = (ctx->opcode >> 11) & 0x1f;
23264 sa = (ctx->opcode >> 6) & 0x1f;
23265
23266 op1 = MASK_SPECIAL(ctx->opcode);
23267 switch (op1) {
23268 case OPC_MULT:
23269 case OPC_MULTU:
23270 case OPC_DIV:
23271 case OPC_DIVU:
23272 op2 = MASK_R6_MULDIV(ctx->opcode);
23273 switch (op2) {
23274 case R6_OPC_MUL:
23275 case R6_OPC_MUH:
23276 case R6_OPC_MULU:
23277 case R6_OPC_MUHU:
23278 case R6_OPC_DIV:
23279 case R6_OPC_MOD:
23280 case R6_OPC_DIVU:
23281 case R6_OPC_MODU:
23282 gen_r6_muldiv(ctx, op2, rd, rs, rt);
23283 break;
23284 default:
23285 MIPS_INVAL("special_r6 muldiv");
23286 gen_reserved_instruction(ctx);
23287 break;
23288 }
23289 break;
23290 case OPC_SELEQZ:
23291 case OPC_SELNEZ:
23292 gen_cond_move(ctx, op1, rd, rs, rt);
23293 break;
23294 case R6_OPC_CLO:
23295 case R6_OPC_CLZ:
23296 if (rt == 0 && sa == 1) {
23297 /*
23298 * Major opcode and function field is shared with preR6 MFHI/MTHI.
23299 * We need additionally to check other fields.
23300 */
23301 gen_cl(ctx, op1, rd, rs);
23302 } else {
23303 gen_reserved_instruction(ctx);
23304 }
23305 break;
23306 case R6_OPC_SDBBP:
23307 if (is_uhi(extract32(ctx->opcode, 6, 20))) {
23308 gen_helper_do_semihosting(cpu_env);
23309 } else {
23310 if (ctx->hflags & MIPS_HFLAG_SBRI) {
23311 gen_reserved_instruction(ctx);
23312 } else {
23313 generate_exception_end(ctx, EXCP_DBp);
23314 }
23315 }
23316 break;
23317 #if defined(TARGET_MIPS64)
23318 case R6_OPC_DCLO:
23319 case R6_OPC_DCLZ:
23320 if (rt == 0 && sa == 1) {
23321 /*
23322 * Major opcode and function field is shared with preR6 MFHI/MTHI.
23323 * We need additionally to check other fields.
23324 */
23325 check_mips_64(ctx);
23326 gen_cl(ctx, op1, rd, rs);
23327 } else {
23328 gen_reserved_instruction(ctx);
23329 }
23330 break;
23331 case OPC_DMULT:
23332 case OPC_DMULTU:
23333 case OPC_DDIV:
23334 case OPC_DDIVU:
23335
23336 op2 = MASK_R6_MULDIV(ctx->opcode);
23337 switch (op2) {
23338 case R6_OPC_DMUL:
23339 case R6_OPC_DMUH:
23340 case R6_OPC_DMULU:
23341 case R6_OPC_DMUHU:
23342 case R6_OPC_DDIV:
23343 case R6_OPC_DMOD:
23344 case R6_OPC_DDIVU:
23345 case R6_OPC_DMODU:
23346 check_mips_64(ctx);
23347 gen_r6_muldiv(ctx, op2, rd, rs, rt);
23348 break;
23349 default:
23350 MIPS_INVAL("special_r6 muldiv");
23351 gen_reserved_instruction(ctx);
23352 break;
23353 }
23354 break;
23355 #endif
23356 default: /* Invalid */
23357 MIPS_INVAL("special_r6");
23358 gen_reserved_instruction(ctx);
23359 break;
23360 }
23361 }
23362
23363 static void decode_opc_special_tx79(CPUMIPSState *env, DisasContext *ctx)
23364 {
23365 int rs = extract32(ctx->opcode, 21, 5);
23366 int rt = extract32(ctx->opcode, 16, 5);
23367 int rd = extract32(ctx->opcode, 11, 5);
23368 uint32_t op1 = MASK_SPECIAL(ctx->opcode);
23369
23370 switch (op1) {
23371 case OPC_MOVN: /* Conditional move */
23372 case OPC_MOVZ:
23373 gen_cond_move(ctx, op1, rd, rs, rt);
23374 break;
23375 case OPC_MFHI: /* Move from HI/LO */
23376 case OPC_MFLO:
23377 gen_HILO(ctx, op1, 0, rd);
23378 break;
23379 case OPC_MTHI:
23380 case OPC_MTLO: /* Move to HI/LO */
23381 gen_HILO(ctx, op1, 0, rs);
23382 break;
23383 case OPC_MULT:
23384 case OPC_MULTU:
23385 gen_mul_txx9(ctx, op1, rd, rs, rt);
23386 break;
23387 case OPC_DIV:
23388 case OPC_DIVU:
23389 gen_muldiv(ctx, op1, 0, rs, rt);
23390 break;
23391 #if defined(TARGET_MIPS64)
23392 case OPC_DMULT:
23393 case OPC_DMULTU:
23394 case OPC_DDIV:
23395 case OPC_DDIVU:
23396 check_insn_opc_user_only(ctx, INSN_R5900);
23397 gen_muldiv(ctx, op1, 0, rs, rt);
23398 break;
23399 #endif
23400 case OPC_JR:
23401 gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4);
23402 break;
23403 default: /* Invalid */
23404 MIPS_INVAL("special_tx79");
23405 gen_reserved_instruction(ctx);
23406 break;
23407 }
23408 }
23409
23410 static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
23411 {
23412 int rs, rt, rd, sa;
23413 uint32_t op1;
23414
23415 rs = (ctx->opcode >> 21) & 0x1f;
23416 rt = (ctx->opcode >> 16) & 0x1f;
23417 rd = (ctx->opcode >> 11) & 0x1f;
23418 sa = (ctx->opcode >> 6) & 0x1f;
23419
23420 op1 = MASK_SPECIAL(ctx->opcode);
23421 switch (op1) {
23422 case OPC_MOVN: /* Conditional move */
23423 case OPC_MOVZ:
23424 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 |
23425 INSN_LOONGSON2E | INSN_LOONGSON2F);
23426 gen_cond_move(ctx, op1, rd, rs, rt);
23427 break;
23428 case OPC_MFHI: /* Move from HI/LO */
23429 case OPC_MFLO:
23430 gen_HILO(ctx, op1, rs & 3, rd);
23431 break;
23432 case OPC_MTHI:
23433 case OPC_MTLO: /* Move to HI/LO */
23434 gen_HILO(ctx, op1, rd & 3, rs);
23435 break;
23436 case OPC_MOVCI:
23437 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
23438 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
23439 check_cp1_enabled(ctx);
23440 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
23441 (ctx->opcode >> 16) & 1);
23442 } else {
23443 generate_exception_err(ctx, EXCP_CpU, 1);
23444 }
23445 break;
23446 case OPC_MULT:
23447 case OPC_MULTU:
23448 if (sa) {
23449 check_insn(ctx, INSN_VR54XX);
23450 op1 = MASK_MUL_VR54XX(ctx->opcode);
23451 gen_mul_vr54xx(ctx, op1, rd, rs, rt);
23452 } else {
23453 gen_muldiv(ctx, op1, rd & 3, rs, rt);
23454 }
23455 break;
23456 case OPC_DIV:
23457 case OPC_DIVU:
23458 gen_muldiv(ctx, op1, 0, rs, rt);
23459 break;
23460 #if defined(TARGET_MIPS64)
23461 case OPC_DMULT:
23462 case OPC_DMULTU:
23463 case OPC_DDIV:
23464 case OPC_DDIVU:
23465 check_insn(ctx, ISA_MIPS3);
23466 check_mips_64(ctx);
23467 gen_muldiv(ctx, op1, 0, rs, rt);
23468 break;
23469 #endif
23470 case OPC_JR:
23471 gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
23472 break;
23473 case OPC_SPIM:
23474 #ifdef MIPS_STRICT_STANDARD
23475 MIPS_INVAL("SPIM");
23476 gen_reserved_instruction(ctx);
23477 #else
23478 /* Implemented as RI exception for now. */
23479 MIPS_INVAL("spim (unofficial)");
23480 gen_reserved_instruction(ctx);
23481 #endif
23482 break;
23483 default: /* Invalid */
23484 MIPS_INVAL("special_legacy");
23485 gen_reserved_instruction(ctx);
23486 break;
23487 }
23488 }
23489
23490 static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
23491 {
23492 int rs, rt, rd, sa;
23493 uint32_t op1;
23494
23495 rs = (ctx->opcode >> 21) & 0x1f;
23496 rt = (ctx->opcode >> 16) & 0x1f;
23497 rd = (ctx->opcode >> 11) & 0x1f;
23498 sa = (ctx->opcode >> 6) & 0x1f;
23499
23500 op1 = MASK_SPECIAL(ctx->opcode);
23501 switch (op1) {
23502 case OPC_SLL: /* Shift with immediate */
23503 if (sa == 5 && rd == 0 &&
23504 rs == 0 && rt == 0) { /* PAUSE */
23505 if ((ctx->insn_flags & ISA_MIPS_R6) &&
23506 (ctx->hflags & MIPS_HFLAG_BMASK)) {
23507 gen_reserved_instruction(ctx);
23508 break;
23509 }
23510 }
23511 /* Fallthrough */
23512 case OPC_SRA:
23513 gen_shift_imm(ctx, op1, rd, rt, sa);
23514 break;
23515 case OPC_SRL:
23516 switch ((ctx->opcode >> 21) & 0x1f) {
23517 case 1:
23518 /* rotr is decoded as srl on non-R2 CPUs */
23519 if (ctx->insn_flags & ISA_MIPS_R2) {
23520 op1 = OPC_ROTR;
23521 }
23522 /* Fallthrough */
23523 case 0:
23524 gen_shift_imm(ctx, op1, rd, rt, sa);
23525 break;
23526 default:
23527 gen_reserved_instruction(ctx);
23528 break;
23529 }
23530 break;
23531 case OPC_ADD:
23532 case OPC_ADDU:
23533 case OPC_SUB:
23534 case OPC_SUBU:
23535 gen_arith(ctx, op1, rd, rs, rt);
23536 break;
23537 case OPC_SLLV: /* Shifts */
23538 case OPC_SRAV:
23539 gen_shift(ctx, op1, rd, rs, rt);
23540 break;
23541 case OPC_SRLV:
23542 switch ((ctx->opcode >> 6) & 0x1f) {
23543 case 1:
23544 /* rotrv is decoded as srlv on non-R2 CPUs */
23545 if (ctx->insn_flags & ISA_MIPS_R2) {
23546 op1 = OPC_ROTRV;
23547 }
23548 /* Fallthrough */
23549 case 0:
23550 gen_shift(ctx, op1, rd, rs, rt);
23551 break;
23552 default:
23553 gen_reserved_instruction(ctx);
23554 break;
23555 }
23556 break;
23557 case OPC_SLT: /* Set on less than */
23558 case OPC_SLTU:
23559 gen_slt(ctx, op1, rd, rs, rt);
23560 break;
23561 case OPC_AND: /* Logic*/
23562 case OPC_OR:
23563 case OPC_NOR:
23564 case OPC_XOR:
23565 gen_logic(ctx, op1, rd, rs, rt);
23566 break;
23567 case OPC_JALR:
23568 gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
23569 break;
23570 case OPC_TGE: /* Traps */
23571 case OPC_TGEU:
23572 case OPC_TLT:
23573 case OPC_TLTU:
23574 case OPC_TEQ:
23575 case OPC_TNE:
23576 check_insn(ctx, ISA_MIPS2);
23577 gen_trap(ctx, op1, rs, rt, -1);
23578 break;
23579 case OPC_PMON:
23580 /* Pmon entry point, also R4010 selsl */
23581 #ifdef MIPS_STRICT_STANDARD
23582 MIPS_INVAL("PMON / selsl");
23583 gen_reserved_instruction(ctx);
23584 #else
23585 gen_helper_0e0i(pmon, sa);
23586 #endif
23587 break;
23588 case OPC_SYSCALL:
23589 generate_exception_end(ctx, EXCP_SYSCALL);
23590 break;
23591 case OPC_BREAK:
23592 generate_exception_end(ctx, EXCP_BREAK);
23593 break;
23594 case OPC_SYNC:
23595 check_insn(ctx, ISA_MIPS2);
23596 gen_sync(extract32(ctx->opcode, 6, 5));
23597 break;
23598
23599 #if defined(TARGET_MIPS64)
23600 /* MIPS64 specific opcodes */
23601 case OPC_DSLL:
23602 case OPC_DSRA:
23603 case OPC_DSLL32:
23604 case OPC_DSRA32:
23605 check_insn(ctx, ISA_MIPS3);
23606 check_mips_64(ctx);
23607 gen_shift_imm(ctx, op1, rd, rt, sa);
23608 break;
23609 case OPC_DSRL:
23610 switch ((ctx->opcode >> 21) & 0x1f) {
23611 case 1:
23612 /* drotr is decoded as dsrl on non-R2 CPUs */
23613 if (ctx->insn_flags & ISA_MIPS_R2) {
23614 op1 = OPC_DROTR;
23615 }
23616 /* Fallthrough */
23617 case 0:
23618 check_insn(ctx, ISA_MIPS3);
23619 check_mips_64(ctx);
23620 gen_shift_imm(ctx, op1, rd, rt, sa);
23621 break;
23622 default:
23623 gen_reserved_instruction(ctx);
23624 break;
23625 }
23626 break;
23627 case OPC_DSRL32:
23628 switch ((ctx->opcode >> 21) & 0x1f) {
23629 case 1:
23630 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
23631 if (ctx->insn_flags & ISA_MIPS_R2) {
23632 op1 = OPC_DROTR32;
23633 }
23634 /* Fallthrough */
23635 case 0:
23636 check_insn(ctx, ISA_MIPS3);
23637 check_mips_64(ctx);
23638 gen_shift_imm(ctx, op1, rd, rt, sa);
23639 break;
23640 default:
23641 gen_reserved_instruction(ctx);
23642 break;
23643 }
23644 break;
23645 case OPC_DADD:
23646 case OPC_DADDU:
23647 case OPC_DSUB:
23648 case OPC_DSUBU:
23649 check_insn(ctx, ISA_MIPS3);
23650 check_mips_64(ctx);
23651 gen_arith(ctx, op1, rd, rs, rt);
23652 break;
23653 case OPC_DSLLV:
23654 case OPC_DSRAV:
23655 check_insn(ctx, ISA_MIPS3);
23656 check_mips_64(ctx);
23657 gen_shift(ctx, op1, rd, rs, rt);
23658 break;
23659 case OPC_DSRLV:
23660 switch ((ctx->opcode >> 6) & 0x1f) {
23661 case 1:
23662 /* drotrv is decoded as dsrlv on non-R2 CPUs */
23663 if (ctx->insn_flags & ISA_MIPS_R2) {
23664 op1 = OPC_DROTRV;
23665 }
23666 /* Fallthrough */
23667 case 0:
23668 check_insn(ctx, ISA_MIPS3);
23669 check_mips_64(ctx);
23670 gen_shift(ctx, op1, rd, rs, rt);
23671 break;
23672 default:
23673 gen_reserved_instruction(ctx);
23674 break;
23675 }
23676 break;
23677 #endif
23678 default:
23679 if (ctx->insn_flags & ISA_MIPS_R6) {
23680 decode_opc_special_r6(env, ctx);
23681 } else if (ctx->insn_flags & INSN_R5900) {
23682 decode_opc_special_tx79(env, ctx);
23683 } else {
23684 decode_opc_special_legacy(env, ctx);
23685 }
23686 }
23687 }
23688
23689
23690 static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
23691 {
23692 int rs, rt, rd;
23693 uint32_t op1;
23694
23695 rs = (ctx->opcode >> 21) & 0x1f;
23696 rt = (ctx->opcode >> 16) & 0x1f;
23697 rd = (ctx->opcode >> 11) & 0x1f;
23698
23699 op1 = MASK_SPECIAL2(ctx->opcode);
23700 switch (op1) {
23701 case OPC_MADD: /* Multiply and add/sub */
23702 case OPC_MADDU:
23703 case OPC_MSUB:
23704 case OPC_MSUBU:
23705 check_insn(ctx, ISA_MIPS_R1);
23706 gen_muldiv(ctx, op1, rd & 3, rs, rt);
23707 break;
23708 case OPC_MUL:
23709 gen_arith(ctx, op1, rd, rs, rt);
23710 break;
23711 case OPC_DIV_G_2F:
23712 case OPC_DIVU_G_2F:
23713 case OPC_MULT_G_2F:
23714 case OPC_MULTU_G_2F:
23715 case OPC_MOD_G_2F:
23716 case OPC_MODU_G_2F:
23717 check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
23718 gen_loongson_integer(ctx, op1, rd, rs, rt);
23719 break;
23720 case OPC_CLO:
23721 case OPC_CLZ:
23722 check_insn(ctx, ISA_MIPS_R1);
23723 gen_cl(ctx, op1, rd, rs);
23724 break;
23725 case OPC_SDBBP:
23726 if (is_uhi(extract32(ctx->opcode, 6, 20))) {
23727 gen_helper_do_semihosting(cpu_env);
23728 } else {
23729 /*
23730 * XXX: not clear which exception should be raised
23731 * when in debug mode...
23732 */
23733 check_insn(ctx, ISA_MIPS_R1);
23734 generate_exception_end(ctx, EXCP_DBp);
23735 }
23736 break;
23737 #if defined(TARGET_MIPS64)
23738 case OPC_DCLO:
23739 case OPC_DCLZ:
23740 check_insn(ctx, ISA_MIPS_R1);
23741 check_mips_64(ctx);
23742 gen_cl(ctx, op1, rd, rs);
23743 break;
23744 case OPC_DMULT_G_2F:
23745 case OPC_DMULTU_G_2F:
23746 case OPC_DDIV_G_2F:
23747 case OPC_DDIVU_G_2F:
23748 case OPC_DMOD_G_2F:
23749 case OPC_DMODU_G_2F:
23750 check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
23751 gen_loongson_integer(ctx, op1, rd, rs, rt);
23752 break;
23753 #endif
23754 default: /* Invalid */
23755 MIPS_INVAL("special2_legacy");
23756 gen_reserved_instruction(ctx);
23757 break;
23758 }
23759 }
23760
23761 static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
23762 {
23763 int rs, rt, rd, sa;
23764 uint32_t op1, op2;
23765 int16_t imm;
23766
23767 rs = (ctx->opcode >> 21) & 0x1f;
23768 rt = (ctx->opcode >> 16) & 0x1f;
23769 rd = (ctx->opcode >> 11) & 0x1f;
23770 sa = (ctx->opcode >> 6) & 0x1f;
23771 imm = (int16_t)ctx->opcode >> 7;
23772
23773 op1 = MASK_SPECIAL3(ctx->opcode);
23774 switch (op1) {
23775 case R6_OPC_PREF:
23776 if (rt >= 24) {
23777 /* hint codes 24-31 are reserved and signal RI */
23778 gen_reserved_instruction(ctx);
23779 }
23780 /* Treat as NOP. */
23781 break;
23782 case R6_OPC_CACHE:
23783 check_cp0_enabled(ctx);
23784 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
23785 gen_cache_operation(ctx, rt, rs, imm);
23786 }
23787 break;
23788 case R6_OPC_SC:
23789 gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
23790 break;
23791 case R6_OPC_LL:
23792 gen_ld(ctx, op1, rt, rs, imm);
23793 break;
23794 case OPC_BSHFL:
23795 {
23796 if (rd == 0) {
23797 /* Treat as NOP. */
23798 break;
23799 }
23800 op2 = MASK_BSHFL(ctx->opcode);
23801 switch (op2) {
23802 case OPC_ALIGN:
23803 case OPC_ALIGN_1:
23804 case OPC_ALIGN_2:
23805 case OPC_ALIGN_3:
23806 gen_align(ctx, 32, rd, rs, rt, sa & 3);
23807 break;
23808 case OPC_BITSWAP:
23809 gen_bitswap(ctx, op2, rd, rt);
23810 break;
23811 }
23812 }
23813 break;
23814 #ifndef CONFIG_USER_ONLY
23815 case OPC_GINV:
23816 if (unlikely(ctx->gi <= 1)) {
23817 gen_reserved_instruction(ctx);
23818 }
23819 check_cp0_enabled(ctx);
23820 switch ((ctx->opcode >> 6) & 3) {
23821 case 0: /* GINVI */
23822 /* Treat as NOP. */
23823 break;
23824 case 2: /* GINVT */
23825 gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, 2));
23826 break;
23827 default:
23828 gen_reserved_instruction(ctx);
23829 break;
23830 }
23831 break;
23832 #endif
23833 #if defined(TARGET_MIPS64)
23834 case R6_OPC_SCD:
23835 gen_st_cond(ctx, rt, rs, imm, MO_TEQ, false);
23836 break;
23837 case R6_OPC_LLD:
23838 gen_ld(ctx, op1, rt, rs, imm);
23839 break;
23840 case OPC_DBSHFL:
23841 check_mips_64(ctx);
23842 {
23843 if (rd == 0) {
23844 /* Treat as NOP. */
23845 break;
23846 }
23847 op2 = MASK_DBSHFL(ctx->opcode);
23848 switch (op2) {
23849 case OPC_DALIGN:
23850 case OPC_DALIGN_1:
23851 case OPC_DALIGN_2:
23852 case OPC_DALIGN_3:
23853 case OPC_DALIGN_4:
23854 case OPC_DALIGN_5:
23855 case OPC_DALIGN_6:
23856 case OPC_DALIGN_7:
23857 gen_align(ctx, 64, rd, rs, rt, sa & 7);
23858 break;
23859 case OPC_DBITSWAP:
23860 gen_bitswap(ctx, op2, rd, rt);
23861 break;
23862 }
23863
23864 }
23865 break;
23866 #endif
23867 default: /* Invalid */
23868 MIPS_INVAL("special3_r6");
23869 gen_reserved_instruction(ctx);
23870 break;
23871 }
23872 }
23873
23874 static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
23875 {
23876 int rs, rt, rd;
23877 uint32_t op1, op2;
23878
23879 rs = (ctx->opcode >> 21) & 0x1f;
23880 rt = (ctx->opcode >> 16) & 0x1f;
23881 rd = (ctx->opcode >> 11) & 0x1f;
23882
23883 op1 = MASK_SPECIAL3(ctx->opcode);
23884 switch (op1) {
23885 case OPC_DIV_G_2E:
23886 case OPC_DIVU_G_2E:
23887 case OPC_MOD_G_2E:
23888 case OPC_MODU_G_2E:
23889 case OPC_MULT_G_2E:
23890 case OPC_MULTU_G_2E:
23891 /*
23892 * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
23893 * the same mask and op1.
23894 */
23895 if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) {
23896 op2 = MASK_ADDUH_QB(ctx->opcode);
23897 switch (op2) {
23898 case OPC_ADDUH_QB:
23899 case OPC_ADDUH_R_QB:
23900 case OPC_ADDQH_PH:
23901 case OPC_ADDQH_R_PH:
23902 case OPC_ADDQH_W:
23903 case OPC_ADDQH_R_W:
23904 case OPC_SUBUH_QB:
23905 case OPC_SUBUH_R_QB:
23906 case OPC_SUBQH_PH:
23907 case OPC_SUBQH_R_PH:
23908 case OPC_SUBQH_W:
23909 case OPC_SUBQH_R_W:
23910 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
23911 break;
23912 case OPC_MUL_PH:
23913 case OPC_MUL_S_PH:
23914 case OPC_MULQ_S_W:
23915 case OPC_MULQ_RS_W:
23916 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1);
23917 break;
23918 default:
23919 MIPS_INVAL("MASK ADDUH.QB");
23920 gen_reserved_instruction(ctx);
23921 break;
23922 }
23923 } else if (ctx->insn_flags & INSN_LOONGSON2E) {
23924 gen_loongson_integer(ctx, op1, rd, rs, rt);
23925 } else {
23926 gen_reserved_instruction(ctx);
23927 }
23928 break;
23929 case OPC_LX_DSP:
23930 op2 = MASK_LX(ctx->opcode);
23931 switch (op2) {
23932 #if defined(TARGET_MIPS64)
23933 case OPC_LDX:
23934 #endif
23935 case OPC_LBUX:
23936 case OPC_LHX:
23937 case OPC_LWX:
23938 gen_mipsdsp_ld(ctx, op2, rd, rs, rt);
23939 break;
23940 default: /* Invalid */
23941 MIPS_INVAL("MASK LX");
23942 gen_reserved_instruction(ctx);
23943 break;
23944 }
23945 break;
23946 case OPC_ABSQ_S_PH_DSP:
23947 op2 = MASK_ABSQ_S_PH(ctx->opcode);
23948 switch (op2) {
23949 case OPC_ABSQ_S_QB:
23950 case OPC_ABSQ_S_PH:
23951 case OPC_ABSQ_S_W:
23952 case OPC_PRECEQ_W_PHL:
23953 case OPC_PRECEQ_W_PHR:
23954 case OPC_PRECEQU_PH_QBL:
23955 case OPC_PRECEQU_PH_QBR:
23956 case OPC_PRECEQU_PH_QBLA:
23957 case OPC_PRECEQU_PH_QBRA:
23958 case OPC_PRECEU_PH_QBL:
23959 case OPC_PRECEU_PH_QBR:
23960 case OPC_PRECEU_PH_QBLA:
23961 case OPC_PRECEU_PH_QBRA:
23962 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
23963 break;
23964 case OPC_BITREV:
23965 case OPC_REPL_QB:
23966 case OPC_REPLV_QB:
23967 case OPC_REPL_PH:
23968 case OPC_REPLV_PH:
23969 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt);
23970 break;
23971 default:
23972 MIPS_INVAL("MASK ABSQ_S.PH");
23973 gen_reserved_instruction(ctx);
23974 break;
23975 }
23976 break;
23977 case OPC_ADDU_QB_DSP:
23978 op2 = MASK_ADDU_QB(ctx->opcode);
23979 switch (op2) {
23980 case OPC_ADDQ_PH:
23981 case OPC_ADDQ_S_PH:
23982 case OPC_ADDQ_S_W:
23983 case OPC_ADDU_QB:
23984 case OPC_ADDU_S_QB:
23985 case OPC_ADDU_PH:
23986 case OPC_ADDU_S_PH:
23987 case OPC_SUBQ_PH:
23988 case OPC_SUBQ_S_PH:
23989 case OPC_SUBQ_S_W:
23990 case OPC_SUBU_QB:
23991 case OPC_SUBU_S_QB:
23992 case OPC_SUBU_PH:
23993 case OPC_SUBU_S_PH:
23994 case OPC_ADDSC:
23995 case OPC_ADDWC:
23996 case OPC_MODSUB:
23997 case OPC_RADDU_W_QB:
23998 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
23999 break;
24000 case OPC_MULEU_S_PH_QBL:
24001 case OPC_MULEU_S_PH_QBR:
24002 case OPC_MULQ_RS_PH:
24003 case OPC_MULEQ_S_W_PHL:
24004 case OPC_MULEQ_S_W_PHR:
24005 case OPC_MULQ_S_PH:
24006 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1);
24007 break;
24008 default: /* Invalid */
24009 MIPS_INVAL("MASK ADDU.QB");
24010 gen_reserved_instruction(ctx);
24011 break;
24012
24013 }
24014 break;
24015 case OPC_CMPU_EQ_QB_DSP:
24016 op2 = MASK_CMPU_EQ_QB(ctx->opcode);
24017 switch (op2) {
24018 case OPC_PRECR_SRA_PH_W:
24019 case OPC_PRECR_SRA_R_PH_W:
24020 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd);
24021 break;
24022 case OPC_PRECR_QB_PH:
24023 case OPC_PRECRQ_QB_PH:
24024 case OPC_PRECRQ_PH_W:
24025 case OPC_PRECRQ_RS_PH_W:
24026 case OPC_PRECRQU_S_QB_PH:
24027 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
24028 break;
24029 case OPC_CMPU_EQ_QB:
24030 case OPC_CMPU_LT_QB:
24031 case OPC_CMPU_LE_QB:
24032 case OPC_CMP_EQ_PH:
24033 case OPC_CMP_LT_PH:
24034 case OPC_CMP_LE_PH:
24035 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0);
24036 break;
24037 case OPC_CMPGU_EQ_QB:
24038 case OPC_CMPGU_LT_QB:
24039 case OPC_CMPGU_LE_QB:
24040 case OPC_CMPGDU_EQ_QB:
24041 case OPC_CMPGDU_LT_QB:
24042 case OPC_CMPGDU_LE_QB:
24043 case OPC_PICK_QB:
24044 case OPC_PICK_PH:
24045 case OPC_PACKRL_PH:
24046 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1);
24047 break;
24048 default: /* Invalid */
24049 MIPS_INVAL("MASK CMPU.EQ.QB");
24050 gen_reserved_instruction(ctx);
24051 break;
24052 }
24053 break;
24054 case OPC_SHLL_QB_DSP:
24055 gen_mipsdsp_shift(ctx, op1, rd, rs, rt);
24056 break;
24057 case OPC_DPA_W_PH_DSP:
24058 op2 = MASK_DPA_W_PH(ctx->opcode);
24059 switch (op2) {
24060 case OPC_DPAU_H_QBL:
24061 case OPC_DPAU_H_QBR:
24062 case OPC_DPSU_H_QBL:
24063 case OPC_DPSU_H_QBR:
24064 case OPC_DPA_W_PH:
24065 case OPC_DPAX_W_PH:
24066 case OPC_DPAQ_S_W_PH:
24067 case OPC_DPAQX_S_W_PH:
24068 case OPC_DPAQX_SA_W_PH:
24069 case OPC_DPS_W_PH:
24070 case OPC_DPSX_W_PH:
24071 case OPC_DPSQ_S_W_PH:
24072 case OPC_DPSQX_S_W_PH:
24073 case OPC_DPSQX_SA_W_PH:
24074 case OPC_MULSAQ_S_W_PH:
24075 case OPC_DPAQ_SA_L_W:
24076 case OPC_DPSQ_SA_L_W:
24077 case OPC_MAQ_S_W_PHL:
24078 case OPC_MAQ_S_W_PHR:
24079 case OPC_MAQ_SA_W_PHL:
24080 case OPC_MAQ_SA_W_PHR:
24081 case OPC_MULSA_W_PH:
24082 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0);
24083 break;
24084 default: /* Invalid */
24085 MIPS_INVAL("MASK DPAW.PH");
24086 gen_reserved_instruction(ctx);
24087 break;
24088 }
24089 break;
24090 case OPC_INSV_DSP:
24091 op2 = MASK_INSV(ctx->opcode);
24092 switch (op2) {
24093 case OPC_INSV:
24094 check_dsp(ctx);
24095 {
24096 TCGv t0, t1;
24097
24098 if (rt == 0) {
24099 break;
24100 }
24101
24102 t0 = tcg_temp_new();
24103 t1 = tcg_temp_new();
24104
24105 gen_load_gpr(t0, rt);
24106 gen_load_gpr(t1, rs);
24107
24108 gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0);
24109
24110 tcg_temp_free(t0);
24111 tcg_temp_free(t1);
24112 break;
24113 }
24114 default: /* Invalid */
24115 MIPS_INVAL("MASK INSV");
24116 gen_reserved_instruction(ctx);
24117 break;
24118 }
24119 break;
24120 case OPC_APPEND_DSP:
24121 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd);
24122 break;
24123 case OPC_EXTR_W_DSP:
24124 op2 = MASK_EXTR_W(ctx->opcode);
24125 switch (op2) {
24126 case OPC_EXTR_W:
24127 case OPC_EXTR_R_W:
24128 case OPC_EXTR_RS_W:
24129 case OPC_EXTR_S_H:
24130 case OPC_EXTRV_S_H:
24131 case OPC_EXTRV_W:
24132 case OPC_EXTRV_R_W:
24133 case OPC_EXTRV_RS_W:
24134 case OPC_EXTP:
24135 case OPC_EXTPV:
24136 case OPC_EXTPDP:
24137 case OPC_EXTPDPV:
24138 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1);
24139 break;
24140 case OPC_RDDSP:
24141 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 1);
24142 break;
24143 case OPC_SHILO:
24144 case OPC_SHILOV:
24145 case OPC_MTHLIP:
24146 case OPC_WRDSP:
24147 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0);
24148 break;
24149 default: /* Invalid */
24150 MIPS_INVAL("MASK EXTR.W");
24151 gen_reserved_instruction(ctx);
24152 break;
24153 }
24154 break;
24155 #if defined(TARGET_MIPS64)
24156 case OPC_DDIV_G_2E:
24157 case OPC_DDIVU_G_2E:
24158 case OPC_DMULT_G_2E:
24159 case OPC_DMULTU_G_2E:
24160 case OPC_DMOD_G_2E:
24161 case OPC_DMODU_G_2E:
24162 check_insn(ctx, INSN_LOONGSON2E);
24163 gen_loongson_integer(ctx, op1, rd, rs, rt);
24164 break;
24165 case OPC_ABSQ_S_QH_DSP:
24166 op2 = MASK_ABSQ_S_QH(ctx->opcode);
24167 switch (op2) {
24168 case OPC_PRECEQ_L_PWL:
24169 case OPC_PRECEQ_L_PWR:
24170 case OPC_PRECEQ_PW_QHL:
24171 case OPC_PRECEQ_PW_QHR:
24172 case OPC_PRECEQ_PW_QHLA:
24173 case OPC_PRECEQ_PW_QHRA:
24174 case OPC_PRECEQU_QH_OBL:
24175 case OPC_PRECEQU_QH_OBR:
24176 case OPC_PRECEQU_QH_OBLA:
24177 case OPC_PRECEQU_QH_OBRA:
24178 case OPC_PRECEU_QH_OBL:
24179 case OPC_PRECEU_QH_OBR:
24180 case OPC_PRECEU_QH_OBLA:
24181 case OPC_PRECEU_QH_OBRA:
24182 case OPC_ABSQ_S_OB:
24183 case OPC_ABSQ_S_PW:
24184 case OPC_ABSQ_S_QH:
24185 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
24186 break;
24187 case OPC_REPL_OB:
24188 case OPC_REPL_PW:
24189 case OPC_REPL_QH:
24190 case OPC_REPLV_OB:
24191 case OPC_REPLV_PW:
24192 case OPC_REPLV_QH:
24193 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt);
24194 break;
24195 default: /* Invalid */
24196 MIPS_INVAL("MASK ABSQ_S.QH");
24197 gen_reserved_instruction(ctx);
24198 break;
24199 }
24200 break;
24201 case OPC_ADDU_OB_DSP:
24202 op2 = MASK_ADDU_OB(ctx->opcode);
24203 switch (op2) {
24204 case OPC_RADDU_L_OB:
24205 case OPC_SUBQ_PW:
24206 case OPC_SUBQ_S_PW:
24207 case OPC_SUBQ_QH:
24208 case OPC_SUBQ_S_QH:
24209 case OPC_SUBU_OB:
24210 case OPC_SUBU_S_OB:
24211 case OPC_SUBU_QH:
24212 case OPC_SUBU_S_QH:
24213 case OPC_SUBUH_OB:
24214 case OPC_SUBUH_R_OB:
24215 case OPC_ADDQ_PW:
24216 case OPC_ADDQ_S_PW:
24217 case OPC_ADDQ_QH:
24218 case OPC_ADDQ_S_QH:
24219 case OPC_ADDU_OB:
24220 case OPC_ADDU_S_OB:
24221 case OPC_ADDU_QH:
24222 case OPC_ADDU_S_QH:
24223 case OPC_ADDUH_OB:
24224 case OPC_ADDUH_R_OB:
24225 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
24226 break;
24227 case OPC_MULEQ_S_PW_QHL:
24228 case OPC_MULEQ_S_PW_QHR:
24229 case OPC_MULEU_S_QH_OBL:
24230 case OPC_MULEU_S_QH_OBR:
24231 case OPC_MULQ_RS_QH:
24232 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1);
24233 break;
24234 default: /* Invalid */
24235 MIPS_INVAL("MASK ADDU.OB");
24236 gen_reserved_instruction(ctx);
24237 break;
24238 }
24239 break;
24240 case OPC_CMPU_EQ_OB_DSP:
24241 op2 = MASK_CMPU_EQ_OB(ctx->opcode);
24242 switch (op2) {
24243 case OPC_PRECR_SRA_QH_PW:
24244 case OPC_PRECR_SRA_R_QH_PW:
24245 /* Return value is rt. */
24246 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd);
24247 break;
24248 case OPC_PRECR_OB_QH:
24249 case OPC_PRECRQ_OB_QH:
24250 case OPC_PRECRQ_PW_L:
24251 case OPC_PRECRQ_QH_PW:
24252 case OPC_PRECRQ_RS_QH_PW:
24253 case OPC_PRECRQU_S_OB_QH:
24254 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
24255 break;
24256 case OPC_CMPU_EQ_OB:
24257 case OPC_CMPU_LT_OB:
24258 case OPC_CMPU_LE_OB:
24259 case OPC_CMP_EQ_QH:
24260 case OPC_CMP_LT_QH:
24261 case OPC_CMP_LE_QH:
24262 case OPC_CMP_EQ_PW:
24263 case OPC_CMP_LT_PW:
24264 case OPC_CMP_LE_PW:
24265 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0);
24266 break;
24267 case OPC_CMPGDU_EQ_OB:
24268 case OPC_CMPGDU_LT_OB:
24269 case OPC_CMPGDU_LE_OB:
24270 case OPC_CMPGU_EQ_OB:
24271 case OPC_CMPGU_LT_OB:
24272 case OPC_CMPGU_LE_OB:
24273 case OPC_PACKRL_PW:
24274 case OPC_PICK_OB:
24275 case OPC_PICK_PW:
24276 case OPC_PICK_QH:
24277 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1);
24278 break;
24279 default: /* Invalid */
24280 MIPS_INVAL("MASK CMPU_EQ.OB");
24281 gen_reserved_instruction(ctx);
24282 break;
24283 }
24284 break;
24285 case OPC_DAPPEND_DSP:
24286 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd);
24287 break;
24288 case OPC_DEXTR_W_DSP:
24289 op2 = MASK_DEXTR_W(ctx->opcode);
24290 switch (op2) {
24291 case OPC_DEXTP:
24292 case OPC_DEXTPDP:
24293 case OPC_DEXTPDPV:
24294 case OPC_DEXTPV:
24295 case OPC_DEXTR_L:
24296 case OPC_DEXTR_R_L:
24297 case OPC_DEXTR_RS_L:
24298 case OPC_DEXTR_W:
24299 case OPC_DEXTR_R_W:
24300 case OPC_DEXTR_RS_W:
24301 case OPC_DEXTR_S_H:
24302 case OPC_DEXTRV_L:
24303 case OPC_DEXTRV_R_L:
24304 case OPC_DEXTRV_RS_L:
24305 case OPC_DEXTRV_S_H:
24306 case OPC_DEXTRV_W:
24307 case OPC_DEXTRV_R_W:
24308 case OPC_DEXTRV_RS_W:
24309 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1);
24310 break;
24311 case OPC_DMTHLIP:
24312 case OPC_DSHILO:
24313 case OPC_DSHILOV:
24314 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0);
24315 break;
24316 default: /* Invalid */
24317 MIPS_INVAL("MASK EXTR.W");
24318 gen_reserved_instruction(ctx);
24319 break;
24320 }
24321 break;
24322 case OPC_DPAQ_W_QH_DSP:
24323 op2 = MASK_DPAQ_W_QH(ctx->opcode);
24324 switch (op2) {
24325 case OPC_DPAU_H_OBL:
24326 case OPC_DPAU_H_OBR:
24327 case OPC_DPSU_H_OBL:
24328 case OPC_DPSU_H_OBR:
24329 case OPC_DPA_W_QH:
24330 case OPC_DPAQ_S_W_QH:
24331 case OPC_DPS_W_QH:
24332 case OPC_DPSQ_S_W_QH:
24333 case OPC_MULSAQ_S_W_QH:
24334 case OPC_DPAQ_SA_L_PW:
24335 case OPC_DPSQ_SA_L_PW:
24336 case OPC_MULSAQ_S_L_PW:
24337 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0);
24338 break;
24339 case OPC_MAQ_S_W_QHLL:
24340 case OPC_MAQ_S_W_QHLR:
24341 case OPC_MAQ_S_W_QHRL:
24342 case OPC_MAQ_S_W_QHRR:
24343 case OPC_MAQ_SA_W_QHLL:
24344 case OPC_MAQ_SA_W_QHLR:
24345 case OPC_MAQ_SA_W_QHRL:
24346 case OPC_MAQ_SA_W_QHRR:
24347 case OPC_MAQ_S_L_PWL:
24348 case OPC_MAQ_S_L_PWR:
24349 case OPC_DMADD:
24350 case OPC_DMADDU:
24351 case OPC_DMSUB:
24352 case OPC_DMSUBU:
24353 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0);
24354 break;
24355 default: /* Invalid */
24356 MIPS_INVAL("MASK DPAQ.W.QH");
24357 gen_reserved_instruction(ctx);
24358 break;
24359 }
24360 break;
24361 case OPC_DINSV_DSP:
24362 op2 = MASK_INSV(ctx->opcode);
24363 switch (op2) {
24364 case OPC_DINSV:
24365 {
24366 TCGv t0, t1;
24367
24368 if (rt == 0) {
24369 break;
24370 }
24371 check_dsp(ctx);
24372
24373 t0 = tcg_temp_new();
24374 t1 = tcg_temp_new();
24375
24376 gen_load_gpr(t0, rt);
24377 gen_load_gpr(t1, rs);
24378
24379 gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0);
24380
24381 tcg_temp_free(t0);
24382 tcg_temp_free(t1);
24383 break;
24384 }
24385 default: /* Invalid */
24386 MIPS_INVAL("MASK DINSV");
24387 gen_reserved_instruction(ctx);
24388 break;
24389 }
24390 break;
24391 case OPC_SHLL_OB_DSP:
24392 gen_mipsdsp_shift(ctx, op1, rd, rs, rt);
24393 break;
24394 #endif
24395 default: /* Invalid */
24396 MIPS_INVAL("special3_legacy");
24397 gen_reserved_instruction(ctx);
24398 break;
24399 }
24400 }
24401
24402
24403 #if defined(TARGET_MIPS64)
24404
24405 static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
24406 {
24407 uint32_t opc = MASK_MMI(ctx->opcode);
24408 int rs = extract32(ctx->opcode, 21, 5);
24409 int rt = extract32(ctx->opcode, 16, 5);
24410 int rd = extract32(ctx->opcode, 11, 5);
24411
24412 switch (opc) {
24413 case MMI_OPC_MULT1:
24414 case MMI_OPC_MULTU1:
24415 case MMI_OPC_MADD:
24416 case MMI_OPC_MADDU:
24417 case MMI_OPC_MADD1:
24418 case MMI_OPC_MADDU1:
24419 gen_mul_txx9(ctx, opc, rd, rs, rt);
24420 break;
24421 case MMI_OPC_DIV1:
24422 case MMI_OPC_DIVU1:
24423 gen_div1_tx79(ctx, opc, rs, rt);
24424 break;
24425 default:
24426 MIPS_INVAL("TX79 MMI class");
24427 gen_reserved_instruction(ctx);
24428 break;
24429 }
24430 }
24431
24432 static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx)
24433 {
24434 gen_reserved_instruction(ctx); /* TODO: MMI_OPC_LQ */
24435 }
24436
24437 static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
24438 {
24439 gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */
24440 }
24441
24442 /*
24443 * The TX79-specific instruction Store Quadword
24444 *
24445 * +--------+-------+-------+------------------------+
24446 * | 011111 | base | rt | offset | SQ
24447 * +--------+-------+-------+------------------------+
24448 * 6 5 5 16
24449 *
24450 * has the same opcode as the Read Hardware Register instruction
24451 *
24452 * +--------+-------+-------+-------+-------+--------+
24453 * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR
24454 * +--------+-------+-------+-------+-------+--------+
24455 * 6 5 5 5 5 6
24456 *
24457 * that is required, trapped and emulated by the Linux kernel. However, all
24458 * RDHWR encodings yield address error exceptions on the TX79 since the SQ
24459 * offset is odd. Therefore all valid SQ instructions can execute normally.
24460 * In user mode, QEMU must verify the upper and lower 11 bits to distinguish
24461 * between SQ and RDHWR, as the Linux kernel does.
24462 */
24463 static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx)
24464 {
24465 int base = extract32(ctx->opcode, 21, 5);
24466 int rt = extract32(ctx->opcode, 16, 5);
24467 int offset = extract32(ctx->opcode, 0, 16);
24468
24469 #ifdef CONFIG_USER_ONLY
24470 uint32_t op1 = MASK_SPECIAL3(ctx->opcode);
24471 uint32_t op2 = extract32(ctx->opcode, 6, 5);
24472
24473 if (base == 0 && op2 == 0 && op1 == OPC_RDHWR) {
24474 int rd = extract32(ctx->opcode, 11, 5);
24475
24476 gen_rdhwr(ctx, rt, rd, 0);
24477 return;
24478 }
24479 #endif
24480
24481 gen_mmi_sq(ctx, base, rt, offset);
24482 }
24483
24484 #endif
24485
24486 static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
24487 {
24488 int rs, rt, rd, sa;
24489 uint32_t op1, op2;
24490 int16_t imm;
24491
24492 rs = (ctx->opcode >> 21) & 0x1f;
24493 rt = (ctx->opcode >> 16) & 0x1f;
24494 rd = (ctx->opcode >> 11) & 0x1f;
24495 sa = (ctx->opcode >> 6) & 0x1f;
24496 imm = sextract32(ctx->opcode, 7, 9);
24497
24498 op1 = MASK_SPECIAL3(ctx->opcode);
24499
24500 /*
24501 * EVA loads and stores overlap Loongson 2E instructions decoded by
24502 * decode_opc_special3_legacy(), so be careful to allow their decoding when
24503 * EVA is absent.
24504 */
24505 if (ctx->eva) {
24506 switch (op1) {
24507 case OPC_LWLE:
24508 case OPC_LWRE:
24509 case OPC_LBUE:
24510 case OPC_LHUE:
24511 case OPC_LBE:
24512 case OPC_LHE:
24513 case OPC_LLE:
24514 case OPC_LWE:
24515 check_cp0_enabled(ctx);
24516 gen_ld(ctx, op1, rt, rs, imm);
24517 return;
24518 case OPC_SWLE:
24519 case OPC_SWRE:
24520 case OPC_SBE:
24521 case OPC_SHE:
24522 case OPC_SWE:
24523 check_cp0_enabled(ctx);
24524 gen_st(ctx, op1, rt, rs, imm);
24525 return;
24526 case OPC_SCE:
24527 check_cp0_enabled(ctx);
24528 gen_st_cond(ctx, rt, rs, imm, MO_TESL, true);
24529 return;
24530 case OPC_CACHEE:
24531 check_cp0_enabled(ctx);
24532 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
24533 gen_cache_operation(ctx, rt, rs, imm);
24534 }
24535 /* Treat as NOP. */
24536 return;
24537 case OPC_PREFE:
24538 check_cp0_enabled(ctx);
24539 /* Treat as NOP. */
24540 return;
24541 }
24542 }
24543
24544 switch (op1) {
24545 case OPC_EXT:
24546 case OPC_INS:
24547 check_insn(ctx, ISA_MIPS_R2);
24548 gen_bitops(ctx, op1, rt, rs, sa, rd);
24549 break;
24550 case OPC_BSHFL:
24551 op2 = MASK_BSHFL(ctx->opcode);
24552 switch (op2) {
24553 case OPC_ALIGN:
24554 case OPC_ALIGN_1:
24555 case OPC_ALIGN_2:
24556 case OPC_ALIGN_3:
24557 case OPC_BITSWAP:
24558 check_insn(ctx, ISA_MIPS_R6);
24559 decode_opc_special3_r6(env, ctx);
24560 break;
24561 default:
24562 check_insn(ctx, ISA_MIPS_R2);
24563 gen_bshfl(ctx, op2, rt, rd);
24564 break;
24565 }
24566 break;
24567 #if defined(TARGET_MIPS64)
24568 case OPC_DEXTM:
24569 case OPC_DEXTU:
24570 case OPC_DEXT:
24571 case OPC_DINSM:
24572 case OPC_DINSU:
24573 case OPC_DINS:
24574 check_insn(ctx, ISA_MIPS_R2);
24575 check_mips_64(ctx);
24576 gen_bitops(ctx, op1, rt, rs, sa, rd);
24577 break;
24578 case OPC_DBSHFL:
24579 op2 = MASK_DBSHFL(ctx->opcode);
24580 switch (op2) {
24581 case OPC_DALIGN:
24582 case OPC_DALIGN_1:
24583 case OPC_DALIGN_2:
24584 case OPC_DALIGN_3:
24585 case OPC_DALIGN_4:
24586 case OPC_DALIGN_5:
24587 case OPC_DALIGN_6:
24588 case OPC_DALIGN_7:
24589 case OPC_DBITSWAP:
24590 check_insn(ctx, ISA_MIPS_R6);
24591 decode_opc_special3_r6(env, ctx);
24592 break;
24593 default:
24594 check_insn(ctx, ISA_MIPS_R2);
24595 check_mips_64(ctx);
24596 op2 = MASK_DBSHFL(ctx->opcode);
24597 gen_bshfl(ctx, op2, rt, rd);
24598 break;
24599 }
24600 break;
24601 #endif
24602 case OPC_RDHWR:
24603 gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3));
24604 break;
24605 case OPC_FORK:
24606 check_mt(ctx);
24607 {
24608 TCGv t0 = tcg_temp_new();
24609 TCGv t1 = tcg_temp_new();
24610
24611 gen_load_gpr(t0, rt);
24612 gen_load_gpr(t1, rs);
24613 gen_helper_fork(t0, t1);
24614 tcg_temp_free(t0);
24615 tcg_temp_free(t1);
24616 }
24617 break;
24618 case OPC_YIELD:
24619 check_mt(ctx);
24620 {
24621 TCGv t0 = tcg_temp_new();
24622
24623 gen_load_gpr(t0, rs);
24624 gen_helper_yield(t0, cpu_env, t0);
24625 gen_store_gpr(t0, rd);
24626 tcg_temp_free(t0);
24627 }
24628 break;
24629 default:
24630 if (ctx->insn_flags & ISA_MIPS_R6) {
24631 decode_opc_special3_r6(env, ctx);
24632 } else {
24633 decode_opc_special3_legacy(env, ctx);
24634 }
24635 }
24636 }
24637
24638 static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
24639 {
24640 int32_t offset;
24641 int rs, rt, rd, sa;
24642 uint32_t op, op1;
24643 int16_t imm;
24644
24645 op = MASK_OP_MAJOR(ctx->opcode);
24646 rs = (ctx->opcode >> 21) & 0x1f;
24647 rt = (ctx->opcode >> 16) & 0x1f;
24648 rd = (ctx->opcode >> 11) & 0x1f;
24649 sa = (ctx->opcode >> 6) & 0x1f;
24650 imm = (int16_t)ctx->opcode;
24651 switch (op) {
24652 case OPC_SPECIAL:
24653 decode_opc_special(env, ctx);
24654 break;
24655 case OPC_SPECIAL2:
24656 #if defined(TARGET_MIPS64)
24657 if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
24658 decode_mmi(env, ctx);
24659 break;
24660 }
24661 #endif
24662 if (TARGET_LONG_BITS == 32 && (ctx->insn_flags & ASE_MXU)) {
24663 if (MASK_SPECIAL2(ctx->opcode) == OPC_MUL) {
24664 gen_arith(ctx, OPC_MUL, rd, rs, rt);
24665 } else {
24666 decode_ase_mxu(ctx, ctx->opcode);
24667 }
24668 break;
24669 }
24670 decode_opc_special2_legacy(env, ctx);
24671 break;
24672 case OPC_SPECIAL3:
24673 #if defined(TARGET_MIPS64)
24674 if (ctx->insn_flags & INSN_R5900) {
24675 decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */
24676 } else {
24677 decode_opc_special3(env, ctx);
24678 }
24679 #else
24680 decode_opc_special3(env, ctx);
24681 #endif
24682 break;
24683 case OPC_REGIMM:
24684 op1 = MASK_REGIMM(ctx->opcode);
24685 switch (op1) {
24686 case OPC_BLTZL: /* REGIMM branches */
24687 case OPC_BGEZL:
24688 case OPC_BLTZALL:
24689 case OPC_BGEZALL:
24690 check_insn(ctx, ISA_MIPS2);
24691 check_insn_opc_removed(ctx, ISA_MIPS_R6);
24692 /* Fallthrough */
24693 case OPC_BLTZ:
24694 case OPC_BGEZ:
24695 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
24696 break;
24697 case OPC_BLTZAL:
24698 case OPC_BGEZAL:
24699 if (ctx->insn_flags & ISA_MIPS_R6) {
24700 if (rs == 0) {
24701 /* OPC_NAL, OPC_BAL */
24702 gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4);
24703 } else {
24704 gen_reserved_instruction(ctx);
24705 }
24706 } else {
24707 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
24708 }
24709 break;
24710 case OPC_TGEI: /* REGIMM traps */
24711 case OPC_TGEIU:
24712 case OPC_TLTI:
24713 case OPC_TLTIU:
24714 case OPC_TEQI:
24715
24716 case OPC_TNEI:
24717 check_insn(ctx, ISA_MIPS2);
24718 check_insn_opc_removed(ctx, ISA_MIPS_R6);
24719 gen_trap(ctx, op1, rs, -1, imm);
24720 break;
24721 case OPC_SIGRIE:
24722 check_insn(ctx, ISA_MIPS_R6);
24723 gen_reserved_instruction(ctx);
24724 break;
24725 case OPC_SYNCI:
24726 check_insn(ctx, ISA_MIPS_R2);
24727 /*
24728 * Break the TB to be able to sync copied instructions
24729 * immediately.
24730 */
24731 ctx->base.is_jmp = DISAS_STOP;
24732 break;
24733 case OPC_BPOSGE32: /* MIPS DSP branch */
24734 #if defined(TARGET_MIPS64)
24735 case OPC_BPOSGE64:
24736 #endif
24737 check_dsp(ctx);
24738 gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2, 4);
24739 break;
24740 #if defined(TARGET_MIPS64)
24741 case OPC_DAHI:
24742 check_insn(ctx, ISA_MIPS_R6);
24743 check_mips_64(ctx);
24744 if (rs != 0) {
24745 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 32);
24746 }
24747 break;
24748 case OPC_DATI:
24749 check_insn(ctx, ISA_MIPS_R6);
24750 check_mips_64(ctx);
24751 if (rs != 0) {
24752 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 48);
24753 }
24754 break;
24755 #endif
24756 default: /* Invalid */
24757 MIPS_INVAL("regimm");
24758 gen_reserved_instruction(ctx);
24759 break;
24760 }
24761 break;
24762 case OPC_CP0:
24763 check_cp0_enabled(ctx);
24764 op1 = MASK_CP0(ctx->opcode);
24765 switch (op1) {
24766 case OPC_MFC0:
24767 case OPC_MTC0:
24768 case OPC_MFTR:
24769 case OPC_MTTR:
24770 case OPC_MFHC0:
24771 case OPC_MTHC0:
24772 #if defined(TARGET_MIPS64)
24773 case OPC_DMFC0:
24774 case OPC_DMTC0:
24775 #endif
24776 #ifndef CONFIG_USER_ONLY
24777 gen_cp0(env, ctx, op1, rt, rd);
24778 #endif /* !CONFIG_USER_ONLY */
24779 break;
24780 case OPC_C0:
24781 case OPC_C0_1:
24782 case OPC_C0_2:
24783 case OPC_C0_3:
24784 case OPC_C0_4:
24785 case OPC_C0_5:
24786 case OPC_C0_6:
24787 case OPC_C0_7:
24788 case OPC_C0_8:
24789 case OPC_C0_9:
24790 case OPC_C0_A:
24791 case OPC_C0_B:
24792 case OPC_C0_C:
24793 case OPC_C0_D:
24794 case OPC_C0_E:
24795 case OPC_C0_F:
24796 #ifndef CONFIG_USER_ONLY
24797 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
24798 #endif /* !CONFIG_USER_ONLY */
24799 break;
24800 case OPC_MFMC0:
24801 #ifndef CONFIG_USER_ONLY
24802 {
24803 uint32_t op2;
24804 TCGv t0 = tcg_temp_new();
24805
24806 op2 = MASK_MFMC0(ctx->opcode);
24807 switch (op2) {
24808 case OPC_DMT:
24809 check_cp0_mt(ctx);
24810 gen_helper_dmt(t0);
24811 gen_store_gpr(t0, rt);
24812 break;
24813 case OPC_EMT:
24814 check_cp0_mt(ctx);
24815 gen_helper_emt(t0);
24816 gen_store_gpr(t0, rt);
24817 break;
24818 case OPC_DVPE:
24819 check_cp0_mt(ctx);
24820 gen_helper_dvpe(t0, cpu_env);
24821 gen_store_gpr(t0, rt);
24822 break;
24823 case OPC_EVPE:
24824 check_cp0_mt(ctx);
24825 gen_helper_evpe(t0, cpu_env);
24826 gen_store_gpr(t0, rt);
24827 break;
24828 case OPC_DVP:
24829 check_insn(ctx, ISA_MIPS_R6);
24830 if (ctx->vp) {
24831 gen_helper_dvp(t0, cpu_env);
24832 gen_store_gpr(t0, rt);
24833 }
24834 break;
24835 case OPC_EVP:
24836 check_insn(ctx, ISA_MIPS_R6);
24837 if (ctx->vp) {
24838 gen_helper_evp(t0, cpu_env);
24839 gen_store_gpr(t0, rt);
24840 }
24841 break;
24842 case OPC_DI:
24843 check_insn(ctx, ISA_MIPS_R2);
24844 save_cpu_state(ctx, 1);
24845 gen_helper_di(t0, cpu_env);
24846 gen_store_gpr(t0, rt);
24847 /*
24848 * Stop translation as we may have switched
24849 * the execution mode.
24850 */
24851 ctx->base.is_jmp = DISAS_STOP;
24852 break;
24853 case OPC_EI:
24854 check_insn(ctx, ISA_MIPS_R2);
24855 save_cpu_state(ctx, 1);
24856 gen_helper_ei(t0, cpu_env);
24857 gen_store_gpr(t0, rt);
24858 /*
24859 * DISAS_STOP isn't sufficient, we need to ensure we break
24860 * out of translated code to check for pending interrupts.
24861 */
24862 gen_save_pc(ctx->base.pc_next + 4);
24863 ctx->base.is_jmp = DISAS_EXIT;
24864 break;
24865 default: /* Invalid */
24866 MIPS_INVAL("mfmc0");
24867 gen_reserved_instruction(ctx);
24868 break;
24869 }
24870 tcg_temp_free(t0);
24871 }
24872 #endif /* !CONFIG_USER_ONLY */
24873 break;
24874 case OPC_RDPGPR:
24875 check_insn(ctx, ISA_MIPS_R2);
24876 gen_load_srsgpr(rt, rd);
24877 break;
24878 case OPC_WRPGPR:
24879 check_insn(ctx, ISA_MIPS_R2);
24880 gen_store_srsgpr(rt, rd);
24881 break;
24882 default:
24883 MIPS_INVAL("cp0");
24884 gen_reserved_instruction(ctx);
24885 break;
24886 }
24887 break;
24888 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */
24889 if (ctx->insn_flags & ISA_MIPS_R6) {
24890 /* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */
24891 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
24892 } else {
24893 /* OPC_ADDI */
24894 /* Arithmetic with immediate opcode */
24895 gen_arith_imm(ctx, op, rt, rs, imm);
24896 }
24897 break;
24898 case OPC_ADDIU:
24899 gen_arith_imm(ctx, op, rt, rs, imm);
24900 break;
24901 case OPC_SLTI: /* Set on less than with immediate opcode */
24902 case OPC_SLTIU:
24903 gen_slt_imm(ctx, op, rt, rs, imm);
24904 break;
24905 case OPC_ANDI: /* Arithmetic with immediate opcode */
24906 case OPC_LUI: /* OPC_AUI */
24907 case OPC_ORI:
24908 case OPC_XORI:
24909 gen_logic_imm(ctx, op, rt, rs, imm);
24910 break;
24911 case OPC_J: /* Jump */
24912 case OPC_JAL:
24913 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
24914 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
24915 break;
24916 /* Branch */
24917 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */
24918 if (ctx->insn_flags & ISA_MIPS_R6) {
24919 if (rt == 0) {
24920 gen_reserved_instruction(ctx);
24921 break;
24922 }
24923 /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */
24924 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
24925 } else {
24926 /* OPC_BLEZL */
24927 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
24928 }
24929 break;
24930 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */
24931 if (ctx->insn_flags & ISA_MIPS_R6) {
24932 if (rt == 0) {
24933 gen_reserved_instruction(ctx);
24934 break;
24935 }
24936 /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */
24937 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
24938 } else {
24939 /* OPC_BGTZL */
24940 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
24941 }
24942 break;
24943 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC, OPC_BLEZ */
24944 if (rt == 0) {
24945 /* OPC_BLEZ */
24946 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
24947 } else {
24948 check_insn(ctx, ISA_MIPS_R6);
24949 /* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */
24950 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
24951 }
24952 break;
24953 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC, OPC_BGTZ */
24954 if (rt == 0) {
24955 /* OPC_BGTZ */
24956 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
24957 } else {
24958 check_insn(ctx, ISA_MIPS_R6);
24959 /* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */
24960 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
24961 }
24962 break;
24963 case OPC_BEQL:
24964 case OPC_BNEL:
24965 check_insn(ctx, ISA_MIPS2);
24966 check_insn_opc_removed(ctx, ISA_MIPS_R6);
24967 /* Fallthrough */
24968 case OPC_BEQ:
24969 case OPC_BNE:
24970 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
24971 break;
24972 case OPC_LL: /* Load and stores */
24973 check_insn(ctx, ISA_MIPS2);
24974 if (ctx->insn_flags & INSN_R5900) {
24975 check_insn_opc_user_only(ctx, INSN_R5900);
24976 }
24977 /* Fallthrough */
24978 case OPC_LWL:
24979 case OPC_LWR:
24980 case OPC_LB:
24981 case OPC_LH:
24982 case OPC_LW:
24983 case OPC_LWPC:
24984 case OPC_LBU:
24985 case OPC_LHU:
24986 gen_ld(ctx, op, rt, rs, imm);
24987 break;
24988 case OPC_SWL:
24989 case OPC_SWR:
24990 case OPC_SB:
24991 case OPC_SH:
24992 case OPC_SW:
24993 gen_st(ctx, op, rt, rs, imm);
24994 break;
24995 case OPC_SC:
24996 check_insn(ctx, ISA_MIPS2);
24997 if (ctx->insn_flags & INSN_R5900) {
24998 check_insn_opc_user_only(ctx, INSN_R5900);
24999 }
25000 gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
25001 break;
25002 case OPC_CACHE:
25003 check_cp0_enabled(ctx);
25004 check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
25005 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
25006 gen_cache_operation(ctx, rt, rs, imm);
25007 }
25008 /* Treat as NOP. */
25009 break;
25010 case OPC_PREF:
25011 if (ctx->insn_flags & INSN_R5900) {
25012 /* Treat as NOP. */
25013 } else {
25014 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
25015 /* Treat as NOP. */
25016 }
25017 break;
25018
25019 /* Floating point (COP1). */
25020 case OPC_LWC1:
25021 case OPC_LDC1:
25022 case OPC_SWC1:
25023 case OPC_SDC1:
25024 gen_cop1_ldst(ctx, op, rt, rs, imm);
25025 break;
25026
25027 case OPC_CP1:
25028 op1 = MASK_CP1(ctx->opcode);
25029
25030 switch (op1) {
25031 case OPC_MFHC1:
25032 case OPC_MTHC1:
25033 check_cp1_enabled(ctx);
25034 check_insn(ctx, ISA_MIPS_R2);
25035 /* fall through */
25036 case OPC_MFC1:
25037 case OPC_CFC1:
25038 case OPC_MTC1:
25039 case OPC_CTC1:
25040 check_cp1_enabled(ctx);
25041 gen_cp1(ctx, op1, rt, rd);
25042 break;
25043 #if defined(TARGET_MIPS64)
25044 case OPC_DMFC1:
25045 case OPC_DMTC1:
25046 check_cp1_enabled(ctx);
25047 check_insn(ctx, ISA_MIPS3);
25048 check_mips_64(ctx);
25049 gen_cp1(ctx, op1, rt, rd);
25050 break;
25051 #endif
25052 case OPC_BC1EQZ: /* OPC_BC1ANY2 */
25053 check_cp1_enabled(ctx);
25054 if (ctx->insn_flags & ISA_MIPS_R6) {
25055 /* OPC_BC1EQZ */
25056 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
25057 rt, imm << 2, 4);
25058 } else {
25059 /* OPC_BC1ANY2 */
25060 check_cop1x(ctx);
25061 check_insn(ctx, ASE_MIPS3D);
25062 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
25063 (rt >> 2) & 0x7, imm << 2);
25064 }
25065 break;
25066 case OPC_BC1NEZ:
25067 check_cp1_enabled(ctx);
25068 check_insn(ctx, ISA_MIPS_R6);
25069 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
25070 rt, imm << 2, 4);
25071 break;
25072 case OPC_BC1ANY4:
25073 check_cp1_enabled(ctx);
25074 check_insn_opc_removed(ctx, ISA_MIPS_R6);
25075 check_cop1x(ctx);
25076 check_insn(ctx, ASE_MIPS3D);
25077 /* fall through */
25078 case OPC_BC1:
25079 check_cp1_enabled(ctx);
25080 check_insn_opc_removed(ctx, ISA_MIPS_R6);
25081 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
25082 (rt >> 2) & 0x7, imm << 2);
25083 break;
25084 case OPC_PS_FMT:
25085 check_ps(ctx);
25086 /* fall through */
25087 case OPC_S_FMT:
25088 case OPC_D_FMT:
25089 check_cp1_enabled(ctx);
25090 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
25091 (imm >> 8) & 0x7);
25092 break;
25093 case OPC_W_FMT:
25094 case OPC_L_FMT:
25095 {
25096 int r6_op = ctx->opcode & FOP(0x3f, 0x1f);
25097 check_cp1_enabled(ctx);
25098 if (ctx->insn_flags & ISA_MIPS_R6) {
25099 switch (r6_op) {
25100 case R6_OPC_CMP_AF_S:
25101 case R6_OPC_CMP_UN_S:
25102 case R6_OPC_CMP_EQ_S:
25103 case R6_OPC_CMP_UEQ_S:
25104 case R6_OPC_CMP_LT_S:
25105 case R6_OPC_CMP_ULT_S:
25106 case R6_OPC_CMP_LE_S:
25107 case R6_OPC_CMP_ULE_S:
25108 case R6_OPC_CMP_SAF_S:
25109 case R6_OPC_CMP_SUN_S:
25110 case R6_OPC_CMP_SEQ_S:
25111 case R6_OPC_CMP_SEUQ_S:
25112 case R6_OPC_CMP_SLT_S:
25113 case R6_OPC_CMP_SULT_S:
25114 case R6_OPC_CMP_SLE_S:
25115 case R6_OPC_CMP_SULE_S:
25116 case R6_OPC_CMP_OR_S:
25117 case R6_OPC_CMP_UNE_S:
25118 case R6_OPC_CMP_NE_S:
25119 case R6_OPC_CMP_SOR_S:
25120 case R6_OPC_CMP_SUNE_S:
25121 case R6_OPC_CMP_SNE_S:
25122 gen_r6_cmp_s(ctx, ctx->opcode & 0x1f, rt, rd, sa);
25123 break;
25124 case R6_OPC_CMP_AF_D:
25125 case R6_OPC_CMP_UN_D:
25126 case R6_OPC_CMP_EQ_D:
25127 case R6_OPC_CMP_UEQ_D:
25128 case R6_OPC_CMP_LT_D:
25129 case R6_OPC_CMP_ULT_D:
25130 case R6_OPC_CMP_LE_D:
25131 case R6_OPC_CMP_ULE_D:
25132 case R6_OPC_CMP_SAF_D:
25133 case R6_OPC_CMP_SUN_D:
25134 case R6_OPC_CMP_SEQ_D:
25135 case R6_OPC_CMP_SEUQ_D:
25136 case R6_OPC_CMP_SLT_D:
25137 case R6_OPC_CMP_SULT_D:
25138 case R6_OPC_CMP_SLE_D:
25139 case R6_OPC_CMP_SULE_D:
25140 case R6_OPC_CMP_OR_D:
25141 case R6_OPC_CMP_UNE_D:
25142 case R6_OPC_CMP_NE_D:
25143 case R6_OPC_CMP_SOR_D:
25144 case R6_OPC_CMP_SUNE_D:
25145 case R6_OPC_CMP_SNE_D:
25146 gen_r6_cmp_d(ctx, ctx->opcode & 0x1f, rt, rd, sa);
25147 break;
25148 default:
25149 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f),
25150 rt, rd, sa, (imm >> 8) & 0x7);
25151
25152 break;
25153 }
25154 } else {
25155 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
25156 (imm >> 8) & 0x7);
25157 }
25158 break;
25159 }
25160 default:
25161 MIPS_INVAL("cp1");
25162 gen_reserved_instruction(ctx);
25163 break;
25164 }
25165 break;
25166
25167 /* Compact branches [R6] and COP2 [non-R6] */
25168 case OPC_BC: /* OPC_LWC2 */
25169 case OPC_BALC: /* OPC_SWC2 */
25170 if (ctx->insn_flags & ISA_MIPS_R6) {
25171 /* OPC_BC, OPC_BALC */
25172 gen_compute_compact_branch(ctx, op, 0, 0,
25173 sextract32(ctx->opcode << 2, 0, 28));
25174 } else if (ctx->insn_flags & ASE_LEXT) {
25175 gen_loongson_lswc2(ctx, rt, rs, rd);
25176 } else {
25177 /* OPC_LWC2, OPC_SWC2 */
25178 /* COP2: Not implemented. */
25179 generate_exception_err(ctx, EXCP_CpU, 2);
25180 }
25181 break;
25182 case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */
25183 case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */
25184 if (ctx->insn_flags & ISA_MIPS_R6) {
25185 if (rs != 0) {
25186 /* OPC_BEQZC, OPC_BNEZC */
25187 gen_compute_compact_branch(ctx, op, rs, 0,
25188 sextract32(ctx->opcode << 2, 0, 23));
25189 } else {
25190 /* OPC_JIC, OPC_JIALC */
25191 gen_compute_compact_branch(ctx, op, 0, rt, imm);
25192 }
25193 } else if (ctx->insn_flags & ASE_LEXT) {
25194 gen_loongson_lsdc2(ctx, rt, rs, rd);
25195 } else {
25196 /* OPC_LWC2, OPC_SWC2 */
25197 /* COP2: Not implemented. */
25198 generate_exception_err(ctx, EXCP_CpU, 2);
25199 }
25200 break;
25201 case OPC_CP2:
25202 check_insn(ctx, ASE_LMMI);
25203 /* Note that these instructions use different fields. */
25204 gen_loongson_multimedia(ctx, sa, rd, rt);
25205 break;
25206
25207 case OPC_CP3:
25208 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
25209 check_cp1_enabled(ctx);
25210 op1 = MASK_CP3(ctx->opcode);
25211 switch (op1) {
25212 case OPC_LUXC1:
25213 case OPC_SUXC1:
25214 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
25215 /* Fallthrough */
25216 case OPC_LWXC1:
25217 case OPC_LDXC1:
25218 case OPC_SWXC1:
25219 case OPC_SDXC1:
25220 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
25221 gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
25222 break;
25223 case OPC_PREFX:
25224 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
25225 /* Treat as NOP. */
25226 break;
25227 case OPC_ALNV_PS:
25228 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
25229 /* Fallthrough */
25230 case OPC_MADD_S:
25231 case OPC_MADD_D:
25232 case OPC_MADD_PS:
25233 case OPC_MSUB_S:
25234 case OPC_MSUB_D:
25235 case OPC_MSUB_PS:
25236 case OPC_NMADD_S:
25237 case OPC_NMADD_D:
25238 case OPC_NMADD_PS:
25239 case OPC_NMSUB_S:
25240 case OPC_NMSUB_D:
25241 case OPC_NMSUB_PS:
25242 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
25243 gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
25244 break;
25245 default:
25246 MIPS_INVAL("cp3");
25247 gen_reserved_instruction(ctx);
25248 break;
25249 }
25250 } else {
25251 generate_exception_err(ctx, EXCP_CpU, 1);
25252 }
25253 break;
25254
25255 #if defined(TARGET_MIPS64)
25256 /* MIPS64 opcodes */
25257 case OPC_LLD:
25258 if (ctx->insn_flags & INSN_R5900) {
25259 check_insn_opc_user_only(ctx, INSN_R5900);
25260 }
25261 /* fall through */
25262 case OPC_LDL:
25263 case OPC_LDR:
25264 case OPC_LWU:
25265 case OPC_LD:
25266 check_insn(ctx, ISA_MIPS3);
25267 check_mips_64(ctx);
25268 gen_ld(ctx, op, rt, rs, imm);
25269 break;
25270 case OPC_SDL:
25271 case OPC_SDR:
25272 case OPC_SD:
25273 check_insn(ctx, ISA_MIPS3);
25274 check_mips_64(ctx);
25275 gen_st(ctx, op, rt, rs, imm);
25276 break;
25277 case OPC_SCD:
25278 check_insn(ctx, ISA_MIPS3);
25279 if (ctx->insn_flags & INSN_R5900) {
25280 check_insn_opc_user_only(ctx, INSN_R5900);
25281 }
25282 check_mips_64(ctx);
25283 gen_st_cond(ctx, rt, rs, imm, MO_TEQ, false);
25284 break;
25285 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
25286 if (ctx->insn_flags & ISA_MIPS_R6) {
25287 /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
25288 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
25289 } else {
25290 /* OPC_DADDI */
25291 check_insn(ctx, ISA_MIPS3);
25292 check_mips_64(ctx);
25293 gen_arith_imm(ctx, op, rt, rs, imm);
25294 }
25295 break;
25296 case OPC_DADDIU:
25297 check_insn(ctx, ISA_MIPS3);
25298 check_mips_64(ctx);
25299 gen_arith_imm(ctx, op, rt, rs, imm);
25300 break;
25301 #else
25302 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
25303 if (ctx->insn_flags & ISA_MIPS_R6) {
25304 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
25305 } else {
25306 MIPS_INVAL("major opcode");
25307 gen_reserved_instruction(ctx);
25308 }
25309 break;
25310 #endif
25311 case OPC_DAUI: /* OPC_JALX */
25312 if (ctx->insn_flags & ISA_MIPS_R6) {
25313 #if defined(TARGET_MIPS64)
25314 /* OPC_DAUI */
25315 check_mips_64(ctx);
25316 if (rs == 0) {
25317 generate_exception(ctx, EXCP_RI);
25318 } else if (rt != 0) {
25319 TCGv t0 = tcg_temp_new();
25320 gen_load_gpr(t0, rs);
25321 tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);
25322 tcg_temp_free(t0);
25323 }
25324 #else
25325 gen_reserved_instruction(ctx);
25326 MIPS_INVAL("major opcode");
25327 #endif
25328 } else {
25329 /* OPC_JALX */
25330 check_insn(ctx, ASE_MIPS16 | ASE_MICROMIPS);
25331 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
25332 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
25333 }
25334 break;
25335 case OPC_MDMX: /* MMI_OPC_LQ */
25336 if (ctx->insn_flags & INSN_R5900) {
25337 #if defined(TARGET_MIPS64)
25338 gen_mmi_lq(env, ctx);
25339 #endif
25340 } else {
25341 /* MDMX: Not implemented. */
25342 }
25343 break;
25344 case OPC_PCREL:
25345 check_insn(ctx, ISA_MIPS_R6);
25346 gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs);
25347 break;
25348 default: /* Invalid */
25349 MIPS_INVAL("major opcode");
25350 return false;
25351 }
25352 return true;
25353 }
25354
25355 static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
25356 {
25357 /* make sure instructions are on a word boundary */
25358 if (ctx->base.pc_next & 0x3) {
25359 env->CP0_BadVAddr = ctx->base.pc_next;
25360 generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL);
25361 return;
25362 }
25363
25364 /* Handle blikely not taken case */
25365 if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) {
25366 TCGLabel *l1 = gen_new_label();
25367
25368 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
25369 tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
25370 gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
25371 gen_set_label(l1);
25372 }
25373
25374 /* Transition to the auto-generated decoder. */
25375
25376 /* ISA extensions */
25377 if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
25378 return;
25379 }
25380
25381 /* ISA (from latest to oldest) */
25382 if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) {
25383 return;
25384 }
25385 if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) {
25386 return;
25387 }
25388
25389 if (decode_opc_legacy(env, ctx)) {
25390 return;
25391 }
25392
25393 gen_reserved_instruction(ctx);
25394 }
25395
25396 static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
25397 {
25398 DisasContext *ctx = container_of(dcbase, DisasContext, base);
25399 CPUMIPSState *env = cs->env_ptr;
25400
25401 ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
25402 ctx->saved_pc = -1;
25403 ctx->insn_flags = env->insn_flags;
25404 ctx->CP0_Config1 = env->CP0_Config1;
25405 ctx->CP0_Config2 = env->CP0_Config2;
25406 ctx->CP0_Config3 = env->CP0_Config3;
25407 ctx->CP0_Config5 = env->CP0_Config5;
25408 ctx->btarget = 0;
25409 ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
25410 ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
25411 ctx->ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
25412 ctx->bi = (env->CP0_Config3 >> CP0C3_BI) & 1;
25413 ctx->bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
25414 ctx->PAMask = env->PAMask;
25415 ctx->mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1;
25416 ctx->eva = (env->CP0_Config5 >> CP0C5_EVA) & 1;
25417 ctx->sc = (env->CP0_Config3 >> CP0C3_SC) & 1;
25418 ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift;
25419 ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
25420 /* Restore delay slot state from the tb context. */
25421 ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 bits? */
25422 ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
25423 ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
25424 (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
25425 ctx->vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
25426 ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
25427 ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
25428 ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
25429 ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1;
25430 ctx->gi = (env->CP0_Config5 >> CP0C5_GI) & 3;
25431 restore_cpu_state(env, ctx);
25432 #ifdef CONFIG_USER_ONLY
25433 ctx->mem_idx = MIPS_HFLAG_UM;
25434 #else
25435 ctx->mem_idx = hflags_mmu_index(ctx->hflags);
25436 #endif
25437 ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
25438 INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
25439
25440 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
25441 ctx->hflags);
25442 }
25443
25444 static void mips_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
25445 {
25446 }
25447
25448 static void mips_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
25449 {
25450 DisasContext *ctx = container_of(dcbase, DisasContext, base);
25451
25452 tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK,
25453 ctx->btarget);
25454 }
25455
25456 static bool mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
25457 const CPUBreakpoint *bp)
25458 {
25459 DisasContext *ctx = container_of(dcbase, DisasContext, base);
25460
25461 save_cpu_state(ctx, 1);
25462 ctx->base.is_jmp = DISAS_NORETURN;
25463 gen_helper_raise_exception_debug(cpu_env);
25464 /*
25465 * The address covered by the breakpoint must be included in
25466 * [tb->pc, tb->pc + tb->size) in order to for it to be
25467 * properly cleared -- thus we increment the PC here so that
25468 * the logic setting tb->size below does the right thing.
25469 */
25470 ctx->base.pc_next += 4;
25471 return true;
25472 }
25473
25474 static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
25475 {
25476 CPUMIPSState *env = cs->env_ptr;
25477 DisasContext *ctx = container_of(dcbase, DisasContext, base);
25478 int insn_bytes;
25479 int is_slot;
25480
25481 is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
25482 if (ctx->insn_flags & ISA_NANOMIPS32) {
25483 ctx->opcode = translator_lduw(env, ctx->base.pc_next);
25484 insn_bytes = decode_nanomips_opc(env, ctx);
25485 } else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
25486 ctx->opcode = translator_ldl(env, ctx->base.pc_next);
25487 insn_bytes = 4;
25488 decode_opc(env, ctx);
25489 } else if (ctx->insn_flags & ASE_MICROMIPS) {
25490 ctx->opcode = translator_lduw(env, ctx->base.pc_next);
25491 insn_bytes = decode_micromips_opc(env, ctx);
25492 } else if (ctx->insn_flags & ASE_MIPS16) {
25493 ctx->opcode = translator_lduw(env, ctx->base.pc_next);
25494 insn_bytes = decode_mips16_opc(env, ctx);
25495 } else {
25496 gen_reserved_instruction(ctx);
25497 g_assert(ctx->base.is_jmp == DISAS_NORETURN);
25498 return;
25499 }
25500
25501 if (ctx->hflags & MIPS_HFLAG_BMASK) {
25502 if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
25503 MIPS_HFLAG_FBNSLOT))) {
25504 /*
25505 * Force to generate branch as there is neither delay nor
25506 * forbidden slot.
25507 */
25508 is_slot = 1;
25509 }
25510 if ((ctx->hflags & MIPS_HFLAG_M16) &&
25511 (ctx->hflags & MIPS_HFLAG_FBNSLOT)) {
25512 /*
25513 * Force to generate branch as microMIPS R6 doesn't restrict
25514 * branches in the forbidden slot.
25515 */
25516 is_slot = 1;
25517 }
25518 }
25519 if (is_slot) {
25520 gen_branch(ctx, insn_bytes);
25521 }
25522 ctx->base.pc_next += insn_bytes;
25523
25524 if (ctx->base.is_jmp != DISAS_NEXT) {
25525 return;
25526 }
25527 /*
25528 * Execute a branch and its delay slot as a single instruction.
25529 * This is what GDB expects and is consistent with what the
25530 * hardware does (e.g. if a delay slot instruction faults, the
25531 * reported PC is the PC of the branch).
25532 */
25533 if (ctx->base.singlestep_enabled &&
25534 (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
25535 ctx->base.is_jmp = DISAS_TOO_MANY;
25536 }
25537 if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE) {
25538 ctx->base.is_jmp = DISAS_TOO_MANY;
25539 }
25540 }
25541
25542 static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
25543 {
25544 DisasContext *ctx = container_of(dcbase, DisasContext, base);
25545
25546 if (ctx->base.singlestep_enabled && ctx->base.is_jmp != DISAS_NORETURN) {
25547 save_cpu_state(ctx, ctx->base.is_jmp != DISAS_EXIT);
25548 gen_helper_raise_exception_debug(cpu_env);
25549 } else {
25550 switch (ctx->base.is_jmp) {
25551 case DISAS_STOP:
25552 gen_save_pc(ctx->base.pc_next);
25553 tcg_gen_lookup_and_goto_ptr();
25554 break;
25555 case DISAS_NEXT:
25556 case DISAS_TOO_MANY:
25557 save_cpu_state(ctx, 0);
25558 gen_goto_tb(ctx, 0, ctx->base.pc_next);
25559 break;
25560 case DISAS_EXIT:
25561 tcg_gen_exit_tb(NULL, 0);
25562 break;
25563 case DISAS_NORETURN:
25564 break;
25565 default:
25566 g_assert_not_reached();
25567 }
25568 }
25569 }
25570
25571 static void mips_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
25572 {
25573 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
25574 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
25575 }
25576
25577 static const TranslatorOps mips_tr_ops = {
25578 .init_disas_context = mips_tr_init_disas_context,
25579 .tb_start = mips_tr_tb_start,
25580 .insn_start = mips_tr_insn_start,
25581 .breakpoint_check = mips_tr_breakpoint_check,
25582 .translate_insn = mips_tr_translate_insn,
25583 .tb_stop = mips_tr_tb_stop,
25584 .disas_log = mips_tr_disas_log,
25585 };
25586
25587 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
25588 {
25589 DisasContext ctx;
25590
25591 translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns);
25592 }
25593
25594 static void fpu_dump_state(CPUMIPSState *env, FILE * f, int flags)
25595 {
25596 int i;
25597 int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
25598
25599 #define printfpr(fp) \
25600 do { \
25601 if (is_fpu64) \
25602 qemu_fprintf(f, "w:%08x d:%016" PRIx64 \
25603 " fd:%13g fs:%13g psu: %13g\n", \
25604 (fp)->w[FP_ENDIAN_IDX], (fp)->d, \
25605 (double)(fp)->fd, \
25606 (double)(fp)->fs[FP_ENDIAN_IDX], \
25607 (double)(fp)->fs[!FP_ENDIAN_IDX]); \
25608 else { \
25609 fpr_t tmp; \
25610 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
25611 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
25612 qemu_fprintf(f, "w:%08x d:%016" PRIx64 \
25613 " fd:%13g fs:%13g psu:%13g\n", \
25614 tmp.w[FP_ENDIAN_IDX], tmp.d, \
25615 (double)tmp.fd, \
25616 (double)tmp.fs[FP_ENDIAN_IDX], \
25617 (double)tmp.fs[!FP_ENDIAN_IDX]); \
25618 } \
25619 } while (0)
25620
25621
25622 qemu_fprintf(f,
25623 "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
25624 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
25625 get_float_exception_flags(&env->active_fpu.fp_status));
25626 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
25627 qemu_fprintf(f, "%3s: ", fregnames[i]);
25628 printfpr(&env->active_fpu.fpr[i]);
25629 }
25630
25631 #undef printfpr
25632 }
25633
25634 void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
25635 {
25636 MIPSCPU *cpu = MIPS_CPU(cs);
25637 CPUMIPSState *env = &cpu->env;
25638 int i;
25639
25640 qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
25641 " LO=0x" TARGET_FMT_lx " ds %04x "
25642 TARGET_FMT_lx " " TARGET_FMT_ld "\n",
25643 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
25644 env->hflags, env->btarget, env->bcond);
25645 for (i = 0; i < 32; i++) {
25646 if ((i & 3) == 0) {
25647 qemu_fprintf(f, "GPR%02d:", i);
25648 }
25649 qemu_fprintf(f, " %s " TARGET_FMT_lx,
25650 regnames[i], env->active_tc.gpr[i]);
25651 if ((i & 3) == 3) {
25652 qemu_fprintf(f, "\n");
25653 }
25654 }
25655
25656 qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x"
25657 TARGET_FMT_lx "\n",
25658 env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
25659 qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
25660 PRIx64 "\n",
25661 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
25662 qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n",
25663 env->CP0_Config2, env->CP0_Config3);
25664 qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n",
25665 env->CP0_Config4, env->CP0_Config5);
25666 if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
25667 fpu_dump_state(env, f, flags);
25668 }
25669 }
25670
25671 void mips_tcg_init(void)
25672 {
25673 int i;
25674
25675 cpu_gpr[0] = NULL;
25676 for (i = 1; i < 32; i++)
25677 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
25678 offsetof(CPUMIPSState,
25679 active_tc.gpr[i]),
25680 regnames[i]);
25681 #if defined(TARGET_MIPS64)
25682 cpu_gpr_hi[0] = NULL;
25683
25684 for (unsigned i = 1; i < 32; i++) {
25685 g_autofree char *rname = g_strdup_printf("%s[hi]", regnames[i]);
25686
25687 cpu_gpr_hi[i] = tcg_global_mem_new_i64(cpu_env,
25688 offsetof(CPUMIPSState,
25689 active_tc.gpr_hi[i]),
25690 rname);
25691 }
25692 #endif /* !TARGET_MIPS64 */
25693 for (i = 0; i < 32; i++) {
25694 int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
25695
25696 fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
25697 }
25698 msa_translate_init();
25699 cpu_PC = tcg_global_mem_new(cpu_env,
25700 offsetof(CPUMIPSState, active_tc.PC), "PC");
25701 for (i = 0; i < MIPS_DSP_ACC; i++) {
25702 cpu_HI[i] = tcg_global_mem_new(cpu_env,
25703 offsetof(CPUMIPSState, active_tc.HI[i]),
25704 regnames_HI[i]);
25705 cpu_LO[i] = tcg_global_mem_new(cpu_env,
25706 offsetof(CPUMIPSState, active_tc.LO[i]),
25707 regnames_LO[i]);
25708 }
25709 cpu_dspctrl = tcg_global_mem_new(cpu_env,
25710 offsetof(CPUMIPSState,
25711 active_tc.DSPControl),
25712 "DSPControl");
25713 bcond = tcg_global_mem_new(cpu_env,
25714 offsetof(CPUMIPSState, bcond), "bcond");
25715 btarget = tcg_global_mem_new(cpu_env,
25716 offsetof(CPUMIPSState, btarget), "btarget");
25717 hflags = tcg_global_mem_new_i32(cpu_env,
25718 offsetof(CPUMIPSState, hflags), "hflags");
25719
25720 fpu_fcr0 = tcg_global_mem_new_i32(cpu_env,
25721 offsetof(CPUMIPSState, active_fpu.fcr0),
25722 "fcr0");
25723 fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
25724 offsetof(CPUMIPSState, active_fpu.fcr31),
25725 "fcr31");
25726 cpu_lladdr = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, lladdr),
25727 "lladdr");
25728 cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval),
25729 "llval");
25730
25731 if (TARGET_LONG_BITS == 32) {
25732 mxu_translate_init();
25733 }
25734 }
25735
25736 void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb,
25737 target_ulong *data)
25738 {
25739 env->active_tc.PC = data[0];
25740 env->hflags &= ~MIPS_HFLAG_BMASK;
25741 env->hflags |= data[1];
25742 switch (env->hflags & MIPS_HFLAG_BMASK_BASE) {
25743 case MIPS_HFLAG_BR:
25744 break;
25745 case MIPS_HFLAG_BC:
25746 case MIPS_HFLAG_BL:
25747 case MIPS_HFLAG_B:
25748 env->btarget = data[2];
25749 break;
25750 }
25751 }
AR7 emulation for QEMU