target/m68k/cpu.h

   1 /*
   2  * m68k virtual CPU header
   3  *
   4  *  Copyright (c) 2005-2007 CodeSourcery
   5  *  Written by Paul Brook
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef M68K_CPU_H
  22 #define M68K_CPU_H
  23
  24 #define TARGET_LONG_BITS 32
  25
  26 #define CPUArchState struct CPUM68KState
  27
  28 #include "qemu-common.h"
  29 #include "exec/cpu-defs.h"
  30 #include "cpu-qom.h"
  31 #include "fpu/softfloat.h"
  32
  33 #define OS_BYTE     0
  34 #define OS_WORD     1
  35 #define OS_LONG     2
  36 #define OS_SINGLE   3
  37 #define OS_DOUBLE   4
  38 #define OS_EXTENDED 5
  39 #define OS_PACKED   6
  40 #define OS_UNSIZED  7
  41
  42 #define MAX_QREGS 32
  43
  44 #define EXCP_ACCESS         2   /* Access (MMU) error.  */
  45 #define EXCP_ADDRESS        3   /* Address error.  */
  46 #define EXCP_ILLEGAL        4   /* Illegal instruction.  */
  47 #define EXCP_DIV0           5   /* Divide by zero */
  48 #define EXCP_CHK            6   /* CHK, CHK2 Instructions */
  49 #define EXCP_TRAPCC         7   /* FTRAPcc, TRAPcc, TRAPV Instructions */
  50 #define EXCP_PRIVILEGE      8   /* Privilege violation.  */
  51 #define EXCP_TRACE          9
  52 #define EXCP_LINEA          10  /* Unimplemented line-A (MAC) opcode.  */
  53 #define EXCP_LINEF          11  /* Unimplemented line-F (FPU) opcode.  */
  54 #define EXCP_DEBUGNBP       12  /* Non-breakpoint debug interrupt.  */
  55 #define EXCP_DEBEGBP        13  /* Breakpoint debug interrupt.  */
  56 #define EXCP_FORMAT         14  /* RTE format error.  */
  57 #define EXCP_UNINITIALIZED  15
  58 #define EXCP_SPURIOUS       24  /* Spurious interrupt */
  59 #define EXCP_INT_LEVEL_1    25  /* Level 1 Interrupt autovector */
  60 #define EXCP_INT_LEVEL_7    31  /* Level 7 Interrupt autovector */
  61 #define EXCP_TRAP0          32   /* User trap #0.  */
  62 #define EXCP_TRAP15         47   /* User trap #15.  */
  63 #define EXCP_FP_BSUN        48 /* Branch Set on Unordered */
  64 #define EXCP_FP_INEX        49 /* Inexact result */
  65 #define EXCP_FP_DZ          50 /* Divide by Zero */
  66 #define EXCP_FP_UNFL        51 /* Underflow */
  67 #define EXCP_FP_OPERR       52 /* Operand Error */
  68 #define EXCP_FP_OVFL        53 /* Overflow */
  69 #define EXCP_FP_SNAN        54 /* Signaling Not-A-Number */
  70 #define EXCP_FP_UNIMP       55 /* Unimplemented Data type */
  71 #define EXCP_MMU_CONF       56  /* MMU Configuration Error */
  72 #define EXCP_MMU_ILLEGAL    57  /* MMU Illegal Operation Error */
  73 #define EXCP_MMU_ACCESS     58  /* MMU Access Level Violation Error */
  74 #define EXCP_UNSUPPORTED    61
  75
  76 #define EXCP_RTE            0x100
  77 #define EXCP_HALT_INSN      0x101
  78
  79 #define M68K_DTTR0   0
  80 #define M68K_DTTR1   1
  81 #define M68K_ITTR0   2
  82 #define M68K_ITTR1   3
  83
  84 #define M68K_MAX_TTR 2
  85 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index]
  86
  87 #define NB_MMU_MODES 2
  88 #define TARGET_INSN_START_EXTRA_WORDS 1
  89
  90 typedef CPU_LDoubleU FPReg;
  91
  92 typedef struct CPUM68KState {
  93     uint32_t dregs[8];
  94     uint32_t aregs[8];
  95     uint32_t pc;
  96     uint32_t sr;
  97
  98     /* SSP and USP.  The current_sp is stored in aregs[7], the other here.  */
  99     int current_sp;
 100     uint32_t sp[3];
 101
 102     /* Condition flags.  */
 103     uint32_t cc_op;
 104     uint32_t cc_x; /* always 0/1 */
 105     uint32_t cc_n; /* in bit 31 (i.e. negative) */
 106     uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */
 107     uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */
 108     uint32_t cc_z; /* == 0 or unused */
 109
 110     FPReg fregs[8];
 111     FPReg fp_result;
 112     uint32_t fpcr;
 113     uint32_t fpsr;
 114     float_status fp_status;
 115
 116     uint64_t mactmp;
 117     /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
 118        two 8-bit parts.  We store a single 64-bit value and
 119        rearrange/extend this when changing modes.  */
 120     uint64_t macc[4];
 121     uint32_t macsr;
 122     uint32_t mac_mask;
 123
 124     /* MMU status.  */
 125     struct {
 126         uint32_t ar;
 127         uint32_t ssw;
 128         /* 68040 */
 129         uint16_t tcr;
 130         uint32_t urp;
 131         uint32_t srp;
 132         bool fault;
 133         uint32_t ttr[4];
 134         uint32_t mmusr;
 135     } mmu;
 136
 137     /* Control registers.  */
 138     uint32_t vbr;
 139     uint32_t mbar;
 140     uint32_t rambar0;
 141     uint32_t cacr;
 142     uint32_t sfc;
 143     uint32_t dfc;
 144
 145     int pending_vector;
 146     int pending_level;
 147
 148     uint32_t qregs[MAX_QREGS];
 149
 150     /* Fields up to this point are cleared by a CPU reset */
 151     struct {} end_reset_fields;
 152
 153     CPU_COMMON
 154
 155     /* Fields from here on are preserved across CPU reset. */
 156     uint32_t features;
 157 } CPUM68KState;
 158
 159 /**
 160  * M68kCPU:
 161  * @env: #CPUM68KState
 162  *
 163  * A Motorola 68k CPU.
 164  */
 165 struct M68kCPU {
 166     /*< private >*/
 167     CPUState parent_obj;
 168     /*< public >*/
 169
 170     CPUM68KState env;
 171 };
 172
 173 static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
 174 {
 175     return container_of(env, M68kCPU, env);
 176 }
 177
 178 #define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))
 179
 180 #define ENV_OFFSET offsetof(M68kCPU, env)
 181
 182 void m68k_cpu_do_interrupt(CPUState *cpu);
 183 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
 184 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 185                          int flags);
 186 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 187 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 188 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 189
 190 void m68k_tcg_init(void);
 191 void m68k_cpu_init_gdb(M68kCPU *cpu);
 192 /* you can call this signal handler from your SIGBUS and SIGSEGV
 193    signal handlers to inform the virtual CPU of exceptions. non zero
 194    is returned if the signal was handled by the virtual CPU.  */
 195 int cpu_m68k_signal_handler(int host_signum, void *pinfo,
 196                            void *puc);
 197 uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
 198 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
 199 void cpu_m68k_set_sr(CPUM68KState *env, uint32_t);
 200 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val);
 201
 202
 203 /* Instead of computing the condition codes after each m68k instruction,
 204  * QEMU just stores one operand (called CC_SRC), the result
 205  * (called CC_DEST) and the type of operation (called CC_OP). When the
 206  * condition codes are needed, the condition codes can be calculated
 207  * using this information. Condition codes are not generated if they
 208  * are only needed for conditional branches.
 209  */
 210 typedef enum {
 211     /* Translator only -- use env->cc_op.  */
 212     CC_OP_DYNAMIC,
 213
 214     /* Each flag bit computed into cc_[xcnvz].  */
 215     CC_OP_FLAGS,
 216
 217     /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v.  */
 218     CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL,
 219     CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL,
 220
 221     /* X in cc_x, {N,Z,C,V} via cc_n/cc_v.  */
 222     CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL,
 223
 224     /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n.  */
 225     CC_OP_LOGIC,
 226
 227     CC_OP_NB
 228 } CCOp;
 229
 230 #define CCF_C 0x01
 231 #define CCF_V 0x02
 232 #define CCF_Z 0x04
 233 #define CCF_N 0x08
 234 #define CCF_X 0x10
 235
 236 #define SR_I_SHIFT 8
 237 #define SR_I  0x0700
 238 #define SR_M  0x1000
 239 #define SR_S  0x2000
 240 #define SR_T_SHIFT 14
 241 #define SR_T  0xc000
 242
 243 #define M68K_SSP    0
 244 #define M68K_USP    1
 245 #define M68K_ISP    2
 246
 247 /* bits for 68040 special status word */
 248 #define M68K_CP_040  0x8000
 249 #define M68K_CU_040  0x4000
 250 #define M68K_CT_040  0x2000
 251 #define M68K_CM_040  0x1000
 252 #define M68K_MA_040  0x0800
 253 #define M68K_ATC_040 0x0400
 254 #define M68K_LK_040  0x0200
 255 #define M68K_RW_040  0x0100
 256 #define M68K_SIZ_040 0x0060
 257 #define M68K_TT_040  0x0018
 258 #define M68K_TM_040  0x0007
 259
 260 #define M68K_TM_040_DATA  0x0001
 261 #define M68K_TM_040_CODE  0x0002
 262 #define M68K_TM_040_SUPER 0x0004
 263
 264 /* bits for 68040 write back status word */
 265 #define M68K_WBV_040   0x80
 266 #define M68K_WBSIZ_040 0x60
 267 #define M68K_WBBYT_040 0x20
 268 #define M68K_WBWRD_040 0x40
 269 #define M68K_WBLNG_040 0x00
 270 #define M68K_WBTT_040  0x18
 271 #define M68K_WBTM_040  0x07
 272
 273 /* bus access size codes */
 274 #define M68K_BA_SIZE_MASK    0x60
 275 #define M68K_BA_SIZE_BYTE    0x20
 276 #define M68K_BA_SIZE_WORD    0x40
 277 #define M68K_BA_SIZE_LONG    0x00
 278 #define M68K_BA_SIZE_LINE    0x60
 279
 280 /* bus access transfer type codes */
 281 #define M68K_BA_TT_MOVE16    0x08
 282
 283 /* bits for 68040 MMU status register (mmusr) */
 284 #define M68K_MMU_B_040   0x0800
 285 #define M68K_MMU_G_040   0x0400
 286 #define M68K_MMU_U1_040  0x0200
 287 #define M68K_MMU_U0_040  0x0100
 288 #define M68K_MMU_S_040   0x0080
 289 #define M68K_MMU_CM_040  0x0060
 290 #define M68K_MMU_M_040   0x0010
 291 #define M68K_MMU_WP_040  0x0004
 292 #define M68K_MMU_T_040   0x0002
 293 #define M68K_MMU_R_040   0x0001
 294
 295 #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \
 296                               M68K_MMU_U0_040 | M68K_MMU_S_040 | \
 297                               M68K_MMU_CM_040 | M68K_MMU_M_040 | \
 298                               M68K_MMU_WP_040)
 299
 300 /* bits for 68040 MMU Translation Control Register */
 301 #define M68K_TCR_ENABLED 0x8000
 302 #define M68K_TCR_PAGE_8K 0x4000
 303
 304 /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */
 305 #define M68K_DESC_WRITEPROT 0x00000004
 306 #define M68K_DESC_USED      0x00000008
 307 #define M68K_DESC_MODIFIED  0x00000010
 308 #define M68K_DESC_CACHEMODE 0x00000060
 309 #define M68K_DESC_CM_WRTHRU 0x00000000
 310 #define M68K_DESC_CM_COPYBK 0x00000020
 311 #define M68K_DESC_CM_SERIAL 0x00000040
 312 #define M68K_DESC_CM_NCACHE 0x00000060
 313 #define M68K_DESC_SUPERONLY 0x00000080
 314 #define M68K_DESC_USERATTR  0x00000300
 315 #define M68K_DESC_USERATTR_SHIFT     8
 316 #define M68K_DESC_GLOBAL    0x00000400
 317 #define M68K_DESC_URESERVED 0x00000800
 318
 319 #define M68K_ROOT_POINTER_ENTRIES   128
 320 #define M68K_4K_PAGE_MASK           (~0xff)
 321 #define M68K_POINTER_BASE(entry)    (entry & ~0x1ff)
 322 #define M68K_ROOT_INDEX(addr)       ((address >> 23) & 0x1fc)
 323 #define M68K_POINTER_INDEX(addr)    ((address >> 16) & 0x1fc)
 324 #define M68K_4K_PAGE_BASE(entry)    (next & M68K_4K_PAGE_MASK)
 325 #define M68K_4K_PAGE_INDEX(addr)    ((address >> 10) & 0xfc)
 326 #define M68K_8K_PAGE_MASK           (~0x7f)
 327 #define M68K_8K_PAGE_BASE(entry)    (next & M68K_8K_PAGE_MASK)
 328 #define M68K_8K_PAGE_INDEX(addr)    ((address >> 11) & 0x7c)
 329 #define M68K_UDT_VALID(entry)       (entry & 2)
 330 #define M68K_PDT_VALID(entry)       (entry & 3)
 331 #define M68K_PDT_INDIRECT(entry)    ((entry & 3) == 2)
 332 #define M68K_INDIRECT_POINTER(addr) (addr & ~3)
 333 #define M68K_TTS_POINTER_SHIFT      18
 334 #define M68K_TTS_ROOT_SHIFT         25
 335
 336 /* bits for 68040 MMU Transparent Translation Registers */
 337 #define M68K_TTR_ADDR_BASE 0xff000000
 338 #define M68K_TTR_ADDR_MASK 0x00ff0000
 339 #define M68K_TTR_ADDR_MASK_SHIFT    8
 340 #define M68K_TTR_ENABLED   0x00008000
 341 #define M68K_TTR_SFIELD    0x00006000
 342 #define M68K_TTR_SFIELD_USER   0x0000
 343 #define M68K_TTR_SFIELD_SUPER  0x2000
 344
 345 /* m68k Control Registers */
 346
 347 /* ColdFire */
 348 /* Memory Management Control Registers */
 349 #define M68K_CR_ASID     0x003
 350 #define M68K_CR_ACR0     0x004
 351 #define M68K_CR_ACR1     0x005
 352 #define M68K_CR_ACR2     0x006
 353 #define M68K_CR_ACR3     0x007
 354 #define M68K_CR_MMUBAR   0x008
 355
 356 /* Processor Miscellaneous Registers */
 357 #define M68K_CR_PC       0x80F
 358
 359 /* Local Memory and Module Control Registers */
 360 #define M68K_CR_ROMBAR0  0xC00
 361 #define M68K_CR_ROMBAR1  0xC01
 362 #define M68K_CR_RAMBAR0  0xC04
 363 #define M68K_CR_RAMBAR1  0xC05
 364 #define M68K_CR_MPCR     0xC0C
 365 #define M68K_CR_EDRAMBAR 0xC0D
 366 #define M68K_CR_SECMBAR  0xC0E
 367 #define M68K_CR_MBAR     0xC0F
 368
 369 /* Local Memory Address Permutation Control Registers */
 370 #define M68K_CR_PCR1U0   0xD02
 371 #define M68K_CR_PCR1L0   0xD03
 372 #define M68K_CR_PCR2U0   0xD04
 373 #define M68K_CR_PCR2L0   0xD05
 374 #define M68K_CR_PCR3U0   0xD06
 375 #define M68K_CR_PCR3L0   0xD07
 376 #define M68K_CR_PCR1U1   0xD0A
 377 #define M68K_CR_PCR1L1   0xD0B
 378 #define M68K_CR_PCR2U1   0xD0C
 379 #define M68K_CR_PCR2L1   0xD0D
 380 #define M68K_CR_PCR3U1   0xD0E
 381 #define M68K_CR_PCR3L1   0xD0F
 382
 383 /* MC680x0 */
 384 /* MC680[1234]0/CPU32 */
 385 #define M68K_CR_SFC      0x000
 386 #define M68K_CR_DFC      0x001
 387 #define M68K_CR_USP      0x800
 388 #define M68K_CR_VBR      0x801 /* + Coldfire */
 389
 390 /* MC680[234]0 */
 391 #define M68K_CR_CACR     0x002 /* + Coldfire */
 392 #define M68K_CR_CAAR     0x802 /* MC68020 and MC68030 only */
 393 #define M68K_CR_MSP      0x803
 394 #define M68K_CR_ISP      0x804
 395
 396 /* MC68040/MC68LC040 */
 397 #define M68K_CR_TC       0x003
 398 #define M68K_CR_ITT0     0x004
 399 #define M68K_CR_ITT1     0x005
 400 #define M68K_CR_DTT0     0x006
 401 #define M68K_CR_DTT1     0x007
 402 #define M68K_CR_MMUSR    0x805
 403 #define M68K_CR_URP      0x806
 404 #define M68K_CR_SRP      0x807
 405
 406 /* MC68EC040 */
 407 #define M68K_CR_IACR0    0x004
 408 #define M68K_CR_IACR1    0x005
 409 #define M68K_CR_DACR0    0x006
 410 #define M68K_CR_DACR1    0x007
 411
 412 #define M68K_FPIAR_SHIFT  0
 413 #define M68K_FPIAR        (1 << M68K_FPIAR_SHIFT)
 414 #define M68K_FPSR_SHIFT   1
 415 #define M68K_FPSR         (1 << M68K_FPSR_SHIFT)
 416 #define M68K_FPCR_SHIFT   2
 417 #define M68K_FPCR         (1 << M68K_FPCR_SHIFT)
 418
 419 /* Floating-Point Status Register */
 420
 421 /* Condition Code */
 422 #define FPSR_CC_MASK  0x0f000000
 423 #define FPSR_CC_A     0x01000000 /* Not-A-Number */
 424 #define FPSR_CC_I     0x02000000 /* Infinity */
 425 #define FPSR_CC_Z     0x04000000 /* Zero */
 426 #define FPSR_CC_N     0x08000000 /* Negative */
 427
 428 /* Quotient */
 429
 430 #define FPSR_QT_MASK  0x00ff0000
 431
 432 /* Floating-Point Control Register */
 433 /* Rounding mode */
 434 #define FPCR_RND_MASK   0x0030
 435 #define FPCR_RND_N      0x0000
 436 #define FPCR_RND_Z      0x0010
 437 #define FPCR_RND_M      0x0020
 438 #define FPCR_RND_P      0x0030
 439
 440 /* Rounding precision */
 441 #define FPCR_PREC_MASK  0x00c0
 442 #define FPCR_PREC_X     0x0000
 443 #define FPCR_PREC_S     0x0040
 444 #define FPCR_PREC_D     0x0080
 445 #define FPCR_PREC_U     0x00c0
 446
 447 #define FPCR_EXCP_MASK 0xff00
 448
 449 /* CACR fields are implementation defined, but some bits are common.  */
 450 #define M68K_CACR_EUSP  0x10
 451
 452 #define MACSR_PAV0  0x100
 453 #define MACSR_OMC   0x080
 454 #define MACSR_SU    0x040
 455 #define MACSR_FI    0x020
 456 #define MACSR_RT    0x010
 457 #define MACSR_N     0x008
 458 #define MACSR_Z     0x004
 459 #define MACSR_V     0x002
 460 #define MACSR_EV    0x001
 461
 462 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
 463 void m68k_switch_sp(CPUM68KState *env);
 464
 465 void do_m68k_semihosting(CPUM68KState *env, int nr);
 466
 467 /* There are 4 ColdFire core ISA revisions: A, A+, B and C.
 468    Each feature covers the subset of instructions common to the
 469    ISA revisions mentioned.  */
 470
 471 enum m68k_features {
 472     M68K_FEATURE_M68000,
 473     M68K_FEATURE_CF_ISA_A,
 474     M68K_FEATURE_CF_ISA_B, /* (ISA B or C).  */
 475     M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).  */
 476     M68K_FEATURE_BRAL, /* Long unconditional branch.  (ISA A+ or B).  */
 477     M68K_FEATURE_CF_FPU,
 478     M68K_FEATURE_CF_MAC,
 479     M68K_FEATURE_CF_EMAC,
 480     M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate).  */
 481     M68K_FEATURE_USP, /* User Stack Pointer.  (ISA A+, B or C).  */
 482     M68K_FEATURE_EXT_FULL, /* 68020+ full extension word.  */
 483     M68K_FEATURE_WORD_INDEX, /* word sized address index registers.  */
 484     M68K_FEATURE_SCALED_INDEX, /* scaled address index registers.  */
 485     M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
 486     M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
 487     M68K_FEATURE_BCCL, /* Long conditional branches.  */
 488     M68K_FEATURE_BITFIELD, /* Bit field insns.  */
 489     M68K_FEATURE_FPU,
 490     M68K_FEATURE_CAS,
 491     M68K_FEATURE_BKPT,
 492     M68K_FEATURE_RTD,
 493     M68K_FEATURE_CHK2,
 494     M68K_FEATURE_M68040, /* instructions specific to MC68040 */
 495     M68K_FEATURE_MOVEP,
 496 };
 497
 498 static inline int m68k_feature(CPUM68KState *env, int feature)
 499 {
 500     return (env->features & (1u << feature)) != 0;
 501 }
 502
 503 void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 504
 505 void register_m68k_insns (CPUM68KState *env);
 506
 507 /* Coldfire Linux uses 8k pages
 508  * and m68k linux uses 4k pages
 509  * use the smallest one
 510  */
 511 #define TARGET_PAGE_BITS 12
 512
 513 enum {
 514     /* 1 bit to define user level / supervisor access */
 515     ACCESS_SUPER = 0x01,
 516     /* 1 bit to indicate direction */
 517     ACCESS_STORE = 0x02,
 518     /* 1 bit to indicate debug access */
 519     ACCESS_DEBUG = 0x04,
 520     /* PTEST instruction */
 521     ACCESS_PTEST = 0x08,
 522     /* Type of instruction that generated the access */
 523     ACCESS_CODE  = 0x10, /* Code fetch access                */
 524     ACCESS_DATA  = 0x20, /* Data load/store access        */
 525 };
 526
 527 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 528 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 529
 530 #define cpu_init(cpu_model) cpu_generic_init(TYPE_M68K_CPU, cpu_model)
 531
 532 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
 533 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
 534
 535 #define cpu_signal_handler cpu_m68k_signal_handler
 536 #define cpu_list m68k_cpu_list
 537
 538 /* MMU modes definitions */
 539 #define MMU_MODE0_SUFFIX _kernel
 540 #define MMU_MODE1_SUFFIX _user
 541 #define MMU_KERNEL_IDX 0
 542 #define MMU_USER_IDX 1
 543 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
 544 {
 545     return (env->sr & SR_S) == 0 ? 1 : 0;
 546 }
 547
 548 int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
 549                               int mmu_idx);
 550 void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr,
 551                                 bool is_write, bool is_exec, int is_asi,
 552                                 unsigned size);
 553
 554 #include "exec/cpu-all.h"
 555
 556 /* TB flags */
 557 #define TB_FLAGS_MACSR          0x0f
 558 #define TB_FLAGS_MSR_S_BIT      13
 559 #define TB_FLAGS_MSR_S          (1 << TB_FLAGS_MSR_S_BIT)
 560 #define TB_FLAGS_SFC_S_BIT      14
 561 #define TB_FLAGS_SFC_S          (1 << TB_FLAGS_SFC_S_BIT)
 562 #define TB_FLAGS_DFC_S_BIT      15
 563 #define TB_FLAGS_DFC_S          (1 << TB_FLAGS_DFC_S_BIT)
 564
 565 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
 566                                         target_ulong *cs_base, uint32_t *flags)
 567 {
 568     *pc = env->pc;
 569     *cs_base = 0;
 570     *flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
 571     if (env->sr & SR_S) {
 572         *flags |= TB_FLAGS_MSR_S;
 573         *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
 574         *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
 575     }
 576 }
 577
 578 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUM68KState *env);
 579 #endif