?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
libcacard: Lock NSS cert db when selecting an applet on an emulated card
[qemu/ar7.git] / target-tricore / tricore-opcodes.h
blob7e6f33bd62fb3a821ccf69f4e6bb078623e65d85
1 /*
2 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
3 *
4 * This library is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2 of the License, or (at your option) any later version.
8 *
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
13 *
14 * You should have received a copy of the GNU Lesser General Public
15 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18 /*
19 * Opcode Masks for Tricore
20 * Format MASK_OP_InstrFormatName_Field
21 */
22
23 /* This creates a mask with bits start .. end set to 1 and applies it to op */
24 #define MASK_BITS_SHIFT(op, start, end) (extract32(op, (start), \
25 (end) - (start) + 1))
26 #define MASK_BITS_SHIFT_SEXT(op, start, end) (sextract32(op, (start),\
27 (end) - (start) + 1))
28
29 /* new opcode masks */
30
31 #define MASK_OP_MAJOR(op) MASK_BITS_SHIFT(op, 0, 7)
32
33 /* 16-Bit Formats */
34 #define MASK_OP_SB_DISP8(op) MASK_BITS_SHIFT(op, 8, 15)
35 #define MASK_OP_SB_DISP8_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 8, 15)
36
37 #define MASK_OP_SBC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
38 #define MASK_OP_SBC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
39 #define MASK_OP_SBC_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
40
41 #define MASK_OP_SBR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
42 #define MASK_OP_SBR_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
43
44 #define MASK_OP_SBRN_N(op) MASK_BITS_SHIFT(op, 12, 15)
45 #define MASK_OP_SBRN_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
46
47 #define MASK_OP_SC_CONST8(op) MASK_BITS_SHIFT(op, 8, 15)
48
49 #define MASK_OP_SLR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
50 #define MASK_OP_SLR_D(op) MASK_BITS_SHIFT(op, 8, 11)
51
52 #define MASK_OP_SLRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
53 #define MASK_OP_SLRO_D(op) MASK_BITS_SHIFT(op, 8, 11)
54
55 #define MASK_OP_SR_OP2(op) MASK_BITS_SHIFT(op, 12, 15)
56 #define MASK_OP_SR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
57
58 #define MASK_OP_SRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
59 #define MASK_OP_SRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
60 #define MASK_OP_SRC_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
61
62 #define MASK_OP_SRO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
63 #define MASK_OP_SRO_OFF4(op) MASK_BITS_SHIFT(op, 8, 11)
64
65 #define MASK_OP_SRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
66 #define MASK_OP_SRR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
67
68 #define MASK_OP_SRRS_S2(op) MASK_BITS_SHIFT(op, 12, 15)
69 #define MASK_OP_SRRS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
70 #define MASK_OP_SRRS_N(op) MASK_BITS_SHIFT(op, 6, 7)
71
72 #define MASK_OP_SSR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
73 #define MASK_OP_SSR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
74
75 #define MASK_OP_SSRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
76 #define MASK_OP_SSRO_S1(op) MASK_BITS_SHIFT(op, 8, 11)
77
78 /* 32-Bit Formats */
79
80 /* ABS Format */
81 #define MASK_OP_ABS_OFF18(op) (MASK_BITS_SHIFT(op, 16, 21) + \
82 (MASK_BITS_SHIFT(op, 28, 31) << 6) + \
83 (MASK_BITS_SHIFT(op, 22, 25) << 10) +\
84 (MASK_BITS_SHIFT(op, 12, 15) << 14))
85 #define MASK_OP_ABS_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
86 #define MASK_OP_ABS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
87
88 /* ABSB Format */
89 #define MASK_OP_ABSB_OFF18(op) MASK_OP_ABS_OFF18(op)
90 #define MASK_OP_ABSB_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
91 #define MASK_OP_ABSB_B(op) MASK_BITS_SHIFT(op, 11, 11)
92 #define MASK_OP_ABSB_BPOS(op) MASK_BITS_SHIFT(op, 8, 10)
93
94 /* B Format */
95 #define MASK_OP_B_DISP24(op) (MASK_BITS_SHIFT(op, 16, 31) + \
96 (MASK_BITS_SHIFT(op, 8, 15) << 16))
97 /* BIT Format */
98 #define MASK_OP_BIT_D(op) MASK_BITS_SHIFT(op, 28, 31)
99 #define MASK_OP_BIT_POS2(op) MASK_BITS_SHIFT(op, 23, 27)
100 #define MASK_OP_BIT_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
101 #define MASK_OP_BIT_POS1(op) MASK_BITS_SHIFT(op, 16, 20)
102 #define MASK_OP_BIT_S2(op) MASK_BITS_SHIFT(op, 12, 15)
103 #define MASK_OP_BIT_S1(op) MASK_BITS_SHIFT(op, 8, 11)
104
105 /* BO Format */
106 #define MASK_OP_BO_OFF10(op) (MASK_BITS_SHIFT(op, 16, 21) + \
107 (MASK_BITS_SHIFT(op, 28, 31) << 6))
108 #define MASK_OP_BO_OFF10_SEXT(op) (MASK_BITS_SHIFT_SEXT(op, 16, 21) + \
109 (MASK_BITS_SHIFT_SEXT(op, 28, 31) << 6))
110 #define MASK_OP_BO_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
111 #define MASK_OP_BO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
112 #define MASK_OP_BO_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
113
114 /* BOL Format */
115 #define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
116 (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
117 (MASK_BITS_SHIFT(op, 22, 27) >> 10))
118
119 #define MASK_OP_BOL_S2(op) MASK_BITS_SHIFT(op, 12, 15)
120 #define MASK_OP_BOL_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
121
122 /* BRC Format */
123 #define MASK_OP_BRC_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
124 #define MASK_OP_BRC_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
125 #define MASK_OP_BRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
126 #define MASK_OP_BRC_S1(op) MASK_BITS_SHIFT(op, 8, 11)
127
128 /* BRN Format */
129 #define MASK_OP_BRN_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
130 #define MASK_OP_BRN_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
131 #define MASK_OP_BRN_N(op) (MASK_BITS_SHIFT(op, 12, 15) + \
132 (MASK_BITS_SHIFT(op, 7, 7) << 4))
133 #define MASK_OP_BRN_S1(op) MASK_BITS_SHIFT(op, 8, 11)
134 /* BRR Format */
135 #define MASK_OP_BRR_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
136 #define MASK_OP_BRR_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
137 #define MASK_OP_BRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
138 #define MASK_OP_BRR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
139
140 /* META MASK for similar instr Formats */
141 #define MASK_OP_META_D(op) MASK_BITS_SHIFT(op, 28, 31)
142 #define MASK_OP_META_S1(op) MASK_BITS_SHIFT(op, 8, 11)
143
144 /* RC Format */
145 #define MASK_OP_RC_D(op) MASK_OP_META_D(op)
146 #define MASK_OP_RC_OP2(op) MASK_BITS_SHIFT(op, 21, 27)
147 #define MASK_OP_RC_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
148 #define MASK_OP_RC_S1(op) MASK_OP_META_S1(op)
149
150 /* RCPW Format */
151
152 #define MASK_OP_RCPW_D(op) MASK_OP_META_D(op)
153 #define MASK_OP_RCPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
154 #define MASK_OP_RCPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
155 #define MASK_OP_RCPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
156 #define MASK_OP_RCPW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
157 #define MASK_OP_RCPW_S1(op) MASK_OP_META_S1(op)
158
159 /* RCR Format */
160
161 #define MASK_OP_RCR_D(op) MASK_OP_META_D(op)
162 #define MASK_OP_RCR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
163 #define MASK_OP_RCR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
164 #define MASK_OP_RCR_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
165 #define MASK_OP_RCR_S1(op) MASK_OP_META_S1(op)
166
167 /* RCRR Format */
168
169 #define MASK_OP_RCRR_D(op) MASK_OP_META_D(op)
170 #define MASK_OP_RCRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
171 #define MASK_OP_RCRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
172 #define MASK_OP_RCRR_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
173 #define MASK_OP_RCRR_S1(op) MASK_OP_META_S1(op)
174
175 /* RCRW Format */
176
177 #define MASK_OP_RCRW_D(op) MASK_OP_META_D(op)
178 #define MASK_OP_RCRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
179 #define MASK_OP_RCRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
180 #define MASK_OP_RCRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
181 #define MASK_OP_RCRW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
182 #define MASK_OP_RCRW_S1(op) MASK_OP_META_S1(op)
183
184 /* RLC Format */
185
186 #define MASK_OP_RLC_D(op) MASK_OP_META_D(op)
187 #define MASK_OP_RLC_CONST16(op) MASK_BITS_SHIFT(op, 12, 27)
188 #define MASK_OP_RLC_S1(op) MASK_OP_META_S1(op)
189
190 /* RR Format */
191 #define MASK_OP_RR_D(op) MASK_OP_META_D(op)
192 #define MASK_OP_RR_OP2(op) MASK_BITS_SHIFT(op, 20, 27)
193 #define MASK_OP_RR_N(op) MASK_BITS_SHIFT(op, 16, 17)
194 #define MASK_OP_RR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
195 #define MASK_OP_RR_S1(op) MASK_OP_META_S1(op)
196
197 /* RR1 Format */
198 #define MASK_OP_RR1_D(op) MASK_OP_META_D(op)
199 #define MASK_OP_RR1_OP2(op) MASK_BITS_SHIFT(op, 18, 27)
200 #define MASK_OP_RR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
201 #define MASK_OP_RR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
202 #define MASK_OP_RR1_S1(op) MASK_OP_META_S1(op)
203
204 /* RR2 Format */
205 #define MASK_OP_RR2_D(op) MASK_OP_META_D(op)
206 #define MASK_OP_RR2_OP2(op) MASK_BITS_SHIFT(op, 16, 27)
207 #define MASK_OP_RR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
208 #define MASK_OP_RR2_S1(op) MASK_OP_META_S1(op)
209
210 /* RRPW Format */
211 #define MASK_OP_RRPW_D(op) MASK_OP_META_D(op)
212 #define MASK_OP_RRPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
213 #define MASK_OP_RRPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
214 #define MASK_OP_RRPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
215 #define MASK_OP_RRPW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
216 #define MASK_OP_RRPW_S1(op) MASK_OP_META_S1(op)
217
218 /* RRR Format */
219 #define MASK_OP_RRR_D(op) MASK_OP_META_D(op)
220 #define MASK_OP_RRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
221 #define MASK_OP_RRR_OP2(op) MASK_BITS_SHIFT(op, 20, 23)
222 #define MASK_OP_RRR_N(op) MASK_BITS_SHIFT(op, 16, 17)
223 #define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
224 #define MASK_OP_RRR_S1(op) MASK_OP_META_S1(op)
225
226 /* RRR1 Format */
227 #define MASK_OP_RRR1_D(op) MASK_OP_META_D(op)
228 #define MASK_OP_RRR1_S3(op) MASK_BITS_SHIFT(op, 24, 27)
229 #define MASK_OP_RRR1_OP2(op) MASK_BITS_SHIFT(op, 18, 23)
230 #define MASK_OP_RRR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
231 #define MASK_OP_RRR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
232 #define MASK_OP_RRR1_S1(op) MASK_OP_META_S1(op)
233
234 /* RRR2 Format */
235 #define MASK_OP_RRR2_D(op) MASK_OP_META_D(op)
236 #define MASK_OP_RRR2_S3(op) MASK_BITS_SHIFT(op, 24, 27)
237 #define MASK_OP_RRR2_OP2(op) MASK_BITS_SHIFT(op, 16, 23)
238 #define MASK_OP_RRR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
239 #define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op)
240
241 /* RRRR Format */
242 #define MASK_OP_RRRR_D(op) MASK_OP_META_D(op)
243 #define MASK_OP_RRRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
244 #define MASK_OP_RRRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
245 #define MASK_OP_RRRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
246 #define MASK_OP_RRRR_S1(op) MASK_OP_META_S1(op)
247
248 /* RRRW Format */
249 #define MASK_OP_RRRW_D(op) MASK_OP_META_D(op)
250 #define MASK_OP_RRRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
251 #define MASK_OP_RRRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
252 #define MASK_OP_RRRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
253 #define MASK_OP_RRRW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
254 #define MASK_OP_RRRW_S1(op) MASK_OP_META_S1(op)
255
256 /* SYS Format */
257 #define MASK_OP_SYS_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
258 #define MASK_OP_SYS_S1D(op) MASK_OP_META_S1(op)
259
260
261
262 /*
263 * Tricore Opcodes Enums
264 *
265 * Format: OPC(1|2|M)_InstrLen_Name
266 * OPC1 = only op1 field is used
267 * OPC2 = op1 and op2 field used part of OPCM
268 * OPCM = op1 field used to group Instr
269 * InstrLen = 16|32
270 * Name = Name of Instr
271 */
272
273 /* 16-Bit */
274 enum {
275
276 OPCM_16_SR_SYSTEM = 0x00,
277 OPCM_16_SR_ACCU = 0x32,
278
279 OPC1_16_SRC_ADD = 0xc2,
280 OPC1_16_SRC_ADD_A15 = 0x92,
281 OPC1_16_SRC_ADD_15A = 0x9a,
282 OPC1_16_SRR_ADD = 0x42,
283 OPC1_16_SRR_ADD_A15 = 0x12,
284 OPC1_16_SRR_ADD_15A = 0x1a,
285 OPC1_16_SRC_ADD_A = 0xb0,
286 OPC1_16_SRR_ADD_A = 0x30,
287 OPC1_16_SRR_ADDS = 0x22,
288 OPC1_16_SRRS_ADDSC_A = 0x10,
289 OPC1_16_SC_AND = 0x16,
290 OPC1_16_SRR_AND = 0x26,
291 OPC1_16_SC_BISR = 0xe0,
292 OPC1_16_SRC_CADD = 0x8a,
293 OPC1_16_SRC_CADDN = 0xca,
294 OPC1_16_SB_CALL = 0x5c,
295 OPC1_16_SRC_CMOV = 0xaa,
296 OPC1_16_SRR_CMOV = 0x2a,
297 OPC1_16_SRC_CMOVN = 0xea,
298 OPC1_16_SRR_CMOVN = 0x6a,
299 OPC1_16_SRC_EQ = 0xba,
300 OPC1_16_SRR_EQ = 0x3a,
301 OPC1_16_SB_J = 0x3c,
302 OPC1_16_SBC_JEQ = 0x1e,
303 OPC1_16_SBR_JEQ = 0x3e,
304 OPC1_16_SBR_JGEZ = 0xce,
305 OPC1_16_SBR_JGTZ = 0x4e,
306 OPC1_16_SR_JI = 0xdc,
307 OPC1_16_SBR_JLEZ = 0x8e,
308 OPC1_16_SBR_JLTZ = 0x0e,
309 OPC1_16_SBC_JNE = 0x5e,
310 OPC1_16_SBR_JNE = 0x7e,
311 OPC1_16_SB_JNZ = 0xee,
312 OPC1_16_SBR_JNZ = 0xf6,
313 OPC1_16_SBR_JNZ_A = 0x7c,
314 OPC1_16_SBRN_JNZ_T = 0xae,
315 OPC1_16_SB_JZ = 0x6e,
316 OPC1_16_SBR_JZ = 0x76,
317 OPC1_16_SBR_JZ_A = 0xbc,
318 OPC1_16_SBRN_JZ_T = 0x2e,
319 OPC1_16_SC_LD_A = 0xd8,
320 OPC1_16_SLR_LD_A = 0xd4,
321 OPC1_16_SLR_LD_A_POSTINC = 0xc4,
322 OPC1_16_SLRO_LD_A = 0xc8,
323 OPC1_16_SRO_LD_A = 0xcc,
324 OPC1_16_SLR_LD_BU = 0x14,
325 OPC1_16_SLR_LD_BU_POSTINC = 0x04,
326 OPC1_16_SLRO_LD_BU = 0x08,
327 OPC1_16_SRO_LD_BU = 0x0c,
328 OPC1_16_SLR_LD_H = 0x94,
329 OPC1_16_SLR_LD_H_POSTINC = 0x84,
330 OPC1_16_SLRO_LD_H = 0x88,
331 OPC1_16_SRO_LD_H = 0x8c,
332 OPC1_16_SC_LD_W = 0x58,
333 OPC1_16_SLR_LD_W = 0x54,
334 OPC1_16_SLR_LD_W_POSTINC = 0x44,
335 OPC1_16_SLRO_LD_W = 0x48,
336 OPC1_16_SRO_LD_W = 0x4c,
337 OPC1_16_SBR_LOOP = 0xfc,
338 OPC1_16_SRC_LT = 0xfa,
339 OPC1_16_SRR_LT = 0x7a,
340 OPC1_16_SC_MOV = 0xda,
341 OPC1_16_SRC_MOV = 0x82,
342 OPC1_16_SRR_MOV = 0x02,
343 OPC1_16_SRC_MOV_E = 0xd2,/* 1.6 only */
344 OPC1_16_SRC_MOV_A = 0xa0,
345 OPC1_16_SRR_MOV_A = 0x60,
346 OPC1_16_SRR_MOV_AA = 0x40,
347 OPC1_16_SRR_MOV_D = 0x80,
348 OPC1_16_SRR_MUL = 0xe2,
349 OPC1_16_SR_NOT = 0x46,
350 OPC1_16_SC_OR = 0x96,
351 OPC1_16_SRR_OR = 0xa6,
352 OPC1_16_SRC_SH = 0x06,
353 OPC1_16_SRC_SHA = 0x86,
354 OPC1_16_SC_ST_A = 0xf8,
355 OPC1_16_SRO_ST_A = 0xec,
356 OPC1_16_SSR_ST_A = 0xf4,
357 OPC1_16_SSR_ST_A_POSTINC = 0xe4,
358 OPC1_16_SSRO_ST_A = 0xe8,
359 OPC1_16_SRO_ST_B = 0x2c,
360 OPC1_16_SSR_ST_B = 0x34,
361 OPC1_16_SSR_ST_B_POSTINC = 0x24,
362 OPC1_16_SSRO_ST_B = 0x28,
363 OPC1_16_SRO_ST_H = 0xac,
364 OPC1_16_SSR_ST_H = 0xb4,
365 OPC1_16_SSR_ST_H_POSTINC = 0xa4,
366 OPC1_16_SSRO_ST_H = 0xa8,
367 OPC1_16_SC_ST_W = 0x78,
368 OPC1_16_SRO_ST_W = 0x6c,
369 OPC1_16_SSR_ST_W = 0x74,
370 OPC1_16_SSR_ST_W_POSTINC = 0x64,
371 OPC1_16_SSRO_ST_W = 0x68,
372 OPC1_16_SRR_SUB = 0xa2,
373 OPC1_16_SRR_SUB_A15B = 0x52,
374 OPC1_16_SRR_SUB_15AB = 0x5a,
375 OPC1_16_SC_SUB_A = 0x20,
376 OPC1_16_SRR_SUBS = 0x62,
377 OPC1_16_SRR_XOR = 0xc6,
378
379 };
380
381 /*
382 * SR Format
383 */
384 /* OPCM_16_SR_SYSTEM */
385 enum {
386
387 OPC2_16_SR_NOP = 0x00,
388 OPC2_16_SR_RET = 0x09,
389 OPC2_16_SR_RFE = 0x08,
390 OPC2_16_SR_DEBUG = 0x0a,
391 };
392 /* OPCM_16_SR_ACCU */
393 enum {
394 OPC2_16_SR_RSUB = 0x05,
395 OPC2_16_SR_SAT_B = 0x00,
396 OPC2_16_SR_SAT_BU = 0x01,
397 OPC2_16_SR_SAT_H = 0x02,
398 OPC2_16_SR_SAT_HU = 0x03,
399
400 };
401
402 /* 32-Bit */
403
404 enum {
405 /* ABS Format 1, M */
406 OPCM_32_ABS_LDW = 0x85,
407 OPCM_32_ABS_LDB = 0x05,
408 OPCM_32_ABS_LDMST_SWAP = 0xe5,
409 OPCM_32_ABS_LDST_CONTEXT = 0x15,
410 OPCM_32_ABS_STORE = 0xa5,
411 OPCM_32_ABS_STOREB_H = 0x25,
412 OPC1_32_ABS_STOREQ = 0x65,
413 OPC1_32_ABS_LD_Q = 0x45,
414 OPC1_32_ABS_LEA = 0xc5,
415 /* ABSB Format */
416 OPC1_32_ABSB_ST_T = 0xd5,
417 /* B Format */
418 OPC1_32_B_CALL = 0x6d,
419 OPC1_32_B_CALLA = 0xed,
420 OPC1_32_B_J = 0x1d,
421 OPC1_32_B_JA = 0x9d,
422 OPC1_32_B_JL = 0x5d,
423 OPC1_32_B_JLA = 0xdd,
424 /* Bit Format */
425 OPCM_32_BIT_ANDACC = 0x47,
426 OPCM_32_BIT_LOGICAL_T1 = 0x87,
427 OPCM_32_BIT_INSERT = 0x67,
428 OPCM_32_BIT_LOGICAL_T2 = 0x07,
429 OPCM_32_BIT_ORAND = 0xc7,
430 OPCM_32_BIT_SH_LOGIC1 = 0x27,
431 OPCM_32_BIT_SH_LOGIC2 = 0xa7,
432 /* BO Format */
433 OPCM_32_BO_ADDRMODE_POST_PRE_BASE = 0x89,
434 OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR = 0xa9,
435 OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE = 0x09,
436 OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR = 0x29,
437 OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE = 0x49,
438 OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR = 0x69,
439 /* BOL Format */
440 OPC1_32_BOL_LD_A_LONGOFF = 0x99,
441 OPC1_32_BOL_LD_W_LONFOFF = 0x19,
442 OPC1_32_BOL_LEA_LONGOFF = 0xd9,
443 OPC1_32_BOL_ST_W_LONGOFF = 0x59,
444 OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */
445 /* BRC Format */
446 OPCM_32_BRC_EQ_NEQ = 0xdf,
447 OPCM_32_BRC_GE = 0xff,
448 OPCM_32_BRC_JLT = 0xbf,
449 OPCM_32_BRC_JNE = 0x9f,
450 /* BRN Format */
451 OPCM_32_BRN_JTT = 0x6f,
452 /* BRR Format */
453 OPCM_32_BRR_EQ_NEQ = 0x5f,
454 OPCM_32_BRR_ADDR_EQ_NEQ = 0x7d,
455 OPCM_32_BRR_GE = 0x7f,
456 OPCM_32_BRR_JLT = 0x3f,
457 OPCM_32_BRR_JNE = 0x1f,
458 OPCM_32_BRR_JNZ = 0xbd,
459 OPCM_32_BRR_LOOP = 0xfd,
460 /* RC Format */
461 OPCM_32_RC_LOGICAL_SHIFT = 0x8f,
462 OPCM_32_RC_ACCUMULATOR = 0x8b,
463 OPCM_32_RC_SERVICEROUTINE = 0xad,
464 OPCM_32_RC_MUL = 0x53,
465 /* RCPW Format */
466 OPCM_32_RCPW_MASK_INSERT = 0xb7,
467 /* RCR Format */
468 OPCM_32_RCR_COND_SELECT = 0xab,
469 OPCM_32_RCR_MADD = 0x13,
470 OPCM_32_RCR_MSUB = 0x33,
471 /* RCRR Format */
472 OPC1_32_RCRR_INSERT = 0x97,
473 /* RCRW Format */
474 OPCM_32_RCRW_MASK_INSERT = 0xd7,
475 /* RLC Format */
476 OPC1_32_RLC_ADDI = 0x1b,
477 OPC1_32_RLC_ADDIH = 0x9b,
478 OPC1_32_RLC_ADDIH_A = 0x11,
479 OPC1_32_RLC_MFCR = 0x4d,
480 OPC1_32_RLC_MOV = 0x3b,
481 OPC1_32_RLC_MOV_U = 0xbb,
482 OPC1_32_RLC_MOV_H = 0x7b,
483 OPC1_32_RLC_MOVH_A = 0x91,
484 OPC1_32_RLC_MTCR = 0xcd,
485 /* RR Format */
486 OPCM_32_RR_LOGICAL_SHIFT = 0x0f,
487 OPCM_32_RR_ACCUMULATOR = 0x0b,
488 OPCM_32_RR_ADRESS = 0x01,
489 OPCM_32_RR_FLOAT = 0x4b,
490 OPCM_32_RR_IDIRECT = 0x2d,
491 /* RR1 Format */
492 OPCM_32_RR1_MUL = 0xb3,
493 OPCM_32_RR1_MULQ = 0x93,
494 /* RR2 Format */
495 OPCM_32_RR2_MUL = 0x73,
496 /* RRPW Format */
497 OPCM_32_RRPW_EXTRACT_INSERT = 0x37,
498 OPC1_32_RRPW_DEXTR = 0x77,
499 /* RRR Format */
500 OPCM_32_RRR_COND_SELECT = 0x2b,
501 OPCM_32_RRR_FLOAT = 0x6b,
502 /* RRR1 Format */
503 OPCM_32_RRR1_MADD = 0x83,
504 OPCM_32_RRR1_MADDQ_H = 0x43,
505 OPCM_32_RRR1_MADDSU_H = 0xc3,
506 OPCM_32_RRR1_MSUB_H = 0xa3,
507 OPCM_32_RRR1_MSUB_Q = 0x63,
508 OPCM_32_RRR1_MSUBADS_H = 0xe3,
509 /* RRR2 Format */
510 OPCM_32_RRR2_MADD = 0x03,
511 OPCM_32_RRR2_MSUB = 0x23,
512 /* RRRR Format */
513 OPCM_32_RRRR_EXTRACT_INSERT = 0x17,
514 /* RRRW Format */
515 OPCM_32_RRRW_EXTRACT_INSERT = 0x57,
516 /* SYS Format */
517 OPCM_32_SYS_INTERRUPTS = 0x0d,
518 OPC1_32_SYS_RSTV = 0x2f,
519 };
520
521
522
523 /*
524 * ABS Format
525 */
526
527 /* OPCM_32_ABS_LDW */
528 enum {
529
530 OPC2_32_ABS_LD_A = 0x02,
531 OPC2_32_ABS_LD_D = 0x01,
532 OPC2_32_ABS_LD_DA = 0x03,
533 OPC2_32_ABS_LD_W = 0x00,
534 };
535
536 /* OPCM_32_ABS_LDB */
537 enum {
538 OPC2_32_ABS_LD_B = 0x00,
539 OPC2_32_ABS_LD_BU = 0x01,
540 OPC2_32_ABS_LD_H = 0x02,
541 OPC2_32_ABS_LD_HU = 0x03,
542 };
543 /* OPCM_32_ABS_LDMST_SWAP */
544 enum {
545 OPC2_32_ABS_LDMST = 0x01,
546 OPC2_32_ABS_SWAP_W = 0x00,
547 };
548 /* OPCM_32_ABS_LDST_CONTEXT */
549 enum {
550 OPC2_32_ABS_LDLCX = 0x02,
551 OPC2_32_ABS_LDUCX = 0x03,
552 OPC2_32_ABS_STLCX = 0x00,
553 OPC2_32_ABS_STUCX = 0x01,
554 };
555 /* OPCM_32_ABS_STORE */
556 enum {
557 OPC2_32_ABS_ST_A = 0x02,
558 OPC2_32_ABS_ST_D = 0x01,
559 OPC2_32_ABS_ST_DA = 0x03,
560 OPC2_32_ABS_ST_W = 0x00,
561 };
562 /* OPCM_32_ABS_STOREB_H */
563 enum {
564 OPC2_32_ABS_ST_B = 0x00,
565 OPC2_32_ABS_ST_H = 0x02,
566 };
567 /*
568 * Bit Format
569 */
570 /* OPCM_32_BIT_ANDACC */
571 enum {
572 OPC2_32_BIT_AND_AND_T = 0x00,
573 OPC2_32_BIT_AND_ANDN_T = 0x03,
574 OPC2_32_BIT_AND_NOR_T = 0x02,
575 OPC2_32_BIT_AND_OR_T = 0x01,
576 };
577 /* OPCM_32_BIT_LOGICAL_T */
578 enum {
579 OPC2_32_BIT_AND_T = 0x00,
580 OPC2_32_BIT_ANDN_T = 0x03,
581 OPC2_32_BIT_NOR_T = 0x02,
582 OPC2_32_BIT_OR_T = 0x01,
583 };
584 /* OPCM_32_BIT_INSERT */
585 enum {
586 OPC2_32_BIT_INS_T = 0x00,
587 OPC2_32_BIT_INSN_T = 0x01,
588 };
589 /* OPCM_32_BIT_LOGICAL_T2 */
590 enum {
591 OPC2_32_BIT_NAND_T = 0x00,
592 OPC2_32_BIT_ORN_T = 0x01,
593 OPC2_32_BIT_XNOR_T = 0x02,
594 OPC2_32_BIT_XOR_T = 0x03,
595 };
596 /* OPCM_32_BIT_ORAND */
597 enum {
598 OPC2_32_BIT_OR_AND_T = 0x00,
599 OPC2_32_BIT_OR_ANDN_T = 0x03,
600 OPC2_32_BIT_OR_NOR_T = 0x02,
601 OPC2_32_BIT_OR_OR_T = 0x01,
602 };
603 /*OPCM_32_BIT_SH_LOGIC1 */
604 enum {
605 OPC2_32_BIT_SH_AND_T = 0x00,
606 OPC2_32_BIT_SH_ANDN_T = 0x03,
607 OPC2_32_BIT_SH_NOR_T = 0x02,
608 OPC2_32_BIT_SH_OR_T = 0x01,
609 };
610 /* OPCM_32_BIT_SH_LOGIC2 */
611 enum {
612 OPC2_32_BIT_SH_NAND_T = 0x00,
613 OPC2_32_BIT_SH_ORN_T = 0x01,
614 OPC2_32_BIT_SH_XNOR_T = 0x02,
615 OPC2_32_BIT_SH_XOR_T = 0x03,
616 };
617 /*
618 * BO Format
619 */
620 /* OPCM_32_BO_ADDRMODE_POST_PRE_BASE */
621 enum {
622 OPC2_32_BO_CACHEA_I_SHORTOFF = 0x2e,
623 OPC2_32_BO_CACHEA_I_POSTINC = 0x0e,
624 OPC2_32_BO_CACHEA_I_PREINC = 0x1e,
625 OPC2_32_BO_CACHEA_W_SHORTOFF = 0x2c,
626 OPC2_32_BO_CACHEA_W_POSTINC = 0x0c,
627 OPC2_32_BO_CACHEA_W_PREINC = 0x1c,
628 OPC2_32_BO_CACHEA_WI_SHORTOFF = 0x2d,
629 OPC2_32_BO_CACHEA_WI_POSTINC = 0x0d,
630 OPC2_32_BO_CACHEA_WI_PREINC = 0x1d,
631 /* 1.3.1 only */
632 OPC2_32_BO_CACHEI_W_SHORTOFF = 0x2b,
633 OPC2_32_BO_CACHEI_W_POSTINC = 0x0b,
634 OPC2_32_BO_CACHEI_W_PREINC = 0x1b,
635 OPC2_32_BO_CACHEI_WI_SHORTOFF = 0x2f,
636 OPC2_32_BO_CACHEI_WI_POSTINC = 0x0f,
637 OPC2_32_BO_CACHEI_WI_PREINC = 0x1f,
638 /* end 1.3.1 only */
639 OPC2_32_BO_ST_A_SHORTOFF = 0x26,
640 OPC2_32_BO_ST_A_POSTINC = 0x06,
641 OPC2_32_BO_ST_A_PREINC = 0x16,
642 OPC2_32_BO_ST_B_SHORTOFF = 0x20,
643 OPC2_32_BO_ST_B_POSTINC = 0x00,
644 OPC2_32_BO_ST_B_PREINC = 0x10,
645 OPC2_32_BO_ST_D_SHORTOFF = 0x25,
646 OPC2_32_BO_ST_D_POSTINC = 0x05,
647 OPC2_32_BO_ST_D_PREINC = 0x15,
648 OPC2_32_BO_ST_DA_SHORTOFF = 0x27,
649 OPC2_32_BO_ST_DA_POSTINC = 0x07,
650 OPC2_32_BO_ST_DA_PREINC = 0x17,
651 OPC2_32_BO_ST_H_SHORTOFF = 0x22,
652 OPC2_32_BO_ST_H_POSTINC = 0x02,
653 OPC2_32_BO_ST_H_PREINC = 0x12,
654 OPC2_32_BO_ST_Q_SHORTOFF = 0x28,
655 OPC2_32_BO_ST_Q_POSTINC = 0x08,
656 OPC2_32_BO_ST_Q_PREINC = 0x18,
657 OPC2_32_BO_ST_W_SHORTOFF = 0x24,
658 OPC2_32_BO_ST_W_POSTINC = 0x04,
659 OPC2_32_BO_ST_W_PREINC = 0x14,
660 };
661 /* OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR */
662 enum {
663 OPC2_32_BO_CACHEA_I_BR = 0x0e,
664 OPC2_32_BO_CACHEA_I_CIRC = 0x1e,
665 OPC2_32_BO_CACHEA_W_BR = 0x0c,
666 OPC2_32_BO_CACHEA_W_CIRC = 0x1c,
667 OPC2_32_BO_CACHEA_WI_BR = 0x0d,
668 OPC2_32_BO_CACHEA_WI_CIRC = 0x1d,
669 OPC2_32_BO_ST_A_BR = 0x06,
670 OPC2_32_BO_ST_A_CIRC = 0x16,
671 OPC2_32_BO_ST_B_BR = 0x00,
672 OPC2_32_BO_ST_B_CIRC = 0x10,
673 OPC2_32_BO_ST_D_BR = 0x05,
674 OPC2_32_BO_ST_D_CIRC = 0x15,
675 OPC2_32_BO_ST_DA_BR = 0x07,
676 OPC2_32_BO_ST_DA_CIRC = 0x17,
677 OPC2_32_BO_ST_H_BR = 0x02,
678 OPC2_32_BO_ST_H_CIRC = 0x12,
679 OPC2_32_BO_ST_Q_BR = 0x08,
680 OPC2_32_BO_ST_Q_CIRC = 0x18,
681 OPC2_32_BO_ST_W_BR = 0x04,
682 OPC2_32_BO_ST_W_CIRC = 0x14,
683 };
684 /* OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE */
685 enum {
686 OPC2_32_BO_LD_A_SHORTOFF = 0x26,
687 OPC2_32_BO_LD_A_POSTINC = 0x06,
688 OPC2_32_BO_LD_A_PREINC = 0x16,
689 OPC2_32_BO_LD_B_SHORTOFF = 0x20,
690 OPC2_32_BO_LD_B_POSTINC = 0x00,
691 OPC2_32_BO_LD_B_PREINC = 0x10,
692 OPC2_32_BO_LD_BU_SHORTOFF = 0x21,
693 OPC2_32_BO_LD_BU_POSTINC = 0x01,
694 OPC2_32_BO_LD_BU_PREINC = 0x11,
695 OPC2_32_BO_LD_D_SHORTOFF = 0x25,
696 OPC2_32_BO_LD_D_POSTINC = 0x05,
697 OPC2_32_BO_LD_D_PREINC = 0x15,
698 OPC2_32_BO_LD_DA_SHORTOFF = 0x27,
699 OPC2_32_BO_LD_DA_POSTINC = 0x07,
700 OPC2_32_BO_LD_DA_PREINC = 0x17,
701 OPC2_32_BO_LD_H_SHORTOFF = 0x22,
702 OPC2_32_BO_LD_H_POSTINC = 0x02,
703 OPC2_32_BO_LD_H_PREINC = 0x12,
704 OPC2_32_BO_LD_HU_SHORTOFF = 0x23,
705 OPC2_32_BO_LD_HU_POSTINC = 0x03,
706 OPC2_32_BO_LD_HU_PREINC = 0x13,
707 OPC2_32_BO_LD_Q_SHORTOFF = 0x28,
708 OPC2_32_BO_LD_Q_POSTINC = 0x08,
709 OPC2_32_BO_LD_Q_PREINC = 0x18,
710 OPC2_32_BO_LD_W_SHORTOFF = 0x24,
711 OPC2_32_BO_LD_W_POSTINC = 0x04,
712 OPC2_32_BO_LD_W_PREINC = 0x14,
713 };
714 /* OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR */
715 enum {
716 OPC2_32_BO_LD_A_BR = 0x06,
717 OPC2_32_BO_LD_A_CIRC = 0x16,
718 OPC2_32_BO_LD_B_BR = 0x00,
719 OPC2_32_BO_LD_B_CIRC = 0x10,
720 OPC2_32_BO_LD_BU_BR = 0x01,
721 OPC2_32_BO_LD_BU_CIRC = 0x11,
722 OPC2_32_BO_LD_D_BR = 0x05,
723 OPC2_32_BO_LD_D_CIRC = 0x15,
724 OPC2_32_BO_LD_DA_BR = 0x07,
725 OPC2_32_BO_LD_DA_CIRC = 0x17,
726 OPC2_32_BO_LD_H_BR = 0x02,
727 OPC2_32_BO_LD_H_CIRC = 0x12,
728 OPC2_32_BO_LD_HU_BR = 0x03,
729 OPC2_32_BO_LD_HU_CIRC = 0x13,
730 OPC2_32_BO_LD_Q_BR = 0x08,
731 OPC2_32_BO_LD_Q_CIRC = 0x18,
732 OPC2_32_BO_LD_W_BR = 0x04,
733 OPC2_32_BO_LD_W_CIRC = 0x14,
734 };
735 /* OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE */
736 enum {
737 OPC2_32_BO_LDLCX_SHORTOFF = 0x24,
738 OPC2_32_BO_LDMST_SHORTOFF = 0x21,
739 OPC2_32_BO_LDMST_POSTINC = 0x01,
740 OPC2_32_BO_LDMST_PREINC = 0x11,
741 OPC2_32_BO_LDUCX_SHORTOFF = 0x25,
742 OPC2_32_BO_LEA_SHORTOFF = 0x28,
743 OPC2_32_BO_STLCX_SHORTOFF = 0x26,
744 OPC2_32_BO_STUCX_SHORTOFF = 0x27,
745 OPC2_32_BO_SWAP_W_SHORTOFF = 0x20,
746 OPC2_32_BO_SWAP_W_POSTINC = 0x00,
747 OPC2_32_BO_SWAP_W_PREINC = 0x10,
748 };
749 /*OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR */
750 enum {
751 OPC2_32_BO_LDMST_BR = 0x01,
752 OPC2_32_BO_LDMST_CIRC = 0x11,
753 OPC2_32_BO_SWAP_W_BR = 0x00,
754 OPC2_32_BO_SWAP_W_CIRC = 0x10,
755 };
756 /*
757 * BRC Format
758 */
759 /*OPCM_32_BRC_EQ_NEQ */
760 enum {
761 OPC2_32_BRC_JEQ = 0x00,
762 OPC2_32_BRC_JNE = 0x01,
763 };
764 /* OPCM_32_BRC_GE */
765 enum {
766 OP2_BRC_JGE = 0x00,
767 OPC_BRC_JGE_U = 0x01,
768 };
769 /* OPCM_32_BRC_JLT */
770 enum {
771 OPC2_32_BRC_JLT = 0x00,
772 OPC2_32_BRC_JLT_U = 0x01,
773 };
774 /* OPCM_32_BRC_JNE */
775 enum {
776 OPC2_32_BRC_JNED = 0x01,
777 OPC2_32_BRC_JNEI = 0x00,
778 };
779 /*
780 * BRN Format
781 */
782 /* OPCM_32_BRN_JTT */
783 enum {
784 OPC2_32_BRN_JNZ_T = 0x01,
785 OPC2_32_BRN_JZ_T = 0x00,
786 };
787 /*
788 * BRR Format
789 */
790 /* OPCM_32_BRR_EQ_NEQ */
791 enum {
792 OPC2_32_BRR_JEQ = 0x00,
793 OPC2_32_BRR_JNE = 0x01,
794 };
795 /* OPCM_32_BRR_ADDR_EQ_NEQ */
796 enum {
797 OPC2_32_BRR_JEQ_A = 0x00,
798 OPC2_32_BRR_JNE_A = 0x01,
799 };
800 /*OPCM_32_BRR_GE */
801 enum {
802 OPC2_32_BRR_JGE = 0x00,
803 OPC2_32_BRR_JGE_U = 0x01,
804 };
805 /* OPCM_32_BRR_JLT */
806 enum {
807 OPC2_32_BRR_JLT = 0x00,
808 OPC2_32_BRR_JLT_U = 0x01,
809 };
810 /* OPCM_32_BRR_JNE */
811 enum {
812 OPC2_32_BRR_JNED = 0x01,
813 OPC2_32_BRR_JNEI = 0x00,
814 };
815 /* OPCM_32_BRR_JNZ */
816 enum {
817 OPC2_32_BRR_JNZ_A = 0x01,
818 OPC2_32_BRR_JZ_A = 0x00,
819 };
820 /* OPCM_32_BRR_LOOP */
821 enum {
822 OPC2_32_BRR_LOOP = 0x00,
823 OPC2_32_BRR_LOOPU = 0x01,
824 };
825 /*
826 * RC Format
827 */
828 /* OPCM_32_RC_LOGICAL_SHIFT */
829 enum {
830 OPC2_32_RC_AND = 0x08,
831 OPC2_32_RC_ANDN = 0x0e,
832 OPC2_32_RC_NAND = 0x09,
833 OPC2_32_RC_NOR = 0x0b,
834 OPC2_32_RC_OR = 0x0a,
835 OPC2_32_RC_ORN = 0x0f,
836 OPC2_32_RC_SH = 0x00,
837 OPC2_32_RC_SH_H = 0x40,
838 OPC2_32_RC_SHA = 0x01,
839 OPC2_32_RC_SHA_H = 0x41,
840 OPC2_32_RC_SHAS = 0x02,
841 OPC2_32_RC_XNOR = 0x0d,
842 OPC2_32_RC_XOR = 0x0c,
843 };
844 /* OPCM_32_RC_ACCUMULATOR */
845 enum {
846 OPC2_32_RC_ABSDIF = 0x0e,
847 OPC2_32_RC_ABSDIFS = 0x0f,
848 OPC2_32_RC_ADD = 0x00,
849 OPC2_32_RC_ADDC = 0x05,
850 OPC2_32_RC_ADDS = 0x02,
851 OPC2_32_RC_ADDS_U = 0x03,
852 OPC2_32_RC_ADDX = 0x04,
853 OPC2_32_RC_AND_EQ = 0x20,
854 OPC2_32_RC_AND_GE = 0x24,
855 OPC2_32_RC_AND_GE_U = 0x25,
856 OPC2_32_RC_AND_LT = 0x22,
857 OPC2_32_RC_AND_LT_U = 0x23,
858 OPC2_32_RC_AND_NE = 0x21,
859 OPC2_32_RC_EQ = 0x10,
860 OPC2_32_RC_EQANY_B = 0x56,
861 OPC2_32_RC_EQANY_H = 0x76,
862 OPC2_32_RC_GE = 0x14,
863 OPC2_32_RC_GE_U = 0x15,
864 OPC2_32_RC_LT = 0x12,
865 OPC2_32_RC_LT_U = 0x13,
866 OPC2_32_RC_MAX = 0x1a,
867 OPC2_32_RC_MAX_U = 0x1b,
868 OPC2_32_RC_MIN = 0x18,
869 OPC2_32_RC_MIN_U = 0x19,
870 OPC2_32_RC_NE = 0x11,
871 OPC2_32_RC_OR_EQ = 0x27,
872 OPC2_32_RC_OR_GE = 0x2b,
873 OPC2_32_RC_OR_GE_U = 0x2c,
874 OPC2_32_RC_OR_LT = 0x29,
875 OPC2_32_RC_OR_LT_U = 0x2a,
876 OPC2_32_RC_OR_NE = 0x28,
877 OPC2_32_RC_RSUB = 0x08,
878 OPC2_32_RC_RSUBS = 0x0a,
879 OPC2_32_RC_RSUBS_U = 0x0b,
880 OPC2_32_RC_SH_EQ = 0x37,
881 OPC2_32_RC_SH_GE = 0x3b,
882 OPC2_32_RC_SH_GE_U = 0x3c,
883 OPC2_32_RC_SH_LT = 0x39,
884 OPC2_32_RC_SH_LT_U = 0x3a,
885 OPC2_32_RC_SH_NE = 0x38,
886 OPC2_32_RC_XOR_EQ = 0x2f,
887 OPC2_32_RC_XOR_GE = 0x33,
888 OPC2_32_RC_XOR_GE_U = 0x34,
889 OPC2_32_RC_XOR_LT = 0x31,
890 OPC2_32_RC_XOR_LT_U = 0x32,
891 OPC2_32_RC_XOR_NE = 0x30,
892 };
893 /* OPCM_32_RC_SERVICEROUTINE */
894 enum {
895 OPC2_32_RC_BISR = 0x00,
896 OPC2_32_RC_SYSCALL = 0x04,
897 };
898 /* OPCM_32_RC_MUL */
899 enum {
900 OPC2_32_RC_MUL_32 = 0x01,
901 OPC2_32_RC_MUL_64 = 0x03,
902 OPC2_32_RC_MULS_32 = 0x05,
903 OPC2_32_RC_MUL_U_64 = 0x02,
904 OPC2_32_RC_MULS_U_32 = 0x04,
905 };
906 /*
907 * RCPW Format
908 */
909 /* OPCM_32_RCPW_MASK_INSERT */
910 enum {
911 OPC2_32_RCPW_IMASK = 0x01,
912 OPC2_32_RCPW_INSERT = 0x00,
913 };
914 /*
915 * RCR Format
916 */
917 /* OPCM_32_RCR_COND_SELECT */
918 enum {
919 OPC2_32_RCR_CADD = 0x00,
920 OPC2_32_RCR_CADDN = 0x01,
921 OPC2_32_RCR_SEL = 0x04,
922 OPC2_32_RCR_SELN = 0x05,
923 };
924 /* OPCM_32_RCR_MADD */
925 enum {
926 OPC2_32_RCR_MADD_32 = 0x01,
927 OPC2_32_RCR_MADD_64 = 0x03,
928 OPC2_32_RCR_MADDS_32 = 0x05,
929 OPC2_32_RCR_MADDS_64 = 0x07,
930 OPC2_32_RCR_MADD_U_64 = 0x02,
931 OPC2_32_RCR_MADDS_U_32 = 0x04,
932 OPC2_32_RCR_MADDS_U_64 = 0x06,
933 };
934 /* OPCM_32_RCR_MSUB */
935 enum {
936 OPC2_32_RCR_MSUB_32 = 0x01,
937 OPC2_32_RCR_MSUB_64 = 0x03,
938 OPC2_32_RCR_MSUBS_32 = 0x05,
939 OPC2_32_RCR_MSUBS_64 = 0x07,
940 OPC2_32_RCR_MSUB_U_32 = 0x02,
941 OPC2_32_RCR_MSUBS_U_32 = 0x04,
942 OPC2_32_RCR_MSUBS_U_64 = 0x06,
943 };
944 /*
945 * RCRW Format
946 */
947 /* OPCM_32_RCRW_MASK_INSERT */
948 enum {
949 OPC2_32_RCRW_IMASK = 0x01,
950 OPC2_32_RCRW_INSERT = 0x00,
951 };
952
953 /*
954 * RR Format
955 */
956 /* OPCM_32_RR_LOGICAL_SHIFT */
957 enum {
958 OPC2_32_RR_AND = 0x08,
959 OPC2_32_RR_ANDN = 0x0e,
960 OPC2_32_RR_CLO = 0x1c,
961 OPC2_32_RR_CLO_H = 0x7d,
962 OPC2_32_RR_CLS = 0x1d,
963 OPC2_32_RR_CLS_H = 0x7e,
964 OPC2_32_RR_CLZ = 0x1b,
965 OPC2_32_RR_CLZ_H = 0x7c,
966 OPC2_32_RR_NAND = 0x09,
967 OPC2_32_RR_NOR = 0x0b,
968 OPC2_32_RR_OR = 0x0a,
969 OPC2_32_RR_ORN = 0x0f,
970 OPC2_32_RR_SH = 0x00,
971 OPC2_32_RR_SH_H = 0x40,
972 OPC2_32_RR_SHA = 0x01,
973 OPC2_32_RR_SHA_H = 0x41,
974 OPC2_32_RR_SHAS = 0x02,
975 OPC2_32_RR_XNOR = 0x0d,
976 OPC2_32_RR_XOR = 0x0c,
977 };
978 /* OPCM_32_RR_ACCUMULATOR */
979 enum {
980 OPC2_32_RR_ABS = 0x1c,
981 OPC2_32_RR_ABS_B = 0x5c,
982 OPC2_32_RR_ABS_H = 0x7c,
983 OPC2_32_RR_ABSDIF = 0x0e,
984 OPC2_32_RR_ABSDIF_B = 0x4e,
985 OPC2_32_RR_ABSDIF_H = 0x6e,
986 OPC2_32_RR_ABSDIFS = 0x0f,
987 OPC2_32_RR_ABSDIFS_H = 0x6f,
988 OPC2_32_RR_ABSS = 0x1d,
989 OPC2_32_RR_ABSS_H = 0x7d,
990 OPC2_32_RR_ADD = 0x00,
991 OPC2_32_RR_ADD_B = 0x40,
992 OPC2_32_RR_ADD_H = 0x60,
993 OPC2_32_RR_ADDC = 0x05,
994 OPC2_32_RR_ADDS = 0x02,
995 OPC2_32_RR_ADDS_H = 0x62,
996 OPC2_32_RR_ADDS_HU = 0x63,
997 OPC2_32_RR_ADDS_U = 0x03,
998 OPC2_32_RR_ADDX = 0x04,
999 OPC2_32_RR_AND_EQ = 0x20,
1000 OPC2_32_RR_AND_GE = 0x24,
1001 OPC2_32_RR_AND_GE_U = 0x25,
1002 OPC2_32_RR_AND_LT = 0x22,
1003 OPC2_32_RR_AND_LT_U = 0x23,
1004 OPC2_32_RR_AND_NE = 0x21,
1005 OPC2_32_RR_EQ = 0x10,
1006 OPC2_32_RR_EQ_B = 0x50,
1007 OPC2_32_RR_EQ_H = 0x70,
1008 OPC2_32_RR_EQ_W = 0x90,
1009 OPC2_32_RR_EQANY_B = 0x56,
1010 OPC2_32_RR_EQANY_H = 0x76,
1011 OPC2_32_RR_GE = 0x14,
1012 OPC2_32_RR_GE_U = 0x15,
1013 OPC2_32_RR_LT = 0x12,
1014 OPC2_32_RR_LT_U = 0x13,
1015 OPC2_32_RR_LT_B = 0x52,
1016 OPC2_32_RR_LT_BU = 0x53,
1017 OPC2_32_RR_LT_H = 0x72,
1018 OPC2_32_RR_LT_HU = 0x73,
1019 OPC2_32_RR_LT_W = 0x92,
1020 OPC2_32_RR_LT_WU = 0x93,
1021 OPC2_32_RR_MAX = 0x1a,
1022 OPC2_32_RR_MAX_U = 0x1b,
1023 OPC2_32_RR_MAX_B = 0x5a,
1024 OPC2_32_RR_MAX_BU = 0x5b,
1025 OPC2_32_RR_MAX_H = 0x7a,
1026 OPC2_32_RR_MAX_HU = 0x7b,
1027 OPC2_32_RR_MIN = 0x19,
1028 OPC2_32_RR_MIN_U = 0x18,
1029 OPC2_32_RR_MIN_B = 0x58,
1030 OPC2_32_RR_MIN_BU = 0x59,
1031 OPC2_32_RR_MIN_H = 0x78,
1032 OPC2_32_RR_MIN_HU = 0x79,
1033 OPC2_32_RR_MOV = 0x1f,
1034 OPC2_32_RR_NE = 0x11,
1035 OPC2_32_RR_OR_EQ = 0x27,
1036 OPC2_32_RR_OR_GE = 0x2b,
1037 OPC2_32_RR_OR_GE_U = 0x2c,
1038 OPC2_32_RR_OR_LT = 0x29,
1039 OPC2_32_RR_OR_LT_U = 0x2a,
1040 OPC2_32_RR_OR_NE = 0x28,
1041 OPC2_32_RR_SAT_B = 0x5e,
1042 OPC2_32_RR_SAT_BU = 0x5f,
1043 OPC2_32_RR_SAT_H = 0x7e,
1044 OPC2_32_RR_SAT_HU = 0x7f,
1045 OPC2_32_RR_SH_EQ = 0x37,
1046 OPC2_32_RR_SH_GE = 0x3b,
1047 OPC2_32_RR_SH_GE_U = 0x3c,
1048 OPC2_32_RR_SH_LT = 0x39,
1049 OPC2_32_RR_SH_LT_U = 0x3a,
1050 OPC2_32_RR_SH_NE = 0x38,
1051 OPC2_32_RR_SUB = 0x08,
1052 OPC2_32_RR_SUB_B = 0x48,
1053 OPC2_32_RR_SUB_H = 0x68,
1054 OPC2_32_RR_SUBC = 0x0d,
1055 OPC2_32_RR_SUBS = 0x0a,
1056 OPC2_32_RR_SUBS_U = 0x0b,
1057 OPC2_32_RR_SUBS_H = 0x6a,
1058 OPC2_32_RR_SUBS_HU = 0x6b,
1059 OPC2_32_RR_SUBX = 0x0c,
1060 OPC2_32_RR_XOR_EQ = 0x2f,
1061 OPC2_32_RR_XOR_GE = 0x33,
1062 OPC2_32_RR_XOR_GE_U = 0x34,
1063 OPC2_32_RR_XOR_LT = 0x31,
1064 OPC2_32_RR_XOR_LT_U = 0x32,
1065 OPC2_32_RR_XOR_NE = 0x30,
1066 };
1067 /* OPCM_32_RR_ADRESS */
1068 enum {
1069 OPC2_32_RR_ADD_A = 0x01,
1070 OPC2_32_RR_ADDSC_A = 0x60,
1071 OPC2_32_RR_ADDSC_AT = 0x62,
1072 OPC2_32_RR_EQ_A = 0x40,
1073 OPC2_32_RR_EQZ = 0x48,
1074 OPC2_32_RR_GE_A = 0x43,
1075 OPC2_32_RR_LT_A = 0x42,
1076 OPC2_32_RR_MOV_A = 0x63,
1077 OPC2_32_RR_MOV_AA = 0x00,
1078 OPC2_32_RR_MOV_D = 0x4c,
1079 OPC2_32_RR_NE_A = 0x41,
1080 OPC2_32_RR_NEZ_A = 0x49,
1081 OPC2_32_RR_SUB_A = 0x02,
1082 };
1083 /* OPCM_32_RR_FLOAT */
1084 enum {
1085 OPC2_32_RR_BMERGE = 0x01,
1086 OPC2_32_RR_BSPLIT = 0x09,
1087 OPC2_32_RR_DVINIT_B = 0x5a,
1088 OPC2_32_RR_DVINIT_BU = 0x4a,
1089 OPC2_32_RR_DVINIT_H = 0x3a,
1090 OPC2_32_RR_DVINIT_HU = 0x2a,
1091 OPC2_32_RR_DVINIT = 0x1a,
1092 OPC2_32_RR_DVINIT_U = 0x0a,
1093 OPC2_32_RR_PARITY = 0x02,
1094 OPC2_32_RR_UNPACK = 0x08,
1095 };
1096 /* OPCM_32_RR_IDIRECT */
1097 enum {
1098 OPC2_32_RR_JI = 0x03,
1099 OPC2_32_RR_JLI = 0x02,
1100 OPC2_32_RR_CALLI = 0x00,
1101 };
1102 /*
1103 * RR1 Format
1104 */
1105 /* OPCM_32_RR1_MUL */
1106 enum {
1107 OPC2_32_RR1_MUL_H_32_LL = 0x1a,
1108 OPC2_32_RR1_MUL_H_32_LU = 0x19,
1109 OPC2_32_RR1_MUL_H_32_UL = 0x18,
1110 OPC2_32_RR1_MUL_H_32_UU = 0x1b,
1111 OPC2_32_RR1_MULM_H_64_LL = 0x1e,
1112 OPC2_32_RR1_MULM_H_64_LU = 0x1d,
1113 OPC2_32_RR1_MULM_H_64_UL = 0x1c,
1114 OPC2_32_RR1_MULM_H_64_UU = 0x1f,
1115 OPC2_32_RR1_MULR_H_16_LL = 0x0e,
1116 OPC2_32_RR1_MULR_H_16_LU = 0x0d,
1117 OPC2_32_RR1_MULR_H_16_UL = 0x0c,
1118 OPC2_32_RR1_MULR_H_16_UU = 0x0f,
1119 };
1120 /* OPCM_32_RR1_MULQ */
1121 enum {
1122 OPC2_32_RR1_MUL_Q_32 = 0x02,
1123 OPC2_32_RR1_MUL_Q_64 = 0x1b,
1124 OPC2_32_RR1_MUL_Q_32_L = 0x01,
1125 OPC2_32_RR1_MUL_Q_64_L = 0x19,
1126 OPC2_32_RR1_MUL_Q_32_U = 0x00,
1127 OPC2_32_RR1_MUL_Q_64_U = 0x18,
1128 OPC2_32_RR1_MUL_Q_32_LL = 0x05,
1129 OPC2_32_RR1_MUL_Q_32_UU = 0x04,
1130 OPC2_32_RR1_MULR_Q_32_L = 0x07,
1131 OPC2_32_RR1_MULR_Q_32_U = 0x06,
1132 };
1133 /*
1134 * RR2 Format
1135 */
1136 /* OPCM_32_RR2_MUL */
1137 enum {
1138 OPC2_32_RR2_MUL_32 = 0x0a,
1139 OPC2_32_RR2_MUL_64 = 0x6a,
1140 OPC2_32_RR2_MULS_32 = 0x8a,
1141 OPC2_32_RR2_MUL_U_64 = 0x68,
1142 OPC2_32_RR2_MULS_U_32 = 0x88,
1143 };
1144 /*
1145 * RRPW Format
1146 */
1147 /* OPCM_32_RRPW_EXTRACT_INSERT */
1148 enum {
1149
1150 OPC2_32_RRPW_EXTR = 0x02,
1151 OPC2_32_RRPW_EXTR_U = 0x03,
1152 OPC2_32_RRPW_IMASK = 0x01,
1153 OPC2_32_RRPW_INSERT = 0x00,
1154 };
1155 /*
1156 * RRR Format
1157 */
1158 /* OPCM_32_RRR_COND_SELECT */
1159 enum {
1160 OPC2_32_RRR_CADD = 0x00,
1161 OPC2_32_RRR_CADDN = 0x01,
1162 OPC2_32_RRR_CSUB = 0x02,
1163 OPC2_32_RRR_CSUBN = 0x03,
1164 OPC2_32_RRR_SEL = 0x04,
1165 OPC2_32_RRR_SELN = 0x05,
1166 };
1167 /* OPCM_32_RRR_FLOAT */
1168 enum {
1169 OPC2_32_RRR_DVADJ = 0x0d,
1170 OPC2_32_RRR_DVSTEP = 0x0f,
1171 OPC2_32_RRR_DVSTEP_U = 0x0e,
1172 OPC2_32_RRR_IXMAX = 0x0a,
1173 OPC2_32_RRR_IXMAX_U = 0x0b,
1174 OPC2_32_RRR_IXMIN = 0x08,
1175 OPC2_32_RRR_IXMIN_U = 0x09,
1176 OPC2_32_RRR_PACK = 0x00,
1177 };
1178 /*
1179 * RRR1 Format
1180 */
1181 /* OPCM_32_RRR1_MADD */
1182 enum {
1183 OPC2_32_RRR1_MADD_H_LL = 0x1a,
1184 OPC2_32_RRR1_MADD_H_LU = 0x19,
1185 OPC2_32_RRR1_MADD_H_UL = 0x18,
1186 OPC2_32_RRR1_MADD_H_UU = 0x1b,
1187 OPC2_32_RRR1_MADDS_H_LL = 0x3a,
1188 OPC2_32_RRR1_MADDS_H_LU = 0x39,
1189 OPC2_32_RRR1_MADDS_H_UL = 0x38,
1190 OPC2_32_RRR1_MADDS_H_UU = 0x3b,
1191 OPC2_32_RRR1_MADDM_H_LL = 0x1e,
1192 OPC2_32_RRR1_MADDM_H_LU = 0x1d,
1193 OPC2_32_RRR1_MADDM_H_UL = 0x1c,
1194 OPC2_32_RRR1_MADDM_H_UU = 0x1f,
1195 OPC2_32_RRR1_MADDMS_H_LL = 0x3e,
1196 OPC2_32_RRR1_MADDMS_H_LU = 0x3d,
1197 OPC2_32_RRR1_MADDMS_H_UL = 0x3c,
1198 OPC2_32_RRR1_MADDMS_H_UU = 0x3f,
1199 OPC2_32_RRR1_MADDR_H_LL = 0x0e,
1200 OPC2_32_RRR1_MADDR_H_LU = 0x0d,
1201 OPC2_32_RRR1_MADDR_H_UL = 0x0c,
1202 OPC2_32_RRR1_MADDR_H_UU = 0x0f,
1203 OPC2_32_RRR1_MADDRS_H_LL = 0x2e,
1204 OPC2_32_RRR1_MADDRS_H_LU = 0x2d,
1205 OPC2_32_RRR1_MADDRS_H_UL = 0x2c,
1206 OPC2_32_RRR1_MADDRS_H_UU = 0x2f,
1207 };
1208 /* OPCM_32_RRR1_MADDQ_H */
1209 enum {
1210 OPC2_32_RRR1_MADD_Q_32 = 0x02,
1211 OPC2_32_RRR1_MADD_Q_64 = 0x1b,
1212 OPC2_32_RRR1_MADD_Q_32_L = 0x01,
1213 OPC2_32_RRR1_MADD_Q_64_L = 0x19,
1214 OPC2_32_RRR1_MADD_Q_32_U = 0x00,
1215 OPC2_32_RRR1_MADD_Q_64_U = 0x18,
1216 OPC2_32_RRR1_MADD_Q_32_LL = 0x05,
1217 OPC2_32_RRR1_MADD_Q_64_LL = 0x1d,
1218 OPC2_32_RRR1_MADD_Q_32_UU = 0x04,
1219 OPC2_32_RRR1_MADD_Q_64_UU = 0x1c,
1220 OPC2_32_RRR1_MADDS_Q_32 = 0x22,
1221 OPC2_32_RRR1_MADDS_Q_64 = 0x3b,
1222 OPC2_32_RRR1_MADDS_Q_32_L = 0x21,
1223 OPC2_32_RRR1_MADDS_Q_64_L = 0x39,
1224 OPC2_32_RRR1_MADDS_Q_32_U = 0x20,
1225 OPC2_32_RRR1_MADDS_Q_64_U = 0x38,
1226 OPC2_32_RRR1_MADDS_Q_32_LL = 0x25,
1227 OPC2_32_RRR1_MADDS_Q_64_LL = 0x3d,
1228 OPC2_32_RRR1_MADDS_Q_32_UU = 0x24,
1229 OPC2_32_RRR1_MADDS_Q_64_UU = 0x3c,
1230 OPC2_32_RRR1_MADDR_H_16_UL = 0x1e,
1231 OPC2_32_RRR1_MADDRS_H_16_UL = 0x3e,
1232 OPC2_32_RRR1_MADDR_Q_32_L = 0x07,
1233 OPC2_32_RRR1_MADDR_Q_32_U = 0x06,
1234 OPC2_32_RRR1_MADDRS_Q_32_LL = 0x27,
1235 OPC2_32_RRR1_MADDRS_Q_32_UU = 0x26,
1236 };
1237 /* OPCM_32_RRR1_MADDSU_H */
1238 enum {
1239 OPC2_32_RRR1_MADDSU_H_32_LL = 0x1a,
1240 OPC2_32_RRR1_MADDSU_H_32_LU = 0x19,
1241 OPC2_32_RRR1_MADDSU_H_32_UL = 0x18,
1242 OPC2_32_RRR1_MADDSU_H_32_UU = 0x1b,
1243 OPC2_32_RRR1_MADDSUS_H_32_LL = 0x3a,
1244 OPC2_32_RRR1_MADDSUS_H_32_LU = 0x39,
1245 OPC2_32_RRR1_MADDSUS_H_32_UL = 0x38,
1246 OPC2_32_RRR1_MADDSUS_H_32_UU = 0x3b,
1247 OPC2_32_RRR1_MADDSUM_H_64_LL = 0x1e,
1248 OPC2_32_RRR1_MADDSUM_H_64_LU = 0x1d,
1249 OPC2_32_RRR1_MADDSUM_H_64_UL = 0x1c,
1250 OPC2_32_RRR1_MADDSUM_H_64_UU = 0x1f,
1251 OPC2_32_RRR1_MADDSUMS_H_64_LL = 0x3e,
1252 OPC2_32_RRR1_MADDSUMS_H_64_LU = 0x3d,
1253 OPC2_32_RRR1_MADDSUMS_H_64_UL = 0x3c,
1254 OPC2_32_RRR1_MADDSUMS_H_64_UU = 0x3f,
1255 OPC2_32_RRR1_MADDSUR_H_16_LL = 0x0e,
1256 OPC2_32_RRR1_MADDSUR_H_16_LU = 0x0d,
1257 OPC2_32_RRR1_MADDSUR_H_16_UL = 0x0c,
1258 OPC2_32_RRR1_MADDSUR_H_16_UU = 0x0f,
1259 OPC2_32_RRR1_MADDSURS_H_16_LL = 0x2e,
1260 OPC2_32_RRR1_MADDSURS_H_16_LU = 0x2d,
1261 OPC2_32_RRR1_MADDSURS_H_16_UL = 0x2c,
1262 OPC2_32_RRR1_MADDSURS_H_16_UU = 0x2f,
1263 };
1264 /* OPCM_32_RRR1_MSUB_H */
1265 enum {
1266 OPC2_32_RRR1_MSUB_H_32_LL = 0x1a,
1267 OPC2_32_RRR1_MSUB_H_32_LU = 0x19,
1268 OPC2_32_RRR1_MSUB_H_32_UL = 0x18,
1269 OPC2_32_RRR1_MSUB_H_32_UU = 0x1b,
1270 OPC2_32_RRR1_MSUBS_H_32_LL = 0x3a,
1271 OPC2_32_RRR1_MSUBS_H_32_LU = 0x39,
1272 OPC2_32_RRR1_MSUBS_H_32_UL = 0x38,
1273 OPC2_32_RRR1_MSUBS_H_32_UU = 0x3b,
1274 OPC2_32_RRR1_MSUBM_H_64_LL = 0x1e,
1275 OPC2_32_RRR1_MSUBM_H_64_LU = 0x1d,
1276 OPC2_32_RRR1_MSUBM_H_64_UL = 0x1c,
1277 OPC2_32_RRR1_MSUBM_H_64_UU = 0x1f,
1278 OPC2_32_RRR1_MSUBMS_H_64_LL = 0x3e,
1279 OPC2_32_RRR1_MSUBMS_H_64_LU = 0x3d,
1280 OPC2_32_RRR1_MSUBMS_H_64_UL = 0x3c,
1281 OPC2_32_RRR1_MSUBMS_H_64_UU = 0x3f,
1282 OPC2_32_RRR1_MSUBR_H_16_LL = 0x0e,
1283 OPC2_32_RRR1_MSUBR_H_16_LU = 0x0d,
1284 OPC2_32_RRR1_MSUBR_H_16_UL = 0x0c,
1285 OPC2_32_RRR1_MSUBR_H_16_UU = 0x0f,
1286 OPC2_32_RRR1_MSUBRS_H_16_LL = 0x2e,
1287 OPC2_32_RRR1_MSUBRS_H_16_LU = 0x2d,
1288 OPC2_32_RRR1_MSUBRS_H_16_UL = 0x2c,
1289 OPC2_32_RRR1_MSUBRS_H_16_UU = 0x2f,
1290 };
1291 /* OPCM_32_RRR1_MSUB_Q */
1292 enum {
1293 OPC2_32_RRR1_MSUB_Q_32 = 0x02,
1294 OPC2_32_RRR1_MSUB_Q_64 = 0x1b,
1295 OPC2_32_RRR1_MSUB_Q_32_L = 0x01,
1296 OPC2_32_RRR1_MSUB_Q_64_L = 0x19,
1297 OPC2_32_RRR1_MSUB_Q_32_U = 0x00,
1298 OPC2_32_RRR1_MSUB_Q_64_U = 0x18,
1299 OPC2_32_RRR1_MSUB_Q_32_LL = 0x05,
1300 OPC2_32_RRR1_MSUB_Q_64_LL = 0x1d,
1301 OPC2_32_RRR1_MSUB_Q_32_UU = 0x04,
1302 OPC2_32_RRR1_MSUB_Q_64_UU = 0x1c,
1303 OPC2_32_RRR1_MSUBS_Q_32 = 0x22,
1304 OPC2_32_RRR1_MSUBS_Q_64 = 0x3b,
1305 OPC2_32_RRR1_MSUBS_Q_32_L = 0x21,
1306 OPC2_32_RRR1_MSUBS_Q_64_L = 0x39,
1307 OPC2_32_RRR1_MSUBS_Q_32_U = 0x20,
1308 OPC2_32_RRR1_MSUBS_Q_64_U = 0x38,
1309 OPC2_32_RRR1_MSUBS_Q_32_LL = 0x25,
1310 OPC2_32_RRR1_MSUBS_Q_64_LL = 0x3d,
1311 OPC2_32_RRR1_MSUBS_Q_32_UU = 0x24,
1312 OPC2_32_RRR1_MSUBS_Q_64_UU = 0x3c,
1313 OPC2_32_RRR1_MSUBR_H_32_UL = 0x1e,
1314 OPC2_32_RRR1_MSUBRS_H_32_UL = 0x3e,
1315 OPC2_32_RRR1_MSUBR_Q_32_LL = 0x07,
1316 OPC2_32_RRR1_MSUBR_Q_32_UU = 0x06,
1317 OPC2_32_RRR1_MSUBRS_Q_32_LL = 0x27,
1318 OPC2_32_RRR1_MSUBRS_Q_32_UU = 0x26,
1319 };
1320 /* OPCM_32_RRR1_MSUBADS_H */
1321 enum {
1322 OPC2_32_RRR1_MSUBAD_H_32_LL = 0x1a,
1323 OPC2_32_RRR1_MSUBAD_H_32_LU = 0x19,
1324 OPC2_32_RRR1_MSUBAD_H_32_UL = 0x18,
1325 OPC2_32_RRR1_MSUBAD_H_32_UU = 0x1b,
1326 OPC2_32_RRR1_MSUBADS_H_32_LL = 0x3a,
1327 OPC2_32_RRR1_MSUBADS_H_32_LU = 0x39,
1328 OPC2_32_RRR1_MSUBADS_H_32_UL = 0x38,
1329 OPC2_32_RRR1_MSUBADS_H_32_UU = 0x3b,
1330 OPC2_32_RRR1_MSUBADM_H_64_LL = 0x1e,
1331 OPC2_32_RRR1_MSUBADM_H_64_LU = 0x1d,
1332 OPC2_32_RRR1_MSUBADM_H_64_UL = 0x1c,
1333 OPC2_32_RRR1_MSUBADM_H_64_UU = 0x1f,
1334 OPC2_32_RRR1_MSUBADMS_H_64_LL = 0x3e,
1335 OPC2_32_RRR1_MSUBADMS_H_64_LU = 0x3d,
1336 OPC2_32_RRR1_MSUBADMS_H_64_UL = 0x3c,
1337 OPC2_32_RRR1_MSUBADMS_H_16_UU = 0x3f,
1338 OPC2_32_RRR1_MSUBADR_H_16_LL = 0x0e,
1339 OPC2_32_RRR1_MSUBADR_H_16_LU = 0x0d,
1340 OPC2_32_RRR1_MSUBADR_H_16_UL = 0x0c,
1341 OPC2_32_RRR1_MSUBADR_H_16_UU = 0x0f,
1342 OPC2_32_RRR1_MSUBADRS_H_16_LL = 0x2e,
1343 OPC2_32_RRR1_MSUBADRS_H_16_LU = 0x2d,
1344 OPC2_32_RRR1_MSUBADRS_H_16_UL = 0x2c,
1345 OPC2_32_RRR1_MSUBADRS_H_16_UU = 0x2f,
1346 };
1347 /*
1348 * RRR2 Format
1349 */
1350 /* OPCM_32_RRR2_MADD */
1351 enum {
1352 OPC2_32_RRR2_MADD_32 = 0x0a,
1353 OPC2_32_RRR2_MADD_64 = 0x6a,
1354 OPC2_32_RRR2_MADDS_32 = 0x8a,
1355 OPC2_32_RRR2_MADDS_64 = 0xea,
1356 OPC2_32_RRR2_MADD_U_32 = 0x68,
1357 OPC2_32_RRR2_MADDS_U_32 = 0x88,
1358 OPC2_32_RRR2_MADDS_U_64 = 0xe8,
1359 };
1360 /* OPCM_32_RRR2_MSUB */
1361 enum {
1362 OPC2_32_RRR2_MSUB_32 = 0x0a,
1363 OPC2_32_RRR2_MSUB_64 = 0x6a,
1364 OPC2_32_RRR2_MSUBS_32 = 0x8a,
1365 OPC2_32_RRR2_MSUBS_64 = 0xea,
1366 OPC2_32_RRR2_MSUB_U_64 = 0x68,
1367 OPC2_32_RRR2_MSUBS_U_32 = 0x88,
1368 OPC2_32_RRR2_MSUBS_U_64 = 0xe8,
1369 };
1370 /*
1371 * RRRR Format
1372 */
1373 /* OPCM_32_RRRR_EXTRACT_INSERT */
1374 enum {
1375 OPC2_32_RRRR_DEXTR = 0x04,
1376 OPC2_32_RRRR_EXTR = 0x02,
1377 OPC2_32_RRRR_EXTR_U = 0x03,
1378 OPC2_32_RRRR_INSERT = 0x00,
1379 };
1380 /*
1381 * RRRW Format
1382 */
1383 /* OPCM_32_RRRW_EXTRACT_INSERT */
1384 enum {
1385 OPC2_32_RRRW_EXTR = 0x02,
1386 OPC2_32_RRRW_EXTR_U = 0x03,
1387 OPC2_32_RRRW_IMASK = 0x01,
1388 OPC2_32_RRRW_INSERT = 0x00,
1389 };
1390 /*
1391 * SYS Format
1392 */
1393 /* OPCM_32_SYS_INTERRUPTS */
1394 enum {
1395 OPC2_32_SYS_DEBUG = 0x04,
1396 OPC2_32_SYS_DISABLE = 0x0d,
1397 OPC2_32_SYS_DSYNC = 0x12,
1398 OPC2_32_SYS_ENABLE = 0x0c,
1399 OPC2_32_SYS_ISYNC = 0x13,
1400 OPC2_32_SYS_NOP = 0x00,
1401 OPC2_32_SYS_RET = 0x06,
1402 OPC2_32_SYS_RFE = 0x07,
1403 OPC2_32_SYS_RFM = 0x05,
1404 OPC2_32_SYS_RSLCX = 0x09,
1405 OPC2_32_SYS_SVLCX = 0x08,
1406 OPC2_32_SYS_TRAPSV = 0x15,
1407 OPC2_32_SYS_TRAPV = 0x14,
1408 };
AR7 emulation for QEMU