target/i386/tcg/tcg-cpu.c

   1 /*
   2  * i386 TCG cpu class initialization
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "helper-tcg.h"
  23 #include "qemu/accel.h"
  24 #include "hw/core/accel-cpu.h"
  25
  26 #include "tcg-cpu.h"
  27
  28 /* Frob eflags into and out of the CPU temporary format.  */
  29
  30 static void x86_cpu_exec_enter(CPUState *cs)
  31 {
  32     X86CPU *cpu = X86_CPU(cs);
  33     CPUX86State *env = &cpu->env;
  34
  35     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
  36     env->df = 1 - (2 * ((env->eflags >> 10) & 1));
  37     CC_OP = CC_OP_EFLAGS;
  38     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
  39 }
  40
  41 static void x86_cpu_exec_exit(CPUState *cs)
  42 {
  43     X86CPU *cpu = X86_CPU(cs);
  44     CPUX86State *env = &cpu->env;
  45
  46     env->eflags = cpu_compute_eflags(env);
  47 }
  48
  49 static void x86_cpu_synchronize_from_tb(CPUState *cs,
  50                                         const TranslationBlock *tb)
  51 {
  52     X86CPU *cpu = X86_CPU(cs);
  53
  54     cpu->env.eip = tb->pc - tb->cs_base;
  55 }
  56
  57 #ifndef CONFIG_USER_ONLY
  58 static bool x86_debug_check_breakpoint(CPUState *cs)
  59 {
  60     X86CPU *cpu = X86_CPU(cs);
  61     CPUX86State *env = &cpu->env;
  62
  63     /* RF disables all architectural breakpoints. */
  64     return !(env->eflags & RF_MASK);
  65 }
  66 #endif
  67
  68 #include "hw/core/tcg-cpu-ops.h"
  69
  70 static const struct TCGCPUOps x86_tcg_ops = {
  71     .initialize = tcg_x86_init,
  72     .synchronize_from_tb = x86_cpu_synchronize_from_tb,
  73     .cpu_exec_enter = x86_cpu_exec_enter,
  74     .cpu_exec_exit = x86_cpu_exec_exit,
  75     .cpu_exec_interrupt = x86_cpu_exec_interrupt,
  76     .tlb_fill = x86_cpu_tlb_fill,
  77 #ifdef CONFIG_USER_ONLY
  78     .fake_user_interrupt = x86_cpu_do_interrupt,
  79 #else
  80     .do_interrupt = x86_cpu_do_interrupt,
  81     .debug_excp_handler = breakpoint_handler,
  82     .debug_check_breakpoint = x86_debug_check_breakpoint,
  83 #endif /* !CONFIG_USER_ONLY */
  84 };
  85
  86 static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
  87 {
  88     /* for x86, all cpus use the same set of operations */
  89     cc->tcg_ops = &x86_tcg_ops;
  90 }
  91
  92 static void tcg_cpu_class_init(CPUClass *cc)
  93 {
  94     cc->init_accel_cpu = tcg_cpu_init_ops;
  95 }
  96
  97 static void tcg_cpu_xsave_init(void)
  98 {
  99 #define XO(bit, field) \
 100     x86_ext_save_areas[bit].offset = offsetof(X86XSaveArea, field);
 101
 102     XO(XSTATE_FP_BIT, legacy);
 103     XO(XSTATE_SSE_BIT, legacy);
 104     XO(XSTATE_YMM_BIT, avx_state);
 105     XO(XSTATE_BNDREGS_BIT, bndreg_state);
 106     XO(XSTATE_BNDCSR_BIT, bndcsr_state);
 107     XO(XSTATE_OPMASK_BIT, opmask_state);
 108     XO(XSTATE_ZMM_Hi256_BIT, zmm_hi256_state);
 109     XO(XSTATE_Hi16_ZMM_BIT, hi16_zmm_state);
 110     XO(XSTATE_PKRU_BIT, pkru_state);
 111
 112 #undef XO
 113 }
 114
 115 /*
 116  * TCG-specific defaults that override cpudef models when using TCG.
 117  * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
 118  */
 119 static PropValue tcg_default_props[] = {
 120     { "vme", "off" },
 121     { NULL, NULL },
 122 };
 123
 124 static void tcg_cpu_instance_init(CPUState *cs)
 125 {
 126     X86CPU *cpu = X86_CPU(cs);
 127     X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
 128
 129     if (xcc->model) {
 130         /* Special cases not set in the X86CPUDefinition structs: */
 131         x86_cpu_apply_props(cpu, tcg_default_props);
 132     }
 133
 134     tcg_cpu_xsave_init();
 135 }
 136
 137 static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
 138 {
 139     AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
 140
 141 #ifndef CONFIG_USER_ONLY
 142     acc->cpu_realizefn = tcg_cpu_realizefn;
 143 #endif /* CONFIG_USER_ONLY */
 144
 145     acc->cpu_class_init = tcg_cpu_class_init;
 146     acc->cpu_instance_init = tcg_cpu_instance_init;
 147 }
 148 static const TypeInfo tcg_cpu_accel_type_info = {
 149     .name = ACCEL_CPU_NAME("tcg"),
 150
 151     .parent = TYPE_ACCEL_CPU,
 152     .class_init = tcg_cpu_accel_class_init,
 153     .abstract = true,
 154 };
 155 static void tcg_cpu_accel_register_types(void)
 156 {
 157     type_register_static(&tcg_cpu_accel_type_info);
 158 }
 159 type_init(tcg_cpu_accel_register_types);