?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge remote-tracking branch 'remotes/kraxel/tags/seabios-1.12-20181120-pull-request...
[qemu/ar7.git] / target / i386 / kvm.c
blobf524e7d9299e35b2759faed5969927dcdbd36f13
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include "standard-headers/asm-x86/kvm_para.h"
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30 #include "hyperv-proto.h"
31
32 #include "exec/gdbstub.h"
33 #include "qemu/host-utils.h"
34 #include "qemu/config-file.h"
35 #include "qemu/error-report.h"
36 #include "hw/i386/pc.h"
37 #include "hw/i386/apic.h"
38 #include "hw/i386/apic_internal.h"
39 #include "hw/i386/apic-msidef.h"
40 #include "hw/i386/intel_iommu.h"
41 #include "hw/i386/x86-iommu.h"
42
43 #include "hw/pci/pci.h"
44 #include "hw/pci/msi.h"
45 #include "hw/pci/msix.h"
46 #include "migration/blocker.h"
47 #include "exec/memattrs.h"
48 #include "trace.h"
49
50 //#define DEBUG_KVM
51
52 #ifdef DEBUG_KVM
53 #define DPRINTF(fmt, ...) \
54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55 #else
56 #define DPRINTF(fmt, ...) \
57 do { } while (0)
58 #endif
59
60 #define MSR_KVM_WALL_CLOCK 0x11
61 #define MSR_KVM_SYSTEM_TIME 0x12
62
63 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65 #define MSR_BUF_SIZE 4096
66
67 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
68 KVM_CAP_INFO(SET_TSS_ADDR),
69 KVM_CAP_INFO(EXT_CPUID),
70 KVM_CAP_INFO(MP_STATE),
71 KVM_CAP_LAST_INFO
72 };
73
74 static bool has_msr_star;
75 static bool has_msr_hsave_pa;
76 static bool has_msr_tsc_aux;
77 static bool has_msr_tsc_adjust;
78 static bool has_msr_tsc_deadline;
79 static bool has_msr_feature_control;
80 static bool has_msr_misc_enable;
81 static bool has_msr_smbase;
82 static bool has_msr_bndcfgs;
83 static int lm_capable_kernel;
84 static bool has_msr_hv_hypercall;
85 static bool has_msr_hv_crash;
86 static bool has_msr_hv_reset;
87 static bool has_msr_hv_vpindex;
88 static bool hv_vpindex_settable;
89 static bool has_msr_hv_runtime;
90 static bool has_msr_hv_synic;
91 static bool has_msr_hv_stimer;
92 static bool has_msr_hv_frequencies;
93 static bool has_msr_hv_reenlightenment;
94 static bool has_msr_xss;
95 static bool has_msr_spec_ctrl;
96 static bool has_msr_virt_ssbd;
97 static bool has_msr_smi_count;
98
99 static uint32_t has_architectural_pmu_version;
100 static uint32_t num_architectural_pmu_gp_counters;
101 static uint32_t num_architectural_pmu_fixed_counters;
102
103 static int has_xsave;
104 static int has_xcrs;
105 static int has_pit_state2;
106
107 static bool has_msr_mcg_ext_ctl;
108
109 static struct kvm_cpuid2 *cpuid_cache;
110 static struct kvm_msr_list *kvm_feature_msrs;
111
112 int kvm_has_pit_state2(void)
113 {
114 return has_pit_state2;
115 }
116
117 bool kvm_has_smm(void)
118 {
119 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
120 }
121
122 bool kvm_has_adjust_clock_stable(void)
123 {
124 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
125
126 return (ret == KVM_CLOCK_TSC_STABLE);
127 }
128
129 bool kvm_allows_irq0_override(void)
130 {
131 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
132 }
133
134 static bool kvm_x2apic_api_set_flags(uint64_t flags)
135 {
136 KVMState *s = KVM_STATE(current_machine->accelerator);
137
138 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
139 }
140
141 #define MEMORIZE(fn, _result) \
142 ({ \
143 static bool _memorized; \
144 \
145 if (_memorized) { \
146 return _result; \
147 } \
148 _memorized = true; \
149 _result = fn; \
150 })
151
152 static bool has_x2apic_api;
153
154 bool kvm_has_x2apic_api(void)
155 {
156 return has_x2apic_api;
157 }
158
159 bool kvm_enable_x2apic(void)
160 {
161 return MEMORIZE(
162 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
163 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
164 has_x2apic_api);
165 }
166
167 bool kvm_hv_vpindex_settable(void)
168 {
169 return hv_vpindex_settable;
170 }
171
172 static int kvm_get_tsc(CPUState *cs)
173 {
174 X86CPU *cpu = X86_CPU(cs);
175 CPUX86State *env = &cpu->env;
176 struct {
177 struct kvm_msrs info;
178 struct kvm_msr_entry entries[1];
179 } msr_data;
180 int ret;
181
182 if (env->tsc_valid) {
183 return 0;
184 }
185
186 msr_data.info.nmsrs = 1;
187 msr_data.entries[0].index = MSR_IA32_TSC;
188 env->tsc_valid = !runstate_is_running();
189
190 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
191 if (ret < 0) {
192 return ret;
193 }
194
195 assert(ret == 1);
196 env->tsc = msr_data.entries[0].data;
197 return 0;
198 }
199
200 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
201 {
202 kvm_get_tsc(cpu);
203 }
204
205 void kvm_synchronize_all_tsc(void)
206 {
207 CPUState *cpu;
208
209 if (kvm_enabled()) {
210 CPU_FOREACH(cpu) {
211 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
212 }
213 }
214 }
215
216 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
217 {
218 struct kvm_cpuid2 *cpuid;
219 int r, size;
220
221 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
222 cpuid = g_malloc0(size);
223 cpuid->nent = max;
224 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
225 if (r == 0 && cpuid->nent >= max) {
226 r = -E2BIG;
227 }
228 if (r < 0) {
229 if (r == -E2BIG) {
230 g_free(cpuid);
231 return NULL;
232 } else {
233 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
234 strerror(-r));
235 exit(1);
236 }
237 }
238 return cpuid;
239 }
240
241 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
242 * for all entries.
243 */
244 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
245 {
246 struct kvm_cpuid2 *cpuid;
247 int max = 1;
248
249 if (cpuid_cache != NULL) {
250 return cpuid_cache;
251 }
252 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
253 max *= 2;
254 }
255 cpuid_cache = cpuid;
256 return cpuid;
257 }
258
259 static const struct kvm_para_features {
260 int cap;
261 int feature;
262 } para_features[] = {
263 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
264 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
265 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
266 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
267 };
268
269 static int get_para_features(KVMState *s)
270 {
271 int i, features = 0;
272
273 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
274 if (kvm_check_extension(s, para_features[i].cap)) {
275 features |= (1 << para_features[i].feature);
276 }
277 }
278
279 return features;
280 }
281
282 static bool host_tsx_blacklisted(void)
283 {
284 int family, model, stepping;\
285 char vendor[CPUID_VENDOR_SZ + 1];
286
287 host_vendor_fms(vendor, &family, &model, &stepping);
288
289 /* Check if we are running on a Haswell host known to have broken TSX */
290 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
291 (family == 6) &&
292 ((model == 63 && stepping < 4) ||
293 model == 60 || model == 69 || model == 70);
294 }
295
296 /* Returns the value for a specific register on the cpuid entry
297 */
298 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
299 {
300 uint32_t ret = 0;
301 switch (reg) {
302 case R_EAX:
303 ret = entry->eax;
304 break;
305 case R_EBX:
306 ret = entry->ebx;
307 break;
308 case R_ECX:
309 ret = entry->ecx;
310 break;
311 case R_EDX:
312 ret = entry->edx;
313 break;
314 }
315 return ret;
316 }
317
318 /* Find matching entry for function/index on kvm_cpuid2 struct
319 */
320 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
321 uint32_t function,
322 uint32_t index)
323 {
324 int i;
325 for (i = 0; i < cpuid->nent; ++i) {
326 if (cpuid->entries[i].function == function &&
327 cpuid->entries[i].index == index) {
328 return &cpuid->entries[i];
329 }
330 }
331 /* not found: */
332 return NULL;
333 }
334
335 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
336 uint32_t index, int reg)
337 {
338 struct kvm_cpuid2 *cpuid;
339 uint32_t ret = 0;
340 uint32_t cpuid_1_edx;
341 bool found = false;
342
343 cpuid = get_supported_cpuid(s);
344
345 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
346 if (entry) {
347 found = true;
348 ret = cpuid_entry_get_reg(entry, reg);
349 }
350
351 /* Fixups for the data returned by KVM, below */
352
353 if (function == 1 && reg == R_EDX) {
354 /* KVM before 2.6.30 misreports the following features */
355 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
356 } else if (function == 1 && reg == R_ECX) {
357 /* We can set the hypervisor flag, even if KVM does not return it on
358 * GET_SUPPORTED_CPUID
359 */
360 ret |= CPUID_EXT_HYPERVISOR;
361 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
362 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
363 * and the irqchip is in the kernel.
364 */
365 if (kvm_irqchip_in_kernel() &&
366 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
367 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
368 }
369
370 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
371 * without the in-kernel irqchip
372 */
373 if (!kvm_irqchip_in_kernel()) {
374 ret &= ~CPUID_EXT_X2APIC;
375 }
376
377 if (enable_cpu_pm) {
378 int disable_exits = kvm_check_extension(s,
379 KVM_CAP_X86_DISABLE_EXITS);
380
381 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
382 ret |= CPUID_EXT_MONITOR;
383 }
384 }
385 } else if (function == 6 && reg == R_EAX) {
386 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
387 } else if (function == 7 && index == 0 && reg == R_EBX) {
388 if (host_tsx_blacklisted()) {
389 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
390 }
391 } else if (function == 0x80000001 && reg == R_ECX) {
392 /*
393 * It's safe to enable TOPOEXT even if it's not returned by
394 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
395 * us to keep CPU models including TOPOEXT runnable on older kernels.
396 */
397 ret |= CPUID_EXT3_TOPOEXT;
398 } else if (function == 0x80000001 && reg == R_EDX) {
399 /* On Intel, kvm returns cpuid according to the Intel spec,
400 * so add missing bits according to the AMD spec:
401 */
402 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
403 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
404 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
405 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
406 * be enabled without the in-kernel irqchip
407 */
408 if (!kvm_irqchip_in_kernel()) {
409 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
410 }
411 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
412 ret |= 1U << KVM_HINTS_REALTIME;
413 found = 1;
414 }
415
416 /* fallback for older kernels */
417 if ((function == KVM_CPUID_FEATURES) && !found) {
418 ret = get_para_features(s);
419 }
420
421 return ret;
422 }
423
424 uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
425 {
426 struct {
427 struct kvm_msrs info;
428 struct kvm_msr_entry entries[1];
429 } msr_data;
430 uint32_t ret;
431
432 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
433 return 0;
434 }
435
436 /* Check if requested MSR is supported feature MSR */
437 int i;
438 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
439 if (kvm_feature_msrs->indices[i] == index) {
440 break;
441 }
442 if (i == kvm_feature_msrs->nmsrs) {
443 return 0; /* if the feature MSR is not supported, simply return 0 */
444 }
445
446 msr_data.info.nmsrs = 1;
447 msr_data.entries[0].index = index;
448
449 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
450 if (ret != 1) {
451 error_report("KVM get MSR (index=0x%x) feature failed, %s",
452 index, strerror(-ret));
453 exit(1);
454 }
455
456 return msr_data.entries[0].data;
457 }
458
459
460 typedef struct HWPoisonPage {
461 ram_addr_t ram_addr;
462 QLIST_ENTRY(HWPoisonPage) list;
463 } HWPoisonPage;
464
465 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
466 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
467
468 static void kvm_unpoison_all(void *param)
469 {
470 HWPoisonPage *page, *next_page;
471
472 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
473 QLIST_REMOVE(page, list);
474 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
475 g_free(page);
476 }
477 }
478
479 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
480 {
481 HWPoisonPage *page;
482
483 QLIST_FOREACH(page, &hwpoison_page_list, list) {
484 if (page->ram_addr == ram_addr) {
485 return;
486 }
487 }
488 page = g_new(HWPoisonPage, 1);
489 page->ram_addr = ram_addr;
490 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
491 }
492
493 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
494 int *max_banks)
495 {
496 int r;
497
498 r = kvm_check_extension(s, KVM_CAP_MCE);
499 if (r > 0) {
500 *max_banks = r;
501 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
502 }
503 return -ENOSYS;
504 }
505
506 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
507 {
508 CPUState *cs = CPU(cpu);
509 CPUX86State *env = &cpu->env;
510 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
511 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
512 uint64_t mcg_status = MCG_STATUS_MCIP;
513 int flags = 0;
514
515 if (code == BUS_MCEERR_AR) {
516 status |= MCI_STATUS_AR | 0x134;
517 mcg_status |= MCG_STATUS_EIPV;
518 } else {
519 status |= 0xc0;
520 mcg_status |= MCG_STATUS_RIPV;
521 }
522
523 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
524 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
525 * guest kernel back into env->mcg_ext_ctl.
526 */
527 cpu_synchronize_state(cs);
528 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
529 mcg_status |= MCG_STATUS_LMCE;
530 flags = 0;
531 }
532
533 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
534 (MCM_ADDR_PHYS << 6) | 0xc, flags);
535 }
536
537 static void hardware_memory_error(void)
538 {
539 fprintf(stderr, "Hardware memory error!\n");
540 exit(1);
541 }
542
543 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
544 {
545 X86CPU *cpu = X86_CPU(c);
546 CPUX86State *env = &cpu->env;
547 ram_addr_t ram_addr;
548 hwaddr paddr;
549
550 /* If we get an action required MCE, it has been injected by KVM
551 * while the VM was running. An action optional MCE instead should
552 * be coming from the main thread, which qemu_init_sigbus identifies
553 * as the "early kill" thread.
554 */
555 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
556
557 if ((env->mcg_cap & MCG_SER_P) && addr) {
558 ram_addr = qemu_ram_addr_from_host(addr);
559 if (ram_addr != RAM_ADDR_INVALID &&
560 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
561 kvm_hwpoison_page_add(ram_addr);
562 kvm_mce_inject(cpu, paddr, code);
563 return;
564 }
565
566 fprintf(stderr, "Hardware memory error for memory used by "
567 "QEMU itself instead of guest system!\n");
568 }
569
570 if (code == BUS_MCEERR_AR) {
571 hardware_memory_error();
572 }
573
574 /* Hope we are lucky for AO MCE */
575 }
576
577 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
578 {
579 CPUX86State *env = &cpu->env;
580
581 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
582 unsigned int bank, bank_num = env->mcg_cap & 0xff;
583 struct kvm_x86_mce mce;
584
585 env->exception_injected = -1;
586
587 /*
588 * There must be at least one bank in use if an MCE is pending.
589 * Find it and use its values for the event injection.
590 */
591 for (bank = 0; bank < bank_num; bank++) {
592 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
593 break;
594 }
595 }
596 assert(bank < bank_num);
597
598 mce.bank = bank;
599 mce.status = env->mce_banks[bank * 4 + 1];
600 mce.mcg_status = env->mcg_status;
601 mce.addr = env->mce_banks[bank * 4 + 2];
602 mce.misc = env->mce_banks[bank * 4 + 3];
603
604 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
605 }
606 return 0;
607 }
608
609 static void cpu_update_state(void *opaque, int running, RunState state)
610 {
611 CPUX86State *env = opaque;
612
613 if (running) {
614 env->tsc_valid = false;
615 }
616 }
617
618 unsigned long kvm_arch_vcpu_id(CPUState *cs)
619 {
620 X86CPU *cpu = X86_CPU(cs);
621 return cpu->apic_id;
622 }
623
624 #ifndef KVM_CPUID_SIGNATURE_NEXT
625 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
626 #endif
627
628 static bool hyperv_hypercall_available(X86CPU *cpu)
629 {
630 return cpu->hyperv_vapic ||
631 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
632 }
633
634 static bool hyperv_enabled(X86CPU *cpu)
635 {
636 CPUState *cs = CPU(cpu);
637 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
638 (hyperv_hypercall_available(cpu) ||
639 cpu->hyperv_time ||
640 cpu->hyperv_relaxed_timing ||
641 cpu->hyperv_crash ||
642 cpu->hyperv_reset ||
643 cpu->hyperv_vpindex ||
644 cpu->hyperv_runtime ||
645 cpu->hyperv_synic ||
646 cpu->hyperv_stimer ||
647 cpu->hyperv_reenlightenment ||
648 cpu->hyperv_tlbflush ||
649 cpu->hyperv_ipi);
650 }
651
652 static int kvm_arch_set_tsc_khz(CPUState *cs)
653 {
654 X86CPU *cpu = X86_CPU(cs);
655 CPUX86State *env = &cpu->env;
656 int r;
657
658 if (!env->tsc_khz) {
659 return 0;
660 }
661
662 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
663 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
664 -ENOTSUP;
665 if (r < 0) {
666 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
667 * TSC frequency doesn't match the one we want.
668 */
669 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
670 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
671 -ENOTSUP;
672 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
673 warn_report("TSC frequency mismatch between "
674 "VM (%" PRId64 " kHz) and host (%d kHz), "
675 "and TSC scaling unavailable",
676 env->tsc_khz, cur_freq);
677 return r;
678 }
679 }
680
681 return 0;
682 }
683
684 static bool tsc_is_stable_and_known(CPUX86State *env)
685 {
686 if (!env->tsc_khz) {
687 return false;
688 }
689 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
690 || env->user_tsc_khz;
691 }
692
693 static int hyperv_handle_properties(CPUState *cs)
694 {
695 X86CPU *cpu = X86_CPU(cs);
696 CPUX86State *env = &cpu->env;
697
698 if (cpu->hyperv_relaxed_timing) {
699 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
700 }
701 if (cpu->hyperv_vapic) {
702 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
703 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
704 }
705 if (cpu->hyperv_time) {
706 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
707 fprintf(stderr, "Hyper-V clocksources "
708 "(requested by 'hv-time' cpu flag) "
709 "are not supported by kernel\n");
710 return -ENOSYS;
711 }
712 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
713 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
714 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
715 }
716 if (cpu->hyperv_frequencies) {
717 if (!has_msr_hv_frequencies) {
718 fprintf(stderr, "Hyper-V frequency MSRs "
719 "(requested by 'hv-frequencies' cpu flag) "
720 "are not supported by kernel\n");
721 return -ENOSYS;
722 }
723 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
724 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
725 }
726 if (cpu->hyperv_crash) {
727 if (!has_msr_hv_crash) {
728 fprintf(stderr, "Hyper-V crash MSRs "
729 "(requested by 'hv-crash' cpu flag) "
730 "are not supported by kernel\n");
731 return -ENOSYS;
732 }
733 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
734 }
735 if (cpu->hyperv_reenlightenment) {
736 if (!has_msr_hv_reenlightenment) {
737 fprintf(stderr,
738 "Hyper-V Reenlightenment MSRs "
739 "(requested by 'hv-reenlightenment' cpu flag) "
740 "are not supported by kernel\n");
741 return -ENOSYS;
742 }
743 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
744 }
745 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
746 if (cpu->hyperv_reset) {
747 if (!has_msr_hv_reset) {
748 fprintf(stderr, "Hyper-V reset MSR "
749 "(requested by 'hv-reset' cpu flag) "
750 "is not supported by kernel\n");
751 return -ENOSYS;
752 }
753 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
754 }
755 if (cpu->hyperv_vpindex) {
756 if (!has_msr_hv_vpindex) {
757 fprintf(stderr, "Hyper-V VP_INDEX MSR "
758 "(requested by 'hv-vpindex' cpu flag) "
759 "is not supported by kernel\n");
760 return -ENOSYS;
761 }
762 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
763 }
764 if (cpu->hyperv_runtime) {
765 if (!has_msr_hv_runtime) {
766 fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
767 "(requested by 'hv-runtime' cpu flag) "
768 "is not supported by kernel\n");
769 return -ENOSYS;
770 }
771 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
772 }
773 if (cpu->hyperv_synic) {
774 unsigned int cap = KVM_CAP_HYPERV_SYNIC;
775 if (!cpu->hyperv_synic_kvm_only) {
776 if (!cpu->hyperv_vpindex) {
777 fprintf(stderr, "Hyper-V SynIC "
778 "(requested by 'hv-synic' cpu flag) "
779 "requires Hyper-V VP_INDEX ('hv-vpindex')\n");
780 return -ENOSYS;
781 }
782 cap = KVM_CAP_HYPERV_SYNIC2;
783 }
784
785 if (!has_msr_hv_synic || !kvm_check_extension(cs->kvm_state, cap)) {
786 fprintf(stderr, "Hyper-V SynIC (requested by 'hv-synic' cpu flag) "
787 "is not supported by kernel\n");
788 return -ENOSYS;
789 }
790
791 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
792 }
793 if (cpu->hyperv_stimer) {
794 if (!has_msr_hv_stimer) {
795 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
796 return -ENOSYS;
797 }
798 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
799 }
800 return 0;
801 }
802
803 static int hyperv_init_vcpu(X86CPU *cpu)
804 {
805 CPUState *cs = CPU(cpu);
806 int ret;
807
808 if (cpu->hyperv_vpindex && !hv_vpindex_settable) {
809 /*
810 * the kernel doesn't support setting vp_index; assert that its value
811 * is in sync
812 */
813 struct {
814 struct kvm_msrs info;
815 struct kvm_msr_entry entries[1];
816 } msr_data = {
817 .info.nmsrs = 1,
818 .entries[0].index = HV_X64_MSR_VP_INDEX,
819 };
820
821 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
822 if (ret < 0) {
823 return ret;
824 }
825 assert(ret == 1);
826
827 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
828 error_report("kernel's vp_index != QEMU's vp_index");
829 return -ENXIO;
830 }
831 }
832
833 if (cpu->hyperv_synic) {
834 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
835 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
836 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
837 if (ret < 0) {
838 error_report("failed to turn on HyperV SynIC in KVM: %s",
839 strerror(-ret));
840 return ret;
841 }
842
843 if (!cpu->hyperv_synic_kvm_only) {
844 ret = hyperv_x86_synic_add(cpu);
845 if (ret < 0) {
846 error_report("failed to create HyperV SynIC: %s",
847 strerror(-ret));
848 return ret;
849 }
850 }
851 }
852
853 return 0;
854 }
855
856 static Error *invtsc_mig_blocker;
857
858 #define KVM_MAX_CPUID_ENTRIES 100
859
860 int kvm_arch_init_vcpu(CPUState *cs)
861 {
862 struct {
863 struct kvm_cpuid2 cpuid;
864 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
865 } QEMU_PACKED cpuid_data;
866 X86CPU *cpu = X86_CPU(cs);
867 CPUX86State *env = &cpu->env;
868 uint32_t limit, i, j, cpuid_i;
869 uint32_t unused;
870 struct kvm_cpuid_entry2 *c;
871 uint32_t signature[3];
872 uint16_t evmcs_version;
873 int kvm_base = KVM_CPUID_SIGNATURE;
874 int r;
875 Error *local_err = NULL;
876
877 memset(&cpuid_data, 0, sizeof(cpuid_data));
878
879 cpuid_i = 0;
880
881 r = kvm_arch_set_tsc_khz(cs);
882 if (r < 0) {
883 goto fail;
884 }
885
886 /* vcpu's TSC frequency is either specified by user, or following
887 * the value used by KVM if the former is not present. In the
888 * latter case, we query it from KVM and record in env->tsc_khz,
889 * so that vcpu's TSC frequency can be migrated later via this field.
890 */
891 if (!env->tsc_khz) {
892 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
893 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
894 -ENOTSUP;
895 if (r > 0) {
896 env->tsc_khz = r;
897 }
898 }
899
900 /* Paravirtualization CPUIDs */
901 if (hyperv_enabled(cpu)) {
902 c = &cpuid_data.entries[cpuid_i++];
903 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
904 if (!cpu->hyperv_vendor_id) {
905 memcpy(signature, "Microsoft Hv", 12);
906 } else {
907 size_t len = strlen(cpu->hyperv_vendor_id);
908
909 if (len > 12) {
910 error_report("hv-vendor-id truncated to 12 characters");
911 len = 12;
912 }
913 memset(signature, 0, 12);
914 memcpy(signature, cpu->hyperv_vendor_id, len);
915 }
916 c->eax = cpu->hyperv_evmcs ?
917 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
918 c->ebx = signature[0];
919 c->ecx = signature[1];
920 c->edx = signature[2];
921
922 c = &cpuid_data.entries[cpuid_i++];
923 c->function = HV_CPUID_INTERFACE;
924 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
925 c->eax = signature[0];
926 c->ebx = 0;
927 c->ecx = 0;
928 c->edx = 0;
929
930 c = &cpuid_data.entries[cpuid_i++];
931 c->function = HV_CPUID_VERSION;
932 c->eax = 0x00001bbc;
933 c->ebx = 0x00060001;
934
935 c = &cpuid_data.entries[cpuid_i++];
936 c->function = HV_CPUID_FEATURES;
937 r = hyperv_handle_properties(cs);
938 if (r) {
939 return r;
940 }
941 c->eax = env->features[FEAT_HYPERV_EAX];
942 c->ebx = env->features[FEAT_HYPERV_EBX];
943 c->edx = env->features[FEAT_HYPERV_EDX];
944
945 c = &cpuid_data.entries[cpuid_i++];
946 c->function = HV_CPUID_ENLIGHTMENT_INFO;
947 if (cpu->hyperv_relaxed_timing) {
948 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
949 }
950 if (cpu->hyperv_vapic) {
951 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
952 }
953 if (cpu->hyperv_tlbflush) {
954 if (kvm_check_extension(cs->kvm_state,
955 KVM_CAP_HYPERV_TLBFLUSH) <= 0) {
956 fprintf(stderr, "Hyper-V TLB flush support "
957 "(requested by 'hv-tlbflush' cpu flag) "
958 " is not supported by kernel\n");
959 return -ENOSYS;
960 }
961 c->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
962 c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
963 }
964 if (cpu->hyperv_ipi) {
965 if (kvm_check_extension(cs->kvm_state,
966 KVM_CAP_HYPERV_SEND_IPI) <= 0) {
967 fprintf(stderr, "Hyper-V IPI send support "
968 "(requested by 'hv-ipi' cpu flag) "
969 " is not supported by kernel\n");
970 return -ENOSYS;
971 }
972 c->eax |= HV_CLUSTER_IPI_RECOMMENDED;
973 c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
974 }
975 if (cpu->hyperv_evmcs) {
976 if (kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
977 (uintptr_t)&evmcs_version)) {
978 fprintf(stderr, "Hyper-V Enlightened VMCS "
979 "(requested by 'hv-evmcs' cpu flag) "
980 "is not supported by kernel\n");
981 return -ENOSYS;
982 }
983 c->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
984 }
985 c->ebx = cpu->hyperv_spinlock_attempts;
986
987 c = &cpuid_data.entries[cpuid_i++];
988 c->function = HV_CPUID_IMPLEMENT_LIMITS;
989
990 c->eax = cpu->hv_max_vps;
991 c->ebx = 0x40;
992
993 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
994 has_msr_hv_hypercall = true;
995
996 if (cpu->hyperv_evmcs) {
997 __u32 function;
998
999 /* Create zeroed 0x40000006..0x40000009 leaves */
1000 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1001 function < HV_CPUID_NESTED_FEATURES; function++) {
1002 c = &cpuid_data.entries[cpuid_i++];
1003 c->function = function;
1004 }
1005
1006 c = &cpuid_data.entries[cpuid_i++];
1007 c->function = HV_CPUID_NESTED_FEATURES;
1008 c->eax = evmcs_version;
1009 }
1010 }
1011
1012 if (cpu->expose_kvm) {
1013 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1014 c = &cpuid_data.entries[cpuid_i++];
1015 c->function = KVM_CPUID_SIGNATURE | kvm_base;
1016 c->eax = KVM_CPUID_FEATURES | kvm_base;
1017 c->ebx = signature[0];
1018 c->ecx = signature[1];
1019 c->edx = signature[2];
1020
1021 c = &cpuid_data.entries[cpuid_i++];
1022 c->function = KVM_CPUID_FEATURES | kvm_base;
1023 c->eax = env->features[FEAT_KVM];
1024 c->edx = env->features[FEAT_KVM_HINTS];
1025 }
1026
1027 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1028
1029 for (i = 0; i <= limit; i++) {
1030 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1031 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1032 abort();
1033 }
1034 c = &cpuid_data.entries[cpuid_i++];
1035
1036 switch (i) {
1037 case 2: {
1038 /* Keep reading function 2 till all the input is received */
1039 int times;
1040
1041 c->function = i;
1042 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1043 KVM_CPUID_FLAG_STATE_READ_NEXT;
1044 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1045 times = c->eax & 0xff;
1046
1047 for (j = 1; j < times; ++j) {
1048 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1049 fprintf(stderr, "cpuid_data is full, no space for "
1050 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1051 abort();
1052 }
1053 c = &cpuid_data.entries[cpuid_i++];
1054 c->function = i;
1055 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1056 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1057 }
1058 break;
1059 }
1060 case 4:
1061 case 0xb:
1062 case 0xd:
1063 for (j = 0; ; j++) {
1064 if (i == 0xd && j == 64) {
1065 break;
1066 }
1067 c->function = i;
1068 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1069 c->index = j;
1070 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1071
1072 if (i == 4 && c->eax == 0) {
1073 break;
1074 }
1075 if (i == 0xb && !(c->ecx & 0xff00)) {
1076 break;
1077 }
1078 if (i == 0xd && c->eax == 0) {
1079 continue;
1080 }
1081 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1082 fprintf(stderr, "cpuid_data is full, no space for "
1083 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1084 abort();
1085 }
1086 c = &cpuid_data.entries[cpuid_i++];
1087 }
1088 break;
1089 case 0x14: {
1090 uint32_t times;
1091
1092 c->function = i;
1093 c->index = 0;
1094 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1095 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1096 times = c->eax;
1097
1098 for (j = 1; j <= times; ++j) {
1099 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1100 fprintf(stderr, "cpuid_data is full, no space for "
1101 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1102 abort();
1103 }
1104 c = &cpuid_data.entries[cpuid_i++];
1105 c->function = i;
1106 c->index = j;
1107 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1108 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1109 }
1110 break;
1111 }
1112 default:
1113 c->function = i;
1114 c->flags = 0;
1115 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1116 break;
1117 }
1118 }
1119
1120 if (limit >= 0x0a) {
1121 uint32_t eax, edx;
1122
1123 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1124
1125 has_architectural_pmu_version = eax & 0xff;
1126 if (has_architectural_pmu_version > 0) {
1127 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1128
1129 /* Shouldn't be more than 32, since that's the number of bits
1130 * available in EBX to tell us _which_ counters are available.
1131 * Play it safe.
1132 */
1133 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1134 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1135 }
1136
1137 if (has_architectural_pmu_version > 1) {
1138 num_architectural_pmu_fixed_counters = edx & 0x1f;
1139
1140 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1141 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1142 }
1143 }
1144 }
1145 }
1146
1147 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1148
1149 for (i = 0x80000000; i <= limit; i++) {
1150 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1151 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1152 abort();
1153 }
1154 c = &cpuid_data.entries[cpuid_i++];
1155
1156 switch (i) {
1157 case 0x8000001d:
1158 /* Query for all AMD cache information leaves */
1159 for (j = 0; ; j++) {
1160 c->function = i;
1161 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1162 c->index = j;
1163 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1164
1165 if (c->eax == 0) {
1166 break;
1167 }
1168 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1169 fprintf(stderr, "cpuid_data is full, no space for "
1170 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1171 abort();
1172 }
1173 c = &cpuid_data.entries[cpuid_i++];
1174 }
1175 break;
1176 default:
1177 c->function = i;
1178 c->flags = 0;
1179 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1180 break;
1181 }
1182 }
1183
1184 /* Call Centaur's CPUID instructions they are supported. */
1185 if (env->cpuid_xlevel2 > 0) {
1186 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1187
1188 for (i = 0xC0000000; i <= limit; i++) {
1189 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1190 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1191 abort();
1192 }
1193 c = &cpuid_data.entries[cpuid_i++];
1194
1195 c->function = i;
1196 c->flags = 0;
1197 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1198 }
1199 }
1200
1201 cpuid_data.cpuid.nent = cpuid_i;
1202
1203 if (((env->cpuid_version >> 8)&0xF) >= 6
1204 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1205 (CPUID_MCE | CPUID_MCA)
1206 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1207 uint64_t mcg_cap, unsupported_caps;
1208 int banks;
1209 int ret;
1210
1211 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1212 if (ret < 0) {
1213 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1214 return ret;
1215 }
1216
1217 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1218 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1219 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1220 return -ENOTSUP;
1221 }
1222
1223 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1224 if (unsupported_caps) {
1225 if (unsupported_caps & MCG_LMCE_P) {
1226 error_report("kvm: LMCE not supported");
1227 return -ENOTSUP;
1228 }
1229 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1230 unsupported_caps);
1231 }
1232
1233 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1234 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1235 if (ret < 0) {
1236 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1237 return ret;
1238 }
1239 }
1240
1241 qemu_add_vm_change_state_handler(cpu_update_state, env);
1242
1243 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1244 if (c) {
1245 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1246 !!(c->ecx & CPUID_EXT_SMX);
1247 }
1248
1249 if (env->mcg_cap & MCG_LMCE_P) {
1250 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1251 }
1252
1253 if (!env->user_tsc_khz) {
1254 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1255 invtsc_mig_blocker == NULL) {
1256 /* for migration */
1257 error_setg(&invtsc_mig_blocker,
1258 "State blocked by non-migratable CPU device"
1259 " (invtsc flag)");
1260 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1261 if (local_err) {
1262 error_report_err(local_err);
1263 error_free(invtsc_mig_blocker);
1264 return r;
1265 }
1266 /* for savevm */
1267 vmstate_x86_cpu.unmigratable = 1;
1268 }
1269 }
1270
1271 if (cpu->vmware_cpuid_freq
1272 /* Guests depend on 0x40000000 to detect this feature, so only expose
1273 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1274 && cpu->expose_kvm
1275 && kvm_base == KVM_CPUID_SIGNATURE
1276 /* TSC clock must be stable and known for this feature. */
1277 && tsc_is_stable_and_known(env)) {
1278
1279 c = &cpuid_data.entries[cpuid_i++];
1280 c->function = KVM_CPUID_SIGNATURE | 0x10;
1281 c->eax = env->tsc_khz;
1282 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1283 * APIC_BUS_CYCLE_NS */
1284 c->ebx = 1000000;
1285 c->ecx = c->edx = 0;
1286
1287 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1288 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1289 }
1290
1291 cpuid_data.cpuid.nent = cpuid_i;
1292
1293 cpuid_data.cpuid.padding = 0;
1294 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1295 if (r) {
1296 goto fail;
1297 }
1298
1299 if (has_xsave) {
1300 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1301 }
1302 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1303
1304 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1305 has_msr_tsc_aux = false;
1306 }
1307
1308 r = hyperv_init_vcpu(cpu);
1309 if (r) {
1310 goto fail;
1311 }
1312
1313 return 0;
1314
1315 fail:
1316 migrate_del_blocker(invtsc_mig_blocker);
1317 return r;
1318 }
1319
1320 void kvm_arch_reset_vcpu(X86CPU *cpu)
1321 {
1322 CPUX86State *env = &cpu->env;
1323
1324 env->xcr0 = 1;
1325 if (kvm_irqchip_in_kernel()) {
1326 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1327 KVM_MP_STATE_UNINITIALIZED;
1328 } else {
1329 env->mp_state = KVM_MP_STATE_RUNNABLE;
1330 }
1331
1332 if (cpu->hyperv_synic) {
1333 int i;
1334 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1335 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1336 }
1337
1338 hyperv_x86_synic_reset(cpu);
1339 }
1340 }
1341
1342 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1343 {
1344 CPUX86State *env = &cpu->env;
1345
1346 /* APs get directly into wait-for-SIPI state. */
1347 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1348 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1349 }
1350 }
1351
1352 static int kvm_get_supported_feature_msrs(KVMState *s)
1353 {
1354 int ret = 0;
1355
1356 if (kvm_feature_msrs != NULL) {
1357 return 0;
1358 }
1359
1360 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1361 return 0;
1362 }
1363
1364 struct kvm_msr_list msr_list;
1365
1366 msr_list.nmsrs = 0;
1367 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1368 if (ret < 0 && ret != -E2BIG) {
1369 error_report("Fetch KVM feature MSR list failed: %s",
1370 strerror(-ret));
1371 return ret;
1372 }
1373
1374 assert(msr_list.nmsrs > 0);
1375 kvm_feature_msrs = (struct kvm_msr_list *) \
1376 g_malloc0(sizeof(msr_list) +
1377 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1378
1379 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1380 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1381
1382 if (ret < 0) {
1383 error_report("Fetch KVM feature MSR list failed: %s",
1384 strerror(-ret));
1385 g_free(kvm_feature_msrs);
1386 kvm_feature_msrs = NULL;
1387 return ret;
1388 }
1389
1390 return 0;
1391 }
1392
1393 static int kvm_get_supported_msrs(KVMState *s)
1394 {
1395 static int kvm_supported_msrs;
1396 int ret = 0;
1397
1398 /* first time */
1399 if (kvm_supported_msrs == 0) {
1400 struct kvm_msr_list msr_list, *kvm_msr_list;
1401
1402 kvm_supported_msrs = -1;
1403
1404 /* Obtain MSR list from KVM. These are the MSRs that we must
1405 * save/restore */
1406 msr_list.nmsrs = 0;
1407 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1408 if (ret < 0 && ret != -E2BIG) {
1409 return ret;
1410 }
1411 /* Old kernel modules had a bug and could write beyond the provided
1412 memory. Allocate at least a safe amount of 1K. */
1413 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1414 msr_list.nmsrs *
1415 sizeof(msr_list.indices[0])));
1416
1417 kvm_msr_list->nmsrs = msr_list.nmsrs;
1418 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1419 if (ret >= 0) {
1420 int i;
1421
1422 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1423 switch (kvm_msr_list->indices[i]) {
1424 case MSR_STAR:
1425 has_msr_star = true;
1426 break;
1427 case MSR_VM_HSAVE_PA:
1428 has_msr_hsave_pa = true;
1429 break;
1430 case MSR_TSC_AUX:
1431 has_msr_tsc_aux = true;
1432 break;
1433 case MSR_TSC_ADJUST:
1434 has_msr_tsc_adjust = true;
1435 break;
1436 case MSR_IA32_TSCDEADLINE:
1437 has_msr_tsc_deadline = true;
1438 break;
1439 case MSR_IA32_SMBASE:
1440 has_msr_smbase = true;
1441 break;
1442 case MSR_SMI_COUNT:
1443 has_msr_smi_count = true;
1444 break;
1445 case MSR_IA32_MISC_ENABLE:
1446 has_msr_misc_enable = true;
1447 break;
1448 case MSR_IA32_BNDCFGS:
1449 has_msr_bndcfgs = true;
1450 break;
1451 case MSR_IA32_XSS:
1452 has_msr_xss = true;
1453 break;
1454 case HV_X64_MSR_CRASH_CTL:
1455 has_msr_hv_crash = true;
1456 break;
1457 case HV_X64_MSR_RESET:
1458 has_msr_hv_reset = true;
1459 break;
1460 case HV_X64_MSR_VP_INDEX:
1461 has_msr_hv_vpindex = true;
1462 break;
1463 case HV_X64_MSR_VP_RUNTIME:
1464 has_msr_hv_runtime = true;
1465 break;
1466 case HV_X64_MSR_SCONTROL:
1467 has_msr_hv_synic = true;
1468 break;
1469 case HV_X64_MSR_STIMER0_CONFIG:
1470 has_msr_hv_stimer = true;
1471 break;
1472 case HV_X64_MSR_TSC_FREQUENCY:
1473 has_msr_hv_frequencies = true;
1474 break;
1475 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1476 has_msr_hv_reenlightenment = true;
1477 break;
1478 case MSR_IA32_SPEC_CTRL:
1479 has_msr_spec_ctrl = true;
1480 break;
1481 case MSR_VIRT_SSBD:
1482 has_msr_virt_ssbd = true;
1483 break;
1484 }
1485 }
1486 }
1487
1488 g_free(kvm_msr_list);
1489 }
1490
1491 return ret;
1492 }
1493
1494 static Notifier smram_machine_done;
1495 static KVMMemoryListener smram_listener;
1496 static AddressSpace smram_address_space;
1497 static MemoryRegion smram_as_root;
1498 static MemoryRegion smram_as_mem;
1499
1500 static void register_smram_listener(Notifier *n, void *unused)
1501 {
1502 MemoryRegion *smram =
1503 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1504
1505 /* Outer container... */
1506 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1507 memory_region_set_enabled(&smram_as_root, true);
1508
1509 /* ... with two regions inside: normal system memory with low
1510 * priority, and...
1511 */
1512 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1513 get_system_memory(), 0, ~0ull);
1514 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1515 memory_region_set_enabled(&smram_as_mem, true);
1516
1517 if (smram) {
1518 /* ... SMRAM with higher priority */
1519 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1520 memory_region_set_enabled(smram, true);
1521 }
1522
1523 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1524 kvm_memory_listener_register(kvm_state, &smram_listener,
1525 &smram_address_space, 1);
1526 }
1527
1528 int kvm_arch_init(MachineState *ms, KVMState *s)
1529 {
1530 uint64_t identity_base = 0xfffbc000;
1531 uint64_t shadow_mem;
1532 int ret;
1533 struct utsname utsname;
1534
1535 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1536 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1537 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1538
1539 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1540
1541 ret = kvm_get_supported_msrs(s);
1542 if (ret < 0) {
1543 return ret;
1544 }
1545
1546 kvm_get_supported_feature_msrs(s);
1547
1548 uname(&utsname);
1549 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1550
1551 /*
1552 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1553 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1554 * Since these must be part of guest physical memory, we need to allocate
1555 * them, both by setting their start addresses in the kernel and by
1556 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1557 *
1558 * Older KVM versions may not support setting the identity map base. In
1559 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1560 * size.
1561 */
1562 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1563 /* Allows up to 16M BIOSes. */
1564 identity_base = 0xfeffc000;
1565
1566 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1567 if (ret < 0) {
1568 return ret;
1569 }
1570 }
1571
1572 /* Set TSS base one page after EPT identity map. */
1573 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1574 if (ret < 0) {
1575 return ret;
1576 }
1577
1578 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1579 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1580 if (ret < 0) {
1581 fprintf(stderr, "e820_add_entry() table is full\n");
1582 return ret;
1583 }
1584 qemu_register_reset(kvm_unpoison_all, NULL);
1585
1586 shadow_mem = machine_kvm_shadow_mem(ms);
1587 if (shadow_mem != -1) {
1588 shadow_mem /= 4096;
1589 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1590 if (ret < 0) {
1591 return ret;
1592 }
1593 }
1594
1595 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1596 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1597 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1598 smram_machine_done.notify = register_smram_listener;
1599 qemu_add_machine_init_done_notifier(&smram_machine_done);
1600 }
1601
1602 if (enable_cpu_pm) {
1603 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1604 int ret;
1605
1606 /* Work around for kernel header with a typo. TODO: fix header and drop. */
1607 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1608 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1609 #endif
1610 if (disable_exits) {
1611 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1612 KVM_X86_DISABLE_EXITS_HLT |
1613 KVM_X86_DISABLE_EXITS_PAUSE);
1614 }
1615
1616 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1617 disable_exits);
1618 if (ret < 0) {
1619 error_report("kvm: guest stopping CPU not supported: %s",
1620 strerror(-ret));
1621 }
1622 }
1623
1624 return 0;
1625 }
1626
1627 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1628 {
1629 lhs->selector = rhs->selector;
1630 lhs->base = rhs->base;
1631 lhs->limit = rhs->limit;
1632 lhs->type = 3;
1633 lhs->present = 1;
1634 lhs->dpl = 3;
1635 lhs->db = 0;
1636 lhs->s = 1;
1637 lhs->l = 0;
1638 lhs->g = 0;
1639 lhs->avl = 0;
1640 lhs->unusable = 0;
1641 }
1642
1643 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1644 {
1645 unsigned flags = rhs->flags;
1646 lhs->selector = rhs->selector;
1647 lhs->base = rhs->base;
1648 lhs->limit = rhs->limit;
1649 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1650 lhs->present = (flags & DESC_P_MASK) != 0;
1651 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1652 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1653 lhs->s = (flags & DESC_S_MASK) != 0;
1654 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1655 lhs->g = (flags & DESC_G_MASK) != 0;
1656 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1657 lhs->unusable = !lhs->present;
1658 lhs->padding = 0;
1659 }
1660
1661 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1662 {
1663 lhs->selector = rhs->selector;
1664 lhs->base = rhs->base;
1665 lhs->limit = rhs->limit;
1666 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1667 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1668 (rhs->dpl << DESC_DPL_SHIFT) |
1669 (rhs->db << DESC_B_SHIFT) |
1670 (rhs->s * DESC_S_MASK) |
1671 (rhs->l << DESC_L_SHIFT) |
1672 (rhs->g * DESC_G_MASK) |
1673 (rhs->avl * DESC_AVL_MASK);
1674 }
1675
1676 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1677 {
1678 if (set) {
1679 *kvm_reg = *qemu_reg;
1680 } else {
1681 *qemu_reg = *kvm_reg;
1682 }
1683 }
1684
1685 static int kvm_getput_regs(X86CPU *cpu, int set)
1686 {
1687 CPUX86State *env = &cpu->env;
1688 struct kvm_regs regs;
1689 int ret = 0;
1690
1691 if (!set) {
1692 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1693 if (ret < 0) {
1694 return ret;
1695 }
1696 }
1697
1698 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1699 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1700 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1701 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1702 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1703 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1704 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1705 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1706 #ifdef TARGET_X86_64
1707 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1708 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1709 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1710 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1711 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1712 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1713 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1714 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1715 #endif
1716
1717 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1718 kvm_getput_reg(&regs.rip, &env->eip, set);
1719
1720 if (set) {
1721 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1722 }
1723
1724 return ret;
1725 }
1726
1727 static int kvm_put_fpu(X86CPU *cpu)
1728 {
1729 CPUX86State *env = &cpu->env;
1730 struct kvm_fpu fpu;
1731 int i;
1732
1733 memset(&fpu, 0, sizeof fpu);
1734 fpu.fsw = env->fpus & ~(7 << 11);
1735 fpu.fsw |= (env->fpstt & 7) << 11;
1736 fpu.fcw = env->fpuc;
1737 fpu.last_opcode = env->fpop;
1738 fpu.last_ip = env->fpip;
1739 fpu.last_dp = env->fpdp;
1740 for (i = 0; i < 8; ++i) {
1741 fpu.ftwx |= (!env->fptags[i]) << i;
1742 }
1743 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1744 for (i = 0; i < CPU_NB_REGS; i++) {
1745 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1746 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1747 }
1748 fpu.mxcsr = env->mxcsr;
1749
1750 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1751 }
1752
1753 #define XSAVE_FCW_FSW 0
1754 #define XSAVE_FTW_FOP 1
1755 #define XSAVE_CWD_RIP 2
1756 #define XSAVE_CWD_RDP 4
1757 #define XSAVE_MXCSR 6
1758 #define XSAVE_ST_SPACE 8
1759 #define XSAVE_XMM_SPACE 40
1760 #define XSAVE_XSTATE_BV 128
1761 #define XSAVE_YMMH_SPACE 144
1762 #define XSAVE_BNDREGS 240
1763 #define XSAVE_BNDCSR 256
1764 #define XSAVE_OPMASK 272
1765 #define XSAVE_ZMM_Hi256 288
1766 #define XSAVE_Hi16_ZMM 416
1767 #define XSAVE_PKRU 672
1768
1769 #define XSAVE_BYTE_OFFSET(word_offset) \
1770 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
1771
1772 #define ASSERT_OFFSET(word_offset, field) \
1773 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1774 offsetof(X86XSaveArea, field))
1775
1776 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1777 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1778 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1779 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1780 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1781 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1782 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1783 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1784 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1785 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1786 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1787 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1788 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1789 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1790 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1791
1792 static int kvm_put_xsave(X86CPU *cpu)
1793 {
1794 CPUX86State *env = &cpu->env;
1795 X86XSaveArea *xsave = env->xsave_buf;
1796
1797 if (!has_xsave) {
1798 return kvm_put_fpu(cpu);
1799 }
1800 x86_cpu_xsave_all_areas(cpu, xsave);
1801
1802 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1803 }
1804
1805 static int kvm_put_xcrs(X86CPU *cpu)
1806 {
1807 CPUX86State *env = &cpu->env;
1808 struct kvm_xcrs xcrs = {};
1809
1810 if (!has_xcrs) {
1811 return 0;
1812 }
1813
1814 xcrs.nr_xcrs = 1;
1815 xcrs.flags = 0;
1816 xcrs.xcrs[0].xcr = 0;
1817 xcrs.xcrs[0].value = env->xcr0;
1818 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1819 }
1820
1821 static int kvm_put_sregs(X86CPU *cpu)
1822 {
1823 CPUX86State *env = &cpu->env;
1824 struct kvm_sregs sregs;
1825
1826 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1827 if (env->interrupt_injected >= 0) {
1828 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1829 (uint64_t)1 << (env->interrupt_injected % 64);
1830 }
1831
1832 if ((env->eflags & VM_MASK)) {
1833 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1834 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1835 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1836 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1837 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1838 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1839 } else {
1840 set_seg(&sregs.cs, &env->segs[R_CS]);
1841 set_seg(&sregs.ds, &env->segs[R_DS]);
1842 set_seg(&sregs.es, &env->segs[R_ES]);
1843 set_seg(&sregs.fs, &env->segs[R_FS]);
1844 set_seg(&sregs.gs, &env->segs[R_GS]);
1845 set_seg(&sregs.ss, &env->segs[R_SS]);
1846 }
1847
1848 set_seg(&sregs.tr, &env->tr);
1849 set_seg(&sregs.ldt, &env->ldt);
1850
1851 sregs.idt.limit = env->idt.limit;
1852 sregs.idt.base = env->idt.base;
1853 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1854 sregs.gdt.limit = env->gdt.limit;
1855 sregs.gdt.base = env->gdt.base;
1856 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1857
1858 sregs.cr0 = env->cr[0];
1859 sregs.cr2 = env->cr[2];
1860 sregs.cr3 = env->cr[3];
1861 sregs.cr4 = env->cr[4];
1862
1863 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1864 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1865
1866 sregs.efer = env->efer;
1867
1868 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1869 }
1870
1871 static void kvm_msr_buf_reset(X86CPU *cpu)
1872 {
1873 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1874 }
1875
1876 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1877 {
1878 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1879 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1880 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1881
1882 assert((void *)(entry + 1) <= limit);
1883
1884 entry->index = index;
1885 entry->reserved = 0;
1886 entry->data = value;
1887 msrs->nmsrs++;
1888 }
1889
1890 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1891 {
1892 kvm_msr_buf_reset(cpu);
1893 kvm_msr_entry_add(cpu, index, value);
1894
1895 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1896 }
1897
1898 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1899 {
1900 int ret;
1901
1902 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1903 assert(ret == 1);
1904 }
1905
1906 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1907 {
1908 CPUX86State *env = &cpu->env;
1909 int ret;
1910
1911 if (!has_msr_tsc_deadline) {
1912 return 0;
1913 }
1914
1915 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1916 if (ret < 0) {
1917 return ret;
1918 }
1919
1920 assert(ret == 1);
1921 return 0;
1922 }
1923
1924 /*
1925 * Provide a separate write service for the feature control MSR in order to
1926 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1927 * before writing any other state because forcibly leaving nested mode
1928 * invalidates the VCPU state.
1929 */
1930 static int kvm_put_msr_feature_control(X86CPU *cpu)
1931 {
1932 int ret;
1933
1934 if (!has_msr_feature_control) {
1935 return 0;
1936 }
1937
1938 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1939 cpu->env.msr_ia32_feature_control);
1940 if (ret < 0) {
1941 return ret;
1942 }
1943
1944 assert(ret == 1);
1945 return 0;
1946 }
1947
1948 static int kvm_put_msrs(X86CPU *cpu, int level)
1949 {
1950 CPUX86State *env = &cpu->env;
1951 int i;
1952 int ret;
1953
1954 kvm_msr_buf_reset(cpu);
1955
1956 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1957 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1958 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1959 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1960 if (has_msr_star) {
1961 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1962 }
1963 if (has_msr_hsave_pa) {
1964 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1965 }
1966 if (has_msr_tsc_aux) {
1967 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1968 }
1969 if (has_msr_tsc_adjust) {
1970 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1971 }
1972 if (has_msr_misc_enable) {
1973 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1974 env->msr_ia32_misc_enable);
1975 }
1976 if (has_msr_smbase) {
1977 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1978 }
1979 if (has_msr_smi_count) {
1980 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
1981 }
1982 if (has_msr_bndcfgs) {
1983 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1984 }
1985 if (has_msr_xss) {
1986 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1987 }
1988 if (has_msr_spec_ctrl) {
1989 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1990 }
1991 if (has_msr_virt_ssbd) {
1992 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
1993 }
1994
1995 #ifdef TARGET_X86_64
1996 if (lm_capable_kernel) {
1997 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1998 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1999 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2000 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
2001 }
2002 #endif
2003
2004 /* If host supports feature MSR, write down. */
2005 if (kvm_feature_msrs) {
2006 int i;
2007 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
2008 if (kvm_feature_msrs->indices[i] == MSR_IA32_ARCH_CAPABILITIES) {
2009 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2010 env->features[FEAT_ARCH_CAPABILITIES]);
2011 break;
2012 }
2013 }
2014
2015 /*
2016 * The following MSRs have side effects on the guest or are too heavy
2017 * for normal writeback. Limit them to reset or full state updates.
2018 */
2019 if (level >= KVM_PUT_RESET_STATE) {
2020 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2021 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2022 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
2023 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2024 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
2025 }
2026 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2027 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
2028 }
2029 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2030 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
2031 }
2032 if (has_architectural_pmu_version > 0) {
2033 if (has_architectural_pmu_version > 1) {
2034 /* Stop the counter. */
2035 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2036 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2037 }
2038
2039 /* Set the counter values. */
2040 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2041 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
2042 env->msr_fixed_counters[i]);
2043 }
2044 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2045 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
2046 env->msr_gp_counters[i]);
2047 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
2048 env->msr_gp_evtsel[i]);
2049 }
2050 if (has_architectural_pmu_version > 1) {
2051 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2052 env->msr_global_status);
2053 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2054 env->msr_global_ovf_ctrl);
2055
2056 /* Now start the PMU. */
2057 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2058 env->msr_fixed_ctr_ctrl);
2059 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2060 env->msr_global_ctrl);
2061 }
2062 }
2063 /*
2064 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2065 * only sync them to KVM on the first cpu
2066 */
2067 if (current_cpu == first_cpu) {
2068 if (has_msr_hv_hypercall) {
2069 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2070 env->msr_hv_guest_os_id);
2071 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2072 env->msr_hv_hypercall);
2073 }
2074 if (cpu->hyperv_time) {
2075 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2076 env->msr_hv_tsc);
2077 }
2078 if (cpu->hyperv_reenlightenment) {
2079 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2080 env->msr_hv_reenlightenment_control);
2081 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2082 env->msr_hv_tsc_emulation_control);
2083 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2084 env->msr_hv_tsc_emulation_status);
2085 }
2086 }
2087 if (cpu->hyperv_vapic) {
2088 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
2089 env->msr_hv_vapic);
2090 }
2091 if (has_msr_hv_crash) {
2092 int j;
2093
2094 for (j = 0; j < HV_CRASH_PARAMS; j++)
2095 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
2096 env->msr_hv_crash_params[j]);
2097
2098 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
2099 }
2100 if (has_msr_hv_runtime) {
2101 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
2102 }
2103 if (cpu->hyperv_vpindex && hv_vpindex_settable) {
2104 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2105 hyperv_vp_index(CPU(cpu)));
2106 }
2107 if (cpu->hyperv_synic) {
2108 int j;
2109
2110 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2111
2112 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
2113 env->msr_hv_synic_control);
2114 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
2115 env->msr_hv_synic_evt_page);
2116 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
2117 env->msr_hv_synic_msg_page);
2118
2119 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
2120 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
2121 env->msr_hv_synic_sint[j]);
2122 }
2123 }
2124 if (has_msr_hv_stimer) {
2125 int j;
2126
2127 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
2128 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
2129 env->msr_hv_stimer_config[j]);
2130 }
2131
2132 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
2133 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
2134 env->msr_hv_stimer_count[j]);
2135 }
2136 }
2137 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2138 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2139
2140 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2141 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2142 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2143 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2144 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2145 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2146 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2147 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2148 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2149 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2150 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2151 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
2152 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2153 /* The CPU GPs if we write to a bit above the physical limit of
2154 * the host CPU (and KVM emulates that)
2155 */
2156 uint64_t mask = env->mtrr_var[i].mask;
2157 mask &= phys_mask;
2158
2159 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2160 env->mtrr_var[i].base);
2161 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
2162 }
2163 }
2164 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2165 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2166 0x14, 1, R_EAX) & 0x7;
2167
2168 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2169 env->msr_rtit_ctrl);
2170 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2171 env->msr_rtit_status);
2172 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2173 env->msr_rtit_output_base);
2174 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2175 env->msr_rtit_output_mask);
2176 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2177 env->msr_rtit_cr3_match);
2178 for (i = 0; i < addr_num; i++) {
2179 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2180 env->msr_rtit_addrs[i]);
2181 }
2182 }
2183
2184 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2185 * kvm_put_msr_feature_control. */
2186 }
2187 if (env->mcg_cap) {
2188 int i;
2189
2190 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2191 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
2192 if (has_msr_mcg_ext_ctl) {
2193 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2194 }
2195 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2196 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
2197 }
2198 }
2199
2200 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2201 if (ret < 0) {
2202 return ret;
2203 }
2204
2205 if (ret < cpu->kvm_msr_buf->nmsrs) {
2206 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2207 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2208 (uint32_t)e->index, (uint64_t)e->data);
2209 }
2210
2211 assert(ret == cpu->kvm_msr_buf->nmsrs);
2212 return 0;
2213 }
2214
2215
2216 static int kvm_get_fpu(X86CPU *cpu)
2217 {
2218 CPUX86State *env = &cpu->env;
2219 struct kvm_fpu fpu;
2220 int i, ret;
2221
2222 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
2223 if (ret < 0) {
2224 return ret;
2225 }
2226
2227 env->fpstt = (fpu.fsw >> 11) & 7;
2228 env->fpus = fpu.fsw;
2229 env->fpuc = fpu.fcw;
2230 env->fpop = fpu.last_opcode;
2231 env->fpip = fpu.last_ip;
2232 env->fpdp = fpu.last_dp;
2233 for (i = 0; i < 8; ++i) {
2234 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2235 }
2236 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
2237 for (i = 0; i < CPU_NB_REGS; i++) {
2238 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2239 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
2240 }
2241 env->mxcsr = fpu.mxcsr;
2242
2243 return 0;
2244 }
2245
2246 static int kvm_get_xsave(X86CPU *cpu)
2247 {
2248 CPUX86State *env = &cpu->env;
2249 X86XSaveArea *xsave = env->xsave_buf;
2250 int ret;
2251
2252 if (!has_xsave) {
2253 return kvm_get_fpu(cpu);
2254 }
2255
2256 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
2257 if (ret < 0) {
2258 return ret;
2259 }
2260 x86_cpu_xrstor_all_areas(cpu, xsave);
2261
2262 return 0;
2263 }
2264
2265 static int kvm_get_xcrs(X86CPU *cpu)
2266 {
2267 CPUX86State *env = &cpu->env;
2268 int i, ret;
2269 struct kvm_xcrs xcrs;
2270
2271 if (!has_xcrs) {
2272 return 0;
2273 }
2274
2275 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
2276 if (ret < 0) {
2277 return ret;
2278 }
2279
2280 for (i = 0; i < xcrs.nr_xcrs; i++) {
2281 /* Only support xcr0 now */
2282 if (xcrs.xcrs[i].xcr == 0) {
2283 env->xcr0 = xcrs.xcrs[i].value;
2284 break;
2285 }
2286 }
2287 return 0;
2288 }
2289
2290 static int kvm_get_sregs(X86CPU *cpu)
2291 {
2292 CPUX86State *env = &cpu->env;
2293 struct kvm_sregs sregs;
2294 int bit, i, ret;
2295
2296 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
2297 if (ret < 0) {
2298 return ret;
2299 }
2300
2301 /* There can only be one pending IRQ set in the bitmap at a time, so try
2302 to find it and save its number instead (-1 for none). */
2303 env->interrupt_injected = -1;
2304 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2305 if (sregs.interrupt_bitmap[i]) {
2306 bit = ctz64(sregs.interrupt_bitmap[i]);
2307 env->interrupt_injected = i * 64 + bit;
2308 break;
2309 }
2310 }
2311
2312 get_seg(&env->segs[R_CS], &sregs.cs);
2313 get_seg(&env->segs[R_DS], &sregs.ds);
2314 get_seg(&env->segs[R_ES], &sregs.es);
2315 get_seg(&env->segs[R_FS], &sregs.fs);
2316 get_seg(&env->segs[R_GS], &sregs.gs);
2317 get_seg(&env->segs[R_SS], &sregs.ss);
2318
2319 get_seg(&env->tr, &sregs.tr);
2320 get_seg(&env->ldt, &sregs.ldt);
2321
2322 env->idt.limit = sregs.idt.limit;
2323 env->idt.base = sregs.idt.base;
2324 env->gdt.limit = sregs.gdt.limit;
2325 env->gdt.base = sregs.gdt.base;
2326
2327 env->cr[0] = sregs.cr0;
2328 env->cr[2] = sregs.cr2;
2329 env->cr[3] = sregs.cr3;
2330 env->cr[4] = sregs.cr4;
2331
2332 env->efer = sregs.efer;
2333
2334 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
2335 x86_update_hflags(env);
2336
2337 return 0;
2338 }
2339
2340 static int kvm_get_msrs(X86CPU *cpu)
2341 {
2342 CPUX86State *env = &cpu->env;
2343 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2344 int ret, i;
2345 uint64_t mtrr_top_bits;
2346
2347 kvm_msr_buf_reset(cpu);
2348
2349 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2350 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2351 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2352 kvm_msr_entry_add(cpu, MSR_PAT, 0);
2353 if (has_msr_star) {
2354 kvm_msr_entry_add(cpu, MSR_STAR, 0);
2355 }
2356 if (has_msr_hsave_pa) {
2357 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2358 }
2359 if (has_msr_tsc_aux) {
2360 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2361 }
2362 if (has_msr_tsc_adjust) {
2363 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2364 }
2365 if (has_msr_tsc_deadline) {
2366 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2367 }
2368 if (has_msr_misc_enable) {
2369 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2370 }
2371 if (has_msr_smbase) {
2372 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2373 }
2374 if (has_msr_smi_count) {
2375 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2376 }
2377 if (has_msr_feature_control) {
2378 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2379 }
2380 if (has_msr_bndcfgs) {
2381 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2382 }
2383 if (has_msr_xss) {
2384 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2385 }
2386 if (has_msr_spec_ctrl) {
2387 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2388 }
2389 if (has_msr_virt_ssbd) {
2390 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2391 }
2392 if (!env->tsc_valid) {
2393 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2394 env->tsc_valid = !runstate_is_running();
2395 }
2396
2397 #ifdef TARGET_X86_64
2398 if (lm_capable_kernel) {
2399 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2400 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2401 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2402 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2403 }
2404 #endif
2405 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2406 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2407 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2408 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2409 }
2410 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2411 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2412 }
2413 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2414 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2415 }
2416 if (has_architectural_pmu_version > 0) {
2417 if (has_architectural_pmu_version > 1) {
2418 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2419 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2420 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2421 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2422 }
2423 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2424 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2425 }
2426 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2427 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2428 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2429 }
2430 }
2431
2432 if (env->mcg_cap) {
2433 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2434 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2435 if (has_msr_mcg_ext_ctl) {
2436 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2437 }
2438 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2439 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2440 }
2441 }
2442
2443 if (has_msr_hv_hypercall) {
2444 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2445 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2446 }
2447 if (cpu->hyperv_vapic) {
2448 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2449 }
2450 if (cpu->hyperv_time) {
2451 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2452 }
2453 if (cpu->hyperv_reenlightenment) {
2454 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2455 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2456 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2457 }
2458 if (has_msr_hv_crash) {
2459 int j;
2460
2461 for (j = 0; j < HV_CRASH_PARAMS; j++) {
2462 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2463 }
2464 }
2465 if (has_msr_hv_runtime) {
2466 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2467 }
2468 if (cpu->hyperv_synic) {
2469 uint32_t msr;
2470
2471 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2472 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2473 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2474 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2475 kvm_msr_entry_add(cpu, msr, 0);
2476 }
2477 }
2478 if (has_msr_hv_stimer) {
2479 uint32_t msr;
2480
2481 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2482 msr++) {
2483 kvm_msr_entry_add(cpu, msr, 0);
2484 }
2485 }
2486 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2487 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2488 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2489 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2490 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2491 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2492 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2493 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2494 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2495 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2496 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2497 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2498 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2499 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2500 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2501 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2502 }
2503 }
2504
2505 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2506 int addr_num =
2507 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2508
2509 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2510 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2511 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2512 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2513 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2514 for (i = 0; i < addr_num; i++) {
2515 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2516 }
2517 }
2518
2519 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2520 if (ret < 0) {
2521 return ret;
2522 }
2523
2524 if (ret < cpu->kvm_msr_buf->nmsrs) {
2525 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2526 error_report("error: failed to get MSR 0x%" PRIx32,
2527 (uint32_t)e->index);
2528 }
2529
2530 assert(ret == cpu->kvm_msr_buf->nmsrs);
2531 /*
2532 * MTRR masks: Each mask consists of 5 parts
2533 * a 10..0: must be zero
2534 * b 11 : valid bit
2535 * c n-1.12: actual mask bits
2536 * d 51..n: reserved must be zero
2537 * e 63.52: reserved must be zero
2538 *
2539 * 'n' is the number of physical bits supported by the CPU and is
2540 * apparently always <= 52. We know our 'n' but don't know what
2541 * the destinations 'n' is; it might be smaller, in which case
2542 * it masks (c) on loading. It might be larger, in which case
2543 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2544 * we're migrating to.
2545 */
2546
2547 if (cpu->fill_mtrr_mask) {
2548 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2549 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2550 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2551 } else {
2552 mtrr_top_bits = 0;
2553 }
2554
2555 for (i = 0; i < ret; i++) {
2556 uint32_t index = msrs[i].index;
2557 switch (index) {
2558 case MSR_IA32_SYSENTER_CS:
2559 env->sysenter_cs = msrs[i].data;
2560 break;
2561 case MSR_IA32_SYSENTER_ESP:
2562 env->sysenter_esp = msrs[i].data;
2563 break;
2564 case MSR_IA32_SYSENTER_EIP:
2565 env->sysenter_eip = msrs[i].data;
2566 break;
2567 case MSR_PAT:
2568 env->pat = msrs[i].data;
2569 break;
2570 case MSR_STAR:
2571 env->star = msrs[i].data;
2572 break;
2573 #ifdef TARGET_X86_64
2574 case MSR_CSTAR:
2575 env->cstar = msrs[i].data;
2576 break;
2577 case MSR_KERNELGSBASE:
2578 env->kernelgsbase = msrs[i].data;
2579 break;
2580 case MSR_FMASK:
2581 env->fmask = msrs[i].data;
2582 break;
2583 case MSR_LSTAR:
2584 env->lstar = msrs[i].data;
2585 break;
2586 #endif
2587 case MSR_IA32_TSC:
2588 env->tsc = msrs[i].data;
2589 break;
2590 case MSR_TSC_AUX:
2591 env->tsc_aux = msrs[i].data;
2592 break;
2593 case MSR_TSC_ADJUST:
2594 env->tsc_adjust = msrs[i].data;
2595 break;
2596 case MSR_IA32_TSCDEADLINE:
2597 env->tsc_deadline = msrs[i].data;
2598 break;
2599 case MSR_VM_HSAVE_PA:
2600 env->vm_hsave = msrs[i].data;
2601 break;
2602 case MSR_KVM_SYSTEM_TIME:
2603 env->system_time_msr = msrs[i].data;
2604 break;
2605 case MSR_KVM_WALL_CLOCK:
2606 env->wall_clock_msr = msrs[i].data;
2607 break;
2608 case MSR_MCG_STATUS:
2609 env->mcg_status = msrs[i].data;
2610 break;
2611 case MSR_MCG_CTL:
2612 env->mcg_ctl = msrs[i].data;
2613 break;
2614 case MSR_MCG_EXT_CTL:
2615 env->mcg_ext_ctl = msrs[i].data;
2616 break;
2617 case MSR_IA32_MISC_ENABLE:
2618 env->msr_ia32_misc_enable = msrs[i].data;
2619 break;
2620 case MSR_IA32_SMBASE:
2621 env->smbase = msrs[i].data;
2622 break;
2623 case MSR_SMI_COUNT:
2624 env->msr_smi_count = msrs[i].data;
2625 break;
2626 case MSR_IA32_FEATURE_CONTROL:
2627 env->msr_ia32_feature_control = msrs[i].data;
2628 break;
2629 case MSR_IA32_BNDCFGS:
2630 env->msr_bndcfgs = msrs[i].data;
2631 break;
2632 case MSR_IA32_XSS:
2633 env->xss = msrs[i].data;
2634 break;
2635 default:
2636 if (msrs[i].index >= MSR_MC0_CTL &&
2637 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2638 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2639 }
2640 break;
2641 case MSR_KVM_ASYNC_PF_EN:
2642 env->async_pf_en_msr = msrs[i].data;
2643 break;
2644 case MSR_KVM_PV_EOI_EN:
2645 env->pv_eoi_en_msr = msrs[i].data;
2646 break;
2647 case MSR_KVM_STEAL_TIME:
2648 env->steal_time_msr = msrs[i].data;
2649 break;
2650 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2651 env->msr_fixed_ctr_ctrl = msrs[i].data;
2652 break;
2653 case MSR_CORE_PERF_GLOBAL_CTRL:
2654 env->msr_global_ctrl = msrs[i].data;
2655 break;
2656 case MSR_CORE_PERF_GLOBAL_STATUS:
2657 env->msr_global_status = msrs[i].data;
2658 break;
2659 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2660 env->msr_global_ovf_ctrl = msrs[i].data;
2661 break;
2662 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2663 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2664 break;
2665 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2666 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2667 break;
2668 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2669 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2670 break;
2671 case HV_X64_MSR_HYPERCALL:
2672 env->msr_hv_hypercall = msrs[i].data;
2673 break;
2674 case HV_X64_MSR_GUEST_OS_ID:
2675 env->msr_hv_guest_os_id = msrs[i].data;
2676 break;
2677 case HV_X64_MSR_APIC_ASSIST_PAGE:
2678 env->msr_hv_vapic = msrs[i].data;
2679 break;
2680 case HV_X64_MSR_REFERENCE_TSC:
2681 env->msr_hv_tsc = msrs[i].data;
2682 break;
2683 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2684 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2685 break;
2686 case HV_X64_MSR_VP_RUNTIME:
2687 env->msr_hv_runtime = msrs[i].data;
2688 break;
2689 case HV_X64_MSR_SCONTROL:
2690 env->msr_hv_synic_control = msrs[i].data;
2691 break;
2692 case HV_X64_MSR_SIEFP:
2693 env->msr_hv_synic_evt_page = msrs[i].data;
2694 break;
2695 case HV_X64_MSR_SIMP:
2696 env->msr_hv_synic_msg_page = msrs[i].data;
2697 break;
2698 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2699 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2700 break;
2701 case HV_X64_MSR_STIMER0_CONFIG:
2702 case HV_X64_MSR_STIMER1_CONFIG:
2703 case HV_X64_MSR_STIMER2_CONFIG:
2704 case HV_X64_MSR_STIMER3_CONFIG:
2705 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2706 msrs[i].data;
2707 break;
2708 case HV_X64_MSR_STIMER0_COUNT:
2709 case HV_X64_MSR_STIMER1_COUNT:
2710 case HV_X64_MSR_STIMER2_COUNT:
2711 case HV_X64_MSR_STIMER3_COUNT:
2712 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2713 msrs[i].data;
2714 break;
2715 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2716 env->msr_hv_reenlightenment_control = msrs[i].data;
2717 break;
2718 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2719 env->msr_hv_tsc_emulation_control = msrs[i].data;
2720 break;
2721 case HV_X64_MSR_TSC_EMULATION_STATUS:
2722 env->msr_hv_tsc_emulation_status = msrs[i].data;
2723 break;
2724 case MSR_MTRRdefType:
2725 env->mtrr_deftype = msrs[i].data;
2726 break;
2727 case MSR_MTRRfix64K_00000:
2728 env->mtrr_fixed[0] = msrs[i].data;
2729 break;
2730 case MSR_MTRRfix16K_80000:
2731 env->mtrr_fixed[1] = msrs[i].data;
2732 break;
2733 case MSR_MTRRfix16K_A0000:
2734 env->mtrr_fixed[2] = msrs[i].data;
2735 break;
2736 case MSR_MTRRfix4K_C0000:
2737 env->mtrr_fixed[3] = msrs[i].data;
2738 break;
2739 case MSR_MTRRfix4K_C8000:
2740 env->mtrr_fixed[4] = msrs[i].data;
2741 break;
2742 case MSR_MTRRfix4K_D0000:
2743 env->mtrr_fixed[5] = msrs[i].data;
2744 break;
2745 case MSR_MTRRfix4K_D8000:
2746 env->mtrr_fixed[6] = msrs[i].data;
2747 break;
2748 case MSR_MTRRfix4K_E0000:
2749 env->mtrr_fixed[7] = msrs[i].data;
2750 break;
2751 case MSR_MTRRfix4K_E8000:
2752 env->mtrr_fixed[8] = msrs[i].data;
2753 break;
2754 case MSR_MTRRfix4K_F0000:
2755 env->mtrr_fixed[9] = msrs[i].data;
2756 break;
2757 case MSR_MTRRfix4K_F8000:
2758 env->mtrr_fixed[10] = msrs[i].data;
2759 break;
2760 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2761 if (index & 1) {
2762 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2763 mtrr_top_bits;
2764 } else {
2765 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2766 }
2767 break;
2768 case MSR_IA32_SPEC_CTRL:
2769 env->spec_ctrl = msrs[i].data;
2770 break;
2771 case MSR_VIRT_SSBD:
2772 env->virt_ssbd = msrs[i].data;
2773 break;
2774 case MSR_IA32_RTIT_CTL:
2775 env->msr_rtit_ctrl = msrs[i].data;
2776 break;
2777 case MSR_IA32_RTIT_STATUS:
2778 env->msr_rtit_status = msrs[i].data;
2779 break;
2780 case MSR_IA32_RTIT_OUTPUT_BASE:
2781 env->msr_rtit_output_base = msrs[i].data;
2782 break;
2783 case MSR_IA32_RTIT_OUTPUT_MASK:
2784 env->msr_rtit_output_mask = msrs[i].data;
2785 break;
2786 case MSR_IA32_RTIT_CR3_MATCH:
2787 env->msr_rtit_cr3_match = msrs[i].data;
2788 break;
2789 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2790 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2791 break;
2792 }
2793 }
2794
2795 return 0;
2796 }
2797
2798 static int kvm_put_mp_state(X86CPU *cpu)
2799 {
2800 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2801
2802 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2803 }
2804
2805 static int kvm_get_mp_state(X86CPU *cpu)
2806 {
2807 CPUState *cs = CPU(cpu);
2808 CPUX86State *env = &cpu->env;
2809 struct kvm_mp_state mp_state;
2810 int ret;
2811
2812 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2813 if (ret < 0) {
2814 return ret;
2815 }
2816 env->mp_state = mp_state.mp_state;
2817 if (kvm_irqchip_in_kernel()) {
2818 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2819 }
2820 return 0;
2821 }
2822
2823 static int kvm_get_apic(X86CPU *cpu)
2824 {
2825 DeviceState *apic = cpu->apic_state;
2826 struct kvm_lapic_state kapic;
2827 int ret;
2828
2829 if (apic && kvm_irqchip_in_kernel()) {
2830 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2831 if (ret < 0) {
2832 return ret;
2833 }
2834
2835 kvm_get_apic_state(apic, &kapic);
2836 }
2837 return 0;
2838 }
2839
2840 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2841 {
2842 CPUState *cs = CPU(cpu);
2843 CPUX86State *env = &cpu->env;
2844 struct kvm_vcpu_events events = {};
2845
2846 if (!kvm_has_vcpu_events()) {
2847 return 0;
2848 }
2849
2850 events.exception.injected = (env->exception_injected >= 0);
2851 events.exception.nr = env->exception_injected;
2852 events.exception.has_error_code = env->has_error_code;
2853 events.exception.error_code = env->error_code;
2854
2855 events.interrupt.injected = (env->interrupt_injected >= 0);
2856 events.interrupt.nr = env->interrupt_injected;
2857 events.interrupt.soft = env->soft_interrupt;
2858
2859 events.nmi.injected = env->nmi_injected;
2860 events.nmi.pending = env->nmi_pending;
2861 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2862
2863 events.sipi_vector = env->sipi_vector;
2864 events.flags = 0;
2865
2866 if (has_msr_smbase) {
2867 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2868 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2869 if (kvm_irqchip_in_kernel()) {
2870 /* As soon as these are moved to the kernel, remove them
2871 * from cs->interrupt_request.
2872 */
2873 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2874 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2875 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2876 } else {
2877 /* Keep these in cs->interrupt_request. */
2878 events.smi.pending = 0;
2879 events.smi.latched_init = 0;
2880 }
2881 /* Stop SMI delivery on old machine types to avoid a reboot
2882 * on an inward migration of an old VM.
2883 */
2884 if (!cpu->kvm_no_smi_migration) {
2885 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2886 }
2887 }
2888
2889 if (level >= KVM_PUT_RESET_STATE) {
2890 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2891 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2892 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2893 }
2894 }
2895
2896 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2897 }
2898
2899 static int kvm_get_vcpu_events(X86CPU *cpu)
2900 {
2901 CPUX86State *env = &cpu->env;
2902 struct kvm_vcpu_events events;
2903 int ret;
2904
2905 if (!kvm_has_vcpu_events()) {
2906 return 0;
2907 }
2908
2909 memset(&events, 0, sizeof(events));
2910 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2911 if (ret < 0) {
2912 return ret;
2913 }
2914 env->exception_injected =
2915 events.exception.injected ? events.exception.nr : -1;
2916 env->has_error_code = events.exception.has_error_code;
2917 env->error_code = events.exception.error_code;
2918
2919 env->interrupt_injected =
2920 events.interrupt.injected ? events.interrupt.nr : -1;
2921 env->soft_interrupt = events.interrupt.soft;
2922
2923 env->nmi_injected = events.nmi.injected;
2924 env->nmi_pending = events.nmi.pending;
2925 if (events.nmi.masked) {
2926 env->hflags2 |= HF2_NMI_MASK;
2927 } else {
2928 env->hflags2 &= ~HF2_NMI_MASK;
2929 }
2930
2931 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2932 if (events.smi.smm) {
2933 env->hflags |= HF_SMM_MASK;
2934 } else {
2935 env->hflags &= ~HF_SMM_MASK;
2936 }
2937 if (events.smi.pending) {
2938 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2939 } else {
2940 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2941 }
2942 if (events.smi.smm_inside_nmi) {
2943 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2944 } else {
2945 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2946 }
2947 if (events.smi.latched_init) {
2948 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2949 } else {
2950 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2951 }
2952 }
2953
2954 env->sipi_vector = events.sipi_vector;
2955
2956 return 0;
2957 }
2958
2959 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2960 {
2961 CPUState *cs = CPU(cpu);
2962 CPUX86State *env = &cpu->env;
2963 int ret = 0;
2964 unsigned long reinject_trap = 0;
2965
2966 if (!kvm_has_vcpu_events()) {
2967 if (env->exception_injected == 1) {
2968 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2969 } else if (env->exception_injected == 3) {
2970 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2971 }
2972 env->exception_injected = -1;
2973 }
2974
2975 /*
2976 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2977 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2978 * by updating the debug state once again if single-stepping is on.
2979 * Another reason to call kvm_update_guest_debug here is a pending debug
2980 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2981 * reinject them via SET_GUEST_DEBUG.
2982 */
2983 if (reinject_trap ||
2984 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2985 ret = kvm_update_guest_debug(cs, reinject_trap);
2986 }
2987 return ret;
2988 }
2989
2990 static int kvm_put_debugregs(X86CPU *cpu)
2991 {
2992 CPUX86State *env = &cpu->env;
2993 struct kvm_debugregs dbgregs;
2994 int i;
2995
2996 if (!kvm_has_debugregs()) {
2997 return 0;
2998 }
2999
3000 for (i = 0; i < 4; i++) {
3001 dbgregs.db[i] = env->dr[i];
3002 }
3003 dbgregs.dr6 = env->dr[6];
3004 dbgregs.dr7 = env->dr[7];
3005 dbgregs.flags = 0;
3006
3007 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
3008 }
3009
3010 static int kvm_get_debugregs(X86CPU *cpu)
3011 {
3012 CPUX86State *env = &cpu->env;
3013 struct kvm_debugregs dbgregs;
3014 int i, ret;
3015
3016 if (!kvm_has_debugregs()) {
3017 return 0;
3018 }
3019
3020 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
3021 if (ret < 0) {
3022 return ret;
3023 }
3024 for (i = 0; i < 4; i++) {
3025 env->dr[i] = dbgregs.db[i];
3026 }
3027 env->dr[4] = env->dr[6] = dbgregs.dr6;
3028 env->dr[5] = env->dr[7] = dbgregs.dr7;
3029
3030 return 0;
3031 }
3032
3033 int kvm_arch_put_registers(CPUState *cpu, int level)
3034 {
3035 X86CPU *x86_cpu = X86_CPU(cpu);
3036 int ret;
3037
3038 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
3039
3040 if (level >= KVM_PUT_RESET_STATE) {
3041 ret = kvm_put_msr_feature_control(x86_cpu);
3042 if (ret < 0) {
3043 return ret;
3044 }
3045 }
3046
3047 if (level == KVM_PUT_FULL_STATE) {
3048 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3049 * because TSC frequency mismatch shouldn't abort migration,
3050 * unless the user explicitly asked for a more strict TSC
3051 * setting (e.g. using an explicit "tsc-freq" option).
3052 */
3053 kvm_arch_set_tsc_khz(cpu);
3054 }
3055
3056 ret = kvm_getput_regs(x86_cpu, 1);
3057 if (ret < 0) {
3058 return ret;
3059 }
3060 ret = kvm_put_xsave(x86_cpu);
3061 if (ret < 0) {
3062 return ret;
3063 }
3064 ret = kvm_put_xcrs(x86_cpu);
3065 if (ret < 0) {
3066 return ret;
3067 }
3068 ret = kvm_put_sregs(x86_cpu);
3069 if (ret < 0) {
3070 return ret;
3071 }
3072 /* must be before kvm_put_msrs */
3073 ret = kvm_inject_mce_oldstyle(x86_cpu);
3074 if (ret < 0) {
3075 return ret;
3076 }
3077 ret = kvm_put_msrs(x86_cpu, level);
3078 if (ret < 0) {
3079 return ret;
3080 }
3081 ret = kvm_put_vcpu_events(x86_cpu, level);
3082 if (ret < 0) {
3083 return ret;
3084 }
3085 if (level >= KVM_PUT_RESET_STATE) {
3086 ret = kvm_put_mp_state(x86_cpu);
3087 if (ret < 0) {
3088 return ret;
3089 }
3090 }
3091
3092 ret = kvm_put_tscdeadline_msr(x86_cpu);
3093 if (ret < 0) {
3094 return ret;
3095 }
3096 ret = kvm_put_debugregs(x86_cpu);
3097 if (ret < 0) {
3098 return ret;
3099 }
3100 /* must be last */
3101 ret = kvm_guest_debug_workarounds(x86_cpu);
3102 if (ret < 0) {
3103 return ret;
3104 }
3105 return 0;
3106 }
3107
3108 int kvm_arch_get_registers(CPUState *cs)
3109 {
3110 X86CPU *cpu = X86_CPU(cs);
3111 int ret;
3112
3113 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
3114
3115 ret = kvm_get_vcpu_events(cpu);
3116 if (ret < 0) {
3117 goto out;
3118 }
3119 /*
3120 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3121 * KVM_GET_REGS and KVM_GET_SREGS.
3122 */
3123 ret = kvm_get_mp_state(cpu);
3124 if (ret < 0) {
3125 goto out;
3126 }
3127 ret = kvm_getput_regs(cpu, 0);
3128 if (ret < 0) {
3129 goto out;
3130 }
3131 ret = kvm_get_xsave(cpu);
3132 if (ret < 0) {
3133 goto out;
3134 }
3135 ret = kvm_get_xcrs(cpu);
3136 if (ret < 0) {
3137 goto out;
3138 }
3139 ret = kvm_get_sregs(cpu);
3140 if (ret < 0) {
3141 goto out;
3142 }
3143 ret = kvm_get_msrs(cpu);
3144 if (ret < 0) {
3145 goto out;
3146 }
3147 ret = kvm_get_apic(cpu);
3148 if (ret < 0) {
3149 goto out;
3150 }
3151 ret = kvm_get_debugregs(cpu);
3152 if (ret < 0) {
3153 goto out;
3154 }
3155 ret = 0;
3156 out:
3157 cpu_sync_bndcs_hflags(&cpu->env);
3158 return ret;
3159 }
3160
3161 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
3162 {
3163 X86CPU *x86_cpu = X86_CPU(cpu);
3164 CPUX86State *env = &x86_cpu->env;
3165 int ret;
3166
3167 /* Inject NMI */
3168 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3169 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3170 qemu_mutex_lock_iothread();
3171 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3172 qemu_mutex_unlock_iothread();
3173 DPRINTF("injected NMI\n");
3174 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3175 if (ret < 0) {
3176 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3177 strerror(-ret));
3178 }
3179 }
3180 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3181 qemu_mutex_lock_iothread();
3182 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3183 qemu_mutex_unlock_iothread();
3184 DPRINTF("injected SMI\n");
3185 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3186 if (ret < 0) {
3187 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3188 strerror(-ret));
3189 }
3190 }
3191 }
3192
3193 if (!kvm_pic_in_kernel()) {
3194 qemu_mutex_lock_iothread();
3195 }
3196
3197 /* Force the VCPU out of its inner loop to process any INIT requests
3198 * or (for userspace APIC, but it is cheap to combine the checks here)
3199 * pending TPR access reports.
3200 */
3201 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
3202 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3203 !(env->hflags & HF_SMM_MASK)) {
3204 cpu->exit_request = 1;
3205 }
3206 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3207 cpu->exit_request = 1;
3208 }
3209 }
3210
3211 if (!kvm_pic_in_kernel()) {
3212 /* Try to inject an interrupt if the guest can accept it */
3213 if (run->ready_for_interrupt_injection &&
3214 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
3215 (env->eflags & IF_MASK)) {
3216 int irq;
3217
3218 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
3219 irq = cpu_get_pic_interrupt(env);
3220 if (irq >= 0) {
3221 struct kvm_interrupt intr;
3222
3223 intr.irq = irq;
3224 DPRINTF("injected interrupt %d\n", irq);
3225 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
3226 if (ret < 0) {
3227 fprintf(stderr,
3228 "KVM: injection failed, interrupt lost (%s)\n",
3229 strerror(-ret));
3230 }
3231 }
3232 }
3233
3234 /* If we have an interrupt but the guest is not ready to receive an
3235 * interrupt, request an interrupt window exit. This will
3236 * cause a return to userspace as soon as the guest is ready to
3237 * receive interrupts. */
3238 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
3239 run->request_interrupt_window = 1;
3240 } else {
3241 run->request_interrupt_window = 0;
3242 }
3243
3244 DPRINTF("setting tpr\n");
3245 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
3246
3247 qemu_mutex_unlock_iothread();
3248 }
3249 }
3250
3251 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
3252 {
3253 X86CPU *x86_cpu = X86_CPU(cpu);
3254 CPUX86State *env = &x86_cpu->env;
3255
3256 if (run->flags & KVM_RUN_X86_SMM) {
3257 env->hflags |= HF_SMM_MASK;
3258 } else {
3259 env->hflags &= ~HF_SMM_MASK;
3260 }
3261 if (run->if_flag) {
3262 env->eflags |= IF_MASK;
3263 } else {
3264 env->eflags &= ~IF_MASK;
3265 }
3266
3267 /* We need to protect the apic state against concurrent accesses from
3268 * different threads in case the userspace irqchip is used. */
3269 if (!kvm_irqchip_in_kernel()) {
3270 qemu_mutex_lock_iothread();
3271 }
3272 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3273 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
3274 if (!kvm_irqchip_in_kernel()) {
3275 qemu_mutex_unlock_iothread();
3276 }
3277 return cpu_get_mem_attrs(env);
3278 }
3279
3280 int kvm_arch_process_async_events(CPUState *cs)
3281 {
3282 X86CPU *cpu = X86_CPU(cs);
3283 CPUX86State *env = &cpu->env;
3284
3285 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
3286 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3287 assert(env->mcg_cap);
3288
3289 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
3290
3291 kvm_cpu_synchronize_state(cs);
3292
3293 if (env->exception_injected == EXCP08_DBLE) {
3294 /* this means triple fault */
3295 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
3296 cs->exit_request = 1;
3297 return 0;
3298 }
3299 env->exception_injected = EXCP12_MCHK;
3300 env->has_error_code = 0;
3301
3302 cs->halted = 0;
3303 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3304 env->mp_state = KVM_MP_STATE_RUNNABLE;
3305 }
3306 }
3307
3308 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3309 !(env->hflags & HF_SMM_MASK)) {
3310 kvm_cpu_synchronize_state(cs);
3311 do_cpu_init(cpu);
3312 }
3313
3314 if (kvm_irqchip_in_kernel()) {
3315 return 0;
3316 }
3317
3318 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3319 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
3320 apic_poll_irq(cpu->apic_state);
3321 }
3322 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3323 (env->eflags & IF_MASK)) ||
3324 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3325 cs->halted = 0;
3326 }
3327 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
3328 kvm_cpu_synchronize_state(cs);
3329 do_cpu_sipi(cpu);
3330 }
3331 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3332 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
3333 kvm_cpu_synchronize_state(cs);
3334 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
3335 env->tpr_access_type);
3336 }
3337
3338 return cs->halted;
3339 }
3340
3341 static int kvm_handle_halt(X86CPU *cpu)
3342 {
3343 CPUState *cs = CPU(cpu);
3344 CPUX86State *env = &cpu->env;
3345
3346 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3347 (env->eflags & IF_MASK)) &&
3348 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3349 cs->halted = 1;
3350 return EXCP_HLT;
3351 }
3352
3353 return 0;
3354 }
3355
3356 static int kvm_handle_tpr_access(X86CPU *cpu)
3357 {
3358 CPUState *cs = CPU(cpu);
3359 struct kvm_run *run = cs->kvm_run;
3360
3361 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
3362 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3363 : TPR_ACCESS_READ);
3364 return 1;
3365 }
3366
3367 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3368 {
3369 static const uint8_t int3 = 0xcc;
3370
3371 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3372 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
3373 return -EINVAL;
3374 }
3375 return 0;
3376 }
3377
3378 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3379 {
3380 uint8_t int3;
3381
3382 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3383 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
3384 return -EINVAL;
3385 }
3386 return 0;
3387 }
3388
3389 static struct {
3390 target_ulong addr;
3391 int len;
3392 int type;
3393 } hw_breakpoint[4];
3394
3395 static int nb_hw_breakpoint;
3396
3397 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3398 {
3399 int n;
3400
3401 for (n = 0; n < nb_hw_breakpoint; n++) {
3402 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3403 (hw_breakpoint[n].len == len || len == -1)) {
3404 return n;
3405 }
3406 }
3407 return -1;
3408 }
3409
3410 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3411 target_ulong len, int type)
3412 {
3413 switch (type) {
3414 case GDB_BREAKPOINT_HW:
3415 len = 1;
3416 break;
3417 case GDB_WATCHPOINT_WRITE:
3418 case GDB_WATCHPOINT_ACCESS:
3419 switch (len) {
3420 case 1:
3421 break;
3422 case 2:
3423 case 4:
3424 case 8:
3425 if (addr & (len - 1)) {
3426 return -EINVAL;
3427 }
3428 break;
3429 default:
3430 return -EINVAL;
3431 }
3432 break;
3433 default:
3434 return -ENOSYS;
3435 }
3436
3437 if (nb_hw_breakpoint == 4) {
3438 return -ENOBUFS;
3439 }
3440 if (find_hw_breakpoint(addr, len, type) >= 0) {
3441 return -EEXIST;
3442 }
3443 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3444 hw_breakpoint[nb_hw_breakpoint].len = len;
3445 hw_breakpoint[nb_hw_breakpoint].type = type;
3446 nb_hw_breakpoint++;
3447
3448 return 0;
3449 }
3450
3451 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3452 target_ulong len, int type)
3453 {
3454 int n;
3455
3456 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3457 if (n < 0) {
3458 return -ENOENT;
3459 }
3460 nb_hw_breakpoint--;
3461 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3462
3463 return 0;
3464 }
3465
3466 void kvm_arch_remove_all_hw_breakpoints(void)
3467 {
3468 nb_hw_breakpoint = 0;
3469 }
3470
3471 static CPUWatchpoint hw_watchpoint;
3472
3473 static int kvm_handle_debug(X86CPU *cpu,
3474 struct kvm_debug_exit_arch *arch_info)
3475 {
3476 CPUState *cs = CPU(cpu);
3477 CPUX86State *env = &cpu->env;
3478 int ret = 0;
3479 int n;
3480
3481 if (arch_info->exception == 1) {
3482 if (arch_info->dr6 & (1 << 14)) {
3483 if (cs->singlestep_enabled) {
3484 ret = EXCP_DEBUG;
3485 }
3486 } else {
3487 for (n = 0; n < 4; n++) {
3488 if (arch_info->dr6 & (1 << n)) {
3489 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3490 case 0x0:
3491 ret = EXCP_DEBUG;
3492 break;
3493 case 0x1:
3494 ret = EXCP_DEBUG;
3495 cs->watchpoint_hit = &hw_watchpoint;
3496 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3497 hw_watchpoint.flags = BP_MEM_WRITE;
3498 break;
3499 case 0x3:
3500 ret = EXCP_DEBUG;
3501 cs->watchpoint_hit = &hw_watchpoint;
3502 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3503 hw_watchpoint.flags = BP_MEM_ACCESS;
3504 break;
3505 }
3506 }
3507 }
3508 }
3509 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3510 ret = EXCP_DEBUG;
3511 }
3512 if (ret == 0) {
3513 cpu_synchronize_state(cs);
3514 assert(env->exception_injected == -1);
3515
3516 /* pass to guest */
3517 env->exception_injected = arch_info->exception;
3518 env->has_error_code = 0;
3519 }
3520
3521 return ret;
3522 }
3523
3524 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3525 {
3526 const uint8_t type_code[] = {
3527 [GDB_BREAKPOINT_HW] = 0x0,
3528 [GDB_WATCHPOINT_WRITE] = 0x1,
3529 [GDB_WATCHPOINT_ACCESS] = 0x3
3530 };
3531 const uint8_t len_code[] = {
3532 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3533 };
3534 int n;
3535
3536 if (kvm_sw_breakpoints_active(cpu)) {
3537 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3538 }
3539 if (nb_hw_breakpoint > 0) {
3540 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3541 dbg->arch.debugreg[7] = 0x0600;
3542 for (n = 0; n < nb_hw_breakpoint; n++) {
3543 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3544 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3545 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3546 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3547 }
3548 }
3549 }
3550
3551 static bool host_supports_vmx(void)
3552 {
3553 uint32_t ecx, unused;
3554
3555 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3556 return ecx & CPUID_EXT_VMX;
3557 }
3558
3559 #define VMX_INVALID_GUEST_STATE 0x80000021
3560
3561 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3562 {
3563 X86CPU *cpu = X86_CPU(cs);
3564 uint64_t code;
3565 int ret;
3566
3567 switch (run->exit_reason) {
3568 case KVM_EXIT_HLT:
3569 DPRINTF("handle_hlt\n");
3570 qemu_mutex_lock_iothread();
3571 ret = kvm_handle_halt(cpu);
3572 qemu_mutex_unlock_iothread();
3573 break;
3574 case KVM_EXIT_SET_TPR:
3575 ret = 0;
3576 break;
3577 case KVM_EXIT_TPR_ACCESS:
3578 qemu_mutex_lock_iothread();
3579 ret = kvm_handle_tpr_access(cpu);
3580 qemu_mutex_unlock_iothread();
3581 break;
3582 case KVM_EXIT_FAIL_ENTRY:
3583 code = run->fail_entry.hardware_entry_failure_reason;
3584 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3585 code);
3586 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3587 fprintf(stderr,
3588 "\nIf you're running a guest on an Intel machine without "
3589 "unrestricted mode\n"
3590 "support, the failure can be most likely due to the guest "
3591 "entering an invalid\n"
3592 "state for Intel VT. For example, the guest maybe running "
3593 "in big real mode\n"
3594 "which is not supported on less recent Intel processors."
3595 "\n\n");
3596 }
3597 ret = -1;
3598 break;
3599 case KVM_EXIT_EXCEPTION:
3600 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3601 run->ex.exception, run->ex.error_code);
3602 ret = -1;
3603 break;
3604 case KVM_EXIT_DEBUG:
3605 DPRINTF("kvm_exit_debug\n");
3606 qemu_mutex_lock_iothread();
3607 ret = kvm_handle_debug(cpu, &run->debug.arch);
3608 qemu_mutex_unlock_iothread();
3609 break;
3610 case KVM_EXIT_HYPERV:
3611 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3612 break;
3613 case KVM_EXIT_IOAPIC_EOI:
3614 ioapic_eoi_broadcast(run->eoi.vector);
3615 ret = 0;
3616 break;
3617 default:
3618 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3619 ret = -1;
3620 break;
3621 }
3622
3623 return ret;
3624 }
3625
3626 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3627 {
3628 X86CPU *cpu = X86_CPU(cs);
3629 CPUX86State *env = &cpu->env;
3630
3631 kvm_cpu_synchronize_state(cs);
3632 return !(env->cr[0] & CR0_PE_MASK) ||
3633 ((env->segs[R_CS].selector & 3) != 3);
3634 }
3635
3636 void kvm_arch_init_irq_routing(KVMState *s)
3637 {
3638 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3639 /* If kernel can't do irq routing, interrupt source
3640 * override 0->2 cannot be set up as required by HPET.
3641 * So we have to disable it.
3642 */
3643 no_hpet = 1;
3644 }
3645 /* We know at this point that we're using the in-kernel
3646 * irqchip, so we can use irqfds, and on x86 we know
3647 * we can use msi via irqfd and GSI routing.
3648 */
3649 kvm_msi_via_irqfd_allowed = true;
3650 kvm_gsi_routing_allowed = true;
3651
3652 if (kvm_irqchip_is_split()) {
3653 int i;
3654
3655 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3656 MSI routes for signaling interrupts to the local apics. */
3657 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3658 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3659 error_report("Could not enable split IRQ mode.");
3660 exit(1);
3661 }
3662 }
3663 }
3664 }
3665
3666 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3667 {
3668 int ret;
3669 if (machine_kernel_irqchip_split(ms)) {
3670 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3671 if (ret) {
3672 error_report("Could not enable split irqchip mode: %s",
3673 strerror(-ret));
3674 exit(1);
3675 } else {
3676 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3677 kvm_split_irqchip = true;
3678 return 1;
3679 }
3680 } else {
3681 return 0;
3682 }
3683 }
3684
3685 /* Classic KVM device assignment interface. Will remain x86 only. */
3686 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3687 uint32_t flags, uint32_t *dev_id)
3688 {
3689 struct kvm_assigned_pci_dev dev_data = {
3690 .segnr = dev_addr->domain,
3691 .busnr = dev_addr->bus,
3692 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3693 .flags = flags,
3694 };
3695 int ret;
3696
3697 dev_data.assigned_dev_id =
3698 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3699
3700 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3701 if (ret < 0) {
3702 return ret;
3703 }
3704
3705 *dev_id = dev_data.assigned_dev_id;
3706
3707 return 0;
3708 }
3709
3710 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3711 {
3712 struct kvm_assigned_pci_dev dev_data = {
3713 .assigned_dev_id = dev_id,
3714 };
3715
3716 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3717 }
3718
3719 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3720 uint32_t irq_type, uint32_t guest_irq)
3721 {
3722 struct kvm_assigned_irq assigned_irq = {
3723 .assigned_dev_id = dev_id,
3724 .guest_irq = guest_irq,
3725 .flags = irq_type,
3726 };
3727
3728 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3729 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3730 } else {
3731 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3732 }
3733 }
3734
3735 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3736 uint32_t guest_irq)
3737 {
3738 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3739 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3740
3741 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3742 }
3743
3744 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3745 {
3746 struct kvm_assigned_pci_dev dev_data = {
3747 .assigned_dev_id = dev_id,
3748 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3749 };
3750
3751 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3752 }
3753
3754 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3755 uint32_t type)
3756 {
3757 struct kvm_assigned_irq assigned_irq = {
3758 .assigned_dev_id = dev_id,
3759 .flags = type,
3760 };
3761
3762 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3763 }
3764
3765 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3766 {
3767 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3768 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3769 }
3770
3771 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3772 {
3773 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3774 KVM_DEV_IRQ_GUEST_MSI, virq);
3775 }
3776
3777 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3778 {
3779 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3780 KVM_DEV_IRQ_HOST_MSI);
3781 }
3782
3783 bool kvm_device_msix_supported(KVMState *s)
3784 {
3785 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3786 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3787 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3788 }
3789
3790 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3791 uint32_t nr_vectors)
3792 {
3793 struct kvm_assigned_msix_nr msix_nr = {
3794 .assigned_dev_id = dev_id,
3795 .entry_nr = nr_vectors,
3796 };
3797
3798 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3799 }
3800
3801 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3802 int virq)
3803 {
3804 struct kvm_assigned_msix_entry msix_entry = {
3805 .assigned_dev_id = dev_id,
3806 .gsi = virq,
3807 .entry = vector,
3808 };
3809
3810 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3811 }
3812
3813 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3814 {
3815 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3816 KVM_DEV_IRQ_GUEST_MSIX, 0);
3817 }
3818
3819 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3820 {
3821 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3822 KVM_DEV_IRQ_HOST_MSIX);
3823 }
3824
3825 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3826 uint64_t address, uint32_t data, PCIDevice *dev)
3827 {
3828 X86IOMMUState *iommu = x86_iommu_get_default();
3829
3830 if (iommu) {
3831 int ret;
3832 MSIMessage src, dst;
3833 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3834
3835 if (!class->int_remap) {
3836 return 0;
3837 }
3838
3839 src.address = route->u.msi.address_hi;
3840 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3841 src.address |= route->u.msi.address_lo;
3842 src.data = route->u.msi.data;
3843
3844 ret = class->int_remap(iommu, &src, &dst, dev ? \
3845 pci_requester_id(dev) : \
3846 X86_IOMMU_SID_INVALID);
3847 if (ret) {
3848 trace_kvm_x86_fixup_msi_error(route->gsi);
3849 return 1;
3850 }
3851
3852 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3853 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3854 route->u.msi.data = dst.data;
3855 }
3856
3857 return 0;
3858 }
3859
3860 typedef struct MSIRouteEntry MSIRouteEntry;
3861
3862 struct MSIRouteEntry {
3863 PCIDevice *dev; /* Device pointer */
3864 int vector; /* MSI/MSIX vector index */
3865 int virq; /* Virtual IRQ index */
3866 QLIST_ENTRY(MSIRouteEntry) list;
3867 };
3868
3869 /* List of used GSI routes */
3870 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3871 QLIST_HEAD_INITIALIZER(msi_route_list);
3872
3873 static void kvm_update_msi_routes_all(void *private, bool global,
3874 uint32_t index, uint32_t mask)
3875 {
3876 int cnt = 0;
3877 MSIRouteEntry *entry;
3878 MSIMessage msg;
3879 PCIDevice *dev;
3880
3881 /* TODO: explicit route update */
3882 QLIST_FOREACH(entry, &msi_route_list, list) {
3883 cnt++;
3884 dev = entry->dev;
3885 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3886 continue;
3887 }
3888 msg = pci_get_msi_message(dev, entry->vector);
3889 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3890 }
3891 kvm_irqchip_commit_routes(kvm_state);
3892 trace_kvm_x86_update_msi_routes(cnt);
3893 }
3894
3895 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3896 int vector, PCIDevice *dev)
3897 {
3898 static bool notify_list_inited = false;
3899 MSIRouteEntry *entry;
3900
3901 if (!dev) {
3902 /* These are (possibly) IOAPIC routes only used for split
3903 * kernel irqchip mode, while what we are housekeeping are
3904 * PCI devices only. */
3905 return 0;
3906 }
3907
3908 entry = g_new0(MSIRouteEntry, 1);
3909 entry->dev = dev;
3910 entry->vector = vector;
3911 entry->virq = route->gsi;
3912 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3913
3914 trace_kvm_x86_add_msi_route(route->gsi);
3915
3916 if (!notify_list_inited) {
3917 /* For the first time we do add route, add ourselves into
3918 * IOMMU's IEC notify list if needed. */
3919 X86IOMMUState *iommu = x86_iommu_get_default();
3920 if (iommu) {
3921 x86_iommu_iec_register_notifier(iommu,
3922 kvm_update_msi_routes_all,
3923 NULL);
3924 }
3925 notify_list_inited = true;
3926 }
3927 return 0;
3928 }
3929
3930 int kvm_arch_release_virq_post(int virq)
3931 {
3932 MSIRouteEntry *entry, *next;
3933 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3934 if (entry->virq == virq) {
3935 trace_kvm_x86_remove_msi_route(virq);
3936 QLIST_REMOVE(entry, list);
3937 g_free(entry);
3938 break;
3939 }
3940 }
3941 return 0;
3942 }
3943
3944 int kvm_arch_msi_data_to_gsi(uint32_t data)
3945 {
3946 abort();
3947 }
AR7 emulation for QEMU