2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/memop.h"
27 #include "fpu_helper.h"
29 /*****************************************************************************/
30 /* Exceptions processing helpers */
32 void helper_raise_exception_err(CPUMIPSState
*env
, uint32_t exception
,
35 do_raise_exception_err(env
, exception
, error_code
, 0);
38 void helper_raise_exception(CPUMIPSState
*env
, uint32_t exception
)
40 do_raise_exception(env
, exception
, GETPC());
43 void helper_raise_exception_debug(CPUMIPSState
*env
)
45 do_raise_exception(env
, EXCP_DEBUG
, 0);
48 static void raise_exception(CPUMIPSState
*env
, uint32_t exception
)
50 do_raise_exception(env
, exception
, 0);
53 /* 64 bits arithmetic for 32 bits hosts */
54 static inline uint64_t get_HILO(CPUMIPSState
*env
)
56 return ((uint64_t)(env
->active_tc
.HI
[0]) << 32) |
57 (uint32_t)env
->active_tc
.LO
[0];
60 static inline target_ulong
set_HIT0_LO(CPUMIPSState
*env
, uint64_t HILO
)
62 env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
63 return env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
66 static inline target_ulong
set_HI_LOT0(CPUMIPSState
*env
, uint64_t HILO
)
68 target_ulong tmp
= env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
69 env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
73 /* Multiplication variants of the vr54xx. */
74 target_ulong
helper_muls(CPUMIPSState
*env
, target_ulong arg1
,
77 return set_HI_LOT0(env
, 0 - ((int64_t)(int32_t)arg1
*
78 (int64_t)(int32_t)arg2
));
81 target_ulong
helper_mulsu(CPUMIPSState
*env
, target_ulong arg1
,
84 return set_HI_LOT0(env
, 0 - (uint64_t)(uint32_t)arg1
*
85 (uint64_t)(uint32_t)arg2
);
88 target_ulong
helper_macc(CPUMIPSState
*env
, target_ulong arg1
,
91 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
92 (int64_t)(int32_t)arg2
);
95 target_ulong
helper_macchi(CPUMIPSState
*env
, target_ulong arg1
,
98 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
99 (int64_t)(int32_t)arg2
);
102 target_ulong
helper_maccu(CPUMIPSState
*env
, target_ulong arg1
,
105 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) +
106 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
109 target_ulong
helper_macchiu(CPUMIPSState
*env
, target_ulong arg1
,
112 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) +
113 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
116 target_ulong
helper_msac(CPUMIPSState
*env
, target_ulong arg1
,
119 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
120 (int64_t)(int32_t)arg2
);
123 target_ulong
helper_msachi(CPUMIPSState
*env
, target_ulong arg1
,
126 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
127 (int64_t)(int32_t)arg2
);
130 target_ulong
helper_msacu(CPUMIPSState
*env
, target_ulong arg1
,
133 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) -
134 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
137 target_ulong
helper_msachiu(CPUMIPSState
*env
, target_ulong arg1
,
140 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) -
141 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
144 target_ulong
helper_mulhi(CPUMIPSState
*env
, target_ulong arg1
,
147 return set_HIT0_LO(env
, (int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
);
150 target_ulong
helper_mulhiu(CPUMIPSState
*env
, target_ulong arg1
,
153 return set_HIT0_LO(env
, (uint64_t)(uint32_t)arg1
*
154 (uint64_t)(uint32_t)arg2
);
157 target_ulong
helper_mulshi(CPUMIPSState
*env
, target_ulong arg1
,
160 return set_HIT0_LO(env
, 0 - (int64_t)(int32_t)arg1
*
161 (int64_t)(int32_t)arg2
);
164 target_ulong
helper_mulshiu(CPUMIPSState
*env
, target_ulong arg1
,
167 return set_HIT0_LO(env
, 0 - (uint64_t)(uint32_t)arg1
*
168 (uint64_t)(uint32_t)arg2
);
171 static inline target_ulong
bitswap(target_ulong v
)
173 v
= ((v
>> 1) & (target_ulong
)0x5555555555555555ULL
) |
174 ((v
& (target_ulong
)0x5555555555555555ULL
) << 1);
175 v
= ((v
>> 2) & (target_ulong
)0x3333333333333333ULL
) |
176 ((v
& (target_ulong
)0x3333333333333333ULL
) << 2);
177 v
= ((v
>> 4) & (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) |
178 ((v
& (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) << 4);
183 target_ulong
helper_dbitswap(target_ulong rt
)
189 target_ulong
helper_bitswap(target_ulong rt
)
191 return (int32_t)bitswap(rt
);
194 target_ulong
helper_rotx(target_ulong rs
, uint32_t shift
, uint32_t shiftx
,
198 uint64_t tmp0
= ((uint64_t)rs
) << 32 | ((uint64_t)rs
& 0xffffffff);
199 uint64_t tmp1
= tmp0
;
200 for (i
= 0; i
<= 46; i
++) {
208 if (stripe
!= 0 && !(i
& 0x4)) {
212 if (tmp0
& (1LL << (i
+ 16))) {
220 uint64_t tmp2
= tmp1
;
221 for (i
= 0; i
<= 38; i
++) {
230 if (tmp1
& (1LL << (i
+ 8))) {
238 uint64_t tmp3
= tmp2
;
239 for (i
= 0; i
<= 34; i
++) {
247 if (tmp2
& (1LL << (i
+ 4))) {
255 uint64_t tmp4
= tmp3
;
256 for (i
= 0; i
<= 32; i
++) {
264 if (tmp3
& (1LL << (i
+ 2))) {
272 uint64_t tmp5
= tmp4
;
273 for (i
= 0; i
<= 31; i
++) {
277 if (tmp4
& (1LL << (i
+ 1))) {
285 return (int64_t)(int32_t)(uint32_t)tmp5
;
288 #ifndef CONFIG_USER_ONLY
290 static inline hwaddr
do_translate_address(CPUMIPSState
*env
,
291 target_ulong address
,
292 MMUAccessType access_type
,
296 CPUState
*cs
= env_cpu(env
);
298 paddr
= cpu_mips_translate_address(env
, address
, access_type
);
301 cpu_loop_exit_restore(cs
, retaddr
);
307 #define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \
308 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
310 if (arg & almask) { \
311 if (!(env->hflags & MIPS_HFLAG_DM)) { \
312 env->CP0_BadVAddr = arg; \
314 do_raise_exception(env, EXCP_AdEL, GETPC()); \
316 env->CP0_LLAddr = do_translate_address(env, arg, MMU_DATA_LOAD, GETPC()); \
318 env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); \
321 HELPER_LD_ATOMIC(ll
, ldl
, 0x3, (target_long
)(int32_t))
323 HELPER_LD_ATOMIC(lld
, ldq
, 0x7, (target_ulong
))
325 #undef HELPER_LD_ATOMIC
328 #ifdef TARGET_WORDS_BIGENDIAN
329 #define GET_LMASK(v) ((v) & 3)
330 #define GET_OFFSET(addr, offset) (addr + (offset))
332 #define GET_LMASK(v) (((v) & 3) ^ 3)
333 #define GET_OFFSET(addr, offset) (addr - (offset))
336 void helper_swl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
339 cpu_stb_mmuidx_ra(env
, arg2
, (uint8_t)(arg1
>> 24), mem_idx
, GETPC());
341 if (GET_LMASK(arg2
) <= 2) {
342 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 16),
346 if (GET_LMASK(arg2
) <= 1) {
347 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 8),
351 if (GET_LMASK(arg2
) == 0) {
352 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 3), (uint8_t)arg1
,
357 void helper_swr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
360 cpu_stb_mmuidx_ra(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
362 if (GET_LMASK(arg2
) >= 1) {
363 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8),
367 if (GET_LMASK(arg2
) >= 2) {
368 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16),
372 if (GET_LMASK(arg2
) == 3) {
373 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24),
378 #if defined(TARGET_MIPS64)
380 * "half" load and stores. We must do the memory access inline,
381 * or fault handling won't work.
383 #ifdef TARGET_WORDS_BIGENDIAN
384 #define GET_LMASK64(v) ((v) & 7)
386 #define GET_LMASK64(v) (((v) & 7) ^ 7)
389 void helper_sdl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
392 cpu_stb_mmuidx_ra(env
, arg2
, (uint8_t)(arg1
>> 56), mem_idx
, GETPC());
394 if (GET_LMASK64(arg2
) <= 6) {
395 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 48),
399 if (GET_LMASK64(arg2
) <= 5) {
400 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 40),
404 if (GET_LMASK64(arg2
) <= 4) {
405 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 3), (uint8_t)(arg1
>> 32),
409 if (GET_LMASK64(arg2
) <= 3) {
410 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 4), (uint8_t)(arg1
>> 24),
414 if (GET_LMASK64(arg2
) <= 2) {
415 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 5), (uint8_t)(arg1
>> 16),
419 if (GET_LMASK64(arg2
) <= 1) {
420 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 6), (uint8_t)(arg1
>> 8),
424 if (GET_LMASK64(arg2
) <= 0) {
425 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, 7), (uint8_t)arg1
,
430 void helper_sdr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
433 cpu_stb_mmuidx_ra(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
435 if (GET_LMASK64(arg2
) >= 1) {
436 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8),
440 if (GET_LMASK64(arg2
) >= 2) {
441 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16),
445 if (GET_LMASK64(arg2
) >= 3) {
446 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24),
450 if (GET_LMASK64(arg2
) >= 4) {
451 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -4), (uint8_t)(arg1
>> 32),
455 if (GET_LMASK64(arg2
) >= 5) {
456 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -5), (uint8_t)(arg1
>> 40),
460 if (GET_LMASK64(arg2
) >= 6) {
461 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -6), (uint8_t)(arg1
>> 48),
465 if (GET_LMASK64(arg2
) == 7) {
466 cpu_stb_mmuidx_ra(env
, GET_OFFSET(arg2
, -7), (uint8_t)(arg1
>> 56),
470 #endif /* TARGET_MIPS64 */
472 static const int multiple_regs
[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
474 void helper_lwm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
477 target_ulong base_reglist
= reglist
& 0xf;
478 target_ulong do_r31
= reglist
& 0x10;
480 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE(multiple_regs
)) {
483 for (i
= 0; i
< base_reglist
; i
++) {
484 env
->active_tc
.gpr
[multiple_regs
[i
]] =
485 (target_long
)cpu_ldl_mmuidx_ra(env
, addr
, mem_idx
, GETPC());
491 env
->active_tc
.gpr
[31] =
492 (target_long
)cpu_ldl_mmuidx_ra(env
, addr
, mem_idx
, GETPC());
496 void helper_swm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
499 target_ulong base_reglist
= reglist
& 0xf;
500 target_ulong do_r31
= reglist
& 0x10;
502 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE(multiple_regs
)) {
505 for (i
= 0; i
< base_reglist
; i
++) {
506 cpu_stw_mmuidx_ra(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]],
513 cpu_stw_mmuidx_ra(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
517 #if defined(TARGET_MIPS64)
518 void helper_ldm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
521 target_ulong base_reglist
= reglist
& 0xf;
522 target_ulong do_r31
= reglist
& 0x10;
524 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE(multiple_regs
)) {
527 for (i
= 0; i
< base_reglist
; i
++) {
528 env
->active_tc
.gpr
[multiple_regs
[i
]] =
529 cpu_ldq_mmuidx_ra(env
, addr
, mem_idx
, GETPC());
535 env
->active_tc
.gpr
[31] =
536 cpu_ldq_mmuidx_ra(env
, addr
, mem_idx
, GETPC());
540 void helper_sdm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
543 target_ulong base_reglist
= reglist
& 0xf;
544 target_ulong do_r31
= reglist
& 0x10;
546 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE(multiple_regs
)) {
549 for (i
= 0; i
< base_reglist
; i
++) {
550 cpu_stq_mmuidx_ra(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]],
557 cpu_stq_mmuidx_ra(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
563 void helper_fork(target_ulong arg1
, target_ulong arg2
)
566 * arg1 = rt, arg2 = rs
567 * TODO: store to TC register
571 target_ulong
helper_yield(CPUMIPSState
*env
, target_ulong arg
)
573 target_long arg1
= arg
;
576 /* No scheduling policy implemented. */
578 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
579 env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_DT
)) {
580 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
581 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
582 do_raise_exception(env
, EXCP_THREAD
, GETPC());
585 } else if (arg1
== 0) {
587 /* TODO: TC underflow */
588 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
589 do_raise_exception(env
, EXCP_THREAD
, GETPC());
591 /* TODO: Deallocate TC */
593 } else if (arg1
> 0) {
594 /* Yield qualifier inputs not implemented. */
595 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
596 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
597 do_raise_exception(env
, EXCP_THREAD
, GETPC());
599 return env
->CP0_YQMask
;
602 #ifndef CONFIG_USER_ONLY
604 static void r4k_mips_tlb_flush_extra(CPUMIPSState
*env
, int first
)
606 /* Discard entries from env->tlb[first] onwards. */
607 while (env
->tlb
->tlb_in_use
> first
) {
608 r4k_invalidate_tlb(env
, --env
->tlb
->tlb_in_use
, 0);
612 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo
)
614 #if defined(TARGET_MIPS64)
615 return extract64(entrylo
, 6, 54);
617 return extract64(entrylo
, 6, 24) | /* PFN */
618 (extract64(entrylo
, 32, 32) << 24); /* PFNX */
622 static void r4k_fill_tlb(CPUMIPSState
*env
, int idx
)
625 uint64_t mask
= env
->CP0_PageMask
>> (TARGET_PAGE_BITS
+ 1);
627 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
628 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
629 if (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) {
634 tlb
->VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
635 #if defined(TARGET_MIPS64)
636 tlb
->VPN
&= env
->SEGMask
;
638 tlb
->ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
639 tlb
->MMID
= env
->CP0_MemoryMapID
;
640 tlb
->PageMask
= env
->CP0_PageMask
;
641 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
642 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
643 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
644 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
645 tlb
->XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) & 1;
646 tlb
->RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) & 1;
647 tlb
->PFN
[0] = (get_tlb_pfn_from_entrylo(env
->CP0_EntryLo0
) & ~mask
) << 12;
648 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
649 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
650 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
651 tlb
->XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) & 1;
652 tlb
->RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) & 1;
653 tlb
->PFN
[1] = (get_tlb_pfn_from_entrylo(env
->CP0_EntryLo1
) & ~mask
) << 12;
656 void r4k_helper_tlbinv(CPUMIPSState
*env
)
658 bool mi
= !!((env
->CP0_Config5
>> CP0C5_MI
) & 1);
659 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
660 uint32_t MMID
= env
->CP0_MemoryMapID
;
665 MMID
= mi
? MMID
: (uint32_t) ASID
;
666 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
667 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
668 tlb_mmid
= mi
? tlb
->MMID
: (uint32_t) tlb
->ASID
;
669 if (!tlb
->G
&& tlb_mmid
== MMID
) {
673 cpu_mips_tlb_flush(env
);
676 void r4k_helper_tlbinvf(CPUMIPSState
*env
)
680 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
681 env
->tlb
->mmu
.r4k
.tlb
[idx
].EHINV
= 1;
683 cpu_mips_tlb_flush(env
);
686 void r4k_helper_tlbwi(CPUMIPSState
*env
)
688 bool mi
= !!((env
->CP0_Config5
>> CP0C5_MI
) & 1);
690 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
691 uint32_t MMID
= env
->CP0_MemoryMapID
;
693 bool EHINV
, G
, V0
, D0
, V1
, D1
, XI0
, XI1
, RI0
, RI1
;
697 MMID
= mi
? MMID
: (uint32_t) ASID
;
699 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
700 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
701 VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
702 #if defined(TARGET_MIPS64)
705 EHINV
= (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) != 0;
706 G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
707 V0
= (env
->CP0_EntryLo0
& 2) != 0;
708 D0
= (env
->CP0_EntryLo0
& 4) != 0;
709 XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) &1;
710 RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) &1;
711 V1
= (env
->CP0_EntryLo1
& 2) != 0;
712 D1
= (env
->CP0_EntryLo1
& 4) != 0;
713 XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) &1;
714 RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) &1;
716 tlb_mmid
= mi
? tlb
->MMID
: (uint32_t) tlb
->ASID
;
718 * Discard cached TLB entries, unless tlbwi is just upgrading access
719 * permissions on the current entry.
721 if (tlb
->VPN
!= VPN
|| tlb_mmid
!= MMID
|| tlb
->G
!= G
||
722 (!tlb
->EHINV
&& EHINV
) ||
723 (tlb
->V0
&& !V0
) || (tlb
->D0
&& !D0
) ||
724 (!tlb
->XI0
&& XI0
) || (!tlb
->RI0
&& RI0
) ||
725 (tlb
->V1
&& !V1
) || (tlb
->D1
&& !D1
) ||
726 (!tlb
->XI1
&& XI1
) || (!tlb
->RI1
&& RI1
)) {
727 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
730 r4k_invalidate_tlb(env
, idx
, 0);
731 r4k_fill_tlb(env
, idx
);
734 void r4k_helper_tlbwr(CPUMIPSState
*env
)
736 int r
= cpu_mips_get_random(env
);
738 r4k_invalidate_tlb(env
, r
, 1);
739 r4k_fill_tlb(env
, r
);
742 void r4k_helper_tlbp(CPUMIPSState
*env
)
744 bool mi
= !!((env
->CP0_Config5
>> CP0C5_MI
) & 1);
749 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
750 uint32_t MMID
= env
->CP0_MemoryMapID
;
754 MMID
= mi
? MMID
: (uint32_t) ASID
;
755 for (i
= 0; i
< env
->tlb
->nb_tlb
; i
++) {
756 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
757 /* 1k pages are not supported. */
758 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
759 tag
= env
->CP0_EntryHi
& ~mask
;
760 VPN
= tlb
->VPN
& ~mask
;
761 #if defined(TARGET_MIPS64)
764 tlb_mmid
= mi
? tlb
->MMID
: (uint32_t) tlb
->ASID
;
765 /* Check ASID/MMID, virtual page number & size */
766 if ((tlb
->G
== 1 || tlb_mmid
== MMID
) && VPN
== tag
&& !tlb
->EHINV
) {
772 if (i
== env
->tlb
->nb_tlb
) {
773 /* No match. Discard any shadow entries, if any of them match. */
774 for (i
= env
->tlb
->nb_tlb
; i
< env
->tlb
->tlb_in_use
; i
++) {
775 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
776 /* 1k pages are not supported. */
777 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
778 tag
= env
->CP0_EntryHi
& ~mask
;
779 VPN
= tlb
->VPN
& ~mask
;
780 #if defined(TARGET_MIPS64)
783 tlb_mmid
= mi
? tlb
->MMID
: (uint32_t) tlb
->ASID
;
784 /* Check ASID/MMID, virtual page number & size */
785 if ((tlb
->G
== 1 || tlb_mmid
== MMID
) && VPN
== tag
) {
786 r4k_mips_tlb_flush_extra(env
, i
);
791 env
->CP0_Index
|= 0x80000000;
795 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn
)
797 #if defined(TARGET_MIPS64)
800 return (extract64(tlb_pfn
, 0, 24) << 6) | /* PFN */
801 (extract64(tlb_pfn
, 24, 32) << 32); /* PFNX */
805 void r4k_helper_tlbr(CPUMIPSState
*env
)
807 bool mi
= !!((env
->CP0_Config5
>> CP0C5_MI
) & 1);
808 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
809 uint32_t MMID
= env
->CP0_MemoryMapID
;
814 MMID
= mi
? MMID
: (uint32_t) ASID
;
815 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
816 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
818 tlb_mmid
= mi
? tlb
->MMID
: (uint32_t) tlb
->ASID
;
819 /* If this will change the current ASID/MMID, flush qemu's TLB. */
820 if (MMID
!= tlb_mmid
) {
821 cpu_mips_tlb_flush(env
);
824 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
827 env
->CP0_EntryHi
= 1 << CP0EnHi_EHINV
;
828 env
->CP0_PageMask
= 0;
829 env
->CP0_EntryLo0
= 0;
830 env
->CP0_EntryLo1
= 0;
832 env
->CP0_EntryHi
= mi
? tlb
->VPN
: tlb
->VPN
| tlb
->ASID
;
833 env
->CP0_MemoryMapID
= tlb
->MMID
;
834 env
->CP0_PageMask
= tlb
->PageMask
;
835 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2) |
836 ((uint64_t)tlb
->RI0
<< CP0EnLo_RI
) |
837 ((uint64_t)tlb
->XI0
<< CP0EnLo_XI
) | (tlb
->C0
<< 3) |
838 get_entrylo_pfn_from_tlb(tlb
->PFN
[0] >> 12);
839 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2) |
840 ((uint64_t)tlb
->RI1
<< CP0EnLo_RI
) |
841 ((uint64_t)tlb
->XI1
<< CP0EnLo_XI
) | (tlb
->C1
<< 3) |
842 get_entrylo_pfn_from_tlb(tlb
->PFN
[1] >> 12);
846 void helper_tlbwi(CPUMIPSState
*env
)
848 env
->tlb
->helper_tlbwi(env
);
851 void helper_tlbwr(CPUMIPSState
*env
)
853 env
->tlb
->helper_tlbwr(env
);
856 void helper_tlbp(CPUMIPSState
*env
)
858 env
->tlb
->helper_tlbp(env
);
861 void helper_tlbr(CPUMIPSState
*env
)
863 env
->tlb
->helper_tlbr(env
);
866 void helper_tlbinv(CPUMIPSState
*env
)
868 env
->tlb
->helper_tlbinv(env
);
871 void helper_tlbinvf(CPUMIPSState
*env
)
873 env
->tlb
->helper_tlbinvf(env
);
876 static void global_invalidate_tlb(CPUMIPSState
*env
,
891 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
892 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
894 (((tlb
->VPN
& ~tlb
->PageMask
) == (invMsgVPN2
& ~tlb
->PageMask
))
897 (extract64(env
->CP0_EntryHi
, 62, 2) == invMsgR
)
900 MMidMatch
= tlb
->MMID
== invMsgMMid
;
901 if ((invAll
&& (idx
> env
->CP0_Wired
)) ||
902 (VAMatch
&& invVAMMid
&& (tlb
->G
|| MMidMatch
)) ||
903 (VAMatch
&& invVA
) ||
904 (MMidMatch
&& !(tlb
->G
) && invMMid
)) {
908 cpu_mips_tlb_flush(env
);
911 void helper_ginvt(CPUMIPSState
*env
, target_ulong arg
, uint32_t type
)
913 bool invAll
= type
== 0;
914 bool invVA
= type
== 1;
915 bool invMMid
= type
== 2;
916 bool invVAMMid
= type
== 3;
917 uint32_t invMsgVPN2
= arg
& (TARGET_PAGE_MASK
<< 1);
919 uint32_t invMsgMMid
= env
->CP0_MemoryMapID
;
920 CPUState
*other_cs
= first_cpu
;
923 invMsgR
= extract64(arg
, 62, 2);
926 CPU_FOREACH(other_cs
) {
927 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
928 global_invalidate_tlb(&other_cpu
->env
, invMsgVPN2
, invMsgR
, invMsgMMid
,
929 invAll
, invVAMMid
, invMMid
, invVA
);
934 target_ulong
helper_di(CPUMIPSState
*env
)
936 target_ulong t0
= env
->CP0_Status
;
938 env
->CP0_Status
= t0
& ~(1 << CP0St_IE
);
942 target_ulong
helper_ei(CPUMIPSState
*env
)
944 target_ulong t0
= env
->CP0_Status
;
946 env
->CP0_Status
= t0
| (1 << CP0St_IE
);
950 static void debug_pre_eret(CPUMIPSState
*env
)
952 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
953 qemu_log("ERET: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
954 env
->active_tc
.PC
, env
->CP0_EPC
);
955 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
956 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
958 if (env
->hflags
& MIPS_HFLAG_DM
) {
959 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
965 static void debug_post_eret(CPUMIPSState
*env
)
967 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
968 qemu_log(" => PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
969 env
->active_tc
.PC
, env
->CP0_EPC
);
970 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
971 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
973 if (env
->hflags
& MIPS_HFLAG_DM
) {
974 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
976 switch (cpu_mmu_index(env
, false)) {
990 cpu_abort(env_cpu(env
), "Invalid MMU mode!\n");
996 static void set_pc(CPUMIPSState
*env
, target_ulong error_pc
)
998 env
->active_tc
.PC
= error_pc
& ~(target_ulong
)1;
1000 env
->hflags
|= MIPS_HFLAG_M16
;
1002 env
->hflags
&= ~(MIPS_HFLAG_M16
);
1006 static inline void exception_return(CPUMIPSState
*env
)
1008 debug_pre_eret(env
);
1009 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
1010 set_pc(env
, env
->CP0_ErrorEPC
);
1011 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
1013 set_pc(env
, env
->CP0_EPC
);
1014 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
1016 compute_hflags(env
);
1017 debug_post_eret(env
);
1020 void helper_eret(CPUMIPSState
*env
)
1022 exception_return(env
);
1023 env
->CP0_LLAddr
= 1;
1027 void helper_eretnc(CPUMIPSState
*env
)
1029 exception_return(env
);
1032 void helper_deret(CPUMIPSState
*env
)
1034 debug_pre_eret(env
);
1036 env
->hflags
&= ~MIPS_HFLAG_DM
;
1037 compute_hflags(env
);
1039 set_pc(env
, env
->CP0_DEPC
);
1041 debug_post_eret(env
);
1043 #endif /* !CONFIG_USER_ONLY */
1045 static inline void check_hwrena(CPUMIPSState
*env
, int reg
, uintptr_t pc
)
1047 if ((env
->hflags
& MIPS_HFLAG_CP0
) || (env
->CP0_HWREna
& (1 << reg
))) {
1050 do_raise_exception(env
, EXCP_RI
, pc
);
1053 target_ulong
helper_rdhwr_cpunum(CPUMIPSState
*env
)
1055 check_hwrena(env
, 0, GETPC());
1056 return env
->CP0_EBase
& 0x3ff;
1059 target_ulong
helper_rdhwr_synci_step(CPUMIPSState
*env
)
1061 check_hwrena(env
, 1, GETPC());
1062 return env
->SYNCI_Step
;
1065 target_ulong
helper_rdhwr_cc(CPUMIPSState
*env
)
1067 check_hwrena(env
, 2, GETPC());
1068 #ifdef CONFIG_USER_ONLY
1069 return env
->CP0_Count
;
1071 return (int32_t)cpu_mips_get_count(env
);
1075 target_ulong
helper_rdhwr_ccres(CPUMIPSState
*env
)
1077 check_hwrena(env
, 3, GETPC());
1081 target_ulong
helper_rdhwr_performance(CPUMIPSState
*env
)
1083 check_hwrena(env
, 4, GETPC());
1084 return env
->CP0_Performance0
;
1087 target_ulong
helper_rdhwr_xnp(CPUMIPSState
*env
)
1089 check_hwrena(env
, 5, GETPC());
1090 return (env
->CP0_Config5
>> CP0C5_XNP
) & 1;
1093 void helper_pmon(CPUMIPSState
*env
, int function
)
1097 case 2: /* TODO: char inbyte(int waitflag); */
1098 if (env
->active_tc
.gpr
[4] == 0) {
1099 env
->active_tc
.gpr
[2] = -1;
1102 case 11: /* TODO: char inbyte (void); */
1103 env
->active_tc
.gpr
[2] = -1;
1107 printf("%c", (char)(env
->active_tc
.gpr
[4] & 0xFF));
1113 unsigned char *fmt
= (void *)(uintptr_t)env
->active_tc
.gpr
[4];
1120 void helper_wait(CPUMIPSState
*env
)
1122 CPUState
*cs
= env_cpu(env
);
1125 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
1127 * Last instruction in the block, PC was updated before
1128 * - no need to recover PC and icount.
1130 raise_exception(env
, EXCP_HLT
);
1133 #if !defined(CONFIG_USER_ONLY)
1135 void mips_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
1136 MMUAccessType access_type
,
1137 int mmu_idx
, uintptr_t retaddr
)
1139 MIPSCPU
*cpu
= MIPS_CPU(cs
);
1140 CPUMIPSState
*env
= &cpu
->env
;
1144 if (!(env
->hflags
& MIPS_HFLAG_DM
)) {
1145 env
->CP0_BadVAddr
= addr
;
1148 if (access_type
== MMU_DATA_STORE
) {
1152 if (access_type
== MMU_INST_FETCH
) {
1153 error_code
|= EXCP_INST_NOTAVAIL
;
1157 do_raise_exception_err(env
, excp
, error_code
, retaddr
);
1160 void mips_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
1161 vaddr addr
, unsigned size
,
1162 MMUAccessType access_type
,
1163 int mmu_idx
, MemTxAttrs attrs
,
1164 MemTxResult response
, uintptr_t retaddr
)
1166 MIPSCPU
*cpu
= MIPS_CPU(cs
);
1167 CPUMIPSState
*env
= &cpu
->env
;
1169 if (access_type
== MMU_INST_FETCH
) {
1170 do_raise_exception(env
, EXCP_IBE
, retaddr
);
1172 do_raise_exception(env
, EXCP_DBE
, retaddr
);
1175 #endif /* !CONFIG_USER_ONLY */
1177 void helper_cache(CPUMIPSState
*env
, target_ulong addr
, uint32_t op
)
1179 #ifndef CONFIG_USER_ONLY
1180 static const char *const type_name
[] = {
1181 "Primary Instruction",
1182 "Primary Data or Unified Primary",
1186 uint32_t cache_type
= extract32(op
, 0, 2);
1187 uint32_t cache_operation
= extract32(op
, 2, 3);
1188 target_ulong index
= addr
& 0x1fffffff;
1190 switch (cache_operation
) {
1191 case 0b010: /* Index Store Tag */
1192 memory_region_dispatch_write(env
->itc_tag
, index
, env
->CP0_TagLo
,
1193 MO_64
, MEMTXATTRS_UNSPECIFIED
);
1195 case 0b001: /* Index Load Tag */
1196 memory_region_dispatch_read(env
->itc_tag
, index
, &env
->CP0_TagLo
,
1197 MO_64
, MEMTXATTRS_UNSPECIFIED
);
1199 case 0b000: /* Index Invalidate */
1200 case 0b100: /* Hit Invalidate */
1201 case 0b110: /* Hit Writeback */
1205 qemu_log_mask(LOG_UNIMP
, "cache operation:%u (type: %s cache)\n",
1206 cache_operation
, type_name
[cache_type
]);