hw/timer/milkymist-sysctl.c

   1 /*
   2  *  QEMU model of the Milkymist System Controller.
   3  *
   4  *  Copyright (c) 2010-2012 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://milkymist.walle.cc/socdoc/sysctl.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "hw/irq.h"
  26 #include "hw/sysbus.h"
  27 #include "migration/vmstate.h"
  28 #include "trace.h"
  29 #include "qemu/timer.h"
  30 #include "sysemu/runstate.h"
  31 #include "hw/ptimer.h"
  32 #include "hw/qdev-properties.h"
  33 #include "qemu/error-report.h"
  34 #include "qemu/module.h"
  35
  36 enum {
  37     CTRL_ENABLE      = (1<<0),
  38     CTRL_AUTORESTART = (1<<1),
  39 };
  40
  41 enum {
  42     ICAP_READY       = (1<<0),
  43 };
  44
  45 enum {
  46     R_GPIO_IN         = 0,
  47     R_GPIO_OUT,
  48     R_GPIO_INTEN,
  49     R_TIMER0_CONTROL  = 4,
  50     R_TIMER0_COMPARE,
  51     R_TIMER0_COUNTER,
  52     R_TIMER1_CONTROL  = 8,
  53     R_TIMER1_COMPARE,
  54     R_TIMER1_COUNTER,
  55     R_ICAP = 16,
  56     R_DBG_SCRATCHPAD  = 20,
  57     R_DBG_WRITE_LOCK,
  58     R_CLK_FREQUENCY   = 29,
  59     R_CAPABILITIES,
  60     R_SYSTEM_ID,
  61     R_MAX
  62 };
  63
  64 #define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl"
  65 #define MILKYMIST_SYSCTL(obj) \
  66     OBJECT_CHECK(MilkymistSysctlState, (obj), TYPE_MILKYMIST_SYSCTL)
  67
  68 struct MilkymistSysctlState {
  69     SysBusDevice parent_obj;
  70
  71     MemoryRegion regs_region;
  72
  73     ptimer_state *ptimer0;
  74     ptimer_state *ptimer1;
  75
  76     uint32_t freq_hz;
  77     uint32_t capabilities;
  78     uint32_t systemid;
  79     uint32_t strappings;
  80
  81     uint32_t regs[R_MAX];
  82
  83     qemu_irq gpio_irq;
  84     qemu_irq timer0_irq;
  85     qemu_irq timer1_irq;
  86 };
  87 typedef struct MilkymistSysctlState MilkymistSysctlState;
  88
  89 static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value)
  90 {
  91     trace_milkymist_sysctl_icap_write(value);
  92     switch (value & 0xffff) {
  93     case 0x000e:
  94         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
  95         break;
  96     }
  97 }
  98
  99 static uint64_t sysctl_read(void *opaque, hwaddr addr,
 100                             unsigned size)
 101 {
 102     MilkymistSysctlState *s = opaque;
 103     uint32_t r = 0;
 104
 105     addr >>= 2;
 106     switch (addr) {
 107     case R_TIMER0_COUNTER:
 108         r = (uint32_t)ptimer_get_count(s->ptimer0);
 109         /* milkymist timer counts up */
 110         r = s->regs[R_TIMER0_COMPARE] - r;
 111         break;
 112     case R_TIMER1_COUNTER:
 113         r = (uint32_t)ptimer_get_count(s->ptimer1);
 114         /* milkymist timer counts up */
 115         r = s->regs[R_TIMER1_COMPARE] - r;
 116         break;
 117     case R_GPIO_IN:
 118     case R_GPIO_OUT:
 119     case R_GPIO_INTEN:
 120     case R_TIMER0_CONTROL:
 121     case R_TIMER0_COMPARE:
 122     case R_TIMER1_CONTROL:
 123     case R_TIMER1_COMPARE:
 124     case R_ICAP:
 125     case R_DBG_SCRATCHPAD:
 126     case R_DBG_WRITE_LOCK:
 127     case R_CLK_FREQUENCY:
 128     case R_CAPABILITIES:
 129     case R_SYSTEM_ID:
 130         r = s->regs[addr];
 131         break;
 132
 133     default:
 134         error_report("milkymist_sysctl: read access to unknown register 0x"
 135                 TARGET_FMT_plx, addr << 2);
 136         break;
 137     }
 138
 139     trace_milkymist_sysctl_memory_read(addr << 2, r);
 140
 141     return r;
 142 }
 143
 144 static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
 145                          unsigned size)
 146 {
 147     MilkymistSysctlState *s = opaque;
 148
 149     trace_milkymist_sysctl_memory_write(addr, value);
 150
 151     addr >>= 2;
 152     switch (addr) {
 153     case R_GPIO_OUT:
 154     case R_GPIO_INTEN:
 155     case R_TIMER0_COUNTER:
 156     case R_TIMER1_COUNTER:
 157     case R_DBG_SCRATCHPAD:
 158         s->regs[addr] = value;
 159         break;
 160     case R_TIMER0_COMPARE:
 161         ptimer_transaction_begin(s->ptimer0);
 162         ptimer_set_limit(s->ptimer0, value, 0);
 163         s->regs[addr] = value;
 164         ptimer_transaction_commit(s->ptimer0);
 165         break;
 166     case R_TIMER1_COMPARE:
 167         ptimer_transaction_begin(s->ptimer1);
 168         ptimer_set_limit(s->ptimer1, value, 0);
 169         s->regs[addr] = value;
 170         ptimer_transaction_commit(s->ptimer1);
 171         break;
 172     case R_TIMER0_CONTROL:
 173         ptimer_transaction_begin(s->ptimer0);
 174         s->regs[addr] = value;
 175         if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) {
 176             trace_milkymist_sysctl_start_timer0();
 177             ptimer_set_count(s->ptimer0,
 178                     s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]);
 179             ptimer_run(s->ptimer0, 0);
 180         } else {
 181             trace_milkymist_sysctl_stop_timer0();
 182             ptimer_stop(s->ptimer0);
 183         }
 184         ptimer_transaction_commit(s->ptimer0);
 185         break;
 186     case R_TIMER1_CONTROL:
 187         ptimer_transaction_begin(s->ptimer1);
 188         s->regs[addr] = value;
 189         if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) {
 190             trace_milkymist_sysctl_start_timer1();
 191             ptimer_set_count(s->ptimer1,
 192                     s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]);
 193             ptimer_run(s->ptimer1, 0);
 194         } else {
 195             trace_milkymist_sysctl_stop_timer1();
 196             ptimer_stop(s->ptimer1);
 197         }
 198         ptimer_transaction_commit(s->ptimer1);
 199         break;
 200     case R_ICAP:
 201         sysctl_icap_write(s, value);
 202         break;
 203     case R_DBG_WRITE_LOCK:
 204         s->regs[addr] = 1;
 205         break;
 206     case R_SYSTEM_ID:
 207         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 208         break;
 209
 210     case R_GPIO_IN:
 211     case R_CLK_FREQUENCY:
 212     case R_CAPABILITIES:
 213         error_report("milkymist_sysctl: write to read-only register 0x"
 214                 TARGET_FMT_plx, addr << 2);
 215         break;
 216
 217     default:
 218         error_report("milkymist_sysctl: write access to unknown register 0x"
 219                 TARGET_FMT_plx, addr << 2);
 220         break;
 221     }
 222 }
 223
 224 static const MemoryRegionOps sysctl_mmio_ops = {
 225     .read = sysctl_read,
 226     .write = sysctl_write,
 227     .valid = {
 228         .min_access_size = 4,
 229         .max_access_size = 4,
 230     },
 231     .endianness = DEVICE_NATIVE_ENDIAN,
 232 };
 233
 234 static void timer0_hit(void *opaque)
 235 {
 236     MilkymistSysctlState *s = opaque;
 237
 238     if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) {
 239         s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE;
 240         trace_milkymist_sysctl_stop_timer0();
 241         ptimer_stop(s->ptimer0);
 242     }
 243
 244     trace_milkymist_sysctl_pulse_irq_timer0();
 245     qemu_irq_pulse(s->timer0_irq);
 246 }
 247
 248 static void timer1_hit(void *opaque)
 249 {
 250     MilkymistSysctlState *s = opaque;
 251
 252     if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) {
 253         s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE;
 254         trace_milkymist_sysctl_stop_timer1();
 255         ptimer_stop(s->ptimer1);
 256     }
 257
 258     trace_milkymist_sysctl_pulse_irq_timer1();
 259     qemu_irq_pulse(s->timer1_irq);
 260 }
 261
 262 static void milkymist_sysctl_reset(DeviceState *d)
 263 {
 264     MilkymistSysctlState *s = MILKYMIST_SYSCTL(d);
 265     int i;
 266
 267     for (i = 0; i < R_MAX; i++) {
 268         s->regs[i] = 0;
 269     }
 270
 271     ptimer_transaction_begin(s->ptimer0);
 272     ptimer_stop(s->ptimer0);
 273     ptimer_transaction_commit(s->ptimer0);
 274     ptimer_transaction_begin(s->ptimer1);
 275     ptimer_stop(s->ptimer1);
 276     ptimer_transaction_commit(s->ptimer1);
 277
 278     /* defaults */
 279     s->regs[R_ICAP] = ICAP_READY;
 280     s->regs[R_SYSTEM_ID] = s->systemid;
 281     s->regs[R_CLK_FREQUENCY] = s->freq_hz;
 282     s->regs[R_CAPABILITIES] = s->capabilities;
 283     s->regs[R_GPIO_IN] = s->strappings;
 284 }
 285
 286 static void milkymist_sysctl_init(Object *obj)
 287 {
 288     MilkymistSysctlState *s = MILKYMIST_SYSCTL(obj);
 289     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 290
 291     sysbus_init_irq(dev, &s->gpio_irq);
 292     sysbus_init_irq(dev, &s->timer0_irq);
 293     sysbus_init_irq(dev, &s->timer1_irq);
 294
 295     memory_region_init_io(&s->regs_region, obj, &sysctl_mmio_ops, s,
 296             "milkymist-sysctl", R_MAX * 4);
 297     sysbus_init_mmio(dev, &s->regs_region);
 298 }
 299
 300 static void milkymist_sysctl_realize(DeviceState *dev, Error **errp)
 301 {
 302     MilkymistSysctlState *s = MILKYMIST_SYSCTL(dev);
 303
 304     s->ptimer0 = ptimer_init(timer0_hit, s, PTIMER_POLICY_DEFAULT);
 305     s->ptimer1 = ptimer_init(timer1_hit, s, PTIMER_POLICY_DEFAULT);
 306
 307     ptimer_transaction_begin(s->ptimer0);
 308     ptimer_set_freq(s->ptimer0, s->freq_hz);
 309     ptimer_transaction_commit(s->ptimer0);
 310     ptimer_transaction_begin(s->ptimer1);
 311     ptimer_set_freq(s->ptimer1, s->freq_hz);
 312     ptimer_transaction_commit(s->ptimer1);
 313 }
 314
 315 static const VMStateDescription vmstate_milkymist_sysctl = {
 316     .name = "milkymist-sysctl",
 317     .version_id = 1,
 318     .minimum_version_id = 1,
 319     .fields = (VMStateField[]) {
 320         VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX),
 321         VMSTATE_PTIMER(ptimer0, MilkymistSysctlState),
 322         VMSTATE_PTIMER(ptimer1, MilkymistSysctlState),
 323         VMSTATE_END_OF_LIST()
 324     }
 325 };
 326
 327 static Property milkymist_sysctl_properties[] = {
 328     DEFINE_PROP_UINT32("frequency", MilkymistSysctlState,
 329     freq_hz, 80000000),
 330     DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState,
 331     capabilities, 0x00000000),
 332     DEFINE_PROP_UINT32("systemid", MilkymistSysctlState,
 333     systemid, 0x10014d31),
 334     DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState,
 335     strappings, 0x00000001),
 336     DEFINE_PROP_END_OF_LIST(),
 337 };
 338
 339 static void milkymist_sysctl_class_init(ObjectClass *klass, void *data)
 340 {
 341     DeviceClass *dc = DEVICE_CLASS(klass);
 342
 343     dc->realize = milkymist_sysctl_realize;
 344     dc->reset = milkymist_sysctl_reset;
 345     dc->vmsd = &vmstate_milkymist_sysctl;
 346     device_class_set_props(dc, milkymist_sysctl_properties);
 347 }
 348
 349 static const TypeInfo milkymist_sysctl_info = {
 350     .name          = TYPE_MILKYMIST_SYSCTL,
 351     .parent        = TYPE_SYS_BUS_DEVICE,
 352     .instance_size = sizeof(MilkymistSysctlState),
 353     .instance_init = milkymist_sysctl_init,
 354     .class_init    = milkymist_sysctl_class_init,
 355 };
 356
 357 static void milkymist_sysctl_register_types(void)
 358 {
 359     type_register_static(&milkymist_sysctl_info);
 360 }
 361
 362 type_init(milkymist_sysctl_register_types)