2 * USB UHCI controller emulation
4 * Copyright (c) 2005 Fabrice Bellard
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #include "qemu/osdep.h"
31 #include "hw/usb/uhci-regs.h"
32 #include "migration/vmstate.h"
33 #include "hw/pci/pci.h"
35 #include "hw/qdev-properties.h"
36 #include "qapi/error.h"
37 #include "qemu/timer.h"
39 #include "sysemu/dma.h"
41 #include "qemu/main-loop.h"
42 #include "qemu/module.h"
43 #include "qom/object.h"
46 #define FRAME_TIMER_FREQ 1000
48 #define FRAME_MAX_LOOPS 256
50 /* Must be large enough to handle 10 frame delay for initial isoc requests */
53 #define MAX_FRAMES_PER_TICK (QH_VALID / 2)
56 TD_RESULT_STOP_FRAME
= 10,
59 TD_RESULT_ASYNC_START
,
63 typedef struct UHCIState UHCIState
;
64 typedef struct UHCIAsync UHCIAsync
;
65 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass
;
67 struct UHCIPCIDeviceClass
{
68 PCIDeviceClass parent_class
;
73 * Pending async transaction.
74 * 'packet' must be the first field because completion
75 * handler does "(UHCIAsync *) pkt" cast.
80 uint8_t static_buf
[64]; /* 64 bytes is enough, except for isoc packets */
83 QTAILQ_ENTRY(UHCIAsync
) next
;
93 QTAILQ_ENTRY(UHCIQueue
) next
;
94 QTAILQ_HEAD(, UHCIAsync
) asyncs
;
98 typedef struct UHCI_TD
{
100 uint32_t ctrl
; /* see TD_CTRL_xxx */
105 typedef struct UHCI_QH
{
110 static void uhci_async_cancel(UHCIAsync
*async
);
111 static void uhci_queue_fill(UHCIQueue
*q
, UHCI_TD
*td
);
112 static void uhci_resume(void *opaque
);
114 static inline int32_t uhci_queue_token(UHCI_TD
*td
)
116 if ((td
->token
& (0xf << 15)) == 0) {
117 /* ctrl ep, cover ep and dev, not pid! */
118 return td
->token
& 0x7ff00;
120 /* covers ep, dev, pid -> identifies the endpoint */
121 return td
->token
& 0x7ffff;
125 static UHCIQueue
*uhci_queue_new(UHCIState
*s
, uint32_t qh_addr
, UHCI_TD
*td
,
130 queue
= g_new0(UHCIQueue
, 1);
132 queue
->qh_addr
= qh_addr
;
133 queue
->token
= uhci_queue_token(td
);
135 QTAILQ_INIT(&queue
->asyncs
);
136 QTAILQ_INSERT_HEAD(&s
->queues
, queue
, next
);
137 queue
->valid
= QH_VALID
;
138 trace_usb_uhci_queue_add(queue
->token
);
142 static void uhci_queue_free(UHCIQueue
*queue
, const char *reason
)
144 UHCIState
*s
= queue
->uhci
;
147 while (!QTAILQ_EMPTY(&queue
->asyncs
)) {
148 async
= QTAILQ_FIRST(&queue
->asyncs
);
149 uhci_async_cancel(async
);
151 usb_device_ep_stopped(queue
->ep
->dev
, queue
->ep
);
153 trace_usb_uhci_queue_del(queue
->token
, reason
);
154 QTAILQ_REMOVE(&s
->queues
, queue
, next
);
158 static UHCIQueue
*uhci_queue_find(UHCIState
*s
, UHCI_TD
*td
)
160 uint32_t token
= uhci_queue_token(td
);
163 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
164 if (queue
->token
== token
) {
171 static bool uhci_queue_verify(UHCIQueue
*queue
, uint32_t qh_addr
, UHCI_TD
*td
,
172 uint32_t td_addr
, bool queuing
)
174 UHCIAsync
*first
= QTAILQ_FIRST(&queue
->asyncs
);
175 uint32_t queue_token_addr
= (queue
->token
>> 8) & 0x7f;
177 return queue
->qh_addr
== qh_addr
&&
178 queue
->token
== uhci_queue_token(td
) &&
179 queue_token_addr
== queue
->ep
->dev
->addr
&&
180 (queuing
|| !(td
->ctrl
& TD_CTRL_ACTIVE
) || first
== NULL
||
181 first
->td_addr
== td_addr
);
184 static UHCIAsync
*uhci_async_alloc(UHCIQueue
*queue
, uint32_t td_addr
)
186 UHCIAsync
*async
= g_new0(UHCIAsync
, 1);
188 async
->queue
= queue
;
189 async
->td_addr
= td_addr
;
190 usb_packet_init(&async
->packet
);
191 trace_usb_uhci_packet_add(async
->queue
->token
, async
->td_addr
);
196 static void uhci_async_free(UHCIAsync
*async
)
198 trace_usb_uhci_packet_del(async
->queue
->token
, async
->td_addr
);
199 usb_packet_cleanup(&async
->packet
);
200 if (async
->buf
!= async
->static_buf
) {
206 static void uhci_async_link(UHCIAsync
*async
)
208 UHCIQueue
*queue
= async
->queue
;
209 QTAILQ_INSERT_TAIL(&queue
->asyncs
, async
, next
);
210 trace_usb_uhci_packet_link_async(async
->queue
->token
, async
->td_addr
);
213 static void uhci_async_unlink(UHCIAsync
*async
)
215 UHCIQueue
*queue
= async
->queue
;
216 QTAILQ_REMOVE(&queue
->asyncs
, async
, next
);
217 trace_usb_uhci_packet_unlink_async(async
->queue
->token
, async
->td_addr
);
220 static void uhci_async_cancel(UHCIAsync
*async
)
222 uhci_async_unlink(async
);
223 trace_usb_uhci_packet_cancel(async
->queue
->token
, async
->td_addr
,
226 usb_cancel_packet(&async
->packet
);
227 uhci_async_free(async
);
231 * Mark all outstanding async packets as invalid.
232 * This is used for canceling them when TDs are removed by the HCD.
234 static void uhci_async_validate_begin(UHCIState
*s
)
238 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
244 * Cancel async packets that are no longer valid
246 static void uhci_async_validate_end(UHCIState
*s
)
248 UHCIQueue
*queue
, *n
;
250 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, n
) {
252 uhci_queue_free(queue
, "validate-end");
257 static void uhci_async_cancel_device(UHCIState
*s
, USBDevice
*dev
)
259 UHCIQueue
*queue
, *n
;
261 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, n
) {
262 if (queue
->ep
->dev
== dev
) {
263 uhci_queue_free(queue
, "cancel-device");
268 static void uhci_async_cancel_all(UHCIState
*s
)
270 UHCIQueue
*queue
, *nq
;
272 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, nq
) {
273 uhci_queue_free(queue
, "cancel-all");
277 static UHCIAsync
*uhci_async_find_td(UHCIState
*s
, uint32_t td_addr
)
282 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
283 QTAILQ_FOREACH(async
, &queue
->asyncs
, next
) {
284 if (async
->td_addr
== td_addr
) {
292 static void uhci_update_irq(UHCIState
*s
)
295 if (((s
->status2
& 1) && (s
->intr
& (1 << 2))) ||
296 ((s
->status2
& 2) && (s
->intr
& (1 << 3))) ||
297 ((s
->status
& UHCI_STS_USBERR
) && (s
->intr
& (1 << 0))) ||
298 ((s
->status
& UHCI_STS_RD
) && (s
->intr
& (1 << 1))) ||
299 (s
->status
& UHCI_STS_HSERR
) ||
300 (s
->status
& UHCI_STS_HCPERR
)) {
303 qemu_set_irq(s
->irq
, level
);
306 static void uhci_reset(DeviceState
*dev
)
308 PCIDevice
*d
= PCI_DEVICE(dev
);
309 UHCIState
*s
= UHCI(d
);
314 trace_usb_uhci_reset();
316 pci_conf
= s
->dev
.config
;
318 pci_conf
[0x6a] = 0x01; /* usb clock */
319 pci_conf
[0x6b] = 0x00;
321 s
->status
= UHCI_STS_HCHALTED
;
327 for(i
= 0; i
< NB_PORTS
; i
++) {
330 if (port
->port
.dev
&& port
->port
.dev
->attached
) {
331 usb_port_reset(&port
->port
);
335 uhci_async_cancel_all(s
);
336 qemu_bh_cancel(s
->bh
);
340 static const VMStateDescription vmstate_uhci_port
= {
343 .minimum_version_id
= 1,
344 .fields
= (VMStateField
[]) {
345 VMSTATE_UINT16(ctrl
, UHCIPort
),
346 VMSTATE_END_OF_LIST()
350 static int uhci_post_load(void *opaque
, int version_id
)
352 UHCIState
*s
= opaque
;
354 if (version_id
< 2) {
355 s
->expire_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
356 (NANOSECONDS_PER_SECOND
/ FRAME_TIMER_FREQ
);
361 static const VMStateDescription vmstate_uhci
= {
364 .minimum_version_id
= 1,
365 .post_load
= uhci_post_load
,
366 .fields
= (VMStateField
[]) {
367 VMSTATE_PCI_DEVICE(dev
, UHCIState
),
368 VMSTATE_UINT8_EQUAL(num_ports_vmstate
, UHCIState
, NULL
),
369 VMSTATE_STRUCT_ARRAY(ports
, UHCIState
, NB_PORTS
, 1,
370 vmstate_uhci_port
, UHCIPort
),
371 VMSTATE_UINT16(cmd
, UHCIState
),
372 VMSTATE_UINT16(status
, UHCIState
),
373 VMSTATE_UINT16(intr
, UHCIState
),
374 VMSTATE_UINT16(frnum
, UHCIState
),
375 VMSTATE_UINT32(fl_base_addr
, UHCIState
),
376 VMSTATE_UINT8(sof_timing
, UHCIState
),
377 VMSTATE_UINT8(status2
, UHCIState
),
378 VMSTATE_TIMER_PTR(frame_timer
, UHCIState
),
379 VMSTATE_INT64_V(expire_time
, UHCIState
, 2),
380 VMSTATE_UINT32_V(pending_int_mask
, UHCIState
, 3),
381 VMSTATE_END_OF_LIST()
385 static void uhci_port_write(void *opaque
, hwaddr addr
,
386 uint64_t val
, unsigned size
)
388 UHCIState
*s
= opaque
;
390 trace_usb_uhci_mmio_writew(addr
, val
);
394 if ((val
& UHCI_CMD_RS
) && !(s
->cmd
& UHCI_CMD_RS
)) {
395 /* start frame processing */
396 trace_usb_uhci_schedule_start();
397 s
->expire_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
398 (NANOSECONDS_PER_SECOND
/ FRAME_TIMER_FREQ
);
399 timer_mod(s
->frame_timer
, s
->expire_time
);
400 s
->status
&= ~UHCI_STS_HCHALTED
;
401 } else if (!(val
& UHCI_CMD_RS
)) {
402 s
->status
|= UHCI_STS_HCHALTED
;
404 if (val
& UHCI_CMD_GRESET
) {
408 /* send reset on the USB bus */
409 for(i
= 0; i
< NB_PORTS
; i
++) {
411 usb_device_reset(port
->port
.dev
);
413 uhci_reset(DEVICE(s
));
416 if (val
& UHCI_CMD_HCRESET
) {
417 uhci_reset(DEVICE(s
));
421 if (val
& UHCI_CMD_EGSM
) {
422 if ((s
->ports
[0].ctrl
& UHCI_PORT_RD
) ||
423 (s
->ports
[1].ctrl
& UHCI_PORT_RD
)) {
430 /* XXX: the chip spec is not coherent, so we add a hidden
431 register to distinguish between IOC and SPD */
432 if (val
& UHCI_STS_USBINT
)
441 if (s
->status
& UHCI_STS_HCHALTED
)
442 s
->frnum
= val
& 0x7ff;
445 s
->fl_base_addr
&= 0xffff0000;
446 s
->fl_base_addr
|= val
& ~0xfff;
449 s
->fl_base_addr
&= 0x0000ffff;
450 s
->fl_base_addr
|= (val
<< 16);
453 s
->sof_timing
= val
& 0xff;
465 dev
= port
->port
.dev
;
466 if (dev
&& dev
->attached
) {
468 if ( (val
& UHCI_PORT_RESET
) &&
469 !(port
->ctrl
& UHCI_PORT_RESET
) ) {
470 usb_device_reset(dev
);
473 port
->ctrl
&= UHCI_PORT_READ_ONLY
;
474 /* enabled may only be set if a device is connected */
475 if (!(port
->ctrl
& UHCI_PORT_CCS
)) {
476 val
&= ~UHCI_PORT_EN
;
478 port
->ctrl
|= (val
& ~UHCI_PORT_READ_ONLY
);
479 /* some bits are reset when a '1' is written to them */
480 port
->ctrl
&= ~(val
& UHCI_PORT_WRITE_CLEAR
);
486 static uint64_t uhci_port_read(void *opaque
, hwaddr addr
, unsigned size
)
488 UHCIState
*s
= opaque
;
505 val
= s
->fl_base_addr
& 0xffff;
508 val
= (s
->fl_base_addr
>> 16) & 0xffff;
526 val
= 0xff7f; /* disabled port */
530 trace_usb_uhci_mmio_readw(addr
, val
);
535 /* signal resume if controller suspended */
536 static void uhci_resume (void *opaque
)
538 UHCIState
*s
= (UHCIState
*)opaque
;
543 if (s
->cmd
& UHCI_CMD_EGSM
) {
544 s
->cmd
|= UHCI_CMD_FGR
;
545 s
->status
|= UHCI_STS_RD
;
550 static void uhci_attach(USBPort
*port1
)
552 UHCIState
*s
= port1
->opaque
;
553 UHCIPort
*port
= &s
->ports
[port1
->index
];
555 /* set connect status */
556 port
->ctrl
|= UHCI_PORT_CCS
| UHCI_PORT_CSC
;
559 if (port
->port
.dev
->speed
== USB_SPEED_LOW
) {
560 port
->ctrl
|= UHCI_PORT_LSDA
;
562 port
->ctrl
&= ~UHCI_PORT_LSDA
;
568 static void uhci_detach(USBPort
*port1
)
570 UHCIState
*s
= port1
->opaque
;
571 UHCIPort
*port
= &s
->ports
[port1
->index
];
573 uhci_async_cancel_device(s
, port1
->dev
);
575 /* set connect status */
576 if (port
->ctrl
& UHCI_PORT_CCS
) {
577 port
->ctrl
&= ~UHCI_PORT_CCS
;
578 port
->ctrl
|= UHCI_PORT_CSC
;
581 if (port
->ctrl
& UHCI_PORT_EN
) {
582 port
->ctrl
&= ~UHCI_PORT_EN
;
583 port
->ctrl
|= UHCI_PORT_ENC
;
589 static void uhci_child_detach(USBPort
*port1
, USBDevice
*child
)
591 UHCIState
*s
= port1
->opaque
;
593 uhci_async_cancel_device(s
, child
);
596 static void uhci_wakeup(USBPort
*port1
)
598 UHCIState
*s
= port1
->opaque
;
599 UHCIPort
*port
= &s
->ports
[port1
->index
];
601 if (port
->ctrl
& UHCI_PORT_SUSPEND
&& !(port
->ctrl
& UHCI_PORT_RD
)) {
602 port
->ctrl
|= UHCI_PORT_RD
;
607 static USBDevice
*uhci_find_device(UHCIState
*s
, uint8_t addr
)
612 for (i
= 0; i
< NB_PORTS
; i
++) {
613 UHCIPort
*port
= &s
->ports
[i
];
614 if (!(port
->ctrl
& UHCI_PORT_EN
)) {
617 dev
= usb_find_device(&port
->port
, addr
);
625 static void uhci_read_td(UHCIState
*s
, UHCI_TD
*td
, uint32_t link
)
627 pci_dma_read(&s
->dev
, link
& ~0xf, td
, sizeof(*td
));
628 le32_to_cpus(&td
->link
);
629 le32_to_cpus(&td
->ctrl
);
630 le32_to_cpus(&td
->token
);
631 le32_to_cpus(&td
->buffer
);
634 static int uhci_handle_td_error(UHCIState
*s
, UHCI_TD
*td
, uint32_t td_addr
,
635 int status
, uint32_t *int_mask
)
637 uint32_t queue_token
= uhci_queue_token(td
);
642 td
->ctrl
|= TD_CTRL_NAK
;
643 return TD_RESULT_NEXT_QH
;
646 td
->ctrl
|= TD_CTRL_STALL
;
647 trace_usb_uhci_packet_complete_stall(queue_token
, td_addr
);
648 ret
= TD_RESULT_NEXT_QH
;
652 td
->ctrl
|= TD_CTRL_BABBLE
| TD_CTRL_STALL
;
653 /* frame interrupted */
654 trace_usb_uhci_packet_complete_babble(queue_token
, td_addr
);
655 ret
= TD_RESULT_STOP_FRAME
;
658 case USB_RET_IOERROR
:
661 td
->ctrl
|= TD_CTRL_TIMEOUT
;
662 td
->ctrl
&= ~(3 << TD_CTRL_ERROR_SHIFT
);
663 trace_usb_uhci_packet_complete_error(queue_token
, td_addr
);
664 ret
= TD_RESULT_NEXT_QH
;
668 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
669 s
->status
|= UHCI_STS_USBERR
;
670 if (td
->ctrl
& TD_CTRL_IOC
) {
677 static int uhci_complete_td(UHCIState
*s
, UHCI_TD
*td
, UHCIAsync
*async
, uint32_t *int_mask
)
679 int len
= 0, max_len
;
682 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
683 pid
= td
->token
& 0xff;
685 if (td
->ctrl
& TD_CTRL_IOS
)
686 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
688 if (async
->packet
.status
!= USB_RET_SUCCESS
) {
689 return uhci_handle_td_error(s
, td
, async
->td_addr
,
690 async
->packet
.status
, int_mask
);
693 len
= async
->packet
.actual_length
;
694 td
->ctrl
= (td
->ctrl
& ~0x7ff) | ((len
- 1) & 0x7ff);
696 /* The NAK bit may have been set by a previous frame, so clear it
697 here. The docs are somewhat unclear, but win2k relies on this
699 td
->ctrl
&= ~(TD_CTRL_ACTIVE
| TD_CTRL_NAK
);
700 if (td
->ctrl
& TD_CTRL_IOC
)
703 if (pid
== USB_TOKEN_IN
) {
704 pci_dma_write(&s
->dev
, td
->buffer
, async
->buf
, len
);
705 if ((td
->ctrl
& TD_CTRL_SPD
) && len
< max_len
) {
707 /* short packet: do not update QH */
708 trace_usb_uhci_packet_complete_shortxfer(async
->queue
->token
,
710 return TD_RESULT_NEXT_QH
;
715 trace_usb_uhci_packet_complete_success(async
->queue
->token
,
717 return TD_RESULT_COMPLETE
;
720 static int uhci_handle_td(UHCIState
*s
, UHCIQueue
*q
, uint32_t qh_addr
,
721 UHCI_TD
*td
, uint32_t td_addr
, uint32_t *int_mask
)
725 bool queuing
= (q
!= NULL
);
726 uint8_t pid
= td
->token
& 0xff;
729 async
= uhci_async_find_td(s
, td_addr
);
731 if (uhci_queue_verify(async
->queue
, qh_addr
, td
, td_addr
, queuing
)) {
732 assert(q
== NULL
|| q
== async
->queue
);
735 uhci_queue_free(async
->queue
, "guest re-used pending td");
741 q
= uhci_queue_find(s
, td
);
742 if (q
&& !uhci_queue_verify(q
, qh_addr
, td
, td_addr
, queuing
)) {
743 uhci_queue_free(q
, "guest re-used qh");
753 if (!(td
->ctrl
& TD_CTRL_ACTIVE
)) {
755 /* Guest marked a pending td non-active, cancel the queue */
756 uhci_queue_free(async
->queue
, "pending td non-active");
759 * ehci11d spec page 22: "Even if the Active bit in the TD is already
760 * cleared when the TD is fetched ... an IOC interrupt is generated"
762 if (td
->ctrl
& TD_CTRL_IOC
) {
765 return TD_RESULT_NEXT_QH
;
770 case USB_TOKEN_SETUP
:
774 /* invalid pid : frame interrupted */
775 s
->status
|= UHCI_STS_HCPERR
;
776 s
->cmd
&= ~UHCI_CMD_RS
;
778 return TD_RESULT_STOP_FRAME
;
783 /* we are busy filling the queue, we are not prepared
784 to consume completed packages then, just leave them
786 return TD_RESULT_ASYNC_CONT
;
790 UHCIAsync
*last
= QTAILQ_LAST(&async
->queue
->asyncs
);
792 * While we are waiting for the current td to complete, the guest
793 * may have added more tds to the queue. Note we re-read the td
794 * rather then caching it, as we want to see guest made changes!
796 uhci_read_td(s
, &last_td
, last
->td_addr
);
797 uhci_queue_fill(async
->queue
, &last_td
);
799 return TD_RESULT_ASYNC_CONT
;
801 uhci_async_unlink(async
);
805 if (s
->completions_only
) {
806 return TD_RESULT_ASYNC_CONT
;
809 /* Allocate new packet */
814 dev
= uhci_find_device(s
, (td
->token
>> 8) & 0x7f);
816 return uhci_handle_td_error(s
, td
, td_addr
, USB_RET_NODEV
,
819 ep
= usb_ep_get(dev
, pid
, (td
->token
>> 15) & 0xf);
820 q
= uhci_queue_new(s
, qh_addr
, td
, ep
);
822 async
= uhci_async_alloc(q
, td_addr
);
824 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
825 spd
= (pid
== USB_TOKEN_IN
&& (td
->ctrl
& TD_CTRL_SPD
) != 0);
826 usb_packet_setup(&async
->packet
, pid
, q
->ep
, 0, td_addr
, spd
,
827 (td
->ctrl
& TD_CTRL_IOC
) != 0);
828 if (max_len
<= sizeof(async
->static_buf
)) {
829 async
->buf
= async
->static_buf
;
831 async
->buf
= g_malloc(max_len
);
833 usb_packet_addbuf(&async
->packet
, async
->buf
, max_len
);
837 case USB_TOKEN_SETUP
:
838 pci_dma_read(&s
->dev
, td
->buffer
, async
->buf
, max_len
);
839 usb_handle_packet(q
->ep
->dev
, &async
->packet
);
840 if (async
->packet
.status
== USB_RET_SUCCESS
) {
841 async
->packet
.actual_length
= max_len
;
846 usb_handle_packet(q
->ep
->dev
, &async
->packet
);
850 abort(); /* Never to execute */
853 if (async
->packet
.status
== USB_RET_ASYNC
) {
854 uhci_async_link(async
);
856 uhci_queue_fill(q
, td
);
858 return TD_RESULT_ASYNC_START
;
862 ret
= uhci_complete_td(s
, td
, async
, int_mask
);
863 uhci_async_free(async
);
867 static void uhci_async_complete(USBPort
*port
, USBPacket
*packet
)
869 UHCIAsync
*async
= container_of(packet
, UHCIAsync
, packet
);
870 UHCIState
*s
= async
->queue
->uhci
;
872 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
873 uhci_async_cancel(async
);
878 /* Force processing of this packet *now*, needed for migration */
879 s
->completions_only
= true;
880 qemu_bh_schedule(s
->bh
);
883 static int is_valid(uint32_t link
)
885 return (link
& 1) == 0;
888 static int is_qh(uint32_t link
)
890 return (link
& 2) != 0;
893 static int depth_first(uint32_t link
)
895 return (link
& 4) != 0;
898 /* QH DB used for detecting QH loops */
899 #define UHCI_MAX_QUEUES 128
901 uint32_t addr
[UHCI_MAX_QUEUES
];
905 static void qhdb_reset(QhDb
*db
)
910 /* Add QH to DB. Returns 1 if already present or DB is full. */
911 static int qhdb_insert(QhDb
*db
, uint32_t addr
)
914 for (i
= 0; i
< db
->count
; i
++)
915 if (db
->addr
[i
] == addr
)
918 if (db
->count
>= UHCI_MAX_QUEUES
)
921 db
->addr
[db
->count
++] = addr
;
925 static void uhci_queue_fill(UHCIQueue
*q
, UHCI_TD
*td
)
927 uint32_t int_mask
= 0;
928 uint32_t plink
= td
->link
;
932 while (is_valid(plink
)) {
933 uhci_read_td(q
->uhci
, &ptd
, plink
);
934 if (!(ptd
.ctrl
& TD_CTRL_ACTIVE
)) {
937 if (uhci_queue_token(&ptd
) != q
->token
) {
940 trace_usb_uhci_td_queue(plink
& ~0xf, ptd
.ctrl
, ptd
.token
);
941 ret
= uhci_handle_td(q
->uhci
, q
, q
->qh_addr
, &ptd
, plink
, &int_mask
);
942 if (ret
== TD_RESULT_ASYNC_CONT
) {
945 assert(ret
== TD_RESULT_ASYNC_START
);
946 assert(int_mask
== 0);
949 usb_device_flush_ep_queue(q
->ep
->dev
, q
->ep
);
952 static void uhci_process_frame(UHCIState
*s
)
954 uint32_t frame_addr
, link
, old_td_ctrl
, val
, int_mask
;
955 uint32_t curr_qh
, td_count
= 0;
961 frame_addr
= s
->fl_base_addr
+ ((s
->frnum
& 0x3ff) << 2);
963 pci_dma_read(&s
->dev
, frame_addr
, &link
, 4);
971 for (cnt
= FRAME_MAX_LOOPS
; is_valid(link
) && cnt
; cnt
--) {
972 if (!s
->completions_only
&& s
->frame_bytes
>= s
->frame_bandwidth
) {
973 /* We've reached the usb 1.1 bandwidth, which is
974 1280 bytes/frame, stop processing */
975 trace_usb_uhci_frame_stop_bandwidth();
980 trace_usb_uhci_qh_load(link
& ~0xf);
982 if (qhdb_insert(&qhdb
, link
)) {
984 * We're going in circles. Which is not a bug because
985 * HCD is allowed to do that as part of the BW management.
987 * Stop processing here if no transaction has been done
988 * since we've been here last time.
991 trace_usb_uhci_frame_loop_stop_idle();
994 trace_usb_uhci_frame_loop_continue();
997 qhdb_insert(&qhdb
, link
);
1001 pci_dma_read(&s
->dev
, link
& ~0xf, &qh
, sizeof(qh
));
1002 le32_to_cpus(&qh
.link
);
1003 le32_to_cpus(&qh
.el_link
);
1005 if (!is_valid(qh
.el_link
)) {
1006 /* QH w/o elements */
1010 /* QH with elements */
1018 uhci_read_td(s
, &td
, link
);
1019 trace_usb_uhci_td_load(curr_qh
& ~0xf, link
& ~0xf, td
.ctrl
, td
.token
);
1021 old_td_ctrl
= td
.ctrl
;
1022 ret
= uhci_handle_td(s
, NULL
, curr_qh
, &td
, link
, &int_mask
);
1023 if (old_td_ctrl
!= td
.ctrl
) {
1024 /* update the status bits of the TD */
1025 val
= cpu_to_le32(td
.ctrl
);
1026 pci_dma_write(&s
->dev
, (link
& ~0xf) + 4, &val
, sizeof(val
));
1030 case TD_RESULT_STOP_FRAME
: /* interrupted frame */
1033 case TD_RESULT_NEXT_QH
:
1034 case TD_RESULT_ASYNC_CONT
:
1035 trace_usb_uhci_td_nextqh(curr_qh
& ~0xf, link
& ~0xf);
1036 link
= curr_qh
? qh
.link
: td
.link
;
1039 case TD_RESULT_ASYNC_START
:
1040 trace_usb_uhci_td_async(curr_qh
& ~0xf, link
& ~0xf);
1041 link
= curr_qh
? qh
.link
: td
.link
;
1044 case TD_RESULT_COMPLETE
:
1045 trace_usb_uhci_td_complete(curr_qh
& ~0xf, link
& ~0xf);
1048 s
->frame_bytes
+= (td
.ctrl
& 0x7ff) + 1;
1051 /* update QH element link */
1053 val
= cpu_to_le32(qh
.el_link
);
1054 pci_dma_write(&s
->dev
, (curr_qh
& ~0xf) + 4, &val
, sizeof(val
));
1056 if (!depth_first(link
)) {
1057 /* done with this QH */
1065 assert(!"unknown return code");
1068 /* go to the next entry */
1072 s
->pending_int_mask
|= int_mask
;
1075 static void uhci_bh(void *opaque
)
1077 UHCIState
*s
= opaque
;
1078 uhci_process_frame(s
);
1081 static void uhci_frame_timer(void *opaque
)
1083 UHCIState
*s
= opaque
;
1084 uint64_t t_now
, t_last_run
;
1086 const uint64_t frame_t
= NANOSECONDS_PER_SECOND
/ FRAME_TIMER_FREQ
;
1088 s
->completions_only
= false;
1089 qemu_bh_cancel(s
->bh
);
1091 if (!(s
->cmd
& UHCI_CMD_RS
)) {
1093 trace_usb_uhci_schedule_stop();
1094 timer_del(s
->frame_timer
);
1095 uhci_async_cancel_all(s
);
1096 /* set hchalted bit in status - UHCI11D 2.1.2 */
1097 s
->status
|= UHCI_STS_HCHALTED
;
1101 /* We still store expire_time in our state, for migration */
1102 t_last_run
= s
->expire_time
- frame_t
;
1103 t_now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1105 /* Process up to MAX_FRAMES_PER_TICK frames */
1106 frames
= (t_now
- t_last_run
) / frame_t
;
1107 if (frames
> s
->maxframes
) {
1108 int skipped
= frames
- s
->maxframes
;
1109 s
->expire_time
+= skipped
* frame_t
;
1110 s
->frnum
= (s
->frnum
+ skipped
) & 0x7ff;
1113 if (frames
> MAX_FRAMES_PER_TICK
) {
1114 frames
= MAX_FRAMES_PER_TICK
;
1117 for (i
= 0; i
< frames
; i
++) {
1119 trace_usb_uhci_frame_start(s
->frnum
);
1120 uhci_async_validate_begin(s
);
1121 uhci_process_frame(s
);
1122 uhci_async_validate_end(s
);
1123 /* The spec says frnum is the frame currently being processed, and
1124 * the guest must look at frnum - 1 on interrupt, so inc frnum now */
1125 s
->frnum
= (s
->frnum
+ 1) & 0x7ff;
1126 s
->expire_time
+= frame_t
;
1129 /* Complete the previous frame(s) */
1130 if (s
->pending_int_mask
) {
1131 s
->status2
|= s
->pending_int_mask
;
1132 s
->status
|= UHCI_STS_USBINT
;
1135 s
->pending_int_mask
= 0;
1137 timer_mod(s
->frame_timer
, t_now
+ frame_t
);
1140 static const MemoryRegionOps uhci_ioport_ops
= {
1141 .read
= uhci_port_read
,
1142 .write
= uhci_port_write
,
1143 .valid
.min_access_size
= 1,
1144 .valid
.max_access_size
= 4,
1145 .impl
.min_access_size
= 2,
1146 .impl
.max_access_size
= 2,
1147 .endianness
= DEVICE_LITTLE_ENDIAN
,
1150 static USBPortOps uhci_port_ops
= {
1151 .attach
= uhci_attach
,
1152 .detach
= uhci_detach
,
1153 .child_detach
= uhci_child_detach
,
1154 .wakeup
= uhci_wakeup
,
1155 .complete
= uhci_async_complete
,
1158 static USBBusOps uhci_bus_ops
= {
1161 void usb_uhci_common_realize(PCIDevice
*dev
, Error
**errp
)
1164 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1165 UHCIPCIDeviceClass
*u
= container_of(pc
, UHCIPCIDeviceClass
, parent_class
);
1166 UHCIState
*s
= UHCI(dev
);
1167 uint8_t *pci_conf
= s
->dev
.config
;
1170 pci_conf
[PCI_CLASS_PROG
] = 0x00;
1171 /* TODO: reset value should be 0. */
1172 pci_conf
[USB_SBRN
] = USB_RELEASE_1
; /* release number */
1173 pci_config_set_interrupt_pin(pci_conf
, u
->info
.irq_pin
+ 1);
1174 s
->irq
= pci_allocate_irq(dev
);
1177 USBPort
*ports
[NB_PORTS
];
1178 for(i
= 0; i
< NB_PORTS
; i
++) {
1179 ports
[i
] = &s
->ports
[i
].port
;
1181 usb_register_companion(s
->masterbus
, ports
, NB_PORTS
,
1182 s
->firstport
, s
, &uhci_port_ops
,
1183 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
,
1186 error_propagate(errp
, err
);
1190 usb_bus_new(&s
->bus
, sizeof(s
->bus
), &uhci_bus_ops
, DEVICE(dev
));
1191 for (i
= 0; i
< NB_PORTS
; i
++) {
1192 usb_register_port(&s
->bus
, &s
->ports
[i
].port
, s
, i
, &uhci_port_ops
,
1193 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
);
1196 s
->bh
= qemu_bh_new(uhci_bh
, s
);
1197 s
->frame_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, uhci_frame_timer
, s
);
1198 s
->num_ports_vmstate
= NB_PORTS
;
1199 QTAILQ_INIT(&s
->queues
);
1201 memory_region_init_io(&s
->io_bar
, OBJECT(s
), &uhci_ioport_ops
, s
,
1204 /* Use region 4 for consistency with real hardware. BSD guests seem
1206 pci_register_bar(&s
->dev
, 4, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io_bar
);
1209 static void usb_uhci_exit(PCIDevice
*dev
)
1211 UHCIState
*s
= UHCI(dev
);
1213 trace_usb_uhci_exit();
1215 if (s
->frame_timer
) {
1216 timer_free(s
->frame_timer
);
1217 s
->frame_timer
= NULL
;
1221 qemu_bh_delete(s
->bh
);
1224 uhci_async_cancel_all(s
);
1226 if (!s
->masterbus
) {
1227 usb_bus_release(&s
->bus
);
1231 static Property uhci_properties_companion
[] = {
1232 DEFINE_PROP_STRING("masterbus", UHCIState
, masterbus
),
1233 DEFINE_PROP_UINT32("firstport", UHCIState
, firstport
, 0),
1234 DEFINE_PROP_UINT32("bandwidth", UHCIState
, frame_bandwidth
, 1280),
1235 DEFINE_PROP_UINT32("maxframes", UHCIState
, maxframes
, 128),
1236 DEFINE_PROP_END_OF_LIST(),
1238 static Property uhci_properties_standalone
[] = {
1239 DEFINE_PROP_UINT32("bandwidth", UHCIState
, frame_bandwidth
, 1280),
1240 DEFINE_PROP_UINT32("maxframes", UHCIState
, maxframes
, 128),
1241 DEFINE_PROP_END_OF_LIST(),
1244 static void uhci_class_init(ObjectClass
*klass
, void *data
)
1246 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1247 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1249 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1250 dc
->vmsd
= &vmstate_uhci
;
1251 dc
->reset
= uhci_reset
;
1252 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
1255 static const TypeInfo uhci_pci_type_info
= {
1257 .parent
= TYPE_PCI_DEVICE
,
1258 .instance_size
= sizeof(UHCIState
),
1259 .class_size
= sizeof(UHCIPCIDeviceClass
),
1261 .class_init
= uhci_class_init
,
1262 .interfaces
= (InterfaceInfo
[]) {
1263 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
1268 void uhci_data_class_init(ObjectClass
*klass
, void *data
)
1270 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1271 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1272 UHCIPCIDeviceClass
*u
= container_of(k
, UHCIPCIDeviceClass
, parent_class
);
1273 UHCIInfo
*info
= data
;
1275 k
->realize
= info
->realize
? info
->realize
: usb_uhci_common_realize
;
1276 k
->exit
= info
->unplug
? usb_uhci_exit
: NULL
;
1277 k
->vendor_id
= info
->vendor_id
;
1278 k
->device_id
= info
->device_id
;
1279 k
->revision
= info
->revision
;
1280 if (!info
->unplug
) {
1281 /* uhci controllers in companion setups can't be hotplugged */
1282 dc
->hotpluggable
= false;
1283 device_class_set_props(dc
, uhci_properties_companion
);
1285 device_class_set_props(dc
, uhci_properties_standalone
);
1287 if (info
->notuser
) {
1288 dc
->user_creatable
= false;
1293 static UHCIInfo uhci_info
[] = {
1295 .name
= "piix3-usb-uhci",
1296 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1297 .device_id
= PCI_DEVICE_ID_INTEL_82371SB_2
,
1302 .name
= "piix4-usb-uhci",
1303 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1304 .device_id
= PCI_DEVICE_ID_INTEL_82371AB_2
,
1309 .name
= "ich9-usb-uhci1", /* 00:1d.0 */
1310 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1311 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI1
,
1316 .name
= "ich9-usb-uhci2", /* 00:1d.1 */
1317 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1318 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI2
,
1323 .name
= "ich9-usb-uhci3", /* 00:1d.2 */
1324 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1325 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI3
,
1330 .name
= "ich9-usb-uhci4", /* 00:1a.0 */
1331 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1332 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI4
,
1337 .name
= "ich9-usb-uhci5", /* 00:1a.1 */
1338 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1339 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI5
,
1344 .name
= "ich9-usb-uhci6", /* 00:1a.2 */
1345 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1346 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI6
,
1353 static void uhci_register_types(void)
1355 TypeInfo uhci_type_info
= {
1356 .parent
= TYPE_UHCI
,
1357 .class_init
= uhci_data_class_init
,
1361 type_register_static(&uhci_pci_type_info
);
1363 for (i
= 0; i
< ARRAY_SIZE(uhci_info
); i
++) {
1364 uhci_type_info
.name
= uhci_info
[i
].name
;
1365 uhci_type_info
.class_data
= uhci_info
+ i
;
1366 type_register(&uhci_type_info
);
1370 type_init(uhci_register_types
)