2 * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
4 * Copyright (c) 2014 Imagination Technologies
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
26 /* Data format min and max values */
27 #define DF_BITS(df) (1 << ((df) + 3))
29 #define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1)
30 #define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1)
32 #define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1)))
33 #define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1)))
35 #define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df)))
36 #define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m)))
38 #define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df))
39 #define SIGNED(x, df) \
40 ((((int64_t)x) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)))
42 /* Element-by-element access macros */
43 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
45 static inline void msa_move_v(wr_t
*pwd
, wr_t
*pws
)
49 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
50 pwd
->d
[i
] = pws
->d
[i
];
54 #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \
55 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
58 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
59 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
61 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
66 MSA_FN_IMM8(andi_b
, pwd
->b
[i
], pws
->b
[i
] & i8
)
67 MSA_FN_IMM8(ori_b
, pwd
->b
[i
], pws
->b
[i
] | i8
)
68 MSA_FN_IMM8(nori_b
, pwd
->b
[i
], ~(pws
->b
[i
] | i8
))
69 MSA_FN_IMM8(xori_b
, pwd
->b
[i
], pws
->b
[i
] ^ i8
)
71 #define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \
72 UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df)
73 MSA_FN_IMM8(bmnzi_b
, pwd
->b
[i
],
74 BIT_MOVE_IF_NOT_ZERO(pwd
->b
[i
], pws
->b
[i
], i8
, DF_BYTE
))
76 #define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \
77 UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df)
78 MSA_FN_IMM8(bmzi_b
, pwd
->b
[i
],
79 BIT_MOVE_IF_ZERO(pwd
->b
[i
], pws
->b
[i
], i8
, DF_BYTE
))
81 #define BIT_SELECT(dest, arg1, arg2, df) \
82 UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df)
83 MSA_FN_IMM8(bseli_b
, pwd
->b
[i
],
84 BIT_SELECT(pwd
->b
[i
], pws
->b
[i
], i8
, DF_BYTE
))
88 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
90 void helper_msa_shf_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
91 uint32_t ws
, uint32_t imm
)
93 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
94 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
100 for (i
= 0; i
< DF_ELEMENTS(DF_BYTE
); i
++) {
101 pwx
->b
[i
] = pws
->b
[SHF_POS(i
, imm
)];
105 for (i
= 0; i
< DF_ELEMENTS(DF_HALF
); i
++) {
106 pwx
->h
[i
] = pws
->h
[SHF_POS(i
, imm
)];
110 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
111 pwx
->w
[i
] = pws
->w
[SHF_POS(i
, imm
)];
117 msa_move_v(pwd
, pwx
);
120 #define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \
121 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
124 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
125 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
126 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
128 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
133 MSA_FN_VECTOR(and_v
, pwd
->d
[i
], pws
->d
[i
] & pwt
->d
[i
])
134 MSA_FN_VECTOR(or_v
, pwd
->d
[i
], pws
->d
[i
] | pwt
->d
[i
])
135 MSA_FN_VECTOR(nor_v
, pwd
->d
[i
], ~(pws
->d
[i
] | pwt
->d
[i
]))
136 MSA_FN_VECTOR(xor_v
, pwd
->d
[i
], pws
->d
[i
] ^ pwt
->d
[i
])
137 MSA_FN_VECTOR(bmnz_v
, pwd
->d
[i
],
138 BIT_MOVE_IF_NOT_ZERO(pwd
->d
[i
], pws
->d
[i
], pwt
->d
[i
], DF_DOUBLE
))
139 MSA_FN_VECTOR(bmz_v
, pwd
->d
[i
],
140 BIT_MOVE_IF_ZERO(pwd
->d
[i
], pws
->d
[i
], pwt
->d
[i
], DF_DOUBLE
))
141 MSA_FN_VECTOR(bsel_v
, pwd
->d
[i
],
142 BIT_SELECT(pwd
->d
[i
], pws
->d
[i
], pwt
->d
[i
], DF_DOUBLE
))
143 #undef BIT_MOVE_IF_NOT_ZERO
144 #undef BIT_MOVE_IF_ZERO
148 static inline int64_t msa_addv_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
153 static inline int64_t msa_subv_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
158 static inline int64_t msa_ceq_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
160 return arg1
== arg2
? -1 : 0;
163 static inline int64_t msa_cle_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
165 return arg1
<= arg2
? -1 : 0;
168 static inline int64_t msa_cle_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
170 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
171 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
172 return u_arg1
<= u_arg2
? -1 : 0;
175 static inline int64_t msa_clt_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
177 return arg1
< arg2
? -1 : 0;
180 static inline int64_t msa_clt_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
182 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
183 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
184 return u_arg1
< u_arg2
? -1 : 0;
187 static inline int64_t msa_max_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
189 return arg1
> arg2
? arg1
: arg2
;
192 static inline int64_t msa_max_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
194 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
195 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
196 return u_arg1
> u_arg2
? arg1
: arg2
;
199 static inline int64_t msa_min_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
201 return arg1
< arg2
? arg1
: arg2
;
204 static inline int64_t msa_min_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
206 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
207 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
208 return u_arg1
< u_arg2
? arg1
: arg2
;
211 #define MSA_BINOP_IMM_DF(helper, func) \
212 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
213 uint32_t wd, uint32_t ws, int32_t u5) \
215 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
216 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
221 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
222 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
226 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
227 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
231 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
232 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
236 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
237 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
245 MSA_BINOP_IMM_DF(addvi
, addv
)
246 MSA_BINOP_IMM_DF(subvi
, subv
)
247 MSA_BINOP_IMM_DF(ceqi
, ceq
)
248 MSA_BINOP_IMM_DF(clei_s
, cle_s
)
249 MSA_BINOP_IMM_DF(clei_u
, cle_u
)
250 MSA_BINOP_IMM_DF(clti_s
, clt_s
)
251 MSA_BINOP_IMM_DF(clti_u
, clt_u
)
252 MSA_BINOP_IMM_DF(maxi_s
, max_s
)
253 MSA_BINOP_IMM_DF(maxi_u
, max_u
)
254 MSA_BINOP_IMM_DF(mini_s
, min_s
)
255 MSA_BINOP_IMM_DF(mini_u
, min_u
)
256 #undef MSA_BINOP_IMM_DF
258 void helper_msa_ldi_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
261 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
266 for (i
= 0; i
< DF_ELEMENTS(DF_BYTE
); i
++) {
267 pwd
->b
[i
] = (int8_t)s10
;
271 for (i
= 0; i
< DF_ELEMENTS(DF_HALF
); i
++) {
272 pwd
->h
[i
] = (int16_t)s10
;
276 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
277 pwd
->w
[i
] = (int32_t)s10
;
281 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
282 pwd
->d
[i
] = (int64_t)s10
;
290 /* Data format bit position and unsigned values */
291 #define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df))
293 static inline int64_t msa_sll_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
295 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
296 return arg1
<< b_arg2
;
299 static inline int64_t msa_sra_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
301 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
302 return arg1
>> b_arg2
;
305 static inline int64_t msa_srl_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
307 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
308 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
309 return u_arg1
>> b_arg2
;
312 static inline int64_t msa_bclr_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
314 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
315 return UNSIGNED(arg1
& (~(1LL << b_arg2
)), df
);
318 static inline int64_t msa_bset_df(uint32_t df
, int64_t arg1
,
321 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
322 return UNSIGNED(arg1
| (1LL << b_arg2
), df
);
325 static inline int64_t msa_bneg_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
327 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
328 return UNSIGNED(arg1
^ (1LL << b_arg2
), df
);
331 static inline int64_t msa_binsl_df(uint32_t df
, int64_t dest
, int64_t arg1
,
334 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
335 uint64_t u_dest
= UNSIGNED(dest
, df
);
336 int32_t sh_d
= BIT_POSITION(arg2
, df
) + 1;
337 int32_t sh_a
= DF_BITS(df
) - sh_d
;
338 if (sh_d
== DF_BITS(df
)) {
341 return UNSIGNED(UNSIGNED(u_dest
<< sh_d
, df
) >> sh_d
, df
) |
342 UNSIGNED(UNSIGNED(u_arg1
>> sh_a
, df
) << sh_a
, df
);
346 static inline int64_t msa_binsr_df(uint32_t df
, int64_t dest
, int64_t arg1
,
349 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
350 uint64_t u_dest
= UNSIGNED(dest
, df
);
351 int32_t sh_d
= BIT_POSITION(arg2
, df
) + 1;
352 int32_t sh_a
= DF_BITS(df
) - sh_d
;
353 if (sh_d
== DF_BITS(df
)) {
356 return UNSIGNED(UNSIGNED(u_dest
>> sh_d
, df
) << sh_d
, df
) |
357 UNSIGNED(UNSIGNED(u_arg1
<< sh_a
, df
) >> sh_a
, df
);
361 static inline int64_t msa_sat_s_df(uint32_t df
, int64_t arg
, uint32_t m
)
363 return arg
< M_MIN_INT(m
+1) ? M_MIN_INT(m
+1) :
364 arg
> M_MAX_INT(m
+1) ? M_MAX_INT(m
+1) :
368 static inline int64_t msa_sat_u_df(uint32_t df
, int64_t arg
, uint32_t m
)
370 uint64_t u_arg
= UNSIGNED(arg
, df
);
371 return u_arg
< M_MAX_UINT(m
+1) ? u_arg
:
375 static inline int64_t msa_srar_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
377 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
381 int64_t r_bit
= (arg1
>> (b_arg2
- 1)) & 1;
382 return (arg1
>> b_arg2
) + r_bit
;
386 static inline int64_t msa_srlr_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
388 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
389 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
393 uint64_t r_bit
= (u_arg1
>> (b_arg2
- 1)) & 1;
394 return (u_arg1
>> b_arg2
) + r_bit
;
398 #define MSA_BINOP_IMMU_DF(helper, func) \
399 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
400 uint32_t ws, uint32_t u5) \
402 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
403 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
408 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
409 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
413 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
414 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
418 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
419 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
423 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
424 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
432 MSA_BINOP_IMMU_DF(slli
, sll
)
433 MSA_BINOP_IMMU_DF(srai
, sra
)
434 MSA_BINOP_IMMU_DF(srli
, srl
)
435 MSA_BINOP_IMMU_DF(bclri
, bclr
)
436 MSA_BINOP_IMMU_DF(bseti
, bset
)
437 MSA_BINOP_IMMU_DF(bnegi
, bneg
)
438 MSA_BINOP_IMMU_DF(sat_s
, sat_s
)
439 MSA_BINOP_IMMU_DF(sat_u
, sat_u
)
440 MSA_BINOP_IMMU_DF(srari
, srar
)
441 MSA_BINOP_IMMU_DF(srlri
, srlr
)
442 #undef MSA_BINOP_IMMU_DF
444 #define MSA_TEROP_IMMU_DF(helper, func) \
445 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
446 uint32_t wd, uint32_t ws, uint32_t u5) \
448 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
449 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
454 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
455 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
460 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
461 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
466 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
467 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
472 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
473 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
482 MSA_TEROP_IMMU_DF(binsli
, binsl
)
483 MSA_TEROP_IMMU_DF(binsri
, binsr
)
484 #undef MSA_TEROP_IMMU_DF
486 static inline int64_t msa_max_a_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
488 uint64_t abs_arg1
= arg1
>= 0 ? arg1
: -arg1
;
489 uint64_t abs_arg2
= arg2
>= 0 ? arg2
: -arg2
;
490 return abs_arg1
> abs_arg2
? arg1
: arg2
;
493 static inline int64_t msa_min_a_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
495 uint64_t abs_arg1
= arg1
>= 0 ? arg1
: -arg1
;
496 uint64_t abs_arg2
= arg2
>= 0 ? arg2
: -arg2
;
497 return abs_arg1
< abs_arg2
? arg1
: arg2
;
500 static inline int64_t msa_add_a_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
502 uint64_t abs_arg1
= arg1
>= 0 ? arg1
: -arg1
;
503 uint64_t abs_arg2
= arg2
>= 0 ? arg2
: -arg2
;
504 return abs_arg1
+ abs_arg2
;
507 static inline int64_t msa_adds_a_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
509 uint64_t max_int
= (uint64_t)DF_MAX_INT(df
);
510 uint64_t abs_arg1
= arg1
>= 0 ? arg1
: -arg1
;
511 uint64_t abs_arg2
= arg2
>= 0 ? arg2
: -arg2
;
512 if (abs_arg1
> max_int
|| abs_arg2
> max_int
) {
513 return (int64_t)max_int
;
515 return (abs_arg1
< max_int
- abs_arg2
) ? abs_arg1
+ abs_arg2
: max_int
;
519 static inline int64_t msa_adds_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
521 int64_t max_int
= DF_MAX_INT(df
);
522 int64_t min_int
= DF_MIN_INT(df
);
524 return (min_int
- arg1
< arg2
) ? arg1
+ arg2
: min_int
;
526 return (arg2
< max_int
- arg1
) ? arg1
+ arg2
: max_int
;
530 static inline uint64_t msa_adds_u_df(uint32_t df
, uint64_t arg1
, uint64_t arg2
)
532 uint64_t max_uint
= DF_MAX_UINT(df
);
533 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
534 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
535 return (u_arg1
< max_uint
- u_arg2
) ? u_arg1
+ u_arg2
: max_uint
;
538 static inline int64_t msa_ave_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
541 return (arg1
>> 1) + (arg2
>> 1) + (arg1
& arg2
& 1);
544 static inline uint64_t msa_ave_u_df(uint32_t df
, uint64_t arg1
, uint64_t arg2
)
546 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
547 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
549 return (u_arg1
>> 1) + (u_arg2
>> 1) + (u_arg1
& u_arg2
& 1);
552 static inline int64_t msa_aver_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
555 return (arg1
>> 1) + (arg2
>> 1) + ((arg1
| arg2
) & 1);
558 static inline uint64_t msa_aver_u_df(uint32_t df
, uint64_t arg1
, uint64_t arg2
)
560 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
561 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
563 return (u_arg1
>> 1) + (u_arg2
>> 1) + ((u_arg1
| u_arg2
) & 1);
566 static inline int64_t msa_subs_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
568 int64_t max_int
= DF_MAX_INT(df
);
569 int64_t min_int
= DF_MIN_INT(df
);
571 return (min_int
+ arg2
< arg1
) ? arg1
- arg2
: min_int
;
573 return (arg1
< max_int
+ arg2
) ? arg1
- arg2
: max_int
;
577 static inline int64_t msa_subs_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
579 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
580 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
581 return (u_arg1
> u_arg2
) ? u_arg1
- u_arg2
: 0;
584 static inline int64_t msa_subsus_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
586 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
587 uint64_t max_uint
= DF_MAX_UINT(df
);
589 uint64_t u_arg2
= (uint64_t)arg2
;
590 return (u_arg1
> u_arg2
) ?
591 (int64_t)(u_arg1
- u_arg2
) :
594 uint64_t u_arg2
= (uint64_t)(-arg2
);
595 return (u_arg1
< max_uint
- u_arg2
) ?
596 (int64_t)(u_arg1
+ u_arg2
) :
601 static inline int64_t msa_subsuu_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
603 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
604 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
605 int64_t max_int
= DF_MAX_INT(df
);
606 int64_t min_int
= DF_MIN_INT(df
);
607 if (u_arg1
> u_arg2
) {
608 return u_arg1
- u_arg2
< (uint64_t)max_int
?
609 (int64_t)(u_arg1
- u_arg2
) :
612 return u_arg2
- u_arg1
< (uint64_t)(-min_int
) ?
613 (int64_t)(u_arg1
- u_arg2
) :
618 static inline int64_t msa_asub_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
621 return (arg1
< arg2
) ?
622 (uint64_t)(arg2
- arg1
) : (uint64_t)(arg1
- arg2
);
625 static inline uint64_t msa_asub_u_df(uint32_t df
, uint64_t arg1
, uint64_t arg2
)
627 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
628 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
629 /* unsigned compare */
630 return (u_arg1
< u_arg2
) ?
631 (uint64_t)(u_arg2
- u_arg1
) : (uint64_t)(u_arg1
- u_arg2
);
634 static inline int64_t msa_mulv_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
639 static inline int64_t msa_div_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
641 if (arg1
== DF_MIN_INT(df
) && arg2
== -1) {
642 return DF_MIN_INT(df
);
644 return arg2
? arg1
/ arg2
: 0;
647 static inline int64_t msa_div_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
649 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
650 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
651 return u_arg2
? u_arg1
/ u_arg2
: 0;
654 static inline int64_t msa_mod_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
656 if (arg1
== DF_MIN_INT(df
) && arg2
== -1) {
659 return arg2
? arg1
% arg2
: 0;
662 static inline int64_t msa_mod_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
664 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
665 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
666 return u_arg2
? u_arg1
% u_arg2
: 0;
669 #define SIGNED_EVEN(a, df) \
670 ((((int64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
672 #define UNSIGNED_EVEN(a, df) \
673 ((((uint64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
675 #define SIGNED_ODD(a, df) \
676 ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
678 #define UNSIGNED_ODD(a, df) \
679 ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
681 #define SIGNED_EXTRACT(e, o, a, df) \
683 e = SIGNED_EVEN(a, df); \
684 o = SIGNED_ODD(a, df); \
687 #define UNSIGNED_EXTRACT(e, o, a, df) \
689 e = UNSIGNED_EVEN(a, df); \
690 o = UNSIGNED_ODD(a, df); \
693 static inline int64_t msa_dotp_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
699 SIGNED_EXTRACT(even_arg1
, odd_arg1
, arg1
, df
);
700 SIGNED_EXTRACT(even_arg2
, odd_arg2
, arg2
, df
);
701 return (even_arg1
* even_arg2
) + (odd_arg1
* odd_arg2
);
704 static inline int64_t msa_dotp_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
710 UNSIGNED_EXTRACT(even_arg1
, odd_arg1
, arg1
, df
);
711 UNSIGNED_EXTRACT(even_arg2
, odd_arg2
, arg2
, df
);
712 return (even_arg1
* even_arg2
) + (odd_arg1
* odd_arg2
);
715 #define CONCATENATE_AND_SLIDE(s, k) \
717 for (i = 0; i < s; i++) { \
718 v[i] = pws->b[s * k + i]; \
719 v[i + s] = pwd->b[s * k + i]; \
721 for (i = 0; i < s; i++) { \
722 pwd->b[s * k + i] = v[i + n]; \
726 static inline void msa_sld_df(uint32_t df
, wr_t
*pwd
,
727 wr_t
*pws
, target_ulong rt
)
729 uint32_t n
= rt
% DF_ELEMENTS(df
);
735 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_BYTE
), 0);
738 for (k
= 0; k
< 2; k
++) {
739 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_HALF
), k
);
743 for (k
= 0; k
< 4; k
++) {
744 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_WORD
), k
);
748 for (k
= 0; k
< 8; k
++) {
749 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_DOUBLE
), k
);
757 static inline int64_t msa_hadd_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
759 return SIGNED_ODD(arg1
, df
) + SIGNED_EVEN(arg2
, df
);
762 static inline int64_t msa_hadd_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
764 return UNSIGNED_ODD(arg1
, df
) + UNSIGNED_EVEN(arg2
, df
);
767 static inline int64_t msa_hsub_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
769 return SIGNED_ODD(arg1
, df
) - SIGNED_EVEN(arg2
, df
);
772 static inline int64_t msa_hsub_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
774 return UNSIGNED_ODD(arg1
, df
) - UNSIGNED_EVEN(arg2
, df
);
777 static inline int64_t msa_mul_q_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
779 int64_t q_min
= DF_MIN_INT(df
);
780 int64_t q_max
= DF_MAX_INT(df
);
782 if (arg1
== q_min
&& arg2
== q_min
) {
785 return (arg1
* arg2
) >> (DF_BITS(df
) - 1);
788 static inline int64_t msa_mulr_q_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
790 int64_t q_min
= DF_MIN_INT(df
);
791 int64_t q_max
= DF_MAX_INT(df
);
792 int64_t r_bit
= 1 << (DF_BITS(df
) - 2);
794 if (arg1
== q_min
&& arg2
== q_min
) {
797 return (arg1
* arg2
+ r_bit
) >> (DF_BITS(df
) - 1);
800 #define MSA_BINOP_DF(func) \
801 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
802 uint32_t wd, uint32_t ws, uint32_t wt) \
804 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
805 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
806 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
811 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
812 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], pwt->b[i]); \
816 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
817 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], pwt->h[i]); \
821 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
822 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], pwt->w[i]); \
826 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
827 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], pwt->d[i]); \
864 MSA_BINOP_DF(subsus_u
)
865 MSA_BINOP_DF(subsuu_s
)
886 void helper_msa_sld_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
887 uint32_t ws
, uint32_t rt
)
889 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
890 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
892 msa_sld_df(df
, pwd
, pws
, env
->active_tc
.gpr
[rt
]);
895 static inline int64_t msa_maddv_df(uint32_t df
, int64_t dest
, int64_t arg1
,
898 return dest
+ arg1
* arg2
;
901 static inline int64_t msa_msubv_df(uint32_t df
, int64_t dest
, int64_t arg1
,
904 return dest
- arg1
* arg2
;
907 static inline int64_t msa_dpadd_s_df(uint32_t df
, int64_t dest
, int64_t arg1
,
914 SIGNED_EXTRACT(even_arg1
, odd_arg1
, arg1
, df
);
915 SIGNED_EXTRACT(even_arg2
, odd_arg2
, arg2
, df
);
916 return dest
+ (even_arg1
* even_arg2
) + (odd_arg1
* odd_arg2
);
919 static inline int64_t msa_dpadd_u_df(uint32_t df
, int64_t dest
, int64_t arg1
,
926 UNSIGNED_EXTRACT(even_arg1
, odd_arg1
, arg1
, df
);
927 UNSIGNED_EXTRACT(even_arg2
, odd_arg2
, arg2
, df
);
928 return dest
+ (even_arg1
* even_arg2
) + (odd_arg1
* odd_arg2
);
931 static inline int64_t msa_dpsub_s_df(uint32_t df
, int64_t dest
, int64_t arg1
,
938 SIGNED_EXTRACT(even_arg1
, odd_arg1
, arg1
, df
);
939 SIGNED_EXTRACT(even_arg2
, odd_arg2
, arg2
, df
);
940 return dest
- ((even_arg1
* even_arg2
) + (odd_arg1
* odd_arg2
));
943 static inline int64_t msa_dpsub_u_df(uint32_t df
, int64_t dest
, int64_t arg1
,
950 UNSIGNED_EXTRACT(even_arg1
, odd_arg1
, arg1
, df
);
951 UNSIGNED_EXTRACT(even_arg2
, odd_arg2
, arg2
, df
);
952 return dest
- ((even_arg1
* even_arg2
) + (odd_arg1
* odd_arg2
));
955 static inline int64_t msa_madd_q_df(uint32_t df
, int64_t dest
, int64_t arg1
,
958 int64_t q_prod
, q_ret
;
960 int64_t q_max
= DF_MAX_INT(df
);
961 int64_t q_min
= DF_MIN_INT(df
);
963 q_prod
= arg1
* arg2
;
964 q_ret
= ((dest
<< (DF_BITS(df
) - 1)) + q_prod
) >> (DF_BITS(df
) - 1);
966 return (q_ret
< q_min
) ? q_min
: (q_max
< q_ret
) ? q_max
: q_ret
;
969 static inline int64_t msa_msub_q_df(uint32_t df
, int64_t dest
, int64_t arg1
,
972 int64_t q_prod
, q_ret
;
974 int64_t q_max
= DF_MAX_INT(df
);
975 int64_t q_min
= DF_MIN_INT(df
);
977 q_prod
= arg1
* arg2
;
978 q_ret
= ((dest
<< (DF_BITS(df
) - 1)) - q_prod
) >> (DF_BITS(df
) - 1);
980 return (q_ret
< q_min
) ? q_min
: (q_max
< q_ret
) ? q_max
: q_ret
;
983 static inline int64_t msa_maddr_q_df(uint32_t df
, int64_t dest
, int64_t arg1
,
986 int64_t q_prod
, q_ret
;
988 int64_t q_max
= DF_MAX_INT(df
);
989 int64_t q_min
= DF_MIN_INT(df
);
990 int64_t r_bit
= 1 << (DF_BITS(df
) - 2);
992 q_prod
= arg1
* arg2
;
993 q_ret
= ((dest
<< (DF_BITS(df
) - 1)) + q_prod
+ r_bit
) >> (DF_BITS(df
) - 1);
995 return (q_ret
< q_min
) ? q_min
: (q_max
< q_ret
) ? q_max
: q_ret
;
998 static inline int64_t msa_msubr_q_df(uint32_t df
, int64_t dest
, int64_t arg1
,
1001 int64_t q_prod
, q_ret
;
1003 int64_t q_max
= DF_MAX_INT(df
);
1004 int64_t q_min
= DF_MIN_INT(df
);
1005 int64_t r_bit
= 1 << (DF_BITS(df
) - 2);
1007 q_prod
= arg1
* arg2
;
1008 q_ret
= ((dest
<< (DF_BITS(df
) - 1)) - q_prod
+ r_bit
) >> (DF_BITS(df
) - 1);
1010 return (q_ret
< q_min
) ? q_min
: (q_max
< q_ret
) ? q_max
: q_ret
;
1013 #define MSA_TEROP_DF(func) \
1014 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1015 uint32_t ws, uint32_t wt) \
1017 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1018 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1019 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1024 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1025 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
1030 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1031 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
1036 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1037 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
1042 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1043 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
1054 MSA_TEROP_DF(dpadd_s
)
1055 MSA_TEROP_DF(dpadd_u
)
1056 MSA_TEROP_DF(dpsub_s
)
1057 MSA_TEROP_DF(dpsub_u
)
1060 MSA_TEROP_DF(madd_q
)
1061 MSA_TEROP_DF(msub_q
)
1062 MSA_TEROP_DF(maddr_q
)
1063 MSA_TEROP_DF(msubr_q
)
1066 static inline void msa_splat_df(uint32_t df
, wr_t
*pwd
,
1067 wr_t
*pws
, target_ulong rt
)
1069 uint32_t n
= rt
% DF_ELEMENTS(df
);
1074 for (i
= 0; i
< DF_ELEMENTS(DF_BYTE
); i
++) {
1075 pwd
->b
[i
] = pws
->b
[n
];
1079 for (i
= 0; i
< DF_ELEMENTS(DF_HALF
); i
++) {
1080 pwd
->h
[i
] = pws
->h
[n
];
1084 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
1085 pwd
->w
[i
] = pws
->w
[n
];
1089 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
1090 pwd
->d
[i
] = pws
->d
[n
];
1098 void helper_msa_splat_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
1099 uint32_t ws
, uint32_t rt
)
1101 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1102 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
1104 msa_splat_df(df
, pwd
, pws
, env
->active_tc
.gpr
[rt
]);
1107 #define MSA_DO_B MSA_DO(b)
1108 #define MSA_DO_H MSA_DO(h)
1109 #define MSA_DO_W MSA_DO(w)
1110 #define MSA_DO_D MSA_DO(d)
1112 #define MSA_LOOP_B MSA_LOOP(B)
1113 #define MSA_LOOP_H MSA_LOOP(H)
1114 #define MSA_LOOP_W MSA_LOOP(W)
1115 #define MSA_LOOP_D MSA_LOOP(D)
1117 #define MSA_LOOP_COND_B MSA_LOOP_COND(DF_BYTE)
1118 #define MSA_LOOP_COND_H MSA_LOOP_COND(DF_HALF)
1119 #define MSA_LOOP_COND_W MSA_LOOP_COND(DF_WORD)
1120 #define MSA_LOOP_COND_D MSA_LOOP_COND(DF_DOUBLE)
1122 #define MSA_LOOP(DF) \
1124 for (i = 0; i < (MSA_LOOP_COND_ ## DF) ; i++) { \
1129 #define MSA_FN_DF(FUNC) \
1130 void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1131 uint32_t ws, uint32_t wt) \
1133 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1134 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1135 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1136 wr_t wx, *pwx = &wx; \
1154 msa_move_v(pwd, pwx); \
1157 #define MSA_LOOP_COND(DF) \
1158 (DF_ELEMENTS(DF) / 2)
1160 #define Rb(pwr, i) (pwr->b[i])
1161 #define Lb(pwr, i) (pwr->b[i + DF_ELEMENTS(DF_BYTE)/2])
1162 #define Rh(pwr, i) (pwr->h[i])
1163 #define Lh(pwr, i) (pwr->h[i + DF_ELEMENTS(DF_HALF)/2])
1164 #define Rw(pwr, i) (pwr->w[i])
1165 #define Lw(pwr, i) (pwr->w[i + DF_ELEMENTS(DF_WORD)/2])
1166 #define Rd(pwr, i) (pwr->d[i])
1167 #define Ld(pwr, i) (pwr->d[i + DF_ELEMENTS(DF_DOUBLE)/2])
1169 #define MSA_DO(DF) \
1171 R##DF(pwx, i) = pwt->DF[2*i]; \
1172 L##DF(pwx, i) = pws->DF[2*i]; \
1177 #define MSA_DO(DF) \
1179 R##DF(pwx, i) = pwt->DF[2*i+1]; \
1180 L##DF(pwx, i) = pws->DF[2*i+1]; \
1185 #define MSA_DO(DF) \
1187 pwx->DF[2*i] = L##DF(pwt, i); \
1188 pwx->DF[2*i+1] = L##DF(pws, i); \
1193 #define MSA_DO(DF) \
1195 pwx->DF[2*i] = R##DF(pwt, i); \
1196 pwx->DF[2*i+1] = R##DF(pws, i); \
1201 #define MSA_DO(DF) \
1203 pwx->DF[2*i] = pwt->DF[2*i]; \
1204 pwx->DF[2*i+1] = pws->DF[2*i]; \
1209 #define MSA_DO(DF) \
1211 pwx->DF[2*i] = pwt->DF[2*i+1]; \
1212 pwx->DF[2*i+1] = pws->DF[2*i+1]; \
1216 #undef MSA_LOOP_COND
1218 #define MSA_LOOP_COND(DF) \
1221 #define MSA_DO(DF) \
1223 uint32_t n = DF_ELEMENTS(df); \
1224 uint32_t k = (pwd->DF[i] & 0x3f) % (2 * n); \
1226 (pwd->DF[i] & 0xc0) ? 0 : k < n ? pwt->DF[k] : pws->DF[k - n]; \
1230 #undef MSA_LOOP_COND
1233 void helper_msa_sldi_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
1234 uint32_t ws
, uint32_t n
)
1236 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1237 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
1239 msa_sld_df(df
, pwd
, pws
, n
);
1242 void helper_msa_splati_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
1243 uint32_t ws
, uint32_t n
)
1245 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1246 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
1248 msa_splat_df(df
, pwd
, pws
, n
);
1251 void helper_msa_copy_s_df(CPUMIPSState
*env
, uint32_t df
, uint32_t rd
,
1252 uint32_t ws
, uint32_t n
)
1254 n
%= DF_ELEMENTS(df
);
1258 env
->active_tc
.gpr
[rd
] = (int8_t)env
->active_fpu
.fpr
[ws
].wr
.b
[n
];
1261 env
->active_tc
.gpr
[rd
] = (int16_t)env
->active_fpu
.fpr
[ws
].wr
.h
[n
];
1264 env
->active_tc
.gpr
[rd
] = (int32_t)env
->active_fpu
.fpr
[ws
].wr
.w
[n
];
1266 #ifdef TARGET_MIPS64
1268 env
->active_tc
.gpr
[rd
] = (int64_t)env
->active_fpu
.fpr
[ws
].wr
.d
[n
];
1276 void helper_msa_copy_u_df(CPUMIPSState
*env
, uint32_t df
, uint32_t rd
,
1277 uint32_t ws
, uint32_t n
)
1279 n
%= DF_ELEMENTS(df
);
1283 env
->active_tc
.gpr
[rd
] = (uint8_t)env
->active_fpu
.fpr
[ws
].wr
.b
[n
];
1286 env
->active_tc
.gpr
[rd
] = (uint16_t)env
->active_fpu
.fpr
[ws
].wr
.h
[n
];
1289 env
->active_tc
.gpr
[rd
] = (uint32_t)env
->active_fpu
.fpr
[ws
].wr
.w
[n
];
1291 #ifdef TARGET_MIPS64
1293 env
->active_tc
.gpr
[rd
] = (uint64_t)env
->active_fpu
.fpr
[ws
].wr
.d
[n
];
1301 void helper_msa_insert_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
1302 uint32_t rs_num
, uint32_t n
)
1304 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1305 target_ulong rs
= env
->active_tc
.gpr
[rs_num
];
1309 pwd
->b
[n
] = (int8_t)rs
;
1312 pwd
->h
[n
] = (int16_t)rs
;
1315 pwd
->w
[n
] = (int32_t)rs
;
1318 pwd
->d
[n
] = (int64_t)rs
;
1325 void helper_msa_insve_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
1326 uint32_t ws
, uint32_t n
)
1328 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1329 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
1333 pwd
->b
[n
] = (int8_t)pws
->b
[0];
1336 pwd
->h
[n
] = (int16_t)pws
->h
[0];
1339 pwd
->w
[n
] = (int32_t)pws
->w
[0];
1342 pwd
->d
[n
] = (int64_t)pws
->d
[0];
1349 void helper_msa_ctcmsa(CPUMIPSState
*env
, target_ulong elm
, uint32_t cd
)
1355 env
->active_tc
.msacsr
= (int32_t)elm
& MSACSR_MASK
;
1356 restore_msa_fp_status(env
);
1357 /* check exception */
1358 if ((GET_FP_ENABLE(env
->active_tc
.msacsr
) | FP_UNIMPLEMENTED
)
1359 & GET_FP_CAUSE(env
->active_tc
.msacsr
)) {
1360 do_raise_exception(env
, EXCP_MSAFPE
, GETPC());
1366 target_ulong
helper_msa_cfcmsa(CPUMIPSState
*env
, uint32_t cs
)
1372 return env
->active_tc
.msacsr
& MSACSR_MASK
;
1377 void helper_msa_move_v(CPUMIPSState
*env
, uint32_t wd
, uint32_t ws
)
1379 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1380 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
1382 msa_move_v(pwd
, pws
);
1385 static inline int64_t msa_pcnt_df(uint32_t df
, int64_t arg
)
1389 x
= UNSIGNED(arg
, df
);
1391 x
= (x
& 0x5555555555555555ULL
) + ((x
>> 1) & 0x5555555555555555ULL
);
1392 x
= (x
& 0x3333333333333333ULL
) + ((x
>> 2) & 0x3333333333333333ULL
);
1393 x
= (x
& 0x0F0F0F0F0F0F0F0FULL
) + ((x
>> 4) & 0x0F0F0F0F0F0F0F0FULL
);
1394 x
= (x
& 0x00FF00FF00FF00FFULL
) + ((x
>> 8) & 0x00FF00FF00FF00FFULL
);
1395 x
= (x
& 0x0000FFFF0000FFFFULL
) + ((x
>> 16) & 0x0000FFFF0000FFFFULL
);
1396 x
= (x
& 0x00000000FFFFFFFFULL
) + ((x
>> 32));
1401 static inline int64_t msa_nlzc_df(uint32_t df
, int64_t arg
)
1406 x
= UNSIGNED(arg
, df
);
1408 c
= DF_BITS(df
) / 2;
1422 static inline int64_t msa_nloc_df(uint32_t df
, int64_t arg
)
1424 return msa_nlzc_df(df
, UNSIGNED((~arg
), df
));
1427 void helper_msa_fill_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
1430 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1435 for (i
= 0; i
< DF_ELEMENTS(DF_BYTE
); i
++) {
1436 pwd
->b
[i
] = (int8_t)env
->active_tc
.gpr
[rs
];
1440 for (i
= 0; i
< DF_ELEMENTS(DF_HALF
); i
++) {
1441 pwd
->h
[i
] = (int16_t)env
->active_tc
.gpr
[rs
];
1445 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
1446 pwd
->w
[i
] = (int32_t)env
->active_tc
.gpr
[rs
];
1450 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
1451 pwd
->d
[i
] = (int64_t)env
->active_tc
.gpr
[rs
];
1459 #define MSA_UNOP_DF(func) \
1460 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
1461 uint32_t wd, uint32_t ws) \
1463 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1464 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1469 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1470 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i]); \
1474 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1475 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i]); \
1479 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1480 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i]); \
1484 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1485 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i]); \
1498 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1499 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1501 #define FLOAT_SNAN16(s) (float16_default_nan(s) ^ 0x0220)
1503 #define FLOAT_SNAN32(s) (float32_default_nan(s) ^ 0x00400020)
1505 #define FLOAT_SNAN64(s) (float64_default_nan(s) ^ 0x0008000000000020ULL)
1506 /* 0x7ff0000000000020 */
1508 static inline void clear_msacsr_cause(CPUMIPSState
*env
)
1510 SET_FP_CAUSE(env
->active_tc
.msacsr
, 0);
1513 static inline void check_msacsr_cause(CPUMIPSState
*env
, uintptr_t retaddr
)
1515 if ((GET_FP_CAUSE(env
->active_tc
.msacsr
) &
1516 (GET_FP_ENABLE(env
->active_tc
.msacsr
) | FP_UNIMPLEMENTED
)) == 0) {
1517 UPDATE_FP_FLAGS(env
->active_tc
.msacsr
,
1518 GET_FP_CAUSE(env
->active_tc
.msacsr
));
1520 do_raise_exception(env
, EXCP_MSAFPE
, retaddr
);
1524 /* Flush-to-zero use cases for update_msacsr() */
1525 #define CLEAR_FS_UNDERFLOW 1
1526 #define CLEAR_IS_INEXACT 2
1527 #define RECIPROCAL_INEXACT 4
1529 static inline int update_msacsr(CPUMIPSState
*env
, int action
, int denormal
)
1537 ieee_ex
= get_float_exception_flags(&env
->active_tc
.msa_fp_status
);
1539 /* QEMU softfloat does not signal all underflow cases */
1541 ieee_ex
|= float_flag_underflow
;
1544 c
= ieee_ex_to_mips(ieee_ex
);
1545 enable
= GET_FP_ENABLE(env
->active_tc
.msacsr
) | FP_UNIMPLEMENTED
;
1547 /* Set Inexact (I) when flushing inputs to zero */
1548 if ((ieee_ex
& float_flag_input_denormal
) &&
1549 (env
->active_tc
.msacsr
& MSACSR_FS_MASK
) != 0) {
1550 if (action
& CLEAR_IS_INEXACT
) {
1557 /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
1558 if ((ieee_ex
& float_flag_output_denormal
) &&
1559 (env
->active_tc
.msacsr
& MSACSR_FS_MASK
) != 0) {
1561 if (action
& CLEAR_FS_UNDERFLOW
) {
1568 /* Set Inexact (I) when Overflow (O) is not enabled */
1569 if ((c
& FP_OVERFLOW
) != 0 && (enable
& FP_OVERFLOW
) == 0) {
1573 /* Clear Exact Underflow when Underflow (U) is not enabled */
1574 if ((c
& FP_UNDERFLOW
) != 0 && (enable
& FP_UNDERFLOW
) == 0 &&
1575 (c
& FP_INEXACT
) == 0) {
1579 /* Reciprocal operations set only Inexact when valid and not
1581 if ((action
& RECIPROCAL_INEXACT
) &&
1582 (c
& (FP_INVALID
| FP_DIV0
)) == 0) {
1586 cause
= c
& enable
; /* all current enabled exceptions */
1589 /* No enabled exception, update the MSACSR Cause
1590 with all current exceptions */
1591 SET_FP_CAUSE(env
->active_tc
.msacsr
,
1592 (GET_FP_CAUSE(env
->active_tc
.msacsr
) | c
));
1594 /* Current exceptions are enabled */
1595 if ((env
->active_tc
.msacsr
& MSACSR_NX_MASK
) == 0) {
1596 /* Exception(s) will trap, update MSACSR Cause
1597 with all enabled exceptions */
1598 SET_FP_CAUSE(env
->active_tc
.msacsr
,
1599 (GET_FP_CAUSE(env
->active_tc
.msacsr
) | c
));
1606 static inline int get_enabled_exceptions(const CPUMIPSState
*env
, int c
)
1608 int enable
= GET_FP_ENABLE(env
->active_tc
.msacsr
) | FP_UNIMPLEMENTED
;
1612 static inline float16
float16_from_float32(int32_t a
, flag ieee
,
1613 float_status
*status
)
1617 f_val
= float32_to_float16((float32
)a
, ieee
, status
);
1618 f_val
= float16_maybe_silence_nan(f_val
, status
);
1620 return a
< 0 ? (f_val
| (1 << 15)) : f_val
;
1623 static inline float32
float32_from_float64(int64_t a
, float_status
*status
)
1627 f_val
= float64_to_float32((float64
)a
, status
);
1628 f_val
= float32_maybe_silence_nan(f_val
, status
);
1630 return a
< 0 ? (f_val
| (1 << 31)) : f_val
;
1633 static inline float32
float32_from_float16(int16_t a
, flag ieee
,
1634 float_status
*status
)
1638 f_val
= float16_to_float32((float16
)a
, ieee
, status
);
1639 f_val
= float32_maybe_silence_nan(f_val
, status
);
1641 return a
< 0 ? (f_val
| (1 << 31)) : f_val
;
1644 static inline float64
float64_from_float32(int32_t a
, float_status
*status
)
1648 f_val
= float32_to_float64((float64
)a
, status
);
1649 f_val
= float64_maybe_silence_nan(f_val
, status
);
1651 return a
< 0 ? (f_val
| (1ULL << 63)) : f_val
;
1654 static inline float32
float32_from_q16(int16_t a
, float_status
*status
)
1658 /* conversion as integer and scaling */
1659 f_val
= int32_to_float32(a
, status
);
1660 f_val
= float32_scalbn(f_val
, -15, status
);
1665 static inline float64
float64_from_q32(int32_t a
, float_status
*status
)
1669 /* conversion as integer and scaling */
1670 f_val
= int32_to_float64(a
, status
);
1671 f_val
= float64_scalbn(f_val
, -31, status
);
1676 static inline int16_t float32_to_q16(float32 a
, float_status
*status
)
1679 int32_t q_min
= 0xffff8000;
1680 int32_t q_max
= 0x00007fff;
1684 if (float32_is_any_nan(a
)) {
1685 float_raise(float_flag_invalid
, status
);
1690 a
= float32_scalbn(a
, 15, status
);
1692 ieee_ex
= get_float_exception_flags(status
);
1693 set_float_exception_flags(ieee_ex
& (~float_flag_underflow
)
1696 if (ieee_ex
& float_flag_overflow
) {
1697 float_raise(float_flag_inexact
, status
);
1698 return (int32_t)a
< 0 ? q_min
: q_max
;
1701 /* conversion to int */
1702 q_val
= float32_to_int32(a
, status
);
1704 ieee_ex
= get_float_exception_flags(status
);
1705 set_float_exception_flags(ieee_ex
& (~float_flag_underflow
)
1708 if (ieee_ex
& float_flag_invalid
) {
1709 set_float_exception_flags(ieee_ex
& (~float_flag_invalid
)
1711 float_raise(float_flag_overflow
| float_flag_inexact
, status
);
1712 return (int32_t)a
< 0 ? q_min
: q_max
;
1715 if (q_val
< q_min
) {
1716 float_raise(float_flag_overflow
| float_flag_inexact
, status
);
1717 return (int16_t)q_min
;
1720 if (q_max
< q_val
) {
1721 float_raise(float_flag_overflow
| float_flag_inexact
, status
);
1722 return (int16_t)q_max
;
1725 return (int16_t)q_val
;
1728 static inline int32_t float64_to_q32(float64 a
, float_status
*status
)
1731 int64_t q_min
= 0xffffffff80000000LL
;
1732 int64_t q_max
= 0x000000007fffffffLL
;
1736 if (float64_is_any_nan(a
)) {
1737 float_raise(float_flag_invalid
, status
);
1742 a
= float64_scalbn(a
, 31, status
);
1744 ieee_ex
= get_float_exception_flags(status
);
1745 set_float_exception_flags(ieee_ex
& (~float_flag_underflow
)
1748 if (ieee_ex
& float_flag_overflow
) {
1749 float_raise(float_flag_inexact
, status
);
1750 return (int64_t)a
< 0 ? q_min
: q_max
;
1753 /* conversion to integer */
1754 q_val
= float64_to_int64(a
, status
);
1756 ieee_ex
= get_float_exception_flags(status
);
1757 set_float_exception_flags(ieee_ex
& (~float_flag_underflow
)
1760 if (ieee_ex
& float_flag_invalid
) {
1761 set_float_exception_flags(ieee_ex
& (~float_flag_invalid
)
1763 float_raise(float_flag_overflow
| float_flag_inexact
, status
);
1764 return (int64_t)a
< 0 ? q_min
: q_max
;
1767 if (q_val
< q_min
) {
1768 float_raise(float_flag_overflow
| float_flag_inexact
, status
);
1769 return (int32_t)q_min
;
1772 if (q_max
< q_val
) {
1773 float_raise(float_flag_overflow
| float_flag_inexact
, status
);
1774 return (int32_t)q_max
;
1777 return (int32_t)q_val
;
1780 #define MSA_FLOAT_COND(DEST, OP, ARG1, ARG2, BITS, QUIET) \
1782 float_status *status = &env->active_tc.msa_fp_status; \
1785 set_float_exception_flags(0, status); \
1787 cond = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
1789 cond = float ## BITS ## _ ## OP ## _quiet(ARG1, ARG2, status); \
1791 DEST = cond ? M_MAX_UINT(BITS) : 0; \
1792 c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \
1794 if (get_enabled_exceptions(env, c)) { \
1795 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
1799 #define MSA_FLOAT_AF(DEST, ARG1, ARG2, BITS, QUIET) \
1801 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1802 if ((DEST & M_MAX_UINT(BITS)) == M_MAX_UINT(BITS)) { \
1807 #define MSA_FLOAT_UEQ(DEST, ARG1, ARG2, BITS, QUIET) \
1809 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1811 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1815 #define MSA_FLOAT_NE(DEST, ARG1, ARG2, BITS, QUIET) \
1817 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1819 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1823 #define MSA_FLOAT_UNE(DEST, ARG1, ARG2, BITS, QUIET) \
1825 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1827 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1829 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1834 #define MSA_FLOAT_ULE(DEST, ARG1, ARG2, BITS, QUIET) \
1836 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1838 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1842 #define MSA_FLOAT_ULT(DEST, ARG1, ARG2, BITS, QUIET) \
1844 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1846 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1850 #define MSA_FLOAT_OR(DEST, ARG1, ARG2, BITS, QUIET) \
1852 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1854 MSA_FLOAT_COND(DEST, le, ARG2, ARG1, BITS, QUIET); \
1858 static inline void compare_af(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
1859 wr_t
*pwt
, uint32_t df
, int quiet
,
1862 wr_t wx
, *pwx
= &wx
;
1865 clear_msacsr_cause(env
);
1869 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
1870 MSA_FLOAT_AF(pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
1874 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
1875 MSA_FLOAT_AF(pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
1882 check_msacsr_cause(env
, retaddr
);
1884 msa_move_v(pwd
, pwx
);
1887 static inline void compare_un(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
1888 wr_t
*pwt
, uint32_t df
, int quiet
,
1891 wr_t wx
, *pwx
= &wx
;
1894 clear_msacsr_cause(env
);
1898 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
1899 MSA_FLOAT_COND(pwx
->w
[i
], unordered
, pws
->w
[i
], pwt
->w
[i
], 32,
1904 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
1905 MSA_FLOAT_COND(pwx
->d
[i
], unordered
, pws
->d
[i
], pwt
->d
[i
], 64,
1913 check_msacsr_cause(env
, retaddr
);
1915 msa_move_v(pwd
, pwx
);
1918 static inline void compare_eq(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
1919 wr_t
*pwt
, uint32_t df
, int quiet
,
1922 wr_t wx
, *pwx
= &wx
;
1925 clear_msacsr_cause(env
);
1929 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
1930 MSA_FLOAT_COND(pwx
->w
[i
], eq
, pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
1934 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
1935 MSA_FLOAT_COND(pwx
->d
[i
], eq
, pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
1942 check_msacsr_cause(env
, retaddr
);
1944 msa_move_v(pwd
, pwx
);
1947 static inline void compare_ueq(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
1948 wr_t
*pwt
, uint32_t df
, int quiet
,
1951 wr_t wx
, *pwx
= &wx
;
1954 clear_msacsr_cause(env
);
1958 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
1959 MSA_FLOAT_UEQ(pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
1963 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
1964 MSA_FLOAT_UEQ(pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
1971 check_msacsr_cause(env
, retaddr
);
1973 msa_move_v(pwd
, pwx
);
1976 static inline void compare_lt(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
1977 wr_t
*pwt
, uint32_t df
, int quiet
,
1980 wr_t wx
, *pwx
= &wx
;
1983 clear_msacsr_cause(env
);
1987 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
1988 MSA_FLOAT_COND(pwx
->w
[i
], lt
, pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
1992 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
1993 MSA_FLOAT_COND(pwx
->d
[i
], lt
, pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
2000 check_msacsr_cause(env
, retaddr
);
2002 msa_move_v(pwd
, pwx
);
2005 static inline void compare_ult(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
2006 wr_t
*pwt
, uint32_t df
, int quiet
,
2009 wr_t wx
, *pwx
= &wx
;
2012 clear_msacsr_cause(env
);
2016 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2017 MSA_FLOAT_ULT(pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
2021 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2022 MSA_FLOAT_ULT(pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
2029 check_msacsr_cause(env
, retaddr
);
2031 msa_move_v(pwd
, pwx
);
2034 static inline void compare_le(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
2035 wr_t
*pwt
, uint32_t df
, int quiet
,
2038 wr_t wx
, *pwx
= &wx
;
2041 clear_msacsr_cause(env
);
2045 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2046 MSA_FLOAT_COND(pwx
->w
[i
], le
, pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
2050 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2051 MSA_FLOAT_COND(pwx
->d
[i
], le
, pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
2058 check_msacsr_cause(env
, retaddr
);
2060 msa_move_v(pwd
, pwx
);
2063 static inline void compare_ule(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
2064 wr_t
*pwt
, uint32_t df
, int quiet
,
2067 wr_t wx
, *pwx
= &wx
;
2070 clear_msacsr_cause(env
);
2074 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2075 MSA_FLOAT_ULE(pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
2079 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2080 MSA_FLOAT_ULE(pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
2087 check_msacsr_cause(env
, retaddr
);
2089 msa_move_v(pwd
, pwx
);
2092 static inline void compare_or(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
2093 wr_t
*pwt
, uint32_t df
, int quiet
,
2096 wr_t wx
, *pwx
= &wx
;
2099 clear_msacsr_cause(env
);
2103 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2104 MSA_FLOAT_OR(pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
2108 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2109 MSA_FLOAT_OR(pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
2116 check_msacsr_cause(env
, retaddr
);
2118 msa_move_v(pwd
, pwx
);
2121 static inline void compare_une(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
2122 wr_t
*pwt
, uint32_t df
, int quiet
,
2125 wr_t wx
, *pwx
= &wx
;
2128 clear_msacsr_cause(env
);
2132 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2133 MSA_FLOAT_UNE(pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
2137 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2138 MSA_FLOAT_UNE(pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
2145 check_msacsr_cause(env
, retaddr
);
2147 msa_move_v(pwd
, pwx
);
2150 static inline void compare_ne(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
2151 wr_t
*pwt
, uint32_t df
, int quiet
,
2154 wr_t wx
, *pwx
= &wx
;
2157 clear_msacsr_cause(env
);
2161 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2162 MSA_FLOAT_NE(pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
2166 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2167 MSA_FLOAT_NE(pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
2174 check_msacsr_cause(env
, retaddr
);
2176 msa_move_v(pwd
, pwx
);
2179 void helper_msa_fcaf_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2180 uint32_t ws
, uint32_t wt
)
2182 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2183 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2184 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2185 compare_af(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2188 void helper_msa_fcun_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2189 uint32_t ws
, uint32_t wt
)
2191 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2192 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2193 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2194 compare_un(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2197 void helper_msa_fceq_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2198 uint32_t ws
, uint32_t wt
)
2200 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2201 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2202 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2203 compare_eq(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2206 void helper_msa_fcueq_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2207 uint32_t ws
, uint32_t wt
)
2209 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2210 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2211 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2212 compare_ueq(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2215 void helper_msa_fclt_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2216 uint32_t ws
, uint32_t wt
)
2218 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2219 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2220 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2221 compare_lt(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2224 void helper_msa_fcult_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2225 uint32_t ws
, uint32_t wt
)
2227 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2228 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2229 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2230 compare_ult(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2233 void helper_msa_fcle_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2234 uint32_t ws
, uint32_t wt
)
2236 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2237 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2238 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2239 compare_le(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2242 void helper_msa_fcule_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2243 uint32_t ws
, uint32_t wt
)
2245 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2246 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2247 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2248 compare_ule(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2251 void helper_msa_fsaf_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2252 uint32_t ws
, uint32_t wt
)
2254 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2255 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2256 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2257 compare_af(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2260 void helper_msa_fsun_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2261 uint32_t ws
, uint32_t wt
)
2263 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2264 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2265 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2266 compare_un(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2269 void helper_msa_fseq_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2270 uint32_t ws
, uint32_t wt
)
2272 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2273 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2274 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2275 compare_eq(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2278 void helper_msa_fsueq_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2279 uint32_t ws
, uint32_t wt
)
2281 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2282 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2283 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2284 compare_ueq(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2287 void helper_msa_fslt_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2288 uint32_t ws
, uint32_t wt
)
2290 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2291 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2292 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2293 compare_lt(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2296 void helper_msa_fsult_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2297 uint32_t ws
, uint32_t wt
)
2299 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2300 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2301 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2302 compare_ult(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2305 void helper_msa_fsle_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2306 uint32_t ws
, uint32_t wt
)
2308 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2309 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2310 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2311 compare_le(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2314 void helper_msa_fsule_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2315 uint32_t ws
, uint32_t wt
)
2317 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2318 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2319 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2320 compare_ule(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2323 void helper_msa_fcor_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2324 uint32_t ws
, uint32_t wt
)
2326 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2327 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2328 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2329 compare_or(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2332 void helper_msa_fcune_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2333 uint32_t ws
, uint32_t wt
)
2335 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2336 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2337 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2338 compare_une(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2341 void helper_msa_fcne_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2342 uint32_t ws
, uint32_t wt
)
2344 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2345 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2346 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2347 compare_ne(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2350 void helper_msa_fsor_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2351 uint32_t ws
, uint32_t wt
)
2353 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2354 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2355 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2356 compare_or(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2359 void helper_msa_fsune_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2360 uint32_t ws
, uint32_t wt
)
2362 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2363 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2364 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2365 compare_une(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2368 void helper_msa_fsne_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2369 uint32_t ws
, uint32_t wt
)
2371 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2372 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2373 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2374 compare_ne(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2377 #define float16_is_zero(ARG) 0
2378 #define float16_is_zero_or_denormal(ARG) 0
2380 #define IS_DENORMAL(ARG, BITS) \
2381 (!float ## BITS ## _is_zero(ARG) \
2382 && float ## BITS ## _is_zero_or_denormal(ARG))
2384 #define MSA_FLOAT_BINOP(DEST, OP, ARG1, ARG2, BITS) \
2386 float_status *status = &env->active_tc.msa_fp_status; \
2389 set_float_exception_flags(0, status); \
2390 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2391 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2393 if (get_enabled_exceptions(env, c)) { \
2394 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2398 void helper_msa_fadd_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2399 uint32_t ws
, uint32_t wt
)
2401 wr_t wx
, *pwx
= &wx
;
2402 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2403 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2404 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2407 clear_msacsr_cause(env
);
2411 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2412 MSA_FLOAT_BINOP(pwx
->w
[i
], add
, pws
->w
[i
], pwt
->w
[i
], 32);
2416 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2417 MSA_FLOAT_BINOP(pwx
->d
[i
], add
, pws
->d
[i
], pwt
->d
[i
], 64);
2424 check_msacsr_cause(env
, GETPC());
2425 msa_move_v(pwd
, pwx
);
2428 void helper_msa_fsub_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2429 uint32_t ws
, uint32_t wt
)
2431 wr_t wx
, *pwx
= &wx
;
2432 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2433 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2434 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2437 clear_msacsr_cause(env
);
2441 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2442 MSA_FLOAT_BINOP(pwx
->w
[i
], sub
, pws
->w
[i
], pwt
->w
[i
], 32);
2446 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2447 MSA_FLOAT_BINOP(pwx
->d
[i
], sub
, pws
->d
[i
], pwt
->d
[i
], 64);
2454 check_msacsr_cause(env
, GETPC());
2455 msa_move_v(pwd
, pwx
);
2458 void helper_msa_fmul_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2459 uint32_t ws
, uint32_t wt
)
2461 wr_t wx
, *pwx
= &wx
;
2462 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2463 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2464 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2467 clear_msacsr_cause(env
);
2471 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2472 MSA_FLOAT_BINOP(pwx
->w
[i
], mul
, pws
->w
[i
], pwt
->w
[i
], 32);
2476 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2477 MSA_FLOAT_BINOP(pwx
->d
[i
], mul
, pws
->d
[i
], pwt
->d
[i
], 64);
2484 check_msacsr_cause(env
, GETPC());
2486 msa_move_v(pwd
, pwx
);
2489 void helper_msa_fdiv_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2490 uint32_t ws
, uint32_t wt
)
2492 wr_t wx
, *pwx
= &wx
;
2493 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2494 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2495 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2498 clear_msacsr_cause(env
);
2502 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2503 MSA_FLOAT_BINOP(pwx
->w
[i
], div
, pws
->w
[i
], pwt
->w
[i
], 32);
2507 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2508 MSA_FLOAT_BINOP(pwx
->d
[i
], div
, pws
->d
[i
], pwt
->d
[i
], 64);
2515 check_msacsr_cause(env
, GETPC());
2517 msa_move_v(pwd
, pwx
);
2520 #define MSA_FLOAT_MULADD(DEST, ARG1, ARG2, ARG3, NEGATE, BITS) \
2522 float_status *status = &env->active_tc.msa_fp_status; \
2525 set_float_exception_flags(0, status); \
2526 DEST = float ## BITS ## _muladd(ARG2, ARG3, ARG1, NEGATE, status); \
2527 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2529 if (get_enabled_exceptions(env, c)) { \
2530 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2534 void helper_msa_fmadd_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2535 uint32_t ws
, uint32_t wt
)
2537 wr_t wx
, *pwx
= &wx
;
2538 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2539 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2540 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2543 clear_msacsr_cause(env
);
2547 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2548 MSA_FLOAT_MULADD(pwx
->w
[i
], pwd
->w
[i
],
2549 pws
->w
[i
], pwt
->w
[i
], 0, 32);
2553 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2554 MSA_FLOAT_MULADD(pwx
->d
[i
], pwd
->d
[i
],
2555 pws
->d
[i
], pwt
->d
[i
], 0, 64);
2562 check_msacsr_cause(env
, GETPC());
2564 msa_move_v(pwd
, pwx
);
2567 void helper_msa_fmsub_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2568 uint32_t ws
, uint32_t wt
)
2570 wr_t wx
, *pwx
= &wx
;
2571 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2572 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2573 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2576 clear_msacsr_cause(env
);
2580 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2581 MSA_FLOAT_MULADD(pwx
->w
[i
], pwd
->w
[i
],
2582 pws
->w
[i
], pwt
->w
[i
],
2583 float_muladd_negate_product
, 32);
2587 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2588 MSA_FLOAT_MULADD(pwx
->d
[i
], pwd
->d
[i
],
2589 pws
->d
[i
], pwt
->d
[i
],
2590 float_muladd_negate_product
, 64);
2597 check_msacsr_cause(env
, GETPC());
2599 msa_move_v(pwd
, pwx
);
2602 void helper_msa_fexp2_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2603 uint32_t ws
, uint32_t wt
)
2605 wr_t wx
, *pwx
= &wx
;
2606 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2607 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2608 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2611 clear_msacsr_cause(env
);
2615 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2616 MSA_FLOAT_BINOP(pwx
->w
[i
], scalbn
, pws
->w
[i
],
2617 pwt
->w
[i
] > 0x200 ? 0x200 :
2618 pwt
->w
[i
] < -0x200 ? -0x200 : pwt
->w
[i
],
2623 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2624 MSA_FLOAT_BINOP(pwx
->d
[i
], scalbn
, pws
->d
[i
],
2625 pwt
->d
[i
] > 0x1000 ? 0x1000 :
2626 pwt
->d
[i
] < -0x1000 ? -0x1000 : pwt
->d
[i
],
2634 check_msacsr_cause(env
, GETPC());
2636 msa_move_v(pwd
, pwx
);
2639 #define MSA_FLOAT_UNOP(DEST, OP, ARG, BITS) \
2641 float_status *status = &env->active_tc.msa_fp_status; \
2644 set_float_exception_flags(0, status); \
2645 DEST = float ## BITS ## _ ## OP(ARG, status); \
2646 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2648 if (get_enabled_exceptions(env, c)) { \
2649 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2653 void helper_msa_fexdo_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2654 uint32_t ws
, uint32_t wt
)
2656 wr_t wx
, *pwx
= &wx
;
2657 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2658 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2659 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2662 clear_msacsr_cause(env
);
2666 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2667 /* Half precision floats come in two formats: standard
2668 IEEE and "ARM" format. The latter gains extra exponent
2669 range by omitting the NaN/Inf encodings. */
2672 MSA_FLOAT_BINOP(Lh(pwx
, i
), from_float32
, pws
->w
[i
], ieee
, 16);
2673 MSA_FLOAT_BINOP(Rh(pwx
, i
), from_float32
, pwt
->w
[i
], ieee
, 16);
2677 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2678 MSA_FLOAT_UNOP(Lw(pwx
, i
), from_float64
, pws
->d
[i
], 32);
2679 MSA_FLOAT_UNOP(Rw(pwx
, i
), from_float64
, pwt
->d
[i
], 32);
2686 check_msacsr_cause(env
, GETPC());
2687 msa_move_v(pwd
, pwx
);
2690 #define MSA_FLOAT_UNOP_XD(DEST, OP, ARG, BITS, XBITS) \
2692 float_status *status = &env->active_tc.msa_fp_status; \
2695 set_float_exception_flags(0, status); \
2696 DEST = float ## BITS ## _ ## OP(ARG, status); \
2697 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2699 if (get_enabled_exceptions(env, c)) { \
2700 DEST = ((FLOAT_SNAN ## XBITS(status) >> 6) << 6) | c; \
2704 void helper_msa_ftq_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2705 uint32_t ws
, uint32_t wt
)
2707 wr_t wx
, *pwx
= &wx
;
2708 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2709 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2710 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2713 clear_msacsr_cause(env
);
2717 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2718 MSA_FLOAT_UNOP_XD(Lh(pwx
, i
), to_q16
, pws
->w
[i
], 32, 16);
2719 MSA_FLOAT_UNOP_XD(Rh(pwx
, i
), to_q16
, pwt
->w
[i
], 32, 16);
2723 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2724 MSA_FLOAT_UNOP_XD(Lw(pwx
, i
), to_q32
, pws
->d
[i
], 64, 32);
2725 MSA_FLOAT_UNOP_XD(Rw(pwx
, i
), to_q32
, pwt
->d
[i
], 64, 32);
2732 check_msacsr_cause(env
, GETPC());
2734 msa_move_v(pwd
, pwx
);
2737 #define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS, STATUS) \
2738 !float ## BITS ## _is_any_nan(ARG1) \
2739 && float ## BITS ## _is_quiet_nan(ARG2, STATUS)
2741 #define MSA_FLOAT_MAXOP(DEST, OP, ARG1, ARG2, BITS) \
2743 float_status *status = &env->active_tc.msa_fp_status; \
2746 set_float_exception_flags(0, status); \
2747 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2748 c = update_msacsr(env, 0, 0); \
2750 if (get_enabled_exceptions(env, c)) { \
2751 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2755 #define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS) \
2757 uint## BITS ##_t S = _S, T = _T; \
2758 uint## BITS ##_t as, at, xs, xt, xd; \
2759 if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \
2762 else if (NUMBER_QNAN_PAIR(T, S, BITS, STATUS)) { \
2765 as = float## BITS ##_abs(S); \
2766 at = float## BITS ##_abs(T); \
2767 MSA_FLOAT_MAXOP(xs, F, S, T, BITS); \
2768 MSA_FLOAT_MAXOP(xt, G, S, T, BITS); \
2769 MSA_FLOAT_MAXOP(xd, F, as, at, BITS); \
2770 X = (as == at || xd == float## BITS ##_abs(xs)) ? xs : xt; \
2773 void helper_msa_fmin_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2774 uint32_t ws
, uint32_t wt
)
2776 float_status
*status
= &env
->active_tc
.msa_fp_status
;
2777 wr_t wx
, *pwx
= &wx
;
2778 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2779 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2780 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2783 clear_msacsr_cause(env
);
2787 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2788 if (NUMBER_QNAN_PAIR(pws
->w
[i
], pwt
->w
[i
], 32, status
)) {
2789 MSA_FLOAT_MAXOP(pwx
->w
[i
], min
, pws
->w
[i
], pws
->w
[i
], 32);
2790 } else if (NUMBER_QNAN_PAIR(pwt
->w
[i
], pws
->w
[i
], 32, status
)) {
2791 MSA_FLOAT_MAXOP(pwx
->w
[i
], min
, pwt
->w
[i
], pwt
->w
[i
], 32);
2793 MSA_FLOAT_MAXOP(pwx
->w
[i
], min
, pws
->w
[i
], pwt
->w
[i
], 32);
2798 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2799 if (NUMBER_QNAN_PAIR(pws
->d
[i
], pwt
->d
[i
], 64, status
)) {
2800 MSA_FLOAT_MAXOP(pwx
->d
[i
], min
, pws
->d
[i
], pws
->d
[i
], 64);
2801 } else if (NUMBER_QNAN_PAIR(pwt
->d
[i
], pws
->d
[i
], 64, status
)) {
2802 MSA_FLOAT_MAXOP(pwx
->d
[i
], min
, pwt
->d
[i
], pwt
->d
[i
], 64);
2804 MSA_FLOAT_MAXOP(pwx
->d
[i
], min
, pws
->d
[i
], pwt
->d
[i
], 64);
2812 check_msacsr_cause(env
, GETPC());
2814 msa_move_v(pwd
, pwx
);
2817 void helper_msa_fmin_a_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2818 uint32_t ws
, uint32_t wt
)
2820 float_status
*status
= &env
->active_tc
.msa_fp_status
;
2821 wr_t wx
, *pwx
= &wx
;
2822 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2823 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2824 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2827 clear_msacsr_cause(env
);
2831 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2832 FMAXMIN_A(min
, max
, pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, status
);
2836 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2837 FMAXMIN_A(min
, max
, pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, status
);
2844 check_msacsr_cause(env
, GETPC());
2846 msa_move_v(pwd
, pwx
);
2849 void helper_msa_fmax_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2850 uint32_t ws
, uint32_t wt
)
2852 float_status
*status
= &env
->active_tc
.msa_fp_status
;
2853 wr_t wx
, *pwx
= &wx
;
2854 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2855 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2856 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2859 clear_msacsr_cause(env
);
2863 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2864 if (NUMBER_QNAN_PAIR(pws
->w
[i
], pwt
->w
[i
], 32, status
)) {
2865 MSA_FLOAT_MAXOP(pwx
->w
[i
], max
, pws
->w
[i
], pws
->w
[i
], 32);
2866 } else if (NUMBER_QNAN_PAIR(pwt
->w
[i
], pws
->w
[i
], 32, status
)) {
2867 MSA_FLOAT_MAXOP(pwx
->w
[i
], max
, pwt
->w
[i
], pwt
->w
[i
], 32);
2869 MSA_FLOAT_MAXOP(pwx
->w
[i
], max
, pws
->w
[i
], pwt
->w
[i
], 32);
2874 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2875 if (NUMBER_QNAN_PAIR(pws
->d
[i
], pwt
->d
[i
], 64, status
)) {
2876 MSA_FLOAT_MAXOP(pwx
->d
[i
], max
, pws
->d
[i
], pws
->d
[i
], 64);
2877 } else if (NUMBER_QNAN_PAIR(pwt
->d
[i
], pws
->d
[i
], 64, status
)) {
2878 MSA_FLOAT_MAXOP(pwx
->d
[i
], max
, pwt
->d
[i
], pwt
->d
[i
], 64);
2880 MSA_FLOAT_MAXOP(pwx
->d
[i
], max
, pws
->d
[i
], pwt
->d
[i
], 64);
2888 check_msacsr_cause(env
, GETPC());
2890 msa_move_v(pwd
, pwx
);
2893 void helper_msa_fmax_a_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2894 uint32_t ws
, uint32_t wt
)
2896 float_status
*status
= &env
->active_tc
.msa_fp_status
;
2897 wr_t wx
, *pwx
= &wx
;
2898 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2899 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2900 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2903 clear_msacsr_cause(env
);
2907 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2908 FMAXMIN_A(max
, min
, pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, status
);
2912 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2913 FMAXMIN_A(max
, min
, pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, status
);
2920 check_msacsr_cause(env
, GETPC());
2922 msa_move_v(pwd
, pwx
);
2925 void helper_msa_fclass_df(CPUMIPSState
*env
, uint32_t df
,
2926 uint32_t wd
, uint32_t ws
)
2928 float_status
* status
= &env
->active_tc
.msa_fp_status
;
2930 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2931 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2932 if (df
== DF_WORD
) {
2933 pwd
->w
[0] = float_class_s(pws
->w
[0], status
);
2934 pwd
->w
[1] = float_class_s(pws
->w
[1], status
);
2935 pwd
->w
[2] = float_class_s(pws
->w
[2], status
);
2936 pwd
->w
[3] = float_class_s(pws
->w
[3], status
);
2938 pwd
->d
[0] = float_class_d(pws
->d
[0], status
);
2939 pwd
->d
[1] = float_class_d(pws
->d
[1], status
);
2943 #define MSA_FLOAT_UNOP0(DEST, OP, ARG, BITS) \
2945 float_status *status = &env->active_tc.msa_fp_status; \
2948 set_float_exception_flags(0, status); \
2949 DEST = float ## BITS ## _ ## OP(ARG, status); \
2950 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2952 if (get_enabled_exceptions(env, c)) { \
2953 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2954 } else if (float ## BITS ## _is_any_nan(ARG)) { \
2959 void helper_msa_ftrunc_s_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2962 wr_t wx
, *pwx
= &wx
;
2963 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2964 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2967 clear_msacsr_cause(env
);
2971 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2972 MSA_FLOAT_UNOP0(pwx
->w
[i
], to_int32_round_to_zero
, pws
->w
[i
], 32);
2976 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2977 MSA_FLOAT_UNOP0(pwx
->d
[i
], to_int64_round_to_zero
, pws
->d
[i
], 64);
2984 check_msacsr_cause(env
, GETPC());
2986 msa_move_v(pwd
, pwx
);
2989 void helper_msa_ftrunc_u_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2992 wr_t wx
, *pwx
= &wx
;
2993 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2994 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2997 clear_msacsr_cause(env
);
3001 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3002 MSA_FLOAT_UNOP0(pwx
->w
[i
], to_uint32_round_to_zero
, pws
->w
[i
], 32);
3006 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3007 MSA_FLOAT_UNOP0(pwx
->d
[i
], to_uint64_round_to_zero
, pws
->d
[i
], 64);
3014 check_msacsr_cause(env
, GETPC());
3016 msa_move_v(pwd
, pwx
);
3019 void helper_msa_fsqrt_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3022 wr_t wx
, *pwx
= &wx
;
3023 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3024 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3027 clear_msacsr_cause(env
);
3031 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3032 MSA_FLOAT_UNOP(pwx
->w
[i
], sqrt
, pws
->w
[i
], 32);
3036 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3037 MSA_FLOAT_UNOP(pwx
->d
[i
], sqrt
, pws
->d
[i
], 64);
3044 check_msacsr_cause(env
, GETPC());
3046 msa_move_v(pwd
, pwx
);
3049 #define MSA_FLOAT_RECIPROCAL(DEST, ARG, BITS) \
3051 float_status *status = &env->active_tc.msa_fp_status; \
3054 set_float_exception_flags(0, status); \
3055 DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \
3056 c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \
3057 float ## BITS ## _is_quiet_nan(DEST, status) ? \
3058 0 : RECIPROCAL_INEXACT, \
3059 IS_DENORMAL(DEST, BITS)); \
3061 if (get_enabled_exceptions(env, c)) { \
3062 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3066 void helper_msa_frsqrt_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3069 wr_t wx
, *pwx
= &wx
;
3070 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3071 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3074 clear_msacsr_cause(env
);
3078 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3079 MSA_FLOAT_RECIPROCAL(pwx
->w
[i
], float32_sqrt(pws
->w
[i
],
3080 &env
->active_tc
.msa_fp_status
), 32);
3084 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3085 MSA_FLOAT_RECIPROCAL(pwx
->d
[i
], float64_sqrt(pws
->d
[i
],
3086 &env
->active_tc
.msa_fp_status
), 64);
3093 check_msacsr_cause(env
, GETPC());
3095 msa_move_v(pwd
, pwx
);
3098 void helper_msa_frcp_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3101 wr_t wx
, *pwx
= &wx
;
3102 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3103 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3106 clear_msacsr_cause(env
);
3110 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3111 MSA_FLOAT_RECIPROCAL(pwx
->w
[i
], pws
->w
[i
], 32);
3115 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3116 MSA_FLOAT_RECIPROCAL(pwx
->d
[i
], pws
->d
[i
], 64);
3123 check_msacsr_cause(env
, GETPC());
3125 msa_move_v(pwd
, pwx
);
3128 void helper_msa_frint_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3131 wr_t wx
, *pwx
= &wx
;
3132 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3133 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3136 clear_msacsr_cause(env
);
3140 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3141 MSA_FLOAT_UNOP(pwx
->w
[i
], round_to_int
, pws
->w
[i
], 32);
3145 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3146 MSA_FLOAT_UNOP(pwx
->d
[i
], round_to_int
, pws
->d
[i
], 64);
3153 check_msacsr_cause(env
, GETPC());
3155 msa_move_v(pwd
, pwx
);
3158 #define MSA_FLOAT_LOGB(DEST, ARG, BITS) \
3160 float_status *status = &env->active_tc.msa_fp_status; \
3163 set_float_exception_flags(0, status); \
3164 set_float_rounding_mode(float_round_down, status); \
3165 DEST = float ## BITS ## _ ## log2(ARG, status); \
3166 DEST = float ## BITS ## _ ## round_to_int(DEST, status); \
3167 set_float_rounding_mode(ieee_rm[(env->active_tc.msacsr & \
3168 MSACSR_RM_MASK) >> MSACSR_RM], \
3171 set_float_exception_flags(get_float_exception_flags(status) & \
3172 (~float_flag_inexact), \
3175 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
3177 if (get_enabled_exceptions(env, c)) { \
3178 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3182 void helper_msa_flog2_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3185 wr_t wx
, *pwx
= &wx
;
3186 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3187 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3190 clear_msacsr_cause(env
);
3194 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3195 MSA_FLOAT_LOGB(pwx
->w
[i
], pws
->w
[i
], 32);
3199 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3200 MSA_FLOAT_LOGB(pwx
->d
[i
], pws
->d
[i
], 64);
3207 check_msacsr_cause(env
, GETPC());
3209 msa_move_v(pwd
, pwx
);
3212 void helper_msa_fexupl_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3215 wr_t wx
, *pwx
= &wx
;
3216 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3217 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3220 clear_msacsr_cause(env
);
3224 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3225 /* Half precision floats come in two formats: standard
3226 IEEE and "ARM" format. The latter gains extra exponent
3227 range by omitting the NaN/Inf encodings. */
3230 MSA_FLOAT_BINOP(pwx
->w
[i
], from_float16
, Lh(pws
, i
), ieee
, 32);
3234 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3235 MSA_FLOAT_UNOP(pwx
->d
[i
], from_float32
, Lw(pws
, i
), 64);
3242 check_msacsr_cause(env
, GETPC());
3243 msa_move_v(pwd
, pwx
);
3246 void helper_msa_fexupr_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3249 wr_t wx
, *pwx
= &wx
;
3250 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3251 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3254 clear_msacsr_cause(env
);
3258 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3259 /* Half precision floats come in two formats: standard
3260 IEEE and "ARM" format. The latter gains extra exponent
3261 range by omitting the NaN/Inf encodings. */
3264 MSA_FLOAT_BINOP(pwx
->w
[i
], from_float16
, Rh(pws
, i
), ieee
, 32);
3268 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3269 MSA_FLOAT_UNOP(pwx
->d
[i
], from_float32
, Rw(pws
, i
), 64);
3276 check_msacsr_cause(env
, GETPC());
3277 msa_move_v(pwd
, pwx
);
3280 void helper_msa_ffql_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3283 wr_t wx
, *pwx
= &wx
;
3284 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3285 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3290 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3291 MSA_FLOAT_UNOP(pwx
->w
[i
], from_q16
, Lh(pws
, i
), 32);
3295 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3296 MSA_FLOAT_UNOP(pwx
->d
[i
], from_q32
, Lw(pws
, i
), 64);
3303 msa_move_v(pwd
, pwx
);
3306 void helper_msa_ffqr_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3309 wr_t wx
, *pwx
= &wx
;
3310 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3311 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3316 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3317 MSA_FLOAT_UNOP(pwx
->w
[i
], from_q16
, Rh(pws
, i
), 32);
3321 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3322 MSA_FLOAT_UNOP(pwx
->d
[i
], from_q32
, Rw(pws
, i
), 64);
3329 msa_move_v(pwd
, pwx
);
3332 void helper_msa_ftint_s_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3335 wr_t wx
, *pwx
= &wx
;
3336 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3337 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3340 clear_msacsr_cause(env
);
3344 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3345 MSA_FLOAT_UNOP0(pwx
->w
[i
], to_int32
, pws
->w
[i
], 32);
3349 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3350 MSA_FLOAT_UNOP0(pwx
->d
[i
], to_int64
, pws
->d
[i
], 64);
3357 check_msacsr_cause(env
, GETPC());
3359 msa_move_v(pwd
, pwx
);
3362 void helper_msa_ftint_u_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3365 wr_t wx
, *pwx
= &wx
;
3366 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3367 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3370 clear_msacsr_cause(env
);
3374 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3375 MSA_FLOAT_UNOP0(pwx
->w
[i
], to_uint32
, pws
->w
[i
], 32);
3379 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3380 MSA_FLOAT_UNOP0(pwx
->d
[i
], to_uint64
, pws
->d
[i
], 64);
3387 check_msacsr_cause(env
, GETPC());
3389 msa_move_v(pwd
, pwx
);
3392 #define float32_from_int32 int32_to_float32
3393 #define float32_from_uint32 uint32_to_float32
3395 #define float64_from_int64 int64_to_float64
3396 #define float64_from_uint64 uint64_to_float64
3398 void helper_msa_ffint_s_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3401 wr_t wx
, *pwx
= &wx
;
3402 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3403 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3406 clear_msacsr_cause(env
);
3410 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3411 MSA_FLOAT_UNOP(pwx
->w
[i
], from_int32
, pws
->w
[i
], 32);
3415 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3416 MSA_FLOAT_UNOP(pwx
->d
[i
], from_int64
, pws
->d
[i
], 64);
3423 check_msacsr_cause(env
, GETPC());
3425 msa_move_v(pwd
, pwx
);
3428 void helper_msa_ffint_u_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3431 wr_t wx
, *pwx
= &wx
;
3432 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3433 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3436 clear_msacsr_cause(env
);
3440 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3441 MSA_FLOAT_UNOP(pwx
->w
[i
], from_uint32
, pws
->w
[i
], 32);
3445 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3446 MSA_FLOAT_UNOP(pwx
->d
[i
], from_uint64
, pws
->d
[i
], 64);
3453 check_msacsr_cause(env
, GETPC());
3455 msa_move_v(pwd
, pwx
);