target-arm/helper.c

   1 #include "qemu/osdep.h"
   2 #include "cpu.h"
   3 #include "internals.h"
   4 #include "exec/gdbstub.h"
   5 #include "exec/helper-proto.h"
   6 #include "qemu/host-utils.h"
   7 #include "sysemu/arch_init.h"
   8 #include "sysemu/sysemu.h"
   9 #include "qemu/bitops.h"
  10 #include "qemu/crc32c.h"
  11 #include "exec/cpu_ldst.h"
  12 #include "arm_ldst.h"
  13 #include <zlib.h> /* For crc32 */
  14 #include "exec/semihost.h"
  15 #include "sysemu/kvm.h"
  16
  17 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
  18
  19 #ifndef CONFIG_USER_ONLY
  20 static bool get_phys_addr(CPUARMState *env, target_ulong address,
  21                           int access_type, ARMMMUIdx mmu_idx,
  22                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
  23                           target_ulong *page_size, uint32_t *fsr,
  24                           ARMMMUFaultInfo *fi);
  25
  26 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
  27                                int access_type, ARMMMUIdx mmu_idx,
  28                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
  29                                target_ulong *page_size_ptr, uint32_t *fsr,
  30                                ARMMMUFaultInfo *fi);
  31
  32 /* Definitions for the PMCCNTR and PMCR registers */
  33 #define PMCRD   0x8
  34 #define PMCRC   0x4
  35 #define PMCRE   0x1
  36 #endif
  37
  38 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  39 {
  40     int nregs;
  41
  42     /* VFP data registers are always little-endian.  */
  43     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  44     if (reg < nregs) {
  45         stfq_le_p(buf, env->vfp.regs[reg]);
  46         return 8;
  47     }
  48     if (arm_feature(env, ARM_FEATURE_NEON)) {
  49         /* Aliases for Q regs.  */
  50         nregs += 16;
  51         if (reg < nregs) {
  52             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  53             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  54             return 16;
  55         }
  56     }
  57     switch (reg - nregs) {
  58     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  59     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  60     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  61     }
  62     return 0;
  63 }
  64
  65 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  66 {
  67     int nregs;
  68
  69     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  70     if (reg < nregs) {
  71         env->vfp.regs[reg] = ldfq_le_p(buf);
  72         return 8;
  73     }
  74     if (arm_feature(env, ARM_FEATURE_NEON)) {
  75         nregs += 16;
  76         if (reg < nregs) {
  77             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  78             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  79             return 16;
  80         }
  81     }
  82     switch (reg - nregs) {
  83     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  84     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  85     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  86     }
  87     return 0;
  88 }
  89
  90 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  91 {
  92     switch (reg) {
  93     case 0 ... 31:
  94         /* 128 bit FP register */
  95         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  96         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  97         return 16;
  98     case 32:
  99         /* FPSR */
 100         stl_p(buf, vfp_get_fpsr(env));
 101         return 4;
 102     case 33:
 103         /* FPCR */
 104         stl_p(buf, vfp_get_fpcr(env));
 105         return 4;
 106     default:
 107         return 0;
 108     }
 109 }
 110
 111 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 112 {
 113     switch (reg) {
 114     case 0 ... 31:
 115         /* 128 bit FP register */
 116         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 117         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 118         return 16;
 119     case 32:
 120         /* FPSR */
 121         vfp_set_fpsr(env, ldl_p(buf));
 122         return 4;
 123     case 33:
 124         /* FPCR */
 125         vfp_set_fpcr(env, ldl_p(buf));
 126         return 4;
 127     default:
 128         return 0;
 129     }
 130 }
 131
 132 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 133 {
 134     assert(ri->fieldoffset);
 135     if (cpreg_field_is_64bit(ri)) {
 136         return CPREG_FIELD64(env, ri);
 137     } else {
 138         return CPREG_FIELD32(env, ri);
 139     }
 140 }
 141
 142 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 143                       uint64_t value)
 144 {
 145     assert(ri->fieldoffset);
 146     if (cpreg_field_is_64bit(ri)) {
 147         CPREG_FIELD64(env, ri) = value;
 148     } else {
 149         CPREG_FIELD32(env, ri) = value;
 150     }
 151 }
 152
 153 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
 154 {
 155     return (char *)env + ri->fieldoffset;
 156 }
 157
 158 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 159 {
 160     /* Raw read of a coprocessor register (as needed for migration, etc). */
 161     if (ri->type & ARM_CP_CONST) {
 162         return ri->resetvalue;
 163     } else if (ri->raw_readfn) {
 164         return ri->raw_readfn(env, ri);
 165     } else if (ri->readfn) {
 166         return ri->readfn(env, ri);
 167     } else {
 168         return raw_read(env, ri);
 169     }
 170 }
 171
 172 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 173                              uint64_t v)
 174 {
 175     /* Raw write of a coprocessor register (as needed for migration, etc).
 176      * Note that constant registers are treated as write-ignored; the
 177      * caller should check for success by whether a readback gives the
 178      * value written.
 179      */
 180     if (ri->type & ARM_CP_CONST) {
 181         return;
 182     } else if (ri->raw_writefn) {
 183         ri->raw_writefn(env, ri, v);
 184     } else if (ri->writefn) {
 185         ri->writefn(env, ri, v);
 186     } else {
 187         raw_write(env, ri, v);
 188     }
 189 }
 190
 191 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
 192 {
 193    /* Return true if the regdef would cause an assertion if you called
 194     * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
 195     * program bug for it not to have the NO_RAW flag).
 196     * NB that returning false here doesn't necessarily mean that calling
 197     * read/write_raw_cp_reg() is safe, because we can't distinguish "has
 198     * read/write access functions which are safe for raw use" from "has
 199     * read/write access functions which have side effects but has forgotten
 200     * to provide raw access functions".
 201     * The tests here line up with the conditions in read/write_raw_cp_reg()
 202     * and assertions in raw_read()/raw_write().
 203     */
 204     if ((ri->type & ARM_CP_CONST) ||
 205         ri->fieldoffset ||
 206         ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
 207         return false;
 208     }
 209     return true;
 210 }
 211
 212 bool write_cpustate_to_list(ARMCPU *cpu)
 213 {
 214     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 215     int i;
 216     bool ok = true;
 217
 218     for (i = 0; i < cpu->cpreg_array_len; i++) {
 219         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 220         const ARMCPRegInfo *ri;
 221
 222         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 223         if (!ri) {
 224             ok = false;
 225             continue;
 226         }
 227         if (ri->type & ARM_CP_NO_RAW) {
 228             continue;
 229         }
 230         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 231     }
 232     return ok;
 233 }
 234
 235 bool write_list_to_cpustate(ARMCPU *cpu)
 236 {
 237     int i;
 238     bool ok = true;
 239
 240     for (i = 0; i < cpu->cpreg_array_len; i++) {
 241         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 242         uint64_t v = cpu->cpreg_values[i];
 243         const ARMCPRegInfo *ri;
 244
 245         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 246         if (!ri) {
 247             ok = false;
 248             continue;
 249         }
 250         if (ri->type & ARM_CP_NO_RAW) {
 251             continue;
 252         }
 253         /* Write value and confirm it reads back as written
 254          * (to catch read-only registers and partially read-only
 255          * registers where the incoming migration value doesn't match)
 256          */
 257         write_raw_cp_reg(&cpu->env, ri, v);
 258         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 259             ok = false;
 260         }
 261     }
 262     return ok;
 263 }
 264
 265 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 266 {
 267     ARMCPU *cpu = opaque;
 268     uint64_t regidx;
 269     const ARMCPRegInfo *ri;
 270
 271     regidx = *(uint32_t *)key;
 272     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 273
 274     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 275         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 276         /* The value array need not be initialized at this point */
 277         cpu->cpreg_array_len++;
 278     }
 279 }
 280
 281 static void count_cpreg(gpointer key, gpointer opaque)
 282 {
 283     ARMCPU *cpu = opaque;
 284     uint64_t regidx;
 285     const ARMCPRegInfo *ri;
 286
 287     regidx = *(uint32_t *)key;
 288     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 289
 290     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 291         cpu->cpreg_array_len++;
 292     }
 293 }
 294
 295 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 296 {
 297     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 298     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 299
 300     if (aidx > bidx) {
 301         return 1;
 302     }
 303     if (aidx < bidx) {
 304         return -1;
 305     }
 306     return 0;
 307 }
 308
 309 void init_cpreg_list(ARMCPU *cpu)
 310 {
 311     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 312      * Note that we require cpreg_tuples[] to be sorted by key ID.
 313      */
 314     GList *keys;
 315     int arraylen;
 316
 317     keys = g_hash_table_get_keys(cpu->cp_regs);
 318     keys = g_list_sort(keys, cpreg_key_compare);
 319
 320     cpu->cpreg_array_len = 0;
 321
 322     g_list_foreach(keys, count_cpreg, cpu);
 323
 324     arraylen = cpu->cpreg_array_len;
 325     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 326     cpu->cpreg_values = g_new(uint64_t, arraylen);
 327     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 328     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 329     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 330     cpu->cpreg_array_len = 0;
 331
 332     g_list_foreach(keys, add_cpreg_to_list, cpu);
 333
 334     assert(cpu->cpreg_array_len == arraylen);
 335
 336     g_list_free(keys);
 337 }
 338
 339 /*
 340  * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
 341  * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
 342  *
 343  * access_el3_aa32ns: Used to check AArch32 register views.
 344  * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
 345  */
 346 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
 347                                         const ARMCPRegInfo *ri)
 348 {
 349     bool secure = arm_is_secure_below_el3(env);
 350
 351     assert(!arm_el_is_aa64(env, 3));
 352     if (secure) {
 353         return CP_ACCESS_TRAP_UNCATEGORIZED;
 354     }
 355     return CP_ACCESS_OK;
 356 }
 357
 358 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
 359                                                 const ARMCPRegInfo *ri)
 360 {
 361     if (!arm_el_is_aa64(env, 3)) {
 362         return access_el3_aa32ns(env, ri);
 363     }
 364     return CP_ACCESS_OK;
 365 }
 366
 367 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 368 {
 369     ARMCPU *cpu = arm_env_get_cpu(env);
 370
 371     raw_write(env, ri, value);
 372     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 373 }
 374
 375 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 376 {
 377     ARMCPU *cpu = arm_env_get_cpu(env);
 378
 379     if (raw_read(env, ri) != value) {
 380         /* Unlike real hardware the qemu TLB uses virtual addresses,
 381          * not modified virtual addresses, so this causes a TLB flush.
 382          */
 383         tlb_flush(CPU(cpu), 1);
 384         raw_write(env, ri, value);
 385     }
 386 }
 387
 388 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 389                              uint64_t value)
 390 {
 391     ARMCPU *cpu = arm_env_get_cpu(env);
 392
 393     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 394         && !extended_addresses_enabled(env)) {
 395         /* For VMSA (when not using the LPAE long descriptor page table
 396          * format) this register includes the ASID, so do a TLB flush.
 397          * For PMSA it is purely a process ID and no action is needed.
 398          */
 399         tlb_flush(CPU(cpu), 1);
 400     }
 401     raw_write(env, ri, value);
 402 }
 403
 404 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 405                           uint64_t value)
 406 {
 407     /* Invalidate all (TLBIALL) */
 408     ARMCPU *cpu = arm_env_get_cpu(env);
 409
 410     tlb_flush(CPU(cpu), 1);
 411 }
 412
 413 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 414                           uint64_t value)
 415 {
 416     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 417     ARMCPU *cpu = arm_env_get_cpu(env);
 418
 419     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 420 }
 421
 422 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 423                            uint64_t value)
 424 {
 425     /* Invalidate by ASID (TLBIASID) */
 426     ARMCPU *cpu = arm_env_get_cpu(env);
 427
 428     tlb_flush(CPU(cpu), value == 0);
 429 }
 430
 431 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 432                            uint64_t value)
 433 {
 434     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 435     ARMCPU *cpu = arm_env_get_cpu(env);
 436
 437     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 438 }
 439
 440 /* IS variants of TLB operations must affect all cores */
 441 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 442                              uint64_t value)
 443 {
 444     CPUState *other_cs;
 445
 446     CPU_FOREACH(other_cs) {
 447         tlb_flush(other_cs, 1);
 448     }
 449 }
 450
 451 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 452                              uint64_t value)
 453 {
 454     CPUState *other_cs;
 455
 456     CPU_FOREACH(other_cs) {
 457         tlb_flush(other_cs, value == 0);
 458     }
 459 }
 460
 461 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 462                              uint64_t value)
 463 {
 464     CPUState *other_cs;
 465
 466     CPU_FOREACH(other_cs) {
 467         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 468     }
 469 }
 470
 471 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 472                              uint64_t value)
 473 {
 474     CPUState *other_cs;
 475
 476     CPU_FOREACH(other_cs) {
 477         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 478     }
 479 }
 480
 481 static const ARMCPRegInfo cp_reginfo[] = {
 482     /* Define the secure and non-secure FCSE identifier CP registers
 483      * separately because there is no secure bank in V8 (no _EL3).  This allows
 484      * the secure register to be properly reset and migrated. There is also no
 485      * v8 EL1 version of the register so the non-secure instance stands alone.
 486      */
 487     { .name = "FCSEIDR(NS)",
 488       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 489       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 490       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
 491       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 492     { .name = "FCSEIDR(S)",
 493       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 494       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 495       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
 496       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 497     /* Define the secure and non-secure context identifier CP registers
 498      * separately because there is no secure bank in V8 (no _EL3).  This allows
 499      * the secure register to be properly reset and migrated.  In the
 500      * non-secure case, the 32-bit register will have reset and migration
 501      * disabled during registration as it is handled by the 64-bit instance.
 502      */
 503     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
 504       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 505       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 506       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
 507       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 508     { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
 509       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 510       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 511       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
 512       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 513     REGINFO_SENTINEL
 514 };
 515
 516 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 517     /* NB: Some of these registers exist in v8 but with more precise
 518      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 519      */
 520     /* MMU Domain access control / MPU write buffer control */
 521     { .name = "DACR",
 522       .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
 523       .access = PL1_RW, .resetvalue = 0,
 524       .writefn = dacr_write, .raw_writefn = raw_write,
 525       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
 526                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
 527     /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
 528      * For v6 and v5, these mappings are overly broad.
 529      */
 530     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
 531       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 532     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
 533       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 534     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
 535       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 536     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
 537       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 538     /* Cache maintenance ops; some of this space may be overridden later. */
 539     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 540       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 541       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 542     REGINFO_SENTINEL
 543 };
 544
 545 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 546     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 547      * over-broad.
 548      */
 549     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 550       .access = PL1_W, .type = ARM_CP_WFI },
 551     REGINFO_SENTINEL
 552 };
 553
 554 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 555     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 556      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 557      */
 558     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 559       .access = PL1_W, .type = ARM_CP_WFI },
 560     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 561      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 562      * OMAPCP will override this space.
 563      */
 564     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 565       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 566       .resetvalue = 0 },
 567     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 568       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 569       .resetvalue = 0 },
 570     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 571     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 572       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
 573       .resetvalue = 0 },
 574     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 575      * implementing it as RAZ means the "debug architecture version" bits
 576      * will read as a reserved value, which should cause Linux to not try
 577      * to use the debug hardware.
 578      */
 579     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 580       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 581     /* MMU TLB control. Note that the wildcarding means we cover not just
 582      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 583      */
 584     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 585       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 586       .type = ARM_CP_NO_RAW },
 587     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 588       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 589       .type = ARM_CP_NO_RAW },
 590     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 591       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 592       .type = ARM_CP_NO_RAW },
 593     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 594       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 595       .type = ARM_CP_NO_RAW },
 596     { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
 597       .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
 598     { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
 599       .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
 600     REGINFO_SENTINEL
 601 };
 602
 603 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 604                         uint64_t value)
 605 {
 606     uint32_t mask = 0;
 607
 608     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 609     if (!arm_feature(env, ARM_FEATURE_V8)) {
 610         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 611          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 612          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 613          */
 614         if (arm_feature(env, ARM_FEATURE_VFP)) {
 615             /* VFP coprocessor: cp10 & cp11 [23:20] */
 616             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 617
 618             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 619                 /* ASEDIS [31] bit is RAO/WI */
 620                 value |= (1 << 31);
 621             }
 622
 623             /* VFPv3 and upwards with NEON implement 32 double precision
 624              * registers (D0-D31).
 625              */
 626             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 627                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 628                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 629                 value |= (1 << 30);
 630             }
 631         }
 632         value &= mask;
 633     }
 634     env->cp15.cpacr_el1 = value;
 635 }
 636
 637 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 638 {
 639     if (arm_feature(env, ARM_FEATURE_V8)) {
 640         /* Check if CPACR accesses are to be trapped to EL2 */
 641         if (arm_current_el(env) == 1 &&
 642             (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
 643             return CP_ACCESS_TRAP_EL2;
 644         /* Check if CPACR accesses are to be trapped to EL3 */
 645         } else if (arm_current_el(env) < 3 &&
 646                    (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 647             return CP_ACCESS_TRAP_EL3;
 648         }
 649     }
 650
 651     return CP_ACCESS_OK;
 652 }
 653
 654 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 655 {
 656     /* Check if CPTR accesses are set to trap to EL3 */
 657     if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 658         return CP_ACCESS_TRAP_EL3;
 659     }
 660
 661     return CP_ACCESS_OK;
 662 }
 663
 664 static const ARMCPRegInfo v6_cp_reginfo[] = {
 665     /* prefetch by MVA in v6, NOP in v7 */
 666     { .name = "MVA_prefetch",
 667       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 668       .access = PL1_W, .type = ARM_CP_NOP },
 669     /* We need to break the TB after ISB to execute self-modifying code
 670      * correctly and also to take any pending interrupts immediately.
 671      * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
 672      */
 673     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 674       .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
 675     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 676       .access = PL0_W, .type = ARM_CP_NOP },
 677     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 678       .access = PL0_W, .type = ARM_CP_NOP },
 679     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 680       .access = PL1_RW,
 681       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
 682                              offsetof(CPUARMState, cp15.ifar_ns) },
 683       .resetvalue = 0, },
 684     /* Watchpoint Fault Address Register : should actually only be present
 685      * for 1136, 1176, 11MPCore.
 686      */
 687     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 688       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 689     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 690       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
 691       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
 692       .resetvalue = 0, .writefn = cpacr_write },
 693     REGINFO_SENTINEL
 694 };
 695
 696 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 697 {
 698     /* Performance monitor registers user accessibility is controlled
 699      * by PMUSERENR.
 700      */
 701     if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) {
 702         return CP_ACCESS_TRAP;
 703     }
 704     return CP_ACCESS_OK;
 705 }
 706
 707 #ifndef CONFIG_USER_ONLY
 708
 709 static inline bool arm_ccnt_enabled(CPUARMState *env)
 710 {
 711     /* This does not support checking PMCCFILTR_EL0 register */
 712
 713     if (!(env->cp15.c9_pmcr & PMCRE)) {
 714         return false;
 715     }
 716
 717     return true;
 718 }
 719
 720 void pmccntr_sync(CPUARMState *env)
 721 {
 722     uint64_t temp_ticks;
 723
 724     temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 725                           ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 726
 727     if (env->cp15.c9_pmcr & PMCRD) {
 728         /* Increment once every 64 processor clock cycles */
 729         temp_ticks /= 64;
 730     }
 731
 732     if (arm_ccnt_enabled(env)) {
 733         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 734     }
 735 }
 736
 737 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 738                        uint64_t value)
 739 {
 740     pmccntr_sync(env);
 741
 742     if (value & PMCRC) {
 743         /* The counter has been reset */
 744         env->cp15.c15_ccnt = 0;
 745     }
 746
 747     /* only the DP, X, D and E bits are writable */
 748     env->cp15.c9_pmcr &= ~0x39;
 749     env->cp15.c9_pmcr |= (value & 0x39);
 750
 751     pmccntr_sync(env);
 752 }
 753
 754 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 755 {
 756     uint64_t total_ticks;
 757
 758     if (!arm_ccnt_enabled(env)) {
 759         /* Counter is disabled, do not change value */
 760         return env->cp15.c15_ccnt;
 761     }
 762
 763     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 764                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 765
 766     if (env->cp15.c9_pmcr & PMCRD) {
 767         /* Increment once every 64 processor clock cycles */
 768         total_ticks /= 64;
 769     }
 770     return total_ticks - env->cp15.c15_ccnt;
 771 }
 772
 773 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 774                         uint64_t value)
 775 {
 776     uint64_t total_ticks;
 777
 778     if (!arm_ccnt_enabled(env)) {
 779         /* Counter is disabled, set the absolute value */
 780         env->cp15.c15_ccnt = value;
 781         return;
 782     }
 783
 784     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 785                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 786
 787     if (env->cp15.c9_pmcr & PMCRD) {
 788         /* Increment once every 64 processor clock cycles */
 789         total_ticks /= 64;
 790     }
 791     env->cp15.c15_ccnt = total_ticks - value;
 792 }
 793
 794 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 795                             uint64_t value)
 796 {
 797     uint64_t cur_val = pmccntr_read(env, NULL);
 798
 799     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 800 }
 801
 802 #else /* CONFIG_USER_ONLY */
 803
 804 void pmccntr_sync(CPUARMState *env)
 805 {
 806 }
 807
 808 #endif
 809
 810 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 811                             uint64_t value)
 812 {
 813     pmccntr_sync(env);
 814     env->cp15.pmccfiltr_el0 = value & 0x7E000000;
 815     pmccntr_sync(env);
 816 }
 817
 818 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 819                             uint64_t value)
 820 {
 821     value &= (1 << 31);
 822     env->cp15.c9_pmcnten |= value;
 823 }
 824
 825 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 826                              uint64_t value)
 827 {
 828     value &= (1 << 31);
 829     env->cp15.c9_pmcnten &= ~value;
 830 }
 831
 832 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 833                          uint64_t value)
 834 {
 835     env->cp15.c9_pmovsr &= ~value;
 836 }
 837
 838 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 839                              uint64_t value)
 840 {
 841     env->cp15.c9_pmxevtyper = value & 0xff;
 842 }
 843
 844 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 845                             uint64_t value)
 846 {
 847     env->cp15.c9_pmuserenr = value & 1;
 848 }
 849
 850 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 851                              uint64_t value)
 852 {
 853     /* We have no event counters so only the C bit can be changed */
 854     value &= (1 << 31);
 855     env->cp15.c9_pminten |= value;
 856 }
 857
 858 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 859                              uint64_t value)
 860 {
 861     value &= (1 << 31);
 862     env->cp15.c9_pminten &= ~value;
 863 }
 864
 865 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 866                        uint64_t value)
 867 {
 868     /* Note that even though the AArch64 view of this register has bits
 869      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 870      * architectural requirements for bits which are RES0 only in some
 871      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 872      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 873      */
 874     raw_write(env, ri, value & ~0x1FULL);
 875 }
 876
 877 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 878 {
 879     /* We only mask off bits that are RES0 both for AArch64 and AArch32.
 880      * For bits that vary between AArch32/64, code needs to check the
 881      * current execution mode before directly using the feature bit.
 882      */
 883     uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
 884
 885     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 886         valid_mask &= ~SCR_HCE;
 887
 888         /* On ARMv7, SMD (or SCD as it is called in v7) is only
 889          * supported if EL2 exists. The bit is UNK/SBZP when
 890          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
 891          * when EL2 is unavailable.
 892          * On ARMv8, this bit is always available.
 893          */
 894         if (arm_feature(env, ARM_FEATURE_V7) &&
 895             !arm_feature(env, ARM_FEATURE_V8)) {
 896             valid_mask &= ~SCR_SMD;
 897         }
 898     }
 899
 900     /* Clear all-context RES0 bits.  */
 901     value &= valid_mask;
 902     raw_write(env, ri, value);
 903 }
 904
 905 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 906 {
 907     ARMCPU *cpu = arm_env_get_cpu(env);
 908
 909     /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
 910      * bank
 911      */
 912     uint32_t index = A32_BANKED_REG_GET(env, csselr,
 913                                         ri->secure & ARM_CP_SECSTATE_S);
 914
 915     return cpu->ccsidr[index];
 916 }
 917
 918 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 919                          uint64_t value)
 920 {
 921     raw_write(env, ri, value & 0xf);
 922 }
 923
 924 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 925 {
 926     CPUState *cs = ENV_GET_CPU(env);
 927     uint64_t ret = 0;
 928
 929     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 930         ret |= CPSR_I;
 931     }
 932     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
 933         ret |= CPSR_F;
 934     }
 935     /* External aborts are not possible in QEMU so A bit is always clear */
 936     return ret;
 937 }
 938
 939 static const ARMCPRegInfo v7_cp_reginfo[] = {
 940     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 941     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 942       .access = PL1_W, .type = ARM_CP_NOP },
 943     /* Performance monitors are implementation defined in v7,
 944      * but with an ARM recommended set of registers, which we
 945      * follow (although we don't actually implement any counters)
 946      *
 947      * Performance registers fall into three categories:
 948      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 949      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 950      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 951      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 952      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 953      */
 954     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 955       .access = PL0_RW, .type = ARM_CP_ALIAS,
 956       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 957       .writefn = pmcntenset_write,
 958       .accessfn = pmreg_access,
 959       .raw_writefn = raw_write },
 960     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
 961       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
 962       .access = PL0_RW, .accessfn = pmreg_access,
 963       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
 964       .writefn = pmcntenset_write, .raw_writefn = raw_write },
 965     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 966       .access = PL0_RW,
 967       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 968       .accessfn = pmreg_access,
 969       .writefn = pmcntenclr_write,
 970       .type = ARM_CP_ALIAS },
 971     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
 972       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
 973       .access = PL0_RW, .accessfn = pmreg_access,
 974       .type = ARM_CP_ALIAS,
 975       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 976       .writefn = pmcntenclr_write },
 977     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 978       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 979       .accessfn = pmreg_access,
 980       .writefn = pmovsr_write,
 981       .raw_writefn = raw_write },
 982     /* Unimplemented so WI. */
 983     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 984       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
 985     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 986      * We choose to RAZ/WI.
 987      */
 988     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 989       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 990       .accessfn = pmreg_access },
 991 #ifndef CONFIG_USER_ONLY
 992     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 993       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
 994       .readfn = pmccntr_read, .writefn = pmccntr_write32,
 995       .accessfn = pmreg_access },
 996     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
 997       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
 998       .access = PL0_RW, .accessfn = pmreg_access,
 999       .type = ARM_CP_IO,
1000       .readfn = pmccntr_read, .writefn = pmccntr_write, },
1001 #endif
1002     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
1003       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
1004       .writefn = pmccfiltr_write,
1005       .access = PL0_RW, .accessfn = pmreg_access,
1006       .type = ARM_CP_IO,
1007       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
1008       .resetvalue = 0, },
1009     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
1010       .access = PL0_RW,
1011       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
1012       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
1013       .raw_writefn = raw_write },
1014     /* Unimplemented, RAZ/WI. */
1015     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
1016       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1017       .accessfn = pmreg_access },
1018     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
1019       .access = PL0_R | PL1_RW,
1020       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1021       .resetvalue = 0,
1022       .writefn = pmuserenr_write, .raw_writefn = raw_write },
1023     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
1024       .access = PL1_RW,
1025       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1026       .resetvalue = 0,
1027       .writefn = pmintenset_write, .raw_writefn = raw_write },
1028     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
1029       .access = PL1_RW, .type = ARM_CP_ALIAS,
1030       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1031       .writefn = pmintenclr_write, },
1032     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
1033       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
1034       .access = PL1_RW, .writefn = vbar_write,
1035       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
1036                              offsetof(CPUARMState, cp15.vbar_ns) },
1037       .resetvalue = 0 },
1038     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
1039       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
1040       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
1041     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
1042       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
1043       .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
1044       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
1045                              offsetof(CPUARMState, cp15.csselr_ns) } },
1046     /* Auxiliary ID register: this actually has an IMPDEF value but for now
1047      * just RAZ for all cores:
1048      */
1049     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1050       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1051       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1052     /* Auxiliary fault status registers: these also are IMPDEF, and we
1053      * choose to RAZ/WI for all cores.
1054      */
1055     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1056       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1057       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1058     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1059       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1060       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1061     /* MAIR can just read-as-written because we don't implement caches
1062      * and so don't need to care about memory attributes.
1063      */
1064     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1065       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1066       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1067       .resetvalue = 0 },
1068     { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
1069       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
1070       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1071       .resetvalue = 0 },
1072     /* For non-long-descriptor page tables these are PRRR and NMRR;
1073      * regardless they still act as reads-as-written for QEMU.
1074      */
1075      /* MAIR0/1 are defined separately from their 64-bit counterpart which
1076       * allows them to assign the correct fieldoffset based on the endianness
1077       * handled in the field definitions.
1078       */
1079     { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1080       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1081       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1082                              offsetof(CPUARMState, cp15.mair0_ns) },
1083       .resetfn = arm_cp_reset_ignore },
1084     { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
1085       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1086       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1087                              offsetof(CPUARMState, cp15.mair1_ns) },
1088       .resetfn = arm_cp_reset_ignore },
1089     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1090       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1091       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1092     /* 32 bit ITLB invalidates */
1093     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1094       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1095     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1096       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1097     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1098       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1099     /* 32 bit DTLB invalidates */
1100     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1101       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1102     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1103       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1104     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1105       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1106     /* 32 bit TLB invalidates */
1107     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1108       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1109     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1110       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1111     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1112       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1113     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1114       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1115     REGINFO_SENTINEL
1116 };
1117
1118 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1119     /* 32 bit TLB invalidates, Inner Shareable */
1120     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1121       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1122     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1123       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1124     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1125       .type = ARM_CP_NO_RAW, .access = PL1_W,
1126       .writefn = tlbiasid_is_write },
1127     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1128       .type = ARM_CP_NO_RAW, .access = PL1_W,
1129       .writefn = tlbimvaa_is_write },
1130     REGINFO_SENTINEL
1131 };
1132
1133 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1134                         uint64_t value)
1135 {
1136     value &= 1;
1137     env->teecr = value;
1138 }
1139
1140 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
1141 {
1142     if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1143         return CP_ACCESS_TRAP;
1144     }
1145     return CP_ACCESS_OK;
1146 }
1147
1148 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1149     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1150       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1151       .resetvalue = 0,
1152       .writefn = teecr_write },
1153     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1154       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1155       .accessfn = teehbr_access, .resetvalue = 0 },
1156     REGINFO_SENTINEL
1157 };
1158
1159 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1160     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1161       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1162       .access = PL0_RW,
1163       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1164     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1165       .access = PL0_RW,
1166       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1167                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1168       .resetfn = arm_cp_reset_ignore },
1169     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1170       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1171       .access = PL0_R|PL1_W,
1172       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1173       .resetvalue = 0},
1174     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1175       .access = PL0_R|PL1_W,
1176       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1177                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1178       .resetfn = arm_cp_reset_ignore },
1179     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1180       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1181       .access = PL1_RW,
1182       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1183     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1184       .access = PL1_RW,
1185       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1186                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1187       .resetvalue = 0 },
1188     REGINFO_SENTINEL
1189 };
1190
1191 #ifndef CONFIG_USER_ONLY
1192
1193 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
1194 {
1195     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1196     if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
1197         return CP_ACCESS_TRAP;
1198     }
1199     return CP_ACCESS_OK;
1200 }
1201
1202 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
1203 {
1204     unsigned int cur_el = arm_current_el(env);
1205     bool secure = arm_is_secure(env);
1206
1207     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1208     if (cur_el == 0 &&
1209         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1210         return CP_ACCESS_TRAP;
1211     }
1212
1213     if (arm_feature(env, ARM_FEATURE_EL2) &&
1214         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1215         !extract32(env->cp15.cnthctl_el2, 0, 1)) {
1216         return CP_ACCESS_TRAP_EL2;
1217     }
1218     return CP_ACCESS_OK;
1219 }
1220
1221 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
1222 {
1223     unsigned int cur_el = arm_current_el(env);
1224     bool secure = arm_is_secure(env);
1225
1226     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1227      * EL0[PV]TEN is zero.
1228      */
1229     if (cur_el == 0 &&
1230         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1231         return CP_ACCESS_TRAP;
1232     }
1233
1234     if (arm_feature(env, ARM_FEATURE_EL2) &&
1235         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1236         !extract32(env->cp15.cnthctl_el2, 1, 1)) {
1237         return CP_ACCESS_TRAP_EL2;
1238     }
1239     return CP_ACCESS_OK;
1240 }
1241
1242 static CPAccessResult gt_pct_access(CPUARMState *env,
1243                                          const ARMCPRegInfo *ri)
1244 {
1245     return gt_counter_access(env, GTIMER_PHYS);
1246 }
1247
1248 static CPAccessResult gt_vct_access(CPUARMState *env,
1249                                          const ARMCPRegInfo *ri)
1250 {
1251     return gt_counter_access(env, GTIMER_VIRT);
1252 }
1253
1254 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1255 {
1256     return gt_timer_access(env, GTIMER_PHYS);
1257 }
1258
1259 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1260 {
1261     return gt_timer_access(env, GTIMER_VIRT);
1262 }
1263
1264 static CPAccessResult gt_stimer_access(CPUARMState *env,
1265                                        const ARMCPRegInfo *ri)
1266 {
1267     /* The AArch64 register view of the secure physical timer is
1268      * always accessible from EL3, and configurably accessible from
1269      * Secure EL1.
1270      */
1271     switch (arm_current_el(env)) {
1272     case 1:
1273         if (!arm_is_secure(env)) {
1274             return CP_ACCESS_TRAP;
1275         }
1276         if (!(env->cp15.scr_el3 & SCR_ST)) {
1277             return CP_ACCESS_TRAP_EL3;
1278         }
1279         return CP_ACCESS_OK;
1280     case 0:
1281     case 2:
1282         return CP_ACCESS_TRAP;
1283     case 3:
1284         return CP_ACCESS_OK;
1285     default:
1286         g_assert_not_reached();
1287     }
1288 }
1289
1290 static uint64_t gt_get_countervalue(CPUARMState *env)
1291 {
1292     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1293 }
1294
1295 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1296 {
1297     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1298
1299     if (gt->ctl & 1) {
1300         /* Timer enabled: calculate and set current ISTATUS, irq, and
1301          * reset timer to when ISTATUS next has to change
1302          */
1303         uint64_t offset = timeridx == GTIMER_VIRT ?
1304                                       cpu->env.cp15.cntvoff_el2 : 0;
1305         uint64_t count = gt_get_countervalue(&cpu->env);
1306         /* Note that this must be unsigned 64 bit arithmetic: */
1307         int istatus = count - offset >= gt->cval;
1308         uint64_t nexttick;
1309
1310         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1311         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1312                      (istatus && !(gt->ctl & 2)));
1313         if (istatus) {
1314             /* Next transition is when count rolls back over to zero */
1315             nexttick = UINT64_MAX;
1316         } else {
1317             /* Next transition is when we hit cval */
1318             nexttick = gt->cval + offset;
1319         }
1320         /* Note that the desired next expiry time might be beyond the
1321          * signed-64-bit range of a QEMUTimer -- in this case we just
1322          * set the timer for as far in the future as possible. When the
1323          * timer expires we will reset the timer for any remaining period.
1324          */
1325         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1326             nexttick = INT64_MAX / GTIMER_SCALE;
1327         }
1328         timer_mod(cpu->gt_timer[timeridx], nexttick);
1329     } else {
1330         /* Timer disabled: ISTATUS and timer output always clear */
1331         gt->ctl &= ~4;
1332         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1333         timer_del(cpu->gt_timer[timeridx]);
1334     }
1335 }
1336
1337 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
1338                            int timeridx)
1339 {
1340     ARMCPU *cpu = arm_env_get_cpu(env);
1341
1342     timer_del(cpu->gt_timer[timeridx]);
1343 }
1344
1345 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1346 {
1347     return gt_get_countervalue(env);
1348 }
1349
1350 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1351 {
1352     return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
1353 }
1354
1355 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1356                           int timeridx,
1357                           uint64_t value)
1358 {
1359     env->cp15.c14_timer[timeridx].cval = value;
1360     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1361 }
1362
1363 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
1364                              int timeridx)
1365 {
1366     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1367
1368     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1369                       (gt_get_countervalue(env) - offset));
1370 }
1371
1372 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1373                           int timeridx,
1374                           uint64_t value)
1375 {
1376     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1377
1378     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
1379                                          sextract64(value, 0, 32);
1380     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1381 }
1382
1383 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1384                          int timeridx,
1385                          uint64_t value)
1386 {
1387     ARMCPU *cpu = arm_env_get_cpu(env);
1388     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1389
1390     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1391     if ((oldval ^ value) & 1) {
1392         /* Enable toggled */
1393         gt_recalc_timer(cpu, timeridx);
1394     } else if ((oldval ^ value) & 2) {
1395         /* IMASK toggled: don't need to recalculate,
1396          * just set the interrupt line based on ISTATUS
1397          */
1398         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1399                      (oldval & 4) && !(value & 2));
1400     }
1401 }
1402
1403 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1404 {
1405     gt_timer_reset(env, ri, GTIMER_PHYS);
1406 }
1407
1408 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1409                                uint64_t value)
1410 {
1411     gt_cval_write(env, ri, GTIMER_PHYS, value);
1412 }
1413
1414 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1415 {
1416     return gt_tval_read(env, ri, GTIMER_PHYS);
1417 }
1418
1419 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1420                                uint64_t value)
1421 {
1422     gt_tval_write(env, ri, GTIMER_PHYS, value);
1423 }
1424
1425 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1426                               uint64_t value)
1427 {
1428     gt_ctl_write(env, ri, GTIMER_PHYS, value);
1429 }
1430
1431 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1432 {
1433     gt_timer_reset(env, ri, GTIMER_VIRT);
1434 }
1435
1436 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1437                                uint64_t value)
1438 {
1439     gt_cval_write(env, ri, GTIMER_VIRT, value);
1440 }
1441
1442 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1443 {
1444     return gt_tval_read(env, ri, GTIMER_VIRT);
1445 }
1446
1447 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1448                                uint64_t value)
1449 {
1450     gt_tval_write(env, ri, GTIMER_VIRT, value);
1451 }
1452
1453 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1454                               uint64_t value)
1455 {
1456     gt_ctl_write(env, ri, GTIMER_VIRT, value);
1457 }
1458
1459 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
1460                               uint64_t value)
1461 {
1462     ARMCPU *cpu = arm_env_get_cpu(env);
1463
1464     raw_write(env, ri, value);
1465     gt_recalc_timer(cpu, GTIMER_VIRT);
1466 }
1467
1468 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1469 {
1470     gt_timer_reset(env, ri, GTIMER_HYP);
1471 }
1472
1473 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1474                               uint64_t value)
1475 {
1476     gt_cval_write(env, ri, GTIMER_HYP, value);
1477 }
1478
1479 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1480 {
1481     return gt_tval_read(env, ri, GTIMER_HYP);
1482 }
1483
1484 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1485                               uint64_t value)
1486 {
1487     gt_tval_write(env, ri, GTIMER_HYP, value);
1488 }
1489
1490 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1491                               uint64_t value)
1492 {
1493     gt_ctl_write(env, ri, GTIMER_HYP, value);
1494 }
1495
1496 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1497 {
1498     gt_timer_reset(env, ri, GTIMER_SEC);
1499 }
1500
1501 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1502                               uint64_t value)
1503 {
1504     gt_cval_write(env, ri, GTIMER_SEC, value);
1505 }
1506
1507 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1508 {
1509     return gt_tval_read(env, ri, GTIMER_SEC);
1510 }
1511
1512 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1513                               uint64_t value)
1514 {
1515     gt_tval_write(env, ri, GTIMER_SEC, value);
1516 }
1517
1518 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1519                               uint64_t value)
1520 {
1521     gt_ctl_write(env, ri, GTIMER_SEC, value);
1522 }
1523
1524 void arm_gt_ptimer_cb(void *opaque)
1525 {
1526     ARMCPU *cpu = opaque;
1527
1528     gt_recalc_timer(cpu, GTIMER_PHYS);
1529 }
1530
1531 void arm_gt_vtimer_cb(void *opaque)
1532 {
1533     ARMCPU *cpu = opaque;
1534
1535     gt_recalc_timer(cpu, GTIMER_VIRT);
1536 }
1537
1538 void arm_gt_htimer_cb(void *opaque)
1539 {
1540     ARMCPU *cpu = opaque;
1541
1542     gt_recalc_timer(cpu, GTIMER_HYP);
1543 }
1544
1545 void arm_gt_stimer_cb(void *opaque)
1546 {
1547     ARMCPU *cpu = opaque;
1548
1549     gt_recalc_timer(cpu, GTIMER_SEC);
1550 }
1551
1552 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1553     /* Note that CNTFRQ is purely reads-as-written for the benefit
1554      * of software; writing it doesn't actually change the timer frequency.
1555      * Our reset value matches the fixed frequency we implement the timer at.
1556      */
1557     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1558       .type = ARM_CP_ALIAS,
1559       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1560       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1561     },
1562     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1563       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1564       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1565       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1566       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1567     },
1568     /* overall control: mostly access permissions */
1569     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1570       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1571       .access = PL1_RW,
1572       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1573       .resetvalue = 0,
1574     },
1575     /* per-timer control */
1576     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1577       .secure = ARM_CP_SECSTATE_NS,
1578       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1579       .accessfn = gt_ptimer_access,
1580       .fieldoffset = offsetoflow32(CPUARMState,
1581                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1582       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1583     },
1584     { .name = "CNTP_CTL(S)",
1585       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1586       .secure = ARM_CP_SECSTATE_S,
1587       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1588       .accessfn = gt_ptimer_access,
1589       .fieldoffset = offsetoflow32(CPUARMState,
1590                                    cp15.c14_timer[GTIMER_SEC].ctl),
1591       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1592     },
1593     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1594       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1595       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1596       .accessfn = gt_ptimer_access,
1597       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1598       .resetvalue = 0,
1599       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1600     },
1601     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1602       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1603       .accessfn = gt_vtimer_access,
1604       .fieldoffset = offsetoflow32(CPUARMState,
1605                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1606       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1607     },
1608     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1609       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1610       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1611       .accessfn = gt_vtimer_access,
1612       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1613       .resetvalue = 0,
1614       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1615     },
1616     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1617     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1618       .secure = ARM_CP_SECSTATE_NS,
1619       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1620       .accessfn = gt_ptimer_access,
1621       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1622     },
1623     { .name = "CNTP_TVAL(S)",
1624       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1625       .secure = ARM_CP_SECSTATE_S,
1626       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1627       .accessfn = gt_ptimer_access,
1628       .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
1629     },
1630     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1631       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1632       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1633       .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
1634       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1635     },
1636     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1637       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1638       .accessfn = gt_vtimer_access,
1639       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1640     },
1641     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1642       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1643       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1644       .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
1645       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1646     },
1647     /* The counter itself */
1648     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1649       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1650       .accessfn = gt_pct_access,
1651       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1652     },
1653     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1654       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1655       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1656       .accessfn = gt_pct_access, .readfn = gt_cnt_read,
1657     },
1658     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1659       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1660       .accessfn = gt_vct_access,
1661       .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
1662     },
1663     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1664       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1665       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1666       .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
1667     },
1668     /* Comparison value, indicating when the timer goes off */
1669     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1670       .secure = ARM_CP_SECSTATE_NS,
1671       .access = PL1_RW | PL0_R,
1672       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1673       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1674       .accessfn = gt_ptimer_access,
1675       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1676     },
1677     { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2,
1678       .secure = ARM_CP_SECSTATE_S,
1679       .access = PL1_RW | PL0_R,
1680       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1681       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1682       .accessfn = gt_ptimer_access,
1683       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1684     },
1685     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1686       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1687       .access = PL1_RW | PL0_R,
1688       .type = ARM_CP_IO,
1689       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1690       .resetvalue = 0, .accessfn = gt_ptimer_access,
1691       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1692     },
1693     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1694       .access = PL1_RW | PL0_R,
1695       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1696       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1697       .accessfn = gt_vtimer_access,
1698       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1699     },
1700     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1701       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1702       .access = PL1_RW | PL0_R,
1703       .type = ARM_CP_IO,
1704       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1705       .resetvalue = 0, .accessfn = gt_vtimer_access,
1706       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1707     },
1708     /* Secure timer -- this is actually restricted to only EL3
1709      * and configurably Secure-EL1 via the accessfn.
1710      */
1711     { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
1712       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
1713       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
1714       .accessfn = gt_stimer_access,
1715       .readfn = gt_sec_tval_read,
1716       .writefn = gt_sec_tval_write,
1717       .resetfn = gt_sec_timer_reset,
1718     },
1719     { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
1720       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
1721       .type = ARM_CP_IO, .access = PL1_RW,
1722       .accessfn = gt_stimer_access,
1723       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
1724       .resetvalue = 0,
1725       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1726     },
1727     { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
1728       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
1729       .type = ARM_CP_IO, .access = PL1_RW,
1730       .accessfn = gt_stimer_access,
1731       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1732       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1733     },
1734     REGINFO_SENTINEL
1735 };
1736
1737 #else
1738 /* In user-mode none of the generic timer registers are accessible,
1739  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1740  * so instead just don't register any of them.
1741  */
1742 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1743     REGINFO_SENTINEL
1744 };
1745
1746 #endif
1747
1748 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1749 {
1750     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1751         raw_write(env, ri, value);
1752     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1753         raw_write(env, ri, value & 0xfffff6ff);
1754     } else {
1755         raw_write(env, ri, value & 0xfffff1ff);
1756     }
1757 }
1758
1759 #ifndef CONFIG_USER_ONLY
1760 /* get_phys_addr() isn't present for user-mode-only targets */
1761
1762 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1763 {
1764     if (ri->opc2 & 4) {
1765         /* The ATS12NSO* operations must trap to EL3 if executed in
1766          * Secure EL1 (which can only happen if EL3 is AArch64).
1767          * They are simply UNDEF if executed from NS EL1.
1768          * They function normally from EL2 or EL3.
1769          */
1770         if (arm_current_el(env) == 1) {
1771             if (arm_is_secure_below_el3(env)) {
1772                 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
1773             }
1774             return CP_ACCESS_TRAP_UNCATEGORIZED;
1775         }
1776     }
1777     return CP_ACCESS_OK;
1778 }
1779
1780 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
1781                              int access_type, ARMMMUIdx mmu_idx)
1782 {
1783     hwaddr phys_addr;
1784     target_ulong page_size;
1785     int prot;
1786     uint32_t fsr;
1787     bool ret;
1788     uint64_t par64;
1789     MemTxAttrs attrs = {};
1790     ARMMMUFaultInfo fi = {};
1791
1792     ret = get_phys_addr(env, value, access_type, mmu_idx,
1793                         &phys_addr, &attrs, &prot, &page_size, &fsr, &fi);
1794     if (extended_addresses_enabled(env)) {
1795         /* fsr is a DFSR/IFSR value for the long descriptor
1796          * translation table format, but with WnR always clear.
1797          * Convert it to a 64-bit PAR.
1798          */
1799         par64 = (1 << 11); /* LPAE bit always set */
1800         if (!ret) {
1801             par64 |= phys_addr & ~0xfffULL;
1802             if (!attrs.secure) {
1803                 par64 |= (1 << 9); /* NS */
1804             }
1805             /* We don't set the ATTR or SH fields in the PAR. */
1806         } else {
1807             par64 |= 1; /* F */
1808             par64 |= (fsr & 0x3f) << 1; /* FS */
1809             /* Note that S2WLK and FSTAGE are always zero, because we don't
1810              * implement virtualization and therefore there can't be a stage 2
1811              * fault.
1812              */
1813         }
1814     } else {
1815         /* fsr is a DFSR/IFSR value for the short descriptor
1816          * translation table format (with WnR always clear).
1817          * Convert it to a 32-bit PAR.
1818          */
1819         if (!ret) {
1820             /* We do not set any attribute bits in the PAR */
1821             if (page_size == (1 << 24)
1822                 && arm_feature(env, ARM_FEATURE_V7)) {
1823                 par64 = (phys_addr & 0xff000000) | (1 << 1);
1824             } else {
1825                 par64 = phys_addr & 0xfffff000;
1826             }
1827             if (!attrs.secure) {
1828                 par64 |= (1 << 9); /* NS */
1829             }
1830         } else {
1831             par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
1832                     ((fsr & 0xf) << 1) | 1;
1833         }
1834     }
1835     return par64;
1836 }
1837
1838 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1839 {
1840     int access_type = ri->opc2 & 1;
1841     uint64_t par64;
1842     ARMMMUIdx mmu_idx;
1843     int el = arm_current_el(env);
1844     bool secure = arm_is_secure_below_el3(env);
1845
1846     switch (ri->opc2 & 6) {
1847     case 0:
1848         /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
1849         switch (el) {
1850         case 3:
1851             mmu_idx = ARMMMUIdx_S1E3;
1852             break;
1853         case 2:
1854             mmu_idx = ARMMMUIdx_S1NSE1;
1855             break;
1856         case 1:
1857             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1858             break;
1859         default:
1860             g_assert_not_reached();
1861         }
1862         break;
1863     case 2:
1864         /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
1865         switch (el) {
1866         case 3:
1867             mmu_idx = ARMMMUIdx_S1SE0;
1868             break;
1869         case 2:
1870             mmu_idx = ARMMMUIdx_S1NSE0;
1871             break;
1872         case 1:
1873             mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1874             break;
1875         default:
1876             g_assert_not_reached();
1877         }
1878         break;
1879     case 4:
1880         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
1881         mmu_idx = ARMMMUIdx_S12NSE1;
1882         break;
1883     case 6:
1884         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
1885         mmu_idx = ARMMMUIdx_S12NSE0;
1886         break;
1887     default:
1888         g_assert_not_reached();
1889     }
1890
1891     par64 = do_ats_write(env, value, access_type, mmu_idx);
1892
1893     A32_BANKED_CURRENT_REG_SET(env, par, par64);
1894 }
1895
1896 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
1897                         uint64_t value)
1898 {
1899     int access_type = ri->opc2 & 1;
1900     uint64_t par64;
1901
1902     par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
1903
1904     A32_BANKED_CURRENT_REG_SET(env, par, par64);
1905 }
1906
1907 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri)
1908 {
1909     if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
1910         return CP_ACCESS_TRAP;
1911     }
1912     return CP_ACCESS_OK;
1913 }
1914
1915 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
1916                         uint64_t value)
1917 {
1918     int access_type = ri->opc2 & 1;
1919     ARMMMUIdx mmu_idx;
1920     int secure = arm_is_secure_below_el3(env);
1921
1922     switch (ri->opc2 & 6) {
1923     case 0:
1924         switch (ri->opc1) {
1925         case 0: /* AT S1E1R, AT S1E1W */
1926             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1927             break;
1928         case 4: /* AT S1E2R, AT S1E2W */
1929             mmu_idx = ARMMMUIdx_S1E2;
1930             break;
1931         case 6: /* AT S1E3R, AT S1E3W */
1932             mmu_idx = ARMMMUIdx_S1E3;
1933             break;
1934         default:
1935             g_assert_not_reached();
1936         }
1937         break;
1938     case 2: /* AT S1E0R, AT S1E0W */
1939         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1940         break;
1941     case 4: /* AT S12E1R, AT S12E1W */
1942         mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
1943         break;
1944     case 6: /* AT S12E0R, AT S12E0W */
1945         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
1946         break;
1947     default:
1948         g_assert_not_reached();
1949     }
1950
1951     env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
1952 }
1953 #endif
1954
1955 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1956     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1957       .access = PL1_RW, .resetvalue = 0,
1958       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
1959                              offsetoflow32(CPUARMState, cp15.par_ns) },
1960       .writefn = par_write },
1961 #ifndef CONFIG_USER_ONLY
1962     /* This underdecoding is safe because the reginfo is NO_RAW. */
1963     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1964       .access = PL1_W, .accessfn = ats_access,
1965       .writefn = ats_write, .type = ARM_CP_NO_RAW },
1966 #endif
1967     REGINFO_SENTINEL
1968 };
1969
1970 /* Return basic MPU access permission bits.  */
1971 static uint32_t simple_mpu_ap_bits(uint32_t val)
1972 {
1973     uint32_t ret;
1974     uint32_t mask;
1975     int i;
1976     ret = 0;
1977     mask = 3;
1978     for (i = 0; i < 16; i += 2) {
1979         ret |= (val >> i) & mask;
1980         mask <<= 2;
1981     }
1982     return ret;
1983 }
1984
1985 /* Pad basic MPU access permission bits to extended format.  */
1986 static uint32_t extended_mpu_ap_bits(uint32_t val)
1987 {
1988     uint32_t ret;
1989     uint32_t mask;
1990     int i;
1991     ret = 0;
1992     mask = 3;
1993     for (i = 0; i < 16; i += 2) {
1994         ret |= (val & mask) << i;
1995         mask <<= 2;
1996     }
1997     return ret;
1998 }
1999
2000 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2001                                  uint64_t value)
2002 {
2003     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
2004 }
2005
2006 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2007 {
2008     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
2009 }
2010
2011 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2012                                  uint64_t value)
2013 {
2014     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
2015 }
2016
2017 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2018 {
2019     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
2020 }
2021
2022 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
2023 {
2024     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2025
2026     if (!u32p) {
2027         return 0;
2028     }
2029
2030     u32p += env->cp15.c6_rgnr;
2031     return *u32p;
2032 }
2033
2034 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
2035                          uint64_t value)
2036 {
2037     ARMCPU *cpu = arm_env_get_cpu(env);
2038     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2039
2040     if (!u32p) {
2041         return;
2042     }
2043
2044     u32p += env->cp15.c6_rgnr;
2045     tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
2046     *u32p = value;
2047 }
2048
2049 static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2050 {
2051     ARMCPU *cpu = arm_env_get_cpu(env);
2052     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2053
2054     if (!u32p) {
2055         return;
2056     }
2057
2058     memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
2059 }
2060
2061 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2062                               uint64_t value)
2063 {
2064     ARMCPU *cpu = arm_env_get_cpu(env);
2065     uint32_t nrgs = cpu->pmsav7_dregion;
2066
2067     if (value >= nrgs) {
2068         qemu_log_mask(LOG_GUEST_ERROR,
2069                       "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2070                       " > %" PRIu32 "\n", (uint32_t)value, nrgs);
2071         return;
2072     }
2073
2074     raw_write(env, ri, value);
2075 }
2076
2077 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
2078     { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
2079       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2080       .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
2081       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2082     { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
2083       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2084       .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
2085       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2086     { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
2087       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2088       .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
2089       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2090     { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
2091       .access = PL1_RW,
2092       .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr),
2093       .writefn = pmsav7_rgnr_write },
2094     REGINFO_SENTINEL
2095 };
2096
2097 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
2098     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2099       .access = PL1_RW, .type = ARM_CP_ALIAS,
2100       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2101       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
2102     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2103       .access = PL1_RW, .type = ARM_CP_ALIAS,
2104       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2105       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
2106     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
2107       .access = PL1_RW,
2108       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2109       .resetvalue = 0, },
2110     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
2111       .access = PL1_RW,
2112       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2113       .resetvalue = 0, },
2114     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2115       .access = PL1_RW,
2116       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
2117     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
2118       .access = PL1_RW,
2119       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
2120     /* Protection region base and size registers */
2121     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
2122       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2123       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
2124     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
2125       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2126       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
2127     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
2128       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2129       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
2130     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
2131       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2132       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
2133     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
2134       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2135       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
2136     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
2137       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2138       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
2139     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
2140       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2141       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
2142     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
2143       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2144       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
2145     REGINFO_SENTINEL
2146 };
2147
2148 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
2149                                  uint64_t value)
2150 {
2151     TCR *tcr = raw_ptr(env, ri);
2152     int maskshift = extract32(value, 0, 3);
2153
2154     if (!arm_feature(env, ARM_FEATURE_V8)) {
2155         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
2156             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2157              * using Long-desciptor translation table format */
2158             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
2159         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
2160             /* In an implementation that includes the Security Extensions
2161              * TTBCR has additional fields PD0 [4] and PD1 [5] for
2162              * Short-descriptor translation table format.
2163              */
2164             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
2165         } else {
2166             value &= TTBCR_N;
2167         }
2168     }
2169
2170     /* Update the masks corresponding to the TCR bank being written
2171      * Note that we always calculate mask and base_mask, but
2172      * they are only used for short-descriptor tables (ie if EAE is 0);
2173      * for long-descriptor tables the TCR fields are used differently
2174      * and the mask and base_mask values are meaningless.
2175      */
2176     tcr->raw_tcr = value;
2177     tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
2178     tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
2179 }
2180
2181 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2182                              uint64_t value)
2183 {
2184     ARMCPU *cpu = arm_env_get_cpu(env);
2185
2186     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2187         /* With LPAE the TTBCR could result in a change of ASID
2188          * via the TTBCR.A1 bit, so do a TLB flush.
2189          */
2190         tlb_flush(CPU(cpu), 1);
2191     }
2192     vmsa_ttbcr_raw_write(env, ri, value);
2193 }
2194
2195 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2196 {
2197     TCR *tcr = raw_ptr(env, ri);
2198
2199     /* Reset both the TCR as well as the masks corresponding to the bank of
2200      * the TCR being reset.
2201      */
2202     tcr->raw_tcr = 0;
2203     tcr->mask = 0;
2204     tcr->base_mask = 0xffffc000u;
2205 }
2206
2207 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2208                                uint64_t value)
2209 {
2210     ARMCPU *cpu = arm_env_get_cpu(env);
2211     TCR *tcr = raw_ptr(env, ri);
2212
2213     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2214     tlb_flush(CPU(cpu), 1);
2215     tcr->raw_tcr = value;
2216 }
2217
2218 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2219                             uint64_t value)
2220 {
2221     /* 64 bit accesses to the TTBRs can change the ASID and so we
2222      * must flush the TLB.
2223      */
2224     if (cpreg_field_is_64bit(ri)) {
2225         ARMCPU *cpu = arm_env_get_cpu(env);
2226
2227         tlb_flush(CPU(cpu), 1);
2228     }
2229     raw_write(env, ri, value);
2230 }
2231
2232 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2233                         uint64_t value)
2234 {
2235     ARMCPU *cpu = arm_env_get_cpu(env);
2236     CPUState *cs = CPU(cpu);
2237
2238     /* Accesses to VTTBR may change the VMID so we must flush the TLB.  */
2239     if (raw_read(env, ri) != value) {
2240         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2241                             ARMMMUIdx_S2NS, -1);
2242         raw_write(env, ri, value);
2243     }
2244 }
2245
2246 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
2247     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2248       .access = PL1_RW, .type = ARM_CP_ALIAS,
2249       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
2250                              offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
2251     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2252       .access = PL1_RW, .resetvalue = 0,
2253       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
2254                              offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
2255     { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
2256       .access = PL1_RW, .resetvalue = 0,
2257       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
2258                              offsetof(CPUARMState, cp15.dfar_ns) } },
2259     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
2260       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
2261       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
2262       .resetvalue = 0, },
2263     REGINFO_SENTINEL
2264 };
2265
2266 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
2267     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
2268       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
2269       .access = PL1_RW,
2270       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
2271     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
2272       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
2273       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2274       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2275                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
2276     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
2277       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
2278       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2279       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2280                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
2281     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
2282       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2283       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
2284       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2285       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
2286     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2287       .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
2288       .raw_writefn = vmsa_ttbcr_raw_write,
2289       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
2290                              offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
2291     REGINFO_SENTINEL
2292 };
2293
2294 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
2295                                 uint64_t value)
2296 {
2297     env->cp15.c15_ticonfig = value & 0xe7;
2298     /* The OS_TYPE bit in this register changes the reported CPUID! */
2299     env->cp15.c0_cpuid = (value & (1 << 5)) ?
2300         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
2301 }
2302
2303 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2304                                 uint64_t value)
2305 {
2306     env->cp15.c15_threadid = value & 0xffff;
2307 }
2308
2309 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
2310                            uint64_t value)
2311 {
2312     /* Wait-for-interrupt (deprecated) */
2313     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
2314 }
2315
2316 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
2317                                   uint64_t value)
2318 {
2319     /* On OMAP there are registers indicating the max/min index of dcache lines
2320      * containing a dirty line; cache flush operations have to reset these.
2321      */
2322     env->cp15.c15_i_max = 0x000;
2323     env->cp15.c15_i_min = 0xff0;
2324 }
2325
2326 static const ARMCPRegInfo omap_cp_reginfo[] = {
2327     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
2328       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
2329       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
2330       .resetvalue = 0, },
2331     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2332       .access = PL1_RW, .type = ARM_CP_NOP },
2333     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2334       .access = PL1_RW,
2335       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
2336       .writefn = omap_ticonfig_write },
2337     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
2338       .access = PL1_RW,
2339       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
2340     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
2341       .access = PL1_RW, .resetvalue = 0xff0,
2342       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
2343     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
2344       .access = PL1_RW,
2345       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
2346       .writefn = omap_threadid_write },
2347     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
2348       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2349       .type = ARM_CP_NO_RAW,
2350       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
2351     /* TODO: Peripheral port remap register:
2352      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2353      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2354      * when MMU is off.
2355      */
2356     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
2357       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
2358       .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
2359       .writefn = omap_cachemaint_write },
2360     { .name = "C9", .cp = 15, .crn = 9,
2361       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
2362       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
2363     REGINFO_SENTINEL
2364 };
2365
2366 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2367                               uint64_t value)
2368 {
2369     env->cp15.c15_cpar = value & 0x3fff;
2370 }
2371
2372 static const ARMCPRegInfo xscale_cp_reginfo[] = {
2373     { .name = "XSCALE_CPAR",
2374       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2375       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
2376       .writefn = xscale_cpar_write, },
2377     { .name = "XSCALE_AUXCR",
2378       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
2379       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
2380       .resetvalue = 0, },
2381     /* XScale specific cache-lockdown: since we have no cache we NOP these
2382      * and hope the guest does not really rely on cache behaviour.
2383      */
2384     { .name = "XSCALE_LOCK_ICACHE_LINE",
2385       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2386       .access = PL1_W, .type = ARM_CP_NOP },
2387     { .name = "XSCALE_UNLOCK_ICACHE",
2388       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2389       .access = PL1_W, .type = ARM_CP_NOP },
2390     { .name = "XSCALE_DCACHE_LOCK",
2391       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
2392       .access = PL1_RW, .type = ARM_CP_NOP },
2393     { .name = "XSCALE_UNLOCK_DCACHE",
2394       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
2395       .access = PL1_W, .type = ARM_CP_NOP },
2396     REGINFO_SENTINEL
2397 };
2398
2399 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2400     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2401      * implementation of this implementation-defined space.
2402      * Ideally this should eventually disappear in favour of actually
2403      * implementing the correct behaviour for all cores.
2404      */
2405     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2406       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2407       .access = PL1_RW,
2408       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2409       .resetvalue = 0 },
2410     REGINFO_SENTINEL
2411 };
2412
2413 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2414     /* Cache status: RAZ because we have no cache so it's always clean */
2415     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2416       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2417       .resetvalue = 0 },
2418     REGINFO_SENTINEL
2419 };
2420
2421 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2422     /* We never have a a block transfer operation in progress */
2423     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2424       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2425       .resetvalue = 0 },
2426     /* The cache ops themselves: these all NOP for QEMU */
2427     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2428       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2429     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2430       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2431     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2432       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2433     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2434       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2435     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2436       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2437     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2438       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2439     REGINFO_SENTINEL
2440 };
2441
2442 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2443     /* The cache test-and-clean instructions always return (1 << 30)
2444      * to indicate that there are no dirty cache lines.
2445      */
2446     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2447       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2448       .resetvalue = (1 << 30) },
2449     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2450       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2451       .resetvalue = (1 << 30) },
2452     REGINFO_SENTINEL
2453 };
2454
2455 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2456     /* Ignore ReadBuffer accesses */
2457     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2458       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2459       .access = PL1_RW, .resetvalue = 0,
2460       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2461     REGINFO_SENTINEL
2462 };
2463
2464 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2465 {
2466     ARMCPU *cpu = arm_env_get_cpu(env);
2467     unsigned int cur_el = arm_current_el(env);
2468     bool secure = arm_is_secure(env);
2469
2470     if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2471         return env->cp15.vpidr_el2;
2472     }
2473     return raw_read(env, ri);
2474 }
2475
2476 static uint64_t mpidr_read_val(CPUARMState *env)
2477 {
2478     ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
2479     uint64_t mpidr = cpu->mp_affinity;
2480
2481     if (arm_feature(env, ARM_FEATURE_V7MP)) {
2482         mpidr |= (1U << 31);
2483         /* Cores which are uniprocessor (non-coherent)
2484          * but still implement the MP extensions set
2485          * bit 30. (For instance, Cortex-R5).
2486          */
2487         if (cpu->mp_is_up) {
2488             mpidr |= (1u << 30);
2489         }
2490     }
2491     return mpidr;
2492 }
2493
2494 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2495 {
2496     unsigned int cur_el = arm_current_el(env);
2497     bool secure = arm_is_secure(env);
2498
2499     if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2500         return env->cp15.vmpidr_el2;
2501     }
2502     return mpidr_read_val(env);
2503 }
2504
2505 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2506     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2507       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2508       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2509     REGINFO_SENTINEL
2510 };
2511
2512 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2513     /* NOP AMAIR0/1 */
2514     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2515       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2516       .access = PL1_RW, .type = ARM_CP_CONST,
2517       .resetvalue = 0 },
2518     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2519     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2520       .access = PL1_RW, .type = ARM_CP_CONST,
2521       .resetvalue = 0 },
2522     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2523       .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2524       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2525                              offsetof(CPUARMState, cp15.par_ns)} },
2526     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2527       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2528       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2529                              offsetof(CPUARMState, cp15.ttbr0_ns) },
2530       .writefn = vmsa_ttbr_write, },
2531     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2532       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2533       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2534                              offsetof(CPUARMState, cp15.ttbr1_ns) },
2535       .writefn = vmsa_ttbr_write, },
2536     REGINFO_SENTINEL
2537 };
2538
2539 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2540 {
2541     return vfp_get_fpcr(env);
2542 }
2543
2544 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2545                             uint64_t value)
2546 {
2547     vfp_set_fpcr(env, value);
2548 }
2549
2550 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2551 {
2552     return vfp_get_fpsr(env);
2553 }
2554
2555 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2556                             uint64_t value)
2557 {
2558     vfp_set_fpsr(env, value);
2559 }
2560
2561 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
2562 {
2563     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2564         return CP_ACCESS_TRAP;
2565     }
2566     return CP_ACCESS_OK;
2567 }
2568
2569 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2570                             uint64_t value)
2571 {
2572     env->daif = value & PSTATE_DAIF;
2573 }
2574
2575 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2576                                           const ARMCPRegInfo *ri)
2577 {
2578     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2579      * SCTLR_EL1.UCI is set.
2580      */
2581     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2582         return CP_ACCESS_TRAP;
2583     }
2584     return CP_ACCESS_OK;
2585 }
2586
2587 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2588  * Page D4-1736 (DDI0487A.b)
2589  */
2590
2591 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2592                                     uint64_t value)
2593 {
2594     ARMCPU *cpu = arm_env_get_cpu(env);
2595     CPUState *cs = CPU(cpu);
2596
2597     if (arm_is_secure_below_el3(env)) {
2598         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2599     } else {
2600         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2601     }
2602 }
2603
2604 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2605                                       uint64_t value)
2606 {
2607     bool sec = arm_is_secure_below_el3(env);
2608     CPUState *other_cs;
2609
2610     CPU_FOREACH(other_cs) {
2611         if (sec) {
2612             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2613         } else {
2614             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2615                                 ARMMMUIdx_S12NSE0, -1);
2616         }
2617     }
2618 }
2619
2620 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2621                                   uint64_t value)
2622 {
2623     /* Note that the 'ALL' scope must invalidate both stage 1 and
2624      * stage 2 translations, whereas most other scopes only invalidate
2625      * stage 1 translations.
2626      */
2627     ARMCPU *cpu = arm_env_get_cpu(env);
2628     CPUState *cs = CPU(cpu);
2629
2630     if (arm_is_secure_below_el3(env)) {
2631         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2632     } else {
2633         if (arm_feature(env, ARM_FEATURE_EL2)) {
2634             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2635                                 ARMMMUIdx_S2NS, -1);
2636         } else {
2637             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2638         }
2639     }
2640 }
2641
2642 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2643                                   uint64_t value)
2644 {
2645     ARMCPU *cpu = arm_env_get_cpu(env);
2646     CPUState *cs = CPU(cpu);
2647
2648     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1);
2649 }
2650
2651 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2652                                   uint64_t value)
2653 {
2654     ARMCPU *cpu = arm_env_get_cpu(env);
2655     CPUState *cs = CPU(cpu);
2656
2657     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1);
2658 }
2659
2660 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2661                                     uint64_t value)
2662 {
2663     /* Note that the 'ALL' scope must invalidate both stage 1 and
2664      * stage 2 translations, whereas most other scopes only invalidate
2665      * stage 1 translations.
2666      */
2667     bool sec = arm_is_secure_below_el3(env);
2668     bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
2669     CPUState *other_cs;
2670
2671     CPU_FOREACH(other_cs) {
2672         if (sec) {
2673             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2674         } else if (has_el2) {
2675             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2676                                 ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1);
2677         } else {
2678             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2679                                 ARMMMUIdx_S12NSE0, -1);
2680         }
2681     }
2682 }
2683
2684 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2685                                     uint64_t value)
2686 {
2687     CPUState *other_cs;
2688
2689     CPU_FOREACH(other_cs) {
2690         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1);
2691     }
2692 }
2693
2694 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2695                                     uint64_t value)
2696 {
2697     CPUState *other_cs;
2698
2699     CPU_FOREACH(other_cs) {
2700         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1);
2701     }
2702 }
2703
2704 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2705                                  uint64_t value)
2706 {
2707     /* Invalidate by VA, EL1&0 (AArch64 version).
2708      * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
2709      * since we don't support flush-for-specific-ASID-only or
2710      * flush-last-level-only.
2711      */
2712     ARMCPU *cpu = arm_env_get_cpu(env);
2713     CPUState *cs = CPU(cpu);
2714     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2715
2716     if (arm_is_secure_below_el3(env)) {
2717         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1,
2718                                  ARMMMUIdx_S1SE0, -1);
2719     } else {
2720         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1,
2721                                  ARMMMUIdx_S12NSE0, -1);
2722     }
2723 }
2724
2725 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2726                                  uint64_t value)
2727 {
2728     /* Invalidate by VA, EL2
2729      * Currently handles both VAE2 and VALE2, since we don't support
2730      * flush-last-level-only.
2731      */
2732     ARMCPU *cpu = arm_env_get_cpu(env);
2733     CPUState *cs = CPU(cpu);
2734     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2735
2736     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1);
2737 }
2738
2739 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2740                                  uint64_t value)
2741 {
2742     /* Invalidate by VA, EL3
2743      * Currently handles both VAE3 and VALE3, since we don't support
2744      * flush-last-level-only.
2745      */
2746     ARMCPU *cpu = arm_env_get_cpu(env);
2747     CPUState *cs = CPU(cpu);
2748     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2749
2750     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1);
2751 }
2752
2753 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2754                                    uint64_t value)
2755 {
2756     bool sec = arm_is_secure_below_el3(env);
2757     CPUState *other_cs;
2758     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2759
2760     CPU_FOREACH(other_cs) {
2761         if (sec) {
2762             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1,
2763                                      ARMMMUIdx_S1SE0, -1);
2764         } else {
2765             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1,
2766                                      ARMMMUIdx_S12NSE0, -1);
2767         }
2768     }
2769 }
2770
2771 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2772                                    uint64_t value)
2773 {
2774     CPUState *other_cs;
2775     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2776
2777     CPU_FOREACH(other_cs) {
2778         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
2779     }
2780 }
2781
2782 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2783                                    uint64_t value)
2784 {
2785     CPUState *other_cs;
2786     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2787
2788     CPU_FOREACH(other_cs) {
2789         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1);
2790     }
2791 }
2792
2793 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2794                                     uint64_t value)
2795 {
2796     /* Invalidate by IPA. This has to invalidate any structures that
2797      * contain only stage 2 translation information, but does not need
2798      * to apply to structures that contain combined stage 1 and stage 2
2799      * translation information.
2800      * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
2801      */
2802     ARMCPU *cpu = arm_env_get_cpu(env);
2803     CPUState *cs = CPU(cpu);
2804     uint64_t pageaddr;
2805
2806     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2807         return;
2808     }
2809
2810     pageaddr = sextract64(value << 12, 0, 48);
2811
2812     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);
2813 }
2814
2815 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2816                                       uint64_t value)
2817 {
2818     CPUState *other_cs;
2819     uint64_t pageaddr;
2820
2821     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2822         return;
2823     }
2824
2825     pageaddr = sextract64(value << 12, 0, 48);
2826
2827     CPU_FOREACH(other_cs) {
2828         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);
2829     }
2830 }
2831
2832 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
2833 {
2834     /* We don't implement EL2, so the only control on DC ZVA is the
2835      * bit in the SCTLR which can prohibit access for EL0.
2836      */
2837     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
2838         return CP_ACCESS_TRAP;
2839     }
2840     return CP_ACCESS_OK;
2841 }
2842
2843 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
2844 {
2845     ARMCPU *cpu = arm_env_get_cpu(env);
2846     int dzp_bit = 1 << 4;
2847
2848     /* DZP indicates whether DC ZVA access is allowed */
2849     if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) {
2850         dzp_bit = 0;
2851     }
2852     return cpu->dcz_blocksize | dzp_bit;
2853 }
2854
2855 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2856 {
2857     if (!(env->pstate & PSTATE_SP)) {
2858         /* Access to SP_EL0 is undefined if it's being used as
2859          * the stack pointer.
2860          */
2861         return CP_ACCESS_TRAP_UNCATEGORIZED;
2862     }
2863     return CP_ACCESS_OK;
2864 }
2865
2866 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
2867 {
2868     return env->pstate & PSTATE_SP;
2869 }
2870
2871 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
2872 {
2873     update_spsel(env, val);
2874 }
2875
2876 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2877                         uint64_t value)
2878 {
2879     ARMCPU *cpu = arm_env_get_cpu(env);
2880
2881     if (raw_read(env, ri) == value) {
2882         /* Skip the TLB flush if nothing actually changed; Linux likes
2883          * to do a lot of pointless SCTLR writes.
2884          */
2885         return;
2886     }
2887
2888     raw_write(env, ri, value);
2889     /* ??? Lots of these bits are not implemented.  */
2890     /* This may enable/disable the MMU, so do a TLB flush.  */
2891     tlb_flush(CPU(cpu), 1);
2892 }
2893
2894 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri)
2895 {
2896     if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
2897         return CP_ACCESS_TRAP_EL2;
2898     }
2899     if (env->cp15.cptr_el[3] & CPTR_TFP) {
2900         return CP_ACCESS_TRAP_EL3;
2901     }
2902     return CP_ACCESS_OK;
2903 }
2904
2905 static const ARMCPRegInfo v8_cp_reginfo[] = {
2906     /* Minimal set of EL0-visible registers. This will need to be expanded
2907      * significantly for system emulation of AArch64 CPUs.
2908      */
2909     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
2910       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
2911       .access = PL0_RW, .type = ARM_CP_NZCV },
2912     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
2913       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
2914       .type = ARM_CP_NO_RAW,
2915       .access = PL0_RW, .accessfn = aa64_daif_access,
2916       .fieldoffset = offsetof(CPUARMState, daif),
2917       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
2918     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
2919       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
2920       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
2921     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
2922       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
2923       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
2924     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
2925       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
2926       .access = PL0_R, .type = ARM_CP_NO_RAW,
2927       .readfn = aa64_dczid_read },
2928     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
2929       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
2930       .access = PL0_W, .type = ARM_CP_DC_ZVA,
2931 #ifndef CONFIG_USER_ONLY
2932       /* Avoid overhead of an access check that always passes in user-mode */
2933       .accessfn = aa64_zva_access,
2934 #endif
2935     },
2936     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
2937       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
2938       .access = PL1_R, .type = ARM_CP_CURRENTEL },
2939     /* Cache ops: all NOPs since we don't emulate caches */
2940     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
2941       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2942       .access = PL1_W, .type = ARM_CP_NOP },
2943     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
2944       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2945       .access = PL1_W, .type = ARM_CP_NOP },
2946     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
2947       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
2948       .access = PL0_W, .type = ARM_CP_NOP,
2949       .accessfn = aa64_cacheop_access },
2950     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
2951       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2952       .access = PL1_W, .type = ARM_CP_NOP },
2953     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
2954       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2955       .access = PL1_W, .type = ARM_CP_NOP },
2956     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
2957       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
2958       .access = PL0_W, .type = ARM_CP_NOP,
2959       .accessfn = aa64_cacheop_access },
2960     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
2961       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2962       .access = PL1_W, .type = ARM_CP_NOP },
2963     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
2964       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
2965       .access = PL0_W, .type = ARM_CP_NOP,
2966       .accessfn = aa64_cacheop_access },
2967     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
2968       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
2969       .access = PL0_W, .type = ARM_CP_NOP,
2970       .accessfn = aa64_cacheop_access },
2971     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
2972       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2973       .access = PL1_W, .type = ARM_CP_NOP },
2974     /* TLBI operations */
2975     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
2976       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2977       .access = PL1_W, .type = ARM_CP_NO_RAW,
2978       .writefn = tlbi_aa64_vmalle1is_write },
2979     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
2980       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2981       .access = PL1_W, .type = ARM_CP_NO_RAW,
2982       .writefn = tlbi_aa64_vae1is_write },
2983     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
2984       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2985       .access = PL1_W, .type = ARM_CP_NO_RAW,
2986       .writefn = tlbi_aa64_vmalle1is_write },
2987     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
2988       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2989       .access = PL1_W, .type = ARM_CP_NO_RAW,
2990       .writefn = tlbi_aa64_vae1is_write },
2991     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
2992       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2993       .access = PL1_W, .type = ARM_CP_NO_RAW,
2994       .writefn = tlbi_aa64_vae1is_write },
2995     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
2996       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2997       .access = PL1_W, .type = ARM_CP_NO_RAW,
2998       .writefn = tlbi_aa64_vae1is_write },
2999     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
3000       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
3001       .access = PL1_W, .type = ARM_CP_NO_RAW,
3002       .writefn = tlbi_aa64_vmalle1_write },
3003     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
3004       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
3005       .access = PL1_W, .type = ARM_CP_NO_RAW,
3006       .writefn = tlbi_aa64_vae1_write },
3007     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
3008       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
3009       .access = PL1_W, .type = ARM_CP_NO_RAW,
3010       .writefn = tlbi_aa64_vmalle1_write },
3011     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
3012       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
3013       .access = PL1_W, .type = ARM_CP_NO_RAW,
3014       .writefn = tlbi_aa64_vae1_write },
3015     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
3016       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3017       .access = PL1_W, .type = ARM_CP_NO_RAW,
3018       .writefn = tlbi_aa64_vae1_write },
3019     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
3020       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3021       .access = PL1_W, .type = ARM_CP_NO_RAW,
3022       .writefn = tlbi_aa64_vae1_write },
3023     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
3024       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
3025       .access = PL2_W, .type = ARM_CP_NO_RAW,
3026       .writefn = tlbi_aa64_ipas2e1is_write },
3027     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
3028       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
3029       .access = PL2_W, .type = ARM_CP_NO_RAW,
3030       .writefn = tlbi_aa64_ipas2e1is_write },
3031     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
3032       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
3033       .access = PL2_W, .type = ARM_CP_NO_RAW,
3034       .writefn = tlbi_aa64_alle1is_write },
3035     { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
3036       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
3037       .access = PL2_W, .type = ARM_CP_NO_RAW,
3038       .writefn = tlbi_aa64_alle1is_write },
3039     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
3040       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
3041       .access = PL2_W, .type = ARM_CP_NO_RAW,
3042       .writefn = tlbi_aa64_ipas2e1_write },
3043     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
3044       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
3045       .access = PL2_W, .type = ARM_CP_NO_RAW,
3046       .writefn = tlbi_aa64_ipas2e1_write },
3047     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
3048       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
3049       .access = PL2_W, .type = ARM_CP_NO_RAW,
3050       .writefn = tlbi_aa64_alle1_write },
3051     { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
3052       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
3053       .access = PL2_W, .type = ARM_CP_NO_RAW,
3054       .writefn = tlbi_aa64_alle1is_write },
3055 #ifndef CONFIG_USER_ONLY
3056     /* 64 bit address translation operations */
3057     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
3058       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
3059       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3060     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
3061       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
3062       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3063     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
3064       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
3065       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3066     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
3067       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
3068       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3069     { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
3070       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
3071       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3072     { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
3073       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
3074       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3075     { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
3076       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
3077       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3078     { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
3079       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
3080       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3081     /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3082     { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
3083       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
3084       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3085     { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
3086       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
3087       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3088     { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
3089       .type = ARM_CP_ALIAS,
3090       .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
3091       .access = PL1_RW, .resetvalue = 0,
3092       .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
3093       .writefn = par_write },
3094 #endif
3095     /* TLB invalidate last level of translation table walk */
3096     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3097       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
3098     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3099       .type = ARM_CP_NO_RAW, .access = PL1_W,
3100       .writefn = tlbimvaa_is_write },
3101     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3102       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
3103     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3104       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
3105     /* 32 bit cache operations */
3106     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3107       .type = ARM_CP_NOP, .access = PL1_W },
3108     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
3109       .type = ARM_CP_NOP, .access = PL1_W },
3110     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3111       .type = ARM_CP_NOP, .access = PL1_W },
3112     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
3113       .type = ARM_CP_NOP, .access = PL1_W },
3114     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
3115       .type = ARM_CP_NOP, .access = PL1_W },
3116     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
3117       .type = ARM_CP_NOP, .access = PL1_W },
3118     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3119       .type = ARM_CP_NOP, .access = PL1_W },
3120     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3121       .type = ARM_CP_NOP, .access = PL1_W },
3122     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
3123       .type = ARM_CP_NOP, .access = PL1_W },
3124     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3125       .type = ARM_CP_NOP, .access = PL1_W },
3126     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
3127       .type = ARM_CP_NOP, .access = PL1_W },
3128     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
3129       .type = ARM_CP_NOP, .access = PL1_W },
3130     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3131       .type = ARM_CP_NOP, .access = PL1_W },
3132     /* MMU Domain access control / MPU write buffer control */
3133     { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
3134       .access = PL1_RW, .resetvalue = 0,
3135       .writefn = dacr_write, .raw_writefn = raw_write,
3136       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
3137                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
3138     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
3139       .type = ARM_CP_ALIAS,
3140       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
3141       .access = PL1_RW,
3142       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
3143     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
3144       .type = ARM_CP_ALIAS,
3145       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
3146       .access = PL1_RW,
3147       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
3148     /* We rely on the access checks not allowing the guest to write to the
3149      * state field when SPSel indicates that it's being used as the stack
3150      * pointer.
3151      */
3152     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
3153       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
3154       .access = PL1_RW, .accessfn = sp_el0_access,
3155       .type = ARM_CP_ALIAS,
3156       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
3157     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
3158       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
3159       .access = PL2_RW, .type = ARM_CP_ALIAS,
3160       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
3161     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
3162       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
3163       .type = ARM_CP_NO_RAW,
3164       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
3165     { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
3166       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
3167       .type = ARM_CP_ALIAS,
3168       .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
3169       .access = PL2_RW, .accessfn = fpexc32_access },
3170     REGINFO_SENTINEL
3171 };
3172
3173 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
3174 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
3175     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3176       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3177       .access = PL2_RW,
3178       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3179     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3180       .type = ARM_CP_NO_RAW,
3181       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3182       .access = PL2_RW,
3183       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3184     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3185       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3186       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3187     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3188       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3189       .access = PL2_RW, .type = ARM_CP_CONST,
3190       .resetvalue = 0 },
3191     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3192       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3193       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3194     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3195       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3196       .access = PL2_RW, .type = ARM_CP_CONST,
3197       .resetvalue = 0 },
3198     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3199       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3200       .access = PL2_RW, .type = ARM_CP_CONST,
3201       .resetvalue = 0 },
3202     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3203       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3204       .access = PL2_RW, .type = ARM_CP_CONST,
3205       .resetvalue = 0 },
3206     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3207       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3208       .access = PL2_RW, .type = ARM_CP_CONST,
3209       .resetvalue = 0 },
3210     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3211       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3212       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3213     { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
3214       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3215       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3216       .type = ARM_CP_CONST, .resetvalue = 0 },
3217     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3218       .cp = 15, .opc1 = 6, .crm = 2,
3219       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3220       .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
3221     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3222       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3223       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3224     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3225       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3226       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3227     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3228       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3229       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3230     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3231       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3232       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3233     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3234       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3235       .resetvalue = 0 },
3236     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3237       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3238       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3239     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3240       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3241       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3242     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3243       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3244       .resetvalue = 0 },
3245     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3246       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3247       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3248     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3249       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3250       .resetvalue = 0 },
3251     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3252       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3253       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3254     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3255       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3256       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3257     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3258       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3259       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3260     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
3261       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3262       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3263       .type = ARM_CP_CONST, .resetvalue = 0 },
3264     REGINFO_SENTINEL
3265 };
3266
3267 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3268 {
3269     ARMCPU *cpu = arm_env_get_cpu(env);
3270     uint64_t valid_mask = HCR_MASK;
3271
3272     if (arm_feature(env, ARM_FEATURE_EL3)) {
3273         valid_mask &= ~HCR_HCD;
3274     } else {
3275         valid_mask &= ~HCR_TSC;
3276     }
3277
3278     /* Clear RES0 bits.  */
3279     value &= valid_mask;
3280
3281     /* These bits change the MMU setup:
3282      * HCR_VM enables stage 2 translation
3283      * HCR_PTW forbids certain page-table setups
3284      * HCR_DC Disables stage1 and enables stage2 translation
3285      */
3286     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
3287         tlb_flush(CPU(cpu), 1);
3288     }
3289     raw_write(env, ri, value);
3290 }
3291
3292 static const ARMCPRegInfo el2_cp_reginfo[] = {
3293     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3294       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3295       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
3296       .writefn = hcr_write },
3297     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
3298       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
3299       .access = PL2_RW, .resetvalue = 0,
3300       .writefn = dacr_write, .raw_writefn = raw_write,
3301       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
3302     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
3303       .type = ARM_CP_ALIAS,
3304       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
3305       .access = PL2_RW,
3306       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
3307     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
3308       .type = ARM_CP_ALIAS,
3309       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
3310       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
3311     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
3312       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
3313       .access = PL2_RW, .resetvalue = 0,
3314       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
3315     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
3316       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
3317       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
3318     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
3319       .type = ARM_CP_ALIAS,
3320       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
3321       .access = PL2_RW,
3322       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
3323     { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
3324       .type = ARM_CP_ALIAS,
3325       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
3326       .access = PL2_RW,
3327       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
3328     { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
3329       .type = ARM_CP_ALIAS,
3330       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
3331       .access = PL2_RW,
3332       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
3333     { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
3334       .type = ARM_CP_ALIAS,
3335       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
3336       .access = PL2_RW,
3337       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
3338     { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
3339       .type = ARM_CP_ALIAS,
3340       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
3341       .access = PL2_RW,
3342       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
3343     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3344       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3345       .access = PL2_RW, .writefn = vbar_write,
3346       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
3347       .resetvalue = 0 },
3348     { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
3349       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
3350       .access = PL3_RW, .type = ARM_CP_ALIAS,
3351       .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
3352     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3353       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3354       .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
3355       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
3356     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3357       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3358       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
3359       .resetvalue = 0 },
3360     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3361       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3362       .access = PL2_RW, .type = ARM_CP_ALIAS,
3363       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
3364     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3365       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3366       .access = PL2_RW, .type = ARM_CP_CONST,
3367       .resetvalue = 0 },
3368     /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3369     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3370       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3371       .access = PL2_RW, .type = ARM_CP_CONST,
3372       .resetvalue = 0 },
3373     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3374       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3375       .access = PL2_RW, .type = ARM_CP_CONST,
3376       .resetvalue = 0 },
3377     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3378       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3379       .access = PL2_RW, .type = ARM_CP_CONST,
3380       .resetvalue = 0 },
3381     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3382       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3383       .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
3384       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3385       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
3386     { .name = "VTCR", .state = ARM_CP_STATE_AA32,
3387       .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3388       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3389       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3390     { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
3391       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3392       .access = PL2_RW, .type = ARM_CP_ALIAS,
3393       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3394     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3395       .cp = 15, .opc1 = 6, .crm = 2,
3396       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3397       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3398       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
3399       .writefn = vttbr_write },
3400     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3401       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3402       .access = PL2_RW, .writefn = vttbr_write,
3403       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
3404     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3405       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3406       .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3407       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
3408     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3409       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3410       .access = PL2_RW, .resetvalue = 0,
3411       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
3412     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3413       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3414       .access = PL2_RW, .resetvalue = 0,
3415       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3416     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3417       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3418       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3419     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
3420       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
3421       .type = ARM_CP_NO_RAW, .access = PL2_W,
3422       .writefn = tlbi_aa64_alle2_write },
3423     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
3424       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
3425       .type = ARM_CP_NO_RAW, .access = PL2_W,
3426       .writefn = tlbi_aa64_vae2_write },
3427     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
3428       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
3429       .access = PL2_W, .type = ARM_CP_NO_RAW,
3430       .writefn = tlbi_aa64_vae2_write },
3431     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
3432       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
3433       .access = PL2_W, .type = ARM_CP_NO_RAW,
3434       .writefn = tlbi_aa64_alle2is_write },
3435     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
3436       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
3437       .type = ARM_CP_NO_RAW, .access = PL2_W,
3438       .writefn = tlbi_aa64_vae2is_write },
3439     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
3440       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
3441       .access = PL2_W, .type = ARM_CP_NO_RAW,
3442       .writefn = tlbi_aa64_vae2is_write },
3443 #ifndef CONFIG_USER_ONLY
3444     /* Unlike the other EL2-related AT operations, these must
3445      * UNDEF from EL3 if EL2 is not implemented, which is why we
3446      * define them here rather than with the rest of the AT ops.
3447      */
3448     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
3449       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3450       .access = PL2_W, .accessfn = at_s1e2_access,
3451       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3452     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
3453       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3454       .access = PL2_W, .accessfn = at_s1e2_access,
3455       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3456     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3457      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3458      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3459      * to behave as if SCR.NS was 1.
3460      */
3461     { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3462       .access = PL2_W,
3463       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3464     { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3465       .access = PL2_W,
3466       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3467     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3468       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3469       /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3470        * reset values as IMPDEF. We choose to reset to 3 to comply with
3471        * both ARMv7 and ARMv8.
3472        */
3473       .access = PL2_RW, .resetvalue = 3,
3474       .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
3475     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3476       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3477       .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
3478       .writefn = gt_cntvoff_write,
3479       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3480     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3481       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
3482       .writefn = gt_cntvoff_write,
3483       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3484     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3485       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3486       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3487       .type = ARM_CP_IO, .access = PL2_RW,
3488       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3489     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3490       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3491       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
3492       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3493     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3494       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3495       .type = ARM_CP_IO, .access = PL2_RW,
3496       .resetfn = gt_hyp_timer_reset,
3497       .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
3498     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3499       .type = ARM_CP_IO,
3500       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3501       .access = PL2_RW,
3502       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
3503       .resetvalue = 0,
3504       .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
3505 #endif
3506     /* The only field of MDCR_EL2 that has a defined architectural reset value
3507      * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
3508      * don't impelment any PMU event counters, so using zero as a reset
3509      * value for MDCR_EL2 is okay
3510      */
3511     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3512       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3513       .access = PL2_RW, .resetvalue = 0,
3514       .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
3515     { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
3516       .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3517       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3518       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3519     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
3520       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3521       .access = PL2_RW,
3522       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3523     REGINFO_SENTINEL
3524 };
3525
3526 static const ARMCPRegInfo el3_cp_reginfo[] = {
3527     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
3528       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
3529       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
3530       .resetvalue = 0, .writefn = scr_write },
3531     { .name = "SCR",  .type = ARM_CP_ALIAS,
3532       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
3533       .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
3534       .writefn = scr_write },
3535     { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
3536       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
3537       .access = PL3_RW, .resetvalue = 0,
3538       .fieldoffset = offsetof(CPUARMState, cp15.sder) },
3539     { .name = "SDER",
3540       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
3541       .access = PL3_RW, .resetvalue = 0,
3542       .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
3543       /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
3544     { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
3545       .access = PL3_W | PL1_R, .resetvalue = 0,
3546       .fieldoffset = offsetof(CPUARMState, cp15.nsacr) },
3547     { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
3548       .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
3549       .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
3550     { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
3551       .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */
3552       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
3553       .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3554       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },
3555     { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
3556       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
3557       .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
3558       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
3559     { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
3560       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
3561       .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
3562       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3563       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
3564     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
3565       .type = ARM_CP_ALIAS,
3566       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
3567       .access = PL3_RW,
3568       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
3569     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
3570       .type = ARM_CP_ALIAS,
3571       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
3572       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
3573     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
3574       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
3575       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
3576     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
3577       .type = ARM_CP_ALIAS,
3578       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
3579       .access = PL3_RW,
3580       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
3581     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
3582       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
3583       .access = PL3_RW, .writefn = vbar_write,
3584       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
3585       .resetvalue = 0 },
3586     { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
3587       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
3588       .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
3589       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
3590     { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
3591       .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
3592       .access = PL3_RW, .resetvalue = 0,
3593       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
3594     { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
3595       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
3596       .access = PL3_RW, .type = ARM_CP_CONST,
3597       .resetvalue = 0 },
3598     { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
3599       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
3600       .access = PL3_RW, .type = ARM_CP_CONST,
3601       .resetvalue = 0 },
3602     { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
3603       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
3604       .access = PL3_RW, .type = ARM_CP_CONST,
3605       .resetvalue = 0 },
3606     { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
3607       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
3608       .access = PL3_W, .type = ARM_CP_NO_RAW,
3609       .writefn = tlbi_aa64_alle3is_write },
3610     { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
3611       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
3612       .access = PL3_W, .type = ARM_CP_NO_RAW,
3613       .writefn = tlbi_aa64_vae3is_write },
3614     { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
3615       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
3616       .access = PL3_W, .type = ARM_CP_NO_RAW,
3617       .writefn = tlbi_aa64_vae3is_write },
3618     { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
3619       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
3620       .access = PL3_W, .type = ARM_CP_NO_RAW,
3621       .writefn = tlbi_aa64_alle3_write },
3622     { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
3623       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
3624       .access = PL3_W, .type = ARM_CP_NO_RAW,
3625       .writefn = tlbi_aa64_vae3_write },
3626     { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
3627       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
3628       .access = PL3_W, .type = ARM_CP_NO_RAW,
3629       .writefn = tlbi_aa64_vae3_write },
3630     REGINFO_SENTINEL
3631 };
3632
3633 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
3634 {
3635     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
3636      * but the AArch32 CTR has its own reginfo struct)
3637      */
3638     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
3639         return CP_ACCESS_TRAP;
3640     }
3641     return CP_ACCESS_OK;
3642 }
3643
3644 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
3645                         uint64_t value)
3646 {
3647     /* Writes to OSLAR_EL1 may update the OS lock status, which can be
3648      * read via a bit in OSLSR_EL1.
3649      */
3650     int oslock;
3651
3652     if (ri->state == ARM_CP_STATE_AA32) {
3653         oslock = (value == 0xC5ACCE55);
3654     } else {
3655         oslock = value & 1;
3656     }
3657
3658     env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
3659 }
3660
3661 static const ARMCPRegInfo debug_cp_reginfo[] = {
3662     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
3663      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
3664      * unlike DBGDRAR it is never accessible from EL0.
3665      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
3666      * accessor.
3667      */
3668     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
3669       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3670     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
3671       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3672       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3673     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3674       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3675     /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
3676     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
3677       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3678       .access = PL1_RW,
3679       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
3680       .resetvalue = 0 },
3681     /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
3682      * We don't implement the configurable EL0 access.
3683      */
3684     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
3685       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3686       .type = ARM_CP_ALIAS,
3687       .access = PL1_R,
3688       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
3689     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
3690       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
3691       .access = PL1_W, .type = ARM_CP_NO_RAW,
3692       .writefn = oslar_write },
3693     { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
3694       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
3695       .access = PL1_R, .resetvalue = 10,
3696       .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
3697     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
3698     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
3699       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
3700       .access = PL1_RW, .type = ARM_CP_NOP },
3701     /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
3702      * implement vector catch debug events yet.
3703      */
3704     { .name = "DBGVCR",
3705       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3706       .access = PL1_RW, .type = ARM_CP_NOP },
3707     REGINFO_SENTINEL
3708 };
3709
3710 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
3711     /* 64 bit access versions of the (dummy) debug registers */
3712     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
3713       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3714     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
3715       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3716     REGINFO_SENTINEL
3717 };
3718
3719 void hw_watchpoint_update(ARMCPU *cpu, int n)
3720 {
3721     CPUARMState *env = &cpu->env;
3722     vaddr len = 0;
3723     vaddr wvr = env->cp15.dbgwvr[n];
3724     uint64_t wcr = env->cp15.dbgwcr[n];
3725     int mask;
3726     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
3727
3728     if (env->cpu_watchpoint[n]) {
3729         cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
3730         env->cpu_watchpoint[n] = NULL;
3731     }
3732
3733     if (!extract64(wcr, 0, 1)) {
3734         /* E bit clear : watchpoint disabled */
3735         return;
3736     }
3737
3738     switch (extract64(wcr, 3, 2)) {
3739     case 0:
3740         /* LSC 00 is reserved and must behave as if the wp is disabled */
3741         return;
3742     case 1:
3743         flags |= BP_MEM_READ;
3744         break;
3745     case 2:
3746         flags |= BP_MEM_WRITE;
3747         break;
3748     case 3:
3749         flags |= BP_MEM_ACCESS;
3750         break;
3751     }
3752
3753     /* Attempts to use both MASK and BAS fields simultaneously are
3754      * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
3755      * thus generating a watchpoint for every byte in the masked region.
3756      */
3757     mask = extract64(wcr, 24, 4);
3758     if (mask == 1 || mask == 2) {
3759         /* Reserved values of MASK; we must act as if the mask value was
3760          * some non-reserved value, or as if the watchpoint were disabled.
3761          * We choose the latter.
3762          */
3763         return;
3764     } else if (mask) {
3765         /* Watchpoint covers an aligned area up to 2GB in size */
3766         len = 1ULL << mask;
3767         /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
3768          * whether the watchpoint fires when the unmasked bits match; we opt
3769          * to generate the exceptions.
3770          */
3771         wvr &= ~(len - 1);
3772     } else {
3773         /* Watchpoint covers bytes defined by the byte address select bits */
3774         int bas = extract64(wcr, 5, 8);
3775         int basstart;
3776
3777         if (bas == 0) {
3778             /* This must act as if the watchpoint is disabled */
3779             return;
3780         }
3781
3782         if (extract64(wvr, 2, 1)) {
3783             /* Deprecated case of an only 4-aligned address. BAS[7:4] are
3784              * ignored, and BAS[3:0] define which bytes to watch.
3785              */
3786             bas &= 0xf;
3787         }
3788         /* The BAS bits are supposed to be programmed to indicate a contiguous
3789          * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
3790          * we fire for each byte in the word/doubleword addressed by the WVR.
3791          * We choose to ignore any non-zero bits after the first range of 1s.
3792          */
3793         basstart = ctz32(bas);
3794         len = cto32(bas >> basstart);
3795         wvr += basstart;
3796     }
3797
3798     cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
3799                           &env->cpu_watchpoint[n]);
3800 }
3801
3802 void hw_watchpoint_update_all(ARMCPU *cpu)
3803 {
3804     int i;
3805     CPUARMState *env = &cpu->env;
3806
3807     /* Completely clear out existing QEMU watchpoints and our array, to
3808      * avoid possible stale entries following migration load.
3809      */
3810     cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
3811     memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
3812
3813     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
3814         hw_watchpoint_update(cpu, i);
3815     }
3816 }
3817
3818 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3819                          uint64_t value)
3820 {
3821     ARMCPU *cpu = arm_env_get_cpu(env);
3822     int i = ri->crm;
3823
3824     /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
3825      * register reads and behaves as if values written are sign extended.
3826      * Bits [1:0] are RES0.
3827      */
3828     value = sextract64(value, 0, 49) & ~3ULL;
3829
3830     raw_write(env, ri, value);
3831     hw_watchpoint_update(cpu, i);
3832 }
3833
3834 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3835                          uint64_t value)
3836 {
3837     ARMCPU *cpu = arm_env_get_cpu(env);
3838     int i = ri->crm;
3839
3840     raw_write(env, ri, value);
3841     hw_watchpoint_update(cpu, i);
3842 }
3843
3844 void hw_breakpoint_update(ARMCPU *cpu, int n)
3845 {
3846     CPUARMState *env = &cpu->env;
3847     uint64_t bvr = env->cp15.dbgbvr[n];
3848     uint64_t bcr = env->cp15.dbgbcr[n];
3849     vaddr addr;
3850     int bt;
3851     int flags = BP_CPU;
3852
3853     if (env->cpu_breakpoint[n]) {
3854         cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
3855         env->cpu_breakpoint[n] = NULL;
3856     }
3857
3858     if (!extract64(bcr, 0, 1)) {
3859         /* E bit clear : watchpoint disabled */
3860         return;
3861     }
3862
3863     bt = extract64(bcr, 20, 4);
3864
3865     switch (bt) {
3866     case 4: /* unlinked address mismatch (reserved if AArch64) */
3867     case 5: /* linked address mismatch (reserved if AArch64) */
3868         qemu_log_mask(LOG_UNIMP,
3869                       "arm: address mismatch breakpoint types not implemented");
3870         return;
3871     case 0: /* unlinked address match */
3872     case 1: /* linked address match */
3873     {
3874         /* Bits [63:49] are hardwired to the value of bit [48]; that is,
3875          * we behave as if the register was sign extended. Bits [1:0] are
3876          * RES0. The BAS field is used to allow setting breakpoints on 16
3877          * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
3878          * a bp will fire if the addresses covered by the bp and the addresses
3879          * covered by the insn overlap but the insn doesn't start at the
3880          * start of the bp address range. We choose to require the insn and
3881          * the bp to have the same address. The constraints on writing to
3882          * BAS enforced in dbgbcr_write mean we have only four cases:
3883          *  0b0000  => no breakpoint
3884          *  0b0011  => breakpoint on addr
3885          *  0b1100  => breakpoint on addr + 2
3886          *  0b1111  => breakpoint on addr
3887          * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
3888          */
3889         int bas = extract64(bcr, 5, 4);
3890         addr = sextract64(bvr, 0, 49) & ~3ULL;
3891         if (bas == 0) {
3892             return;
3893         }
3894         if (bas == 0xc) {
3895             addr += 2;
3896         }
3897         break;
3898     }
3899     case 2: /* unlinked context ID match */
3900     case 8: /* unlinked VMID match (reserved if no EL2) */
3901     case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
3902         qemu_log_mask(LOG_UNIMP,
3903                       "arm: unlinked context breakpoint types not implemented");
3904         return;
3905     case 9: /* linked VMID match (reserved if no EL2) */
3906     case 11: /* linked context ID and VMID match (reserved if no EL2) */
3907     case 3: /* linked context ID match */
3908     default:
3909         /* We must generate no events for Linked context matches (unless
3910          * they are linked to by some other bp/wp, which is handled in
3911          * updates for the linking bp/wp). We choose to also generate no events
3912          * for reserved values.
3913          */
3914         return;
3915     }
3916
3917     cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
3918 }
3919
3920 void hw_breakpoint_update_all(ARMCPU *cpu)
3921 {
3922     int i;
3923     CPUARMState *env = &cpu->env;
3924
3925     /* Completely clear out existing QEMU breakpoints and our array, to
3926      * avoid possible stale entries following migration load.
3927      */
3928     cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
3929     memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
3930
3931     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
3932         hw_breakpoint_update(cpu, i);
3933     }
3934 }
3935
3936 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3937                          uint64_t value)
3938 {
3939     ARMCPU *cpu = arm_env_get_cpu(env);
3940     int i = ri->crm;
3941
3942     raw_write(env, ri, value);
3943     hw_breakpoint_update(cpu, i);
3944 }
3945
3946 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3947                          uint64_t value)
3948 {
3949     ARMCPU *cpu = arm_env_get_cpu(env);
3950     int i = ri->crm;
3951
3952     /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
3953      * copy of BAS[0].
3954      */
3955     value = deposit64(value, 6, 1, extract64(value, 5, 1));
3956     value = deposit64(value, 8, 1, extract64(value, 7, 1));
3957
3958     raw_write(env, ri, value);
3959     hw_breakpoint_update(cpu, i);
3960 }
3961
3962 static void define_debug_regs(ARMCPU *cpu)
3963 {
3964     /* Define v7 and v8 architectural debug registers.
3965      * These are just dummy implementations for now.
3966      */
3967     int i;
3968     int wrps, brps, ctx_cmps;
3969     ARMCPRegInfo dbgdidr = {
3970         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
3971         .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
3972     };
3973
3974     /* Note that all these register fields hold "number of Xs minus 1". */
3975     brps = extract32(cpu->dbgdidr, 24, 4);
3976     wrps = extract32(cpu->dbgdidr, 28, 4);
3977     ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
3978
3979     assert(ctx_cmps <= brps);
3980
3981     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
3982      * of the debug registers such as number of breakpoints;
3983      * check that if they both exist then they agree.
3984      */
3985     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
3986         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
3987         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
3988         assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
3989     }
3990
3991     define_one_arm_cp_reg(cpu, &dbgdidr);
3992     define_arm_cp_regs(cpu, debug_cp_reginfo);
3993
3994     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
3995         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
3996     }
3997
3998     for (i = 0; i < brps + 1; i++) {
3999         ARMCPRegInfo dbgregs[] = {
4000             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
4001               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
4002               .access = PL1_RW,
4003               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
4004               .writefn = dbgbvr_write, .raw_writefn = raw_write
4005             },
4006             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
4007               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
4008               .access = PL1_RW,
4009               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
4010               .writefn = dbgbcr_write, .raw_writefn = raw_write
4011             },
4012             REGINFO_SENTINEL
4013         };
4014         define_arm_cp_regs(cpu, dbgregs);
4015     }
4016
4017     for (i = 0; i < wrps + 1; i++) {
4018         ARMCPRegInfo dbgregs[] = {
4019             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
4020               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
4021               .access = PL1_RW,
4022               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
4023               .writefn = dbgwvr_write, .raw_writefn = raw_write
4024             },
4025             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
4026               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
4027               .access = PL1_RW,
4028               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
4029               .writefn = dbgwcr_write, .raw_writefn = raw_write
4030             },
4031             REGINFO_SENTINEL
4032         };
4033         define_arm_cp_regs(cpu, dbgregs);
4034     }
4035 }
4036
4037 void register_cp_regs_for_features(ARMCPU *cpu)
4038 {
4039     /* Register all the coprocessor registers based on feature bits */
4040     CPUARMState *env = &cpu->env;
4041     if (arm_feature(env, ARM_FEATURE_M)) {
4042         /* M profile has no coprocessor registers */
4043         return;
4044     }
4045
4046     define_arm_cp_regs(cpu, cp_reginfo);
4047     if (!arm_feature(env, ARM_FEATURE_V8)) {
4048         /* Must go early as it is full of wildcards that may be
4049          * overridden by later definitions.
4050          */
4051         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
4052     }
4053
4054     if (arm_feature(env, ARM_FEATURE_V6)) {
4055         /* The ID registers all have impdef reset values */
4056         ARMCPRegInfo v6_idregs[] = {
4057             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
4058               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
4059               .access = PL1_R, .type = ARM_CP_CONST,
4060               .resetvalue = cpu->id_pfr0 },
4061             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
4062               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
4063               .access = PL1_R, .type = ARM_CP_CONST,
4064               .resetvalue = cpu->id_pfr1 },
4065             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
4066               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
4067               .access = PL1_R, .type = ARM_CP_CONST,
4068               .resetvalue = cpu->id_dfr0 },
4069             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
4070               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
4071               .access = PL1_R, .type = ARM_CP_CONST,
4072               .resetvalue = cpu->id_afr0 },
4073             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
4074               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
4075               .access = PL1_R, .type = ARM_CP_CONST,
4076               .resetvalue = cpu->id_mmfr0 },
4077             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
4078               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
4079               .access = PL1_R, .type = ARM_CP_CONST,
4080               .resetvalue = cpu->id_mmfr1 },
4081             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
4082               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
4083               .access = PL1_R, .type = ARM_CP_CONST,
4084               .resetvalue = cpu->id_mmfr2 },
4085             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
4086               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
4087               .access = PL1_R, .type = ARM_CP_CONST,
4088               .resetvalue = cpu->id_mmfr3 },
4089             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
4090               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
4091               .access = PL1_R, .type = ARM_CP_CONST,
4092               .resetvalue = cpu->id_isar0 },
4093             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
4094               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
4095               .access = PL1_R, .type = ARM_CP_CONST,
4096               .resetvalue = cpu->id_isar1 },
4097             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
4098               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
4099               .access = PL1_R, .type = ARM_CP_CONST,
4100               .resetvalue = cpu->id_isar2 },
4101             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
4102               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
4103               .access = PL1_R, .type = ARM_CP_CONST,
4104               .resetvalue = cpu->id_isar3 },
4105             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
4106               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
4107               .access = PL1_R, .type = ARM_CP_CONST,
4108               .resetvalue = cpu->id_isar4 },
4109             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
4110               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
4111               .access = PL1_R, .type = ARM_CP_CONST,
4112               .resetvalue = cpu->id_isar5 },
4113             /* 6..7 are as yet unallocated and must RAZ */
4114             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
4115               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
4116               .resetvalue = 0 },
4117             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
4118               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
4119               .resetvalue = 0 },
4120             REGINFO_SENTINEL
4121         };
4122         define_arm_cp_regs(cpu, v6_idregs);
4123         define_arm_cp_regs(cpu, v6_cp_reginfo);
4124     } else {
4125         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
4126     }
4127     if (arm_feature(env, ARM_FEATURE_V6K)) {
4128         define_arm_cp_regs(cpu, v6k_cp_reginfo);
4129     }
4130     if (arm_feature(env, ARM_FEATURE_V7MP) &&
4131         !arm_feature(env, ARM_FEATURE_MPU)) {
4132         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
4133     }
4134     if (arm_feature(env, ARM_FEATURE_V7)) {
4135         /* v7 performance monitor control register: same implementor
4136          * field as main ID register, and we implement only the cycle
4137          * count register.
4138          */
4139 #ifndef CONFIG_USER_ONLY
4140         ARMCPRegInfo pmcr = {
4141             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
4142             .access = PL0_RW,
4143             .type = ARM_CP_IO | ARM_CP_ALIAS,
4144             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
4145             .accessfn = pmreg_access, .writefn = pmcr_write,
4146             .raw_writefn = raw_write,
4147         };
4148         ARMCPRegInfo pmcr64 = {
4149             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
4150             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
4151             .access = PL0_RW, .accessfn = pmreg_access,
4152             .type = ARM_CP_IO,
4153             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
4154             .resetvalue = cpu->midr & 0xff000000,
4155             .writefn = pmcr_write, .raw_writefn = raw_write,
4156         };
4157         define_one_arm_cp_reg(cpu, &pmcr);
4158         define_one_arm_cp_reg(cpu, &pmcr64);
4159 #endif
4160         ARMCPRegInfo clidr = {
4161             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
4162             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
4163             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
4164         };
4165         define_one_arm_cp_reg(cpu, &clidr);
4166         define_arm_cp_regs(cpu, v7_cp_reginfo);
4167         define_debug_regs(cpu);
4168     } else {
4169         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
4170     }
4171     if (arm_feature(env, ARM_FEATURE_V8)) {
4172         /* AArch64 ID registers, which all have impdef reset values */
4173         ARMCPRegInfo v8_idregs[] = {
4174             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
4175               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
4176               .access = PL1_R, .type = ARM_CP_CONST,
4177               .resetvalue = cpu->id_aa64pfr0 },
4178             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
4179               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
4180               .access = PL1_R, .type = ARM_CP_CONST,
4181               .resetvalue = cpu->id_aa64pfr1},
4182             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
4183               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
4184               .access = PL1_R, .type = ARM_CP_CONST,
4185               /* We mask out the PMUVer field, because we don't currently
4186                * implement the PMU. Not advertising it prevents the guest
4187                * from trying to use it and getting UNDEFs on registers we
4188                * don't implement.
4189                */
4190               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
4191             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
4192               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
4193               .access = PL1_R, .type = ARM_CP_CONST,
4194               .resetvalue = cpu->id_aa64dfr1 },
4195             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
4196               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
4197               .access = PL1_R, .type = ARM_CP_CONST,
4198               .resetvalue = cpu->id_aa64afr0 },
4199             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
4200               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
4201               .access = PL1_R, .type = ARM_CP_CONST,
4202               .resetvalue = cpu->id_aa64afr1 },
4203             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
4204               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
4205               .access = PL1_R, .type = ARM_CP_CONST,
4206               .resetvalue = cpu->id_aa64isar0 },
4207             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
4208               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
4209               .access = PL1_R, .type = ARM_CP_CONST,
4210               .resetvalue = cpu->id_aa64isar1 },
4211             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
4212               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
4213               .access = PL1_R, .type = ARM_CP_CONST,
4214               .resetvalue = cpu->id_aa64mmfr0 },
4215             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
4216               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
4217               .access = PL1_R, .type = ARM_CP_CONST,
4218               .resetvalue = cpu->id_aa64mmfr1 },
4219             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
4220               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
4221               .access = PL1_R, .type = ARM_CP_CONST,
4222               .resetvalue = cpu->mvfr0 },
4223             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
4224               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
4225               .access = PL1_R, .type = ARM_CP_CONST,
4226               .resetvalue = cpu->mvfr1 },
4227             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
4228               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
4229               .access = PL1_R, .type = ARM_CP_CONST,
4230               .resetvalue = cpu->mvfr2 },
4231             REGINFO_SENTINEL
4232         };
4233         /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4234         if (!arm_feature(env, ARM_FEATURE_EL3) &&
4235             !arm_feature(env, ARM_FEATURE_EL2)) {
4236             ARMCPRegInfo rvbar = {
4237                 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
4238                 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
4239                 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
4240             };
4241             define_one_arm_cp_reg(cpu, &rvbar);
4242         }
4243         define_arm_cp_regs(cpu, v8_idregs);
4244         define_arm_cp_regs(cpu, v8_cp_reginfo);
4245     }
4246     if (arm_feature(env, ARM_FEATURE_EL2)) {
4247         uint64_t vmpidr_def = mpidr_read_val(env);
4248         ARMCPRegInfo vpidr_regs[] = {
4249             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
4250               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4251               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4252               .resetvalue = cpu->midr,
4253               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4254             { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
4255               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4256               .access = PL2_RW, .resetvalue = cpu->midr,
4257               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4258             { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
4259               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4260               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4261               .resetvalue = vmpidr_def,
4262               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4263             { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
4264               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4265               .access = PL2_RW,
4266               .resetvalue = vmpidr_def,
4267               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4268             REGINFO_SENTINEL
4269         };
4270         define_arm_cp_regs(cpu, vpidr_regs);
4271         define_arm_cp_regs(cpu, el2_cp_reginfo);
4272         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4273         if (!arm_feature(env, ARM_FEATURE_EL3)) {
4274             ARMCPRegInfo rvbar = {
4275                 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
4276                 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
4277                 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
4278             };
4279             define_one_arm_cp_reg(cpu, &rvbar);
4280         }
4281     } else {
4282         /* If EL2 is missing but higher ELs are enabled, we need to
4283          * register the no_el2 reginfos.
4284          */
4285         if (arm_feature(env, ARM_FEATURE_EL3)) {
4286             /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4287              * of MIDR_EL1 and MPIDR_EL1.
4288              */
4289             ARMCPRegInfo vpidr_regs[] = {
4290                 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4291                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4292                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4293                   .type = ARM_CP_CONST, .resetvalue = cpu->midr,
4294                   .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4295                 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4296                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4297                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4298                   .type = ARM_CP_NO_RAW,
4299                   .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
4300                 REGINFO_SENTINEL
4301             };
4302             define_arm_cp_regs(cpu, vpidr_regs);
4303             define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
4304         }
4305     }
4306     if (arm_feature(env, ARM_FEATURE_EL3)) {
4307         define_arm_cp_regs(cpu, el3_cp_reginfo);
4308         ARMCPRegInfo rvbar = {
4309             .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
4310             .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
4311             .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar
4312         };
4313         define_one_arm_cp_reg(cpu, &rvbar);
4314     }
4315     if (arm_feature(env, ARM_FEATURE_MPU)) {
4316         if (arm_feature(env, ARM_FEATURE_V6)) {
4317             /* PMSAv6 not implemented */
4318             assert(arm_feature(env, ARM_FEATURE_V7));
4319             define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4320             define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
4321         } else {
4322             define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
4323         }
4324     } else {
4325         define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4326         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
4327     }
4328     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
4329         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
4330     }
4331     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
4332         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
4333     }
4334     if (arm_feature(env, ARM_FEATURE_VAPA)) {
4335         define_arm_cp_regs(cpu, vapa_cp_reginfo);
4336     }
4337     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
4338         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
4339     }
4340     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
4341         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
4342     }
4343     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
4344         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
4345     }
4346     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
4347         define_arm_cp_regs(cpu, omap_cp_reginfo);
4348     }
4349     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
4350         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
4351     }
4352     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4353         define_arm_cp_regs(cpu, xscale_cp_reginfo);
4354     }
4355     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
4356         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
4357     }
4358     if (arm_feature(env, ARM_FEATURE_LPAE)) {
4359         define_arm_cp_regs(cpu, lpae_cp_reginfo);
4360     }
4361     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
4362      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
4363      * be read-only (ie write causes UNDEF exception).
4364      */
4365     {
4366         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
4367             /* Pre-v8 MIDR space.
4368              * Note that the MIDR isn't a simple constant register because
4369              * of the TI925 behaviour where writes to another register can
4370              * cause the MIDR value to change.
4371              *
4372              * Unimplemented registers in the c15 0 0 0 space default to
4373              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
4374              * and friends override accordingly.
4375              */
4376             { .name = "MIDR",
4377               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
4378               .access = PL1_R, .resetvalue = cpu->midr,
4379               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
4380               .readfn = midr_read,
4381               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4382               .type = ARM_CP_OVERRIDE },
4383             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
4384             { .name = "DUMMY",
4385               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
4386               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4387             { .name = "DUMMY",
4388               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
4389               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4390             { .name = "DUMMY",
4391               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
4392               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4393             { .name = "DUMMY",
4394               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
4395               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4396             { .name = "DUMMY",
4397               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
4398               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4399             REGINFO_SENTINEL
4400         };
4401         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
4402             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
4403               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
4404               .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
4405               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4406               .readfn = midr_read },
4407             /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
4408             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4409               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4410               .access = PL1_R, .resetvalue = cpu->midr },
4411             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4412               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
4413               .access = PL1_R, .resetvalue = cpu->midr },
4414             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
4415               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
4416               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
4417             REGINFO_SENTINEL
4418         };
4419         ARMCPRegInfo id_cp_reginfo[] = {
4420             /* These are common to v8 and pre-v8 */
4421             { .name = "CTR",
4422               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
4423               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4424             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
4425               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
4426               .access = PL0_R, .accessfn = ctr_el0_access,
4427               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4428             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
4429             { .name = "TCMTR",
4430               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
4431               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4432             REGINFO_SENTINEL
4433         };
4434         /* TLBTR is specific to VMSA */
4435         ARMCPRegInfo id_tlbtr_reginfo = {
4436               .name = "TLBTR",
4437               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
4438               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
4439         };
4440         /* MPUIR is specific to PMSA V6+ */
4441         ARMCPRegInfo id_mpuir_reginfo = {
4442               .name = "MPUIR",
4443               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4444               .access = PL1_R, .type = ARM_CP_CONST,
4445               .resetvalue = cpu->pmsav7_dregion << 8
4446         };
4447         ARMCPRegInfo crn0_wi_reginfo = {
4448             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
4449             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
4450             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
4451         };
4452         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
4453             arm_feature(env, ARM_FEATURE_STRONGARM)) {
4454             ARMCPRegInfo *r;
4455             /* Register the blanket "writes ignored" value first to cover the
4456              * whole space. Then update the specific ID registers to allow write
4457              * access, so that they ignore writes rather than causing them to
4458              * UNDEF.
4459              */
4460             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
4461             for (r = id_pre_v8_midr_cp_reginfo;
4462                  r->type != ARM_CP_SENTINEL; r++) {
4463                 r->access = PL1_RW;
4464             }
4465             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
4466                 r->access = PL1_RW;
4467             }
4468             id_tlbtr_reginfo.access = PL1_RW;
4469             id_tlbtr_reginfo.access = PL1_RW;
4470         }
4471         if (arm_feature(env, ARM_FEATURE_V8)) {
4472             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
4473         } else {
4474             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
4475         }
4476         define_arm_cp_regs(cpu, id_cp_reginfo);
4477         if (!arm_feature(env, ARM_FEATURE_MPU)) {
4478             define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
4479         } else if (arm_feature(env, ARM_FEATURE_V7)) {
4480             define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
4481         }
4482     }
4483
4484     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
4485         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
4486     }
4487
4488     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
4489         ARMCPRegInfo auxcr_reginfo[] = {
4490             { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
4491               .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
4492               .access = PL1_RW, .type = ARM_CP_CONST,
4493               .resetvalue = cpu->reset_auxcr },
4494             { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
4495               .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
4496               .access = PL2_RW, .type = ARM_CP_CONST,
4497               .resetvalue = 0 },
4498             { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
4499               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
4500               .access = PL3_RW, .type = ARM_CP_CONST,
4501               .resetvalue = 0 },
4502             REGINFO_SENTINEL
4503         };
4504         define_arm_cp_regs(cpu, auxcr_reginfo);
4505     }
4506
4507     if (arm_feature(env, ARM_FEATURE_CBAR)) {
4508         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4509             /* 32 bit view is [31:18] 0...0 [43:32]. */
4510             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
4511                 | extract64(cpu->reset_cbar, 32, 12);
4512             ARMCPRegInfo cbar_reginfo[] = {
4513                 { .name = "CBAR",
4514                   .type = ARM_CP_CONST,
4515                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4516                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
4517                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
4518                   .type = ARM_CP_CONST,
4519                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
4520                   .access = PL1_R, .resetvalue = cbar32 },
4521                 REGINFO_SENTINEL
4522             };
4523             /* We don't implement a r/w 64 bit CBAR currently */
4524             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
4525             define_arm_cp_regs(cpu, cbar_reginfo);
4526         } else {
4527             ARMCPRegInfo cbar = {
4528                 .name = "CBAR",
4529                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4530                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
4531                 .fieldoffset = offsetof(CPUARMState,
4532                                         cp15.c15_config_base_address)
4533             };
4534             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
4535                 cbar.access = PL1_R;
4536                 cbar.fieldoffset = 0;
4537                 cbar.type = ARM_CP_CONST;
4538             }
4539             define_one_arm_cp_reg(cpu, &cbar);
4540         }
4541     }
4542
4543     /* Generic registers whose values depend on the implementation */
4544     {
4545         ARMCPRegInfo sctlr = {
4546             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
4547             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
4548             .access = PL1_RW,
4549             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
4550                                    offsetof(CPUARMState, cp15.sctlr_ns) },
4551             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
4552             .raw_writefn = raw_write,
4553         };
4554         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4555             /* Normally we would always end the TB on an SCTLR write, but Linux
4556              * arch/arm/mach-pxa/sleep.S expects two instructions following
4557              * an MMU enable to execute from cache.  Imitate this behaviour.
4558              */
4559             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
4560         }
4561         define_one_arm_cp_reg(cpu, &sctlr);
4562     }
4563 }
4564
4565 ARMCPU *cpu_arm_init(const char *cpu_model)
4566 {
4567     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
4568 }
4569
4570 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
4571 {
4572     CPUState *cs = CPU(cpu);
4573     CPUARMState *env = &cpu->env;
4574
4575     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4576         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
4577                                  aarch64_fpu_gdb_set_reg,
4578                                  34, "aarch64-fpu.xml", 0);
4579     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
4580         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4581                                  51, "arm-neon.xml", 0);
4582     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
4583         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4584                                  35, "arm-vfp3.xml", 0);
4585     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
4586         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4587                                  19, "arm-vfp.xml", 0);
4588     }
4589 }
4590
4591 /* Sort alphabetically by type name, except for "any". */
4592 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
4593 {
4594     ObjectClass *class_a = (ObjectClass *)a;
4595     ObjectClass *class_b = (ObjectClass *)b;
4596     const char *name_a, *name_b;
4597
4598     name_a = object_class_get_name(class_a);
4599     name_b = object_class_get_name(class_b);
4600     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
4601         return 1;
4602     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
4603         return -1;
4604     } else {
4605         return strcmp(name_a, name_b);
4606     }
4607 }
4608
4609 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
4610 {
4611     ObjectClass *oc = data;
4612     CPUListState *s = user_data;
4613     const char *typename;
4614     char *name;
4615
4616     typename = object_class_get_name(oc);
4617     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
4618     (*s->cpu_fprintf)(s->file, "  %s\n",
4619                       name);
4620     g_free(name);
4621 }
4622
4623 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
4624 {
4625     CPUListState s = {
4626         .file = f,
4627         .cpu_fprintf = cpu_fprintf,
4628     };
4629     GSList *list;
4630
4631     list = object_class_get_list(TYPE_ARM_CPU, false);
4632     list = g_slist_sort(list, arm_cpu_list_compare);
4633     (*cpu_fprintf)(f, "Available CPUs:\n");
4634     g_slist_foreach(list, arm_cpu_list_entry, &s);
4635     g_slist_free(list);
4636 #ifdef CONFIG_KVM
4637     /* The 'host' CPU type is dynamically registered only if KVM is
4638      * enabled, so we have to special-case it here:
4639      */
4640     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
4641 #endif
4642 }
4643
4644 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
4645 {
4646     ObjectClass *oc = data;
4647     CpuDefinitionInfoList **cpu_list = user_data;
4648     CpuDefinitionInfoList *entry;
4649     CpuDefinitionInfo *info;
4650     const char *typename;
4651
4652     typename = object_class_get_name(oc);
4653     info = g_malloc0(sizeof(*info));
4654     info->name = g_strndup(typename,
4655                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
4656
4657     entry = g_malloc0(sizeof(*entry));
4658     entry->value = info;
4659     entry->next = *cpu_list;
4660     *cpu_list = entry;
4661 }
4662
4663 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
4664 {
4665     CpuDefinitionInfoList *cpu_list = NULL;
4666     GSList *list;
4667
4668     list = object_class_get_list(TYPE_ARM_CPU, false);
4669     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
4670     g_slist_free(list);
4671
4672     return cpu_list;
4673 }
4674
4675 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
4676                                    void *opaque, int state, int secstate,
4677                                    int crm, int opc1, int opc2)
4678 {
4679     /* Private utility function for define_one_arm_cp_reg_with_opaque():
4680      * add a single reginfo struct to the hash table.
4681      */
4682     uint32_t *key = g_new(uint32_t, 1);
4683     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
4684     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
4685     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
4686
4687     /* Reset the secure state to the specific incoming state.  This is
4688      * necessary as the register may have been defined with both states.
4689      */
4690     r2->secure = secstate;
4691
4692     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
4693         /* Register is banked (using both entries in array).
4694          * Overwriting fieldoffset as the array is only used to define
4695          * banked registers but later only fieldoffset is used.
4696          */
4697         r2->fieldoffset = r->bank_fieldoffsets[ns];
4698     }
4699
4700     if (state == ARM_CP_STATE_AA32) {
4701         if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
4702             /* If the register is banked then we don't need to migrate or
4703              * reset the 32-bit instance in certain cases:
4704              *
4705              * 1) If the register has both 32-bit and 64-bit instances then we
4706              *    can count on the 64-bit instance taking care of the
4707              *    non-secure bank.
4708              * 2) If ARMv8 is enabled then we can count on a 64-bit version
4709              *    taking care of the secure bank.  This requires that separate
4710              *    32 and 64-bit definitions are provided.
4711              */
4712             if ((r->state == ARM_CP_STATE_BOTH && ns) ||
4713                 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
4714                 r2->type |= ARM_CP_ALIAS;
4715             }
4716         } else if ((secstate != r->secure) && !ns) {
4717             /* The register is not banked so we only want to allow migration of
4718              * the non-secure instance.
4719              */
4720             r2->type |= ARM_CP_ALIAS;
4721         }
4722
4723         if (r->state == ARM_CP_STATE_BOTH) {
4724             /* We assume it is a cp15 register if the .cp field is left unset.
4725              */
4726             if (r2->cp == 0) {
4727                 r2->cp = 15;
4728             }
4729
4730 #ifdef HOST_WORDS_BIGENDIAN
4731             if (r2->fieldoffset) {
4732                 r2->fieldoffset += sizeof(uint32_t);
4733             }
4734 #endif
4735         }
4736     }
4737     if (state == ARM_CP_STATE_AA64) {
4738         /* To allow abbreviation of ARMCPRegInfo
4739          * definitions, we treat cp == 0 as equivalent to
4740          * the value for "standard guest-visible sysreg".
4741          * STATE_BOTH definitions are also always "standard
4742          * sysreg" in their AArch64 view (the .cp value may
4743          * be non-zero for the benefit of the AArch32 view).
4744          */
4745         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
4746             r2->cp = CP_REG_ARM64_SYSREG_CP;
4747         }
4748         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
4749                                   r2->opc0, opc1, opc2);
4750     } else {
4751         *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
4752     }
4753     if (opaque) {
4754         r2->opaque = opaque;
4755     }
4756     /* reginfo passed to helpers is correct for the actual access,
4757      * and is never ARM_CP_STATE_BOTH:
4758      */
4759     r2->state = state;
4760     /* Make sure reginfo passed to helpers for wildcarded regs
4761      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
4762      */
4763     r2->crm = crm;
4764     r2->opc1 = opc1;
4765     r2->opc2 = opc2;
4766     /* By convention, for wildcarded registers only the first
4767      * entry is used for migration; the others are marked as
4768      * ALIAS so we don't try to transfer the register
4769      * multiple times. Special registers (ie NOP/WFI) are
4770      * never migratable and not even raw-accessible.
4771      */
4772     if ((r->type & ARM_CP_SPECIAL)) {
4773         r2->type |= ARM_CP_NO_RAW;
4774     }
4775     if (((r->crm == CP_ANY) && crm != 0) ||
4776         ((r->opc1 == CP_ANY) && opc1 != 0) ||
4777         ((r->opc2 == CP_ANY) && opc2 != 0)) {
4778         r2->type |= ARM_CP_ALIAS;
4779     }
4780
4781     /* Check that raw accesses are either forbidden or handled. Note that
4782      * we can't assert this earlier because the setup of fieldoffset for
4783      * banked registers has to be done first.
4784      */
4785     if (!(r2->type & ARM_CP_NO_RAW)) {
4786         assert(!raw_accessors_invalid(r2));
4787     }
4788
4789     /* Overriding of an existing definition must be explicitly
4790      * requested.
4791      */
4792     if (!(r->type & ARM_CP_OVERRIDE)) {
4793         ARMCPRegInfo *oldreg;
4794         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
4795         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
4796             fprintf(stderr, "Register redefined: cp=%d %d bit "
4797                     "crn=%d crm=%d opc1=%d opc2=%d, "
4798                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
4799                     r2->crn, r2->crm, r2->opc1, r2->opc2,
4800                     oldreg->name, r2->name);
4801             g_assert_not_reached();
4802         }
4803     }
4804     g_hash_table_insert(cpu->cp_regs, key, r2);
4805 }
4806
4807
4808 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
4809                                        const ARMCPRegInfo *r, void *opaque)
4810 {
4811     /* Define implementations of coprocessor registers.
4812      * We store these in a hashtable because typically
4813      * there are less than 150 registers in a space which
4814      * is 16*16*16*8*8 = 262144 in size.
4815      * Wildcarding is supported for the crm, opc1 and opc2 fields.
4816      * If a register is defined twice then the second definition is
4817      * used, so this can be used to define some generic registers and
4818      * then override them with implementation specific variations.
4819      * At least one of the original and the second definition should
4820      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
4821      * against accidental use.
4822      *
4823      * The state field defines whether the register is to be
4824      * visible in the AArch32 or AArch64 execution state. If the
4825      * state is set to ARM_CP_STATE_BOTH then we synthesise a
4826      * reginfo structure for the AArch32 view, which sees the lower
4827      * 32 bits of the 64 bit register.
4828      *
4829      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
4830      * be wildcarded. AArch64 registers are always considered to be 64
4831      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
4832      * the register, if any.
4833      */
4834     int crm, opc1, opc2, state;
4835     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
4836     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
4837     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
4838     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
4839     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
4840     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
4841     /* 64 bit registers have only CRm and Opc1 fields */
4842     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
4843     /* op0 only exists in the AArch64 encodings */
4844     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
4845     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
4846     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
4847     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
4848      * encodes a minimum access level for the register. We roll this
4849      * runtime check into our general permission check code, so check
4850      * here that the reginfo's specified permissions are strict enough
4851      * to encompass the generic architectural permission check.
4852      */
4853     if (r->state != ARM_CP_STATE_AA32) {
4854         int mask = 0;
4855         switch (r->opc1) {
4856         case 0: case 1: case 2:
4857             /* min_EL EL1 */
4858             mask = PL1_RW;
4859             break;
4860         case 3:
4861             /* min_EL EL0 */
4862             mask = PL0_RW;
4863             break;
4864         case 4:
4865             /* min_EL EL2 */
4866             mask = PL2_RW;
4867             break;
4868         case 5:
4869             /* unallocated encoding, so not possible */
4870             assert(false);
4871             break;
4872         case 6:
4873             /* min_EL EL3 */
4874             mask = PL3_RW;
4875             break;
4876         case 7:
4877             /* min_EL EL1, secure mode only (we don't check the latter) */
4878             mask = PL1_RW;
4879             break;
4880         default:
4881             /* broken reginfo with out-of-range opc1 */
4882             assert(false);
4883             break;
4884         }
4885         /* assert our permissions are not too lax (stricter is fine) */
4886         assert((r->access & ~mask) == 0);
4887     }
4888
4889     /* Check that the register definition has enough info to handle
4890      * reads and writes if they are permitted.
4891      */
4892     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
4893         if (r->access & PL3_R) {
4894             assert((r->fieldoffset ||
4895                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
4896                    r->readfn);
4897         }
4898         if (r->access & PL3_W) {
4899             assert((r->fieldoffset ||
4900                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
4901                    r->writefn);
4902         }
4903     }
4904     /* Bad type field probably means missing sentinel at end of reg list */
4905     assert(cptype_valid(r->type));
4906     for (crm = crmmin; crm <= crmmax; crm++) {
4907         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
4908             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
4909                 for (state = ARM_CP_STATE_AA32;
4910                      state <= ARM_CP_STATE_AA64; state++) {
4911                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
4912                         continue;
4913                     }
4914                     if (state == ARM_CP_STATE_AA32) {
4915                         /* Under AArch32 CP registers can be common
4916                          * (same for secure and non-secure world) or banked.
4917                          */
4918                         switch (r->secure) {
4919                         case ARM_CP_SECSTATE_S:
4920                         case ARM_CP_SECSTATE_NS:
4921                             add_cpreg_to_hashtable(cpu, r, opaque, state,
4922                                                    r->secure, crm, opc1, opc2);
4923                             break;
4924                         default:
4925                             add_cpreg_to_hashtable(cpu, r, opaque, state,
4926                                                    ARM_CP_SECSTATE_S,
4927                                                    crm, opc1, opc2);
4928                             add_cpreg_to_hashtable(cpu, r, opaque, state,
4929                                                    ARM_CP_SECSTATE_NS,
4930                                                    crm, opc1, opc2);
4931                             break;
4932                         }
4933                     } else {
4934                         /* AArch64 registers get mapped to non-secure instance
4935                          * of AArch32 */
4936                         add_cpreg_to_hashtable(cpu, r, opaque, state,
4937                                                ARM_CP_SECSTATE_NS,
4938                                                crm, opc1, opc2);
4939                     }
4940                 }
4941             }
4942         }
4943     }
4944 }
4945
4946 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
4947                                     const ARMCPRegInfo *regs, void *opaque)
4948 {
4949     /* Define a whole list of registers */
4950     const ARMCPRegInfo *r;
4951     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
4952         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
4953     }
4954 }
4955
4956 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
4957 {
4958     return g_hash_table_lookup(cpregs, &encoded_cp);
4959 }
4960
4961 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
4962                          uint64_t value)
4963 {
4964     /* Helper coprocessor write function for write-ignore registers */
4965 }
4966
4967 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
4968 {
4969     /* Helper coprocessor write function for read-as-zero registers */
4970     return 0;
4971 }
4972
4973 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
4974 {
4975     /* Helper coprocessor reset function for do-nothing-on-reset registers */
4976 }
4977
4978 static int bad_mode_switch(CPUARMState *env, int mode)
4979 {
4980     /* Return true if it is not valid for us to switch to
4981      * this CPU mode (ie all the UNPREDICTABLE cases in
4982      * the ARM ARM CPSRWriteByInstr pseudocode).
4983      */
4984     switch (mode) {
4985     case ARM_CPU_MODE_USR:
4986     case ARM_CPU_MODE_SYS:
4987     case ARM_CPU_MODE_SVC:
4988     case ARM_CPU_MODE_ABT:
4989     case ARM_CPU_MODE_UND:
4990     case ARM_CPU_MODE_IRQ:
4991     case ARM_CPU_MODE_FIQ:
4992         return 0;
4993     case ARM_CPU_MODE_MON:
4994         return !arm_is_secure(env);
4995     default:
4996         return 1;
4997     }
4998 }
4999
5000 uint32_t cpsr_read(CPUARMState *env)
5001 {
5002     int ZF;
5003     ZF = (env->ZF == 0);
5004     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
5005         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
5006         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
5007         | ((env->condexec_bits & 0xfc) << 8)
5008         | (env->GE << 16) | (env->daif & CPSR_AIF);
5009 }
5010
5011 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
5012 {
5013     uint32_t changed_daif;
5014
5015     if (mask & CPSR_NZCV) {
5016         env->ZF = (~val) & CPSR_Z;
5017         env->NF = val;
5018         env->CF = (val >> 29) & 1;
5019         env->VF = (val << 3) & 0x80000000;
5020     }
5021     if (mask & CPSR_Q)
5022         env->QF = ((val & CPSR_Q) != 0);
5023     if (mask & CPSR_T)
5024         env->thumb = ((val & CPSR_T) != 0);
5025     if (mask & CPSR_IT_0_1) {
5026         env->condexec_bits &= ~3;
5027         env->condexec_bits |= (val >> 25) & 3;
5028     }
5029     if (mask & CPSR_IT_2_7) {
5030         env->condexec_bits &= 3;
5031         env->condexec_bits |= (val >> 8) & 0xfc;
5032     }
5033     if (mask & CPSR_GE) {
5034         env->GE = (val >> 16) & 0xf;
5035     }
5036
5037     /* In a V7 implementation that includes the security extensions but does
5038      * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5039      * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5040      * bits respectively.
5041      *
5042      * In a V8 implementation, it is permitted for privileged software to
5043      * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5044      */
5045     if (!arm_feature(env, ARM_FEATURE_V8) &&
5046         arm_feature(env, ARM_FEATURE_EL3) &&
5047         !arm_feature(env, ARM_FEATURE_EL2) &&
5048         !arm_is_secure(env)) {
5049
5050         changed_daif = (env->daif ^ val) & mask;
5051
5052         if (changed_daif & CPSR_A) {
5053             /* Check to see if we are allowed to change the masking of async
5054              * abort exceptions from a non-secure state.
5055              */
5056             if (!(env->cp15.scr_el3 & SCR_AW)) {
5057                 qemu_log_mask(LOG_GUEST_ERROR,
5058                               "Ignoring attempt to switch CPSR_A flag from "
5059                               "non-secure world with SCR.AW bit clear\n");
5060                 mask &= ~CPSR_A;
5061             }
5062         }
5063
5064         if (changed_daif & CPSR_F) {
5065             /* Check to see if we are allowed to change the masking of FIQ
5066              * exceptions from a non-secure state.
5067              */
5068             if (!(env->cp15.scr_el3 & SCR_FW)) {
5069                 qemu_log_mask(LOG_GUEST_ERROR,
5070                               "Ignoring attempt to switch CPSR_F flag from "
5071                               "non-secure world with SCR.FW bit clear\n");
5072                 mask &= ~CPSR_F;
5073             }
5074
5075             /* Check whether non-maskable FIQ (NMFI) support is enabled.
5076              * If this bit is set software is not allowed to mask
5077              * FIQs, but is allowed to set CPSR_F to 0.
5078              */
5079             if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
5080                 (val & CPSR_F)) {
5081                 qemu_log_mask(LOG_GUEST_ERROR,
5082                               "Ignoring attempt to enable CPSR_F flag "
5083                               "(non-maskable FIQ [NMFI] support enabled)\n");
5084                 mask &= ~CPSR_F;
5085             }
5086         }
5087     }
5088
5089     env->daif &= ~(CPSR_AIF & mask);
5090     env->daif |= val & CPSR_AIF & mask;
5091
5092     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
5093         if (bad_mode_switch(env, val & CPSR_M)) {
5094             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
5095              * We choose to ignore the attempt and leave the CPSR M field
5096              * untouched.
5097              */
5098             mask &= ~CPSR_M;
5099         } else {
5100             switch_mode(env, val & CPSR_M);
5101         }
5102     }
5103     mask &= ~CACHED_CPSR_BITS;
5104     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
5105 }
5106
5107 /* Sign/zero extend */
5108 uint32_t HELPER(sxtb16)(uint32_t x)
5109 {
5110     uint32_t res;
5111     res = (uint16_t)(int8_t)x;
5112     res |= (uint32_t)(int8_t)(x >> 16) << 16;
5113     return res;
5114 }
5115
5116 uint32_t HELPER(uxtb16)(uint32_t x)
5117 {
5118     uint32_t res;
5119     res = (uint16_t)(uint8_t)x;
5120     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
5121     return res;
5122 }
5123
5124 uint32_t HELPER(clz)(uint32_t x)
5125 {
5126     return clz32(x);
5127 }
5128
5129 int32_t HELPER(sdiv)(int32_t num, int32_t den)
5130 {
5131     if (den == 0)
5132       return 0;
5133     if (num == INT_MIN && den == -1)
5134       return INT_MIN;
5135     return num / den;
5136 }
5137
5138 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
5139 {
5140     if (den == 0)
5141       return 0;
5142     return num / den;
5143 }
5144
5145 uint32_t HELPER(rbit)(uint32_t x)
5146 {
5147     return revbit32(x);
5148 }
5149
5150 #if defined(CONFIG_USER_ONLY)
5151
5152 /* These should probably raise undefined insn exceptions.  */
5153 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
5154 {
5155     ARMCPU *cpu = arm_env_get_cpu(env);
5156
5157     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
5158 }
5159
5160 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
5161 {
5162     ARMCPU *cpu = arm_env_get_cpu(env);
5163
5164     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
5165     return 0;
5166 }
5167
5168 void switch_mode(CPUARMState *env, int mode)
5169 {
5170     ARMCPU *cpu = arm_env_get_cpu(env);
5171
5172     if (mode != ARM_CPU_MODE_USR) {
5173         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
5174     }
5175 }
5176
5177 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
5178 {
5179     ARMCPU *cpu = arm_env_get_cpu(env);
5180
5181     cpu_abort(CPU(cpu), "banked r13 write\n");
5182 }
5183
5184 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
5185 {
5186     ARMCPU *cpu = arm_env_get_cpu(env);
5187
5188     cpu_abort(CPU(cpu), "banked r13 read\n");
5189     return 0;
5190 }
5191
5192 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5193                                  uint32_t cur_el, bool secure)
5194 {
5195     return 1;
5196 }
5197
5198 void aarch64_sync_64_to_32(CPUARMState *env)
5199 {
5200     g_assert_not_reached();
5201 }
5202
5203 #else
5204
5205 /* Map CPU modes onto saved register banks.  */
5206 int bank_number(int mode)
5207 {
5208     switch (mode) {
5209     case ARM_CPU_MODE_USR:
5210     case ARM_CPU_MODE_SYS:
5211         return BANK_USRSYS;
5212     case ARM_CPU_MODE_SVC:
5213         return BANK_SVC;
5214     case ARM_CPU_MODE_ABT:
5215         return BANK_ABT;
5216     case ARM_CPU_MODE_UND:
5217         return BANK_UND;
5218     case ARM_CPU_MODE_IRQ:
5219         return BANK_IRQ;
5220     case ARM_CPU_MODE_FIQ:
5221         return BANK_FIQ;
5222     case ARM_CPU_MODE_HYP:
5223         return BANK_HYP;
5224     case ARM_CPU_MODE_MON:
5225         return BANK_MON;
5226     }
5227     g_assert_not_reached();
5228 }
5229
5230 void switch_mode(CPUARMState *env, int mode)
5231 {
5232     int old_mode;
5233     int i;
5234
5235     old_mode = env->uncached_cpsr & CPSR_M;
5236     if (mode == old_mode)
5237         return;
5238
5239     if (old_mode == ARM_CPU_MODE_FIQ) {
5240         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
5241         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
5242     } else if (mode == ARM_CPU_MODE_FIQ) {
5243         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
5244         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
5245     }
5246
5247     i = bank_number(old_mode);
5248     env->banked_r13[i] = env->regs[13];
5249     env->banked_r14[i] = env->regs[14];
5250     env->banked_spsr[i] = env->spsr;
5251
5252     i = bank_number(mode);
5253     env->regs[13] = env->banked_r13[i];
5254     env->regs[14] = env->banked_r14[i];
5255     env->spsr = env->banked_spsr[i];
5256 }
5257
5258 /* Physical Interrupt Target EL Lookup Table
5259  *
5260  * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5261  *
5262  * The below multi-dimensional table is used for looking up the target
5263  * exception level given numerous condition criteria.  Specifically, the
5264  * target EL is based on SCR and HCR routing controls as well as the
5265  * currently executing EL and secure state.
5266  *
5267  *    Dimensions:
5268  *    target_el_table[2][2][2][2][2][4]
5269  *                    |  |  |  |  |  +--- Current EL
5270  *                    |  |  |  |  +------ Non-secure(0)/Secure(1)
5271  *                    |  |  |  +--------- HCR mask override
5272  *                    |  |  +------------ SCR exec state control
5273  *                    |  +--------------- SCR mask override
5274  *                    +------------------ 32-bit(0)/64-bit(1) EL3
5275  *
5276  *    The table values are as such:
5277  *    0-3 = EL0-EL3
5278  *     -1 = Cannot occur
5279  *
5280  * The ARM ARM target EL table includes entries indicating that an "exception
5281  * is not taken".  The two cases where this is applicable are:
5282  *    1) An exception is taken from EL3 but the SCR does not have the exception
5283  *    routed to EL3.
5284  *    2) An exception is taken from EL2 but the HCR does not have the exception
5285  *    routed to EL2.
5286  * In these two cases, the below table contain a target of EL1.  This value is
5287  * returned as it is expected that the consumer of the table data will check
5288  * for "target EL >= current EL" to ensure the exception is not taken.
5289  *
5290  *            SCR     HCR
5291  *         64  EA     AMO                 From
5292  *        BIT IRQ     IMO      Non-secure         Secure
5293  *        EL3 FIQ  RW FMO   EL0 EL1 EL2 EL3   EL0 EL1 EL2 EL3
5294  */
5295 static const int8_t target_el_table[2][2][2][2][2][4] = {
5296     {{{{/* 0   0   0   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5297        {/* 0   0   0   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},
5298       {{/* 0   0   1   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5299        {/* 0   0   1   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},},
5300      {{{/* 0   1   0   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5301        {/* 0   1   0   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},
5302       {{/* 0   1   1   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5303        {/* 0   1   1   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},},},
5304     {{{{/* 1   0   0   0 */{ 1,  1,  2, -1 },{ 1,  1, -1,  1 },},
5305        {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},
5306       {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1, -1,  1 },},
5307        {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},},
5308      {{{/* 1   1   0   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5309        {/* 1   1   0   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},
5310       {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5311        {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},},},
5312 };
5313
5314 /*
5315  * Determine the target EL for physical exceptions
5316  */
5317 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5318                                  uint32_t cur_el, bool secure)
5319 {
5320     CPUARMState *env = cs->env_ptr;
5321     int rw;
5322     int scr;
5323     int hcr;
5324     int target_el;
5325     /* Is the highest EL AArch64? */
5326     int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
5327
5328     if (arm_feature(env, ARM_FEATURE_EL3)) {
5329         rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
5330     } else {
5331         /* Either EL2 is the highest EL (and so the EL2 register width
5332          * is given by is64); or there is no EL2 or EL3, in which case
5333          * the value of 'rw' does not affect the table lookup anyway.
5334          */
5335         rw = is64;
5336     }
5337
5338     switch (excp_idx) {
5339     case EXCP_IRQ:
5340         scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
5341         hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
5342         break;
5343     case EXCP_FIQ:
5344         scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
5345         hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
5346         break;
5347     default:
5348         scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
5349         hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
5350         break;
5351     };
5352
5353     /* If HCR.TGE is set then HCR is treated as being 1 */
5354     hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
5355
5356     /* Perform a table-lookup for the target EL given the current state */
5357     target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
5358
5359     assert(target_el > 0);
5360
5361     return target_el;
5362 }
5363
5364 static void v7m_push(CPUARMState *env, uint32_t val)
5365 {
5366     CPUState *cs = CPU(arm_env_get_cpu(env));
5367
5368     env->regs[13] -= 4;
5369     stl_phys(cs->as, env->regs[13], val);
5370 }
5371
5372 static uint32_t v7m_pop(CPUARMState *env)
5373 {
5374     CPUState *cs = CPU(arm_env_get_cpu(env));
5375     uint32_t val;
5376
5377     val = ldl_phys(cs->as, env->regs[13]);
5378     env->regs[13] += 4;
5379     return val;
5380 }
5381
5382 /* Switch to V7M main or process stack pointer.  */
5383 static void switch_v7m_sp(CPUARMState *env, int process)
5384 {
5385     uint32_t tmp;
5386     if (env->v7m.current_sp != process) {
5387         tmp = env->v7m.other_sp;
5388         env->v7m.other_sp = env->regs[13];
5389         env->regs[13] = tmp;
5390         env->v7m.current_sp = process;
5391     }
5392 }
5393
5394 static void do_v7m_exception_exit(CPUARMState *env)
5395 {
5396     uint32_t type;
5397     uint32_t xpsr;
5398
5399     type = env->regs[15];
5400     if (env->v7m.exception != 0)
5401         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
5402
5403     /* Switch to the target stack.  */
5404     switch_v7m_sp(env, (type & 4) != 0);
5405     /* Pop registers.  */
5406     env->regs[0] = v7m_pop(env);
5407     env->regs[1] = v7m_pop(env);
5408     env->regs[2] = v7m_pop(env);
5409     env->regs[3] = v7m_pop(env);
5410     env->regs[12] = v7m_pop(env);
5411     env->regs[14] = v7m_pop(env);
5412     env->regs[15] = v7m_pop(env);
5413     if (env->regs[15] & 1) {
5414         qemu_log_mask(LOG_GUEST_ERROR,
5415                       "M profile return from interrupt with misaligned "
5416                       "PC is UNPREDICTABLE\n");
5417         /* Actual hardware seems to ignore the lsbit, and there are several
5418          * RTOSes out there which incorrectly assume the r15 in the stack
5419          * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
5420          */
5421         env->regs[15] &= ~1U;
5422     }
5423     xpsr = v7m_pop(env);
5424     xpsr_write(env, xpsr, 0xfffffdff);
5425     /* Undo stack alignment.  */
5426     if (xpsr & 0x200)
5427         env->regs[13] |= 4;
5428     /* ??? The exception return type specifies Thread/Handler mode.  However
5429        this is also implied by the xPSR value. Not sure what to do
5430        if there is a mismatch.  */
5431     /* ??? Likewise for mismatches between the CONTROL register and the stack
5432        pointer.  */
5433 }
5434
5435 void arm_v7m_cpu_do_interrupt(CPUState *cs)
5436 {
5437     ARMCPU *cpu = ARM_CPU(cs);
5438     CPUARMState *env = &cpu->env;
5439     uint32_t xpsr = xpsr_read(env);
5440     uint32_t lr;
5441     uint32_t addr;
5442
5443     arm_log_exception(cs->exception_index);
5444
5445     lr = 0xfffffff1;
5446     if (env->v7m.current_sp)
5447         lr |= 4;
5448     if (env->v7m.exception == 0)
5449         lr |= 8;
5450
5451     /* For exceptions we just mark as pending on the NVIC, and let that
5452        handle it.  */
5453     /* TODO: Need to escalate if the current priority is higher than the
5454        one we're raising.  */
5455     switch (cs->exception_index) {
5456     case EXCP_UDEF:
5457         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
5458         return;
5459     case EXCP_SWI:
5460         /* The PC already points to the next instruction.  */
5461         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
5462         return;
5463     case EXCP_PREFETCH_ABORT:
5464     case EXCP_DATA_ABORT:
5465         /* TODO: if we implemented the MPU registers, this is where we
5466          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
5467          */
5468         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
5469         return;
5470     case EXCP_BKPT:
5471         if (semihosting_enabled()) {
5472             int nr;
5473             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
5474             if (nr == 0xab) {
5475                 env->regs[15] += 2;
5476                 qemu_log_mask(CPU_LOG_INT,
5477                               "...handling as semihosting call 0x%x\n",
5478                               env->regs[0]);
5479                 env->regs[0] = do_arm_semihosting(env);
5480                 return;
5481             }
5482         }
5483         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
5484         return;
5485     case EXCP_IRQ:
5486         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
5487         break;
5488     case EXCP_EXCEPTION_EXIT:
5489         do_v7m_exception_exit(env);
5490         return;
5491     default:
5492         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5493         return; /* Never happens.  Keep compiler happy.  */
5494     }
5495
5496     /* Align stack pointer.  */
5497     /* ??? Should only do this if Configuration Control Register
5498        STACKALIGN bit is set.  */
5499     if (env->regs[13] & 4) {
5500         env->regs[13] -= 4;
5501         xpsr |= 0x200;
5502     }
5503     /* Switch to the handler mode.  */
5504     v7m_push(env, xpsr);
5505     v7m_push(env, env->regs[15]);
5506     v7m_push(env, env->regs[14]);
5507     v7m_push(env, env->regs[12]);
5508     v7m_push(env, env->regs[3]);
5509     v7m_push(env, env->regs[2]);
5510     v7m_push(env, env->regs[1]);
5511     v7m_push(env, env->regs[0]);
5512     switch_v7m_sp(env, 0);
5513     /* Clear IT bits */
5514     env->condexec_bits = 0;
5515     env->regs[14] = lr;
5516     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
5517     env->regs[15] = addr & 0xfffffffe;
5518     env->thumb = addr & 1;
5519 }
5520
5521 /* Function used to synchronize QEMU's AArch64 register set with AArch32
5522  * register set.  This is necessary when switching between AArch32 and AArch64
5523  * execution state.
5524  */
5525 void aarch64_sync_32_to_64(CPUARMState *env)
5526 {
5527     int i;
5528     uint32_t mode = env->uncached_cpsr & CPSR_M;
5529
5530     /* We can blanket copy R[0:7] to X[0:7] */
5531     for (i = 0; i < 8; i++) {
5532         env->xregs[i] = env->regs[i];
5533     }
5534
5535     /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
5536      * Otherwise, they come from the banked user regs.
5537      */
5538     if (mode == ARM_CPU_MODE_FIQ) {
5539         for (i = 8; i < 13; i++) {
5540             env->xregs[i] = env->usr_regs[i - 8];
5541         }
5542     } else {
5543         for (i = 8; i < 13; i++) {
5544             env->xregs[i] = env->regs[i];
5545         }
5546     }
5547
5548     /* Registers x13-x23 are the various mode SP and FP registers. Registers
5549      * r13 and r14 are only copied if we are in that mode, otherwise we copy
5550      * from the mode banked register.
5551      */
5552     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5553         env->xregs[13] = env->regs[13];
5554         env->xregs[14] = env->regs[14];
5555     } else {
5556         env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
5557         /* HYP is an exception in that it is copied from r14 */
5558         if (mode == ARM_CPU_MODE_HYP) {
5559             env->xregs[14] = env->regs[14];
5560         } else {
5561             env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
5562         }
5563     }
5564
5565     if (mode == ARM_CPU_MODE_HYP) {
5566         env->xregs[15] = env->regs[13];
5567     } else {
5568         env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
5569     }
5570
5571     if (mode == ARM_CPU_MODE_IRQ) {
5572         env->xregs[16] = env->regs[14];
5573         env->xregs[17] = env->regs[13];
5574     } else {
5575         env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
5576         env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
5577     }
5578
5579     if (mode == ARM_CPU_MODE_SVC) {
5580         env->xregs[18] = env->regs[14];
5581         env->xregs[19] = env->regs[13];
5582     } else {
5583         env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
5584         env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
5585     }
5586
5587     if (mode == ARM_CPU_MODE_ABT) {
5588         env->xregs[20] = env->regs[14];
5589         env->xregs[21] = env->regs[13];
5590     } else {
5591         env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
5592         env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
5593     }
5594
5595     if (mode == ARM_CPU_MODE_UND) {
5596         env->xregs[22] = env->regs[14];
5597         env->xregs[23] = env->regs[13];
5598     } else {
5599         env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
5600         env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
5601     }
5602
5603     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5604      * mode, then we can copy from r8-r14.  Otherwise, we copy from the
5605      * FIQ bank for r8-r14.
5606      */
5607     if (mode == ARM_CPU_MODE_FIQ) {
5608         for (i = 24; i < 31; i++) {
5609             env->xregs[i] = env->regs[i - 16];   /* X[24:30] <- R[8:14] */
5610         }
5611     } else {
5612         for (i = 24; i < 29; i++) {
5613             env->xregs[i] = env->fiq_regs[i - 24];
5614         }
5615         env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
5616         env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
5617     }
5618
5619     env->pc = env->regs[15];
5620 }
5621
5622 /* Function used to synchronize QEMU's AArch32 register set with AArch64
5623  * register set.  This is necessary when switching between AArch32 and AArch64
5624  * execution state.
5625  */
5626 void aarch64_sync_64_to_32(CPUARMState *env)
5627 {
5628     int i;
5629     uint32_t mode = env->uncached_cpsr & CPSR_M;
5630
5631     /* We can blanket copy X[0:7] to R[0:7] */
5632     for (i = 0; i < 8; i++) {
5633         env->regs[i] = env->xregs[i];
5634     }
5635
5636     /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
5637      * Otherwise, we copy x8-x12 into the banked user regs.
5638      */
5639     if (mode == ARM_CPU_MODE_FIQ) {
5640         for (i = 8; i < 13; i++) {
5641             env->usr_regs[i - 8] = env->xregs[i];
5642         }
5643     } else {
5644         for (i = 8; i < 13; i++) {
5645             env->regs[i] = env->xregs[i];
5646         }
5647     }
5648
5649     /* Registers r13 & r14 depend on the current mode.
5650      * If we are in a given mode, we copy the corresponding x registers to r13
5651      * and r14.  Otherwise, we copy the x register to the banked r13 and r14
5652      * for the mode.
5653      */
5654     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5655         env->regs[13] = env->xregs[13];
5656         env->regs[14] = env->xregs[14];
5657     } else {
5658         env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
5659
5660         /* HYP is an exception in that it does not have its own banked r14 but
5661          * shares the USR r14
5662          */
5663         if (mode == ARM_CPU_MODE_HYP) {
5664             env->regs[14] = env->xregs[14];
5665         } else {
5666             env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
5667         }
5668     }
5669
5670     if (mode == ARM_CPU_MODE_HYP) {
5671         env->regs[13] = env->xregs[15];
5672     } else {
5673         env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
5674     }
5675
5676     if (mode == ARM_CPU_MODE_IRQ) {
5677         env->regs[14] = env->xregs[16];
5678         env->regs[13] = env->xregs[17];
5679     } else {
5680         env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
5681         env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
5682     }
5683
5684     if (mode == ARM_CPU_MODE_SVC) {
5685         env->regs[14] = env->xregs[18];
5686         env->regs[13] = env->xregs[19];
5687     } else {
5688         env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
5689         env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
5690     }
5691
5692     if (mode == ARM_CPU_MODE_ABT) {
5693         env->regs[14] = env->xregs[20];
5694         env->regs[13] = env->xregs[21];
5695     } else {
5696         env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
5697         env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
5698     }
5699
5700     if (mode == ARM_CPU_MODE_UND) {
5701         env->regs[14] = env->xregs[22];
5702         env->regs[13] = env->xregs[23];
5703     } else {
5704         env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
5705         env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
5706     }
5707
5708     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5709      * mode, then we can copy to r8-r14.  Otherwise, we copy to the
5710      * FIQ bank for r8-r14.
5711      */
5712     if (mode == ARM_CPU_MODE_FIQ) {
5713         for (i = 24; i < 31; i++) {
5714             env->regs[i - 16] = env->xregs[i];   /* X[24:30] -> R[8:14] */
5715         }
5716     } else {
5717         for (i = 24; i < 29; i++) {
5718             env->fiq_regs[i - 24] = env->xregs[i];
5719         }
5720         env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
5721         env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
5722     }
5723
5724     env->regs[15] = env->pc;
5725 }
5726
5727 static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
5728 {
5729     ARMCPU *cpu = ARM_CPU(cs);
5730     CPUARMState *env = &cpu->env;
5731     uint32_t addr;
5732     uint32_t mask;
5733     int new_mode;
5734     uint32_t offset;
5735     uint32_t moe;
5736
5737     /* If this is a debug exception we must update the DBGDSCR.MOE bits */
5738     switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
5739     case EC_BREAKPOINT:
5740     case EC_BREAKPOINT_SAME_EL:
5741         moe = 1;
5742         break;
5743     case EC_WATCHPOINT:
5744     case EC_WATCHPOINT_SAME_EL:
5745         moe = 10;
5746         break;
5747     case EC_AA32_BKPT:
5748         moe = 3;
5749         break;
5750     case EC_VECTORCATCH:
5751         moe = 5;
5752         break;
5753     default:
5754         moe = 0;
5755         break;
5756     }
5757
5758     if (moe) {
5759         env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
5760     }
5761
5762     /* TODO: Vectored interrupt controller.  */
5763     switch (cs->exception_index) {
5764     case EXCP_UDEF:
5765         new_mode = ARM_CPU_MODE_UND;
5766         addr = 0x04;
5767         mask = CPSR_I;
5768         if (env->thumb)
5769             offset = 2;
5770         else
5771             offset = 4;
5772         break;
5773     case EXCP_SWI:
5774         new_mode = ARM_CPU_MODE_SVC;
5775         addr = 0x08;
5776         mask = CPSR_I;
5777         /* The PC already points to the next instruction.  */
5778         offset = 0;
5779         break;
5780     case EXCP_BKPT:
5781         env->exception.fsr = 2;
5782         /* Fall through to prefetch abort.  */
5783     case EXCP_PREFETCH_ABORT:
5784         A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
5785         A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
5786         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
5787                       env->exception.fsr, (uint32_t)env->exception.vaddress);
5788         new_mode = ARM_CPU_MODE_ABT;
5789         addr = 0x0c;
5790         mask = CPSR_A | CPSR_I;
5791         offset = 4;
5792         break;
5793     case EXCP_DATA_ABORT:
5794         A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
5795         A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
5796         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
5797                       env->exception.fsr,
5798                       (uint32_t)env->exception.vaddress);
5799         new_mode = ARM_CPU_MODE_ABT;
5800         addr = 0x10;
5801         mask = CPSR_A | CPSR_I;
5802         offset = 8;
5803         break;
5804     case EXCP_IRQ:
5805         new_mode = ARM_CPU_MODE_IRQ;
5806         addr = 0x18;
5807         /* Disable IRQ and imprecise data aborts.  */
5808         mask = CPSR_A | CPSR_I;
5809         offset = 4;
5810         if (env->cp15.scr_el3 & SCR_IRQ) {
5811             /* IRQ routed to monitor mode */
5812             new_mode = ARM_CPU_MODE_MON;
5813             mask |= CPSR_F;
5814         }
5815         break;
5816     case EXCP_FIQ:
5817         new_mode = ARM_CPU_MODE_FIQ;
5818         addr = 0x1c;
5819         /* Disable FIQ, IRQ and imprecise data aborts.  */
5820         mask = CPSR_A | CPSR_I | CPSR_F;
5821         if (env->cp15.scr_el3 & SCR_FIQ) {
5822             /* FIQ routed to monitor mode */
5823             new_mode = ARM_CPU_MODE_MON;
5824         }
5825         offset = 4;
5826         break;
5827     case EXCP_SMC:
5828         new_mode = ARM_CPU_MODE_MON;
5829         addr = 0x08;
5830         mask = CPSR_A | CPSR_I | CPSR_F;
5831         offset = 0;
5832         break;
5833     default:
5834         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5835         return; /* Never happens.  Keep compiler happy.  */
5836     }
5837
5838     if (new_mode == ARM_CPU_MODE_MON) {
5839         addr += env->cp15.mvbar;
5840     } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
5841         /* High vectors. When enabled, base address cannot be remapped. */
5842         addr += 0xffff0000;
5843     } else {
5844         /* ARM v7 architectures provide a vector base address register to remap
5845          * the interrupt vector table.
5846          * This register is only followed in non-monitor mode, and is banked.
5847          * Note: only bits 31:5 are valid.
5848          */
5849         addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
5850     }
5851
5852     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
5853         env->cp15.scr_el3 &= ~SCR_NS;
5854     }
5855
5856     switch_mode (env, new_mode);
5857     /* For exceptions taken to AArch32 we must clear the SS bit in both
5858      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
5859      */
5860     env->uncached_cpsr &= ~PSTATE_SS;
5861     env->spsr = cpsr_read(env);
5862     /* Clear IT bits.  */
5863     env->condexec_bits = 0;
5864     /* Switch to the new mode, and to the correct instruction set.  */
5865     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
5866     env->daif |= mask;
5867     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
5868      * and we should just guard the thumb mode on V4 */
5869     if (arm_feature(env, ARM_FEATURE_V4T)) {
5870         env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
5871     }
5872     env->regs[14] = env->regs[15] + offset;
5873     env->regs[15] = addr;
5874 }
5875
5876 /* Handle exception entry to a target EL which is using AArch64 */
5877 static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
5878 {
5879     ARMCPU *cpu = ARM_CPU(cs);
5880     CPUARMState *env = &cpu->env;
5881     unsigned int new_el = env->exception.target_el;
5882     target_ulong addr = env->cp15.vbar_el[new_el];
5883     unsigned int new_mode = aarch64_pstate_mode(new_el, true);
5884
5885     if (arm_current_el(env) < new_el) {
5886         /* Entry vector offset depends on whether the implemented EL
5887          * immediately lower than the target level is using AArch32 or AArch64
5888          */
5889         bool is_aa64;
5890
5891         switch (new_el) {
5892         case 3:
5893             is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
5894             break;
5895         case 2:
5896             is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0;
5897             break;
5898         case 1:
5899             is_aa64 = is_a64(env);
5900             break;
5901         default:
5902             g_assert_not_reached();
5903         }
5904
5905         if (is_aa64) {
5906             addr += 0x400;
5907         } else {
5908             addr += 0x600;
5909         }
5910     } else if (pstate_read(env) & PSTATE_SP) {
5911         addr += 0x200;
5912     }
5913
5914     switch (cs->exception_index) {
5915     case EXCP_PREFETCH_ABORT:
5916     case EXCP_DATA_ABORT:
5917         env->cp15.far_el[new_el] = env->exception.vaddress;
5918         qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
5919                       env->cp15.far_el[new_el]);
5920         /* fall through */
5921     case EXCP_BKPT:
5922     case EXCP_UDEF:
5923     case EXCP_SWI:
5924     case EXCP_HVC:
5925     case EXCP_HYP_TRAP:
5926     case EXCP_SMC:
5927         env->cp15.esr_el[new_el] = env->exception.syndrome;
5928         break;
5929     case EXCP_IRQ:
5930     case EXCP_VIRQ:
5931         addr += 0x80;
5932         break;
5933     case EXCP_FIQ:
5934     case EXCP_VFIQ:
5935         addr += 0x100;
5936         break;
5937     case EXCP_SEMIHOST:
5938         qemu_log_mask(CPU_LOG_INT,
5939                       "...handling as semihosting call 0x%" PRIx64 "\n",
5940                       env->xregs[0]);
5941         env->xregs[0] = do_arm_semihosting(env);
5942         return;
5943     default:
5944         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5945     }
5946
5947     if (is_a64(env)) {
5948         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env);
5949         aarch64_save_sp(env, arm_current_el(env));
5950         env->elr_el[new_el] = env->pc;
5951     } else {
5952         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
5953         if (!env->thumb) {
5954             env->cp15.esr_el[new_el] |= 1 << 25;
5955         }
5956         env->elr_el[new_el] = env->regs[15];
5957
5958         aarch64_sync_32_to_64(env);
5959
5960         env->condexec_bits = 0;
5961     }
5962     qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
5963                   env->elr_el[new_el]);
5964
5965     pstate_write(env, PSTATE_DAIF | new_mode);
5966     env->aarch64 = 1;
5967     aarch64_restore_sp(env, new_el);
5968
5969     env->pc = addr;
5970
5971     qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
5972                   new_el, env->pc, pstate_read(env));
5973 }
5974
5975 static inline bool check_for_semihosting(CPUState *cs)
5976 {
5977     /* Check whether this exception is a semihosting call; if so
5978      * then handle it and return true; otherwise return false.
5979      */
5980     ARMCPU *cpu = ARM_CPU(cs);
5981     CPUARMState *env = &cpu->env;
5982
5983     if (is_a64(env)) {
5984         if (cs->exception_index == EXCP_SEMIHOST) {
5985             /* This is always the 64-bit semihosting exception.
5986              * The "is this usermode" and "is semihosting enabled"
5987              * checks have been done at translate time.
5988              */
5989             qemu_log_mask(CPU_LOG_INT,
5990                           "...handling as semihosting call 0x%" PRIx64 "\n",
5991                           env->xregs[0]);
5992             env->xregs[0] = do_arm_semihosting(env);
5993             return true;
5994         }
5995         return false;
5996     } else {
5997         uint32_t imm;
5998
5999         /* Only intercept calls from privileged modes, to provide some
6000          * semblance of security.
6001          */
6002         if (!semihosting_enabled() ||
6003             ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)) {
6004             return false;
6005         }
6006
6007         switch (cs->exception_index) {
6008         case EXCP_SWI:
6009             /* Check for semihosting interrupt.  */
6010             if (env->thumb) {
6011                 imm = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
6012                     & 0xff;
6013                 if (imm == 0xab) {
6014                     break;
6015                 }
6016             } else {
6017                 imm = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
6018                     & 0xffffff;
6019                 if (imm == 0x123456) {
6020                     break;
6021                 }
6022             }
6023             return false;
6024         case EXCP_BKPT:
6025             /* See if this is a semihosting syscall.  */
6026             if (env->thumb) {
6027                 imm = arm_lduw_code(env, env->regs[15], env->bswap_code)
6028                     & 0xff;
6029                 if (imm == 0xab) {
6030                     env->regs[15] += 2;
6031                     break;
6032                 }
6033             }
6034             return false;
6035         default:
6036             return false;
6037         }
6038
6039         qemu_log_mask(CPU_LOG_INT,
6040                       "...handling as semihosting call 0x%x\n",
6041                       env->regs[0]);
6042         env->regs[0] = do_arm_semihosting(env);
6043         return true;
6044     }
6045 }
6046
6047 /* Handle a CPU exception for A and R profile CPUs.
6048  * Do any appropriate logging, handle PSCI calls, and then hand off
6049  * to the AArch64-entry or AArch32-entry function depending on the
6050  * target exception level's register width.
6051  */
6052 void arm_cpu_do_interrupt(CPUState *cs)
6053 {
6054     ARMCPU *cpu = ARM_CPU(cs);
6055     CPUARMState *env = &cpu->env;
6056     unsigned int new_el = env->exception.target_el;
6057
6058     assert(!IS_M(env));
6059
6060     arm_log_exception(cs->exception_index);
6061     qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
6062                   new_el);
6063     if (qemu_loglevel_mask(CPU_LOG_INT)
6064         && !excp_is_internal(cs->exception_index)) {
6065         qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n",
6066                       env->exception.syndrome >> ARM_EL_EC_SHIFT,
6067                       env->exception.syndrome);
6068     }
6069
6070     if (arm_is_psci_call(cpu, cs->exception_index)) {
6071         arm_handle_psci_call(cpu);
6072         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
6073         return;
6074     }
6075
6076     /* Semihosting semantics depend on the register width of the
6077      * code that caused the exception, not the target exception level,
6078      * so must be handled here.
6079      */
6080     if (check_for_semihosting(cs)) {
6081         return;
6082     }
6083
6084     assert(!excp_is_internal(cs->exception_index));
6085     if (arm_el_is_aa64(env, new_el)) {
6086         arm_cpu_do_interrupt_aarch64(cs);
6087     } else {
6088         arm_cpu_do_interrupt_aarch32(cs);
6089     }
6090
6091     if (!kvm_enabled()) {
6092         cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
6093     }
6094 }
6095
6096 /* Return the exception level which controls this address translation regime */
6097 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
6098 {
6099     switch (mmu_idx) {
6100     case ARMMMUIdx_S2NS:
6101     case ARMMMUIdx_S1E2:
6102         return 2;
6103     case ARMMMUIdx_S1E3:
6104         return 3;
6105     case ARMMMUIdx_S1SE0:
6106         return arm_el_is_aa64(env, 3) ? 1 : 3;
6107     case ARMMMUIdx_S1SE1:
6108     case ARMMMUIdx_S1NSE0:
6109     case ARMMMUIdx_S1NSE1:
6110         return 1;
6111     default:
6112         g_assert_not_reached();
6113     }
6114 }
6115
6116 /* Return true if this address translation regime is secure */
6117 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
6118 {
6119     switch (mmu_idx) {
6120     case ARMMMUIdx_S12NSE0:
6121     case ARMMMUIdx_S12NSE1:
6122     case ARMMMUIdx_S1NSE0:
6123     case ARMMMUIdx_S1NSE1:
6124     case ARMMMUIdx_S1E2:
6125     case ARMMMUIdx_S2NS:
6126         return false;
6127     case ARMMMUIdx_S1E3:
6128     case ARMMMUIdx_S1SE0:
6129     case ARMMMUIdx_S1SE1:
6130         return true;
6131     default:
6132         g_assert_not_reached();
6133     }
6134 }
6135
6136 /* Return the SCTLR value which controls this address translation regime */
6137 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
6138 {
6139     return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
6140 }
6141
6142 /* Return true if the specified stage of address translation is disabled */
6143 static inline bool regime_translation_disabled(CPUARMState *env,
6144                                                ARMMMUIdx mmu_idx)
6145 {
6146     if (mmu_idx == ARMMMUIdx_S2NS) {
6147         return (env->cp15.hcr_el2 & HCR_VM) == 0;
6148     }
6149     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
6150 }
6151
6152 /* Return the TCR controlling this translation regime */
6153 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
6154 {
6155     if (mmu_idx == ARMMMUIdx_S2NS) {
6156         return &env->cp15.vtcr_el2;
6157     }
6158     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
6159 }
6160
6161 /* Return the TTBR associated with this translation regime */
6162 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
6163                                    int ttbrn)
6164 {
6165     if (mmu_idx == ARMMMUIdx_S2NS) {
6166         return env->cp15.vttbr_el2;
6167     }
6168     if (ttbrn == 0) {
6169         return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
6170     } else {
6171         return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
6172     }
6173 }
6174
6175 /* Return true if the translation regime is using LPAE format page tables */
6176 static inline bool regime_using_lpae_format(CPUARMState *env,
6177                                             ARMMMUIdx mmu_idx)
6178 {
6179     int el = regime_el(env, mmu_idx);
6180     if (el == 2 || arm_el_is_aa64(env, el)) {
6181         return true;
6182     }
6183     if (arm_feature(env, ARM_FEATURE_LPAE)
6184         && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
6185         return true;
6186     }
6187     return false;
6188 }
6189
6190 /* Returns true if the stage 1 translation regime is using LPAE format page
6191  * tables. Used when raising alignment exceptions, whose FSR changes depending
6192  * on whether the long or short descriptor format is in use. */
6193 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
6194 {
6195     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
6196         mmu_idx += ARMMMUIdx_S1NSE0;
6197     }
6198
6199     return regime_using_lpae_format(env, mmu_idx);
6200 }
6201
6202 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
6203 {
6204     switch (mmu_idx) {
6205     case ARMMMUIdx_S1SE0:
6206     case ARMMMUIdx_S1NSE0:
6207         return true;
6208     default:
6209         return false;
6210     case ARMMMUIdx_S12NSE0:
6211     case ARMMMUIdx_S12NSE1:
6212         g_assert_not_reached();
6213     }
6214 }
6215
6216 /* Translate section/page access permissions to page
6217  * R/W protection flags
6218  *
6219  * @env:         CPUARMState
6220  * @mmu_idx:     MMU index indicating required translation regime
6221  * @ap:          The 3-bit access permissions (AP[2:0])
6222  * @domain_prot: The 2-bit domain access permissions
6223  */
6224 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
6225                                 int ap, int domain_prot)
6226 {
6227     bool is_user = regime_is_user(env, mmu_idx);
6228
6229     if (domain_prot == 3) {
6230         return PAGE_READ | PAGE_WRITE;
6231     }
6232
6233     switch (ap) {
6234     case 0:
6235         if (arm_feature(env, ARM_FEATURE_V7)) {
6236             return 0;
6237         }
6238         switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
6239         case SCTLR_S:
6240             return is_user ? 0 : PAGE_READ;
6241         case SCTLR_R:
6242             return PAGE_READ;
6243         default:
6244             return 0;
6245         }
6246     case 1:
6247         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6248     case 2:
6249         if (is_user) {
6250             return PAGE_READ;
6251         } else {
6252             return PAGE_READ | PAGE_WRITE;
6253         }
6254     case 3:
6255         return PAGE_READ | PAGE_WRITE;
6256     case 4: /* Reserved.  */
6257         return 0;
6258     case 5:
6259         return is_user ? 0 : PAGE_READ;
6260     case 6:
6261         return PAGE_READ;
6262     case 7:
6263         if (!arm_feature(env, ARM_FEATURE_V6K)) {
6264             return 0;
6265         }
6266         return PAGE_READ;
6267     default:
6268         g_assert_not_reached();
6269     }
6270 }
6271
6272 /* Translate section/page access permissions to page
6273  * R/W protection flags.
6274  *
6275  * @ap:      The 2-bit simple AP (AP[2:1])
6276  * @is_user: TRUE if accessing from PL0
6277  */
6278 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
6279 {
6280     switch (ap) {
6281     case 0:
6282         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6283     case 1:
6284         return PAGE_READ | PAGE_WRITE;
6285     case 2:
6286         return is_user ? 0 : PAGE_READ;
6287     case 3:
6288         return PAGE_READ;
6289     default:
6290         g_assert_not_reached();
6291     }
6292 }
6293
6294 static inline int
6295 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
6296 {
6297     return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
6298 }
6299
6300 /* Translate S2 section/page access permissions to protection flags
6301  *
6302  * @env:     CPUARMState
6303  * @s2ap:    The 2-bit stage2 access permissions (S2AP)
6304  * @xn:      XN (execute-never) bit
6305  */
6306 static int get_S2prot(CPUARMState *env, int s2ap, int xn)
6307 {
6308     int prot = 0;
6309
6310     if (s2ap & 1) {
6311         prot |= PAGE_READ;
6312     }
6313     if (s2ap & 2) {
6314         prot |= PAGE_WRITE;
6315     }
6316     if (!xn) {
6317         prot |= PAGE_EXEC;
6318     }
6319     return prot;
6320 }
6321
6322 /* Translate section/page access permissions to protection flags
6323  *
6324  * @env:     CPUARMState
6325  * @mmu_idx: MMU index indicating required translation regime
6326  * @is_aa64: TRUE if AArch64
6327  * @ap:      The 2-bit simple AP (AP[2:1])
6328  * @ns:      NS (non-secure) bit
6329  * @xn:      XN (execute-never) bit
6330  * @pxn:     PXN (privileged execute-never) bit
6331  */
6332 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
6333                       int ap, int ns, int xn, int pxn)
6334 {
6335     bool is_user = regime_is_user(env, mmu_idx);
6336     int prot_rw, user_rw;
6337     bool have_wxn;
6338     int wxn = 0;
6339
6340     assert(mmu_idx != ARMMMUIdx_S2NS);
6341
6342     user_rw = simple_ap_to_rw_prot_is_user(ap, true);
6343     if (is_user) {
6344         prot_rw = user_rw;
6345     } else {
6346         prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
6347     }
6348
6349     if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
6350         return prot_rw;
6351     }
6352
6353     /* TODO have_wxn should be replaced with
6354      *   ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
6355      * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
6356      * compatible processors have EL2, which is required for [U]WXN.
6357      */
6358     have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
6359
6360     if (have_wxn) {
6361         wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
6362     }
6363
6364     if (is_aa64) {
6365         switch (regime_el(env, mmu_idx)) {
6366         case 1:
6367             if (!is_user) {
6368                 xn = pxn || (user_rw & PAGE_WRITE);
6369             }
6370             break;
6371         case 2:
6372         case 3:
6373             break;
6374         }
6375     } else if (arm_feature(env, ARM_FEATURE_V7)) {
6376         switch (regime_el(env, mmu_idx)) {
6377         case 1:
6378         case 3:
6379             if (is_user) {
6380                 xn = xn || !(user_rw & PAGE_READ);
6381             } else {
6382                 int uwxn = 0;
6383                 if (have_wxn) {
6384                     uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
6385                 }
6386                 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
6387                      (uwxn && (user_rw & PAGE_WRITE));
6388             }
6389             break;
6390         case 2:
6391             break;
6392         }
6393     } else {
6394         xn = wxn = 0;
6395     }
6396
6397     if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
6398         return prot_rw;
6399     }
6400     return prot_rw | PAGE_EXEC;
6401 }
6402
6403 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
6404                                      uint32_t *table, uint32_t address)
6405 {
6406     /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
6407     TCR *tcr = regime_tcr(env, mmu_idx);
6408
6409     if (address & tcr->mask) {
6410         if (tcr->raw_tcr & TTBCR_PD1) {
6411             /* Translation table walk disabled for TTBR1 */
6412             return false;
6413         }
6414         *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
6415     } else {
6416         if (tcr->raw_tcr & TTBCR_PD0) {
6417             /* Translation table walk disabled for TTBR0 */
6418             return false;
6419         }
6420         *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
6421     }
6422     *table |= (address >> 18) & 0x3ffc;
6423     return true;
6424 }
6425
6426 /* Translate a S1 pagetable walk through S2 if needed.  */
6427 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
6428                                hwaddr addr, MemTxAttrs txattrs,
6429                                uint32_t *fsr,
6430                                ARMMMUFaultInfo *fi)
6431 {
6432     if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) &&
6433         !regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
6434         target_ulong s2size;
6435         hwaddr s2pa;
6436         int s2prot;
6437         int ret;
6438
6439         ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
6440                                  &txattrs, &s2prot, &s2size, fsr, fi);
6441         if (ret) {
6442             fi->s2addr = addr;
6443             fi->stage2 = true;
6444             fi->s1ptw = true;
6445             return ~0;
6446         }
6447         addr = s2pa;
6448     }
6449     return addr;
6450 }
6451
6452 /* All loads done in the course of a page table walk go through here.
6453  * TODO: rather than ignoring errors from physical memory reads (which
6454  * are external aborts in ARM terminology) we should propagate this
6455  * error out so that we can turn it into a Data Abort if this walk
6456  * was being done for a CPU load/store or an address translation instruction
6457  * (but not if it was for a debug access).
6458  */
6459 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6460                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6461                             ARMMMUFaultInfo *fi)
6462 {
6463     ARMCPU *cpu = ARM_CPU(cs);
6464     CPUARMState *env = &cpu->env;
6465     MemTxAttrs attrs = {};
6466     AddressSpace *as;
6467
6468     attrs.secure = is_secure;
6469     as = arm_addressspace(cs, attrs);
6470     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6471     if (fi->s1ptw) {
6472         return 0;
6473     }
6474     return address_space_ldl(as, addr, attrs, NULL);
6475 }
6476
6477 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6478                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6479                             ARMMMUFaultInfo *fi)
6480 {
6481     ARMCPU *cpu = ARM_CPU(cs);
6482     CPUARMState *env = &cpu->env;
6483     MemTxAttrs attrs = {};
6484     AddressSpace *as;
6485
6486     attrs.secure = is_secure;
6487     as = arm_addressspace(cs, attrs);
6488     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6489     if (fi->s1ptw) {
6490         return 0;
6491     }
6492     return address_space_ldq(as, addr, attrs, NULL);
6493 }
6494
6495 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
6496                              int access_type, ARMMMUIdx mmu_idx,
6497                              hwaddr *phys_ptr, int *prot,
6498                              target_ulong *page_size, uint32_t *fsr,
6499                              ARMMMUFaultInfo *fi)
6500 {
6501     CPUState *cs = CPU(arm_env_get_cpu(env));
6502     int code;
6503     uint32_t table;
6504     uint32_t desc;
6505     int type;
6506     int ap;
6507     int domain = 0;
6508     int domain_prot;
6509     hwaddr phys_addr;
6510     uint32_t dacr;
6511
6512     /* Pagetable walk.  */
6513     /* Lookup l1 descriptor.  */
6514     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6515         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6516         code = 5;
6517         goto do_fault;
6518     }
6519     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6520                        mmu_idx, fsr, fi);
6521     type = (desc & 3);
6522     domain = (desc >> 5) & 0x0f;
6523     if (regime_el(env, mmu_idx) == 1) {
6524         dacr = env->cp15.dacr_ns;
6525     } else {
6526         dacr = env->cp15.dacr_s;
6527     }
6528     domain_prot = (dacr >> (domain * 2)) & 3;
6529     if (type == 0) {
6530         /* Section translation fault.  */
6531         code = 5;
6532         goto do_fault;
6533     }
6534     if (domain_prot == 0 || domain_prot == 2) {
6535         if (type == 2)
6536             code = 9; /* Section domain fault.  */
6537         else
6538             code = 11; /* Page domain fault.  */
6539         goto do_fault;
6540     }
6541     if (type == 2) {
6542         /* 1Mb section.  */
6543         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6544         ap = (desc >> 10) & 3;
6545         code = 13;
6546         *page_size = 1024 * 1024;
6547     } else {
6548         /* Lookup l2 entry.  */
6549         if (type == 1) {
6550             /* Coarse pagetable.  */
6551             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6552         } else {
6553             /* Fine pagetable.  */
6554             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
6555         }
6556         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6557                            mmu_idx, fsr, fi);
6558         switch (desc & 3) {
6559         case 0: /* Page translation fault.  */
6560             code = 7;
6561             goto do_fault;
6562         case 1: /* 64k page.  */
6563             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6564             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
6565             *page_size = 0x10000;
6566             break;
6567         case 2: /* 4k page.  */
6568             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6569             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
6570             *page_size = 0x1000;
6571             break;
6572         case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
6573             if (type == 1) {
6574                 /* ARMv6/XScale extended small page format */
6575                 if (arm_feature(env, ARM_FEATURE_XSCALE)
6576                     || arm_feature(env, ARM_FEATURE_V6)) {
6577                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6578                     *page_size = 0x1000;
6579                 } else {
6580                     /* UNPREDICTABLE in ARMv5; we choose to take a
6581                      * page translation fault.
6582                      */
6583                     code = 7;
6584                     goto do_fault;
6585                 }
6586             } else {
6587                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
6588                 *page_size = 0x400;
6589             }
6590             ap = (desc >> 4) & 3;
6591             break;
6592         default:
6593             /* Never happens, but compiler isn't smart enough to tell.  */
6594             abort();
6595         }
6596         code = 15;
6597     }
6598     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6599     *prot |= *prot ? PAGE_EXEC : 0;
6600     if (!(*prot & (1 << access_type))) {
6601         /* Access permission fault.  */
6602         goto do_fault;
6603     }
6604     *phys_ptr = phys_addr;
6605     return false;
6606 do_fault:
6607     *fsr = code | (domain << 4);
6608     return true;
6609 }
6610
6611 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
6612                              int access_type, ARMMMUIdx mmu_idx,
6613                              hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
6614                              target_ulong *page_size, uint32_t *fsr,
6615                              ARMMMUFaultInfo *fi)
6616 {
6617     CPUState *cs = CPU(arm_env_get_cpu(env));
6618     int code;
6619     uint32_t table;
6620     uint32_t desc;
6621     uint32_t xn;
6622     uint32_t pxn = 0;
6623     int type;
6624     int ap;
6625     int domain = 0;
6626     int domain_prot;
6627     hwaddr phys_addr;
6628     uint32_t dacr;
6629     bool ns;
6630
6631     /* Pagetable walk.  */
6632     /* Lookup l1 descriptor.  */
6633     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6634         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6635         code = 5;
6636         goto do_fault;
6637     }
6638     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6639                        mmu_idx, fsr, fi);
6640     type = (desc & 3);
6641     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
6642         /* Section translation fault, or attempt to use the encoding
6643          * which is Reserved on implementations without PXN.
6644          */
6645         code = 5;
6646         goto do_fault;
6647     }
6648     if ((type == 1) || !(desc & (1 << 18))) {
6649         /* Page or Section.  */
6650         domain = (desc >> 5) & 0x0f;
6651     }
6652     if (regime_el(env, mmu_idx) == 1) {
6653         dacr = env->cp15.dacr_ns;
6654     } else {
6655         dacr = env->cp15.dacr_s;
6656     }
6657     domain_prot = (dacr >> (domain * 2)) & 3;
6658     if (domain_prot == 0 || domain_prot == 2) {
6659         if (type != 1) {
6660             code = 9; /* Section domain fault.  */
6661         } else {
6662             code = 11; /* Page domain fault.  */
6663         }
6664         goto do_fault;
6665     }
6666     if (type != 1) {
6667         if (desc & (1 << 18)) {
6668             /* Supersection.  */
6669             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
6670             phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
6671             phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
6672             *page_size = 0x1000000;
6673         } else {
6674             /* Section.  */
6675             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6676             *page_size = 0x100000;
6677         }
6678         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
6679         xn = desc & (1 << 4);
6680         pxn = desc & 1;
6681         code = 13;
6682         ns = extract32(desc, 19, 1);
6683     } else {
6684         if (arm_feature(env, ARM_FEATURE_PXN)) {
6685             pxn = (desc >> 2) & 1;
6686         }
6687         ns = extract32(desc, 3, 1);
6688         /* Lookup l2 entry.  */
6689         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6690         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6691                            mmu_idx, fsr, fi);
6692         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
6693         switch (desc & 3) {
6694         case 0: /* Page translation fault.  */
6695             code = 7;
6696             goto do_fault;
6697         case 1: /* 64k page.  */
6698             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6699             xn = desc & (1 << 15);
6700             *page_size = 0x10000;
6701             break;
6702         case 2: case 3: /* 4k page.  */
6703             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6704             xn = desc & 1;
6705             *page_size = 0x1000;
6706             break;
6707         default:
6708             /* Never happens, but compiler isn't smart enough to tell.  */
6709             abort();
6710         }
6711         code = 15;
6712     }
6713     if (domain_prot == 3) {
6714         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
6715     } else {
6716         if (pxn && !regime_is_user(env, mmu_idx)) {
6717             xn = 1;
6718         }
6719         if (xn && access_type == 2)
6720             goto do_fault;
6721
6722         if (arm_feature(env, ARM_FEATURE_V6K) &&
6723                 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
6724             /* The simplified model uses AP[0] as an access control bit.  */
6725             if ((ap & 1) == 0) {
6726                 /* Access flag fault.  */
6727                 code = (code == 15) ? 6 : 3;
6728                 goto do_fault;
6729             }
6730             *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
6731         } else {
6732             *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6733         }
6734         if (*prot && !xn) {
6735             *prot |= PAGE_EXEC;
6736         }
6737         if (!(*prot & (1 << access_type))) {
6738             /* Access permission fault.  */
6739             goto do_fault;
6740         }
6741     }
6742     if (ns) {
6743         /* The NS bit will (as required by the architecture) have no effect if
6744          * the CPU doesn't support TZ or this is a non-secure translation
6745          * regime, because the attribute will already be non-secure.
6746          */
6747         attrs->secure = false;
6748     }
6749     *phys_ptr = phys_addr;
6750     return false;
6751 do_fault:
6752     *fsr = code | (domain << 4);
6753     return true;
6754 }
6755
6756 /* Fault type for long-descriptor MMU fault reporting; this corresponds
6757  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
6758  */
6759 typedef enum {
6760     translation_fault = 1,
6761     access_fault = 2,
6762     permission_fault = 3,
6763 } MMUFaultType;
6764
6765 /*
6766  * check_s2_startlevel
6767  * @cpu:        ARMCPU
6768  * @is_aa64:    True if the translation regime is in AArch64 state
6769  * @startlevel: Suggested starting level
6770  * @inputsize:  Bitsize of IPAs
6771  * @stride:     Page-table stride (See the ARM ARM)
6772  *
6773  * Returns true if the suggested starting level is OK and false otherwise.
6774  */
6775 static bool check_s2_startlevel(ARMCPU *cpu, bool is_aa64, int level,
6776                                 int inputsize, int stride)
6777 {
6778     /* Negative levels are never allowed.  */
6779     if (level < 0) {
6780         return false;
6781     }
6782
6783     if (is_aa64) {
6784         unsigned int pamax = arm_pamax(cpu);
6785
6786         switch (stride) {
6787         case 13: /* 64KB Pages.  */
6788             if (level == 0 || (level == 1 && pamax <= 42)) {
6789                 return false;
6790             }
6791             break;
6792         case 11: /* 16KB Pages.  */
6793             if (level == 0 || (level == 1 && pamax <= 40)) {
6794                 return false;
6795             }
6796             break;
6797         case 9: /* 4KB Pages.  */
6798             if (level == 0 && pamax <= 42) {
6799                 return false;
6800             }
6801             break;
6802         default:
6803             g_assert_not_reached();
6804         }
6805     } else {
6806         const int grainsize = stride + 3;
6807         int startsizecheck;
6808
6809         /* AArch32 only supports 4KB pages. Assert on that.  */
6810         assert(stride == 9);
6811
6812         if (level == 0) {
6813             return false;
6814         }
6815
6816         startsizecheck = inputsize - ((3 - level) * stride + grainsize);
6817         if (startsizecheck < 1 || startsizecheck > stride + 4) {
6818             return false;
6819         }
6820     }
6821     return true;
6822 }
6823
6824 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
6825                                int access_type, ARMMMUIdx mmu_idx,
6826                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
6827                                target_ulong *page_size_ptr, uint32_t *fsr,
6828                                ARMMMUFaultInfo *fi)
6829 {
6830     ARMCPU *cpu = arm_env_get_cpu(env);
6831     CPUState *cs = CPU(cpu);
6832     /* Read an LPAE long-descriptor translation table. */
6833     MMUFaultType fault_type = translation_fault;
6834     uint32_t level = 1;
6835     uint32_t epd = 0;
6836     int32_t t0sz, t1sz;
6837     uint32_t tg;
6838     uint64_t ttbr;
6839     int ttbr_select;
6840     hwaddr descaddr, descmask;
6841     uint32_t tableattrs;
6842     target_ulong page_size;
6843     uint32_t attrs;
6844     int32_t stride = 9;
6845     int32_t va_size = 32;
6846     int inputsize;
6847     int32_t tbi = 0;
6848     TCR *tcr = regime_tcr(env, mmu_idx);
6849     int ap, ns, xn, pxn;
6850     uint32_t el = regime_el(env, mmu_idx);
6851     bool ttbr1_valid = true;
6852     uint64_t descaddrmask;
6853
6854     /* TODO:
6855      * This code does not handle the different format TCR for VTCR_EL2.
6856      * This code also does not support shareability levels.
6857      * Attribute and permission bit handling should also be checked when adding
6858      * support for those page table walks.
6859      */
6860     if (arm_el_is_aa64(env, el)) {
6861         va_size = 64;
6862         if (el > 1) {
6863             if (mmu_idx != ARMMMUIdx_S2NS) {
6864                 tbi = extract64(tcr->raw_tcr, 20, 1);
6865             }
6866         } else {
6867             if (extract64(address, 55, 1)) {
6868                 tbi = extract64(tcr->raw_tcr, 38, 1);
6869             } else {
6870                 tbi = extract64(tcr->raw_tcr, 37, 1);
6871             }
6872         }
6873         tbi *= 8;
6874
6875         /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
6876          * invalid.
6877          */
6878         if (el > 1) {
6879             ttbr1_valid = false;
6880         }
6881     } else {
6882         /* There is no TTBR1 for EL2 */
6883         if (el == 2) {
6884             ttbr1_valid = false;
6885         }
6886     }
6887
6888     /* Determine whether this address is in the region controlled by
6889      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
6890      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
6891      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
6892      */
6893     if (va_size == 64) {
6894         /* AArch64 translation.  */
6895         t0sz = extract32(tcr->raw_tcr, 0, 6);
6896         t0sz = MIN(t0sz, 39);
6897         t0sz = MAX(t0sz, 16);
6898     } else if (mmu_idx != ARMMMUIdx_S2NS) {
6899         /* AArch32 stage 1 translation.  */
6900         t0sz = extract32(tcr->raw_tcr, 0, 3);
6901     } else {
6902         /* AArch32 stage 2 translation.  */
6903         bool sext = extract32(tcr->raw_tcr, 4, 1);
6904         bool sign = extract32(tcr->raw_tcr, 3, 1);
6905         t0sz = sextract32(tcr->raw_tcr, 0, 4);
6906
6907         /* If the sign-extend bit is not the same as t0sz[3], the result
6908          * is unpredictable. Flag this as a guest error.  */
6909         if (sign != sext) {
6910             qemu_log_mask(LOG_GUEST_ERROR,
6911                           "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n");
6912         }
6913     }
6914     t1sz = extract32(tcr->raw_tcr, 16, 6);
6915     if (va_size == 64) {
6916         t1sz = MIN(t1sz, 39);
6917         t1sz = MAX(t1sz, 16);
6918     }
6919     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
6920         /* there is a ttbr0 region and we are in it (high bits all zero) */
6921         ttbr_select = 0;
6922     } else if (ttbr1_valid && t1sz &&
6923                !extract64(~address, va_size - t1sz, t1sz - tbi)) {
6924         /* there is a ttbr1 region and we are in it (high bits all one) */
6925         ttbr_select = 1;
6926     } else if (!t0sz) {
6927         /* ttbr0 region is "everything not in the ttbr1 region" */
6928         ttbr_select = 0;
6929     } else if (!t1sz && ttbr1_valid) {
6930         /* ttbr1 region is "everything not in the ttbr0 region" */
6931         ttbr_select = 1;
6932     } else {
6933         /* in the gap between the two regions, this is a Translation fault */
6934         fault_type = translation_fault;
6935         goto do_fault;
6936     }
6937
6938     /* Note that QEMU ignores shareability and cacheability attributes,
6939      * so we don't need to do anything with the SH, ORGN, IRGN fields
6940      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
6941      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
6942      * implement any ASID-like capability so we can ignore it (instead
6943      * we will always flush the TLB any time the ASID is changed).
6944      */
6945     if (ttbr_select == 0) {
6946         ttbr = regime_ttbr(env, mmu_idx, 0);
6947         if (el < 2) {
6948             epd = extract32(tcr->raw_tcr, 7, 1);
6949         }
6950         inputsize = va_size - t0sz;
6951
6952         tg = extract32(tcr->raw_tcr, 14, 2);
6953         if (tg == 1) { /* 64KB pages */
6954             stride = 13;
6955         }
6956         if (tg == 2) { /* 16KB pages */
6957             stride = 11;
6958         }
6959     } else {
6960         /* We should only be here if TTBR1 is valid */
6961         assert(ttbr1_valid);
6962
6963         ttbr = regime_ttbr(env, mmu_idx, 1);
6964         epd = extract32(tcr->raw_tcr, 23, 1);
6965         inputsize = va_size - t1sz;
6966
6967         tg = extract32(tcr->raw_tcr, 30, 2);
6968         if (tg == 3)  { /* 64KB pages */
6969             stride = 13;
6970         }
6971         if (tg == 1) { /* 16KB pages */
6972             stride = 11;
6973         }
6974     }
6975
6976     /* Here we should have set up all the parameters for the translation:
6977      * va_size, inputsize, ttbr, epd, stride, tbi
6978      */
6979
6980     if (epd) {
6981         /* Translation table walk disabled => Translation fault on TLB miss
6982          * Note: This is always 0 on 64-bit EL2 and EL3.
6983          */
6984         goto do_fault;
6985     }
6986
6987     if (mmu_idx != ARMMMUIdx_S2NS) {
6988         /* The starting level depends on the virtual address size (which can
6989          * be up to 48 bits) and the translation granule size. It indicates
6990          * the number of strides (stride bits at a time) needed to
6991          * consume the bits of the input address. In the pseudocode this is:
6992          *  level = 4 - RoundUp((inputsize - grainsize) / stride)
6993          * where their 'inputsize' is our 'inputsize', 'grainsize' is
6994          * our 'stride + 3' and 'stride' is our 'stride'.
6995          * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
6996          * = 4 - (inputsize - stride - 3 + stride - 1) / stride
6997          * = 4 - (inputsize - 4) / stride;
6998          */
6999         level = 4 - (inputsize - 4) / stride;
7000     } else {
7001         /* For stage 2 translations the starting level is specified by the
7002          * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
7003          */
7004         int startlevel = extract32(tcr->raw_tcr, 6, 2);
7005         bool ok;
7006
7007         if (va_size == 32 || stride == 9) {
7008             /* AArch32 or 4KB pages */
7009             level = 2 - startlevel;
7010         } else {
7011             /* 16KB or 64KB pages */
7012             level = 3 - startlevel;
7013         }
7014
7015         /* Check that the starting level is valid. */
7016         ok = check_s2_startlevel(cpu, va_size == 64, level,
7017                                  inputsize, stride);
7018         if (!ok) {
7019             /* AArch64 reports these as level 0 faults.
7020              * AArch32 reports these as level 1 faults.
7021              */
7022             level = va_size == 64 ? 0 : 1;
7023             fault_type = translation_fault;
7024             goto do_fault;
7025         }
7026     }
7027
7028     /* Clear the vaddr bits which aren't part of the within-region address,
7029      * so that we don't have to special case things when calculating the
7030      * first descriptor address.
7031      */
7032     if (va_size != inputsize) {
7033         address &= (1ULL << inputsize) - 1;
7034     }
7035
7036     descmask = (1ULL << (stride + 3)) - 1;
7037
7038     /* Now we can extract the actual base address from the TTBR */
7039     descaddr = extract64(ttbr, 0, 48);
7040     descaddr &= ~((1ULL << (inputsize - (stride * (4 - level)))) - 1);
7041
7042     /* The address field in the descriptor goes up to bit 39 for ARMv7
7043      * but up to bit 47 for ARMv8.
7044      */
7045     if (arm_feature(env, ARM_FEATURE_V8)) {
7046         descaddrmask = 0xfffffffff000ULL;
7047     } else {
7048         descaddrmask = 0xfffffff000ULL;
7049     }
7050
7051     /* Secure accesses start with the page table in secure memory and
7052      * can be downgraded to non-secure at any step. Non-secure accesses
7053      * remain non-secure. We implement this by just ORing in the NSTable/NS
7054      * bits at each step.
7055      */
7056     tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
7057     for (;;) {
7058         uint64_t descriptor;
7059         bool nstable;
7060
7061         descaddr |= (address >> (stride * (4 - level))) & descmask;
7062         descaddr &= ~7ULL;
7063         nstable = extract32(tableattrs, 4, 1);
7064         descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi);
7065         if (fi->s1ptw) {
7066             goto do_fault;
7067         }
7068
7069         if (!(descriptor & 1) ||
7070             (!(descriptor & 2) && (level == 3))) {
7071             /* Invalid, or the Reserved level 3 encoding */
7072             goto do_fault;
7073         }
7074         descaddr = descriptor & descaddrmask;
7075
7076         if ((descriptor & 2) && (level < 3)) {
7077             /* Table entry. The top five bits are attributes which  may
7078              * propagate down through lower levels of the table (and
7079              * which are all arranged so that 0 means "no effect", so
7080              * we can gather them up by ORing in the bits at each level).
7081              */
7082             tableattrs |= extract64(descriptor, 59, 5);
7083             level++;
7084             continue;
7085         }
7086         /* Block entry at level 1 or 2, or page entry at level 3.
7087          * These are basically the same thing, although the number
7088          * of bits we pull in from the vaddr varies.
7089          */
7090         page_size = (1ULL << ((stride * (4 - level)) + 3));
7091         descaddr |= (address & (page_size - 1));
7092         /* Extract attributes from the descriptor */
7093         attrs = extract64(descriptor, 2, 10)
7094             | (extract64(descriptor, 52, 12) << 10);
7095
7096         if (mmu_idx == ARMMMUIdx_S2NS) {
7097             /* Stage 2 table descriptors do not include any attribute fields */
7098             break;
7099         }
7100         /* Merge in attributes from table descriptors */
7101         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
7102         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
7103         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
7104          * means "force PL1 access only", which means forcing AP[1] to 0.
7105          */
7106         if (extract32(tableattrs, 2, 1)) {
7107             attrs &= ~(1 << 4);
7108         }
7109         attrs |= nstable << 3; /* NS */
7110         break;
7111     }
7112     /* Here descaddr is the final physical address, and attributes
7113      * are all in attrs.
7114      */
7115     fault_type = access_fault;
7116     if ((attrs & (1 << 8)) == 0) {
7117         /* Access flag */
7118         goto do_fault;
7119     }
7120
7121     ap = extract32(attrs, 4, 2);
7122     xn = extract32(attrs, 12, 1);
7123
7124     if (mmu_idx == ARMMMUIdx_S2NS) {
7125         ns = true;
7126         *prot = get_S2prot(env, ap, xn);
7127     } else {
7128         ns = extract32(attrs, 3, 1);
7129         pxn = extract32(attrs, 11, 1);
7130         *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
7131     }
7132
7133     fault_type = permission_fault;
7134     if (!(*prot & (1 << access_type))) {
7135         goto do_fault;
7136     }
7137
7138     if (ns) {
7139         /* The NS bit will (as required by the architecture) have no effect if
7140          * the CPU doesn't support TZ or this is a non-secure translation
7141          * regime, because the attribute will already be non-secure.
7142          */
7143         txattrs->secure = false;
7144     }
7145     *phys_ptr = descaddr;
7146     *page_size_ptr = page_size;
7147     return false;
7148
7149 do_fault:
7150     /* Long-descriptor format IFSR/DFSR value */
7151     *fsr = (1 << 9) | (fault_type << 2) | level;
7152     /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2.  */
7153     fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS);
7154     return true;
7155 }
7156
7157 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
7158                                                 ARMMMUIdx mmu_idx,
7159                                                 int32_t address, int *prot)
7160 {
7161     *prot = PAGE_READ | PAGE_WRITE;
7162     switch (address) {
7163     case 0xF0000000 ... 0xFFFFFFFF:
7164         if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
7165             *prot |= PAGE_EXEC;
7166         }
7167         break;
7168     case 0x00000000 ... 0x7FFFFFFF:
7169         *prot |= PAGE_EXEC;
7170         break;
7171     }
7172
7173 }
7174
7175 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
7176                                  int access_type, ARMMMUIdx mmu_idx,
7177                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7178 {
7179     ARMCPU *cpu = arm_env_get_cpu(env);
7180     int n;
7181     bool is_user = regime_is_user(env, mmu_idx);
7182
7183     *phys_ptr = address;
7184     *prot = 0;
7185
7186     if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
7187         get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7188     } else { /* MPU enabled */
7189         for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
7190             /* region search */
7191             uint32_t base = env->pmsav7.drbar[n];
7192             uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
7193             uint32_t rmask;
7194             bool srdis = false;
7195
7196             if (!(env->pmsav7.drsr[n] & 0x1)) {
7197                 continue;
7198             }
7199
7200             if (!rsize) {
7201                 qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
7202                 continue;
7203             }
7204             rsize++;
7205             rmask = (1ull << rsize) - 1;
7206
7207             if (base & rmask) {
7208                 qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
7209                               "to DRSR region size, mask = %" PRIx32,
7210                               base, rmask);
7211                 continue;
7212             }
7213
7214             if (address < base || address > base + rmask) {
7215                 continue;
7216             }
7217
7218             /* Region matched */
7219
7220             if (rsize >= 8) { /* no subregions for regions < 256 bytes */
7221                 int i, snd;
7222                 uint32_t srdis_mask;
7223
7224                 rsize -= 3; /* sub region size (power of 2) */
7225                 snd = ((address - base) >> rsize) & 0x7;
7226                 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
7227
7228                 srdis_mask = srdis ? 0x3 : 0x0;
7229                 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
7230                     /* This will check in groups of 2, 4 and then 8, whether
7231                      * the subregion bits are consistent. rsize is incremented
7232                      * back up to give the region size, considering consistent
7233                      * adjacent subregions as one region. Stop testing if rsize
7234                      * is already big enough for an entire QEMU page.
7235                      */
7236                     int snd_rounded = snd & ~(i - 1);
7237                     uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
7238                                                      snd_rounded + 8, i);
7239                     if (srdis_mask ^ srdis_multi) {
7240                         break;
7241                     }
7242                     srdis_mask = (srdis_mask << i) | srdis_mask;
7243                     rsize++;
7244                 }
7245             }
7246             if (rsize < TARGET_PAGE_BITS) {
7247                 qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
7248                               "alignment of %" PRIu32 " bits. Minimum is %d\n",
7249                               rsize, TARGET_PAGE_BITS);
7250                 continue;
7251             }
7252             if (srdis) {
7253                 continue;
7254             }
7255             break;
7256         }
7257
7258         if (n == -1) { /* no hits */
7259             if (cpu->pmsav7_dregion &&
7260                 (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
7261                 /* background fault */
7262                 *fsr = 0;
7263                 return true;
7264             }
7265             get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7266         } else { /* a MPU hit! */
7267             uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
7268
7269             if (is_user) { /* User mode AP bit decoding */
7270                 switch (ap) {
7271                 case 0:
7272                 case 1:
7273                 case 5:
7274                     break; /* no access */
7275                 case 3:
7276                     *prot |= PAGE_WRITE;
7277                     /* fall through */
7278                 case 2:
7279                 case 6:
7280                     *prot |= PAGE_READ | PAGE_EXEC;
7281                     break;
7282                 default:
7283                     qemu_log_mask(LOG_GUEST_ERROR,
7284                                   "Bad value for AP bits in DRACR %"
7285                                   PRIx32 "\n", ap);
7286                 }
7287             } else { /* Priv. mode AP bits decoding */
7288                 switch (ap) {
7289                 case 0:
7290                     break; /* no access */
7291                 case 1:
7292                 case 2:
7293                 case 3:
7294                     *prot |= PAGE_WRITE;
7295                     /* fall through */
7296                 case 5:
7297                 case 6:
7298                     *prot |= PAGE_READ | PAGE_EXEC;
7299                     break;
7300                 default:
7301                     qemu_log_mask(LOG_GUEST_ERROR,
7302                                   "Bad value for AP bits in DRACR %"
7303                                   PRIx32 "\n", ap);
7304                 }
7305             }
7306
7307             /* execute never */
7308             if (env->pmsav7.dracr[n] & (1 << 12)) {
7309                 *prot &= ~PAGE_EXEC;
7310             }
7311         }
7312     }
7313
7314     *fsr = 0x00d; /* Permission fault */
7315     return !(*prot & (1 << access_type));
7316 }
7317
7318 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
7319                                  int access_type, ARMMMUIdx mmu_idx,
7320                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7321 {
7322     int n;
7323     uint32_t mask;
7324     uint32_t base;
7325     bool is_user = regime_is_user(env, mmu_idx);
7326
7327     *phys_ptr = address;
7328     for (n = 7; n >= 0; n--) {
7329         base = env->cp15.c6_region[n];
7330         if ((base & 1) == 0) {
7331             continue;
7332         }
7333         mask = 1 << ((base >> 1) & 0x1f);
7334         /* Keep this shift separate from the above to avoid an
7335            (undefined) << 32.  */
7336         mask = (mask << 1) - 1;
7337         if (((base ^ address) & ~mask) == 0) {
7338             break;
7339         }
7340     }
7341     if (n < 0) {
7342         *fsr = 2;
7343         return true;
7344     }
7345
7346     if (access_type == 2) {
7347         mask = env->cp15.pmsav5_insn_ap;
7348     } else {
7349         mask = env->cp15.pmsav5_data_ap;
7350     }
7351     mask = (mask >> (n * 4)) & 0xf;
7352     switch (mask) {
7353     case 0:
7354         *fsr = 1;
7355         return true;
7356     case 1:
7357         if (is_user) {
7358             *fsr = 1;
7359             return true;
7360         }
7361         *prot = PAGE_READ | PAGE_WRITE;
7362         break;
7363     case 2:
7364         *prot = PAGE_READ;
7365         if (!is_user) {
7366             *prot |= PAGE_WRITE;
7367         }
7368         break;
7369     case 3:
7370         *prot = PAGE_READ | PAGE_WRITE;
7371         break;
7372     case 5:
7373         if (is_user) {
7374             *fsr = 1;
7375             return true;
7376         }
7377         *prot = PAGE_READ;
7378         break;
7379     case 6:
7380         *prot = PAGE_READ;
7381         break;
7382     default:
7383         /* Bad permission.  */
7384         *fsr = 1;
7385         return true;
7386     }
7387     *prot |= PAGE_EXEC;
7388     return false;
7389 }
7390
7391 /* get_phys_addr - get the physical address for this virtual address
7392  *
7393  * Find the physical address corresponding to the given virtual address,
7394  * by doing a translation table walk on MMU based systems or using the
7395  * MPU state on MPU based systems.
7396  *
7397  * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
7398  * prot and page_size may not be filled in, and the populated fsr value provides
7399  * information on why the translation aborted, in the format of a
7400  * DFSR/IFSR fault register, with the following caveats:
7401  *  * we honour the short vs long DFSR format differences.
7402  *  * the WnR bit is never set (the caller must do this).
7403  *  * for PSMAv5 based systems we don't bother to return a full FSR format
7404  *    value.
7405  *
7406  * @env: CPUARMState
7407  * @address: virtual address to get physical address for
7408  * @access_type: 0 for read, 1 for write, 2 for execute
7409  * @mmu_idx: MMU index indicating required translation regime
7410  * @phys_ptr: set to the physical address corresponding to the virtual address
7411  * @attrs: set to the memory transaction attributes to use
7412  * @prot: set to the permissions for the page containing phys_ptr
7413  * @page_size: set to the size of the page containing phys_ptr
7414  * @fsr: set to the DFSR/IFSR value on failure
7415  */
7416 static bool get_phys_addr(CPUARMState *env, target_ulong address,
7417                           int access_type, ARMMMUIdx mmu_idx,
7418                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
7419                           target_ulong *page_size, uint32_t *fsr,
7420                           ARMMMUFaultInfo *fi)
7421 {
7422     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
7423         /* Call ourselves recursively to do the stage 1 and then stage 2
7424          * translations.
7425          */
7426         if (arm_feature(env, ARM_FEATURE_EL2)) {
7427             hwaddr ipa;
7428             int s2_prot;
7429             int ret;
7430
7431             ret = get_phys_addr(env, address, access_type,
7432                                 mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs,
7433                                 prot, page_size, fsr, fi);
7434
7435             /* If S1 fails or S2 is disabled, return early.  */
7436             if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
7437                 *phys_ptr = ipa;
7438                 return ret;
7439             }
7440
7441             /* S1 is done. Now do S2 translation.  */
7442             ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS,
7443                                      phys_ptr, attrs, &s2_prot,
7444                                      page_size, fsr, fi);
7445             fi->s2addr = ipa;
7446             /* Combine the S1 and S2 perms.  */
7447             *prot &= s2_prot;
7448             return ret;
7449         } else {
7450             /*
7451              * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
7452              */
7453             mmu_idx += ARMMMUIdx_S1NSE0;
7454         }
7455     }
7456
7457     /* The page table entries may downgrade secure to non-secure, but
7458      * cannot upgrade an non-secure translation regime's attributes
7459      * to secure.
7460      */
7461     attrs->secure = regime_is_secure(env, mmu_idx);
7462     attrs->user = regime_is_user(env, mmu_idx);
7463
7464     /* Fast Context Switch Extension. This doesn't exist at all in v8.
7465      * In v7 and earlier it affects all stage 1 translations.
7466      */
7467     if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
7468         && !arm_feature(env, ARM_FEATURE_V8)) {
7469         if (regime_el(env, mmu_idx) == 3) {
7470             address += env->cp15.fcseidr_s;
7471         } else {
7472             address += env->cp15.fcseidr_ns;
7473         }
7474     }
7475
7476     /* pmsav7 has special handling for when MPU is disabled so call it before
7477      * the common MMU/MPU disabled check below.
7478      */
7479     if (arm_feature(env, ARM_FEATURE_MPU) &&
7480         arm_feature(env, ARM_FEATURE_V7)) {
7481         *page_size = TARGET_PAGE_SIZE;
7482         return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
7483                                     phys_ptr, prot, fsr);
7484     }
7485
7486     if (regime_translation_disabled(env, mmu_idx)) {
7487         /* MMU/MPU disabled.  */
7488         *phys_ptr = address;
7489         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7490         *page_size = TARGET_PAGE_SIZE;
7491         return 0;
7492     }
7493
7494     if (arm_feature(env, ARM_FEATURE_MPU)) {
7495         /* Pre-v7 MPU */
7496         *page_size = TARGET_PAGE_SIZE;
7497         return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
7498                                     phys_ptr, prot, fsr);
7499     }
7500
7501     if (regime_using_lpae_format(env, mmu_idx)) {
7502         return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
7503                                   attrs, prot, page_size, fsr, fi);
7504     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
7505         return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
7506                                 attrs, prot, page_size, fsr, fi);
7507     } else {
7508         return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
7509                                 prot, page_size, fsr, fi);
7510     }
7511 }
7512
7513 /* Walk the page table and (if the mapping exists) add the page
7514  * to the TLB. Return false on success, or true on failure. Populate
7515  * fsr with ARM DFSR/IFSR fault register format value on failure.
7516  */
7517 bool arm_tlb_fill(CPUState *cs, vaddr address,
7518                   int access_type, int mmu_idx, uint32_t *fsr,
7519                   ARMMMUFaultInfo *fi)
7520 {
7521     ARMCPU *cpu = ARM_CPU(cs);
7522     CPUARMState *env = &cpu->env;
7523     hwaddr phys_addr;
7524     target_ulong page_size;
7525     int prot;
7526     int ret;
7527     MemTxAttrs attrs = {};
7528
7529     ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
7530                         &attrs, &prot, &page_size, fsr, fi);
7531     if (!ret) {
7532         /* Map a single [sub]page.  */
7533         phys_addr &= TARGET_PAGE_MASK;
7534         address &= TARGET_PAGE_MASK;
7535         tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
7536                                 prot, mmu_idx, page_size);
7537         return 0;
7538     }
7539
7540     return ret;
7541 }
7542
7543 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
7544                                          MemTxAttrs *attrs)
7545 {
7546     ARMCPU *cpu = ARM_CPU(cs);
7547     CPUARMState *env = &cpu->env;
7548     hwaddr phys_addr;
7549     target_ulong page_size;
7550     int prot;
7551     bool ret;
7552     uint32_t fsr;
7553     ARMMMUFaultInfo fi = {};
7554
7555     *attrs = (MemTxAttrs) {};
7556
7557     ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr,
7558                         attrs, &prot, &page_size, &fsr, &fi);
7559
7560     if (ret) {
7561         return -1;
7562     }
7563     return phys_addr;
7564 }
7565
7566 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
7567 {
7568     if ((env->uncached_cpsr & CPSR_M) == mode) {
7569         env->regs[13] = val;
7570     } else {
7571         env->banked_r13[bank_number(mode)] = val;
7572     }
7573 }
7574
7575 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
7576 {
7577     if ((env->uncached_cpsr & CPSR_M) == mode) {
7578         return env->regs[13];
7579     } else {
7580         return env->banked_r13[bank_number(mode)];
7581     }
7582 }
7583
7584 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
7585 {
7586     ARMCPU *cpu = arm_env_get_cpu(env);
7587
7588     switch (reg) {
7589     case 0: /* APSR */
7590         return xpsr_read(env) & 0xf8000000;
7591     case 1: /* IAPSR */
7592         return xpsr_read(env) & 0xf80001ff;
7593     case 2: /* EAPSR */
7594         return xpsr_read(env) & 0xff00fc00;
7595     case 3: /* xPSR */
7596         return xpsr_read(env) & 0xff00fdff;
7597     case 5: /* IPSR */
7598         return xpsr_read(env) & 0x000001ff;
7599     case 6: /* EPSR */
7600         return xpsr_read(env) & 0x0700fc00;
7601     case 7: /* IEPSR */
7602         return xpsr_read(env) & 0x0700edff;
7603     case 8: /* MSP */
7604         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
7605     case 9: /* PSP */
7606         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
7607     case 16: /* PRIMASK */
7608         return (env->daif & PSTATE_I) != 0;
7609     case 17: /* BASEPRI */
7610     case 18: /* BASEPRI_MAX */
7611         return env->v7m.basepri;
7612     case 19: /* FAULTMASK */
7613         return (env->daif & PSTATE_F) != 0;
7614     case 20: /* CONTROL */
7615         return env->v7m.control;
7616     default:
7617         /* ??? For debugging only.  */
7618         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
7619         return 0;
7620     }
7621 }
7622
7623 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
7624 {
7625     ARMCPU *cpu = arm_env_get_cpu(env);
7626
7627     switch (reg) {
7628     case 0: /* APSR */
7629         xpsr_write(env, val, 0xf8000000);
7630         break;
7631     case 1: /* IAPSR */
7632         xpsr_write(env, val, 0xf8000000);
7633         break;
7634     case 2: /* EAPSR */
7635         xpsr_write(env, val, 0xfe00fc00);
7636         break;
7637     case 3: /* xPSR */
7638         xpsr_write(env, val, 0xfe00fc00);
7639         break;
7640     case 5: /* IPSR */
7641         /* IPSR bits are readonly.  */
7642         break;
7643     case 6: /* EPSR */
7644         xpsr_write(env, val, 0x0600fc00);
7645         break;
7646     case 7: /* IEPSR */
7647         xpsr_write(env, val, 0x0600fc00);
7648         break;
7649     case 8: /* MSP */
7650         if (env->v7m.current_sp)
7651             env->v7m.other_sp = val;
7652         else
7653             env->regs[13] = val;
7654         break;
7655     case 9: /* PSP */
7656         if (env->v7m.current_sp)
7657             env->regs[13] = val;
7658         else
7659             env->v7m.other_sp = val;
7660         break;
7661     case 16: /* PRIMASK */
7662         if (val & 1) {
7663             env->daif |= PSTATE_I;
7664         } else {
7665             env->daif &= ~PSTATE_I;
7666         }
7667         break;
7668     case 17: /* BASEPRI */
7669         env->v7m.basepri = val & 0xff;
7670         break;
7671     case 18: /* BASEPRI_MAX */
7672         val &= 0xff;
7673         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
7674             env->v7m.basepri = val;
7675         break;
7676     case 19: /* FAULTMASK */
7677         if (val & 1) {
7678             env->daif |= PSTATE_F;
7679         } else {
7680             env->daif &= ~PSTATE_F;
7681         }
7682         break;
7683     case 20: /* CONTROL */
7684         env->v7m.control = val & 3;
7685         switch_v7m_sp(env, (val & 2) != 0);
7686         break;
7687     default:
7688         /* ??? For debugging only.  */
7689         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
7690         return;
7691     }
7692 }
7693
7694 #endif
7695
7696 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
7697 {
7698     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
7699      * Note that we do not implement the (architecturally mandated)
7700      * alignment fault for attempts to use this on Device memory
7701      * (which matches the usual QEMU behaviour of not implementing either
7702      * alignment faults or any memory attribute handling).
7703      */
7704
7705     ARMCPU *cpu = arm_env_get_cpu(env);
7706     uint64_t blocklen = 4 << cpu->dcz_blocksize;
7707     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
7708
7709 #ifndef CONFIG_USER_ONLY
7710     {
7711         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
7712          * the block size so we might have to do more than one TLB lookup.
7713          * We know that in fact for any v8 CPU the page size is at least 4K
7714          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
7715          * 1K as an artefact of legacy v5 subpage support being present in the
7716          * same QEMU executable.
7717          */
7718         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
7719         void *hostaddr[maxidx];
7720         int try, i;
7721         unsigned mmu_idx = cpu_mmu_index(env, false);
7722         TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
7723
7724         for (try = 0; try < 2; try++) {
7725
7726             for (i = 0; i < maxidx; i++) {
7727                 hostaddr[i] = tlb_vaddr_to_host(env,
7728                                                 vaddr + TARGET_PAGE_SIZE * i,
7729                                                 1, mmu_idx);
7730                 if (!hostaddr[i]) {
7731                     break;
7732                 }
7733             }
7734             if (i == maxidx) {
7735                 /* If it's all in the TLB it's fair game for just writing to;
7736                  * we know we don't need to update dirty status, etc.
7737                  */
7738                 for (i = 0; i < maxidx - 1; i++) {
7739                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
7740                 }
7741                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
7742                 return;
7743             }
7744             /* OK, try a store and see if we can populate the tlb. This
7745              * might cause an exception if the memory isn't writable,
7746              * in which case we will longjmp out of here. We must for
7747              * this purpose use the actual register value passed to us
7748              * so that we get the fault address right.
7749              */
7750             helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA());
7751             /* Now we can populate the other TLB entries, if any */
7752             for (i = 0; i < maxidx; i++) {
7753                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
7754                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
7755                     helper_ret_stb_mmu(env, va, 0, oi, GETRA());
7756                 }
7757             }
7758         }
7759
7760         /* Slow path (probably attempt to do this to an I/O device or
7761          * similar, or clearing of a block of code we have translations
7762          * cached for). Just do a series of byte writes as the architecture
7763          * demands. It's not worth trying to use a cpu_physical_memory_map(),
7764          * memset(), unmap() sequence here because:
7765          *  + we'd need to account for the blocksize being larger than a page
7766          *  + the direct-RAM access case is almost always going to be dealt
7767          *    with in the fastpath code above, so there's no speed benefit
7768          *  + we would have to deal with the map returning NULL because the
7769          *    bounce buffer was in use
7770          */
7771         for (i = 0; i < blocklen; i++) {
7772             helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA());
7773         }
7774     }
7775 #else
7776     memset(g2h(vaddr), 0, blocklen);
7777 #endif
7778 }
7779
7780 /* Note that signed overflow is undefined in C.  The following routines are
7781    careful to use unsigned types where modulo arithmetic is required.
7782    Failure to do so _will_ break on newer gcc.  */
7783
7784 /* Signed saturating arithmetic.  */
7785
7786 /* Perform 16-bit signed saturating addition.  */
7787 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
7788 {
7789     uint16_t res;
7790
7791     res = a + b;
7792     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
7793         if (a & 0x8000)
7794             res = 0x8000;
7795         else
7796             res = 0x7fff;
7797     }
7798     return res;
7799 }
7800
7801 /* Perform 8-bit signed saturating addition.  */
7802 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
7803 {
7804     uint8_t res;
7805
7806     res = a + b;
7807     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
7808         if (a & 0x80)
7809             res = 0x80;
7810         else
7811             res = 0x7f;
7812     }
7813     return res;
7814 }
7815
7816 /* Perform 16-bit signed saturating subtraction.  */
7817 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
7818 {
7819     uint16_t res;
7820
7821     res = a - b;
7822     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
7823         if (a & 0x8000)
7824             res = 0x8000;
7825         else
7826             res = 0x7fff;
7827     }
7828     return res;
7829 }
7830
7831 /* Perform 8-bit signed saturating subtraction.  */
7832 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
7833 {
7834     uint8_t res;
7835
7836     res = a - b;
7837     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
7838         if (a & 0x80)
7839             res = 0x80;
7840         else
7841             res = 0x7f;
7842     }
7843     return res;
7844 }
7845
7846 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
7847 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
7848 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
7849 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
7850 #define PFX q
7851
7852 #include "op_addsub.h"
7853
7854 /* Unsigned saturating arithmetic.  */
7855 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
7856 {
7857     uint16_t res;
7858     res = a + b;
7859     if (res < a)
7860         res = 0xffff;
7861     return res;
7862 }
7863
7864 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
7865 {
7866     if (a > b)
7867         return a - b;
7868     else
7869         return 0;
7870 }
7871
7872 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
7873 {
7874     uint8_t res;
7875     res = a + b;
7876     if (res < a)
7877         res = 0xff;
7878     return res;
7879 }
7880
7881 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
7882 {
7883     if (a > b)
7884         return a - b;
7885     else
7886         return 0;
7887 }
7888
7889 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
7890 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
7891 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
7892 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
7893 #define PFX uq
7894
7895 #include "op_addsub.h"
7896
7897 /* Signed modulo arithmetic.  */
7898 #define SARITH16(a, b, n, op) do { \
7899     int32_t sum; \
7900     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
7901     RESULT(sum, n, 16); \
7902     if (sum >= 0) \
7903         ge |= 3 << (n * 2); \
7904     } while(0)
7905
7906 #define SARITH8(a, b, n, op) do { \
7907     int32_t sum; \
7908     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
7909     RESULT(sum, n, 8); \
7910     if (sum >= 0) \
7911         ge |= 1 << n; \
7912     } while(0)
7913
7914
7915 #define ADD16(a, b, n) SARITH16(a, b, n, +)
7916 #define SUB16(a, b, n) SARITH16(a, b, n, -)
7917 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
7918 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
7919 #define PFX s
7920 #define ARITH_GE
7921
7922 #include "op_addsub.h"
7923
7924 /* Unsigned modulo arithmetic.  */
7925 #define ADD16(a, b, n) do { \
7926     uint32_t sum; \
7927     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
7928     RESULT(sum, n, 16); \
7929     if ((sum >> 16) == 1) \
7930         ge |= 3 << (n * 2); \
7931     } while(0)
7932
7933 #define ADD8(a, b, n) do { \
7934     uint32_t sum; \
7935     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
7936     RESULT(sum, n, 8); \
7937     if ((sum >> 8) == 1) \
7938         ge |= 1 << n; \
7939     } while(0)
7940
7941 #define SUB16(a, b, n) do { \
7942     uint32_t sum; \
7943     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
7944     RESULT(sum, n, 16); \
7945     if ((sum >> 16) == 0) \
7946         ge |= 3 << (n * 2); \
7947     } while(0)
7948
7949 #define SUB8(a, b, n) do { \
7950     uint32_t sum; \
7951     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
7952     RESULT(sum, n, 8); \
7953     if ((sum >> 8) == 0) \
7954         ge |= 1 << n; \
7955     } while(0)
7956
7957 #define PFX u
7958 #define ARITH_GE
7959
7960 #include "op_addsub.h"
7961
7962 /* Halved signed arithmetic.  */
7963 #define ADD16(a, b, n) \
7964   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
7965 #define SUB16(a, b, n) \
7966   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
7967 #define ADD8(a, b, n) \
7968   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
7969 #define SUB8(a, b, n) \
7970   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
7971 #define PFX sh
7972
7973 #include "op_addsub.h"
7974
7975 /* Halved unsigned arithmetic.  */
7976 #define ADD16(a, b, n) \
7977   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7978 #define SUB16(a, b, n) \
7979   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7980 #define ADD8(a, b, n) \
7981   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7982 #define SUB8(a, b, n) \
7983   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7984 #define PFX uh
7985
7986 #include "op_addsub.h"
7987
7988 static inline uint8_t do_usad(uint8_t a, uint8_t b)
7989 {
7990     if (a > b)
7991         return a - b;
7992     else
7993         return b - a;
7994 }
7995
7996 /* Unsigned sum of absolute byte differences.  */
7997 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
7998 {
7999     uint32_t sum;
8000     sum = do_usad(a, b);
8001     sum += do_usad(a >> 8, b >> 8);
8002     sum += do_usad(a >> 16, b >>16);
8003     sum += do_usad(a >> 24, b >> 24);
8004     return sum;
8005 }
8006
8007 /* For ARMv6 SEL instruction.  */
8008 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
8009 {
8010     uint32_t mask;
8011
8012     mask = 0;
8013     if (flags & 1)
8014         mask |= 0xff;
8015     if (flags & 2)
8016         mask |= 0xff00;
8017     if (flags & 4)
8018         mask |= 0xff0000;
8019     if (flags & 8)
8020         mask |= 0xff000000;
8021     return (a & mask) | (b & ~mask);
8022 }
8023
8024 /* VFP support.  We follow the convention used for VFP instructions:
8025    Single precision routines have a "s" suffix, double precision a
8026    "d" suffix.  */
8027
8028 /* Convert host exception flags to vfp form.  */
8029 static inline int vfp_exceptbits_from_host(int host_bits)
8030 {
8031     int target_bits = 0;
8032
8033     if (host_bits & float_flag_invalid)
8034         target_bits |= 1;
8035     if (host_bits & float_flag_divbyzero)
8036         target_bits |= 2;
8037     if (host_bits & float_flag_overflow)
8038         target_bits |= 4;
8039     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
8040         target_bits |= 8;
8041     if (host_bits & float_flag_inexact)
8042         target_bits |= 0x10;
8043     if (host_bits & float_flag_input_denormal)
8044         target_bits |= 0x80;
8045     return target_bits;
8046 }
8047
8048 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
8049 {
8050     int i;
8051     uint32_t fpscr;
8052
8053     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
8054             | (env->vfp.vec_len << 16)
8055             | (env->vfp.vec_stride << 20);
8056     i = get_float_exception_flags(&env->vfp.fp_status);
8057     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
8058     fpscr |= vfp_exceptbits_from_host(i);
8059     return fpscr;
8060 }
8061
8062 uint32_t vfp_get_fpscr(CPUARMState *env)
8063 {
8064     return HELPER(vfp_get_fpscr)(env);
8065 }
8066
8067 /* Convert vfp exception flags to target form.  */
8068 static inline int vfp_exceptbits_to_host(int target_bits)
8069 {
8070     int host_bits = 0;
8071
8072     if (target_bits & 1)
8073         host_bits |= float_flag_invalid;
8074     if (target_bits & 2)
8075         host_bits |= float_flag_divbyzero;
8076     if (target_bits & 4)
8077         host_bits |= float_flag_overflow;
8078     if (target_bits & 8)
8079         host_bits |= float_flag_underflow;
8080     if (target_bits & 0x10)
8081         host_bits |= float_flag_inexact;
8082     if (target_bits & 0x80)
8083         host_bits |= float_flag_input_denormal;
8084     return host_bits;
8085 }
8086
8087 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
8088 {
8089     int i;
8090     uint32_t changed;
8091
8092     changed = env->vfp.xregs[ARM_VFP_FPSCR];
8093     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
8094     env->vfp.vec_len = (val >> 16) & 7;
8095     env->vfp.vec_stride = (val >> 20) & 3;
8096
8097     changed ^= val;
8098     if (changed & (3 << 22)) {
8099         i = (val >> 22) & 3;
8100         switch (i) {
8101         case FPROUNDING_TIEEVEN:
8102             i = float_round_nearest_even;
8103             break;
8104         case FPROUNDING_POSINF:
8105             i = float_round_up;
8106             break;
8107         case FPROUNDING_NEGINF:
8108             i = float_round_down;
8109             break;
8110         case FPROUNDING_ZERO:
8111             i = float_round_to_zero;
8112             break;
8113         }
8114         set_float_rounding_mode(i, &env->vfp.fp_status);
8115     }
8116     if (changed & (1 << 24)) {
8117         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8118         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8119     }
8120     if (changed & (1 << 25))
8121         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
8122
8123     i = vfp_exceptbits_to_host(val);
8124     set_float_exception_flags(i, &env->vfp.fp_status);
8125     set_float_exception_flags(0, &env->vfp.standard_fp_status);
8126 }
8127
8128 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
8129 {
8130     HELPER(vfp_set_fpscr)(env, val);
8131 }
8132
8133 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
8134
8135 #define VFP_BINOP(name) \
8136 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
8137 { \
8138     float_status *fpst = fpstp; \
8139     return float32_ ## name(a, b, fpst); \
8140 } \
8141 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
8142 { \
8143     float_status *fpst = fpstp; \
8144     return float64_ ## name(a, b, fpst); \
8145 }
8146 VFP_BINOP(add)
8147 VFP_BINOP(sub)
8148 VFP_BINOP(mul)
8149 VFP_BINOP(div)
8150 VFP_BINOP(min)
8151 VFP_BINOP(max)
8152 VFP_BINOP(minnum)
8153 VFP_BINOP(maxnum)
8154 #undef VFP_BINOP
8155
8156 float32 VFP_HELPER(neg, s)(float32 a)
8157 {
8158     return float32_chs(a);
8159 }
8160
8161 float64 VFP_HELPER(neg, d)(float64 a)
8162 {
8163     return float64_chs(a);
8164 }
8165
8166 float32 VFP_HELPER(abs, s)(float32 a)
8167 {
8168     return float32_abs(a);
8169 }
8170
8171 float64 VFP_HELPER(abs, d)(float64 a)
8172 {
8173     return float64_abs(a);
8174 }
8175
8176 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
8177 {
8178     return float32_sqrt(a, &env->vfp.fp_status);
8179 }
8180
8181 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
8182 {
8183     return float64_sqrt(a, &env->vfp.fp_status);
8184 }
8185
8186 /* XXX: check quiet/signaling case */
8187 #define DO_VFP_cmp(p, type) \
8188 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
8189 { \
8190     uint32_t flags; \
8191     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
8192     case 0: flags = 0x6; break; \
8193     case -1: flags = 0x8; break; \
8194     case 1: flags = 0x2; break; \
8195     default: case 2: flags = 0x3; break; \
8196     } \
8197     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8198         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8199 } \
8200 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
8201 { \
8202     uint32_t flags; \
8203     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
8204     case 0: flags = 0x6; break; \
8205     case -1: flags = 0x8; break; \
8206     case 1: flags = 0x2; break; \
8207     default: case 2: flags = 0x3; break; \
8208     } \
8209     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8210         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8211 }
8212 DO_VFP_cmp(s, float32)
8213 DO_VFP_cmp(d, float64)
8214 #undef DO_VFP_cmp
8215
8216 /* Integer to float and float to integer conversions */
8217
8218 #define CONV_ITOF(name, fsz, sign) \
8219     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
8220 { \
8221     float_status *fpst = fpstp; \
8222     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
8223 }
8224
8225 #define CONV_FTOI(name, fsz, sign, round) \
8226 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
8227 { \
8228     float_status *fpst = fpstp; \
8229     if (float##fsz##_is_any_nan(x)) { \
8230         float_raise(float_flag_invalid, fpst); \
8231         return 0; \
8232     } \
8233     return float##fsz##_to_##sign##int32##round(x, fpst); \
8234 }
8235
8236 #define FLOAT_CONVS(name, p, fsz, sign) \
8237 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
8238 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
8239 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
8240
8241 FLOAT_CONVS(si, s, 32, )
8242 FLOAT_CONVS(si, d, 64, )
8243 FLOAT_CONVS(ui, s, 32, u)
8244 FLOAT_CONVS(ui, d, 64, u)
8245
8246 #undef CONV_ITOF
8247 #undef CONV_FTOI
8248 #undef FLOAT_CONVS
8249
8250 /* floating point conversion */
8251 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
8252 {
8253     float64 r = float32_to_float64(x, &env->vfp.fp_status);
8254     /* ARM requires that S<->D conversion of any kind of NaN generates
8255      * a quiet NaN by forcing the most significant frac bit to 1.
8256      */
8257     return float64_maybe_silence_nan(r);
8258 }
8259
8260 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
8261 {
8262     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
8263     /* ARM requires that S<->D conversion of any kind of NaN generates
8264      * a quiet NaN by forcing the most significant frac bit to 1.
8265      */
8266     return float32_maybe_silence_nan(r);
8267 }
8268
8269 /* VFP3 fixed point conversion.  */
8270 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8271 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
8272                                      void *fpstp) \
8273 { \
8274     float_status *fpst = fpstp; \
8275     float##fsz tmp; \
8276     tmp = itype##_to_##float##fsz(x, fpst); \
8277     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
8278 }
8279
8280 /* Notice that we want only input-denormal exception flags from the
8281  * scalbn operation: the other possible flags (overflow+inexact if
8282  * we overflow to infinity, output-denormal) aren't correct for the
8283  * complete scale-and-convert operation.
8284  */
8285 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
8286 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
8287                                              uint32_t shift, \
8288                                              void *fpstp) \
8289 { \
8290     float_status *fpst = fpstp; \
8291     int old_exc_flags = get_float_exception_flags(fpst); \
8292     float##fsz tmp; \
8293     if (float##fsz##_is_any_nan(x)) { \
8294         float_raise(float_flag_invalid, fpst); \
8295         return 0; \
8296     } \
8297     tmp = float##fsz##_scalbn(x, shift, fpst); \
8298     old_exc_flags |= get_float_exception_flags(fpst) \
8299         & float_flag_input_denormal; \
8300     set_float_exception_flags(old_exc_flags, fpst); \
8301     return float##fsz##_to_##itype##round(tmp, fpst); \
8302 }
8303
8304 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
8305 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8306 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
8307 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8308
8309 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
8310 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8311 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8312
8313 VFP_CONV_FIX(sh, d, 64, 64, int16)
8314 VFP_CONV_FIX(sl, d, 64, 64, int32)
8315 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
8316 VFP_CONV_FIX(uh, d, 64, 64, uint16)
8317 VFP_CONV_FIX(ul, d, 64, 64, uint32)
8318 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
8319 VFP_CONV_FIX(sh, s, 32, 32, int16)
8320 VFP_CONV_FIX(sl, s, 32, 32, int32)
8321 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
8322 VFP_CONV_FIX(uh, s, 32, 32, uint16)
8323 VFP_CONV_FIX(ul, s, 32, 32, uint32)
8324 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
8325 #undef VFP_CONV_FIX
8326 #undef VFP_CONV_FIX_FLOAT
8327 #undef VFP_CONV_FLOAT_FIX_ROUND
8328
8329 /* Set the current fp rounding mode and return the old one.
8330  * The argument is a softfloat float_round_ value.
8331  */
8332 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
8333 {
8334     float_status *fp_status = &env->vfp.fp_status;
8335
8336     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8337     set_float_rounding_mode(rmode, fp_status);
8338
8339     return prev_rmode;
8340 }
8341
8342 /* Set the current fp rounding mode in the standard fp status and return
8343  * the old one. This is for NEON instructions that need to change the
8344  * rounding mode but wish to use the standard FPSCR values for everything
8345  * else. Always set the rounding mode back to the correct value after
8346  * modifying it.
8347  * The argument is a softfloat float_round_ value.
8348  */
8349 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
8350 {
8351     float_status *fp_status = &env->vfp.standard_fp_status;
8352
8353     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8354     set_float_rounding_mode(rmode, fp_status);
8355
8356     return prev_rmode;
8357 }
8358
8359 /* Half precision conversions.  */
8360 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
8361 {
8362     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8363     float32 r = float16_to_float32(make_float16(a), ieee, s);
8364     if (ieee) {
8365         return float32_maybe_silence_nan(r);
8366     }
8367     return r;
8368 }
8369
8370 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
8371 {
8372     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8373     float16 r = float32_to_float16(a, ieee, s);
8374     if (ieee) {
8375         r = float16_maybe_silence_nan(r);
8376     }
8377     return float16_val(r);
8378 }
8379
8380 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8381 {
8382     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
8383 }
8384
8385 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8386 {
8387     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
8388 }
8389
8390 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8391 {
8392     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
8393 }
8394
8395 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8396 {
8397     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
8398 }
8399
8400 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
8401 {
8402     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8403     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
8404     if (ieee) {
8405         return float64_maybe_silence_nan(r);
8406     }
8407     return r;
8408 }
8409
8410 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
8411 {
8412     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8413     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
8414     if (ieee) {
8415         r = float16_maybe_silence_nan(r);
8416     }
8417     return float16_val(r);
8418 }
8419
8420 #define float32_two make_float32(0x40000000)
8421 #define float32_three make_float32(0x40400000)
8422 #define float32_one_point_five make_float32(0x3fc00000)
8423
8424 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
8425 {
8426     float_status *s = &env->vfp.standard_fp_status;
8427     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8428         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8429         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8430             float_raise(float_flag_input_denormal, s);
8431         }
8432         return float32_two;
8433     }
8434     return float32_sub(float32_two, float32_mul(a, b, s), s);
8435 }
8436
8437 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
8438 {
8439     float_status *s = &env->vfp.standard_fp_status;
8440     float32 product;
8441     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8442         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8443         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8444             float_raise(float_flag_input_denormal, s);
8445         }
8446         return float32_one_point_five;
8447     }
8448     product = float32_mul(a, b, s);
8449     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
8450 }
8451
8452 /* NEON helpers.  */
8453
8454 /* Constants 256 and 512 are used in some helpers; we avoid relying on
8455  * int->float conversions at run-time.  */
8456 #define float64_256 make_float64(0x4070000000000000LL)
8457 #define float64_512 make_float64(0x4080000000000000LL)
8458 #define float32_maxnorm make_float32(0x7f7fffff)
8459 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
8460
8461 /* Reciprocal functions
8462  *
8463  * The algorithm that must be used to calculate the estimate
8464  * is specified by the ARM ARM, see FPRecipEstimate()
8465  */
8466
8467 static float64 recip_estimate(float64 a, float_status *real_fp_status)
8468 {
8469     /* These calculations mustn't set any fp exception flags,
8470      * so we use a local copy of the fp_status.
8471      */
8472     float_status dummy_status = *real_fp_status;
8473     float_status *s = &dummy_status;
8474     /* q = (int)(a * 512.0) */
8475     float64 q = float64_mul(float64_512, a, s);
8476     int64_t q_int = float64_to_int64_round_to_zero(q, s);
8477
8478     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
8479     q = int64_to_float64(q_int, s);
8480     q = float64_add(q, float64_half, s);
8481     q = float64_div(q, float64_512, s);
8482     q = float64_div(float64_one, q, s);
8483
8484     /* s = (int)(256.0 * r + 0.5) */
8485     q = float64_mul(q, float64_256, s);
8486     q = float64_add(q, float64_half, s);
8487     q_int = float64_to_int64_round_to_zero(q, s);
8488
8489     /* return (double)s / 256.0 */
8490     return float64_div(int64_to_float64(q_int, s), float64_256, s);
8491 }
8492
8493 /* Common wrapper to call recip_estimate */
8494 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
8495 {
8496     uint64_t val64 = float64_val(num);
8497     uint64_t frac = extract64(val64, 0, 52);
8498     int64_t exp = extract64(val64, 52, 11);
8499     uint64_t sbit;
8500     float64 scaled, estimate;
8501
8502     /* Generate the scaled number for the estimate function */
8503     if (exp == 0) {
8504         if (extract64(frac, 51, 1) == 0) {
8505             exp = -1;
8506             frac = extract64(frac, 0, 50) << 2;
8507         } else {
8508             frac = extract64(frac, 0, 51) << 1;
8509         }
8510     }
8511
8512     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
8513     scaled = make_float64((0x3feULL << 52)
8514                           | extract64(frac, 44, 8) << 44);
8515
8516     estimate = recip_estimate(scaled, fpst);
8517
8518     /* Build new result */
8519     val64 = float64_val(estimate);
8520     sbit = 0x8000000000000000ULL & val64;
8521     exp = off - exp;
8522     frac = extract64(val64, 0, 52);
8523
8524     if (exp == 0) {
8525         frac = 1ULL << 51 | extract64(frac, 1, 51);
8526     } else if (exp == -1) {
8527         frac = 1ULL << 50 | extract64(frac, 2, 50);
8528         exp = 0;
8529     }
8530
8531     return make_float64(sbit | (exp << 52) | frac);
8532 }
8533
8534 static bool round_to_inf(float_status *fpst, bool sign_bit)
8535 {
8536     switch (fpst->float_rounding_mode) {
8537     case float_round_nearest_even: /* Round to Nearest */
8538         return true;
8539     case float_round_up: /* Round to +Inf */
8540         return !sign_bit;
8541     case float_round_down: /* Round to -Inf */
8542         return sign_bit;
8543     case float_round_to_zero: /* Round to Zero */
8544         return false;
8545     }
8546
8547     g_assert_not_reached();
8548 }
8549
8550 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
8551 {
8552     float_status *fpst = fpstp;
8553     float32 f32 = float32_squash_input_denormal(input, fpst);
8554     uint32_t f32_val = float32_val(f32);
8555     uint32_t f32_sbit = 0x80000000ULL & f32_val;
8556     int32_t f32_exp = extract32(f32_val, 23, 8);
8557     uint32_t f32_frac = extract32(f32_val, 0, 23);
8558     float64 f64, r64;
8559     uint64_t r64_val;
8560     int64_t r64_exp;
8561     uint64_t r64_frac;
8562
8563     if (float32_is_any_nan(f32)) {
8564         float32 nan = f32;
8565         if (float32_is_signaling_nan(f32)) {
8566             float_raise(float_flag_invalid, fpst);
8567             nan = float32_maybe_silence_nan(f32);
8568         }
8569         if (fpst->default_nan_mode) {
8570             nan =  float32_default_nan;
8571         }
8572         return nan;
8573     } else if (float32_is_infinity(f32)) {
8574         return float32_set_sign(float32_zero, float32_is_neg(f32));
8575     } else if (float32_is_zero(f32)) {
8576         float_raise(float_flag_divbyzero, fpst);
8577         return float32_set_sign(float32_infinity, float32_is_neg(f32));
8578     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
8579         /* Abs(value) < 2.0^-128 */
8580         float_raise(float_flag_overflow | float_flag_inexact, fpst);
8581         if (round_to_inf(fpst, f32_sbit)) {
8582             return float32_set_sign(float32_infinity, float32_is_neg(f32));
8583         } else {
8584             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
8585         }
8586     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
8587         float_raise(float_flag_underflow, fpst);
8588         return float32_set_sign(float32_zero, float32_is_neg(f32));
8589     }
8590
8591
8592     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
8593     r64 = call_recip_estimate(f64, 253, fpst);
8594     r64_val = float64_val(r64);
8595     r64_exp = extract64(r64_val, 52, 11);
8596     r64_frac = extract64(r64_val, 0, 52);
8597
8598     /* result = sign : result_exp<7:0> : fraction<51:29>; */
8599     return make_float32(f32_sbit |
8600                         (r64_exp & 0xff) << 23 |
8601                         extract64(r64_frac, 29, 24));
8602 }
8603
8604 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
8605 {
8606     float_status *fpst = fpstp;
8607     float64 f64 = float64_squash_input_denormal(input, fpst);
8608     uint64_t f64_val = float64_val(f64);
8609     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
8610     int64_t f64_exp = extract64(f64_val, 52, 11);
8611     float64 r64;
8612     uint64_t r64_val;
8613     int64_t r64_exp;
8614     uint64_t r64_frac;
8615
8616     /* Deal with any special cases */
8617     if (float64_is_any_nan(f64)) {
8618         float64 nan = f64;
8619         if (float64_is_signaling_nan(f64)) {
8620             float_raise(float_flag_invalid, fpst);
8621             nan = float64_maybe_silence_nan(f64);
8622         }
8623         if (fpst->default_nan_mode) {
8624             nan =  float64_default_nan;
8625         }
8626         return nan;
8627     } else if (float64_is_infinity(f64)) {
8628         return float64_set_sign(float64_zero, float64_is_neg(f64));
8629     } else if (float64_is_zero(f64)) {
8630         float_raise(float_flag_divbyzero, fpst);
8631         return float64_set_sign(float64_infinity, float64_is_neg(f64));
8632     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
8633         /* Abs(value) < 2.0^-1024 */
8634         float_raise(float_flag_overflow | float_flag_inexact, fpst);
8635         if (round_to_inf(fpst, f64_sbit)) {
8636             return float64_set_sign(float64_infinity, float64_is_neg(f64));
8637         } else {
8638             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
8639         }
8640     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
8641         float_raise(float_flag_underflow, fpst);
8642         return float64_set_sign(float64_zero, float64_is_neg(f64));
8643     }
8644
8645     r64 = call_recip_estimate(f64, 2045, fpst);
8646     r64_val = float64_val(r64);
8647     r64_exp = extract64(r64_val, 52, 11);
8648     r64_frac = extract64(r64_val, 0, 52);
8649
8650     /* result = sign : result_exp<10:0> : fraction<51:0> */
8651     return make_float64(f64_sbit |
8652                         ((r64_exp & 0x7ff) << 52) |
8653                         r64_frac);
8654 }
8655
8656 /* The algorithm that must be used to calculate the estimate
8657  * is specified by the ARM ARM.
8658  */
8659 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
8660 {
8661     /* These calculations mustn't set any fp exception flags,
8662      * so we use a local copy of the fp_status.
8663      */
8664     float_status dummy_status = *real_fp_status;
8665     float_status *s = &dummy_status;
8666     float64 q;
8667     int64_t q_int;
8668
8669     if (float64_lt(a, float64_half, s)) {
8670         /* range 0.25 <= a < 0.5 */
8671
8672         /* a in units of 1/512 rounded down */
8673         /* q0 = (int)(a * 512.0);  */
8674         q = float64_mul(float64_512, a, s);
8675         q_int = float64_to_int64_round_to_zero(q, s);
8676
8677         /* reciprocal root r */
8678         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
8679         q = int64_to_float64(q_int, s);
8680         q = float64_add(q, float64_half, s);
8681         q = float64_div(q, float64_512, s);
8682         q = float64_sqrt(q, s);
8683         q = float64_div(float64_one, q, s);
8684     } else {
8685         /* range 0.5 <= a < 1.0 */
8686
8687         /* a in units of 1/256 rounded down */
8688         /* q1 = (int)(a * 256.0); */
8689         q = float64_mul(float64_256, a, s);
8690         int64_t q_int = float64_to_int64_round_to_zero(q, s);
8691
8692         /* reciprocal root r */
8693         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
8694         q = int64_to_float64(q_int, s);
8695         q = float64_add(q, float64_half, s);
8696         q = float64_div(q, float64_256, s);
8697         q = float64_sqrt(q, s);
8698         q = float64_div(float64_one, q, s);
8699     }
8700     /* r in units of 1/256 rounded to nearest */
8701     /* s = (int)(256.0 * r + 0.5); */
8702
8703     q = float64_mul(q, float64_256,s );
8704     q = float64_add(q, float64_half, s);
8705     q_int = float64_to_int64_round_to_zero(q, s);
8706
8707     /* return (double)s / 256.0;*/
8708     return float64_div(int64_to_float64(q_int, s), float64_256, s);
8709 }
8710
8711 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
8712 {
8713     float_status *s = fpstp;
8714     float32 f32 = float32_squash_input_denormal(input, s);
8715     uint32_t val = float32_val(f32);
8716     uint32_t f32_sbit = 0x80000000 & val;
8717     int32_t f32_exp = extract32(val, 23, 8);
8718     uint32_t f32_frac = extract32(val, 0, 23);
8719     uint64_t f64_frac;
8720     uint64_t val64;
8721     int result_exp;
8722     float64 f64;
8723
8724     if (float32_is_any_nan(f32)) {
8725         float32 nan = f32;
8726         if (float32_is_signaling_nan(f32)) {
8727             float_raise(float_flag_invalid, s);
8728             nan = float32_maybe_silence_nan(f32);
8729         }
8730         if (s->default_nan_mode) {
8731             nan =  float32_default_nan;
8732         }
8733         return nan;
8734     } else if (float32_is_zero(f32)) {
8735         float_raise(float_flag_divbyzero, s);
8736         return float32_set_sign(float32_infinity, float32_is_neg(f32));
8737     } else if (float32_is_neg(f32)) {
8738         float_raise(float_flag_invalid, s);
8739         return float32_default_nan;
8740     } else if (float32_is_infinity(f32)) {
8741         return float32_zero;
8742     }
8743
8744     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8745      * preserving the parity of the exponent.  */
8746
8747     f64_frac = ((uint64_t) f32_frac) << 29;
8748     if (f32_exp == 0) {
8749         while (extract64(f64_frac, 51, 1) == 0) {
8750             f64_frac = f64_frac << 1;
8751             f32_exp = f32_exp-1;
8752         }
8753         f64_frac = extract64(f64_frac, 0, 51) << 1;
8754     }
8755
8756     if (extract64(f32_exp, 0, 1) == 0) {
8757         f64 = make_float64(((uint64_t) f32_sbit) << 32
8758                            | (0x3feULL << 52)
8759                            | f64_frac);
8760     } else {
8761         f64 = make_float64(((uint64_t) f32_sbit) << 32
8762                            | (0x3fdULL << 52)
8763                            | f64_frac);
8764     }
8765
8766     result_exp = (380 - f32_exp) / 2;
8767
8768     f64 = recip_sqrt_estimate(f64, s);
8769
8770     val64 = float64_val(f64);
8771
8772     val = ((result_exp & 0xff) << 23)
8773         | ((val64 >> 29)  & 0x7fffff);
8774     return make_float32(val);
8775 }
8776
8777 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
8778 {
8779     float_status *s = fpstp;
8780     float64 f64 = float64_squash_input_denormal(input, s);
8781     uint64_t val = float64_val(f64);
8782     uint64_t f64_sbit = 0x8000000000000000ULL & val;
8783     int64_t f64_exp = extract64(val, 52, 11);
8784     uint64_t f64_frac = extract64(val, 0, 52);
8785     int64_t result_exp;
8786     uint64_t result_frac;
8787
8788     if (float64_is_any_nan(f64)) {
8789         float64 nan = f64;
8790         if (float64_is_signaling_nan(f64)) {
8791             float_raise(float_flag_invalid, s);
8792             nan = float64_maybe_silence_nan(f64);
8793         }
8794         if (s->default_nan_mode) {
8795             nan =  float64_default_nan;
8796         }
8797         return nan;
8798     } else if (float64_is_zero(f64)) {
8799         float_raise(float_flag_divbyzero, s);
8800         return float64_set_sign(float64_infinity, float64_is_neg(f64));
8801     } else if (float64_is_neg(f64)) {
8802         float_raise(float_flag_invalid, s);
8803         return float64_default_nan;
8804     } else if (float64_is_infinity(f64)) {
8805         return float64_zero;
8806     }
8807
8808     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8809      * preserving the parity of the exponent.  */
8810
8811     if (f64_exp == 0) {
8812         while (extract64(f64_frac, 51, 1) == 0) {
8813             f64_frac = f64_frac << 1;
8814             f64_exp = f64_exp - 1;
8815         }
8816         f64_frac = extract64(f64_frac, 0, 51) << 1;
8817     }
8818
8819     if (extract64(f64_exp, 0, 1) == 0) {
8820         f64 = make_float64(f64_sbit
8821                            | (0x3feULL << 52)
8822                            | f64_frac);
8823     } else {
8824         f64 = make_float64(f64_sbit
8825                            | (0x3fdULL << 52)
8826                            | f64_frac);
8827     }
8828
8829     result_exp = (3068 - f64_exp) / 2;
8830
8831     f64 = recip_sqrt_estimate(f64, s);
8832
8833     result_frac = extract64(float64_val(f64), 0, 52);
8834
8835     return make_float64(f64_sbit |
8836                         ((result_exp & 0x7ff) << 52) |
8837                         result_frac);
8838 }
8839
8840 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
8841 {
8842     float_status *s = fpstp;
8843     float64 f64;
8844
8845     if ((a & 0x80000000) == 0) {
8846         return 0xffffffff;
8847     }
8848
8849     f64 = make_float64((0x3feULL << 52)
8850                        | ((int64_t)(a & 0x7fffffff) << 21));
8851
8852     f64 = recip_estimate(f64, s);
8853
8854     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
8855 }
8856
8857 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
8858 {
8859     float_status *fpst = fpstp;
8860     float64 f64;
8861
8862     if ((a & 0xc0000000) == 0) {
8863         return 0xffffffff;
8864     }
8865
8866     if (a & 0x80000000) {
8867         f64 = make_float64((0x3feULL << 52)
8868                            | ((uint64_t)(a & 0x7fffffff) << 21));
8869     } else { /* bits 31-30 == '01' */
8870         f64 = make_float64((0x3fdULL << 52)
8871                            | ((uint64_t)(a & 0x3fffffff) << 22));
8872     }
8873
8874     f64 = recip_sqrt_estimate(f64, fpst);
8875
8876     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
8877 }
8878
8879 /* VFPv4 fused multiply-accumulate */
8880 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
8881 {
8882     float_status *fpst = fpstp;
8883     return float32_muladd(a, b, c, 0, fpst);
8884 }
8885
8886 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
8887 {
8888     float_status *fpst = fpstp;
8889     return float64_muladd(a, b, c, 0, fpst);
8890 }
8891
8892 /* ARMv8 round to integral */
8893 float32 HELPER(rints_exact)(float32 x, void *fp_status)
8894 {
8895     return float32_round_to_int(x, fp_status);
8896 }
8897
8898 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
8899 {
8900     return float64_round_to_int(x, fp_status);
8901 }
8902
8903 float32 HELPER(rints)(float32 x, void *fp_status)
8904 {
8905     int old_flags = get_float_exception_flags(fp_status), new_flags;
8906     float32 ret;
8907
8908     ret = float32_round_to_int(x, fp_status);
8909
8910     /* Suppress any inexact exceptions the conversion produced */
8911     if (!(old_flags & float_flag_inexact)) {
8912         new_flags = get_float_exception_flags(fp_status);
8913         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
8914     }
8915
8916     return ret;
8917 }
8918
8919 float64 HELPER(rintd)(float64 x, void *fp_status)
8920 {
8921     int old_flags = get_float_exception_flags(fp_status), new_flags;
8922     float64 ret;
8923
8924     ret = float64_round_to_int(x, fp_status);
8925
8926     new_flags = get_float_exception_flags(fp_status);
8927
8928     /* Suppress any inexact exceptions the conversion produced */
8929     if (!(old_flags & float_flag_inexact)) {
8930         new_flags = get_float_exception_flags(fp_status);
8931         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
8932     }
8933
8934     return ret;
8935 }
8936
8937 /* Convert ARM rounding mode to softfloat */
8938 int arm_rmode_to_sf(int rmode)
8939 {
8940     switch (rmode) {
8941     case FPROUNDING_TIEAWAY:
8942         rmode = float_round_ties_away;
8943         break;
8944     case FPROUNDING_ODD:
8945         /* FIXME: add support for TIEAWAY and ODD */
8946         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
8947                       rmode);
8948     case FPROUNDING_TIEEVEN:
8949     default:
8950         rmode = float_round_nearest_even;
8951         break;
8952     case FPROUNDING_POSINF:
8953         rmode = float_round_up;
8954         break;
8955     case FPROUNDING_NEGINF:
8956         rmode = float_round_down;
8957         break;
8958     case FPROUNDING_ZERO:
8959         rmode = float_round_to_zero;
8960         break;
8961     }
8962     return rmode;
8963 }
8964
8965 /* CRC helpers.
8966  * The upper bytes of val (above the number specified by 'bytes') must have
8967  * been zeroed out by the caller.
8968  */
8969 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
8970 {
8971     uint8_t buf[4];
8972
8973     stl_le_p(buf, val);
8974
8975     /* zlib crc32 converts the accumulator and output to one's complement.  */
8976     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
8977 }
8978
8979 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
8980 {
8981     uint8_t buf[4];
8982
8983     stl_le_p(buf, val);
8984
8985     /* Linux crc32c converts the output to one's complement.  */
8986     return crc32c(acc, buf, bytes) ^ 0xffffffff;
8987 }