hw/intc/bcm2836_control.c

   1 /*
   2  * Rasperry Pi 2 emulation ARM control logic module.
   3  * Copyright (c) 2015, Microsoft
   4  * Written by Andrew Baumann
   5  *
   6  * Based on bcm2835_ic.c (Raspberry Pi emulation) (c) 2012 Gregory Estrade
   7  * This code is licensed under the GNU GPLv2 and later.
   8  *
   9  * At present, only implements interrupt routing, and mailboxes (i.e.,
  10  * not local timer, PMU interrupt, or AXI counters).
  11  *
  12  * Ref:
  13  * https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf
  14  */
  15
  16 #include "hw/intc/bcm2836_control.h"
  17
  18 #define ROUTE_CORE(x) ((x) & 0x3)
  19 #define ROUTE_FIQ(x)  (((x) & 0x4) != 0)
  20
  21 #define IRQ_BIT(cntrl, num) (((cntrl) & (1 << (num))) != 0)
  22 #define FIQ_BIT(cntrl, num) (((cntrl) & (1 << ((num) + 4))) != 0)
  23
  24 #define IRQ_CNTPSIRQ    0
  25 #define IRQ_CNTPNSIRQ   1
  26 #define IRQ_CNTHPIRQ    2
  27 #define IRQ_CNTVIRQ     3
  28 #define IRQ_MAILBOX0    4
  29 #define IRQ_MAILBOX1    5
  30 #define IRQ_MAILBOX2    6
  31 #define IRQ_MAILBOX3    7
  32 #define IRQ_GPU         8
  33 #define IRQ_PMU         9
  34 #define IRQ_AXI         10
  35 #define IRQ_TIMER       11
  36 #define IRQ_MAX         IRQ_TIMER
  37
  38 /* Update interrupts.  */
  39 static void bcm2836_control_update(BCM2836ControlState *s)
  40 {
  41     int i, j;
  42
  43     /* reset pending IRQs/FIQs */
  44     for (i = 0; i < BCM2836_NCORES; i++) {
  45         s->irqsrc[i] = s->fiqsrc[i] = 0;
  46     }
  47
  48     /* apply routing logic, update status regs */
  49     if (s->gpu_irq) {
  50         assert(s->route_gpu_irq < BCM2836_NCORES);
  51         s->irqsrc[s->route_gpu_irq] |= (uint32_t)1 << IRQ_GPU;
  52     }
  53
  54     if (s->gpu_fiq) {
  55         assert(s->route_gpu_fiq < BCM2836_NCORES);
  56         s->fiqsrc[s->route_gpu_fiq] |= (uint32_t)1 << IRQ_GPU;
  57     }
  58
  59     for (i = 0; i < BCM2836_NCORES; i++) {
  60         /* handle local interrupts for this core */
  61         if (s->localirqs[i]) {
  62             /* sanity check localirqs: mailboxes are handled below */
  63             assert(s->localirqs[i] < (1 << IRQ_MAILBOX0));
  64             for (j = 0; j < IRQ_MAILBOX0; j++) {
  65                 if ((s->localirqs[i] & (1 << j)) != 0) {
  66                     /* local interrupt j is set */
  67                     if (FIQ_BIT(s->timercontrol[i], j)) {
  68                         /* deliver a FIQ */
  69                         s->fiqsrc[i] |= (uint32_t)1 << j;
  70                     } else if (IRQ_BIT(s->timercontrol[i], j)) {
  71                         /* deliver an IRQ */
  72                         s->irqsrc[i] |= (uint32_t)1 << j;
  73                     } else {
  74                         /* the interrupt is masked */
  75                     }
  76                 }
  77             }
  78         }
  79
  80         /* handle mailboxes for this core */
  81         for (j = 0; j < BCM2836_MBPERCORE; j++) {
  82             if (s->mailboxes[i * BCM2836_MBPERCORE + j] != 0) {
  83                 /* mailbox j is set */
  84                 if (FIQ_BIT(s->mailboxcontrol[i], j)) {
  85                     /* deliver a FIQ */
  86                     s->fiqsrc[i] |= (uint32_t)1 << (j + IRQ_MAILBOX0);
  87                 } else if (IRQ_BIT(s->mailboxcontrol[i], j)) {
  88                     /* deliver an IRQ */
  89                     s->irqsrc[i] |= (uint32_t)1 << (j + IRQ_MAILBOX0);
  90                 } else {
  91                     /* the interrupt is masked */
  92                 }
  93             }
  94         }
  95     }
  96
  97     /* call set_irq appropriately for each output */
  98     for (i = 0; i < BCM2836_NCORES; i++) {
  99         qemu_set_irq(s->irq[i], s->irqsrc[i] != 0);
 100         qemu_set_irq(s->fiq[i], s->fiqsrc[i] != 0);
 101     }
 102 }
 103
 104 static void bcm2836_control_set_local_irq(void *opaque, int core, int local_irq,
 105                                           int level)
 106 {
 107     BCM2836ControlState *s = opaque;
 108
 109     assert(core >= 0 && core < BCM2836_NCORES);
 110     assert(local_irq >= 0 && local_irq <= IRQ_CNTVIRQ);
 111
 112     if (level) {
 113         s->localirqs[core] |= 1 << local_irq;
 114     } else {
 115         s->localirqs[core] &= ~((uint32_t)1 << local_irq);
 116     }
 117
 118     bcm2836_control_update(s);
 119 }
 120
 121 /* XXX: the following wrapper functions are a kludgy workaround,
 122  * needed because I can't seem to pass useful information in the "irq"
 123  * parameter when using named interrupts. Feel free to clean this up!
 124  */
 125
 126 static void bcm2836_control_set_local_irq0(void *opaque, int core, int level)
 127 {
 128     bcm2836_control_set_local_irq(opaque, core, 0, level);
 129 }
 130
 131 static void bcm2836_control_set_local_irq1(void *opaque, int core, int level)
 132 {
 133     bcm2836_control_set_local_irq(opaque, core, 1, level);
 134 }
 135
 136 static void bcm2836_control_set_local_irq2(void *opaque, int core, int level)
 137 {
 138     bcm2836_control_set_local_irq(opaque, core, 2, level);
 139 }
 140
 141 static void bcm2836_control_set_local_irq3(void *opaque, int core, int level)
 142 {
 143     bcm2836_control_set_local_irq(opaque, core, 3, level);
 144 }
 145
 146 static void bcm2836_control_set_gpu_irq(void *opaque, int irq, int level)
 147 {
 148     BCM2836ControlState *s = opaque;
 149
 150     s->gpu_irq = level;
 151
 152     bcm2836_control_update(s);
 153 }
 154
 155 static void bcm2836_control_set_gpu_fiq(void *opaque, int irq, int level)
 156 {
 157     BCM2836ControlState *s = opaque;
 158
 159     s->gpu_fiq = level;
 160
 161     bcm2836_control_update(s);
 162 }
 163
 164 static uint64_t bcm2836_control_read(void *opaque, hwaddr offset, unsigned size)
 165 {
 166     BCM2836ControlState *s = opaque;
 167
 168     if (offset == 0xc) {
 169         /* GPU interrupt routing */
 170         assert(s->route_gpu_fiq < BCM2836_NCORES
 171                && s->route_gpu_irq < BCM2836_NCORES);
 172         return ((uint32_t)s->route_gpu_fiq << 2) | s->route_gpu_irq;
 173     } else if (offset >= 0x40 && offset < 0x50) {
 174         /* Timer interrupt control registers */
 175         return s->timercontrol[(offset - 0x40) >> 2];
 176     } else if (offset >= 0x50 && offset < 0x60) {
 177         /* Mailbox interrupt control registers */
 178         return s->mailboxcontrol[(offset - 0x50) >> 2];
 179     } else if (offset >= 0x60 && offset < 0x70) {
 180         /* IRQ source registers */
 181         return s->irqsrc[(offset - 0x60) >> 2];
 182     } else if (offset >= 0x70 && offset < 0x80) {
 183         /* FIQ source registers */
 184         return s->fiqsrc[(offset - 0x70) >> 2];
 185     } else if (offset >= 0xc0 && offset < 0x100) {
 186         /* Mailboxes */
 187         return s->mailboxes[(offset - 0xc0) >> 2];
 188     } else {
 189         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 190                       __func__, offset);
 191         return 0;
 192     }
 193 }
 194
 195 static void bcm2836_control_write(void *opaque, hwaddr offset,
 196                                   uint64_t val, unsigned size)
 197 {
 198     BCM2836ControlState *s = opaque;
 199
 200     if (offset == 0xc) {
 201         /* GPU interrupt routing */
 202         s->route_gpu_irq = val & 0x3;
 203         s->route_gpu_fiq = (val >> 2) & 0x3;
 204     } else if (offset >= 0x40 && offset < 0x50) {
 205         /* Timer interrupt control registers */
 206         s->timercontrol[(offset - 0x40) >> 2] = val & 0xff;
 207     } else if (offset >= 0x50 && offset < 0x60) {
 208         /* Mailbox interrupt control registers */
 209         s->mailboxcontrol[(offset - 0x50) >> 2] = val & 0xff;
 210     } else if (offset >= 0x80 && offset < 0xc0) {
 211         /* Mailbox set registers */
 212         s->mailboxes[(offset - 0x80) >> 2] |= val;
 213     } else if (offset >= 0xc0 && offset < 0x100) {
 214         /* Mailbox clear registers */
 215         s->mailboxes[(offset - 0xc0) >> 2] &= ~val;
 216     } else {
 217         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 218                       __func__, offset);
 219         return;
 220     }
 221
 222     bcm2836_control_update(s);
 223 }
 224
 225 static const MemoryRegionOps bcm2836_control_ops = {
 226     .read = bcm2836_control_read,
 227     .write = bcm2836_control_write,
 228     .endianness = DEVICE_NATIVE_ENDIAN,
 229     .valid.min_access_size = 4,
 230     .valid.max_access_size = 4,
 231 };
 232
 233 static void bcm2836_control_reset(DeviceState *d)
 234 {
 235     BCM2836ControlState *s = BCM2836_CONTROL(d);
 236     int i;
 237
 238     s->route_gpu_irq = s->route_gpu_fiq = 0;
 239
 240     for (i = 0; i < BCM2836_NCORES; i++) {
 241         s->timercontrol[i] = 0;
 242         s->mailboxcontrol[i] = 0;
 243     }
 244
 245     for (i = 0; i < BCM2836_NCORES * BCM2836_MBPERCORE; i++) {
 246         s->mailboxes[i] = 0;
 247     }
 248 }
 249
 250 static void bcm2836_control_init(Object *obj)
 251 {
 252     BCM2836ControlState *s = BCM2836_CONTROL(obj);
 253     DeviceState *dev = DEVICE(obj);
 254
 255     memory_region_init_io(&s->iomem, obj, &bcm2836_control_ops, s,
 256                           TYPE_BCM2836_CONTROL, 0x100);
 257     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 258
 259     /* inputs from each CPU core */
 260     qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq0, "cntpsirq",
 261                             BCM2836_NCORES);
 262     qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq1, "cntpnsirq",
 263                             BCM2836_NCORES);
 264     qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq2, "cnthpirq",
 265                             BCM2836_NCORES);
 266     qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq3, "cntvirq",
 267                             BCM2836_NCORES);
 268     /* qdev_init_gpio_in_named(dev, bcm2836_control_set_pmu_irq, "pmuirq",
 269                             BCM2836_NCORES); */
 270
 271     /* IRQ and FIQ inputs from upstream bcm2835 controller */
 272     qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_irq, "gpu_irq", 1);
 273     qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_fiq, "gpu_fiq", 1);
 274
 275     /* outputs to CPU cores */
 276     qdev_init_gpio_out_named(dev, s->irq, "irq", BCM2836_NCORES);
 277     qdev_init_gpio_out_named(dev, s->fiq, "fiq", BCM2836_NCORES);
 278 }
 279
 280 static const VMStateDescription vmstate_bcm2836_control = {
 281     .name = TYPE_BCM2836_CONTROL,
 282     .version_id = 1,
 283     .minimum_version_id = 1,
 284     .fields = (VMStateField[]) {
 285         VMSTATE_UINT32_ARRAY(mailboxes, BCM2836ControlState,
 286                              BCM2836_NCORES * BCM2836_MBPERCORE),
 287         VMSTATE_UINT8(route_gpu_irq, BCM2836ControlState),
 288         VMSTATE_UINT8(route_gpu_fiq, BCM2836ControlState),
 289         VMSTATE_UINT32_ARRAY(timercontrol, BCM2836ControlState, BCM2836_NCORES),
 290         VMSTATE_UINT32_ARRAY(mailboxcontrol, BCM2836ControlState,
 291                              BCM2836_NCORES),
 292         VMSTATE_END_OF_LIST()
 293     }
 294 };
 295
 296 static void bcm2836_control_class_init(ObjectClass *klass, void *data)
 297 {
 298     DeviceClass *dc = DEVICE_CLASS(klass);
 299
 300     dc->reset = bcm2836_control_reset;
 301     dc->vmsd = &vmstate_bcm2836_control;
 302 }
 303
 304 static TypeInfo bcm2836_control_info = {
 305     .name          = TYPE_BCM2836_CONTROL,
 306     .parent        = TYPE_SYS_BUS_DEVICE,
 307     .instance_size = sizeof(BCM2836ControlState),
 308     .class_init    = bcm2836_control_class_init,
 309     .instance_init = bcm2836_control_init,
 310 };
 311
 312 static void bcm2836_control_register_types(void)
 313 {
 314     type_register_static(&bcm2836_control_info);
 315 }
 316
 317 type_init(bcm2836_control_register_types)