4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
24 #include "tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "exec/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* Function prototype for gen_ functions for calling Neon helpers */
74 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
75 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
76 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
78 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
80 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
81 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
82 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
83 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
84 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
85 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
86 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
87 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
88 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, TCGMemOp
);
90 /* initialize TCG globals. */
91 void a64_translate_init(void)
95 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, pc
),
98 for (i
= 0; i
< 32; i
++) {
99 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
100 offsetof(CPUARMState
, xregs
[i
]),
104 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
105 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
108 static inline int get_a64_user_mem_index(DisasContext
*s
)
110 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
111 * if EL1, access as if EL0; otherwise access at current EL
115 switch (s
->mmu_idx
) {
116 case ARMMMUIdx_S12NSE1
:
117 useridx
= ARMMMUIdx_S12NSE0
;
119 case ARMMMUIdx_S1SE1
:
120 useridx
= ARMMMUIdx_S1SE0
;
123 g_assert_not_reached();
125 useridx
= s
->mmu_idx
;
128 return arm_to_core_mmu_idx(useridx
);
131 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
132 fprintf_function cpu_fprintf
, int flags
)
134 ARMCPU
*cpu
= ARM_CPU(cs
);
135 CPUARMState
*env
= &cpu
->env
;
136 uint32_t psr
= pstate_read(env
);
138 int el
= arm_current_el(env
);
139 const char *ns_status
;
141 cpu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
142 for (i
= 0; i
< 32; i
++) {
144 cpu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
146 cpu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
147 (i
+ 2) % 3 ? " " : "\n");
151 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
152 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
156 cpu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
158 psr
& PSTATE_N
? 'N' : '-',
159 psr
& PSTATE_Z
? 'Z' : '-',
160 psr
& PSTATE_C
? 'C' : '-',
161 psr
& PSTATE_V
? 'V' : '-',
164 psr
& PSTATE_SP
? 'h' : 't');
166 if (!(flags
& CPU_DUMP_FPU
)) {
167 cpu_fprintf(f
, "\n");
170 if (fp_exception_el(env
, el
) != 0) {
171 cpu_fprintf(f
, " FPU disabled\n");
174 cpu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
175 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
177 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
178 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
180 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
182 if (i
== FFR_PRED_NUM
) {
183 cpu_fprintf(f
, "FFR=");
184 /* It's last, so end the line. */
187 cpu_fprintf(f
, "P%02d=", i
);
200 /* More than one quadword per predicate. */
205 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
207 if (j
* 4 + 4 <= zcr_len
+ 1) {
210 digits
= (zcr_len
% 4 + 1) * 4;
212 cpu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
213 env
->vfp
.pregs
[i
].p
[j
],
214 j
? ":" : eol
? "\n" : " ");
218 for (i
= 0; i
< 32; i
++) {
220 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
221 i
, env
->vfp
.zregs
[i
].d
[1],
222 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
223 } else if (zcr_len
== 1) {
224 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
225 ":%016" PRIx64
":%016" PRIx64
"\n",
226 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
227 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
229 for (j
= zcr_len
; j
>= 0; j
--) {
230 bool odd
= (zcr_len
- j
) % 2 != 0;
232 cpu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
235 cpu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
237 cpu_fprintf(f
, " [%x]=", j
);
240 cpu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
241 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
242 env
->vfp
.zregs
[i
].d
[j
* 2],
243 odd
|| j
== 0 ? "\n" : ":");
248 for (i
= 0; i
< 32; i
++) {
249 uint64_t *q
= aa64_vfp_qreg(env
, i
);
250 cpu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
251 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
256 void gen_a64_set_pc_im(uint64_t val
)
258 tcg_gen_movi_i64(cpu_pc
, val
);
261 /* Load the PC from a generic TCG variable.
263 * If address tagging is enabled via the TCR TBI bits, then loading
264 * an address into the PC will clear out any tag in the it:
265 * + for EL2 and EL3 there is only one TBI bit, and if it is set
266 * then the address is zero-extended, clearing bits [63:56]
267 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
268 * and TBI1 controls addressses with bit 55 == 1.
269 * If the appropriate TBI bit is set for the address then
270 * the address is sign-extended from bit 55 into bits [63:56]
272 * We can avoid doing this for relative-branches, because the
273 * PC + offset can never overflow into the tag bits (assuming
274 * that virtual addresses are less than 56 bits wide, as they
275 * are currently), but we must handle it for branch-to-register.
277 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
280 if (s
->current_el
<= 1) {
281 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
282 * examine bit 55 of address, can just generate code.
283 * If mixed, then test via generated code
285 if (s
->tbi0
&& s
->tbi1
) {
286 TCGv_i64 tmp_reg
= tcg_temp_new_i64();
287 /* Both bits set, sign extension from bit 55 into [63:56] will
290 tcg_gen_shli_i64(tmp_reg
, src
, 8);
291 tcg_gen_sari_i64(cpu_pc
, tmp_reg
, 8);
292 tcg_temp_free_i64(tmp_reg
);
293 } else if (!s
->tbi0
&& !s
->tbi1
) {
294 /* Neither bit set, just load it as-is */
295 tcg_gen_mov_i64(cpu_pc
, src
);
297 TCGv_i64 tcg_tmpval
= tcg_temp_new_i64();
298 TCGv_i64 tcg_bit55
= tcg_temp_new_i64();
299 TCGv_i64 tcg_zero
= tcg_const_i64(0);
301 tcg_gen_andi_i64(tcg_bit55
, src
, (1ull << 55));
304 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
305 tcg_gen_andi_i64(tcg_tmpval
, src
,
306 0x00FFFFFFFFFFFFFFull
);
307 tcg_gen_movcond_i64(TCG_COND_EQ
, cpu_pc
, tcg_bit55
, tcg_zero
,
310 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
311 tcg_gen_ori_i64(tcg_tmpval
, src
,
312 0xFF00000000000000ull
);
313 tcg_gen_movcond_i64(TCG_COND_NE
, cpu_pc
, tcg_bit55
, tcg_zero
,
316 tcg_temp_free_i64(tcg_zero
);
317 tcg_temp_free_i64(tcg_bit55
);
318 tcg_temp_free_i64(tcg_tmpval
);
320 } else { /* EL > 1 */
322 /* Force tag byte to all zero */
323 tcg_gen_andi_i64(cpu_pc
, src
, 0x00FFFFFFFFFFFFFFull
);
325 /* Load unmodified address */
326 tcg_gen_mov_i64(cpu_pc
, src
);
331 typedef struct DisasCompare64
{
336 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
340 arm_test_cc(&c32
, cc
);
342 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
343 * properly. The NE/EQ comparisons are also fine with this choice. */
344 c64
->cond
= c32
.cond
;
345 c64
->value
= tcg_temp_new_i64();
346 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
351 static void a64_free_cc(DisasCompare64
*c64
)
353 tcg_temp_free_i64(c64
->value
);
356 static void gen_exception_internal(int excp
)
358 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
360 assert(excp_is_internal(excp
));
361 gen_helper_exception_internal(cpu_env
, tcg_excp
);
362 tcg_temp_free_i32(tcg_excp
);
365 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
367 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
368 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
369 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
371 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
373 tcg_temp_free_i32(tcg_el
);
374 tcg_temp_free_i32(tcg_syn
);
375 tcg_temp_free_i32(tcg_excp
);
378 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
380 gen_a64_set_pc_im(s
->pc
- offset
);
381 gen_exception_internal(excp
);
382 s
->base
.is_jmp
= DISAS_NORETURN
;
385 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
386 uint32_t syndrome
, uint32_t target_el
)
388 gen_a64_set_pc_im(s
->pc
- offset
);
389 gen_exception(excp
, syndrome
, target_el
);
390 s
->base
.is_jmp
= DISAS_NORETURN
;
393 static void gen_exception_bkpt_insn(DisasContext
*s
, int offset
,
398 gen_a64_set_pc_im(s
->pc
- offset
);
399 tcg_syn
= tcg_const_i32(syndrome
);
400 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
401 tcg_temp_free_i32(tcg_syn
);
402 s
->base
.is_jmp
= DISAS_NORETURN
;
405 static void gen_ss_advance(DisasContext
*s
)
407 /* If the singlestep state is Active-not-pending, advance to
412 gen_helper_clear_pstate_ss(cpu_env
);
416 static void gen_step_complete_exception(DisasContext
*s
)
418 /* We just completed step of an insn. Move from Active-not-pending
419 * to Active-pending, and then also take the swstep exception.
420 * This corresponds to making the (IMPDEF) choice to prioritize
421 * swstep exceptions over asynchronous exceptions taken to an exception
422 * level where debug is disabled. This choice has the advantage that
423 * we do not need to maintain internal state corresponding to the
424 * ISV/EX syndrome bits between completion of the step and generation
425 * of the exception, and our syndrome information is always correct.
428 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
429 default_exception_el(s
));
430 s
->base
.is_jmp
= DISAS_NORETURN
;
433 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
435 /* No direct tb linking with singlestep (either QEMU's or the ARM
436 * debug architecture kind) or deterministic io
438 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
439 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
443 #ifndef CONFIG_USER_ONLY
444 /* Only link tbs from inside the same guest page */
445 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
453 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
455 TranslationBlock
*tb
;
458 if (use_goto_tb(s
, n
, dest
)) {
460 gen_a64_set_pc_im(dest
);
461 tcg_gen_exit_tb(tb
, n
);
462 s
->base
.is_jmp
= DISAS_NORETURN
;
464 gen_a64_set_pc_im(dest
);
466 gen_step_complete_exception(s
);
467 } else if (s
->base
.singlestep_enabled
) {
468 gen_exception_internal(EXCP_DEBUG
);
470 tcg_gen_lookup_and_goto_ptr();
471 s
->base
.is_jmp
= DISAS_NORETURN
;
476 void unallocated_encoding(DisasContext
*s
)
478 /* Unallocated and reserved encodings are uncategorized */
479 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
480 default_exception_el(s
));
483 static void init_tmp_a64_array(DisasContext
*s
)
485 #ifdef CONFIG_DEBUG_TCG
486 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
488 s
->tmp_a64_count
= 0;
491 static void free_tmp_a64(DisasContext
*s
)
494 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
495 tcg_temp_free_i64(s
->tmp_a64
[i
]);
497 init_tmp_a64_array(s
);
500 TCGv_i64
new_tmp_a64(DisasContext
*s
)
502 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
503 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
506 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
508 TCGv_i64 t
= new_tmp_a64(s
);
509 tcg_gen_movi_i64(t
, 0);
514 * Register access functions
516 * These functions are used for directly accessing a register in where
517 * changes to the final register value are likely to be made. If you
518 * need to use a register for temporary calculation (e.g. index type
519 * operations) use the read_* form.
521 * B1.2.1 Register mappings
523 * In instruction register encoding 31 can refer to ZR (zero register) or
524 * the SP (stack pointer) depending on context. In QEMU's case we map SP
525 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
526 * This is the point of the _sp forms.
528 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
531 return new_tmp_a64_zero(s
);
537 /* register access for when 31 == SP */
538 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
543 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
544 * representing the register contents. This TCGv is an auto-freed
545 * temporary so it need not be explicitly freed, and may be modified.
547 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
549 TCGv_i64 v
= new_tmp_a64(s
);
552 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
554 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
557 tcg_gen_movi_i64(v
, 0);
562 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
564 TCGv_i64 v
= new_tmp_a64(s
);
566 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
568 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
573 /* Return the offset into CPUARMState of a slice (from
574 * the least significant end) of FP register Qn (ie
576 * (Note that this is not the same mapping as for A32; see cpu.h)
578 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
580 return vec_reg_offset(s
, regno
, 0, size
);
583 /* Offset of the high half of the 128 bit vector Qn */
584 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
586 return vec_reg_offset(s
, regno
, 1, MO_64
);
589 /* Convenience accessors for reading and writing single and double
590 * FP registers. Writing clears the upper parts of the associated
591 * 128 bit vector register, as required by the architecture.
592 * Note that unlike the GP register accessors, the values returned
593 * by the read functions must be manually freed.
595 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
597 TCGv_i64 v
= tcg_temp_new_i64();
599 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
603 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
605 TCGv_i32 v
= tcg_temp_new_i32();
607 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
611 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
613 TCGv_i32 v
= tcg_temp_new_i32();
615 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
619 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
620 * If SVE is not enabled, then there are only 128 bits in the vector.
622 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
624 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
625 unsigned vsz
= vec_full_reg_size(s
);
628 TCGv_i64 tcg_zero
= tcg_const_i64(0);
629 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
630 tcg_temp_free_i64(tcg_zero
);
633 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
637 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
639 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
641 tcg_gen_st_i64(v
, cpu_env
, ofs
);
642 clear_vec_high(s
, false, reg
);
645 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
647 TCGv_i64 tmp
= tcg_temp_new_i64();
649 tcg_gen_extu_i32_i64(tmp
, v
);
650 write_fp_dreg(s
, reg
, tmp
);
651 tcg_temp_free_i64(tmp
);
654 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
656 TCGv_ptr statusptr
= tcg_temp_new_ptr();
659 /* In A64 all instructions (both FP and Neon) use the FPCR; there
660 * is no equivalent of the A32 Neon "standard FPSCR value".
661 * However half-precision operations operate under a different
662 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
665 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
667 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
669 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
673 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
674 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
675 GVecGen2Fn
*gvec_fn
, int vece
)
677 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
678 is_q
? 16 : 8, vec_full_reg_size(s
));
681 /* Expand a 2-operand + immediate AdvSIMD vector operation using
682 * an expander function.
684 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
685 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
687 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
688 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
691 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
692 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
693 GVecGen3Fn
*gvec_fn
, int vece
)
695 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
696 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
699 /* Expand a 2-operand + immediate AdvSIMD vector operation using
702 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
703 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
705 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
706 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
709 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
710 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
711 int rn
, int rm
, const GVecGen3
*gvec_op
)
713 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
714 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
715 vec_full_reg_size(s
), gvec_op
);
718 /* Expand a 3-operand operation using an out-of-line helper. */
719 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
720 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
722 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
723 vec_full_reg_offset(s
, rn
),
724 vec_full_reg_offset(s
, rm
),
725 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
728 /* Expand a 3-operand + env pointer operation using
729 * an out-of-line helper.
731 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
732 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
734 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
735 vec_full_reg_offset(s
, rn
),
736 vec_full_reg_offset(s
, rm
), cpu_env
,
737 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
740 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
741 * an out-of-line helper.
743 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
744 int rm
, bool is_fp16
, int data
,
745 gen_helper_gvec_3_ptr
*fn
)
747 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
748 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
749 vec_full_reg_offset(s
, rn
),
750 vec_full_reg_offset(s
, rm
), fpst
,
751 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
752 tcg_temp_free_ptr(fpst
);
755 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
756 * than the 32 bit equivalent.
758 static inline void gen_set_NZ64(TCGv_i64 result
)
760 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
761 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
764 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
765 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
768 gen_set_NZ64(result
);
770 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
771 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
773 tcg_gen_movi_i32(cpu_CF
, 0);
774 tcg_gen_movi_i32(cpu_VF
, 0);
777 /* dest = T0 + T1; compute C, N, V and Z flags */
778 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
781 TCGv_i64 result
, flag
, tmp
;
782 result
= tcg_temp_new_i64();
783 flag
= tcg_temp_new_i64();
784 tmp
= tcg_temp_new_i64();
786 tcg_gen_movi_i64(tmp
, 0);
787 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
789 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
791 gen_set_NZ64(result
);
793 tcg_gen_xor_i64(flag
, result
, t0
);
794 tcg_gen_xor_i64(tmp
, t0
, t1
);
795 tcg_gen_andc_i64(flag
, flag
, tmp
);
796 tcg_temp_free_i64(tmp
);
797 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
799 tcg_gen_mov_i64(dest
, result
);
800 tcg_temp_free_i64(result
);
801 tcg_temp_free_i64(flag
);
803 /* 32 bit arithmetic */
804 TCGv_i32 t0_32
= tcg_temp_new_i32();
805 TCGv_i32 t1_32
= tcg_temp_new_i32();
806 TCGv_i32 tmp
= tcg_temp_new_i32();
808 tcg_gen_movi_i32(tmp
, 0);
809 tcg_gen_extrl_i64_i32(t0_32
, t0
);
810 tcg_gen_extrl_i64_i32(t1_32
, t1
);
811 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
812 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
813 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
814 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
815 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
816 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
818 tcg_temp_free_i32(tmp
);
819 tcg_temp_free_i32(t0_32
);
820 tcg_temp_free_i32(t1_32
);
824 /* dest = T0 - T1; compute C, N, V and Z flags */
825 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
828 /* 64 bit arithmetic */
829 TCGv_i64 result
, flag
, tmp
;
831 result
= tcg_temp_new_i64();
832 flag
= tcg_temp_new_i64();
833 tcg_gen_sub_i64(result
, t0
, t1
);
835 gen_set_NZ64(result
);
837 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
838 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
840 tcg_gen_xor_i64(flag
, result
, t0
);
841 tmp
= tcg_temp_new_i64();
842 tcg_gen_xor_i64(tmp
, t0
, t1
);
843 tcg_gen_and_i64(flag
, flag
, tmp
);
844 tcg_temp_free_i64(tmp
);
845 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
846 tcg_gen_mov_i64(dest
, result
);
847 tcg_temp_free_i64(flag
);
848 tcg_temp_free_i64(result
);
850 /* 32 bit arithmetic */
851 TCGv_i32 t0_32
= tcg_temp_new_i32();
852 TCGv_i32 t1_32
= tcg_temp_new_i32();
855 tcg_gen_extrl_i64_i32(t0_32
, t0
);
856 tcg_gen_extrl_i64_i32(t1_32
, t1
);
857 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
858 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
859 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
860 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
861 tmp
= tcg_temp_new_i32();
862 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
863 tcg_temp_free_i32(t0_32
);
864 tcg_temp_free_i32(t1_32
);
865 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
866 tcg_temp_free_i32(tmp
);
867 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
871 /* dest = T0 + T1 + CF; do not compute flags. */
872 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
874 TCGv_i64 flag
= tcg_temp_new_i64();
875 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
876 tcg_gen_add_i64(dest
, t0
, t1
);
877 tcg_gen_add_i64(dest
, dest
, flag
);
878 tcg_temp_free_i64(flag
);
881 tcg_gen_ext32u_i64(dest
, dest
);
885 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
886 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
889 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
890 result
= tcg_temp_new_i64();
891 cf_64
= tcg_temp_new_i64();
892 vf_64
= tcg_temp_new_i64();
893 tmp
= tcg_const_i64(0);
895 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
896 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
897 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
898 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
899 gen_set_NZ64(result
);
901 tcg_gen_xor_i64(vf_64
, result
, t0
);
902 tcg_gen_xor_i64(tmp
, t0
, t1
);
903 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
904 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
906 tcg_gen_mov_i64(dest
, result
);
908 tcg_temp_free_i64(tmp
);
909 tcg_temp_free_i64(vf_64
);
910 tcg_temp_free_i64(cf_64
);
911 tcg_temp_free_i64(result
);
913 TCGv_i32 t0_32
, t1_32
, tmp
;
914 t0_32
= tcg_temp_new_i32();
915 t1_32
= tcg_temp_new_i32();
916 tmp
= tcg_const_i32(0);
918 tcg_gen_extrl_i64_i32(t0_32
, t0
);
919 tcg_gen_extrl_i64_i32(t1_32
, t1
);
920 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
921 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
923 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
924 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
925 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
926 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
927 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
929 tcg_temp_free_i32(tmp
);
930 tcg_temp_free_i32(t1_32
);
931 tcg_temp_free_i32(t0_32
);
936 * Load/Store generators
940 * Store from GPR register to memory.
942 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
943 TCGv_i64 tcg_addr
, int size
, int memidx
,
945 unsigned int iss_srt
,
946 bool iss_sf
, bool iss_ar
)
949 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
954 syn
= syn_data_abort_with_iss(0,
960 0, 0, 0, 0, 0, false);
961 disas_set_insn_syndrome(s
, syn
);
965 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
966 TCGv_i64 tcg_addr
, int size
,
968 unsigned int iss_srt
,
969 bool iss_sf
, bool iss_ar
)
971 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
972 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
976 * Load from memory to GPR register
978 static void do_gpr_ld_memidx(DisasContext
*s
,
979 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
980 int size
, bool is_signed
,
981 bool extend
, int memidx
,
982 bool iss_valid
, unsigned int iss_srt
,
983 bool iss_sf
, bool iss_ar
)
985 TCGMemOp memop
= s
->be_data
+ size
;
993 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
995 if (extend
&& is_signed
) {
997 tcg_gen_ext32u_i64(dest
, dest
);
1003 syn
= syn_data_abort_with_iss(0,
1009 0, 0, 0, 0, 0, false);
1010 disas_set_insn_syndrome(s
, syn
);
1014 static void do_gpr_ld(DisasContext
*s
,
1015 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
1016 int size
, bool is_signed
, bool extend
,
1017 bool iss_valid
, unsigned int iss_srt
,
1018 bool iss_sf
, bool iss_ar
)
1020 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
1022 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
1026 * Store from FP register to memory
1028 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
1030 /* This writes the bottom N bits of a 128 bit wide vector to memory */
1031 TCGv_i64 tmp
= tcg_temp_new_i64();
1032 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
1034 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
1037 bool be
= s
->be_data
== MO_BE
;
1038 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
1040 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1041 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1043 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
1044 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1046 tcg_temp_free_i64(tcg_hiaddr
);
1049 tcg_temp_free_i64(tmp
);
1053 * Load from memory to FP register
1055 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1057 /* This always zero-extends and writes to a full 128 bit wide vector */
1058 TCGv_i64 tmplo
= tcg_temp_new_i64();
1062 TCGMemOp memop
= s
->be_data
+ size
;
1063 tmphi
= tcg_const_i64(0);
1064 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1066 bool be
= s
->be_data
== MO_BE
;
1067 TCGv_i64 tcg_hiaddr
;
1069 tmphi
= tcg_temp_new_i64();
1070 tcg_hiaddr
= tcg_temp_new_i64();
1072 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1073 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1075 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1077 tcg_temp_free_i64(tcg_hiaddr
);
1080 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1081 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1083 tcg_temp_free_i64(tmplo
);
1084 tcg_temp_free_i64(tmphi
);
1086 clear_vec_high(s
, true, destidx
);
1090 * Vector load/store helpers.
1092 * The principal difference between this and a FP load is that we don't
1093 * zero extend as we are filling a partial chunk of the vector register.
1094 * These functions don't support 128 bit loads/stores, which would be
1095 * normal load/store operations.
1097 * The _i32 versions are useful when operating on 32 bit quantities
1098 * (eg for floating point single or using Neon helper functions).
1101 /* Get value of an element within a vector register */
1102 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1103 int element
, TCGMemOp memop
)
1105 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1108 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1111 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1114 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1117 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1120 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1123 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1127 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1130 g_assert_not_reached();
1134 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1135 int element
, TCGMemOp memop
)
1137 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1140 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1143 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1146 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1149 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1153 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1156 g_assert_not_reached();
1160 /* Set value of an element within a vector register */
1161 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1162 int element
, TCGMemOp memop
)
1164 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1167 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1170 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1173 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1176 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1179 g_assert_not_reached();
1183 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1184 int destidx
, int element
, TCGMemOp memop
)
1186 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1189 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1192 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1195 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1198 g_assert_not_reached();
1202 /* Store from vector register to memory */
1203 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1204 TCGv_i64 tcg_addr
, int size
)
1206 TCGMemOp memop
= s
->be_data
+ size
;
1207 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1209 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1210 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1212 tcg_temp_free_i64(tcg_tmp
);
1215 /* Load from memory to vector register */
1216 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1217 TCGv_i64 tcg_addr
, int size
)
1219 TCGMemOp memop
= s
->be_data
+ size
;
1220 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1222 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1223 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1225 tcg_temp_free_i64(tcg_tmp
);
1228 /* Check that FP/Neon access is enabled. If it is, return
1229 * true. If not, emit code to generate an appropriate exception,
1230 * and return false; the caller should not emit any code for
1231 * the instruction. Note that this check must happen after all
1232 * unallocated-encoding checks (otherwise the syndrome information
1233 * for the resulting exception will be incorrect).
1235 static inline bool fp_access_check(DisasContext
*s
)
1237 assert(!s
->fp_access_checked
);
1238 s
->fp_access_checked
= true;
1240 if (!s
->fp_excp_el
) {
1244 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1249 /* Check that SVE access is enabled. If it is, return true.
1250 * If not, emit code to generate an appropriate exception and return false.
1252 bool sve_access_check(DisasContext
*s
)
1254 if (s
->sve_excp_el
) {
1255 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_sve_access_trap(),
1259 return fp_access_check(s
);
1263 * This utility function is for doing register extension with an
1264 * optional shift. You will likely want to pass a temporary for the
1265 * destination register. See DecodeRegExtend() in the ARM ARM.
1267 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1268 int option
, unsigned int shift
)
1270 int extsize
= extract32(option
, 0, 2);
1271 bool is_signed
= extract32(option
, 2, 1);
1276 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1279 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1282 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1285 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1291 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1294 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1297 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1300 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1306 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1310 static inline void gen_check_sp_alignment(DisasContext
*s
)
1312 /* The AArch64 architecture mandates that (if enabled via PSTATE
1313 * or SCTLR bits) there is a check that SP is 16-aligned on every
1314 * SP-relative load or store (with an exception generated if it is not).
1315 * In line with general QEMU practice regarding misaligned accesses,
1316 * we omit these checks for the sake of guest program performance.
1317 * This function is provided as a hook so we can more easily add these
1318 * checks in future (possibly as a "favour catching guest program bugs
1319 * over speed" user selectable option).
1324 * This provides a simple table based table lookup decoder. It is
1325 * intended to be used when the relevant bits for decode are too
1326 * awkwardly placed and switch/if based logic would be confusing and
1327 * deeply nested. Since it's a linear search through the table, tables
1328 * should be kept small.
1330 * It returns the first handler where insn & mask == pattern, or
1331 * NULL if there is no match.
1332 * The table is terminated by an empty mask (i.e. 0)
1334 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1337 const AArch64DecodeTable
*tptr
= table
;
1339 while (tptr
->mask
) {
1340 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1341 return tptr
->disas_fn
;
1349 * The instruction disassembly implemented here matches
1350 * the instruction encoding classifications in chapter C4
1351 * of the ARM Architecture Reference Manual (DDI0487B_a);
1352 * classification names and decode diagrams here should generally
1353 * match up with those in the manual.
1356 /* Unconditional branch (immediate)
1358 * +----+-----------+-------------------------------------+
1359 * | op | 0 0 1 0 1 | imm26 |
1360 * +----+-----------+-------------------------------------+
1362 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1364 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1366 if (insn
& (1U << 31)) {
1367 /* BL Branch with link */
1368 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1371 /* B Branch / BL Branch with link */
1372 gen_goto_tb(s
, 0, addr
);
1375 /* Compare and branch (immediate)
1376 * 31 30 25 24 23 5 4 0
1377 * +----+-------------+----+---------------------+--------+
1378 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1379 * +----+-------------+----+---------------------+--------+
1381 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1383 unsigned int sf
, op
, rt
;
1385 TCGLabel
*label_match
;
1388 sf
= extract32(insn
, 31, 1);
1389 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1390 rt
= extract32(insn
, 0, 5);
1391 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1393 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1394 label_match
= gen_new_label();
1396 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1397 tcg_cmp
, 0, label_match
);
1399 gen_goto_tb(s
, 0, s
->pc
);
1400 gen_set_label(label_match
);
1401 gen_goto_tb(s
, 1, addr
);
1404 /* Test and branch (immediate)
1405 * 31 30 25 24 23 19 18 5 4 0
1406 * +----+-------------+----+-------+-------------+------+
1407 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1408 * +----+-------------+----+-------+-------------+------+
1410 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1412 unsigned int bit_pos
, op
, rt
;
1414 TCGLabel
*label_match
;
1417 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1418 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1419 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1420 rt
= extract32(insn
, 0, 5);
1422 tcg_cmp
= tcg_temp_new_i64();
1423 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1424 label_match
= gen_new_label();
1425 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1426 tcg_cmp
, 0, label_match
);
1427 tcg_temp_free_i64(tcg_cmp
);
1428 gen_goto_tb(s
, 0, s
->pc
);
1429 gen_set_label(label_match
);
1430 gen_goto_tb(s
, 1, addr
);
1433 /* Conditional branch (immediate)
1434 * 31 25 24 23 5 4 3 0
1435 * +---------------+----+---------------------+----+------+
1436 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1437 * +---------------+----+---------------------+----+------+
1439 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1444 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1445 unallocated_encoding(s
);
1448 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1449 cond
= extract32(insn
, 0, 4);
1452 /* genuinely conditional branches */
1453 TCGLabel
*label_match
= gen_new_label();
1454 arm_gen_test_cc(cond
, label_match
);
1455 gen_goto_tb(s
, 0, s
->pc
);
1456 gen_set_label(label_match
);
1457 gen_goto_tb(s
, 1, addr
);
1459 /* 0xe and 0xf are both "always" conditions */
1460 gen_goto_tb(s
, 0, addr
);
1464 /* HINT instruction group, including various allocated HINTs */
1465 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1466 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1468 unsigned int selector
= crm
<< 3 | op2
;
1471 unallocated_encoding(s
);
1479 s
->base
.is_jmp
= DISAS_WFI
;
1481 /* When running in MTTCG we don't generate jumps to the yield and
1482 * WFE helpers as it won't affect the scheduling of other vCPUs.
1483 * If we wanted to more completely model WFE/SEV so we don't busy
1484 * spin unnecessarily we would need to do something more involved.
1487 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1488 s
->base
.is_jmp
= DISAS_YIELD
;
1492 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1493 s
->base
.is_jmp
= DISAS_WFE
;
1498 /* we treat all as NOP at least for now */
1501 /* default specified as NOP equivalent */
1506 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1508 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1511 /* CLREX, DSB, DMB, ISB */
1512 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1513 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1518 unallocated_encoding(s
);
1529 case 1: /* MBReqTypes_Reads */
1530 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1532 case 2: /* MBReqTypes_Writes */
1533 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1535 default: /* MBReqTypes_All */
1536 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1542 /* We need to break the TB after this insn to execute
1543 * a self-modified code correctly and also to take
1544 * any pending interrupts immediately.
1546 gen_goto_tb(s
, 0, s
->pc
);
1549 unallocated_encoding(s
);
1554 /* MSR (immediate) - move immediate to processor state field */
1555 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1556 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1558 int op
= op1
<< 3 | op2
;
1560 case 0x05: /* SPSel */
1561 if (s
->current_el
== 0) {
1562 unallocated_encoding(s
);
1566 case 0x1e: /* DAIFSet */
1567 case 0x1f: /* DAIFClear */
1569 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1570 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1571 gen_a64_set_pc_im(s
->pc
- 4);
1572 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1573 tcg_temp_free_i32(tcg_imm
);
1574 tcg_temp_free_i32(tcg_op
);
1575 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1576 gen_a64_set_pc_im(s
->pc
);
1577 s
->base
.is_jmp
= (op
== 0x1f ? DISAS_EXIT
: DISAS_JUMP
);
1581 unallocated_encoding(s
);
1586 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1588 TCGv_i32 tmp
= tcg_temp_new_i32();
1589 TCGv_i32 nzcv
= tcg_temp_new_i32();
1591 /* build bit 31, N */
1592 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1593 /* build bit 30, Z */
1594 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1595 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1596 /* build bit 29, C */
1597 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1598 /* build bit 28, V */
1599 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1600 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1601 /* generate result */
1602 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1604 tcg_temp_free_i32(nzcv
);
1605 tcg_temp_free_i32(tmp
);
1608 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1611 TCGv_i32 nzcv
= tcg_temp_new_i32();
1613 /* take NZCV from R[t] */
1614 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1617 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1619 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1620 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1622 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1623 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1625 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1626 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1627 tcg_temp_free_i32(nzcv
);
1630 /* MRS - move from system register
1631 * MSR (register) - move to system register
1634 * These are all essentially the same insn in 'read' and 'write'
1635 * versions, with varying op0 fields.
1637 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1638 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1639 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1641 const ARMCPRegInfo
*ri
;
1644 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1645 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1646 crn
, crm
, op0
, op1
, op2
));
1649 /* Unknown register; this might be a guest error or a QEMU
1650 * unimplemented feature.
1652 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1653 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1654 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1655 unallocated_encoding(s
);
1659 /* Check access permissions */
1660 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1661 unallocated_encoding(s
);
1666 /* Emit code to perform further access permissions checks at
1667 * runtime; this may result in an exception.
1670 TCGv_i32 tcg_syn
, tcg_isread
;
1673 gen_a64_set_pc_im(s
->pc
- 4);
1674 tmpptr
= tcg_const_ptr(ri
);
1675 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1676 tcg_syn
= tcg_const_i32(syndrome
);
1677 tcg_isread
= tcg_const_i32(isread
);
1678 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1679 tcg_temp_free_ptr(tmpptr
);
1680 tcg_temp_free_i32(tcg_syn
);
1681 tcg_temp_free_i32(tcg_isread
);
1684 /* Handle special cases first */
1685 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1689 tcg_rt
= cpu_reg(s
, rt
);
1691 gen_get_nzcv(tcg_rt
);
1693 gen_set_nzcv(tcg_rt
);
1696 case ARM_CP_CURRENTEL
:
1697 /* Reads as current EL value from pstate, which is
1698 * guaranteed to be constant by the tb flags.
1700 tcg_rt
= cpu_reg(s
, rt
);
1701 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1704 /* Writes clear the aligned block of memory which rt points into. */
1705 tcg_rt
= cpu_reg(s
, rt
);
1706 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1711 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1713 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1717 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1721 tcg_rt
= cpu_reg(s
, rt
);
1724 if (ri
->type
& ARM_CP_CONST
) {
1725 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1726 } else if (ri
->readfn
) {
1728 tmpptr
= tcg_const_ptr(ri
);
1729 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1730 tcg_temp_free_ptr(tmpptr
);
1732 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1735 if (ri
->type
& ARM_CP_CONST
) {
1736 /* If not forbidden by access permissions, treat as WI */
1738 } else if (ri
->writefn
) {
1740 tmpptr
= tcg_const_ptr(ri
);
1741 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1742 tcg_temp_free_ptr(tmpptr
);
1744 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1748 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1749 /* I/O operations must end the TB here (whether read or write) */
1751 s
->base
.is_jmp
= DISAS_UPDATE
;
1752 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1753 /* We default to ending the TB on a coprocessor register write,
1754 * but allow this to be suppressed by the register definition
1755 * (usually only necessary to work around guest bugs).
1757 s
->base
.is_jmp
= DISAS_UPDATE
;
1762 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1763 * +---------------------+---+-----+-----+-------+-------+-----+------+
1764 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1765 * +---------------------+---+-----+-----+-------+-------+-----+------+
1767 static void disas_system(DisasContext
*s
, uint32_t insn
)
1769 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1770 l
= extract32(insn
, 21, 1);
1771 op0
= extract32(insn
, 19, 2);
1772 op1
= extract32(insn
, 16, 3);
1773 crn
= extract32(insn
, 12, 4);
1774 crm
= extract32(insn
, 8, 4);
1775 op2
= extract32(insn
, 5, 3);
1776 rt
= extract32(insn
, 0, 5);
1779 if (l
|| rt
!= 31) {
1780 unallocated_encoding(s
);
1784 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1785 handle_hint(s
, insn
, op1
, op2
, crm
);
1787 case 3: /* CLREX, DSB, DMB, ISB */
1788 handle_sync(s
, insn
, op1
, op2
, crm
);
1790 case 4: /* MSR (immediate) */
1791 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1794 unallocated_encoding(s
);
1799 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1802 /* Exception generation
1804 * 31 24 23 21 20 5 4 2 1 0
1805 * +-----------------+-----+------------------------+-----+----+
1806 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1807 * +-----------------------+------------------------+----------+
1809 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1811 int opc
= extract32(insn
, 21, 3);
1812 int op2_ll
= extract32(insn
, 0, 5);
1813 int imm16
= extract32(insn
, 5, 16);
1818 /* For SVC, HVC and SMC we advance the single-step state
1819 * machine before taking the exception. This is architecturally
1820 * mandated, to ensure that single-stepping a system call
1821 * instruction works properly.
1826 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1827 default_exception_el(s
));
1830 if (s
->current_el
== 0) {
1831 unallocated_encoding(s
);
1834 /* The pre HVC helper handles cases when HVC gets trapped
1835 * as an undefined insn by runtime configuration.
1837 gen_a64_set_pc_im(s
->pc
- 4);
1838 gen_helper_pre_hvc(cpu_env
);
1840 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1843 if (s
->current_el
== 0) {
1844 unallocated_encoding(s
);
1847 gen_a64_set_pc_im(s
->pc
- 4);
1848 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1849 gen_helper_pre_smc(cpu_env
, tmp
);
1850 tcg_temp_free_i32(tmp
);
1852 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1855 unallocated_encoding(s
);
1861 unallocated_encoding(s
);
1865 gen_exception_bkpt_insn(s
, 4, syn_aa64_bkpt(imm16
));
1869 unallocated_encoding(s
);
1872 /* HLT. This has two purposes.
1873 * Architecturally, it is an external halting debug instruction.
1874 * Since QEMU doesn't implement external debug, we treat this as
1875 * it is required for halting debug disabled: it will UNDEF.
1876 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1878 if (semihosting_enabled() && imm16
== 0xf000) {
1879 #ifndef CONFIG_USER_ONLY
1880 /* In system mode, don't allow userspace access to semihosting,
1881 * to provide some semblance of security (and for consistency
1882 * with our 32-bit semihosting).
1884 if (s
->current_el
== 0) {
1885 unsupported_encoding(s
, insn
);
1889 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1891 unsupported_encoding(s
, insn
);
1895 if (op2_ll
< 1 || op2_ll
> 3) {
1896 unallocated_encoding(s
);
1899 /* DCPS1, DCPS2, DCPS3 */
1900 unsupported_encoding(s
, insn
);
1903 unallocated_encoding(s
);
1908 /* Unconditional branch (register)
1909 * 31 25 24 21 20 16 15 10 9 5 4 0
1910 * +---------------+-------+-------+-------+------+-------+
1911 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1912 * +---------------+-------+-------+-------+------+-------+
1914 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1916 unsigned int opc
, op2
, op3
, rn
, op4
;
1918 opc
= extract32(insn
, 21, 4);
1919 op2
= extract32(insn
, 16, 5);
1920 op3
= extract32(insn
, 10, 6);
1921 rn
= extract32(insn
, 5, 5);
1922 op4
= extract32(insn
, 0, 5);
1924 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1925 unallocated_encoding(s
);
1933 gen_a64_set_pc(s
, cpu_reg(s
, rn
));
1934 /* BLR also needs to load return address */
1936 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1940 if (s
->current_el
== 0) {
1941 unallocated_encoding(s
);
1944 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
1947 gen_helper_exception_return(cpu_env
);
1948 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
1951 /* Must exit loop to check un-masked IRQs */
1952 s
->base
.is_jmp
= DISAS_EXIT
;
1956 unallocated_encoding(s
);
1958 unsupported_encoding(s
, insn
);
1962 unallocated_encoding(s
);
1966 s
->base
.is_jmp
= DISAS_JUMP
;
1969 /* Branches, exception generating and system instructions */
1970 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1972 switch (extract32(insn
, 25, 7)) {
1973 case 0x0a: case 0x0b:
1974 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1975 disas_uncond_b_imm(s
, insn
);
1977 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1978 disas_comp_b_imm(s
, insn
);
1980 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1981 disas_test_b_imm(s
, insn
);
1983 case 0x2a: /* Conditional branch (immediate) */
1984 disas_cond_b_imm(s
, insn
);
1986 case 0x6a: /* Exception generation / System */
1987 if (insn
& (1 << 24)) {
1988 disas_system(s
, insn
);
1993 case 0x6b: /* Unconditional branch (register) */
1994 disas_uncond_b_reg(s
, insn
);
1997 unallocated_encoding(s
);
2003 * Load/Store exclusive instructions are implemented by remembering
2004 * the value/address loaded, and seeing if these are the same
2005 * when the store is performed. This is not actually the architecturally
2006 * mandated semantics, but it works for typical guest code sequences
2007 * and avoids having to monitor regular stores.
2009 * The store exclusive uses the atomic cmpxchg primitives to avoid
2010 * races in multi-threaded linux-user and when MTTCG softmmu is
2013 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2014 TCGv_i64 addr
, int size
, bool is_pair
)
2016 int idx
= get_mem_index(s
);
2017 TCGMemOp memop
= s
->be_data
;
2019 g_assert(size
<= 3);
2021 g_assert(size
>= 2);
2023 /* The pair must be single-copy atomic for the doubleword. */
2024 memop
|= MO_64
| MO_ALIGN
;
2025 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2026 if (s
->be_data
== MO_LE
) {
2027 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2028 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2030 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2031 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2034 /* The pair must be single-copy atomic for *each* doubleword, not
2035 the entire quadword, however it must be quadword aligned. */
2037 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2038 memop
| MO_ALIGN_16
);
2040 TCGv_i64 addr2
= tcg_temp_new_i64();
2041 tcg_gen_addi_i64(addr2
, addr
, 8);
2042 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2043 tcg_temp_free_i64(addr2
);
2045 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2046 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2049 memop
|= size
| MO_ALIGN
;
2050 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2051 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2053 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2056 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2057 TCGv_i64 addr
, int size
, int is_pair
)
2059 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2060 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2063 * [addr + datasize] = {Rt2};
2069 * env->exclusive_addr = -1;
2071 TCGLabel
*fail_label
= gen_new_label();
2072 TCGLabel
*done_label
= gen_new_label();
2075 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2077 tmp
= tcg_temp_new_i64();
2080 if (s
->be_data
== MO_LE
) {
2081 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2083 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2085 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2086 cpu_exclusive_val
, tmp
,
2088 MO_64
| MO_ALIGN
| s
->be_data
);
2089 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2090 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2091 if (!HAVE_CMPXCHG128
) {
2092 gen_helper_exit_atomic(cpu_env
);
2093 s
->base
.is_jmp
= DISAS_NORETURN
;
2094 } else if (s
->be_data
== MO_LE
) {
2095 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2100 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2105 } else if (s
->be_data
== MO_LE
) {
2106 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2107 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2109 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2110 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2113 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2114 cpu_reg(s
, rt
), get_mem_index(s
),
2115 size
| MO_ALIGN
| s
->be_data
);
2116 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2118 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2119 tcg_temp_free_i64(tmp
);
2120 tcg_gen_br(done_label
);
2122 gen_set_label(fail_label
);
2123 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2124 gen_set_label(done_label
);
2125 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2128 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2131 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2132 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2133 int memidx
= get_mem_index(s
);
2134 TCGv_i64 addr
= cpu_reg_sp(s
, rn
);
2137 gen_check_sp_alignment(s
);
2139 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, addr
, tcg_rs
, tcg_rt
, memidx
,
2140 size
| MO_ALIGN
| s
->be_data
);
2143 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2146 TCGv_i64 s1
= cpu_reg(s
, rs
);
2147 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2148 TCGv_i64 t1
= cpu_reg(s
, rt
);
2149 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2150 TCGv_i64 addr
= cpu_reg_sp(s
, rn
);
2151 int memidx
= get_mem_index(s
);
2154 gen_check_sp_alignment(s
);
2158 TCGv_i64 cmp
= tcg_temp_new_i64();
2159 TCGv_i64 val
= tcg_temp_new_i64();
2161 if (s
->be_data
== MO_LE
) {
2162 tcg_gen_concat32_i64(val
, t1
, t2
);
2163 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2165 tcg_gen_concat32_i64(val
, t2
, t1
);
2166 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2169 tcg_gen_atomic_cmpxchg_i64(cmp
, addr
, cmp
, val
, memidx
,
2170 MO_64
| MO_ALIGN
| s
->be_data
);
2171 tcg_temp_free_i64(val
);
2173 if (s
->be_data
== MO_LE
) {
2174 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2176 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2178 tcg_temp_free_i64(cmp
);
2179 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2180 if (HAVE_CMPXCHG128
) {
2181 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2182 if (s
->be_data
== MO_LE
) {
2183 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
, addr
, t1
, t2
);
2185 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
, addr
, t1
, t2
);
2187 tcg_temp_free_i32(tcg_rs
);
2189 gen_helper_exit_atomic(cpu_env
);
2190 s
->base
.is_jmp
= DISAS_NORETURN
;
2193 TCGv_i64 d1
= tcg_temp_new_i64();
2194 TCGv_i64 d2
= tcg_temp_new_i64();
2195 TCGv_i64 a2
= tcg_temp_new_i64();
2196 TCGv_i64 c1
= tcg_temp_new_i64();
2197 TCGv_i64 c2
= tcg_temp_new_i64();
2198 TCGv_i64 zero
= tcg_const_i64(0);
2200 /* Load the two words, in memory order. */
2201 tcg_gen_qemu_ld_i64(d1
, addr
, memidx
,
2202 MO_64
| MO_ALIGN_16
| s
->be_data
);
2203 tcg_gen_addi_i64(a2
, addr
, 8);
2204 tcg_gen_qemu_ld_i64(d2
, addr
, memidx
, MO_64
| s
->be_data
);
2206 /* Compare the two words, also in memory order. */
2207 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2208 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2209 tcg_gen_and_i64(c2
, c2
, c1
);
2211 /* If compare equal, write back new data, else write back old data. */
2212 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2213 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2214 tcg_gen_qemu_st_i64(c1
, addr
, memidx
, MO_64
| s
->be_data
);
2215 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2216 tcg_temp_free_i64(a2
);
2217 tcg_temp_free_i64(c1
);
2218 tcg_temp_free_i64(c2
);
2219 tcg_temp_free_i64(zero
);
2221 /* Write back the data from memory to Rs. */
2222 tcg_gen_mov_i64(s1
, d1
);
2223 tcg_gen_mov_i64(s2
, d2
);
2224 tcg_temp_free_i64(d1
);
2225 tcg_temp_free_i64(d2
);
2229 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2230 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2232 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2234 int opc0
= extract32(opc
, 0, 1);
2238 regsize
= opc0
? 32 : 64;
2240 regsize
= size
== 3 ? 64 : 32;
2242 return regsize
== 64;
2245 /* Load/store exclusive
2247 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2248 * +-----+-------------+----+---+----+------+----+-------+------+------+
2249 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2250 * +-----+-------------+----+---+----+------+----+-------+------+------+
2252 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2253 * L: 0 -> store, 1 -> load
2254 * o2: 0 -> exclusive, 1 -> not
2255 * o1: 0 -> single register, 1 -> register pair
2256 * o0: 1 -> load-acquire/store-release, 0 -> not
2258 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2260 int rt
= extract32(insn
, 0, 5);
2261 int rn
= extract32(insn
, 5, 5);
2262 int rt2
= extract32(insn
, 10, 5);
2263 int rs
= extract32(insn
, 16, 5);
2264 int is_lasr
= extract32(insn
, 15, 1);
2265 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2266 int size
= extract32(insn
, 30, 2);
2269 switch (o2_L_o1_o0
) {
2270 case 0x0: /* STXR */
2271 case 0x1: /* STLXR */
2273 gen_check_sp_alignment(s
);
2276 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2278 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2279 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, false);
2282 case 0x4: /* LDXR */
2283 case 0x5: /* LDAXR */
2285 gen_check_sp_alignment(s
);
2287 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2289 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, false);
2291 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2295 case 0x9: /* STLR */
2296 /* Generate ISS for non-exclusive accesses including LASR. */
2298 gen_check_sp_alignment(s
);
2300 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2301 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2302 do_gpr_st(s
, cpu_reg(s
, rt
), tcg_addr
, size
, true, rt
,
2303 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2306 case 0xd: /* LDAR */
2307 /* Generate ISS for non-exclusive accesses including LASR. */
2309 gen_check_sp_alignment(s
);
2311 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2312 do_gpr_ld(s
, cpu_reg(s
, rt
), tcg_addr
, size
, false, false, true, rt
,
2313 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2314 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2317 case 0x2: case 0x3: /* CASP / STXP */
2318 if (size
& 2) { /* STXP / STLXP */
2320 gen_check_sp_alignment(s
);
2323 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2325 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2326 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, true);
2330 && ((rt
| rs
) & 1) == 0
2331 && dc_isar_feature(aa64_atomics
, s
)) {
2333 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2338 case 0x6: case 0x7: /* CASPA / LDXP */
2339 if (size
& 2) { /* LDXP / LDAXP */
2341 gen_check_sp_alignment(s
);
2343 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2345 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, true);
2347 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2352 && ((rt
| rs
) & 1) == 0
2353 && dc_isar_feature(aa64_atomics
, s
)) {
2354 /* CASPA / CASPAL */
2355 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2361 case 0xb: /* CASL */
2362 case 0xe: /* CASA */
2363 case 0xf: /* CASAL */
2364 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2365 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2370 unallocated_encoding(s
);
2374 * Load register (literal)
2376 * 31 30 29 27 26 25 24 23 5 4 0
2377 * +-----+-------+---+-----+-------------------+-------+
2378 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2379 * +-----+-------+---+-----+-------------------+-------+
2381 * V: 1 -> vector (simd/fp)
2382 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2383 * 10-> 32 bit signed, 11 -> prefetch
2384 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2386 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2388 int rt
= extract32(insn
, 0, 5);
2389 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2390 bool is_vector
= extract32(insn
, 26, 1);
2391 int opc
= extract32(insn
, 30, 2);
2392 bool is_signed
= false;
2394 TCGv_i64 tcg_rt
, tcg_addr
;
2398 unallocated_encoding(s
);
2402 if (!fp_access_check(s
)) {
2407 /* PRFM (literal) : prefetch */
2410 size
= 2 + extract32(opc
, 0, 1);
2411 is_signed
= extract32(opc
, 1, 1);
2414 tcg_rt
= cpu_reg(s
, rt
);
2416 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2418 do_fp_ld(s
, rt
, tcg_addr
, size
);
2420 /* Only unsigned 32bit loads target 32bit registers. */
2421 bool iss_sf
= opc
!= 0;
2423 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2424 true, rt
, iss_sf
, false);
2426 tcg_temp_free_i64(tcg_addr
);
2430 * LDNP (Load Pair - non-temporal hint)
2431 * LDP (Load Pair - non vector)
2432 * LDPSW (Load Pair Signed Word - non vector)
2433 * STNP (Store Pair - non-temporal hint)
2434 * STP (Store Pair - non vector)
2435 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2436 * LDP (Load Pair of SIMD&FP)
2437 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2438 * STP (Store Pair of SIMD&FP)
2440 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2441 * +-----+-------+---+---+-------+---+-----------------------------+
2442 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2443 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2445 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2447 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2448 * V: 0 -> GPR, 1 -> Vector
2449 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2450 * 10 -> signed offset, 11 -> pre-index
2451 * L: 0 -> Store 1 -> Load
2453 * Rt, Rt2 = GPR or SIMD registers to be stored
2454 * Rn = general purpose register containing address
2455 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2457 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2459 int rt
= extract32(insn
, 0, 5);
2460 int rn
= extract32(insn
, 5, 5);
2461 int rt2
= extract32(insn
, 10, 5);
2462 uint64_t offset
= sextract64(insn
, 15, 7);
2463 int index
= extract32(insn
, 23, 2);
2464 bool is_vector
= extract32(insn
, 26, 1);
2465 bool is_load
= extract32(insn
, 22, 1);
2466 int opc
= extract32(insn
, 30, 2);
2468 bool is_signed
= false;
2469 bool postindex
= false;
2472 TCGv_i64 tcg_addr
; /* calculated address */
2476 unallocated_encoding(s
);
2483 size
= 2 + extract32(opc
, 1, 1);
2484 is_signed
= extract32(opc
, 0, 1);
2485 if (!is_load
&& is_signed
) {
2486 unallocated_encoding(s
);
2492 case 1: /* post-index */
2497 /* signed offset with "non-temporal" hint. Since we don't emulate
2498 * caches we don't care about hints to the cache system about
2499 * data access patterns, and handle this identically to plain
2503 /* There is no non-temporal-hint version of LDPSW */
2504 unallocated_encoding(s
);
2509 case 2: /* signed offset, rn not updated */
2512 case 3: /* pre-index */
2518 if (is_vector
&& !fp_access_check(s
)) {
2525 gen_check_sp_alignment(s
);
2528 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2531 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2536 do_fp_ld(s
, rt
, tcg_addr
, size
);
2538 do_fp_st(s
, rt
, tcg_addr
, size
);
2540 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2542 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2544 do_fp_st(s
, rt2
, tcg_addr
, size
);
2547 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2548 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2551 TCGv_i64 tmp
= tcg_temp_new_i64();
2553 /* Do not modify tcg_rt before recognizing any exception
2554 * from the second load.
2556 do_gpr_ld(s
, tmp
, tcg_addr
, size
, is_signed
, false,
2557 false, 0, false, false);
2558 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2559 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2560 false, 0, false, false);
2562 tcg_gen_mov_i64(tcg_rt
, tmp
);
2563 tcg_temp_free_i64(tmp
);
2565 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2566 false, 0, false, false);
2567 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2568 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2569 false, 0, false, false);
2575 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2577 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2579 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2584 * Load/store (immediate post-indexed)
2585 * Load/store (immediate pre-indexed)
2586 * Load/store (unscaled immediate)
2588 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2589 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2590 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2591 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2593 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2595 * V = 0 -> non-vector
2596 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2597 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2599 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2605 int rn
= extract32(insn
, 5, 5);
2606 int imm9
= sextract32(insn
, 12, 9);
2607 int idx
= extract32(insn
, 10, 2);
2608 bool is_signed
= false;
2609 bool is_store
= false;
2610 bool is_extended
= false;
2611 bool is_unpriv
= (idx
== 2);
2612 bool iss_valid
= !is_vector
;
2619 size
|= (opc
& 2) << 1;
2620 if (size
> 4 || is_unpriv
) {
2621 unallocated_encoding(s
);
2624 is_store
= ((opc
& 1) == 0);
2625 if (!fp_access_check(s
)) {
2629 if (size
== 3 && opc
== 2) {
2630 /* PRFM - prefetch */
2632 unallocated_encoding(s
);
2637 if (opc
== 3 && size
> 1) {
2638 unallocated_encoding(s
);
2641 is_store
= (opc
== 0);
2642 is_signed
= extract32(opc
, 1, 1);
2643 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2661 g_assert_not_reached();
2665 gen_check_sp_alignment(s
);
2667 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2670 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2675 do_fp_st(s
, rt
, tcg_addr
, size
);
2677 do_fp_ld(s
, rt
, tcg_addr
, size
);
2680 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2681 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2682 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2685 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2686 iss_valid
, rt
, iss_sf
, false);
2688 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2689 is_signed
, is_extended
, memidx
,
2690 iss_valid
, rt
, iss_sf
, false);
2695 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2697 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2699 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2704 * Load/store (register offset)
2706 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2707 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2708 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2709 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2712 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2713 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2715 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2716 * opc<0>: 0 -> store, 1 -> load
2717 * V: 1 -> vector/simd
2718 * opt: extend encoding (see DecodeRegExtend)
2719 * S: if S=1 then scale (essentially index by sizeof(size))
2720 * Rt: register to transfer into/out of
2721 * Rn: address register or SP for base
2722 * Rm: offset register or ZR for offset
2724 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2730 int rn
= extract32(insn
, 5, 5);
2731 int shift
= extract32(insn
, 12, 1);
2732 int rm
= extract32(insn
, 16, 5);
2733 int opt
= extract32(insn
, 13, 3);
2734 bool is_signed
= false;
2735 bool is_store
= false;
2736 bool is_extended
= false;
2741 if (extract32(opt
, 1, 1) == 0) {
2742 unallocated_encoding(s
);
2747 size
|= (opc
& 2) << 1;
2749 unallocated_encoding(s
);
2752 is_store
= !extract32(opc
, 0, 1);
2753 if (!fp_access_check(s
)) {
2757 if (size
== 3 && opc
== 2) {
2758 /* PRFM - prefetch */
2761 if (opc
== 3 && size
> 1) {
2762 unallocated_encoding(s
);
2765 is_store
= (opc
== 0);
2766 is_signed
= extract32(opc
, 1, 1);
2767 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2771 gen_check_sp_alignment(s
);
2773 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2775 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2776 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2778 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2782 do_fp_st(s
, rt
, tcg_addr
, size
);
2784 do_fp_ld(s
, rt
, tcg_addr
, size
);
2787 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2788 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2790 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2791 true, rt
, iss_sf
, false);
2793 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2794 is_signed
, is_extended
,
2795 true, rt
, iss_sf
, false);
2801 * Load/store (unsigned immediate)
2803 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2804 * +----+-------+---+-----+-----+------------+-------+------+
2805 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2806 * +----+-------+---+-----+-----+------------+-------+------+
2809 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2810 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2812 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2813 * opc<0>: 0 -> store, 1 -> load
2814 * Rn: base address register (inc SP)
2815 * Rt: target register
2817 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2823 int rn
= extract32(insn
, 5, 5);
2824 unsigned int imm12
= extract32(insn
, 10, 12);
2825 unsigned int offset
;
2830 bool is_signed
= false;
2831 bool is_extended
= false;
2834 size
|= (opc
& 2) << 1;
2836 unallocated_encoding(s
);
2839 is_store
= !extract32(opc
, 0, 1);
2840 if (!fp_access_check(s
)) {
2844 if (size
== 3 && opc
== 2) {
2845 /* PRFM - prefetch */
2848 if (opc
== 3 && size
> 1) {
2849 unallocated_encoding(s
);
2852 is_store
= (opc
== 0);
2853 is_signed
= extract32(opc
, 1, 1);
2854 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2858 gen_check_sp_alignment(s
);
2860 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2861 offset
= imm12
<< size
;
2862 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2866 do_fp_st(s
, rt
, tcg_addr
, size
);
2868 do_fp_ld(s
, rt
, tcg_addr
, size
);
2871 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2872 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2874 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2875 true, rt
, iss_sf
, false);
2877 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
2878 true, rt
, iss_sf
, false);
2883 /* Atomic memory operations
2885 * 31 30 27 26 24 22 21 16 15 12 10 5 0
2886 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
2887 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
2888 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
2890 * Rt: the result register
2891 * Rn: base address or SP
2892 * Rs: the source register for the operation
2893 * V: vector flag (always 0 as of v8.3)
2897 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
2898 int size
, int rt
, bool is_vector
)
2900 int rs
= extract32(insn
, 16, 5);
2901 int rn
= extract32(insn
, 5, 5);
2902 int o3_opc
= extract32(insn
, 12, 4);
2903 TCGv_i64 tcg_rn
, tcg_rs
;
2904 AtomicThreeOpFn
*fn
;
2906 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
2907 unallocated_encoding(s
);
2911 case 000: /* LDADD */
2912 fn
= tcg_gen_atomic_fetch_add_i64
;
2914 case 001: /* LDCLR */
2915 fn
= tcg_gen_atomic_fetch_and_i64
;
2917 case 002: /* LDEOR */
2918 fn
= tcg_gen_atomic_fetch_xor_i64
;
2920 case 003: /* LDSET */
2921 fn
= tcg_gen_atomic_fetch_or_i64
;
2923 case 004: /* LDSMAX */
2924 fn
= tcg_gen_atomic_fetch_smax_i64
;
2926 case 005: /* LDSMIN */
2927 fn
= tcg_gen_atomic_fetch_smin_i64
;
2929 case 006: /* LDUMAX */
2930 fn
= tcg_gen_atomic_fetch_umax_i64
;
2932 case 007: /* LDUMIN */
2933 fn
= tcg_gen_atomic_fetch_umin_i64
;
2936 fn
= tcg_gen_atomic_xchg_i64
;
2939 unallocated_encoding(s
);
2944 gen_check_sp_alignment(s
);
2946 tcg_rn
= cpu_reg_sp(s
, rn
);
2947 tcg_rs
= read_cpu_reg(s
, rs
, true);
2949 if (o3_opc
== 1) { /* LDCLR */
2950 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
2953 /* The tcg atomic primitives are all full barriers. Therefore we
2954 * can ignore the Acquire and Release bits of this instruction.
2956 fn(cpu_reg(s
, rt
), tcg_rn
, tcg_rs
, get_mem_index(s
),
2957 s
->be_data
| size
| MO_ALIGN
);
2960 /* Load/store register (all forms) */
2961 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2963 int rt
= extract32(insn
, 0, 5);
2964 int opc
= extract32(insn
, 22, 2);
2965 bool is_vector
= extract32(insn
, 26, 1);
2966 int size
= extract32(insn
, 30, 2);
2968 switch (extract32(insn
, 24, 2)) {
2970 if (extract32(insn
, 21, 1) == 0) {
2971 /* Load/store register (unscaled immediate)
2972 * Load/store immediate pre/post-indexed
2973 * Load/store register unprivileged
2975 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2978 switch (extract32(insn
, 10, 2)) {
2980 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
2983 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2988 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
2991 unallocated_encoding(s
);
2994 /* AdvSIMD load/store multiple structures
2996 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2997 * +---+---+---------------+---+-------------+--------+------+------+------+
2998 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2999 * +---+---+---------------+---+-------------+--------+------+------+------+
3001 * AdvSIMD load/store multiple structures (post-indexed)
3003 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3004 * +---+---+---------------+---+---+---------+--------+------+------+------+
3005 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3006 * +---+---+---------------+---+---+---------+--------+------+------+------+
3008 * Rt: first (or only) SIMD&FP register to be transferred
3009 * Rn: base address or SP
3010 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3012 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3014 int rt
= extract32(insn
, 0, 5);
3015 int rn
= extract32(insn
, 5, 5);
3016 int size
= extract32(insn
, 10, 2);
3017 int opcode
= extract32(insn
, 12, 4);
3018 bool is_store
= !extract32(insn
, 22, 1);
3019 bool is_postidx
= extract32(insn
, 23, 1);
3020 bool is_q
= extract32(insn
, 30, 1);
3021 TCGv_i64 tcg_addr
, tcg_rn
, tcg_ebytes
;
3023 int ebytes
= 1 << size
;
3024 int elements
= (is_q
? 128 : 64) / (8 << size
);
3025 int rpt
; /* num iterations */
3026 int selem
; /* structure elements */
3029 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3030 unallocated_encoding(s
);
3034 /* From the shared decode logic */
3065 unallocated_encoding(s
);
3069 if (size
== 3 && !is_q
&& selem
!= 1) {
3071 unallocated_encoding(s
);
3075 if (!fp_access_check(s
)) {
3080 gen_check_sp_alignment(s
);
3083 tcg_rn
= cpu_reg_sp(s
, rn
);
3084 tcg_addr
= tcg_temp_new_i64();
3085 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
3086 tcg_ebytes
= tcg_const_i64(ebytes
);
3088 for (r
= 0; r
< rpt
; r
++) {
3090 for (e
= 0; e
< elements
; e
++) {
3091 int tt
= (rt
+ r
) % 32;
3093 for (xs
= 0; xs
< selem
; xs
++) {
3095 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
3097 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
3099 /* For non-quad operations, setting a slice of the low
3100 * 64 bits of the register clears the high 64 bits (in
3101 * the ARM ARM pseudocode this is implicit in the fact
3102 * that 'rval' is a 64 bit wide variable).
3103 * For quad operations, we might still need to zero the
3104 * high bits of SVE. We optimize by noticing that we only
3105 * need to do this the first time we touch a register.
3107 if (e
== 0 && (r
== 0 || xs
== selem
- 1)) {
3108 clear_vec_high(s
, is_q
, tt
);
3111 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_ebytes
);
3118 int rm
= extract32(insn
, 16, 5);
3120 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
3122 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3125 tcg_temp_free_i64(tcg_ebytes
);
3126 tcg_temp_free_i64(tcg_addr
);
3129 /* AdvSIMD load/store single structure
3131 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3132 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3133 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3134 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3136 * AdvSIMD load/store single structure (post-indexed)
3138 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3139 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3140 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3141 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3143 * Rt: first (or only) SIMD&FP register to be transferred
3144 * Rn: base address or SP
3145 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3146 * index = encoded in Q:S:size dependent on size
3148 * lane_size = encoded in R, opc
3149 * transfer width = encoded in opc, S, size
3151 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3153 int rt
= extract32(insn
, 0, 5);
3154 int rn
= extract32(insn
, 5, 5);
3155 int size
= extract32(insn
, 10, 2);
3156 int S
= extract32(insn
, 12, 1);
3157 int opc
= extract32(insn
, 13, 3);
3158 int R
= extract32(insn
, 21, 1);
3159 int is_load
= extract32(insn
, 22, 1);
3160 int is_postidx
= extract32(insn
, 23, 1);
3161 int is_q
= extract32(insn
, 30, 1);
3163 int scale
= extract32(opc
, 1, 2);
3164 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3165 bool replicate
= false;
3166 int index
= is_q
<< 3 | S
<< 2 | size
;
3168 TCGv_i64 tcg_addr
, tcg_rn
, tcg_ebytes
;
3172 if (!is_load
|| S
) {
3173 unallocated_encoding(s
);
3182 if (extract32(size
, 0, 1)) {
3183 unallocated_encoding(s
);
3189 if (extract32(size
, 1, 1)) {
3190 unallocated_encoding(s
);
3193 if (!extract32(size
, 0, 1)) {
3197 unallocated_encoding(s
);
3205 g_assert_not_reached();
3208 if (!fp_access_check(s
)) {
3212 ebytes
= 1 << scale
;
3215 gen_check_sp_alignment(s
);
3218 tcg_rn
= cpu_reg_sp(s
, rn
);
3219 tcg_addr
= tcg_temp_new_i64();
3220 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
3221 tcg_ebytes
= tcg_const_i64(ebytes
);
3223 for (xs
= 0; xs
< selem
; xs
++) {
3225 /* Load and replicate to all elements */
3226 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3228 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
3229 get_mem_index(s
), s
->be_data
+ scale
);
3230 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3231 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3233 tcg_temp_free_i64(tcg_tmp
);
3235 /* Load/store one element per register */
3237 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
);
3239 do_vec_st(s
, rt
, index
, tcg_addr
, scale
);
3242 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_ebytes
);
3247 int rm
= extract32(insn
, 16, 5);
3249 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
3251 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3254 tcg_temp_free_i64(tcg_ebytes
);
3255 tcg_temp_free_i64(tcg_addr
);
3258 /* Loads and stores */
3259 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3261 switch (extract32(insn
, 24, 6)) {
3262 case 0x08: /* Load/store exclusive */
3263 disas_ldst_excl(s
, insn
);
3265 case 0x18: case 0x1c: /* Load register (literal) */
3266 disas_ld_lit(s
, insn
);
3268 case 0x28: case 0x29:
3269 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3270 disas_ldst_pair(s
, insn
);
3272 case 0x38: case 0x39:
3273 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3274 disas_ldst_reg(s
, insn
);
3276 case 0x0c: /* AdvSIMD load/store multiple structures */
3277 disas_ldst_multiple_struct(s
, insn
);
3279 case 0x0d: /* AdvSIMD load/store single structure */
3280 disas_ldst_single_struct(s
, insn
);
3283 unallocated_encoding(s
);
3288 /* PC-rel. addressing
3289 * 31 30 29 28 24 23 5 4 0
3290 * +----+-------+-----------+-------------------+------+
3291 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3292 * +----+-------+-----------+-------------------+------+
3294 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3296 unsigned int page
, rd
;
3300 page
= extract32(insn
, 31, 1);
3301 /* SignExtend(immhi:immlo) -> offset */
3302 offset
= sextract64(insn
, 5, 19);
3303 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3304 rd
= extract32(insn
, 0, 5);
3308 /* ADRP (page based) */
3313 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3317 * Add/subtract (immediate)
3319 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3320 * +--+--+--+-----------+-----+-------------+-----+-----+
3321 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3322 * +--+--+--+-----------+-----+-------------+-----+-----+
3324 * sf: 0 -> 32bit, 1 -> 64bit
3325 * op: 0 -> add , 1 -> sub
3327 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3329 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3331 int rd
= extract32(insn
, 0, 5);
3332 int rn
= extract32(insn
, 5, 5);
3333 uint64_t imm
= extract32(insn
, 10, 12);
3334 int shift
= extract32(insn
, 22, 2);
3335 bool setflags
= extract32(insn
, 29, 1);
3336 bool sub_op
= extract32(insn
, 30, 1);
3337 bool is_64bit
= extract32(insn
, 31, 1);
3339 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3340 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3341 TCGv_i64 tcg_result
;
3350 unallocated_encoding(s
);
3354 tcg_result
= tcg_temp_new_i64();
3357 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3359 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3362 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3364 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3366 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3368 tcg_temp_free_i64(tcg_imm
);
3372 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3374 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3377 tcg_temp_free_i64(tcg_result
);
3380 /* The input should be a value in the bottom e bits (with higher
3381 * bits zero); returns that value replicated into every element
3382 * of size e in a 64 bit integer.
3384 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3394 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3395 static inline uint64_t bitmask64(unsigned int length
)
3397 assert(length
> 0 && length
<= 64);
3398 return ~0ULL >> (64 - length
);
3401 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3402 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3403 * value (ie should cause a guest UNDEF exception), and true if they are
3404 * valid, in which case the decoded bit pattern is written to result.
3406 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3407 unsigned int imms
, unsigned int immr
)
3410 unsigned e
, levels
, s
, r
;
3413 assert(immn
< 2 && imms
< 64 && immr
< 64);
3415 /* The bit patterns we create here are 64 bit patterns which
3416 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3417 * 64 bits each. Each element contains the same value: a run
3418 * of between 1 and e-1 non-zero bits, rotated within the
3419 * element by between 0 and e-1 bits.
3421 * The element size and run length are encoded into immn (1 bit)
3422 * and imms (6 bits) as follows:
3423 * 64 bit elements: immn = 1, imms = <length of run - 1>
3424 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3425 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3426 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3427 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3428 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3429 * Notice that immn = 0, imms = 11111x is the only combination
3430 * not covered by one of the above options; this is reserved.
3431 * Further, <length of run - 1> all-ones is a reserved pattern.
3433 * In all cases the rotation is by immr % e (and immr is 6 bits).
3436 /* First determine the element size */
3437 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3439 /* This is the immn == 0, imms == 0x11111x case */
3449 /* <length of run - 1> mustn't be all-ones. */
3453 /* Create the value of one element: s+1 set bits rotated
3454 * by r within the element (which is e bits wide)...
3456 mask
= bitmask64(s
+ 1);
3458 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3459 mask
&= bitmask64(e
);
3461 /* ...then replicate the element over the whole 64 bit value */
3462 mask
= bitfield_replicate(mask
, e
);
3467 /* Logical (immediate)
3468 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3469 * +----+-----+-------------+---+------+------+------+------+
3470 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3471 * +----+-----+-------------+---+------+------+------+------+
3473 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3475 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3476 TCGv_i64 tcg_rd
, tcg_rn
;
3478 bool is_and
= false;
3480 sf
= extract32(insn
, 31, 1);
3481 opc
= extract32(insn
, 29, 2);
3482 is_n
= extract32(insn
, 22, 1);
3483 immr
= extract32(insn
, 16, 6);
3484 imms
= extract32(insn
, 10, 6);
3485 rn
= extract32(insn
, 5, 5);
3486 rd
= extract32(insn
, 0, 5);
3489 unallocated_encoding(s
);
3493 if (opc
== 0x3) { /* ANDS */
3494 tcg_rd
= cpu_reg(s
, rd
);
3496 tcg_rd
= cpu_reg_sp(s
, rd
);
3498 tcg_rn
= cpu_reg(s
, rn
);
3500 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3501 /* some immediate field values are reserved */
3502 unallocated_encoding(s
);
3507 wmask
&= 0xffffffff;
3511 case 0x3: /* ANDS */
3513 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3517 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3520 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3523 assert(FALSE
); /* must handle all above */
3527 if (!sf
&& !is_and
) {
3528 /* zero extend final result; we know we can skip this for AND
3529 * since the immediate had the high 32 bits clear.
3531 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3534 if (opc
== 3) { /* ANDS */
3535 gen_logic_CC(sf
, tcg_rd
);
3540 * Move wide (immediate)
3542 * 31 30 29 28 23 22 21 20 5 4 0
3543 * +--+-----+-------------+-----+----------------+------+
3544 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3545 * +--+-----+-------------+-----+----------------+------+
3547 * sf: 0 -> 32 bit, 1 -> 64 bit
3548 * opc: 00 -> N, 10 -> Z, 11 -> K
3549 * hw: shift/16 (0,16, and sf only 32, 48)
3551 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3553 int rd
= extract32(insn
, 0, 5);
3554 uint64_t imm
= extract32(insn
, 5, 16);
3555 int sf
= extract32(insn
, 31, 1);
3556 int opc
= extract32(insn
, 29, 2);
3557 int pos
= extract32(insn
, 21, 2) << 4;
3558 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3561 if (!sf
&& (pos
>= 32)) {
3562 unallocated_encoding(s
);
3576 tcg_gen_movi_i64(tcg_rd
, imm
);
3579 tcg_imm
= tcg_const_i64(imm
);
3580 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3581 tcg_temp_free_i64(tcg_imm
);
3583 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3587 unallocated_encoding(s
);
3593 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3594 * +----+-----+-------------+---+------+------+------+------+
3595 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3596 * +----+-----+-------------+---+------+------+------+------+
3598 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3600 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3601 TCGv_i64 tcg_rd
, tcg_tmp
;
3603 sf
= extract32(insn
, 31, 1);
3604 opc
= extract32(insn
, 29, 2);
3605 n
= extract32(insn
, 22, 1);
3606 ri
= extract32(insn
, 16, 6);
3607 si
= extract32(insn
, 10, 6);
3608 rn
= extract32(insn
, 5, 5);
3609 rd
= extract32(insn
, 0, 5);
3610 bitsize
= sf
? 64 : 32;
3612 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3613 unallocated_encoding(s
);
3617 tcg_rd
= cpu_reg(s
, rd
);
3619 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3620 to be smaller than bitsize, we'll never reference data outside the
3621 low 32-bits anyway. */
3622 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3624 /* Recognize simple(r) extractions. */
3626 /* Wd<s-r:0> = Wn<s:r> */
3627 len
= (si
- ri
) + 1;
3628 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3629 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3631 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3632 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3635 /* opc == 1, BXFIL fall through to deposit */
3636 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3639 /* Handle the ri > si case with a deposit
3640 * Wd<32+s-r,32-r> = Wn<s:0>
3643 pos
= (bitsize
- ri
) & (bitsize
- 1);
3646 if (opc
== 0 && len
< ri
) {
3647 /* SBFM: sign extend the destination field from len to fill
3648 the balance of the word. Let the deposit below insert all
3649 of those sign bits. */
3650 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3654 if (opc
== 1) { /* BFM, BXFIL */
3655 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3657 /* SBFM or UBFM: We start with zero, and we haven't modified
3658 any bits outside bitsize, therefore the zero-extension
3659 below is unneeded. */
3660 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3665 if (!sf
) { /* zero extend final result */
3666 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3671 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3672 * +----+------+-------------+---+----+------+--------+------+------+
3673 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3674 * +----+------+-------------+---+----+------+--------+------+------+
3676 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3678 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3680 sf
= extract32(insn
, 31, 1);
3681 n
= extract32(insn
, 22, 1);
3682 rm
= extract32(insn
, 16, 5);
3683 imm
= extract32(insn
, 10, 6);
3684 rn
= extract32(insn
, 5, 5);
3685 rd
= extract32(insn
, 0, 5);
3686 op21
= extract32(insn
, 29, 2);
3687 op0
= extract32(insn
, 21, 1);
3688 bitsize
= sf
? 64 : 32;
3690 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3691 unallocated_encoding(s
);
3693 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3695 tcg_rd
= cpu_reg(s
, rd
);
3697 if (unlikely(imm
== 0)) {
3698 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3699 * so an extract from bit 0 is a special case.
3702 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3704 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3706 } else if (rm
== rn
) { /* ROR */
3707 tcg_rm
= cpu_reg(s
, rm
);
3709 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3711 TCGv_i32 tmp
= tcg_temp_new_i32();
3712 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3713 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3714 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3715 tcg_temp_free_i32(tmp
);
3718 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3719 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3720 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3721 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3722 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3724 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3730 /* Data processing - immediate */
3731 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3733 switch (extract32(insn
, 23, 6)) {
3734 case 0x20: case 0x21: /* PC-rel. addressing */
3735 disas_pc_rel_adr(s
, insn
);
3737 case 0x22: case 0x23: /* Add/subtract (immediate) */
3738 disas_add_sub_imm(s
, insn
);
3740 case 0x24: /* Logical (immediate) */
3741 disas_logic_imm(s
, insn
);
3743 case 0x25: /* Move wide (immediate) */
3744 disas_movw_imm(s
, insn
);
3746 case 0x26: /* Bitfield */
3747 disas_bitfield(s
, insn
);
3749 case 0x27: /* Extract */
3750 disas_extract(s
, insn
);
3753 unallocated_encoding(s
);
3758 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3759 * Note that it is the caller's responsibility to ensure that the
3760 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3761 * mandated semantics for out of range shifts.
3763 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3764 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3766 switch (shift_type
) {
3767 case A64_SHIFT_TYPE_LSL
:
3768 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3770 case A64_SHIFT_TYPE_LSR
:
3771 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3773 case A64_SHIFT_TYPE_ASR
:
3775 tcg_gen_ext32s_i64(dst
, src
);
3777 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3779 case A64_SHIFT_TYPE_ROR
:
3781 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3784 t0
= tcg_temp_new_i32();
3785 t1
= tcg_temp_new_i32();
3786 tcg_gen_extrl_i64_i32(t0
, src
);
3787 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3788 tcg_gen_rotr_i32(t0
, t0
, t1
);
3789 tcg_gen_extu_i32_i64(dst
, t0
);
3790 tcg_temp_free_i32(t0
);
3791 tcg_temp_free_i32(t1
);
3795 assert(FALSE
); /* all shift types should be handled */
3799 if (!sf
) { /* zero extend final result */
3800 tcg_gen_ext32u_i64(dst
, dst
);
3804 /* Shift a TCGv src by immediate, put result in dst.
3805 * The shift amount must be in range (this should always be true as the
3806 * relevant instructions will UNDEF on bad shift immediates).
3808 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3809 enum a64_shift_type shift_type
, unsigned int shift_i
)
3811 assert(shift_i
< (sf
? 64 : 32));
3814 tcg_gen_mov_i64(dst
, src
);
3816 TCGv_i64 shift_const
;
3818 shift_const
= tcg_const_i64(shift_i
);
3819 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3820 tcg_temp_free_i64(shift_const
);
3824 /* Logical (shifted register)
3825 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3826 * +----+-----+-----------+-------+---+------+--------+------+------+
3827 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3828 * +----+-----+-----------+-------+---+------+--------+------+------+
3830 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3832 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3833 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3835 sf
= extract32(insn
, 31, 1);
3836 opc
= extract32(insn
, 29, 2);
3837 shift_type
= extract32(insn
, 22, 2);
3838 invert
= extract32(insn
, 21, 1);
3839 rm
= extract32(insn
, 16, 5);
3840 shift_amount
= extract32(insn
, 10, 6);
3841 rn
= extract32(insn
, 5, 5);
3842 rd
= extract32(insn
, 0, 5);
3844 if (!sf
&& (shift_amount
& (1 << 5))) {
3845 unallocated_encoding(s
);
3849 tcg_rd
= cpu_reg(s
, rd
);
3851 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3852 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3853 * register-register MOV and MVN, so it is worth special casing.
3855 tcg_rm
= cpu_reg(s
, rm
);
3857 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3859 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3863 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3865 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3871 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3874 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3877 tcg_rn
= cpu_reg(s
, rn
);
3879 switch (opc
| (invert
<< 2)) {
3882 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3885 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3888 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3892 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3895 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3898 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3906 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3910 gen_logic_CC(sf
, tcg_rd
);
3915 * Add/subtract (extended register)
3917 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3918 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3919 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3920 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3922 * sf: 0 -> 32bit, 1 -> 64bit
3923 * op: 0 -> add , 1 -> sub
3926 * option: extension type (see DecodeRegExtend)
3927 * imm3: optional shift to Rm
3929 * Rd = Rn + LSL(extend(Rm), amount)
3931 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3933 int rd
= extract32(insn
, 0, 5);
3934 int rn
= extract32(insn
, 5, 5);
3935 int imm3
= extract32(insn
, 10, 3);
3936 int option
= extract32(insn
, 13, 3);
3937 int rm
= extract32(insn
, 16, 5);
3938 bool setflags
= extract32(insn
, 29, 1);
3939 bool sub_op
= extract32(insn
, 30, 1);
3940 bool sf
= extract32(insn
, 31, 1);
3942 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3944 TCGv_i64 tcg_result
;
3947 unallocated_encoding(s
);
3951 /* non-flag setting ops may use SP */
3953 tcg_rd
= cpu_reg_sp(s
, rd
);
3955 tcg_rd
= cpu_reg(s
, rd
);
3957 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3959 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3960 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3962 tcg_result
= tcg_temp_new_i64();
3966 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3968 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3972 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3974 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3979 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3981 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3984 tcg_temp_free_i64(tcg_result
);
3988 * Add/subtract (shifted register)
3990 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3991 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3992 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3993 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3995 * sf: 0 -> 32bit, 1 -> 64bit
3996 * op: 0 -> add , 1 -> sub
3998 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3999 * imm6: Shift amount to apply to Rm before the add/sub
4001 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4003 int rd
= extract32(insn
, 0, 5);
4004 int rn
= extract32(insn
, 5, 5);
4005 int imm6
= extract32(insn
, 10, 6);
4006 int rm
= extract32(insn
, 16, 5);
4007 int shift_type
= extract32(insn
, 22, 2);
4008 bool setflags
= extract32(insn
, 29, 1);
4009 bool sub_op
= extract32(insn
, 30, 1);
4010 bool sf
= extract32(insn
, 31, 1);
4012 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4013 TCGv_i64 tcg_rn
, tcg_rm
;
4014 TCGv_i64 tcg_result
;
4016 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4017 unallocated_encoding(s
);
4021 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4022 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4024 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4026 tcg_result
= tcg_temp_new_i64();
4030 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4032 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4036 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4038 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4043 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4045 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4048 tcg_temp_free_i64(tcg_result
);
4051 /* Data-processing (3 source)
4053 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4054 * +--+------+-----------+------+------+----+------+------+------+
4055 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4056 * +--+------+-----------+------+------+----+------+------+------+
4058 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4060 int rd
= extract32(insn
, 0, 5);
4061 int rn
= extract32(insn
, 5, 5);
4062 int ra
= extract32(insn
, 10, 5);
4063 int rm
= extract32(insn
, 16, 5);
4064 int op_id
= (extract32(insn
, 29, 3) << 4) |
4065 (extract32(insn
, 21, 3) << 1) |
4066 extract32(insn
, 15, 1);
4067 bool sf
= extract32(insn
, 31, 1);
4068 bool is_sub
= extract32(op_id
, 0, 1);
4069 bool is_high
= extract32(op_id
, 2, 1);
4070 bool is_signed
= false;
4075 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4077 case 0x42: /* SMADDL */
4078 case 0x43: /* SMSUBL */
4079 case 0x44: /* SMULH */
4082 case 0x0: /* MADD (32bit) */
4083 case 0x1: /* MSUB (32bit) */
4084 case 0x40: /* MADD (64bit) */
4085 case 0x41: /* MSUB (64bit) */
4086 case 0x4a: /* UMADDL */
4087 case 0x4b: /* UMSUBL */
4088 case 0x4c: /* UMULH */
4091 unallocated_encoding(s
);
4096 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4097 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4098 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4099 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4102 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4104 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4107 tcg_temp_free_i64(low_bits
);
4111 tcg_op1
= tcg_temp_new_i64();
4112 tcg_op2
= tcg_temp_new_i64();
4113 tcg_tmp
= tcg_temp_new_i64();
4116 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4117 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4120 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4121 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4123 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4124 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4128 if (ra
== 31 && !is_sub
) {
4129 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4130 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4132 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4134 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4136 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4141 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4144 tcg_temp_free_i64(tcg_op1
);
4145 tcg_temp_free_i64(tcg_op2
);
4146 tcg_temp_free_i64(tcg_tmp
);
4149 /* Add/subtract (with carry)
4150 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4151 * +--+--+--+------------------------+------+---------+------+-----+
4152 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
4153 * +--+--+--+------------------------+------+---------+------+-----+
4157 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4159 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4160 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4162 if (extract32(insn
, 10, 6) != 0) {
4163 unallocated_encoding(s
);
4167 sf
= extract32(insn
, 31, 1);
4168 op
= extract32(insn
, 30, 1);
4169 setflags
= extract32(insn
, 29, 1);
4170 rm
= extract32(insn
, 16, 5);
4171 rn
= extract32(insn
, 5, 5);
4172 rd
= extract32(insn
, 0, 5);
4174 tcg_rd
= cpu_reg(s
, rd
);
4175 tcg_rn
= cpu_reg(s
, rn
);
4178 tcg_y
= new_tmp_a64(s
);
4179 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4181 tcg_y
= cpu_reg(s
, rm
);
4185 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4187 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4191 /* Conditional compare (immediate / register)
4192 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4193 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4194 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4195 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4198 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4200 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4201 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4202 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4205 if (!extract32(insn
, 29, 1)) {
4206 unallocated_encoding(s
);
4209 if (insn
& (1 << 10 | 1 << 4)) {
4210 unallocated_encoding(s
);
4213 sf
= extract32(insn
, 31, 1);
4214 op
= extract32(insn
, 30, 1);
4215 is_imm
= extract32(insn
, 11, 1);
4216 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4217 cond
= extract32(insn
, 12, 4);
4218 rn
= extract32(insn
, 5, 5);
4219 nzcv
= extract32(insn
, 0, 4);
4221 /* Set T0 = !COND. */
4222 tcg_t0
= tcg_temp_new_i32();
4223 arm_test_cc(&c
, cond
);
4224 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4227 /* Load the arguments for the new comparison. */
4229 tcg_y
= new_tmp_a64(s
);
4230 tcg_gen_movi_i64(tcg_y
, y
);
4232 tcg_y
= cpu_reg(s
, y
);
4234 tcg_rn
= cpu_reg(s
, rn
);
4236 /* Set the flags for the new comparison. */
4237 tcg_tmp
= tcg_temp_new_i64();
4239 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4241 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4243 tcg_temp_free_i64(tcg_tmp
);
4245 /* If COND was false, force the flags to #nzcv. Compute two masks
4246 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4247 * For tcg hosts that support ANDC, we can make do with just T1.
4248 * In either case, allow the tcg optimizer to delete any unused mask.
4250 tcg_t1
= tcg_temp_new_i32();
4251 tcg_t2
= tcg_temp_new_i32();
4252 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4253 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4255 if (nzcv
& 8) { /* N */
4256 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4258 if (TCG_TARGET_HAS_andc_i32
) {
4259 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4261 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4264 if (nzcv
& 4) { /* Z */
4265 if (TCG_TARGET_HAS_andc_i32
) {
4266 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4268 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4271 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4273 if (nzcv
& 2) { /* C */
4274 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4276 if (TCG_TARGET_HAS_andc_i32
) {
4277 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4279 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4282 if (nzcv
& 1) { /* V */
4283 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4285 if (TCG_TARGET_HAS_andc_i32
) {
4286 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4288 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4291 tcg_temp_free_i32(tcg_t0
);
4292 tcg_temp_free_i32(tcg_t1
);
4293 tcg_temp_free_i32(tcg_t2
);
4296 /* Conditional select
4297 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4298 * +----+----+---+-----------------+------+------+-----+------+------+
4299 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4300 * +----+----+---+-----------------+------+------+-----+------+------+
4302 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4304 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4305 TCGv_i64 tcg_rd
, zero
;
4308 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4309 /* S == 1 or op2<1> == 1 */
4310 unallocated_encoding(s
);
4313 sf
= extract32(insn
, 31, 1);
4314 else_inv
= extract32(insn
, 30, 1);
4315 rm
= extract32(insn
, 16, 5);
4316 cond
= extract32(insn
, 12, 4);
4317 else_inc
= extract32(insn
, 10, 1);
4318 rn
= extract32(insn
, 5, 5);
4319 rd
= extract32(insn
, 0, 5);
4321 tcg_rd
= cpu_reg(s
, rd
);
4323 a64_test_cc(&c
, cond
);
4324 zero
= tcg_const_i64(0);
4326 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4328 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4330 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4333 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4334 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4335 if (else_inv
&& else_inc
) {
4336 tcg_gen_neg_i64(t_false
, t_false
);
4337 } else if (else_inv
) {
4338 tcg_gen_not_i64(t_false
, t_false
);
4339 } else if (else_inc
) {
4340 tcg_gen_addi_i64(t_false
, t_false
, 1);
4342 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4345 tcg_temp_free_i64(zero
);
4349 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4353 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4354 unsigned int rn
, unsigned int rd
)
4356 TCGv_i64 tcg_rd
, tcg_rn
;
4357 tcg_rd
= cpu_reg(s
, rd
);
4358 tcg_rn
= cpu_reg(s
, rn
);
4361 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4363 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4364 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4365 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4366 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4367 tcg_temp_free_i32(tcg_tmp32
);
4371 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4372 unsigned int rn
, unsigned int rd
)
4374 TCGv_i64 tcg_rd
, tcg_rn
;
4375 tcg_rd
= cpu_reg(s
, rd
);
4376 tcg_rn
= cpu_reg(s
, rn
);
4379 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4381 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4382 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4383 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4384 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4385 tcg_temp_free_i32(tcg_tmp32
);
4389 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4390 unsigned int rn
, unsigned int rd
)
4392 TCGv_i64 tcg_rd
, tcg_rn
;
4393 tcg_rd
= cpu_reg(s
, rd
);
4394 tcg_rn
= cpu_reg(s
, rn
);
4397 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4399 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4400 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4401 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4402 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4403 tcg_temp_free_i32(tcg_tmp32
);
4407 /* REV with sf==1, opcode==3 ("REV64") */
4408 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4409 unsigned int rn
, unsigned int rd
)
4412 unallocated_encoding(s
);
4415 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4418 /* REV with sf==0, opcode==2
4419 * REV32 (sf==1, opcode==2)
4421 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4422 unsigned int rn
, unsigned int rd
)
4424 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4427 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4428 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4430 /* bswap32_i64 requires zero high word */
4431 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4432 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4433 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4434 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4435 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4437 tcg_temp_free_i64(tcg_tmp
);
4439 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4440 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4444 /* REV16 (opcode==1) */
4445 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4446 unsigned int rn
, unsigned int rd
)
4448 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4449 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4450 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4451 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4453 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4454 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4455 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4456 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4457 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4459 tcg_temp_free_i64(mask
);
4460 tcg_temp_free_i64(tcg_tmp
);
4463 /* Data-processing (1 source)
4464 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4465 * +----+---+---+-----------------+---------+--------+------+------+
4466 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4467 * +----+---+---+-----------------+---------+--------+------+------+
4469 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4471 unsigned int sf
, opcode
, rn
, rd
;
4473 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
4474 unallocated_encoding(s
);
4478 sf
= extract32(insn
, 31, 1);
4479 opcode
= extract32(insn
, 10, 6);
4480 rn
= extract32(insn
, 5, 5);
4481 rd
= extract32(insn
, 0, 5);
4485 handle_rbit(s
, sf
, rn
, rd
);
4488 handle_rev16(s
, sf
, rn
, rd
);
4491 handle_rev32(s
, sf
, rn
, rd
);
4494 handle_rev64(s
, sf
, rn
, rd
);
4497 handle_clz(s
, sf
, rn
, rd
);
4500 handle_cls(s
, sf
, rn
, rd
);
4505 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4506 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4508 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4509 tcg_rd
= cpu_reg(s
, rd
);
4511 if (!sf
&& is_signed
) {
4512 tcg_n
= new_tmp_a64(s
);
4513 tcg_m
= new_tmp_a64(s
);
4514 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4515 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4517 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4518 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4522 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4524 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4527 if (!sf
) { /* zero extend final result */
4528 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4532 /* LSLV, LSRV, ASRV, RORV */
4533 static void handle_shift_reg(DisasContext
*s
,
4534 enum a64_shift_type shift_type
, unsigned int sf
,
4535 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4537 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4538 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4539 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4541 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4542 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4543 tcg_temp_free_i64(tcg_shift
);
4546 /* CRC32[BHWX], CRC32C[BHWX] */
4547 static void handle_crc32(DisasContext
*s
,
4548 unsigned int sf
, unsigned int sz
, bool crc32c
,
4549 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4551 TCGv_i64 tcg_acc
, tcg_val
;
4554 if (!dc_isar_feature(aa64_crc32
, s
)
4555 || (sf
== 1 && sz
!= 3)
4556 || (sf
== 0 && sz
== 3)) {
4557 unallocated_encoding(s
);
4562 tcg_val
= cpu_reg(s
, rm
);
4576 g_assert_not_reached();
4578 tcg_val
= new_tmp_a64(s
);
4579 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4582 tcg_acc
= cpu_reg(s
, rn
);
4583 tcg_bytes
= tcg_const_i32(1 << sz
);
4586 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4588 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4591 tcg_temp_free_i32(tcg_bytes
);
4594 /* Data-processing (2 source)
4595 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4596 * +----+---+---+-----------------+------+--------+------+------+
4597 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4598 * +----+---+---+-----------------+------+--------+------+------+
4600 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4602 unsigned int sf
, rm
, opcode
, rn
, rd
;
4603 sf
= extract32(insn
, 31, 1);
4604 rm
= extract32(insn
, 16, 5);
4605 opcode
= extract32(insn
, 10, 6);
4606 rn
= extract32(insn
, 5, 5);
4607 rd
= extract32(insn
, 0, 5);
4609 if (extract32(insn
, 29, 1)) {
4610 unallocated_encoding(s
);
4616 handle_div(s
, false, sf
, rm
, rn
, rd
);
4619 handle_div(s
, true, sf
, rm
, rn
, rd
);
4622 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4625 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4628 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4631 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4640 case 23: /* CRC32 */
4642 int sz
= extract32(opcode
, 0, 2);
4643 bool crc32c
= extract32(opcode
, 2, 1);
4644 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4648 unallocated_encoding(s
);
4653 /* Data processing - register */
4654 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4656 switch (extract32(insn
, 24, 5)) {
4657 case 0x0a: /* Logical (shifted register) */
4658 disas_logic_reg(s
, insn
);
4660 case 0x0b: /* Add/subtract */
4661 if (insn
& (1 << 21)) { /* (extended register) */
4662 disas_add_sub_ext_reg(s
, insn
);
4664 disas_add_sub_reg(s
, insn
);
4667 case 0x1b: /* Data-processing (3 source) */
4668 disas_data_proc_3src(s
, insn
);
4671 switch (extract32(insn
, 21, 3)) {
4672 case 0x0: /* Add/subtract (with carry) */
4673 disas_adc_sbc(s
, insn
);
4675 case 0x2: /* Conditional compare */
4676 disas_cc(s
, insn
); /* both imm and reg forms */
4678 case 0x4: /* Conditional select */
4679 disas_cond_select(s
, insn
);
4681 case 0x6: /* Data-processing */
4682 if (insn
& (1 << 30)) { /* (1 source) */
4683 disas_data_proc_1src(s
, insn
);
4684 } else { /* (2 source) */
4685 disas_data_proc_2src(s
, insn
);
4689 unallocated_encoding(s
);
4694 unallocated_encoding(s
);
4699 static void handle_fp_compare(DisasContext
*s
, int size
,
4700 unsigned int rn
, unsigned int rm
,
4701 bool cmp_with_zero
, bool signal_all_nans
)
4703 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4704 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
4706 if (size
== MO_64
) {
4707 TCGv_i64 tcg_vn
, tcg_vm
;
4709 tcg_vn
= read_fp_dreg(s
, rn
);
4710 if (cmp_with_zero
) {
4711 tcg_vm
= tcg_const_i64(0);
4713 tcg_vm
= read_fp_dreg(s
, rm
);
4715 if (signal_all_nans
) {
4716 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4718 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4720 tcg_temp_free_i64(tcg_vn
);
4721 tcg_temp_free_i64(tcg_vm
);
4723 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
4724 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
4726 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
4727 if (cmp_with_zero
) {
4728 tcg_gen_movi_i32(tcg_vm
, 0);
4730 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
4735 if (signal_all_nans
) {
4736 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4738 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4742 if (signal_all_nans
) {
4743 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4745 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4749 g_assert_not_reached();
4752 tcg_temp_free_i32(tcg_vn
);
4753 tcg_temp_free_i32(tcg_vm
);
4756 tcg_temp_free_ptr(fpst
);
4758 gen_set_nzcv(tcg_flags
);
4760 tcg_temp_free_i64(tcg_flags
);
4763 /* Floating point compare
4764 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4765 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4766 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4767 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4769 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4771 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4774 mos
= extract32(insn
, 29, 3);
4775 type
= extract32(insn
, 22, 2);
4776 rm
= extract32(insn
, 16, 5);
4777 op
= extract32(insn
, 14, 2);
4778 rn
= extract32(insn
, 5, 5);
4779 opc
= extract32(insn
, 3, 2);
4780 op2r
= extract32(insn
, 0, 3);
4782 if (mos
|| op
|| op2r
) {
4783 unallocated_encoding(s
);
4796 if (dc_isar_feature(aa64_fp16
, s
)) {
4801 unallocated_encoding(s
);
4805 if (!fp_access_check(s
)) {
4809 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
4812 /* Floating point conditional compare
4813 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4814 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4815 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4816 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4818 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4820 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4822 TCGLabel
*label_continue
= NULL
;
4825 mos
= extract32(insn
, 29, 3);
4826 type
= extract32(insn
, 22, 2);
4827 rm
= extract32(insn
, 16, 5);
4828 cond
= extract32(insn
, 12, 4);
4829 rn
= extract32(insn
, 5, 5);
4830 op
= extract32(insn
, 4, 1);
4831 nzcv
= extract32(insn
, 0, 4);
4834 unallocated_encoding(s
);
4847 if (dc_isar_feature(aa64_fp16
, s
)) {
4852 unallocated_encoding(s
);
4856 if (!fp_access_check(s
)) {
4860 if (cond
< 0x0e) { /* not always */
4861 TCGLabel
*label_match
= gen_new_label();
4862 label_continue
= gen_new_label();
4863 arm_gen_test_cc(cond
, label_match
);
4865 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4866 gen_set_nzcv(tcg_flags
);
4867 tcg_temp_free_i64(tcg_flags
);
4868 tcg_gen_br(label_continue
);
4869 gen_set_label(label_match
);
4872 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
4875 gen_set_label(label_continue
);
4879 /* Floating point conditional select
4880 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4881 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4882 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4883 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4885 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4887 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4888 TCGv_i64 t_true
, t_false
, t_zero
;
4892 mos
= extract32(insn
, 29, 3);
4893 type
= extract32(insn
, 22, 2);
4894 rm
= extract32(insn
, 16, 5);
4895 cond
= extract32(insn
, 12, 4);
4896 rn
= extract32(insn
, 5, 5);
4897 rd
= extract32(insn
, 0, 5);
4900 unallocated_encoding(s
);
4913 if (dc_isar_feature(aa64_fp16
, s
)) {
4918 unallocated_encoding(s
);
4922 if (!fp_access_check(s
)) {
4926 /* Zero extend sreg & hreg inputs to 64 bits now. */
4927 t_true
= tcg_temp_new_i64();
4928 t_false
= tcg_temp_new_i64();
4929 read_vec_element(s
, t_true
, rn
, 0, sz
);
4930 read_vec_element(s
, t_false
, rm
, 0, sz
);
4932 a64_test_cc(&c
, cond
);
4933 t_zero
= tcg_const_i64(0);
4934 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4935 tcg_temp_free_i64(t_zero
);
4936 tcg_temp_free_i64(t_false
);
4939 /* Note that sregs & hregs write back zeros to the high bits,
4940 and we've already done the zero-extension. */
4941 write_fp_dreg(s
, rd
, t_true
);
4942 tcg_temp_free_i64(t_true
);
4945 /* Floating-point data-processing (1 source) - half precision */
4946 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
4948 TCGv_ptr fpst
= NULL
;
4949 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
4950 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4953 case 0x0: /* FMOV */
4954 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4956 case 0x1: /* FABS */
4957 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
4959 case 0x2: /* FNEG */
4960 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
4962 case 0x3: /* FSQRT */
4963 fpst
= get_fpstatus_ptr(true);
4964 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
4966 case 0x8: /* FRINTN */
4967 case 0x9: /* FRINTP */
4968 case 0xa: /* FRINTM */
4969 case 0xb: /* FRINTZ */
4970 case 0xc: /* FRINTA */
4972 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4973 fpst
= get_fpstatus_ptr(true);
4975 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
4976 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
4978 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
4979 tcg_temp_free_i32(tcg_rmode
);
4982 case 0xe: /* FRINTX */
4983 fpst
= get_fpstatus_ptr(true);
4984 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
4986 case 0xf: /* FRINTI */
4987 fpst
= get_fpstatus_ptr(true);
4988 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
4994 write_fp_sreg(s
, rd
, tcg_res
);
4997 tcg_temp_free_ptr(fpst
);
4999 tcg_temp_free_i32(tcg_op
);
5000 tcg_temp_free_i32(tcg_res
);
5003 /* Floating-point data-processing (1 source) - single precision */
5004 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5010 fpst
= get_fpstatus_ptr(false);
5011 tcg_op
= read_fp_sreg(s
, rn
);
5012 tcg_res
= tcg_temp_new_i32();
5015 case 0x0: /* FMOV */
5016 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5018 case 0x1: /* FABS */
5019 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5021 case 0x2: /* FNEG */
5022 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5024 case 0x3: /* FSQRT */
5025 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5027 case 0x8: /* FRINTN */
5028 case 0x9: /* FRINTP */
5029 case 0xa: /* FRINTM */
5030 case 0xb: /* FRINTZ */
5031 case 0xc: /* FRINTA */
5033 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5035 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5036 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5038 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5039 tcg_temp_free_i32(tcg_rmode
);
5042 case 0xe: /* FRINTX */
5043 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
5045 case 0xf: /* FRINTI */
5046 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5052 write_fp_sreg(s
, rd
, tcg_res
);
5054 tcg_temp_free_ptr(fpst
);
5055 tcg_temp_free_i32(tcg_op
);
5056 tcg_temp_free_i32(tcg_res
);
5059 /* Floating-point data-processing (1 source) - double precision */
5060 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5067 case 0x0: /* FMOV */
5068 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5072 fpst
= get_fpstatus_ptr(false);
5073 tcg_op
= read_fp_dreg(s
, rn
);
5074 tcg_res
= tcg_temp_new_i64();
5077 case 0x1: /* FABS */
5078 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5080 case 0x2: /* FNEG */
5081 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5083 case 0x3: /* FSQRT */
5084 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5086 case 0x8: /* FRINTN */
5087 case 0x9: /* FRINTP */
5088 case 0xa: /* FRINTM */
5089 case 0xb: /* FRINTZ */
5090 case 0xc: /* FRINTA */
5092 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5094 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5095 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5097 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5098 tcg_temp_free_i32(tcg_rmode
);
5101 case 0xe: /* FRINTX */
5102 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
5104 case 0xf: /* FRINTI */
5105 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5111 write_fp_dreg(s
, rd
, tcg_res
);
5113 tcg_temp_free_ptr(fpst
);
5114 tcg_temp_free_i64(tcg_op
);
5115 tcg_temp_free_i64(tcg_res
);
5118 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5119 int rd
, int rn
, int dtype
, int ntype
)
5124 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5126 /* Single to double */
5127 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5128 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5129 write_fp_dreg(s
, rd
, tcg_rd
);
5130 tcg_temp_free_i64(tcg_rd
);
5132 /* Single to half */
5133 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5134 TCGv_i32 ahp
= get_ahp_flag();
5135 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5137 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5138 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5139 write_fp_sreg(s
, rd
, tcg_rd
);
5140 tcg_temp_free_i32(tcg_rd
);
5141 tcg_temp_free_i32(ahp
);
5142 tcg_temp_free_ptr(fpst
);
5144 tcg_temp_free_i32(tcg_rn
);
5149 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5150 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5152 /* Double to single */
5153 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5155 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5156 TCGv_i32 ahp
= get_ahp_flag();
5157 /* Double to half */
5158 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5159 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5160 tcg_temp_free_ptr(fpst
);
5161 tcg_temp_free_i32(ahp
);
5163 write_fp_sreg(s
, rd
, tcg_rd
);
5164 tcg_temp_free_i32(tcg_rd
);
5165 tcg_temp_free_i64(tcg_rn
);
5170 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5171 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5172 TCGv_i32 tcg_ahp
= get_ahp_flag();
5173 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5175 /* Half to single */
5176 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5177 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5178 write_fp_sreg(s
, rd
, tcg_rd
);
5179 tcg_temp_free_ptr(tcg_fpst
);
5180 tcg_temp_free_i32(tcg_ahp
);
5181 tcg_temp_free_i32(tcg_rd
);
5183 /* Half to double */
5184 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5185 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5186 write_fp_dreg(s
, rd
, tcg_rd
);
5187 tcg_temp_free_i64(tcg_rd
);
5189 tcg_temp_free_i32(tcg_rn
);
5197 /* Floating point data-processing (1 source)
5198 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5199 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5200 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5201 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5203 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5205 int type
= extract32(insn
, 22, 2);
5206 int opcode
= extract32(insn
, 15, 6);
5207 int rn
= extract32(insn
, 5, 5);
5208 int rd
= extract32(insn
, 0, 5);
5211 case 0x4: case 0x5: case 0x7:
5213 /* FCVT between half, single and double precision */
5214 int dtype
= extract32(opcode
, 0, 2);
5215 if (type
== 2 || dtype
== type
) {
5216 unallocated_encoding(s
);
5219 if (!fp_access_check(s
)) {
5223 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5229 /* 32-to-32 and 64-to-64 ops */
5232 if (!fp_access_check(s
)) {
5236 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5239 if (!fp_access_check(s
)) {
5243 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5246 if (!dc_isar_feature(aa64_fp16
, s
)) {
5247 unallocated_encoding(s
);
5251 if (!fp_access_check(s
)) {
5255 handle_fp_1src_half(s
, opcode
, rd
, rn
);
5258 unallocated_encoding(s
);
5262 unallocated_encoding(s
);
5267 /* Floating-point data-processing (2 source) - single precision */
5268 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
5269 int rd
, int rn
, int rm
)
5276 tcg_res
= tcg_temp_new_i32();
5277 fpst
= get_fpstatus_ptr(false);
5278 tcg_op1
= read_fp_sreg(s
, rn
);
5279 tcg_op2
= read_fp_sreg(s
, rm
);
5282 case 0x0: /* FMUL */
5283 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5285 case 0x1: /* FDIV */
5286 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5288 case 0x2: /* FADD */
5289 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5291 case 0x3: /* FSUB */
5292 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5294 case 0x4: /* FMAX */
5295 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5297 case 0x5: /* FMIN */
5298 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5300 case 0x6: /* FMAXNM */
5301 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5303 case 0x7: /* FMINNM */
5304 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5306 case 0x8: /* FNMUL */
5307 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5308 gen_helper_vfp_negs(tcg_res
, tcg_res
);
5312 write_fp_sreg(s
, rd
, tcg_res
);
5314 tcg_temp_free_ptr(fpst
);
5315 tcg_temp_free_i32(tcg_op1
);
5316 tcg_temp_free_i32(tcg_op2
);
5317 tcg_temp_free_i32(tcg_res
);
5320 /* Floating-point data-processing (2 source) - double precision */
5321 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
5322 int rd
, int rn
, int rm
)
5329 tcg_res
= tcg_temp_new_i64();
5330 fpst
= get_fpstatus_ptr(false);
5331 tcg_op1
= read_fp_dreg(s
, rn
);
5332 tcg_op2
= read_fp_dreg(s
, rm
);
5335 case 0x0: /* FMUL */
5336 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5338 case 0x1: /* FDIV */
5339 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5341 case 0x2: /* FADD */
5342 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5344 case 0x3: /* FSUB */
5345 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5347 case 0x4: /* FMAX */
5348 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5350 case 0x5: /* FMIN */
5351 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5353 case 0x6: /* FMAXNM */
5354 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5356 case 0x7: /* FMINNM */
5357 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5359 case 0x8: /* FNMUL */
5360 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5361 gen_helper_vfp_negd(tcg_res
, tcg_res
);
5365 write_fp_dreg(s
, rd
, tcg_res
);
5367 tcg_temp_free_ptr(fpst
);
5368 tcg_temp_free_i64(tcg_op1
);
5369 tcg_temp_free_i64(tcg_op2
);
5370 tcg_temp_free_i64(tcg_res
);
5373 /* Floating-point data-processing (2 source) - half precision */
5374 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
5375 int rd
, int rn
, int rm
)
5382 tcg_res
= tcg_temp_new_i32();
5383 fpst
= get_fpstatus_ptr(true);
5384 tcg_op1
= read_fp_hreg(s
, rn
);
5385 tcg_op2
= read_fp_hreg(s
, rm
);
5388 case 0x0: /* FMUL */
5389 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5391 case 0x1: /* FDIV */
5392 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5394 case 0x2: /* FADD */
5395 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5397 case 0x3: /* FSUB */
5398 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5400 case 0x4: /* FMAX */
5401 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5403 case 0x5: /* FMIN */
5404 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5406 case 0x6: /* FMAXNM */
5407 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5409 case 0x7: /* FMINNM */
5410 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5412 case 0x8: /* FNMUL */
5413 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5414 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
5417 g_assert_not_reached();
5420 write_fp_sreg(s
, rd
, tcg_res
);
5422 tcg_temp_free_ptr(fpst
);
5423 tcg_temp_free_i32(tcg_op1
);
5424 tcg_temp_free_i32(tcg_op2
);
5425 tcg_temp_free_i32(tcg_res
);
5428 /* Floating point data-processing (2 source)
5429 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5430 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5431 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
5432 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5434 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
5436 int type
= extract32(insn
, 22, 2);
5437 int rd
= extract32(insn
, 0, 5);
5438 int rn
= extract32(insn
, 5, 5);
5439 int rm
= extract32(insn
, 16, 5);
5440 int opcode
= extract32(insn
, 12, 4);
5443 unallocated_encoding(s
);
5449 if (!fp_access_check(s
)) {
5452 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
5455 if (!fp_access_check(s
)) {
5458 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
5461 if (!dc_isar_feature(aa64_fp16
, s
)) {
5462 unallocated_encoding(s
);
5465 if (!fp_access_check(s
)) {
5468 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
5471 unallocated_encoding(s
);
5475 /* Floating-point data-processing (3 source) - single precision */
5476 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
5477 int rd
, int rn
, int rm
, int ra
)
5479 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
5480 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5481 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5483 tcg_op1
= read_fp_sreg(s
, rn
);
5484 tcg_op2
= read_fp_sreg(s
, rm
);
5485 tcg_op3
= read_fp_sreg(s
, ra
);
5487 /* These are fused multiply-add, and must be done as one
5488 * floating point operation with no rounding between the
5489 * multiplication and addition steps.
5490 * NB that doing the negations here as separate steps is
5491 * correct : an input NaN should come out with its sign bit
5492 * flipped if it is a negated-input.
5495 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
5499 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
5502 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5504 write_fp_sreg(s
, rd
, tcg_res
);
5506 tcg_temp_free_ptr(fpst
);
5507 tcg_temp_free_i32(tcg_op1
);
5508 tcg_temp_free_i32(tcg_op2
);
5509 tcg_temp_free_i32(tcg_op3
);
5510 tcg_temp_free_i32(tcg_res
);
5513 /* Floating-point data-processing (3 source) - double precision */
5514 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
5515 int rd
, int rn
, int rm
, int ra
)
5517 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
5518 TCGv_i64 tcg_res
= tcg_temp_new_i64();
5519 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5521 tcg_op1
= read_fp_dreg(s
, rn
);
5522 tcg_op2
= read_fp_dreg(s
, rm
);
5523 tcg_op3
= read_fp_dreg(s
, ra
);
5525 /* These are fused multiply-add, and must be done as one
5526 * floating point operation with no rounding between the
5527 * multiplication and addition steps.
5528 * NB that doing the negations here as separate steps is
5529 * correct : an input NaN should come out with its sign bit
5530 * flipped if it is a negated-input.
5533 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
5537 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
5540 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5542 write_fp_dreg(s
, rd
, tcg_res
);
5544 tcg_temp_free_ptr(fpst
);
5545 tcg_temp_free_i64(tcg_op1
);
5546 tcg_temp_free_i64(tcg_op2
);
5547 tcg_temp_free_i64(tcg_op3
);
5548 tcg_temp_free_i64(tcg_res
);
5551 /* Floating-point data-processing (3 source) - half precision */
5552 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
5553 int rd
, int rn
, int rm
, int ra
)
5555 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
5556 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5557 TCGv_ptr fpst
= get_fpstatus_ptr(true);
5559 tcg_op1
= read_fp_hreg(s
, rn
);
5560 tcg_op2
= read_fp_hreg(s
, rm
);
5561 tcg_op3
= read_fp_hreg(s
, ra
);
5563 /* These are fused multiply-add, and must be done as one
5564 * floating point operation with no rounding between the
5565 * multiplication and addition steps.
5566 * NB that doing the negations here as separate steps is
5567 * correct : an input NaN should come out with its sign bit
5568 * flipped if it is a negated-input.
5571 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
5575 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
5578 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5580 write_fp_sreg(s
, rd
, tcg_res
);
5582 tcg_temp_free_ptr(fpst
);
5583 tcg_temp_free_i32(tcg_op1
);
5584 tcg_temp_free_i32(tcg_op2
);
5585 tcg_temp_free_i32(tcg_op3
);
5586 tcg_temp_free_i32(tcg_res
);
5589 /* Floating point data-processing (3 source)
5590 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
5591 * +---+---+---+-----------+------+----+------+----+------+------+------+
5592 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
5593 * +---+---+---+-----------+------+----+------+----+------+------+------+
5595 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
5597 int type
= extract32(insn
, 22, 2);
5598 int rd
= extract32(insn
, 0, 5);
5599 int rn
= extract32(insn
, 5, 5);
5600 int ra
= extract32(insn
, 10, 5);
5601 int rm
= extract32(insn
, 16, 5);
5602 bool o0
= extract32(insn
, 15, 1);
5603 bool o1
= extract32(insn
, 21, 1);
5607 if (!fp_access_check(s
)) {
5610 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5613 if (!fp_access_check(s
)) {
5616 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5619 if (!dc_isar_feature(aa64_fp16
, s
)) {
5620 unallocated_encoding(s
);
5623 if (!fp_access_check(s
)) {
5626 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5629 unallocated_encoding(s
);
5633 /* The imm8 encodes the sign bit, enough bits to represent an exponent in
5634 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
5635 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
5637 uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
5643 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5644 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
5645 extract32(imm8
, 0, 6);
5649 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5650 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
5651 (extract32(imm8
, 0, 6) << 3);
5655 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5656 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
5657 (extract32(imm8
, 0, 6) << 6);
5660 g_assert_not_reached();
5665 /* Floating point immediate
5666 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
5667 * +---+---+---+-----------+------+---+------------+-------+------+------+
5668 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
5669 * +---+---+---+-----------+------+---+------------+-------+------+------+
5671 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
5673 int rd
= extract32(insn
, 0, 5);
5674 int imm8
= extract32(insn
, 13, 8);
5675 int type
= extract32(insn
, 22, 2);
5689 if (dc_isar_feature(aa64_fp16
, s
)) {
5694 unallocated_encoding(s
);
5698 if (!fp_access_check(s
)) {
5702 imm
= vfp_expand_imm(sz
, imm8
);
5704 tcg_res
= tcg_const_i64(imm
);
5705 write_fp_dreg(s
, rd
, tcg_res
);
5706 tcg_temp_free_i64(tcg_res
);
5709 /* Handle floating point <=> fixed point conversions. Note that we can
5710 * also deal with fp <=> integer conversions as a special case (scale == 64)
5711 * OPTME: consider handling that special case specially or at least skipping
5712 * the call to scalbn in the helpers for zero shifts.
5714 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
5715 bool itof
, int rmode
, int scale
, int sf
, int type
)
5717 bool is_signed
= !(opcode
& 1);
5718 TCGv_ptr tcg_fpstatus
;
5719 TCGv_i32 tcg_shift
, tcg_single
;
5720 TCGv_i64 tcg_double
;
5722 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
5724 tcg_shift
= tcg_const_i32(64 - scale
);
5727 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
5729 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
5732 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
5734 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
5737 tcg_int
= tcg_extend
;
5741 case 1: /* float64 */
5742 tcg_double
= tcg_temp_new_i64();
5744 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
5745 tcg_shift
, tcg_fpstatus
);
5747 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
5748 tcg_shift
, tcg_fpstatus
);
5750 write_fp_dreg(s
, rd
, tcg_double
);
5751 tcg_temp_free_i64(tcg_double
);
5754 case 0: /* float32 */
5755 tcg_single
= tcg_temp_new_i32();
5757 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
5758 tcg_shift
, tcg_fpstatus
);
5760 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
5761 tcg_shift
, tcg_fpstatus
);
5763 write_fp_sreg(s
, rd
, tcg_single
);
5764 tcg_temp_free_i32(tcg_single
);
5767 case 3: /* float16 */
5768 tcg_single
= tcg_temp_new_i32();
5770 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
5771 tcg_shift
, tcg_fpstatus
);
5773 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
5774 tcg_shift
, tcg_fpstatus
);
5776 write_fp_sreg(s
, rd
, tcg_single
);
5777 tcg_temp_free_i32(tcg_single
);
5781 g_assert_not_reached();
5784 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
5787 if (extract32(opcode
, 2, 1)) {
5788 /* There are too many rounding modes to all fit into rmode,
5789 * so FCVTA[US] is a special case.
5791 rmode
= FPROUNDING_TIEAWAY
;
5794 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5796 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
5799 case 1: /* float64 */
5800 tcg_double
= read_fp_dreg(s
, rn
);
5803 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
5804 tcg_shift
, tcg_fpstatus
);
5806 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
5807 tcg_shift
, tcg_fpstatus
);
5811 gen_helper_vfp_tould(tcg_int
, tcg_double
,
5812 tcg_shift
, tcg_fpstatus
);
5814 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
5815 tcg_shift
, tcg_fpstatus
);
5819 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
5821 tcg_temp_free_i64(tcg_double
);
5824 case 0: /* float32 */
5825 tcg_single
= read_fp_sreg(s
, rn
);
5828 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
5829 tcg_shift
, tcg_fpstatus
);
5831 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
5832 tcg_shift
, tcg_fpstatus
);
5835 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5837 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
5838 tcg_shift
, tcg_fpstatus
);
5840 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
5841 tcg_shift
, tcg_fpstatus
);
5843 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5844 tcg_temp_free_i32(tcg_dest
);
5846 tcg_temp_free_i32(tcg_single
);
5849 case 3: /* float16 */
5850 tcg_single
= read_fp_sreg(s
, rn
);
5853 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
5854 tcg_shift
, tcg_fpstatus
);
5856 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
5857 tcg_shift
, tcg_fpstatus
);
5860 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5862 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
5863 tcg_shift
, tcg_fpstatus
);
5865 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
5866 tcg_shift
, tcg_fpstatus
);
5868 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5869 tcg_temp_free_i32(tcg_dest
);
5871 tcg_temp_free_i32(tcg_single
);
5875 g_assert_not_reached();
5878 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
5879 tcg_temp_free_i32(tcg_rmode
);
5882 tcg_temp_free_ptr(tcg_fpstatus
);
5883 tcg_temp_free_i32(tcg_shift
);
5886 /* Floating point <-> fixed point conversions
5887 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5888 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5889 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5890 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5892 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
5894 int rd
= extract32(insn
, 0, 5);
5895 int rn
= extract32(insn
, 5, 5);
5896 int scale
= extract32(insn
, 10, 6);
5897 int opcode
= extract32(insn
, 16, 3);
5898 int rmode
= extract32(insn
, 19, 2);
5899 int type
= extract32(insn
, 22, 2);
5900 bool sbit
= extract32(insn
, 29, 1);
5901 bool sf
= extract32(insn
, 31, 1);
5904 if (sbit
|| (!sf
&& scale
< 32)) {
5905 unallocated_encoding(s
);
5910 case 0: /* float32 */
5911 case 1: /* float64 */
5913 case 3: /* float16 */
5914 if (dc_isar_feature(aa64_fp16
, s
)) {
5919 unallocated_encoding(s
);
5923 switch ((rmode
<< 3) | opcode
) {
5924 case 0x2: /* SCVTF */
5925 case 0x3: /* UCVTF */
5928 case 0x18: /* FCVTZS */
5929 case 0x19: /* FCVTZU */
5933 unallocated_encoding(s
);
5937 if (!fp_access_check(s
)) {
5941 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5944 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5946 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5947 * without conversion.
5951 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5957 tmp
= tcg_temp_new_i64();
5958 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5959 write_fp_dreg(s
, rd
, tmp
);
5960 tcg_temp_free_i64(tmp
);
5964 write_fp_dreg(s
, rd
, tcg_rn
);
5967 /* 64 bit to top half. */
5968 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5969 clear_vec_high(s
, true, rd
);
5973 tmp
= tcg_temp_new_i64();
5974 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
5975 write_fp_dreg(s
, rd
, tmp
);
5976 tcg_temp_free_i64(tmp
);
5979 g_assert_not_reached();
5982 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5987 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5991 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5994 /* 64 bits from top half */
5995 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
5999 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6002 g_assert_not_reached();
6007 /* Floating point <-> integer conversions
6008 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6009 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6010 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6011 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6013 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6015 int rd
= extract32(insn
, 0, 5);
6016 int rn
= extract32(insn
, 5, 5);
6017 int opcode
= extract32(insn
, 16, 3);
6018 int rmode
= extract32(insn
, 19, 2);
6019 int type
= extract32(insn
, 22, 2);
6020 bool sbit
= extract32(insn
, 29, 1);
6021 bool sf
= extract32(insn
, 31, 1);
6024 unallocated_encoding(s
);
6030 bool itof
= opcode
& 1;
6033 unallocated_encoding(s
);
6037 switch (sf
<< 3 | type
<< 1 | rmode
) {
6038 case 0x0: /* 32 bit */
6039 case 0xa: /* 64 bit */
6040 case 0xd: /* 64 bit to top half of quad */
6042 case 0x6: /* 16-bit float, 32-bit int */
6043 case 0xe: /* 16-bit float, 64-bit int */
6044 if (dc_isar_feature(aa64_fp16
, s
)) {
6049 /* all other sf/type/rmode combinations are invalid */
6050 unallocated_encoding(s
);
6054 if (!fp_access_check(s
)) {
6057 handle_fmov(s
, rd
, rn
, type
, itof
);
6059 /* actual FP conversions */
6060 bool itof
= extract32(opcode
, 1, 1);
6062 if (rmode
!= 0 && opcode
> 1) {
6063 unallocated_encoding(s
);
6067 case 0: /* float32 */
6068 case 1: /* float64 */
6070 case 3: /* float16 */
6071 if (dc_isar_feature(aa64_fp16
, s
)) {
6076 unallocated_encoding(s
);
6080 if (!fp_access_check(s
)) {
6083 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6087 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6088 * 31 30 29 28 25 24 0
6089 * +---+---+---+---------+-----------------------------+
6090 * | | 0 | | 1 1 1 1 | |
6091 * +---+---+---+---------+-----------------------------+
6093 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6095 if (extract32(insn
, 24, 1)) {
6096 /* Floating point data-processing (3 source) */
6097 disas_fp_3src(s
, insn
);
6098 } else if (extract32(insn
, 21, 1) == 0) {
6099 /* Floating point to fixed point conversions */
6100 disas_fp_fixed_conv(s
, insn
);
6102 switch (extract32(insn
, 10, 2)) {
6104 /* Floating point conditional compare */
6105 disas_fp_ccomp(s
, insn
);
6108 /* Floating point data-processing (2 source) */
6109 disas_fp_2src(s
, insn
);
6112 /* Floating point conditional select */
6113 disas_fp_csel(s
, insn
);
6116 switch (ctz32(extract32(insn
, 12, 4))) {
6117 case 0: /* [15:12] == xxx1 */
6118 /* Floating point immediate */
6119 disas_fp_imm(s
, insn
);
6121 case 1: /* [15:12] == xx10 */
6122 /* Floating point compare */
6123 disas_fp_compare(s
, insn
);
6125 case 2: /* [15:12] == x100 */
6126 /* Floating point data-processing (1 source) */
6127 disas_fp_1src(s
, insn
);
6129 case 3: /* [15:12] == 1000 */
6130 unallocated_encoding(s
);
6132 default: /* [15:12] == 0000 */
6133 /* Floating point <-> integer conversions */
6134 disas_fp_int_conv(s
, insn
);
6142 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6145 /* Extract 64 bits from the middle of two concatenated 64 bit
6146 * vector register slices left:right. The extracted bits start
6147 * at 'pos' bits into the right (least significant) side.
6148 * We return the result in tcg_right, and guarantee not to
6151 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6152 assert(pos
> 0 && pos
< 64);
6154 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6155 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6156 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6158 tcg_temp_free_i64(tcg_tmp
);
6162 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6163 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6164 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6165 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6167 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6169 int is_q
= extract32(insn
, 30, 1);
6170 int op2
= extract32(insn
, 22, 2);
6171 int imm4
= extract32(insn
, 11, 4);
6172 int rm
= extract32(insn
, 16, 5);
6173 int rn
= extract32(insn
, 5, 5);
6174 int rd
= extract32(insn
, 0, 5);
6175 int pos
= imm4
<< 3;
6176 TCGv_i64 tcg_resl
, tcg_resh
;
6178 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6179 unallocated_encoding(s
);
6183 if (!fp_access_check(s
)) {
6187 tcg_resh
= tcg_temp_new_i64();
6188 tcg_resl
= tcg_temp_new_i64();
6190 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6191 * either extracting 128 bits from a 128:128 concatenation, or
6192 * extracting 64 bits from a 64:64 concatenation.
6195 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6197 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6198 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6200 tcg_gen_movi_i64(tcg_resh
, 0);
6207 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6208 EltPosns
*elt
= eltposns
;
6215 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6217 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6220 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6221 tcg_hh
= tcg_temp_new_i64();
6222 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6223 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
6224 tcg_temp_free_i64(tcg_hh
);
6228 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6229 tcg_temp_free_i64(tcg_resl
);
6230 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6231 tcg_temp_free_i64(tcg_resh
);
6235 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6236 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6237 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6238 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6240 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
6242 int op2
= extract32(insn
, 22, 2);
6243 int is_q
= extract32(insn
, 30, 1);
6244 int rm
= extract32(insn
, 16, 5);
6245 int rn
= extract32(insn
, 5, 5);
6246 int rd
= extract32(insn
, 0, 5);
6247 int is_tblx
= extract32(insn
, 12, 1);
6248 int len
= extract32(insn
, 13, 2);
6249 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
6250 TCGv_i32 tcg_regno
, tcg_numregs
;
6253 unallocated_encoding(s
);
6257 if (!fp_access_check(s
)) {
6261 /* This does a table lookup: for every byte element in the input
6262 * we index into a table formed from up to four vector registers,
6263 * and then the output is the result of the lookups. Our helper
6264 * function does the lookup operation for a single 64 bit part of
6267 tcg_resl
= tcg_temp_new_i64();
6268 tcg_resh
= tcg_temp_new_i64();
6271 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6273 tcg_gen_movi_i64(tcg_resl
, 0);
6275 if (is_tblx
&& is_q
) {
6276 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6278 tcg_gen_movi_i64(tcg_resh
, 0);
6281 tcg_idx
= tcg_temp_new_i64();
6282 tcg_regno
= tcg_const_i32(rn
);
6283 tcg_numregs
= tcg_const_i32(len
+ 1);
6284 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
6285 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
6286 tcg_regno
, tcg_numregs
);
6288 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
6289 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
6290 tcg_regno
, tcg_numregs
);
6292 tcg_temp_free_i64(tcg_idx
);
6293 tcg_temp_free_i32(tcg_regno
);
6294 tcg_temp_free_i32(tcg_numregs
);
6296 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6297 tcg_temp_free_i64(tcg_resl
);
6298 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6299 tcg_temp_free_i64(tcg_resh
);
6303 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
6304 * +---+---+-------------+------+---+------+---+------------------+------+
6305 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
6306 * +---+---+-------------+------+---+------+---+------------------+------+
6308 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
6310 int rd
= extract32(insn
, 0, 5);
6311 int rn
= extract32(insn
, 5, 5);
6312 int rm
= extract32(insn
, 16, 5);
6313 int size
= extract32(insn
, 22, 2);
6314 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
6315 * bit 2 indicates 1 vs 2 variant of the insn.
6317 int opcode
= extract32(insn
, 12, 2);
6318 bool part
= extract32(insn
, 14, 1);
6319 bool is_q
= extract32(insn
, 30, 1);
6320 int esize
= 8 << size
;
6322 int datasize
= is_q
? 128 : 64;
6323 int elements
= datasize
/ esize
;
6324 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
6326 if (opcode
== 0 || (size
== 3 && !is_q
)) {
6327 unallocated_encoding(s
);
6331 if (!fp_access_check(s
)) {
6335 tcg_resl
= tcg_const_i64(0);
6336 tcg_resh
= tcg_const_i64(0);
6337 tcg_res
= tcg_temp_new_i64();
6339 for (i
= 0; i
< elements
; i
++) {
6341 case 1: /* UZP1/2 */
6343 int midpoint
= elements
/ 2;
6345 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
6347 read_vec_element(s
, tcg_res
, rm
,
6348 2 * (i
- midpoint
) + part
, size
);
6352 case 2: /* TRN1/2 */
6354 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
6356 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
6359 case 3: /* ZIP1/2 */
6361 int base
= part
* elements
/ 2;
6363 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
6365 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
6370 g_assert_not_reached();
6375 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
6376 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
6378 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
6379 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
6383 tcg_temp_free_i64(tcg_res
);
6385 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6386 tcg_temp_free_i64(tcg_resl
);
6387 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6388 tcg_temp_free_i64(tcg_resh
);
6392 * do_reduction_op helper
6394 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
6395 * important for correct NaN propagation that we do these
6396 * operations in exactly the order specified by the pseudocode.
6398 * This is a recursive function, TCG temps should be freed by the
6399 * calling function once it is done with the values.
6401 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
6402 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
6404 if (esize
== size
) {
6406 TCGMemOp msize
= esize
== 16 ? MO_16
: MO_32
;
6409 /* We should have one register left here */
6410 assert(ctpop8(vmap
) == 1);
6411 element
= ctz32(vmap
);
6412 assert(element
< 8);
6414 tcg_elem
= tcg_temp_new_i32();
6415 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
6418 int bits
= size
/ 2;
6419 int shift
= ctpop8(vmap
) / 2;
6420 int vmap_lo
= (vmap
>> shift
) & vmap
;
6421 int vmap_hi
= (vmap
& ~vmap_lo
);
6422 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
6424 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
6425 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
6426 tcg_res
= tcg_temp_new_i32();
6429 case 0x0c: /* fmaxnmv half-precision */
6430 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6432 case 0x0f: /* fmaxv half-precision */
6433 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6435 case 0x1c: /* fminnmv half-precision */
6436 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6438 case 0x1f: /* fminv half-precision */
6439 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6441 case 0x2c: /* fmaxnmv */
6442 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6444 case 0x2f: /* fmaxv */
6445 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6447 case 0x3c: /* fminnmv */
6448 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6450 case 0x3f: /* fminv */
6451 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6454 g_assert_not_reached();
6457 tcg_temp_free_i32(tcg_hi
);
6458 tcg_temp_free_i32(tcg_lo
);
6463 /* AdvSIMD across lanes
6464 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6465 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6466 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6467 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6469 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
6471 int rd
= extract32(insn
, 0, 5);
6472 int rn
= extract32(insn
, 5, 5);
6473 int size
= extract32(insn
, 22, 2);
6474 int opcode
= extract32(insn
, 12, 5);
6475 bool is_q
= extract32(insn
, 30, 1);
6476 bool is_u
= extract32(insn
, 29, 1);
6478 bool is_min
= false;
6482 TCGv_i64 tcg_res
, tcg_elt
;
6485 case 0x1b: /* ADDV */
6487 unallocated_encoding(s
);
6491 case 0x3: /* SADDLV, UADDLV */
6492 case 0xa: /* SMAXV, UMAXV */
6493 case 0x1a: /* SMINV, UMINV */
6494 if (size
== 3 || (size
== 2 && !is_q
)) {
6495 unallocated_encoding(s
);
6499 case 0xc: /* FMAXNMV, FMINNMV */
6500 case 0xf: /* FMAXV, FMINV */
6501 /* Bit 1 of size field encodes min vs max and the actual size
6502 * depends on the encoding of the U bit. If not set (and FP16
6503 * enabled) then we do half-precision float instead of single
6506 is_min
= extract32(size
, 1, 1);
6508 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
6510 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
6511 unallocated_encoding(s
);
6518 unallocated_encoding(s
);
6522 if (!fp_access_check(s
)) {
6527 elements
= (is_q
? 128 : 64) / esize
;
6529 tcg_res
= tcg_temp_new_i64();
6530 tcg_elt
= tcg_temp_new_i64();
6532 /* These instructions operate across all lanes of a vector
6533 * to produce a single result. We can guarantee that a 64
6534 * bit intermediate is sufficient:
6535 * + for [US]ADDLV the maximum element size is 32 bits, and
6536 * the result type is 64 bits
6537 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
6538 * same as the element size, which is 32 bits at most
6539 * For the integer operations we can choose to work at 64
6540 * or 32 bits and truncate at the end; for simplicity
6541 * we use 64 bits always. The floating point
6542 * ops do require 32 bit intermediates, though.
6545 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
6547 for (i
= 1; i
< elements
; i
++) {
6548 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
6551 case 0x03: /* SADDLV / UADDLV */
6552 case 0x1b: /* ADDV */
6553 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
6555 case 0x0a: /* SMAXV / UMAXV */
6557 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
6559 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
6562 case 0x1a: /* SMINV / UMINV */
6564 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
6566 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
6570 g_assert_not_reached();
6575 /* Floating point vector reduction ops which work across 32
6576 * bit (single) or 16 bit (half-precision) intermediates.
6577 * Note that correct NaN propagation requires that we do these
6578 * operations in exactly the order specified by the pseudocode.
6580 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
6581 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
6582 int vmap
= (1 << elements
) - 1;
6583 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
6584 (is_q
? 128 : 64), vmap
, fpst
);
6585 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
6586 tcg_temp_free_i32(tcg_res32
);
6587 tcg_temp_free_ptr(fpst
);
6590 tcg_temp_free_i64(tcg_elt
);
6592 /* Now truncate the result to the width required for the final output */
6593 if (opcode
== 0x03) {
6594 /* SADDLV, UADDLV: result is 2*esize */
6600 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
6603 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
6606 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6611 g_assert_not_reached();
6614 write_fp_dreg(s
, rd
, tcg_res
);
6615 tcg_temp_free_i64(tcg_res
);
6618 /* DUP (Element, Vector)
6620 * 31 30 29 21 20 16 15 10 9 5 4 0
6621 * +---+---+-------------------+--------+-------------+------+------+
6622 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
6623 * +---+---+-------------------+--------+-------------+------+------+
6625 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6627 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
6630 int size
= ctz32(imm5
);
6631 int index
= imm5
>> (size
+ 1);
6633 if (size
> 3 || (size
== 3 && !is_q
)) {
6634 unallocated_encoding(s
);
6638 if (!fp_access_check(s
)) {
6642 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
6643 vec_reg_offset(s
, rn
, index
, size
),
6644 is_q
? 16 : 8, vec_full_reg_size(s
));
6647 /* DUP (element, scalar)
6648 * 31 21 20 16 15 10 9 5 4 0
6649 * +-----------------------+--------+-------------+------+------+
6650 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
6651 * +-----------------------+--------+-------------+------+------+
6653 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
6656 int size
= ctz32(imm5
);
6661 unallocated_encoding(s
);
6665 if (!fp_access_check(s
)) {
6669 index
= imm5
>> (size
+ 1);
6671 /* This instruction just extracts the specified element and
6672 * zero-extends it into the bottom of the destination register.
6674 tmp
= tcg_temp_new_i64();
6675 read_vec_element(s
, tmp
, rn
, index
, size
);
6676 write_fp_dreg(s
, rd
, tmp
);
6677 tcg_temp_free_i64(tmp
);
6682 * 31 30 29 21 20 16 15 10 9 5 4 0
6683 * +---+---+-------------------+--------+-------------+------+------+
6684 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
6685 * +---+---+-------------------+--------+-------------+------+------+
6687 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6689 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
6692 int size
= ctz32(imm5
);
6693 uint32_t dofs
, oprsz
, maxsz
;
6695 if (size
> 3 || ((size
== 3) && !is_q
)) {
6696 unallocated_encoding(s
);
6700 if (!fp_access_check(s
)) {
6704 dofs
= vec_full_reg_offset(s
, rd
);
6705 oprsz
= is_q
? 16 : 8;
6706 maxsz
= vec_full_reg_size(s
);
6708 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
6713 * 31 21 20 16 15 14 11 10 9 5 4 0
6714 * +-----------------------+--------+------------+---+------+------+
6715 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6716 * +-----------------------+--------+------------+---+------+------+
6718 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6719 * index: encoded in imm5<4:size+1>
6721 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
6724 int size
= ctz32(imm5
);
6725 int src_index
, dst_index
;
6729 unallocated_encoding(s
);
6733 if (!fp_access_check(s
)) {
6737 dst_index
= extract32(imm5
, 1+size
, 5);
6738 src_index
= extract32(imm4
, size
, 4);
6740 tmp
= tcg_temp_new_i64();
6742 read_vec_element(s
, tmp
, rn
, src_index
, size
);
6743 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
6745 tcg_temp_free_i64(tmp
);
6751 * 31 21 20 16 15 10 9 5 4 0
6752 * +-----------------------+--------+-------------+------+------+
6753 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
6754 * +-----------------------+--------+-------------+------+------+
6756 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6757 * index: encoded in imm5<4:size+1>
6759 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
6761 int size
= ctz32(imm5
);
6765 unallocated_encoding(s
);
6769 if (!fp_access_check(s
)) {
6773 idx
= extract32(imm5
, 1 + size
, 4 - size
);
6774 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
6781 * 31 30 29 21 20 16 15 12 10 9 5 4 0
6782 * +---+---+-------------------+--------+-------------+------+------+
6783 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
6784 * +---+---+-------------------+--------+-------------+------+------+
6786 * U: unsigned when set
6787 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6789 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
6790 int rn
, int rd
, int imm5
)
6792 int size
= ctz32(imm5
);
6796 /* Check for UnallocatedEncodings */
6798 if (size
> 2 || (size
== 2 && !is_q
)) {
6799 unallocated_encoding(s
);
6804 || (size
< 3 && is_q
)
6805 || (size
== 3 && !is_q
)) {
6806 unallocated_encoding(s
);
6811 if (!fp_access_check(s
)) {
6815 element
= extract32(imm5
, 1+size
, 4);
6817 tcg_rd
= cpu_reg(s
, rd
);
6818 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
6819 if (is_signed
&& !is_q
) {
6820 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
6825 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6826 * +---+---+----+-----------------+------+---+------+---+------+------+
6827 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6828 * +---+---+----+-----------------+------+---+------+---+------+------+
6830 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
6832 int rd
= extract32(insn
, 0, 5);
6833 int rn
= extract32(insn
, 5, 5);
6834 int imm4
= extract32(insn
, 11, 4);
6835 int op
= extract32(insn
, 29, 1);
6836 int is_q
= extract32(insn
, 30, 1);
6837 int imm5
= extract32(insn
, 16, 5);
6842 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
6844 unallocated_encoding(s
);
6849 /* DUP (element - vector) */
6850 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
6854 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
6859 handle_simd_insg(s
, rd
, rn
, imm5
);
6861 unallocated_encoding(s
);
6866 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6867 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
6870 unallocated_encoding(s
);
6876 /* AdvSIMD modified immediate
6877 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6878 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6879 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6880 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6882 * There are a number of operations that can be carried out here:
6883 * MOVI - move (shifted) imm into register
6884 * MVNI - move inverted (shifted) imm into register
6885 * ORR - bitwise OR of (shifted) imm with register
6886 * BIC - bitwise clear of (shifted) imm with register
6887 * With ARMv8.2 we also have:
6888 * FMOV half-precision
6890 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
6892 int rd
= extract32(insn
, 0, 5);
6893 int cmode
= extract32(insn
, 12, 4);
6894 int cmode_3_1
= extract32(cmode
, 1, 3);
6895 int cmode_0
= extract32(cmode
, 0, 1);
6896 int o2
= extract32(insn
, 11, 1);
6897 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
6898 bool is_neg
= extract32(insn
, 29, 1);
6899 bool is_q
= extract32(insn
, 30, 1);
6902 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
6903 /* Check for FMOV (vector, immediate) - half-precision */
6904 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
6905 unallocated_encoding(s
);
6910 if (!fp_access_check(s
)) {
6914 /* See AdvSIMDExpandImm() in ARM ARM */
6915 switch (cmode_3_1
) {
6916 case 0: /* Replicate(Zeros(24):imm8, 2) */
6917 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6918 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6919 case 3: /* Replicate(imm8:Zeros(24), 2) */
6921 int shift
= cmode_3_1
* 8;
6922 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
6925 case 4: /* Replicate(Zeros(8):imm8, 4) */
6926 case 5: /* Replicate(imm8:Zeros(8), 4) */
6928 int shift
= (cmode_3_1
& 0x1) * 8;
6929 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
6934 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6935 imm
= (abcdefgh
<< 16) | 0xffff;
6937 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6938 imm
= (abcdefgh
<< 8) | 0xff;
6940 imm
= bitfield_replicate(imm
, 32);
6943 if (!cmode_0
&& !is_neg
) {
6944 imm
= bitfield_replicate(abcdefgh
, 8);
6945 } else if (!cmode_0
&& is_neg
) {
6948 for (i
= 0; i
< 8; i
++) {
6949 if ((abcdefgh
) & (1 << i
)) {
6950 imm
|= 0xffULL
<< (i
* 8);
6953 } else if (cmode_0
) {
6955 imm
= (abcdefgh
& 0x3f) << 48;
6956 if (abcdefgh
& 0x80) {
6957 imm
|= 0x8000000000000000ULL
;
6959 if (abcdefgh
& 0x40) {
6960 imm
|= 0x3fc0000000000000ULL
;
6962 imm
|= 0x4000000000000000ULL
;
6966 /* FMOV (vector, immediate) - half-precision */
6967 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
6968 /* now duplicate across the lanes */
6969 imm
= bitfield_replicate(imm
, 16);
6971 imm
= (abcdefgh
& 0x3f) << 19;
6972 if (abcdefgh
& 0x80) {
6975 if (abcdefgh
& 0x40) {
6986 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
6987 g_assert_not_reached();
6990 if (cmode_3_1
!= 7 && is_neg
) {
6994 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
6995 /* MOVI or MVNI, with MVNI negation handled above. */
6996 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
6997 vec_full_reg_size(s
), imm
);
6999 /* ORR or BIC, with BIC negation to AND handled above. */
7001 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7003 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7008 /* AdvSIMD scalar copy
7009 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7010 * +-----+----+-----------------+------+---+------+---+------+------+
7011 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7012 * +-----+----+-----------------+------+---+------+---+------+------+
7014 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7016 int rd
= extract32(insn
, 0, 5);
7017 int rn
= extract32(insn
, 5, 5);
7018 int imm4
= extract32(insn
, 11, 4);
7019 int imm5
= extract32(insn
, 16, 5);
7020 int op
= extract32(insn
, 29, 1);
7022 if (op
!= 0 || imm4
!= 0) {
7023 unallocated_encoding(s
);
7027 /* DUP (element, scalar) */
7028 handle_simd_dupes(s
, rd
, rn
, imm5
);
7031 /* AdvSIMD scalar pairwise
7032 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7033 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7034 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7035 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7037 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7039 int u
= extract32(insn
, 29, 1);
7040 int size
= extract32(insn
, 22, 2);
7041 int opcode
= extract32(insn
, 12, 5);
7042 int rn
= extract32(insn
, 5, 5);
7043 int rd
= extract32(insn
, 0, 5);
7046 /* For some ops (the FP ones), size[1] is part of the encoding.
7047 * For ADDP strictly it is not but size[1] is always 1 for valid
7050 opcode
|= (extract32(size
, 1, 1) << 5);
7053 case 0x3b: /* ADDP */
7054 if (u
|| size
!= 3) {
7055 unallocated_encoding(s
);
7058 if (!fp_access_check(s
)) {
7064 case 0xc: /* FMAXNMP */
7065 case 0xd: /* FADDP */
7066 case 0xf: /* FMAXP */
7067 case 0x2c: /* FMINNMP */
7068 case 0x2f: /* FMINP */
7069 /* FP op, size[0] is 32 or 64 bit*/
7071 if (!dc_isar_feature(aa64_fp16
, s
)) {
7072 unallocated_encoding(s
);
7078 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7081 if (!fp_access_check(s
)) {
7085 fpst
= get_fpstatus_ptr(size
== MO_16
);
7088 unallocated_encoding(s
);
7092 if (size
== MO_64
) {
7093 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7094 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7095 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7097 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7098 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7101 case 0x3b: /* ADDP */
7102 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7104 case 0xc: /* FMAXNMP */
7105 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7107 case 0xd: /* FADDP */
7108 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7110 case 0xf: /* FMAXP */
7111 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7113 case 0x2c: /* FMINNMP */
7114 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7116 case 0x2f: /* FMINP */
7117 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7120 g_assert_not_reached();
7123 write_fp_dreg(s
, rd
, tcg_res
);
7125 tcg_temp_free_i64(tcg_op1
);
7126 tcg_temp_free_i64(tcg_op2
);
7127 tcg_temp_free_i64(tcg_res
);
7129 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7130 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7131 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7133 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7134 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7136 if (size
== MO_16
) {
7138 case 0xc: /* FMAXNMP */
7139 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7141 case 0xd: /* FADDP */
7142 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7144 case 0xf: /* FMAXP */
7145 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7147 case 0x2c: /* FMINNMP */
7148 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7150 case 0x2f: /* FMINP */
7151 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7154 g_assert_not_reached();
7158 case 0xc: /* FMAXNMP */
7159 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7161 case 0xd: /* FADDP */
7162 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7164 case 0xf: /* FMAXP */
7165 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7167 case 0x2c: /* FMINNMP */
7168 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7170 case 0x2f: /* FMINP */
7171 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7174 g_assert_not_reached();
7178 write_fp_sreg(s
, rd
, tcg_res
);
7180 tcg_temp_free_i32(tcg_op1
);
7181 tcg_temp_free_i32(tcg_op2
);
7182 tcg_temp_free_i32(tcg_res
);
7186 tcg_temp_free_ptr(fpst
);
7191 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7193 * This code is handles the common shifting code and is used by both
7194 * the vector and scalar code.
7196 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7197 TCGv_i64 tcg_rnd
, bool accumulate
,
7198 bool is_u
, int size
, int shift
)
7200 bool extended_result
= false;
7201 bool round
= tcg_rnd
!= NULL
;
7203 TCGv_i64 tcg_src_hi
;
7205 if (round
&& size
== 3) {
7206 extended_result
= true;
7207 ext_lshift
= 64 - shift
;
7208 tcg_src_hi
= tcg_temp_new_i64();
7209 } else if (shift
== 64) {
7210 if (!accumulate
&& is_u
) {
7211 /* result is zero */
7212 tcg_gen_movi_i64(tcg_res
, 0);
7217 /* Deal with the rounding step */
7219 if (extended_result
) {
7220 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7222 /* take care of sign extending tcg_res */
7223 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
7224 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7225 tcg_src
, tcg_src_hi
,
7228 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7232 tcg_temp_free_i64(tcg_zero
);
7234 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
7238 /* Now do the shift right */
7239 if (round
&& extended_result
) {
7240 /* extended case, >64 bit precision required */
7241 if (ext_lshift
== 0) {
7242 /* special case, only high bits matter */
7243 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
7245 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7246 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
7247 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
7252 /* essentially shifting in 64 zeros */
7253 tcg_gen_movi_i64(tcg_src
, 0);
7255 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7259 /* effectively extending the sign-bit */
7260 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
7262 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
7268 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
7270 tcg_gen_mov_i64(tcg_res
, tcg_src
);
7273 if (extended_result
) {
7274 tcg_temp_free_i64(tcg_src_hi
);
7278 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
7279 static void handle_scalar_simd_shri(DisasContext
*s
,
7280 bool is_u
, int immh
, int immb
,
7281 int opcode
, int rn
, int rd
)
7284 int immhb
= immh
<< 3 | immb
;
7285 int shift
= 2 * (8 << size
) - immhb
;
7286 bool accumulate
= false;
7288 bool insert
= false;
7293 if (!extract32(immh
, 3, 1)) {
7294 unallocated_encoding(s
);
7298 if (!fp_access_check(s
)) {
7303 case 0x02: /* SSRA / USRA (accumulate) */
7306 case 0x04: /* SRSHR / URSHR (rounding) */
7309 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7310 accumulate
= round
= true;
7312 case 0x08: /* SRI */
7318 uint64_t round_const
= 1ULL << (shift
- 1);
7319 tcg_round
= tcg_const_i64(round_const
);
7324 tcg_rn
= read_fp_dreg(s
, rn
);
7325 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7328 /* shift count same as element size is valid but does nothing;
7329 * special case to avoid potential shift by 64.
7331 int esize
= 8 << size
;
7332 if (shift
!= esize
) {
7333 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
7334 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
7337 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7338 accumulate
, is_u
, size
, shift
);
7341 write_fp_dreg(s
, rd
, tcg_rd
);
7343 tcg_temp_free_i64(tcg_rn
);
7344 tcg_temp_free_i64(tcg_rd
);
7346 tcg_temp_free_i64(tcg_round
);
7350 /* SHL/SLI - Scalar shift left */
7351 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
7352 int immh
, int immb
, int opcode
,
7355 int size
= 32 - clz32(immh
) - 1;
7356 int immhb
= immh
<< 3 | immb
;
7357 int shift
= immhb
- (8 << size
);
7358 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7359 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7361 if (!extract32(immh
, 3, 1)) {
7362 unallocated_encoding(s
);
7366 if (!fp_access_check(s
)) {
7370 tcg_rn
= read_fp_dreg(s
, rn
);
7371 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7374 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
7376 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
7379 write_fp_dreg(s
, rd
, tcg_rd
);
7381 tcg_temp_free_i64(tcg_rn
);
7382 tcg_temp_free_i64(tcg_rd
);
7385 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
7386 * (signed/unsigned) narrowing */
7387 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
7388 bool is_u_shift
, bool is_u_narrow
,
7389 int immh
, int immb
, int opcode
,
7392 int immhb
= immh
<< 3 | immb
;
7393 int size
= 32 - clz32(immh
) - 1;
7394 int esize
= 8 << size
;
7395 int shift
= (2 * esize
) - immhb
;
7396 int elements
= is_scalar
? 1 : (64 / esize
);
7397 bool round
= extract32(opcode
, 0, 1);
7398 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
7399 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
7400 TCGv_i32 tcg_rd_narrowed
;
7403 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
7404 { gen_helper_neon_narrow_sat_s8
,
7405 gen_helper_neon_unarrow_sat8
},
7406 { gen_helper_neon_narrow_sat_s16
,
7407 gen_helper_neon_unarrow_sat16
},
7408 { gen_helper_neon_narrow_sat_s32
,
7409 gen_helper_neon_unarrow_sat32
},
7412 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
7413 gen_helper_neon_narrow_sat_u8
,
7414 gen_helper_neon_narrow_sat_u16
,
7415 gen_helper_neon_narrow_sat_u32
,
7418 NeonGenNarrowEnvFn
*narrowfn
;
7424 if (extract32(immh
, 3, 1)) {
7425 unallocated_encoding(s
);
7429 if (!fp_access_check(s
)) {
7434 narrowfn
= unsigned_narrow_fns
[size
];
7436 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
7439 tcg_rn
= tcg_temp_new_i64();
7440 tcg_rd
= tcg_temp_new_i64();
7441 tcg_rd_narrowed
= tcg_temp_new_i32();
7442 tcg_final
= tcg_const_i64(0);
7445 uint64_t round_const
= 1ULL << (shift
- 1);
7446 tcg_round
= tcg_const_i64(round_const
);
7451 for (i
= 0; i
< elements
; i
++) {
7452 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
7453 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7454 false, is_u_shift
, size
+1, shift
);
7455 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
7456 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
7457 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
7461 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
7463 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
7467 tcg_temp_free_i64(tcg_round
);
7469 tcg_temp_free_i64(tcg_rn
);
7470 tcg_temp_free_i64(tcg_rd
);
7471 tcg_temp_free_i32(tcg_rd_narrowed
);
7472 tcg_temp_free_i64(tcg_final
);
7474 clear_vec_high(s
, is_q
, rd
);
7477 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
7478 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
7479 bool src_unsigned
, bool dst_unsigned
,
7480 int immh
, int immb
, int rn
, int rd
)
7482 int immhb
= immh
<< 3 | immb
;
7483 int size
= 32 - clz32(immh
) - 1;
7484 int shift
= immhb
- (8 << size
);
7488 assert(!(scalar
&& is_q
));
7491 if (!is_q
&& extract32(immh
, 3, 1)) {
7492 unallocated_encoding(s
);
7496 /* Since we use the variable-shift helpers we must
7497 * replicate the shift count into each element of
7498 * the tcg_shift value.
7502 shift
|= shift
<< 8;
7505 shift
|= shift
<< 16;
7511 g_assert_not_reached();
7515 if (!fp_access_check(s
)) {
7520 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
7521 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
7522 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
7523 { NULL
, gen_helper_neon_qshl_u64
},
7525 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
7526 int maxpass
= is_q
? 2 : 1;
7528 for (pass
= 0; pass
< maxpass
; pass
++) {
7529 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7531 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7532 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
7533 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
7535 tcg_temp_free_i64(tcg_op
);
7537 tcg_temp_free_i64(tcg_shift
);
7538 clear_vec_high(s
, is_q
, rd
);
7540 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
7541 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
7543 { gen_helper_neon_qshl_s8
,
7544 gen_helper_neon_qshl_s16
,
7545 gen_helper_neon_qshl_s32
},
7546 { gen_helper_neon_qshlu_s8
,
7547 gen_helper_neon_qshlu_s16
,
7548 gen_helper_neon_qshlu_s32
}
7550 { NULL
, NULL
, NULL
},
7551 { gen_helper_neon_qshl_u8
,
7552 gen_helper_neon_qshl_u16
,
7553 gen_helper_neon_qshl_u32
}
7556 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
7557 TCGMemOp memop
= scalar
? size
: MO_32
;
7558 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
7560 for (pass
= 0; pass
< maxpass
; pass
++) {
7561 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7563 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
7564 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
7568 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
7571 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
7576 g_assert_not_reached();
7578 write_fp_sreg(s
, rd
, tcg_op
);
7580 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
7583 tcg_temp_free_i32(tcg_op
);
7585 tcg_temp_free_i32(tcg_shift
);
7588 clear_vec_high(s
, is_q
, rd
);
7593 /* Common vector code for handling integer to FP conversion */
7594 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
7595 int elements
, int is_signed
,
7596 int fracbits
, int size
)
7598 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
7599 TCGv_i32 tcg_shift
= NULL
;
7601 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
7604 if (fracbits
|| size
== MO_64
) {
7605 tcg_shift
= tcg_const_i32(fracbits
);
7608 if (size
== MO_64
) {
7609 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
7610 TCGv_i64 tcg_double
= tcg_temp_new_i64();
7612 for (pass
= 0; pass
< elements
; pass
++) {
7613 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
7616 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
7617 tcg_shift
, tcg_fpst
);
7619 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
7620 tcg_shift
, tcg_fpst
);
7622 if (elements
== 1) {
7623 write_fp_dreg(s
, rd
, tcg_double
);
7625 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
7629 tcg_temp_free_i64(tcg_int64
);
7630 tcg_temp_free_i64(tcg_double
);
7633 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
7634 TCGv_i32 tcg_float
= tcg_temp_new_i32();
7636 for (pass
= 0; pass
< elements
; pass
++) {
7637 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
7643 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
7644 tcg_shift
, tcg_fpst
);
7646 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
7647 tcg_shift
, tcg_fpst
);
7651 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
7653 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
7660 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
7661 tcg_shift
, tcg_fpst
);
7663 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
7664 tcg_shift
, tcg_fpst
);
7668 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
7670 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
7675 g_assert_not_reached();
7678 if (elements
== 1) {
7679 write_fp_sreg(s
, rd
, tcg_float
);
7681 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
7685 tcg_temp_free_i32(tcg_int32
);
7686 tcg_temp_free_i32(tcg_float
);
7689 tcg_temp_free_ptr(tcg_fpst
);
7691 tcg_temp_free_i32(tcg_shift
);
7694 clear_vec_high(s
, elements
<< size
== 16, rd
);
7697 /* UCVTF/SCVTF - Integer to FP conversion */
7698 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
7699 bool is_q
, bool is_u
,
7700 int immh
, int immb
, int opcode
,
7703 int size
, elements
, fracbits
;
7704 int immhb
= immh
<< 3 | immb
;
7708 if (!is_scalar
&& !is_q
) {
7709 unallocated_encoding(s
);
7712 } else if (immh
& 4) {
7714 } else if (immh
& 2) {
7716 if (!dc_isar_feature(aa64_fp16
, s
)) {
7717 unallocated_encoding(s
);
7721 /* immh == 0 would be a failure of the decode logic */
7722 g_assert(immh
== 1);
7723 unallocated_encoding(s
);
7730 elements
= (8 << is_q
) >> size
;
7732 fracbits
= (16 << size
) - immhb
;
7734 if (!fp_access_check(s
)) {
7738 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
7741 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
7742 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
7743 bool is_q
, bool is_u
,
7744 int immh
, int immb
, int rn
, int rd
)
7746 int immhb
= immh
<< 3 | immb
;
7747 int pass
, size
, fracbits
;
7748 TCGv_ptr tcg_fpstatus
;
7749 TCGv_i32 tcg_rmode
, tcg_shift
;
7753 if (!is_scalar
&& !is_q
) {
7754 unallocated_encoding(s
);
7757 } else if (immh
& 0x4) {
7759 } else if (immh
& 0x2) {
7761 if (!dc_isar_feature(aa64_fp16
, s
)) {
7762 unallocated_encoding(s
);
7766 /* Should have split out AdvSIMD modified immediate earlier. */
7768 unallocated_encoding(s
);
7772 if (!fp_access_check(s
)) {
7776 assert(!(is_scalar
&& is_q
));
7778 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
7779 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
7780 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7781 fracbits
= (16 << size
) - immhb
;
7782 tcg_shift
= tcg_const_i32(fracbits
);
7784 if (size
== MO_64
) {
7785 int maxpass
= is_scalar
? 1 : 2;
7787 for (pass
= 0; pass
< maxpass
; pass
++) {
7788 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7790 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7792 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7794 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7796 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
7797 tcg_temp_free_i64(tcg_op
);
7799 clear_vec_high(s
, is_q
, rd
);
7801 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
7802 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
7807 fn
= gen_helper_vfp_touhh
;
7809 fn
= gen_helper_vfp_toshh
;
7814 fn
= gen_helper_vfp_touls
;
7816 fn
= gen_helper_vfp_tosls
;
7820 g_assert_not_reached();
7823 for (pass
= 0; pass
< maxpass
; pass
++) {
7824 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7826 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
7827 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7829 write_fp_sreg(s
, rd
, tcg_op
);
7831 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
7833 tcg_temp_free_i32(tcg_op
);
7836 clear_vec_high(s
, is_q
, rd
);
7840 tcg_temp_free_ptr(tcg_fpstatus
);
7841 tcg_temp_free_i32(tcg_shift
);
7842 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7843 tcg_temp_free_i32(tcg_rmode
);
7846 /* AdvSIMD scalar shift by immediate
7847 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
7848 * +-----+---+-------------+------+------+--------+---+------+------+
7849 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
7850 * +-----+---+-------------+------+------+--------+---+------+------+
7852 * This is the scalar version so it works on a fixed sized registers
7854 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
7856 int rd
= extract32(insn
, 0, 5);
7857 int rn
= extract32(insn
, 5, 5);
7858 int opcode
= extract32(insn
, 11, 5);
7859 int immb
= extract32(insn
, 16, 3);
7860 int immh
= extract32(insn
, 19, 4);
7861 bool is_u
= extract32(insn
, 29, 1);
7864 unallocated_encoding(s
);
7869 case 0x08: /* SRI */
7871 unallocated_encoding(s
);
7875 case 0x00: /* SSHR / USHR */
7876 case 0x02: /* SSRA / USRA */
7877 case 0x04: /* SRSHR / URSHR */
7878 case 0x06: /* SRSRA / URSRA */
7879 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7881 case 0x0a: /* SHL / SLI */
7882 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7884 case 0x1c: /* SCVTF, UCVTF */
7885 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
7888 case 0x10: /* SQSHRUN, SQSHRUN2 */
7889 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
7891 unallocated_encoding(s
);
7894 handle_vec_simd_sqshrn(s
, true, false, false, true,
7895 immh
, immb
, opcode
, rn
, rd
);
7897 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
7898 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
7899 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
7900 immh
, immb
, opcode
, rn
, rd
);
7902 case 0xc: /* SQSHLU */
7904 unallocated_encoding(s
);
7907 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
7909 case 0xe: /* SQSHL, UQSHL */
7910 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
7912 case 0x1f: /* FCVTZS, FCVTZU */
7913 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
7916 unallocated_encoding(s
);
7921 /* AdvSIMD scalar three different
7922 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7923 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7924 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7925 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7927 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7929 bool is_u
= extract32(insn
, 29, 1);
7930 int size
= extract32(insn
, 22, 2);
7931 int opcode
= extract32(insn
, 12, 4);
7932 int rm
= extract32(insn
, 16, 5);
7933 int rn
= extract32(insn
, 5, 5);
7934 int rd
= extract32(insn
, 0, 5);
7937 unallocated_encoding(s
);
7942 case 0x9: /* SQDMLAL, SQDMLAL2 */
7943 case 0xb: /* SQDMLSL, SQDMLSL2 */
7944 case 0xd: /* SQDMULL, SQDMULL2 */
7945 if (size
== 0 || size
== 3) {
7946 unallocated_encoding(s
);
7951 unallocated_encoding(s
);
7955 if (!fp_access_check(s
)) {
7960 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7961 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7962 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7964 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
7965 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
7967 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
7968 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7971 case 0xd: /* SQDMULL, SQDMULL2 */
7973 case 0xb: /* SQDMLSL, SQDMLSL2 */
7974 tcg_gen_neg_i64(tcg_res
, tcg_res
);
7976 case 0x9: /* SQDMLAL, SQDMLAL2 */
7977 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
7978 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
7982 g_assert_not_reached();
7985 write_fp_dreg(s
, rd
, tcg_res
);
7987 tcg_temp_free_i64(tcg_op1
);
7988 tcg_temp_free_i64(tcg_op2
);
7989 tcg_temp_free_i64(tcg_res
);
7991 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
7992 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
7993 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7995 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
7996 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7999 case 0xd: /* SQDMULL, SQDMULL2 */
8001 case 0xb: /* SQDMLSL, SQDMLSL2 */
8002 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8004 case 0x9: /* SQDMLAL, SQDMLAL2 */
8006 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8007 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8008 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8010 tcg_temp_free_i64(tcg_op3
);
8014 g_assert_not_reached();
8017 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8018 write_fp_dreg(s
, rd
, tcg_res
);
8020 tcg_temp_free_i32(tcg_op1
);
8021 tcg_temp_free_i32(tcg_op2
);
8022 tcg_temp_free_i64(tcg_res
);
8026 /* CMTST : test is "if (X & Y != 0)". */
8027 static void gen_cmtst_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
8029 tcg_gen_and_i32(d
, a
, b
);
8030 tcg_gen_setcondi_i32(TCG_COND_NE
, d
, d
, 0);
8031 tcg_gen_neg_i32(d
, d
);
8034 static void gen_cmtst_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
8036 tcg_gen_and_i64(d
, a
, b
);
8037 tcg_gen_setcondi_i64(TCG_COND_NE
, d
, d
, 0);
8038 tcg_gen_neg_i64(d
, d
);
8041 static void gen_cmtst_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
8043 tcg_gen_and_vec(vece
, d
, a
, b
);
8044 tcg_gen_dupi_vec(vece
, a
, 0);
8045 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, d
, d
, a
);
8048 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8049 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8051 /* Handle 64x64->64 opcodes which are shared between the scalar
8052 * and vector 3-same groups. We cover every opcode where size == 3
8053 * is valid in either the three-reg-same (integer, not pairwise)
8054 * or scalar-three-reg-same groups.
8059 case 0x1: /* SQADD */
8061 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8063 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8066 case 0x5: /* SQSUB */
8068 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8070 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8073 case 0x6: /* CMGT, CMHI */
8074 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8075 * We implement this using setcond (test) and then negating.
8077 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8079 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8080 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8082 case 0x7: /* CMGE, CMHS */
8083 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8085 case 0x11: /* CMTST, CMEQ */
8090 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8092 case 0x8: /* SSHL, USHL */
8094 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8096 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8099 case 0x9: /* SQSHL, UQSHL */
8101 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8103 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8106 case 0xa: /* SRSHL, URSHL */
8108 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8110 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8113 case 0xb: /* SQRSHL, UQRSHL */
8115 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8117 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8120 case 0x10: /* ADD, SUB */
8122 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8124 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8128 g_assert_not_reached();
8132 /* Handle the 3-same-operands float operations; shared by the scalar
8133 * and vector encodings. The caller must filter out any encodings
8134 * not allocated for the encoding it is dealing with.
8136 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8137 int fpopcode
, int rd
, int rn
, int rm
)
8140 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8142 for (pass
= 0; pass
< elements
; pass
++) {
8145 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8146 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8147 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8149 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8150 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8153 case 0x39: /* FMLS */
8154 /* As usual for ARM, separate negation for fused multiply-add */
8155 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8157 case 0x19: /* FMLA */
8158 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8159 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8162 case 0x18: /* FMAXNM */
8163 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8165 case 0x1a: /* FADD */
8166 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8168 case 0x1b: /* FMULX */
8169 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8171 case 0x1c: /* FCMEQ */
8172 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8174 case 0x1e: /* FMAX */
8175 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8177 case 0x1f: /* FRECPS */
8178 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8180 case 0x38: /* FMINNM */
8181 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8183 case 0x3a: /* FSUB */
8184 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8186 case 0x3e: /* FMIN */
8187 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8189 case 0x3f: /* FRSQRTS */
8190 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8192 case 0x5b: /* FMUL */
8193 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8195 case 0x5c: /* FCMGE */
8196 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8198 case 0x5d: /* FACGE */
8199 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8201 case 0x5f: /* FDIV */
8202 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8204 case 0x7a: /* FABD */
8205 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8206 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8208 case 0x7c: /* FCMGT */
8209 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8211 case 0x7d: /* FACGT */
8212 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8215 g_assert_not_reached();
8218 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8220 tcg_temp_free_i64(tcg_res
);
8221 tcg_temp_free_i64(tcg_op1
);
8222 tcg_temp_free_i64(tcg_op2
);
8225 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8226 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8227 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8229 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8230 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8233 case 0x39: /* FMLS */
8234 /* As usual for ARM, separate negation for fused multiply-add */
8235 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
8237 case 0x19: /* FMLA */
8238 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8239 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
8242 case 0x1a: /* FADD */
8243 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8245 case 0x1b: /* FMULX */
8246 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8248 case 0x1c: /* FCMEQ */
8249 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8251 case 0x1e: /* FMAX */
8252 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8254 case 0x1f: /* FRECPS */
8255 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8257 case 0x18: /* FMAXNM */
8258 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8260 case 0x38: /* FMINNM */
8261 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8263 case 0x3a: /* FSUB */
8264 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8266 case 0x3e: /* FMIN */
8267 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8269 case 0x3f: /* FRSQRTS */
8270 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8272 case 0x5b: /* FMUL */
8273 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8275 case 0x5c: /* FCMGE */
8276 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8278 case 0x5d: /* FACGE */
8279 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8281 case 0x5f: /* FDIV */
8282 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8284 case 0x7a: /* FABD */
8285 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8286 gen_helper_vfp_abss(tcg_res
, tcg_res
);
8288 case 0x7c: /* FCMGT */
8289 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8291 case 0x7d: /* FACGT */
8292 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8295 g_assert_not_reached();
8298 if (elements
== 1) {
8299 /* scalar single so clear high part */
8300 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8302 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
8303 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
8304 tcg_temp_free_i64(tcg_tmp
);
8306 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8309 tcg_temp_free_i32(tcg_res
);
8310 tcg_temp_free_i32(tcg_op1
);
8311 tcg_temp_free_i32(tcg_op2
);
8315 tcg_temp_free_ptr(fpst
);
8317 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
8320 /* AdvSIMD scalar three same
8321 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8322 * +-----+---+-----------+------+---+------+--------+---+------+------+
8323 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8324 * +-----+---+-----------+------+---+------+--------+---+------+------+
8326 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
8328 int rd
= extract32(insn
, 0, 5);
8329 int rn
= extract32(insn
, 5, 5);
8330 int opcode
= extract32(insn
, 11, 5);
8331 int rm
= extract32(insn
, 16, 5);
8332 int size
= extract32(insn
, 22, 2);
8333 bool u
= extract32(insn
, 29, 1);
8336 if (opcode
>= 0x18) {
8337 /* Floating point: U, size[1] and opcode indicate operation */
8338 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
8340 case 0x1b: /* FMULX */
8341 case 0x1f: /* FRECPS */
8342 case 0x3f: /* FRSQRTS */
8343 case 0x5d: /* FACGE */
8344 case 0x7d: /* FACGT */
8345 case 0x1c: /* FCMEQ */
8346 case 0x5c: /* FCMGE */
8347 case 0x7c: /* FCMGT */
8348 case 0x7a: /* FABD */
8351 unallocated_encoding(s
);
8355 if (!fp_access_check(s
)) {
8359 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
8364 case 0x1: /* SQADD, UQADD */
8365 case 0x5: /* SQSUB, UQSUB */
8366 case 0x9: /* SQSHL, UQSHL */
8367 case 0xb: /* SQRSHL, UQRSHL */
8369 case 0x8: /* SSHL, USHL */
8370 case 0xa: /* SRSHL, URSHL */
8371 case 0x6: /* CMGT, CMHI */
8372 case 0x7: /* CMGE, CMHS */
8373 case 0x11: /* CMTST, CMEQ */
8374 case 0x10: /* ADD, SUB (vector) */
8376 unallocated_encoding(s
);
8380 case 0x16: /* SQDMULH, SQRDMULH (vector) */
8381 if (size
!= 1 && size
!= 2) {
8382 unallocated_encoding(s
);
8387 unallocated_encoding(s
);
8391 if (!fp_access_check(s
)) {
8395 tcg_rd
= tcg_temp_new_i64();
8398 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8399 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
8401 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
8402 tcg_temp_free_i64(tcg_rn
);
8403 tcg_temp_free_i64(tcg_rm
);
8405 /* Do a single operation on the lowest element in the vector.
8406 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
8407 * no side effects for all these operations.
8408 * OPTME: special-purpose helpers would avoid doing some
8409 * unnecessary work in the helper for the 8 and 16 bit cases.
8411 NeonGenTwoOpEnvFn
*genenvfn
;
8412 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8413 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
8414 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
8416 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8417 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
8420 case 0x1: /* SQADD, UQADD */
8422 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8423 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
8424 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
8425 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
8427 genenvfn
= fns
[size
][u
];
8430 case 0x5: /* SQSUB, UQSUB */
8432 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8433 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
8434 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
8435 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
8437 genenvfn
= fns
[size
][u
];
8440 case 0x9: /* SQSHL, UQSHL */
8442 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8443 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
8444 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
8445 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
8447 genenvfn
= fns
[size
][u
];
8450 case 0xb: /* SQRSHL, UQRSHL */
8452 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8453 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
8454 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
8455 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
8457 genenvfn
= fns
[size
][u
];
8460 case 0x16: /* SQDMULH, SQRDMULH */
8462 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
8463 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
8464 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
8466 assert(size
== 1 || size
== 2);
8467 genenvfn
= fns
[size
- 1][u
];
8471 g_assert_not_reached();
8474 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
8475 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
8476 tcg_temp_free_i32(tcg_rd32
);
8477 tcg_temp_free_i32(tcg_rn
);
8478 tcg_temp_free_i32(tcg_rm
);
8481 write_fp_dreg(s
, rd
, tcg_rd
);
8483 tcg_temp_free_i64(tcg_rd
);
8486 /* AdvSIMD scalar three same FP16
8487 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
8488 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8489 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
8490 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8491 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
8492 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
8494 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
8497 int rd
= extract32(insn
, 0, 5);
8498 int rn
= extract32(insn
, 5, 5);
8499 int opcode
= extract32(insn
, 11, 3);
8500 int rm
= extract32(insn
, 16, 5);
8501 bool u
= extract32(insn
, 29, 1);
8502 bool a
= extract32(insn
, 23, 1);
8503 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
8510 case 0x03: /* FMULX */
8511 case 0x04: /* FCMEQ (reg) */
8512 case 0x07: /* FRECPS */
8513 case 0x0f: /* FRSQRTS */
8514 case 0x14: /* FCMGE (reg) */
8515 case 0x15: /* FACGE */
8516 case 0x1a: /* FABD */
8517 case 0x1c: /* FCMGT (reg) */
8518 case 0x1d: /* FACGT */
8521 unallocated_encoding(s
);
8525 if (!dc_isar_feature(aa64_fp16
, s
)) {
8526 unallocated_encoding(s
);
8529 if (!fp_access_check(s
)) {
8533 fpst
= get_fpstatus_ptr(true);
8535 tcg_op1
= read_fp_hreg(s
, rn
);
8536 tcg_op2
= read_fp_hreg(s
, rm
);
8537 tcg_res
= tcg_temp_new_i32();
8540 case 0x03: /* FMULX */
8541 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8543 case 0x04: /* FCMEQ (reg) */
8544 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8546 case 0x07: /* FRECPS */
8547 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8549 case 0x0f: /* FRSQRTS */
8550 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8552 case 0x14: /* FCMGE (reg) */
8553 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8555 case 0x15: /* FACGE */
8556 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8558 case 0x1a: /* FABD */
8559 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8560 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
8562 case 0x1c: /* FCMGT (reg) */
8563 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8565 case 0x1d: /* FACGT */
8566 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8569 g_assert_not_reached();
8572 write_fp_sreg(s
, rd
, tcg_res
);
8575 tcg_temp_free_i32(tcg_res
);
8576 tcg_temp_free_i32(tcg_op1
);
8577 tcg_temp_free_i32(tcg_op2
);
8578 tcg_temp_free_ptr(fpst
);
8581 /* AdvSIMD scalar three same extra
8582 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
8583 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
8584 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
8585 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
8587 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
8590 int rd
= extract32(insn
, 0, 5);
8591 int rn
= extract32(insn
, 5, 5);
8592 int opcode
= extract32(insn
, 11, 4);
8593 int rm
= extract32(insn
, 16, 5);
8594 int size
= extract32(insn
, 22, 2);
8595 bool u
= extract32(insn
, 29, 1);
8596 TCGv_i32 ele1
, ele2
, ele3
;
8600 switch (u
* 16 + opcode
) {
8601 case 0x10: /* SQRDMLAH (vector) */
8602 case 0x11: /* SQRDMLSH (vector) */
8603 if (size
!= 1 && size
!= 2) {
8604 unallocated_encoding(s
);
8607 feature
= dc_isar_feature(aa64_rdm
, s
);
8610 unallocated_encoding(s
);
8614 unallocated_encoding(s
);
8617 if (!fp_access_check(s
)) {
8621 /* Do a single operation on the lowest element in the vector.
8622 * We use the standard Neon helpers and rely on 0 OP 0 == 0
8623 * with no side effects for all these operations.
8624 * OPTME: special-purpose helpers would avoid doing some
8625 * unnecessary work in the helper for the 16 bit cases.
8627 ele1
= tcg_temp_new_i32();
8628 ele2
= tcg_temp_new_i32();
8629 ele3
= tcg_temp_new_i32();
8631 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
8632 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
8633 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
8636 case 0x0: /* SQRDMLAH */
8638 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8640 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8643 case 0x1: /* SQRDMLSH */
8645 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8647 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8651 g_assert_not_reached();
8653 tcg_temp_free_i32(ele1
);
8654 tcg_temp_free_i32(ele2
);
8656 res
= tcg_temp_new_i64();
8657 tcg_gen_extu_i32_i64(res
, ele3
);
8658 tcg_temp_free_i32(ele3
);
8660 write_fp_dreg(s
, rd
, res
);
8661 tcg_temp_free_i64(res
);
8664 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
8665 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
8666 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
8668 /* Handle 64->64 opcodes which are shared between the scalar and
8669 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
8670 * is valid in either group and also the double-precision fp ops.
8671 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
8677 case 0x4: /* CLS, CLZ */
8679 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
8681 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
8685 /* This opcode is shared with CNT and RBIT but we have earlier
8686 * enforced that size == 3 if and only if this is the NOT insn.
8688 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
8690 case 0x7: /* SQABS, SQNEG */
8692 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
8694 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
8697 case 0xa: /* CMLT */
8698 /* 64 bit integer comparison against zero, result is
8699 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
8704 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
8705 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8707 case 0x8: /* CMGT, CMGE */
8708 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
8710 case 0x9: /* CMEQ, CMLE */
8711 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
8713 case 0xb: /* ABS, NEG */
8715 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
8717 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8718 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
8719 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
8721 tcg_temp_free_i64(tcg_zero
);
8724 case 0x2f: /* FABS */
8725 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
8727 case 0x6f: /* FNEG */
8728 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
8730 case 0x7f: /* FSQRT */
8731 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
8733 case 0x1a: /* FCVTNS */
8734 case 0x1b: /* FCVTMS */
8735 case 0x1c: /* FCVTAS */
8736 case 0x3a: /* FCVTPS */
8737 case 0x3b: /* FCVTZS */
8739 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8740 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8741 tcg_temp_free_i32(tcg_shift
);
8744 case 0x5a: /* FCVTNU */
8745 case 0x5b: /* FCVTMU */
8746 case 0x5c: /* FCVTAU */
8747 case 0x7a: /* FCVTPU */
8748 case 0x7b: /* FCVTZU */
8750 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8751 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8752 tcg_temp_free_i32(tcg_shift
);
8755 case 0x18: /* FRINTN */
8756 case 0x19: /* FRINTM */
8757 case 0x38: /* FRINTP */
8758 case 0x39: /* FRINTZ */
8759 case 0x58: /* FRINTA */
8760 case 0x79: /* FRINTI */
8761 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
8763 case 0x59: /* FRINTX */
8764 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
8767 g_assert_not_reached();
8771 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
8772 bool is_scalar
, bool is_u
, bool is_q
,
8773 int size
, int rn
, int rd
)
8775 bool is_double
= (size
== MO_64
);
8778 if (!fp_access_check(s
)) {
8782 fpst
= get_fpstatus_ptr(size
== MO_16
);
8785 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8786 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8787 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8788 NeonGenTwoDoubleOPFn
*genfn
;
8793 case 0x2e: /* FCMLT (zero) */
8796 case 0x2c: /* FCMGT (zero) */
8797 genfn
= gen_helper_neon_cgt_f64
;
8799 case 0x2d: /* FCMEQ (zero) */
8800 genfn
= gen_helper_neon_ceq_f64
;
8802 case 0x6d: /* FCMLE (zero) */
8805 case 0x6c: /* FCMGE (zero) */
8806 genfn
= gen_helper_neon_cge_f64
;
8809 g_assert_not_reached();
8812 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8813 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8815 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
8817 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
8819 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8821 tcg_temp_free_i64(tcg_res
);
8822 tcg_temp_free_i64(tcg_zero
);
8823 tcg_temp_free_i64(tcg_op
);
8825 clear_vec_high(s
, !is_scalar
, rd
);
8827 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8828 TCGv_i32 tcg_zero
= tcg_const_i32(0);
8829 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8830 NeonGenTwoSingleOPFn
*genfn
;
8832 int pass
, maxpasses
;
8834 if (size
== MO_16
) {
8836 case 0x2e: /* FCMLT (zero) */
8839 case 0x2c: /* FCMGT (zero) */
8840 genfn
= gen_helper_advsimd_cgt_f16
;
8842 case 0x2d: /* FCMEQ (zero) */
8843 genfn
= gen_helper_advsimd_ceq_f16
;
8845 case 0x6d: /* FCMLE (zero) */
8848 case 0x6c: /* FCMGE (zero) */
8849 genfn
= gen_helper_advsimd_cge_f16
;
8852 g_assert_not_reached();
8856 case 0x2e: /* FCMLT (zero) */
8859 case 0x2c: /* FCMGT (zero) */
8860 genfn
= gen_helper_neon_cgt_f32
;
8862 case 0x2d: /* FCMEQ (zero) */
8863 genfn
= gen_helper_neon_ceq_f32
;
8865 case 0x6d: /* FCMLE (zero) */
8868 case 0x6c: /* FCMGE (zero) */
8869 genfn
= gen_helper_neon_cge_f32
;
8872 g_assert_not_reached();
8879 int vector_size
= 8 << is_q
;
8880 maxpasses
= vector_size
>> size
;
8883 for (pass
= 0; pass
< maxpasses
; pass
++) {
8884 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8886 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
8888 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
8891 write_fp_sreg(s
, rd
, tcg_res
);
8893 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
8896 tcg_temp_free_i32(tcg_res
);
8897 tcg_temp_free_i32(tcg_zero
);
8898 tcg_temp_free_i32(tcg_op
);
8900 clear_vec_high(s
, is_q
, rd
);
8904 tcg_temp_free_ptr(fpst
);
8907 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
8908 bool is_scalar
, bool is_u
, bool is_q
,
8909 int size
, int rn
, int rd
)
8911 bool is_double
= (size
== 3);
8912 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8915 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8916 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8919 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8920 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8922 case 0x3d: /* FRECPE */
8923 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
8925 case 0x3f: /* FRECPX */
8926 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
8928 case 0x7d: /* FRSQRTE */
8929 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
8932 g_assert_not_reached();
8934 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8936 tcg_temp_free_i64(tcg_res
);
8937 tcg_temp_free_i64(tcg_op
);
8938 clear_vec_high(s
, !is_scalar
, rd
);
8940 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8941 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8942 int pass
, maxpasses
;
8947 maxpasses
= is_q
? 4 : 2;
8950 for (pass
= 0; pass
< maxpasses
; pass
++) {
8951 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
8954 case 0x3c: /* URECPE */
8955 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
8957 case 0x3d: /* FRECPE */
8958 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
8960 case 0x3f: /* FRECPX */
8961 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
8963 case 0x7d: /* FRSQRTE */
8964 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
8967 g_assert_not_reached();
8971 write_fp_sreg(s
, rd
, tcg_res
);
8973 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8976 tcg_temp_free_i32(tcg_res
);
8977 tcg_temp_free_i32(tcg_op
);
8979 clear_vec_high(s
, is_q
, rd
);
8982 tcg_temp_free_ptr(fpst
);
8985 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
8986 int opcode
, bool u
, bool is_q
,
8987 int size
, int rn
, int rd
)
8989 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
8990 * in the source becomes a size element in the destination).
8993 TCGv_i32 tcg_res
[2];
8994 int destelt
= is_q
? 2 : 0;
8995 int passes
= scalar
? 1 : 2;
8998 tcg_res
[1] = tcg_const_i32(0);
9001 for (pass
= 0; pass
< passes
; pass
++) {
9002 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9003 NeonGenNarrowFn
*genfn
= NULL
;
9004 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9007 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9009 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9011 tcg_res
[pass
] = tcg_temp_new_i32();
9014 case 0x12: /* XTN, SQXTUN */
9016 static NeonGenNarrowFn
* const xtnfns
[3] = {
9017 gen_helper_neon_narrow_u8
,
9018 gen_helper_neon_narrow_u16
,
9019 tcg_gen_extrl_i64_i32
,
9021 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9022 gen_helper_neon_unarrow_sat8
,
9023 gen_helper_neon_unarrow_sat16
,
9024 gen_helper_neon_unarrow_sat32
,
9027 genenvfn
= sqxtunfns
[size
];
9029 genfn
= xtnfns
[size
];
9033 case 0x14: /* SQXTN, UQXTN */
9035 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9036 { gen_helper_neon_narrow_sat_s8
,
9037 gen_helper_neon_narrow_sat_u8
},
9038 { gen_helper_neon_narrow_sat_s16
,
9039 gen_helper_neon_narrow_sat_u16
},
9040 { gen_helper_neon_narrow_sat_s32
,
9041 gen_helper_neon_narrow_sat_u32
},
9043 genenvfn
= fns
[size
][u
];
9046 case 0x16: /* FCVTN, FCVTN2 */
9047 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9049 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9051 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9052 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9053 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9054 TCGv_i32 ahp
= get_ahp_flag();
9056 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9057 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9058 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9059 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9060 tcg_temp_free_i32(tcg_lo
);
9061 tcg_temp_free_i32(tcg_hi
);
9062 tcg_temp_free_ptr(fpst
);
9063 tcg_temp_free_i32(ahp
);
9066 case 0x56: /* FCVTXN, FCVTXN2 */
9067 /* 64 bit to 32 bit float conversion
9068 * with von Neumann rounding (round to odd)
9071 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9074 g_assert_not_reached();
9078 genfn(tcg_res
[pass
], tcg_op
);
9079 } else if (genenvfn
) {
9080 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9083 tcg_temp_free_i64(tcg_op
);
9086 for (pass
= 0; pass
< 2; pass
++) {
9087 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9088 tcg_temp_free_i32(tcg_res
[pass
]);
9090 clear_vec_high(s
, is_q
, rd
);
9093 /* Remaining saturating accumulating ops */
9094 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9095 bool is_q
, int size
, int rn
, int rd
)
9097 bool is_double
= (size
== 3);
9100 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9101 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9104 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9105 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9106 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9108 if (is_u
) { /* USQADD */
9109 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9110 } else { /* SUQADD */
9111 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9113 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9115 tcg_temp_free_i64(tcg_rd
);
9116 tcg_temp_free_i64(tcg_rn
);
9117 clear_vec_high(s
, !is_scalar
, rd
);
9119 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9120 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9121 int pass
, maxpasses
;
9126 maxpasses
= is_q
? 4 : 2;
9129 for (pass
= 0; pass
< maxpasses
; pass
++) {
9131 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9132 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9134 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9135 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9138 if (is_u
) { /* USQADD */
9141 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9144 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9147 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9150 g_assert_not_reached();
9152 } else { /* SUQADD */
9155 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9158 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9161 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9164 g_assert_not_reached();
9169 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9170 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9171 tcg_temp_free_i64(tcg_zero
);
9173 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9175 tcg_temp_free_i32(tcg_rd
);
9176 tcg_temp_free_i32(tcg_rn
);
9177 clear_vec_high(s
, is_q
, rd
);
9181 /* AdvSIMD scalar two reg misc
9182 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9183 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9184 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9185 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9187 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9189 int rd
= extract32(insn
, 0, 5);
9190 int rn
= extract32(insn
, 5, 5);
9191 int opcode
= extract32(insn
, 12, 5);
9192 int size
= extract32(insn
, 22, 2);
9193 bool u
= extract32(insn
, 29, 1);
9194 bool is_fcvt
= false;
9197 TCGv_ptr tcg_fpstatus
;
9200 case 0x3: /* USQADD / SUQADD*/
9201 if (!fp_access_check(s
)) {
9204 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9206 case 0x7: /* SQABS / SQNEG */
9208 case 0xa: /* CMLT */
9210 unallocated_encoding(s
);
9214 case 0x8: /* CMGT, CMGE */
9215 case 0x9: /* CMEQ, CMLE */
9216 case 0xb: /* ABS, NEG */
9218 unallocated_encoding(s
);
9222 case 0x12: /* SQXTUN */
9224 unallocated_encoding(s
);
9228 case 0x14: /* SQXTN, UQXTN */
9230 unallocated_encoding(s
);
9233 if (!fp_access_check(s
)) {
9236 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9241 /* Floating point: U, size[1] and opcode indicate operation;
9242 * size[0] indicates single or double precision.
9244 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9245 size
= extract32(size
, 0, 1) ? 3 : 2;
9247 case 0x2c: /* FCMGT (zero) */
9248 case 0x2d: /* FCMEQ (zero) */
9249 case 0x2e: /* FCMLT (zero) */
9250 case 0x6c: /* FCMGE (zero) */
9251 case 0x6d: /* FCMLE (zero) */
9252 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
9254 case 0x1d: /* SCVTF */
9255 case 0x5d: /* UCVTF */
9257 bool is_signed
= (opcode
== 0x1d);
9258 if (!fp_access_check(s
)) {
9261 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
9264 case 0x3d: /* FRECPE */
9265 case 0x3f: /* FRECPX */
9266 case 0x7d: /* FRSQRTE */
9267 if (!fp_access_check(s
)) {
9270 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
9272 case 0x1a: /* FCVTNS */
9273 case 0x1b: /* FCVTMS */
9274 case 0x3a: /* FCVTPS */
9275 case 0x3b: /* FCVTZS */
9276 case 0x5a: /* FCVTNU */
9277 case 0x5b: /* FCVTMU */
9278 case 0x7a: /* FCVTPU */
9279 case 0x7b: /* FCVTZU */
9281 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9283 case 0x1c: /* FCVTAS */
9284 case 0x5c: /* FCVTAU */
9285 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
9287 rmode
= FPROUNDING_TIEAWAY
;
9289 case 0x56: /* FCVTXN, FCVTXN2 */
9291 unallocated_encoding(s
);
9294 if (!fp_access_check(s
)) {
9297 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
9300 unallocated_encoding(s
);
9305 unallocated_encoding(s
);
9309 if (!fp_access_check(s
)) {
9314 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9315 tcg_fpstatus
= get_fpstatus_ptr(false);
9316 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9319 tcg_fpstatus
= NULL
;
9323 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9324 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9326 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
9327 write_fp_dreg(s
, rd
, tcg_rd
);
9328 tcg_temp_free_i64(tcg_rd
);
9329 tcg_temp_free_i64(tcg_rn
);
9331 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9332 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9334 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9337 case 0x7: /* SQABS, SQNEG */
9339 NeonGenOneOpEnvFn
*genfn
;
9340 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
9341 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
9342 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
9343 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
9345 genfn
= fns
[size
][u
];
9346 genfn(tcg_rd
, cpu_env
, tcg_rn
);
9349 case 0x1a: /* FCVTNS */
9350 case 0x1b: /* FCVTMS */
9351 case 0x1c: /* FCVTAS */
9352 case 0x3a: /* FCVTPS */
9353 case 0x3b: /* FCVTZS */
9355 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9356 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9357 tcg_temp_free_i32(tcg_shift
);
9360 case 0x5a: /* FCVTNU */
9361 case 0x5b: /* FCVTMU */
9362 case 0x5c: /* FCVTAU */
9363 case 0x7a: /* FCVTPU */
9364 case 0x7b: /* FCVTZU */
9366 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9367 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9368 tcg_temp_free_i32(tcg_shift
);
9372 g_assert_not_reached();
9375 write_fp_sreg(s
, rd
, tcg_rd
);
9376 tcg_temp_free_i32(tcg_rd
);
9377 tcg_temp_free_i32(tcg_rn
);
9381 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9382 tcg_temp_free_i32(tcg_rmode
);
9383 tcg_temp_free_ptr(tcg_fpstatus
);
9387 static void gen_ssra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9389 tcg_gen_vec_sar8i_i64(a
, a
, shift
);
9390 tcg_gen_vec_add8_i64(d
, d
, a
);
9393 static void gen_ssra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9395 tcg_gen_vec_sar16i_i64(a
, a
, shift
);
9396 tcg_gen_vec_add16_i64(d
, d
, a
);
9399 static void gen_ssra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
9401 tcg_gen_sari_i32(a
, a
, shift
);
9402 tcg_gen_add_i32(d
, d
, a
);
9405 static void gen_ssra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9407 tcg_gen_sari_i64(a
, a
, shift
);
9408 tcg_gen_add_i64(d
, d
, a
);
9411 static void gen_ssra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
9413 tcg_gen_sari_vec(vece
, a
, a
, sh
);
9414 tcg_gen_add_vec(vece
, d
, d
, a
);
9417 static void gen_usra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9419 tcg_gen_vec_shr8i_i64(a
, a
, shift
);
9420 tcg_gen_vec_add8_i64(d
, d
, a
);
9423 static void gen_usra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9425 tcg_gen_vec_shr16i_i64(a
, a
, shift
);
9426 tcg_gen_vec_add16_i64(d
, d
, a
);
9429 static void gen_usra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
9431 tcg_gen_shri_i32(a
, a
, shift
);
9432 tcg_gen_add_i32(d
, d
, a
);
9435 static void gen_usra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9437 tcg_gen_shri_i64(a
, a
, shift
);
9438 tcg_gen_add_i64(d
, d
, a
);
9441 static void gen_usra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
9443 tcg_gen_shri_vec(vece
, a
, a
, sh
);
9444 tcg_gen_add_vec(vece
, d
, d
, a
);
9447 static void gen_shr8_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9449 uint64_t mask
= dup_const(MO_8
, 0xff >> shift
);
9450 TCGv_i64 t
= tcg_temp_new_i64();
9452 tcg_gen_shri_i64(t
, a
, shift
);
9453 tcg_gen_andi_i64(t
, t
, mask
);
9454 tcg_gen_andi_i64(d
, d
, ~mask
);
9455 tcg_gen_or_i64(d
, d
, t
);
9456 tcg_temp_free_i64(t
);
9459 static void gen_shr16_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9461 uint64_t mask
= dup_const(MO_16
, 0xffff >> shift
);
9462 TCGv_i64 t
= tcg_temp_new_i64();
9464 tcg_gen_shri_i64(t
, a
, shift
);
9465 tcg_gen_andi_i64(t
, t
, mask
);
9466 tcg_gen_andi_i64(d
, d
, ~mask
);
9467 tcg_gen_or_i64(d
, d
, t
);
9468 tcg_temp_free_i64(t
);
9471 static void gen_shr32_ins_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
9473 tcg_gen_shri_i32(a
, a
, shift
);
9474 tcg_gen_deposit_i32(d
, d
, a
, 0, 32 - shift
);
9477 static void gen_shr64_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9479 tcg_gen_shri_i64(a
, a
, shift
);
9480 tcg_gen_deposit_i64(d
, d
, a
, 0, 64 - shift
);
9483 static void gen_shr_ins_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
9485 uint64_t mask
= (2ull << ((8 << vece
) - 1)) - 1;
9486 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
9487 TCGv_vec m
= tcg_temp_new_vec_matching(d
);
9489 tcg_gen_dupi_vec(vece
, m
, mask
^ (mask
>> sh
));
9490 tcg_gen_shri_vec(vece
, t
, a
, sh
);
9491 tcg_gen_and_vec(vece
, d
, d
, m
);
9492 tcg_gen_or_vec(vece
, d
, d
, t
);
9494 tcg_temp_free_vec(t
);
9495 tcg_temp_free_vec(m
);
9498 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
9499 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
9500 int immh
, int immb
, int opcode
, int rn
, int rd
)
9502 static const GVecGen2i ssra_op
[4] = {
9503 { .fni8
= gen_ssra8_i64
,
9504 .fniv
= gen_ssra_vec
,
9506 .opc
= INDEX_op_sari_vec
,
9508 { .fni8
= gen_ssra16_i64
,
9509 .fniv
= gen_ssra_vec
,
9511 .opc
= INDEX_op_sari_vec
,
9513 { .fni4
= gen_ssra32_i32
,
9514 .fniv
= gen_ssra_vec
,
9516 .opc
= INDEX_op_sari_vec
,
9518 { .fni8
= gen_ssra64_i64
,
9519 .fniv
= gen_ssra_vec
,
9520 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9522 .opc
= INDEX_op_sari_vec
,
9525 static const GVecGen2i usra_op
[4] = {
9526 { .fni8
= gen_usra8_i64
,
9527 .fniv
= gen_usra_vec
,
9529 .opc
= INDEX_op_shri_vec
,
9531 { .fni8
= gen_usra16_i64
,
9532 .fniv
= gen_usra_vec
,
9534 .opc
= INDEX_op_shri_vec
,
9536 { .fni4
= gen_usra32_i32
,
9537 .fniv
= gen_usra_vec
,
9539 .opc
= INDEX_op_shri_vec
,
9541 { .fni8
= gen_usra64_i64
,
9542 .fniv
= gen_usra_vec
,
9543 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9545 .opc
= INDEX_op_shri_vec
,
9548 static const GVecGen2i sri_op
[4] = {
9549 { .fni8
= gen_shr8_ins_i64
,
9550 .fniv
= gen_shr_ins_vec
,
9552 .opc
= INDEX_op_shri_vec
,
9554 { .fni8
= gen_shr16_ins_i64
,
9555 .fniv
= gen_shr_ins_vec
,
9557 .opc
= INDEX_op_shri_vec
,
9559 { .fni4
= gen_shr32_ins_i32
,
9560 .fniv
= gen_shr_ins_vec
,
9562 .opc
= INDEX_op_shri_vec
,
9564 { .fni8
= gen_shr64_ins_i64
,
9565 .fniv
= gen_shr_ins_vec
,
9566 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9568 .opc
= INDEX_op_shri_vec
,
9572 int size
= 32 - clz32(immh
) - 1;
9573 int immhb
= immh
<< 3 | immb
;
9574 int shift
= 2 * (8 << size
) - immhb
;
9575 bool accumulate
= false;
9576 int dsize
= is_q
? 128 : 64;
9577 int esize
= 8 << size
;
9578 int elements
= dsize
/esize
;
9579 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
9580 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9581 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9583 uint64_t round_const
;
9586 if (extract32(immh
, 3, 1) && !is_q
) {
9587 unallocated_encoding(s
);
9590 tcg_debug_assert(size
<= 3);
9592 if (!fp_access_check(s
)) {
9597 case 0x02: /* SSRA / USRA (accumulate) */
9599 /* Shift count same as element size produces zero to add. */
9600 if (shift
== 8 << size
) {
9603 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
9605 /* Shift count same as element size produces all sign to add. */
9606 if (shift
== 8 << size
) {
9609 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
9612 case 0x08: /* SRI */
9613 /* Shift count same as element size is valid but does nothing. */
9614 if (shift
== 8 << size
) {
9617 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
9620 case 0x00: /* SSHR / USHR */
9622 if (shift
== 8 << size
) {
9623 /* Shift count the same size as element size produces zero. */
9624 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
9625 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
9627 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
9630 /* Shift count the same size as element size produces all sign. */
9631 if (shift
== 8 << size
) {
9634 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
9638 case 0x04: /* SRSHR / URSHR (rounding) */
9640 case 0x06: /* SRSRA / URSRA (accum + rounding) */
9644 g_assert_not_reached();
9647 round_const
= 1ULL << (shift
- 1);
9648 tcg_round
= tcg_const_i64(round_const
);
9650 for (i
= 0; i
< elements
; i
++) {
9651 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
9653 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
9656 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
9657 accumulate
, is_u
, size
, shift
);
9659 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
9661 tcg_temp_free_i64(tcg_round
);
9664 clear_vec_high(s
, is_q
, rd
);
9667 static void gen_shl8_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9669 uint64_t mask
= dup_const(MO_8
, 0xff << shift
);
9670 TCGv_i64 t
= tcg_temp_new_i64();
9672 tcg_gen_shli_i64(t
, a
, shift
);
9673 tcg_gen_andi_i64(t
, t
, mask
);
9674 tcg_gen_andi_i64(d
, d
, ~mask
);
9675 tcg_gen_or_i64(d
, d
, t
);
9676 tcg_temp_free_i64(t
);
9679 static void gen_shl16_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9681 uint64_t mask
= dup_const(MO_16
, 0xffff << shift
);
9682 TCGv_i64 t
= tcg_temp_new_i64();
9684 tcg_gen_shli_i64(t
, a
, shift
);
9685 tcg_gen_andi_i64(t
, t
, mask
);
9686 tcg_gen_andi_i64(d
, d
, ~mask
);
9687 tcg_gen_or_i64(d
, d
, t
);
9688 tcg_temp_free_i64(t
);
9691 static void gen_shl32_ins_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
9693 tcg_gen_deposit_i32(d
, d
, a
, shift
, 32 - shift
);
9696 static void gen_shl64_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9698 tcg_gen_deposit_i64(d
, d
, a
, shift
, 64 - shift
);
9701 static void gen_shl_ins_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
9703 uint64_t mask
= (1ull << sh
) - 1;
9704 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
9705 TCGv_vec m
= tcg_temp_new_vec_matching(d
);
9707 tcg_gen_dupi_vec(vece
, m
, mask
);
9708 tcg_gen_shli_vec(vece
, t
, a
, sh
);
9709 tcg_gen_and_vec(vece
, d
, d
, m
);
9710 tcg_gen_or_vec(vece
, d
, d
, t
);
9712 tcg_temp_free_vec(t
);
9713 tcg_temp_free_vec(m
);
9716 /* SHL/SLI - Vector shift left */
9717 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
9718 int immh
, int immb
, int opcode
, int rn
, int rd
)
9720 static const GVecGen2i shi_op
[4] = {
9721 { .fni8
= gen_shl8_ins_i64
,
9722 .fniv
= gen_shl_ins_vec
,
9723 .opc
= INDEX_op_shli_vec
,
9724 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9727 { .fni8
= gen_shl16_ins_i64
,
9728 .fniv
= gen_shl_ins_vec
,
9729 .opc
= INDEX_op_shli_vec
,
9730 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9733 { .fni4
= gen_shl32_ins_i32
,
9734 .fniv
= gen_shl_ins_vec
,
9735 .opc
= INDEX_op_shli_vec
,
9736 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9739 { .fni8
= gen_shl64_ins_i64
,
9740 .fniv
= gen_shl_ins_vec
,
9741 .opc
= INDEX_op_shli_vec
,
9742 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9746 int size
= 32 - clz32(immh
) - 1;
9747 int immhb
= immh
<< 3 | immb
;
9748 int shift
= immhb
- (8 << size
);
9750 if (extract32(immh
, 3, 1) && !is_q
) {
9751 unallocated_encoding(s
);
9755 if (size
> 3 && !is_q
) {
9756 unallocated_encoding(s
);
9760 if (!fp_access_check(s
)) {
9765 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &shi_op
[size
]);
9767 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
9771 /* USHLL/SHLL - Vector shift left with widening */
9772 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
9773 int immh
, int immb
, int opcode
, int rn
, int rd
)
9775 int size
= 32 - clz32(immh
) - 1;
9776 int immhb
= immh
<< 3 | immb
;
9777 int shift
= immhb
- (8 << size
);
9779 int esize
= 8 << size
;
9780 int elements
= dsize
/esize
;
9781 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9782 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9786 unallocated_encoding(s
);
9790 if (!fp_access_check(s
)) {
9794 /* For the LL variants the store is larger than the load,
9795 * so if rd == rn we would overwrite parts of our input.
9796 * So load everything right now and use shifts in the main loop.
9798 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
9800 for (i
= 0; i
< elements
; i
++) {
9801 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
9802 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
9803 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
9804 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
9808 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
9809 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
9810 int immh
, int immb
, int opcode
, int rn
, int rd
)
9812 int immhb
= immh
<< 3 | immb
;
9813 int size
= 32 - clz32(immh
) - 1;
9815 int esize
= 8 << size
;
9816 int elements
= dsize
/esize
;
9817 int shift
= (2 * esize
) - immhb
;
9818 bool round
= extract32(opcode
, 0, 1);
9819 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
9823 if (extract32(immh
, 3, 1)) {
9824 unallocated_encoding(s
);
9828 if (!fp_access_check(s
)) {
9832 tcg_rn
= tcg_temp_new_i64();
9833 tcg_rd
= tcg_temp_new_i64();
9834 tcg_final
= tcg_temp_new_i64();
9835 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
9838 uint64_t round_const
= 1ULL << (shift
- 1);
9839 tcg_round
= tcg_const_i64(round_const
);
9844 for (i
= 0; i
< elements
; i
++) {
9845 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
9846 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
9847 false, true, size
+1, shift
);
9849 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
9853 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
9855 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
9858 tcg_temp_free_i64(tcg_round
);
9860 tcg_temp_free_i64(tcg_rn
);
9861 tcg_temp_free_i64(tcg_rd
);
9862 tcg_temp_free_i64(tcg_final
);
9864 clear_vec_high(s
, is_q
, rd
);
9868 /* AdvSIMD shift by immediate
9869 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
9870 * +---+---+---+-------------+------+------+--------+---+------+------+
9871 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
9872 * +---+---+---+-------------+------+------+--------+---+------+------+
9874 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
9876 int rd
= extract32(insn
, 0, 5);
9877 int rn
= extract32(insn
, 5, 5);
9878 int opcode
= extract32(insn
, 11, 5);
9879 int immb
= extract32(insn
, 16, 3);
9880 int immh
= extract32(insn
, 19, 4);
9881 bool is_u
= extract32(insn
, 29, 1);
9882 bool is_q
= extract32(insn
, 30, 1);
9885 case 0x08: /* SRI */
9887 unallocated_encoding(s
);
9891 case 0x00: /* SSHR / USHR */
9892 case 0x02: /* SSRA / USRA (accumulate) */
9893 case 0x04: /* SRSHR / URSHR (rounding) */
9894 case 0x06: /* SRSRA / URSRA (accum + rounding) */
9895 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9897 case 0x0a: /* SHL / SLI */
9898 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9900 case 0x10: /* SHRN */
9901 case 0x11: /* RSHRN / SQRSHRUN */
9903 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
9906 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
9909 case 0x12: /* SQSHRN / UQSHRN */
9910 case 0x13: /* SQRSHRN / UQRSHRN */
9911 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
9914 case 0x14: /* SSHLL / USHLL */
9915 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9917 case 0x1c: /* SCVTF / UCVTF */
9918 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
9921 case 0xc: /* SQSHLU */
9923 unallocated_encoding(s
);
9926 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
9928 case 0xe: /* SQSHL, UQSHL */
9929 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
9931 case 0x1f: /* FCVTZS/ FCVTZU */
9932 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
9935 unallocated_encoding(s
);
9940 /* Generate code to do a "long" addition or subtraction, ie one done in
9941 * TCGv_i64 on vector lanes twice the width specified by size.
9943 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
9944 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
9946 static NeonGenTwo64OpFn
* const fns
[3][2] = {
9947 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
9948 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
9949 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
9951 NeonGenTwo64OpFn
*genfn
;
9954 genfn
= fns
[size
][is_sub
];
9955 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9958 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
9959 int opcode
, int rd
, int rn
, int rm
)
9961 /* 3-reg-different widening insns: 64 x 64 -> 128 */
9962 TCGv_i64 tcg_res
[2];
9965 tcg_res
[0] = tcg_temp_new_i64();
9966 tcg_res
[1] = tcg_temp_new_i64();
9968 /* Does this op do an adding accumulate, a subtracting accumulate,
9969 * or no accumulate at all?
9987 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9988 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9991 /* size == 2 means two 32x32->64 operations; this is worth special
9992 * casing because we can generally handle it inline.
9995 for (pass
= 0; pass
< 2; pass
++) {
9996 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9997 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9998 TCGv_i64 tcg_passres
;
9999 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10001 int elt
= pass
+ is_q
* 2;
10003 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10004 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10007 tcg_passres
= tcg_res
[pass
];
10009 tcg_passres
= tcg_temp_new_i64();
10013 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10014 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10016 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10017 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10019 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10020 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10022 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10023 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10025 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10026 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10027 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10029 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10030 tcg_temp_free_i64(tcg_tmp1
);
10031 tcg_temp_free_i64(tcg_tmp2
);
10034 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10035 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10036 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10037 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10039 case 9: /* SQDMLAL, SQDMLAL2 */
10040 case 11: /* SQDMLSL, SQDMLSL2 */
10041 case 13: /* SQDMULL, SQDMULL2 */
10042 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10043 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10044 tcg_passres
, tcg_passres
);
10047 g_assert_not_reached();
10050 if (opcode
== 9 || opcode
== 11) {
10051 /* saturating accumulate ops */
10053 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10055 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10056 tcg_res
[pass
], tcg_passres
);
10057 } else if (accop
> 0) {
10058 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10059 } else if (accop
< 0) {
10060 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10064 tcg_temp_free_i64(tcg_passres
);
10067 tcg_temp_free_i64(tcg_op1
);
10068 tcg_temp_free_i64(tcg_op2
);
10071 /* size 0 or 1, generally helper functions */
10072 for (pass
= 0; pass
< 2; pass
++) {
10073 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10074 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10075 TCGv_i64 tcg_passres
;
10076 int elt
= pass
+ is_q
* 2;
10078 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10079 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10082 tcg_passres
= tcg_res
[pass
];
10084 tcg_passres
= tcg_temp_new_i64();
10088 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10089 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10091 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10092 static NeonGenWidenFn
* const widenfns
[2][2] = {
10093 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10094 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10096 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10098 widenfn(tcg_op2_64
, tcg_op2
);
10099 widenfn(tcg_passres
, tcg_op1
);
10100 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10101 tcg_passres
, tcg_op2_64
);
10102 tcg_temp_free_i64(tcg_op2_64
);
10105 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10106 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10109 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10111 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10115 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10117 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10121 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10122 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10123 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10126 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10128 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10132 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10134 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10138 case 9: /* SQDMLAL, SQDMLAL2 */
10139 case 11: /* SQDMLSL, SQDMLSL2 */
10140 case 13: /* SQDMULL, SQDMULL2 */
10142 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10143 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10144 tcg_passres
, tcg_passres
);
10146 case 14: /* PMULL */
10148 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
10151 g_assert_not_reached();
10153 tcg_temp_free_i32(tcg_op1
);
10154 tcg_temp_free_i32(tcg_op2
);
10157 if (opcode
== 9 || opcode
== 11) {
10158 /* saturating accumulate ops */
10160 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10162 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10166 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10167 tcg_res
[pass
], tcg_passres
);
10169 tcg_temp_free_i64(tcg_passres
);
10174 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10175 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10176 tcg_temp_free_i64(tcg_res
[0]);
10177 tcg_temp_free_i64(tcg_res
[1]);
10180 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10181 int opcode
, int rd
, int rn
, int rm
)
10183 TCGv_i64 tcg_res
[2];
10184 int part
= is_q
? 2 : 0;
10187 for (pass
= 0; pass
< 2; pass
++) {
10188 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10189 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10190 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10191 static NeonGenWidenFn
* const widenfns
[3][2] = {
10192 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10193 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10194 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10196 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10198 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10199 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10200 widenfn(tcg_op2_wide
, tcg_op2
);
10201 tcg_temp_free_i32(tcg_op2
);
10202 tcg_res
[pass
] = tcg_temp_new_i64();
10203 gen_neon_addl(size
, (opcode
== 3),
10204 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10205 tcg_temp_free_i64(tcg_op1
);
10206 tcg_temp_free_i64(tcg_op2_wide
);
10209 for (pass
= 0; pass
< 2; pass
++) {
10210 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10211 tcg_temp_free_i64(tcg_res
[pass
]);
10215 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10217 tcg_gen_addi_i64(in
, in
, 1U << 31);
10218 tcg_gen_extrh_i64_i32(res
, in
);
10221 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10222 int opcode
, int rd
, int rn
, int rm
)
10224 TCGv_i32 tcg_res
[2];
10225 int part
= is_q
? 2 : 0;
10228 for (pass
= 0; pass
< 2; pass
++) {
10229 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10230 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10231 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10232 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10233 { gen_helper_neon_narrow_high_u8
,
10234 gen_helper_neon_narrow_round_high_u8
},
10235 { gen_helper_neon_narrow_high_u16
,
10236 gen_helper_neon_narrow_round_high_u16
},
10237 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10239 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10241 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10242 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10244 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10246 tcg_temp_free_i64(tcg_op1
);
10247 tcg_temp_free_i64(tcg_op2
);
10249 tcg_res
[pass
] = tcg_temp_new_i32();
10250 gennarrow(tcg_res
[pass
], tcg_wideres
);
10251 tcg_temp_free_i64(tcg_wideres
);
10254 for (pass
= 0; pass
< 2; pass
++) {
10255 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10256 tcg_temp_free_i32(tcg_res
[pass
]);
10258 clear_vec_high(s
, is_q
, rd
);
10261 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
10263 /* PMULL of 64 x 64 -> 128 is an odd special case because it
10264 * is the only three-reg-diff instruction which produces a
10265 * 128-bit wide result from a single operation. However since
10266 * it's possible to calculate the two halves more or less
10267 * separately we just use two helper calls.
10269 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10270 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10271 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10273 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
10274 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
10275 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
10276 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
10277 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
10278 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
10280 tcg_temp_free_i64(tcg_op1
);
10281 tcg_temp_free_i64(tcg_op2
);
10282 tcg_temp_free_i64(tcg_res
);
10285 /* AdvSIMD three different
10286 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10287 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10288 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10289 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10291 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10293 /* Instructions in this group fall into three basic classes
10294 * (in each case with the operation working on each element in
10295 * the input vectors):
10296 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10298 * (2) wide 64 x 128 -> 128
10299 * (3) narrowing 128 x 128 -> 64
10300 * Here we do initial decode, catch unallocated cases and
10301 * dispatch to separate functions for each class.
10303 int is_q
= extract32(insn
, 30, 1);
10304 int is_u
= extract32(insn
, 29, 1);
10305 int size
= extract32(insn
, 22, 2);
10306 int opcode
= extract32(insn
, 12, 4);
10307 int rm
= extract32(insn
, 16, 5);
10308 int rn
= extract32(insn
, 5, 5);
10309 int rd
= extract32(insn
, 0, 5);
10312 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10313 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10314 /* 64 x 128 -> 128 */
10316 unallocated_encoding(s
);
10319 if (!fp_access_check(s
)) {
10322 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10324 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10325 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10326 /* 128 x 128 -> 64 */
10328 unallocated_encoding(s
);
10331 if (!fp_access_check(s
)) {
10334 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10336 case 14: /* PMULL, PMULL2 */
10337 if (is_u
|| size
== 1 || size
== 2) {
10338 unallocated_encoding(s
);
10342 if (!dc_isar_feature(aa64_pmull
, s
)) {
10343 unallocated_encoding(s
);
10346 if (!fp_access_check(s
)) {
10349 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
10353 case 9: /* SQDMLAL, SQDMLAL2 */
10354 case 11: /* SQDMLSL, SQDMLSL2 */
10355 case 13: /* SQDMULL, SQDMULL2 */
10356 if (is_u
|| size
== 0) {
10357 unallocated_encoding(s
);
10361 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10362 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10363 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10364 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10365 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10366 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10367 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10368 /* 64 x 64 -> 128 */
10370 unallocated_encoding(s
);
10374 if (!fp_access_check(s
)) {
10378 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10381 /* opcode 15 not allocated */
10382 unallocated_encoding(s
);
10387 static void gen_bsl_i64(TCGv_i64 rd
, TCGv_i64 rn
, TCGv_i64 rm
)
10389 tcg_gen_xor_i64(rn
, rn
, rm
);
10390 tcg_gen_and_i64(rn
, rn
, rd
);
10391 tcg_gen_xor_i64(rd
, rm
, rn
);
10394 static void gen_bit_i64(TCGv_i64 rd
, TCGv_i64 rn
, TCGv_i64 rm
)
10396 tcg_gen_xor_i64(rn
, rn
, rd
);
10397 tcg_gen_and_i64(rn
, rn
, rm
);
10398 tcg_gen_xor_i64(rd
, rd
, rn
);
10401 static void gen_bif_i64(TCGv_i64 rd
, TCGv_i64 rn
, TCGv_i64 rm
)
10403 tcg_gen_xor_i64(rn
, rn
, rd
);
10404 tcg_gen_andc_i64(rn
, rn
, rm
);
10405 tcg_gen_xor_i64(rd
, rd
, rn
);
10408 static void gen_bsl_vec(unsigned vece
, TCGv_vec rd
, TCGv_vec rn
, TCGv_vec rm
)
10410 tcg_gen_xor_vec(vece
, rn
, rn
, rm
);
10411 tcg_gen_and_vec(vece
, rn
, rn
, rd
);
10412 tcg_gen_xor_vec(vece
, rd
, rm
, rn
);
10415 static void gen_bit_vec(unsigned vece
, TCGv_vec rd
, TCGv_vec rn
, TCGv_vec rm
)
10417 tcg_gen_xor_vec(vece
, rn
, rn
, rd
);
10418 tcg_gen_and_vec(vece
, rn
, rn
, rm
);
10419 tcg_gen_xor_vec(vece
, rd
, rd
, rn
);
10422 static void gen_bif_vec(unsigned vece
, TCGv_vec rd
, TCGv_vec rn
, TCGv_vec rm
)
10424 tcg_gen_xor_vec(vece
, rn
, rn
, rd
);
10425 tcg_gen_andc_vec(vece
, rn
, rn
, rm
);
10426 tcg_gen_xor_vec(vece
, rd
, rd
, rn
);
10429 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10430 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10432 static const GVecGen3 bsl_op
= {
10433 .fni8
= gen_bsl_i64
,
10434 .fniv
= gen_bsl_vec
,
10435 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10438 static const GVecGen3 bit_op
= {
10439 .fni8
= gen_bit_i64
,
10440 .fniv
= gen_bit_vec
,
10441 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10444 static const GVecGen3 bif_op
= {
10445 .fni8
= gen_bif_i64
,
10446 .fniv
= gen_bif_vec
,
10447 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10451 int rd
= extract32(insn
, 0, 5);
10452 int rn
= extract32(insn
, 5, 5);
10453 int rm
= extract32(insn
, 16, 5);
10454 int size
= extract32(insn
, 22, 2);
10455 bool is_u
= extract32(insn
, 29, 1);
10456 bool is_q
= extract32(insn
, 30, 1);
10458 if (!fp_access_check(s
)) {
10462 switch (size
+ 4 * is_u
) {
10464 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10467 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10470 if (rn
== rm
) { /* MOV */
10471 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_mov
, 0);
10473 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10477 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10480 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10483 case 5: /* BSL bitwise select */
10484 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bsl_op
);
10486 case 6: /* BIT, bitwise insert if true */
10487 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bit_op
);
10489 case 7: /* BIF, bitwise insert if false */
10490 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bif_op
);
10494 g_assert_not_reached();
10498 /* Pairwise op subgroup of C3.6.16.
10500 * This is called directly or via the handle_3same_float for float pairwise
10501 * operations where the opcode and size are calculated differently.
10503 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10504 int size
, int rn
, int rm
, int rd
)
10509 /* Floating point operations need fpst */
10510 if (opcode
>= 0x58) {
10511 fpst
= get_fpstatus_ptr(false);
10516 if (!fp_access_check(s
)) {
10520 /* These operations work on the concatenated rm:rn, with each pair of
10521 * adjacent elements being operated on to produce an element in the result.
10524 TCGv_i64 tcg_res
[2];
10526 for (pass
= 0; pass
< 2; pass
++) {
10527 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10528 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10529 int passreg
= (pass
== 0) ? rn
: rm
;
10531 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10532 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10533 tcg_res
[pass
] = tcg_temp_new_i64();
10536 case 0x17: /* ADDP */
10537 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10539 case 0x58: /* FMAXNMP */
10540 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10542 case 0x5a: /* FADDP */
10543 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10545 case 0x5e: /* FMAXP */
10546 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10548 case 0x78: /* FMINNMP */
10549 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10551 case 0x7e: /* FMINP */
10552 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10555 g_assert_not_reached();
10558 tcg_temp_free_i64(tcg_op1
);
10559 tcg_temp_free_i64(tcg_op2
);
10562 for (pass
= 0; pass
< 2; pass
++) {
10563 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10564 tcg_temp_free_i64(tcg_res
[pass
]);
10567 int maxpass
= is_q
? 4 : 2;
10568 TCGv_i32 tcg_res
[4];
10570 for (pass
= 0; pass
< maxpass
; pass
++) {
10571 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10572 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10573 NeonGenTwoOpFn
*genfn
= NULL
;
10574 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10575 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10577 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10578 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10579 tcg_res
[pass
] = tcg_temp_new_i32();
10582 case 0x17: /* ADDP */
10584 static NeonGenTwoOpFn
* const fns
[3] = {
10585 gen_helper_neon_padd_u8
,
10586 gen_helper_neon_padd_u16
,
10592 case 0x14: /* SMAXP, UMAXP */
10594 static NeonGenTwoOpFn
* const fns
[3][2] = {
10595 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10596 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10597 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10599 genfn
= fns
[size
][u
];
10602 case 0x15: /* SMINP, UMINP */
10604 static NeonGenTwoOpFn
* const fns
[3][2] = {
10605 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
10606 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
10607 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10609 genfn
= fns
[size
][u
];
10612 /* The FP operations are all on single floats (32 bit) */
10613 case 0x58: /* FMAXNMP */
10614 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10616 case 0x5a: /* FADDP */
10617 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10619 case 0x5e: /* FMAXP */
10620 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10622 case 0x78: /* FMINNMP */
10623 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10625 case 0x7e: /* FMINP */
10626 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10629 g_assert_not_reached();
10632 /* FP ops called directly, otherwise call now */
10634 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10637 tcg_temp_free_i32(tcg_op1
);
10638 tcg_temp_free_i32(tcg_op2
);
10641 for (pass
= 0; pass
< maxpass
; pass
++) {
10642 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
10643 tcg_temp_free_i32(tcg_res
[pass
]);
10645 clear_vec_high(s
, is_q
, rd
);
10649 tcg_temp_free_ptr(fpst
);
10653 /* Floating point op subgroup of C3.6.16. */
10654 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
10656 /* For floating point ops, the U, size[1] and opcode bits
10657 * together indicate the operation. size[0] indicates single
10660 int fpopcode
= extract32(insn
, 11, 5)
10661 | (extract32(insn
, 23, 1) << 5)
10662 | (extract32(insn
, 29, 1) << 6);
10663 int is_q
= extract32(insn
, 30, 1);
10664 int size
= extract32(insn
, 22, 1);
10665 int rm
= extract32(insn
, 16, 5);
10666 int rn
= extract32(insn
, 5, 5);
10667 int rd
= extract32(insn
, 0, 5);
10669 int datasize
= is_q
? 128 : 64;
10670 int esize
= 32 << size
;
10671 int elements
= datasize
/ esize
;
10673 if (size
== 1 && !is_q
) {
10674 unallocated_encoding(s
);
10678 switch (fpopcode
) {
10679 case 0x58: /* FMAXNMP */
10680 case 0x5a: /* FADDP */
10681 case 0x5e: /* FMAXP */
10682 case 0x78: /* FMINNMP */
10683 case 0x7e: /* FMINP */
10684 if (size
&& !is_q
) {
10685 unallocated_encoding(s
);
10688 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
10691 case 0x1b: /* FMULX */
10692 case 0x1f: /* FRECPS */
10693 case 0x3f: /* FRSQRTS */
10694 case 0x5d: /* FACGE */
10695 case 0x7d: /* FACGT */
10696 case 0x19: /* FMLA */
10697 case 0x39: /* FMLS */
10698 case 0x18: /* FMAXNM */
10699 case 0x1a: /* FADD */
10700 case 0x1c: /* FCMEQ */
10701 case 0x1e: /* FMAX */
10702 case 0x38: /* FMINNM */
10703 case 0x3a: /* FSUB */
10704 case 0x3e: /* FMIN */
10705 case 0x5b: /* FMUL */
10706 case 0x5c: /* FCMGE */
10707 case 0x5f: /* FDIV */
10708 case 0x7a: /* FABD */
10709 case 0x7c: /* FCMGT */
10710 if (!fp_access_check(s
)) {
10714 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
10717 unallocated_encoding(s
);
10722 static void gen_mla8_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10724 gen_helper_neon_mul_u8(a
, a
, b
);
10725 gen_helper_neon_add_u8(d
, d
, a
);
10728 static void gen_mla16_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10730 gen_helper_neon_mul_u16(a
, a
, b
);
10731 gen_helper_neon_add_u16(d
, d
, a
);
10734 static void gen_mla32_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10736 tcg_gen_mul_i32(a
, a
, b
);
10737 tcg_gen_add_i32(d
, d
, a
);
10740 static void gen_mla64_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
10742 tcg_gen_mul_i64(a
, a
, b
);
10743 tcg_gen_add_i64(d
, d
, a
);
10746 static void gen_mla_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
10748 tcg_gen_mul_vec(vece
, a
, a
, b
);
10749 tcg_gen_add_vec(vece
, d
, d
, a
);
10752 static void gen_mls8_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10754 gen_helper_neon_mul_u8(a
, a
, b
);
10755 gen_helper_neon_sub_u8(d
, d
, a
);
10758 static void gen_mls16_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10760 gen_helper_neon_mul_u16(a
, a
, b
);
10761 gen_helper_neon_sub_u16(d
, d
, a
);
10764 static void gen_mls32_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10766 tcg_gen_mul_i32(a
, a
, b
);
10767 tcg_gen_sub_i32(d
, d
, a
);
10770 static void gen_mls64_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
10772 tcg_gen_mul_i64(a
, a
, b
);
10773 tcg_gen_sub_i64(d
, d
, a
);
10776 static void gen_mls_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
10778 tcg_gen_mul_vec(vece
, a
, a
, b
);
10779 tcg_gen_sub_vec(vece
, d
, d
, a
);
10782 /* Integer op subgroup of C3.6.16. */
10783 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
10785 static const GVecGen3 cmtst_op
[4] = {
10786 { .fni4
= gen_helper_neon_tst_u8
,
10787 .fniv
= gen_cmtst_vec
,
10789 { .fni4
= gen_helper_neon_tst_u16
,
10790 .fniv
= gen_cmtst_vec
,
10792 { .fni4
= gen_cmtst_i32
,
10793 .fniv
= gen_cmtst_vec
,
10795 { .fni8
= gen_cmtst_i64
,
10796 .fniv
= gen_cmtst_vec
,
10797 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10800 static const GVecGen3 mla_op
[4] = {
10801 { .fni4
= gen_mla8_i32
,
10802 .fniv
= gen_mla_vec
,
10803 .opc
= INDEX_op_mul_vec
,
10806 { .fni4
= gen_mla16_i32
,
10807 .fniv
= gen_mla_vec
,
10808 .opc
= INDEX_op_mul_vec
,
10811 { .fni4
= gen_mla32_i32
,
10812 .fniv
= gen_mla_vec
,
10813 .opc
= INDEX_op_mul_vec
,
10816 { .fni8
= gen_mla64_i64
,
10817 .fniv
= gen_mla_vec
,
10818 .opc
= INDEX_op_mul_vec
,
10819 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10823 static const GVecGen3 mls_op
[4] = {
10824 { .fni4
= gen_mls8_i32
,
10825 .fniv
= gen_mls_vec
,
10826 .opc
= INDEX_op_mul_vec
,
10829 { .fni4
= gen_mls16_i32
,
10830 .fniv
= gen_mls_vec
,
10831 .opc
= INDEX_op_mul_vec
,
10834 { .fni4
= gen_mls32_i32
,
10835 .fniv
= gen_mls_vec
,
10836 .opc
= INDEX_op_mul_vec
,
10839 { .fni8
= gen_mls64_i64
,
10840 .fniv
= gen_mls_vec
,
10841 .opc
= INDEX_op_mul_vec
,
10842 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10847 int is_q
= extract32(insn
, 30, 1);
10848 int u
= extract32(insn
, 29, 1);
10849 int size
= extract32(insn
, 22, 2);
10850 int opcode
= extract32(insn
, 11, 5);
10851 int rm
= extract32(insn
, 16, 5);
10852 int rn
= extract32(insn
, 5, 5);
10853 int rd
= extract32(insn
, 0, 5);
10858 case 0x13: /* MUL, PMUL */
10859 if (u
&& size
!= 0) {
10860 unallocated_encoding(s
);
10864 case 0x0: /* SHADD, UHADD */
10865 case 0x2: /* SRHADD, URHADD */
10866 case 0x4: /* SHSUB, UHSUB */
10867 case 0xc: /* SMAX, UMAX */
10868 case 0xd: /* SMIN, UMIN */
10869 case 0xe: /* SABD, UABD */
10870 case 0xf: /* SABA, UABA */
10871 case 0x12: /* MLA, MLS */
10873 unallocated_encoding(s
);
10877 case 0x16: /* SQDMULH, SQRDMULH */
10878 if (size
== 0 || size
== 3) {
10879 unallocated_encoding(s
);
10884 if (size
== 3 && !is_q
) {
10885 unallocated_encoding(s
);
10891 if (!fp_access_check(s
)) {
10896 case 0x10: /* ADD, SUB */
10898 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
10900 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
10903 case 0x13: /* MUL, PMUL */
10904 if (!u
) { /* MUL */
10905 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
10909 case 0x12: /* MLA, MLS */
10911 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
10913 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
10917 if (!u
) { /* CMTST */
10918 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
10922 cond
= TCG_COND_EQ
;
10924 case 0x06: /* CMGT, CMHI */
10925 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
10927 case 0x07: /* CMGE, CMHS */
10928 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
10930 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
10931 vec_full_reg_offset(s
, rn
),
10932 vec_full_reg_offset(s
, rm
),
10933 is_q
? 16 : 8, vec_full_reg_size(s
));
10939 for (pass
= 0; pass
< 2; pass
++) {
10940 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10941 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10942 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10944 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10945 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10947 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
10949 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10951 tcg_temp_free_i64(tcg_res
);
10952 tcg_temp_free_i64(tcg_op1
);
10953 tcg_temp_free_i64(tcg_op2
);
10956 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10957 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10958 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10959 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10960 NeonGenTwoOpFn
*genfn
= NULL
;
10961 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
10963 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
10964 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
10967 case 0x0: /* SHADD, UHADD */
10969 static NeonGenTwoOpFn
* const fns
[3][2] = {
10970 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
10971 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
10972 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
10974 genfn
= fns
[size
][u
];
10977 case 0x1: /* SQADD, UQADD */
10979 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
10980 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
10981 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
10982 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
10984 genenvfn
= fns
[size
][u
];
10987 case 0x2: /* SRHADD, URHADD */
10989 static NeonGenTwoOpFn
* const fns
[3][2] = {
10990 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
10991 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
10992 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
10994 genfn
= fns
[size
][u
];
10997 case 0x4: /* SHSUB, UHSUB */
10999 static NeonGenTwoOpFn
* const fns
[3][2] = {
11000 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11001 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11002 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11004 genfn
= fns
[size
][u
];
11007 case 0x5: /* SQSUB, UQSUB */
11009 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11010 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
11011 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
11012 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
11014 genenvfn
= fns
[size
][u
];
11017 case 0x8: /* SSHL, USHL */
11019 static NeonGenTwoOpFn
* const fns
[3][2] = {
11020 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
11021 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
11022 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
11024 genfn
= fns
[size
][u
];
11027 case 0x9: /* SQSHL, UQSHL */
11029 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11030 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11031 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11032 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11034 genenvfn
= fns
[size
][u
];
11037 case 0xa: /* SRSHL, URSHL */
11039 static NeonGenTwoOpFn
* const fns
[3][2] = {
11040 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11041 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11042 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11044 genfn
= fns
[size
][u
];
11047 case 0xb: /* SQRSHL, UQRSHL */
11049 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11050 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11051 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11052 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11054 genenvfn
= fns
[size
][u
];
11057 case 0xc: /* SMAX, UMAX */
11059 static NeonGenTwoOpFn
* const fns
[3][2] = {
11060 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
11061 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
11062 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11064 genfn
= fns
[size
][u
];
11068 case 0xd: /* SMIN, UMIN */
11070 static NeonGenTwoOpFn
* const fns
[3][2] = {
11071 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
11072 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
11073 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11075 genfn
= fns
[size
][u
];
11078 case 0xe: /* SABD, UABD */
11079 case 0xf: /* SABA, UABA */
11081 static NeonGenTwoOpFn
* const fns
[3][2] = {
11082 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
11083 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
11084 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
11086 genfn
= fns
[size
][u
];
11089 case 0x13: /* MUL, PMUL */
11090 assert(u
); /* PMUL */
11092 genfn
= gen_helper_neon_mul_p8
;
11094 case 0x16: /* SQDMULH, SQRDMULH */
11096 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11097 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11098 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11100 assert(size
== 1 || size
== 2);
11101 genenvfn
= fns
[size
- 1][u
];
11105 g_assert_not_reached();
11109 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11111 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11114 if (opcode
== 0xf) {
11115 /* SABA, UABA: accumulating ops */
11116 static NeonGenTwoOpFn
* const fns
[3] = {
11117 gen_helper_neon_add_u8
,
11118 gen_helper_neon_add_u16
,
11122 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11123 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11126 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11128 tcg_temp_free_i32(tcg_res
);
11129 tcg_temp_free_i32(tcg_op1
);
11130 tcg_temp_free_i32(tcg_op2
);
11133 clear_vec_high(s
, is_q
, rd
);
11136 /* AdvSIMD three same
11137 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11138 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11139 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11140 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11142 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11144 int opcode
= extract32(insn
, 11, 5);
11147 case 0x3: /* logic ops */
11148 disas_simd_3same_logic(s
, insn
);
11150 case 0x17: /* ADDP */
11151 case 0x14: /* SMAXP, UMAXP */
11152 case 0x15: /* SMINP, UMINP */
11154 /* Pairwise operations */
11155 int is_q
= extract32(insn
, 30, 1);
11156 int u
= extract32(insn
, 29, 1);
11157 int size
= extract32(insn
, 22, 2);
11158 int rm
= extract32(insn
, 16, 5);
11159 int rn
= extract32(insn
, 5, 5);
11160 int rd
= extract32(insn
, 0, 5);
11161 if (opcode
== 0x17) {
11162 if (u
|| (size
== 3 && !is_q
)) {
11163 unallocated_encoding(s
);
11168 unallocated_encoding(s
);
11172 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11175 case 0x18 ... 0x31:
11176 /* floating point ops, sz[1] and U are part of opcode */
11177 disas_simd_3same_float(s
, insn
);
11180 disas_simd_3same_int(s
, insn
);
11186 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11188 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11189 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11190 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11191 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11193 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11194 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11197 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11199 int opcode
, fpopcode
;
11200 int is_q
, u
, a
, rm
, rn
, rd
;
11201 int datasize
, elements
;
11204 bool pairwise
= false;
11206 if (!dc_isar_feature(aa64_fp16
, s
)) {
11207 unallocated_encoding(s
);
11211 if (!fp_access_check(s
)) {
11215 /* For these floating point ops, the U, a and opcode bits
11216 * together indicate the operation.
11218 opcode
= extract32(insn
, 11, 3);
11219 u
= extract32(insn
, 29, 1);
11220 a
= extract32(insn
, 23, 1);
11221 is_q
= extract32(insn
, 30, 1);
11222 rm
= extract32(insn
, 16, 5);
11223 rn
= extract32(insn
, 5, 5);
11224 rd
= extract32(insn
, 0, 5);
11226 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11227 datasize
= is_q
? 128 : 64;
11228 elements
= datasize
/ 16;
11230 switch (fpopcode
) {
11231 case 0x10: /* FMAXNMP */
11232 case 0x12: /* FADDP */
11233 case 0x16: /* FMAXP */
11234 case 0x18: /* FMINNMP */
11235 case 0x1e: /* FMINP */
11240 fpst
= get_fpstatus_ptr(true);
11243 int maxpass
= is_q
? 8 : 4;
11244 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11245 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11246 TCGv_i32 tcg_res
[8];
11248 for (pass
= 0; pass
< maxpass
; pass
++) {
11249 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11250 int passelt
= (pass
<< 1) & (maxpass
- 1);
11252 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11253 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11254 tcg_res
[pass
] = tcg_temp_new_i32();
11256 switch (fpopcode
) {
11257 case 0x10: /* FMAXNMP */
11258 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11261 case 0x12: /* FADDP */
11262 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11264 case 0x16: /* FMAXP */
11265 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11267 case 0x18: /* FMINNMP */
11268 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11271 case 0x1e: /* FMINP */
11272 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11275 g_assert_not_reached();
11279 for (pass
= 0; pass
< maxpass
; pass
++) {
11280 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11281 tcg_temp_free_i32(tcg_res
[pass
]);
11284 tcg_temp_free_i32(tcg_op1
);
11285 tcg_temp_free_i32(tcg_op2
);
11288 for (pass
= 0; pass
< elements
; pass
++) {
11289 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11290 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11291 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11293 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11294 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11296 switch (fpopcode
) {
11297 case 0x0: /* FMAXNM */
11298 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11300 case 0x1: /* FMLA */
11301 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11302 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11305 case 0x2: /* FADD */
11306 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11308 case 0x3: /* FMULX */
11309 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11311 case 0x4: /* FCMEQ */
11312 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11314 case 0x6: /* FMAX */
11315 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11317 case 0x7: /* FRECPS */
11318 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11320 case 0x8: /* FMINNM */
11321 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11323 case 0x9: /* FMLS */
11324 /* As usual for ARM, separate negation for fused multiply-add */
11325 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11326 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11327 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11330 case 0xa: /* FSUB */
11331 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11333 case 0xe: /* FMIN */
11334 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11336 case 0xf: /* FRSQRTS */
11337 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11339 case 0x13: /* FMUL */
11340 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11342 case 0x14: /* FCMGE */
11343 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11345 case 0x15: /* FACGE */
11346 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11348 case 0x17: /* FDIV */
11349 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11351 case 0x1a: /* FABD */
11352 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11353 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11355 case 0x1c: /* FCMGT */
11356 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11358 case 0x1d: /* FACGT */
11359 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11362 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11363 __func__
, insn
, fpopcode
, s
->pc
);
11364 g_assert_not_reached();
11367 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11368 tcg_temp_free_i32(tcg_res
);
11369 tcg_temp_free_i32(tcg_op1
);
11370 tcg_temp_free_i32(tcg_op2
);
11374 tcg_temp_free_ptr(fpst
);
11376 clear_vec_high(s
, is_q
, rd
);
11379 /* AdvSIMD three same extra
11380 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11381 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11382 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11383 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11385 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11387 int rd
= extract32(insn
, 0, 5);
11388 int rn
= extract32(insn
, 5, 5);
11389 int opcode
= extract32(insn
, 11, 4);
11390 int rm
= extract32(insn
, 16, 5);
11391 int size
= extract32(insn
, 22, 2);
11392 bool u
= extract32(insn
, 29, 1);
11393 bool is_q
= extract32(insn
, 30, 1);
11397 switch (u
* 16 + opcode
) {
11398 case 0x10: /* SQRDMLAH (vector) */
11399 case 0x11: /* SQRDMLSH (vector) */
11400 if (size
!= 1 && size
!= 2) {
11401 unallocated_encoding(s
);
11404 feature
= dc_isar_feature(aa64_rdm
, s
);
11406 case 0x02: /* SDOT (vector) */
11407 case 0x12: /* UDOT (vector) */
11408 if (size
!= MO_32
) {
11409 unallocated_encoding(s
);
11412 feature
= dc_isar_feature(aa64_dp
, s
);
11414 case 0x18: /* FCMLA, #0 */
11415 case 0x19: /* FCMLA, #90 */
11416 case 0x1a: /* FCMLA, #180 */
11417 case 0x1b: /* FCMLA, #270 */
11418 case 0x1c: /* FCADD, #90 */
11419 case 0x1e: /* FCADD, #270 */
11421 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11422 || (size
== 3 && !is_q
)) {
11423 unallocated_encoding(s
);
11426 feature
= dc_isar_feature(aa64_fcma
, s
);
11429 unallocated_encoding(s
);
11433 unallocated_encoding(s
);
11436 if (!fp_access_check(s
)) {
11441 case 0x0: /* SQRDMLAH (vector) */
11444 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11447 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11450 g_assert_not_reached();
11454 case 0x1: /* SQRDMLSH (vector) */
11457 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11460 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11463 g_assert_not_reached();
11467 case 0x2: /* SDOT / UDOT */
11468 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11469 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11472 case 0x8: /* FCMLA, #0 */
11473 case 0x9: /* FCMLA, #90 */
11474 case 0xa: /* FCMLA, #180 */
11475 case 0xb: /* FCMLA, #270 */
11476 rot
= extract32(opcode
, 0, 2);
11479 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11480 gen_helper_gvec_fcmlah
);
11483 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11484 gen_helper_gvec_fcmlas
);
11487 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11488 gen_helper_gvec_fcmlad
);
11491 g_assert_not_reached();
11495 case 0xc: /* FCADD, #90 */
11496 case 0xe: /* FCADD, #270 */
11497 rot
= extract32(opcode
, 1, 1);
11500 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11501 gen_helper_gvec_fcaddh
);
11504 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11505 gen_helper_gvec_fcadds
);
11508 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11509 gen_helper_gvec_fcaddd
);
11512 g_assert_not_reached();
11517 g_assert_not_reached();
11521 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11522 int size
, int rn
, int rd
)
11524 /* Handle 2-reg-misc ops which are widening (so each size element
11525 * in the source becomes a 2*size element in the destination.
11526 * The only instruction like this is FCVTL.
11531 /* 32 -> 64 bit fp conversion */
11532 TCGv_i64 tcg_res
[2];
11533 int srcelt
= is_q
? 2 : 0;
11535 for (pass
= 0; pass
< 2; pass
++) {
11536 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11537 tcg_res
[pass
] = tcg_temp_new_i64();
11539 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11540 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11541 tcg_temp_free_i32(tcg_op
);
11543 for (pass
= 0; pass
< 2; pass
++) {
11544 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11545 tcg_temp_free_i64(tcg_res
[pass
]);
11548 /* 16 -> 32 bit fp conversion */
11549 int srcelt
= is_q
? 4 : 0;
11550 TCGv_i32 tcg_res
[4];
11551 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11552 TCGv_i32 ahp
= get_ahp_flag();
11554 for (pass
= 0; pass
< 4; pass
++) {
11555 tcg_res
[pass
] = tcg_temp_new_i32();
11557 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11558 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11561 for (pass
= 0; pass
< 4; pass
++) {
11562 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11563 tcg_temp_free_i32(tcg_res
[pass
]);
11566 tcg_temp_free_ptr(fpst
);
11567 tcg_temp_free_i32(ahp
);
11571 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11572 bool is_q
, int size
, int rn
, int rd
)
11574 int op
= (opcode
<< 1) | u
;
11575 int opsz
= op
+ size
;
11576 int grp_size
= 3 - opsz
;
11577 int dsize
= is_q
? 128 : 64;
11581 unallocated_encoding(s
);
11585 if (!fp_access_check(s
)) {
11590 /* Special case bytes, use bswap op on each group of elements */
11591 int groups
= dsize
/ (8 << grp_size
);
11593 for (i
= 0; i
< groups
; i
++) {
11594 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11596 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11597 switch (grp_size
) {
11599 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11602 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11605 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11608 g_assert_not_reached();
11610 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11611 tcg_temp_free_i64(tcg_tmp
);
11613 clear_vec_high(s
, is_q
, rd
);
11615 int revmask
= (1 << grp_size
) - 1;
11616 int esize
= 8 << size
;
11617 int elements
= dsize
/ esize
;
11618 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11619 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11620 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11622 for (i
= 0; i
< elements
; i
++) {
11623 int e_rev
= (i
& 0xf) ^ revmask
;
11624 int off
= e_rev
* esize
;
11625 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11627 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11628 tcg_rn
, off
- 64, esize
);
11630 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11633 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11634 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11636 tcg_temp_free_i64(tcg_rd_hi
);
11637 tcg_temp_free_i64(tcg_rd
);
11638 tcg_temp_free_i64(tcg_rn
);
11642 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11643 bool is_q
, int size
, int rn
, int rd
)
11645 /* Implement the pairwise operations from 2-misc:
11646 * SADDLP, UADDLP, SADALP, UADALP.
11647 * These all add pairs of elements in the input to produce a
11648 * double-width result element in the output (possibly accumulating).
11650 bool accum
= (opcode
== 0x6);
11651 int maxpass
= is_q
? 2 : 1;
11653 TCGv_i64 tcg_res
[2];
11656 /* 32 + 32 -> 64 op */
11657 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11659 for (pass
= 0; pass
< maxpass
; pass
++) {
11660 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11661 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11663 tcg_res
[pass
] = tcg_temp_new_i64();
11665 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11666 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11667 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11669 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11670 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11673 tcg_temp_free_i64(tcg_op1
);
11674 tcg_temp_free_i64(tcg_op2
);
11677 for (pass
= 0; pass
< maxpass
; pass
++) {
11678 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11679 NeonGenOneOpFn
*genfn
;
11680 static NeonGenOneOpFn
* const fns
[2][2] = {
11681 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11682 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11685 genfn
= fns
[size
][u
];
11687 tcg_res
[pass
] = tcg_temp_new_i64();
11689 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11690 genfn(tcg_res
[pass
], tcg_op
);
11693 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11695 gen_helper_neon_addl_u16(tcg_res
[pass
],
11696 tcg_res
[pass
], tcg_op
);
11698 gen_helper_neon_addl_u32(tcg_res
[pass
],
11699 tcg_res
[pass
], tcg_op
);
11702 tcg_temp_free_i64(tcg_op
);
11706 tcg_res
[1] = tcg_const_i64(0);
11708 for (pass
= 0; pass
< 2; pass
++) {
11709 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11710 tcg_temp_free_i64(tcg_res
[pass
]);
11714 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11716 /* Implement SHLL and SHLL2 */
11718 int part
= is_q
? 2 : 0;
11719 TCGv_i64 tcg_res
[2];
11721 for (pass
= 0; pass
< 2; pass
++) {
11722 static NeonGenWidenFn
* const widenfns
[3] = {
11723 gen_helper_neon_widen_u8
,
11724 gen_helper_neon_widen_u16
,
11725 tcg_gen_extu_i32_i64
,
11727 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11728 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11730 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11731 tcg_res
[pass
] = tcg_temp_new_i64();
11732 widenfn(tcg_res
[pass
], tcg_op
);
11733 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11735 tcg_temp_free_i32(tcg_op
);
11738 for (pass
= 0; pass
< 2; pass
++) {
11739 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11740 tcg_temp_free_i64(tcg_res
[pass
]);
11744 /* AdvSIMD two reg misc
11745 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11746 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11747 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11748 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11750 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
11752 int size
= extract32(insn
, 22, 2);
11753 int opcode
= extract32(insn
, 12, 5);
11754 bool u
= extract32(insn
, 29, 1);
11755 bool is_q
= extract32(insn
, 30, 1);
11756 int rn
= extract32(insn
, 5, 5);
11757 int rd
= extract32(insn
, 0, 5);
11758 bool need_fpstatus
= false;
11759 bool need_rmode
= false;
11761 TCGv_i32 tcg_rmode
;
11762 TCGv_ptr tcg_fpstatus
;
11765 case 0x0: /* REV64, REV32 */
11766 case 0x1: /* REV16 */
11767 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11769 case 0x5: /* CNT, NOT, RBIT */
11770 if (u
&& size
== 0) {
11773 } else if (u
&& size
== 1) {
11776 } else if (!u
&& size
== 0) {
11780 unallocated_encoding(s
);
11782 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
11783 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
11785 unallocated_encoding(s
);
11788 if (!fp_access_check(s
)) {
11792 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
11794 case 0x4: /* CLS, CLZ */
11796 unallocated_encoding(s
);
11800 case 0x2: /* SADDLP, UADDLP */
11801 case 0x6: /* SADALP, UADALP */
11803 unallocated_encoding(s
);
11806 if (!fp_access_check(s
)) {
11809 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11811 case 0x13: /* SHLL, SHLL2 */
11812 if (u
== 0 || size
== 3) {
11813 unallocated_encoding(s
);
11816 if (!fp_access_check(s
)) {
11819 handle_shll(s
, is_q
, size
, rn
, rd
);
11821 case 0xa: /* CMLT */
11823 unallocated_encoding(s
);
11827 case 0x8: /* CMGT, CMGE */
11828 case 0x9: /* CMEQ, CMLE */
11829 case 0xb: /* ABS, NEG */
11830 if (size
== 3 && !is_q
) {
11831 unallocated_encoding(s
);
11835 case 0x3: /* SUQADD, USQADD */
11836 if (size
== 3 && !is_q
) {
11837 unallocated_encoding(s
);
11840 if (!fp_access_check(s
)) {
11843 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
11845 case 0x7: /* SQABS, SQNEG */
11846 if (size
== 3 && !is_q
) {
11847 unallocated_encoding(s
);
11852 case 0x16 ... 0x1d:
11855 /* Floating point: U, size[1] and opcode indicate operation;
11856 * size[0] indicates single or double precision.
11858 int is_double
= extract32(size
, 0, 1);
11859 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
11860 size
= is_double
? 3 : 2;
11862 case 0x2f: /* FABS */
11863 case 0x6f: /* FNEG */
11864 if (size
== 3 && !is_q
) {
11865 unallocated_encoding(s
);
11869 case 0x1d: /* SCVTF */
11870 case 0x5d: /* UCVTF */
11872 bool is_signed
= (opcode
== 0x1d) ? true : false;
11873 int elements
= is_double
? 2 : is_q
? 4 : 2;
11874 if (is_double
&& !is_q
) {
11875 unallocated_encoding(s
);
11878 if (!fp_access_check(s
)) {
11881 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
11884 case 0x2c: /* FCMGT (zero) */
11885 case 0x2d: /* FCMEQ (zero) */
11886 case 0x2e: /* FCMLT (zero) */
11887 case 0x6c: /* FCMGE (zero) */
11888 case 0x6d: /* FCMLE (zero) */
11889 if (size
== 3 && !is_q
) {
11890 unallocated_encoding(s
);
11893 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11895 case 0x7f: /* FSQRT */
11896 if (size
== 3 && !is_q
) {
11897 unallocated_encoding(s
);
11901 case 0x1a: /* FCVTNS */
11902 case 0x1b: /* FCVTMS */
11903 case 0x3a: /* FCVTPS */
11904 case 0x3b: /* FCVTZS */
11905 case 0x5a: /* FCVTNU */
11906 case 0x5b: /* FCVTMU */
11907 case 0x7a: /* FCVTPU */
11908 case 0x7b: /* FCVTZU */
11909 need_fpstatus
= true;
11911 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
11912 if (size
== 3 && !is_q
) {
11913 unallocated_encoding(s
);
11917 case 0x5c: /* FCVTAU */
11918 case 0x1c: /* FCVTAS */
11919 need_fpstatus
= true;
11921 rmode
= FPROUNDING_TIEAWAY
;
11922 if (size
== 3 && !is_q
) {
11923 unallocated_encoding(s
);
11927 case 0x3c: /* URECPE */
11929 unallocated_encoding(s
);
11933 case 0x3d: /* FRECPE */
11934 case 0x7d: /* FRSQRTE */
11935 if (size
== 3 && !is_q
) {
11936 unallocated_encoding(s
);
11939 if (!fp_access_check(s
)) {
11942 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11944 case 0x56: /* FCVTXN, FCVTXN2 */
11946 unallocated_encoding(s
);
11950 case 0x16: /* FCVTN, FCVTN2 */
11951 /* handle_2misc_narrow does a 2*size -> size operation, but these
11952 * instructions encode the source size rather than dest size.
11954 if (!fp_access_check(s
)) {
11957 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
11959 case 0x17: /* FCVTL, FCVTL2 */
11960 if (!fp_access_check(s
)) {
11963 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
11965 case 0x18: /* FRINTN */
11966 case 0x19: /* FRINTM */
11967 case 0x38: /* FRINTP */
11968 case 0x39: /* FRINTZ */
11970 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
11972 case 0x59: /* FRINTX */
11973 case 0x79: /* FRINTI */
11974 need_fpstatus
= true;
11975 if (size
== 3 && !is_q
) {
11976 unallocated_encoding(s
);
11980 case 0x58: /* FRINTA */
11982 rmode
= FPROUNDING_TIEAWAY
;
11983 need_fpstatus
= true;
11984 if (size
== 3 && !is_q
) {
11985 unallocated_encoding(s
);
11989 case 0x7c: /* URSQRTE */
11991 unallocated_encoding(s
);
11994 need_fpstatus
= true;
11997 unallocated_encoding(s
);
12003 unallocated_encoding(s
);
12007 if (!fp_access_check(s
)) {
12011 if (need_fpstatus
|| need_rmode
) {
12012 tcg_fpstatus
= get_fpstatus_ptr(false);
12014 tcg_fpstatus
= NULL
;
12017 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12018 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12025 if (u
&& size
== 0) { /* NOT */
12026 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12032 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12039 /* All 64-bit element operations can be shared with scalar 2misc */
12042 /* Coverity claims (size == 3 && !is_q) has been eliminated
12043 * from all paths leading to here.
12045 tcg_debug_assert(is_q
);
12046 for (pass
= 0; pass
< 2; pass
++) {
12047 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12048 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12050 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12052 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12053 tcg_rmode
, tcg_fpstatus
);
12055 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12057 tcg_temp_free_i64(tcg_res
);
12058 tcg_temp_free_i64(tcg_op
);
12063 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12064 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12065 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12068 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12071 /* Special cases for 32 bit elements */
12073 case 0xa: /* CMLT */
12074 /* 32 bit integer comparison against zero, result is
12075 * test ? (2^32 - 1) : 0. We implement via setcond(test)
12078 cond
= TCG_COND_LT
;
12080 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
12081 tcg_gen_neg_i32(tcg_res
, tcg_res
);
12083 case 0x8: /* CMGT, CMGE */
12084 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
12086 case 0x9: /* CMEQ, CMLE */
12087 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
12089 case 0x4: /* CLS */
12091 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12093 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12096 case 0x7: /* SQABS, SQNEG */
12098 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12100 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12103 case 0xb: /* ABS, NEG */
12105 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12107 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12108 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12109 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
12110 tcg_zero
, tcg_op
, tcg_res
);
12111 tcg_temp_free_i32(tcg_zero
);
12114 case 0x2f: /* FABS */
12115 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12117 case 0x6f: /* FNEG */
12118 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12120 case 0x7f: /* FSQRT */
12121 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12123 case 0x1a: /* FCVTNS */
12124 case 0x1b: /* FCVTMS */
12125 case 0x1c: /* FCVTAS */
12126 case 0x3a: /* FCVTPS */
12127 case 0x3b: /* FCVTZS */
12129 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12130 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12131 tcg_shift
, tcg_fpstatus
);
12132 tcg_temp_free_i32(tcg_shift
);
12135 case 0x5a: /* FCVTNU */
12136 case 0x5b: /* FCVTMU */
12137 case 0x5c: /* FCVTAU */
12138 case 0x7a: /* FCVTPU */
12139 case 0x7b: /* FCVTZU */
12141 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12142 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12143 tcg_shift
, tcg_fpstatus
);
12144 tcg_temp_free_i32(tcg_shift
);
12147 case 0x18: /* FRINTN */
12148 case 0x19: /* FRINTM */
12149 case 0x38: /* FRINTP */
12150 case 0x39: /* FRINTZ */
12151 case 0x58: /* FRINTA */
12152 case 0x79: /* FRINTI */
12153 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12155 case 0x59: /* FRINTX */
12156 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12158 case 0x7c: /* URSQRTE */
12159 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
12162 g_assert_not_reached();
12165 /* Use helpers for 8 and 16 bit elements */
12167 case 0x5: /* CNT, RBIT */
12168 /* For these two insns size is part of the opcode specifier
12169 * (handled earlier); they always operate on byte elements.
12172 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12174 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12177 case 0x7: /* SQABS, SQNEG */
12179 NeonGenOneOpEnvFn
*genfn
;
12180 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12181 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12182 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12184 genfn
= fns
[size
][u
];
12185 genfn(tcg_res
, cpu_env
, tcg_op
);
12188 case 0x8: /* CMGT, CMGE */
12189 case 0x9: /* CMEQ, CMLE */
12190 case 0xa: /* CMLT */
12192 static NeonGenTwoOpFn
* const fns
[3][2] = {
12193 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
12194 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
12195 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
12197 NeonGenTwoOpFn
*genfn
;
12200 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12202 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
12203 comp
= (opcode
- 0x8) * 2 + u
;
12204 /* ...but LE, LT are implemented as reverse GE, GT */
12205 reverse
= (comp
> 2);
12209 genfn
= fns
[comp
][size
];
12211 genfn(tcg_res
, tcg_zero
, tcg_op
);
12213 genfn(tcg_res
, tcg_op
, tcg_zero
);
12215 tcg_temp_free_i32(tcg_zero
);
12218 case 0xb: /* ABS, NEG */
12220 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12222 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
12224 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
12226 tcg_temp_free_i32(tcg_zero
);
12229 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
12231 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
12235 case 0x4: /* CLS, CLZ */
12238 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12240 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12244 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12246 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12251 g_assert_not_reached();
12255 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12257 tcg_temp_free_i32(tcg_res
);
12258 tcg_temp_free_i32(tcg_op
);
12261 clear_vec_high(s
, is_q
, rd
);
12264 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12265 tcg_temp_free_i32(tcg_rmode
);
12267 if (need_fpstatus
) {
12268 tcg_temp_free_ptr(tcg_fpstatus
);
12272 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12274 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12275 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12276 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12277 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12278 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12279 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12281 * This actually covers two groups where scalar access is governed by
12282 * bit 28. A bunch of the instructions (float to integral) only exist
12283 * in the vector form and are un-allocated for the scalar decode. Also
12284 * in the scalar decode Q is always 1.
12286 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12288 int fpop
, opcode
, a
, u
;
12292 bool only_in_vector
= false;
12295 TCGv_i32 tcg_rmode
= NULL
;
12296 TCGv_ptr tcg_fpstatus
= NULL
;
12297 bool need_rmode
= false;
12298 bool need_fpst
= true;
12301 if (!dc_isar_feature(aa64_fp16
, s
)) {
12302 unallocated_encoding(s
);
12306 rd
= extract32(insn
, 0, 5);
12307 rn
= extract32(insn
, 5, 5);
12309 a
= extract32(insn
, 23, 1);
12310 u
= extract32(insn
, 29, 1);
12311 is_scalar
= extract32(insn
, 28, 1);
12312 is_q
= extract32(insn
, 30, 1);
12314 opcode
= extract32(insn
, 12, 5);
12315 fpop
= deposit32(opcode
, 5, 1, a
);
12316 fpop
= deposit32(fpop
, 6, 1, u
);
12318 rd
= extract32(insn
, 0, 5);
12319 rn
= extract32(insn
, 5, 5);
12322 case 0x1d: /* SCVTF */
12323 case 0x5d: /* UCVTF */
12330 elements
= (is_q
? 8 : 4);
12333 if (!fp_access_check(s
)) {
12336 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12340 case 0x2c: /* FCMGT (zero) */
12341 case 0x2d: /* FCMEQ (zero) */
12342 case 0x2e: /* FCMLT (zero) */
12343 case 0x6c: /* FCMGE (zero) */
12344 case 0x6d: /* FCMLE (zero) */
12345 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12347 case 0x3d: /* FRECPE */
12348 case 0x3f: /* FRECPX */
12350 case 0x18: /* FRINTN */
12352 only_in_vector
= true;
12353 rmode
= FPROUNDING_TIEEVEN
;
12355 case 0x19: /* FRINTM */
12357 only_in_vector
= true;
12358 rmode
= FPROUNDING_NEGINF
;
12360 case 0x38: /* FRINTP */
12362 only_in_vector
= true;
12363 rmode
= FPROUNDING_POSINF
;
12365 case 0x39: /* FRINTZ */
12367 only_in_vector
= true;
12368 rmode
= FPROUNDING_ZERO
;
12370 case 0x58: /* FRINTA */
12372 only_in_vector
= true;
12373 rmode
= FPROUNDING_TIEAWAY
;
12375 case 0x59: /* FRINTX */
12376 case 0x79: /* FRINTI */
12377 only_in_vector
= true;
12378 /* current rounding mode */
12380 case 0x1a: /* FCVTNS */
12382 rmode
= FPROUNDING_TIEEVEN
;
12384 case 0x1b: /* FCVTMS */
12386 rmode
= FPROUNDING_NEGINF
;
12388 case 0x1c: /* FCVTAS */
12390 rmode
= FPROUNDING_TIEAWAY
;
12392 case 0x3a: /* FCVTPS */
12394 rmode
= FPROUNDING_POSINF
;
12396 case 0x3b: /* FCVTZS */
12398 rmode
= FPROUNDING_ZERO
;
12400 case 0x5a: /* FCVTNU */
12402 rmode
= FPROUNDING_TIEEVEN
;
12404 case 0x5b: /* FCVTMU */
12406 rmode
= FPROUNDING_NEGINF
;
12408 case 0x5c: /* FCVTAU */
12410 rmode
= FPROUNDING_TIEAWAY
;
12412 case 0x7a: /* FCVTPU */
12414 rmode
= FPROUNDING_POSINF
;
12416 case 0x7b: /* FCVTZU */
12418 rmode
= FPROUNDING_ZERO
;
12420 case 0x2f: /* FABS */
12421 case 0x6f: /* FNEG */
12424 case 0x7d: /* FRSQRTE */
12425 case 0x7f: /* FSQRT (vector) */
12428 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12429 g_assert_not_reached();
12433 /* Check additional constraints for the scalar encoding */
12436 unallocated_encoding(s
);
12439 /* FRINTxx is only in the vector form */
12440 if (only_in_vector
) {
12441 unallocated_encoding(s
);
12446 if (!fp_access_check(s
)) {
12450 if (need_rmode
|| need_fpst
) {
12451 tcg_fpstatus
= get_fpstatus_ptr(true);
12455 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12456 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12460 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12461 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12464 case 0x1a: /* FCVTNS */
12465 case 0x1b: /* FCVTMS */
12466 case 0x1c: /* FCVTAS */
12467 case 0x3a: /* FCVTPS */
12468 case 0x3b: /* FCVTZS */
12469 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12471 case 0x3d: /* FRECPE */
12472 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12474 case 0x3f: /* FRECPX */
12475 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12477 case 0x5a: /* FCVTNU */
12478 case 0x5b: /* FCVTMU */
12479 case 0x5c: /* FCVTAU */
12480 case 0x7a: /* FCVTPU */
12481 case 0x7b: /* FCVTZU */
12482 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12484 case 0x6f: /* FNEG */
12485 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12487 case 0x7d: /* FRSQRTE */
12488 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12491 g_assert_not_reached();
12494 /* limit any sign extension going on */
12495 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12496 write_fp_sreg(s
, rd
, tcg_res
);
12498 tcg_temp_free_i32(tcg_res
);
12499 tcg_temp_free_i32(tcg_op
);
12501 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12502 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12503 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12505 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12508 case 0x1a: /* FCVTNS */
12509 case 0x1b: /* FCVTMS */
12510 case 0x1c: /* FCVTAS */
12511 case 0x3a: /* FCVTPS */
12512 case 0x3b: /* FCVTZS */
12513 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12515 case 0x3d: /* FRECPE */
12516 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12518 case 0x5a: /* FCVTNU */
12519 case 0x5b: /* FCVTMU */
12520 case 0x5c: /* FCVTAU */
12521 case 0x7a: /* FCVTPU */
12522 case 0x7b: /* FCVTZU */
12523 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12525 case 0x18: /* FRINTN */
12526 case 0x19: /* FRINTM */
12527 case 0x38: /* FRINTP */
12528 case 0x39: /* FRINTZ */
12529 case 0x58: /* FRINTA */
12530 case 0x79: /* FRINTI */
12531 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12533 case 0x59: /* FRINTX */
12534 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12536 case 0x2f: /* FABS */
12537 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12539 case 0x6f: /* FNEG */
12540 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12542 case 0x7d: /* FRSQRTE */
12543 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12545 case 0x7f: /* FSQRT */
12546 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12549 g_assert_not_reached();
12552 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12554 tcg_temp_free_i32(tcg_res
);
12555 tcg_temp_free_i32(tcg_op
);
12558 clear_vec_high(s
, is_q
, rd
);
12562 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12563 tcg_temp_free_i32(tcg_rmode
);
12566 if (tcg_fpstatus
) {
12567 tcg_temp_free_ptr(tcg_fpstatus
);
12571 /* AdvSIMD scalar x indexed element
12572 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12573 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12574 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12575 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12576 * AdvSIMD vector x indexed element
12577 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12578 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12579 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12580 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12582 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12584 /* This encoding has two kinds of instruction:
12585 * normal, where we perform elt x idxelt => elt for each
12586 * element in the vector
12587 * long, where we perform elt x idxelt and generate a result of
12588 * double the width of the input element
12589 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12591 bool is_scalar
= extract32(insn
, 28, 1);
12592 bool is_q
= extract32(insn
, 30, 1);
12593 bool u
= extract32(insn
, 29, 1);
12594 int size
= extract32(insn
, 22, 2);
12595 int l
= extract32(insn
, 21, 1);
12596 int m
= extract32(insn
, 20, 1);
12597 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12598 int rm
= extract32(insn
, 16, 4);
12599 int opcode
= extract32(insn
, 12, 4);
12600 int h
= extract32(insn
, 11, 1);
12601 int rn
= extract32(insn
, 5, 5);
12602 int rd
= extract32(insn
, 0, 5);
12603 bool is_long
= false;
12605 bool is_fp16
= false;
12609 switch (16 * u
+ opcode
) {
12610 case 0x08: /* MUL */
12611 case 0x10: /* MLA */
12612 case 0x14: /* MLS */
12614 unallocated_encoding(s
);
12618 case 0x02: /* SMLAL, SMLAL2 */
12619 case 0x12: /* UMLAL, UMLAL2 */
12620 case 0x06: /* SMLSL, SMLSL2 */
12621 case 0x16: /* UMLSL, UMLSL2 */
12622 case 0x0a: /* SMULL, SMULL2 */
12623 case 0x1a: /* UMULL, UMULL2 */
12625 unallocated_encoding(s
);
12630 case 0x03: /* SQDMLAL, SQDMLAL2 */
12631 case 0x07: /* SQDMLSL, SQDMLSL2 */
12632 case 0x0b: /* SQDMULL, SQDMULL2 */
12635 case 0x0c: /* SQDMULH */
12636 case 0x0d: /* SQRDMULH */
12638 case 0x01: /* FMLA */
12639 case 0x05: /* FMLS */
12640 case 0x09: /* FMUL */
12641 case 0x19: /* FMULX */
12644 case 0x1d: /* SQRDMLAH */
12645 case 0x1f: /* SQRDMLSH */
12646 if (!dc_isar_feature(aa64_rdm
, s
)) {
12647 unallocated_encoding(s
);
12651 case 0x0e: /* SDOT */
12652 case 0x1e: /* UDOT */
12653 if (size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12654 unallocated_encoding(s
);
12658 case 0x11: /* FCMLA #0 */
12659 case 0x13: /* FCMLA #90 */
12660 case 0x15: /* FCMLA #180 */
12661 case 0x17: /* FCMLA #270 */
12662 if (!dc_isar_feature(aa64_fcma
, s
)) {
12663 unallocated_encoding(s
);
12669 unallocated_encoding(s
);
12674 case 1: /* normal fp */
12675 /* convert insn encoded size to TCGMemOp size */
12677 case 0: /* half-precision */
12681 case MO_32
: /* single precision */
12682 case MO_64
: /* double precision */
12685 unallocated_encoding(s
);
12690 case 2: /* complex fp */
12691 /* Each indexable element is a complex pair. */
12696 unallocated_encoding(s
);
12704 unallocated_encoding(s
);
12709 default: /* integer */
12713 unallocated_encoding(s
);
12718 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12719 unallocated_encoding(s
);
12723 /* Given TCGMemOp size, adjust register and indexing. */
12726 index
= h
<< 2 | l
<< 1 | m
;
12729 index
= h
<< 1 | l
;
12734 unallocated_encoding(s
);
12741 g_assert_not_reached();
12744 if (!fp_access_check(s
)) {
12749 fpst
= get_fpstatus_ptr(is_fp16
);
12754 switch (16 * u
+ opcode
) {
12755 case 0x0e: /* SDOT */
12756 case 0x1e: /* UDOT */
12757 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
12758 u
? gen_helper_gvec_udot_idx_b
12759 : gen_helper_gvec_sdot_idx_b
);
12761 case 0x11: /* FCMLA #0 */
12762 case 0x13: /* FCMLA #90 */
12763 case 0x15: /* FCMLA #180 */
12764 case 0x17: /* FCMLA #270 */
12766 int rot
= extract32(insn
, 13, 2);
12767 int data
= (index
<< 2) | rot
;
12768 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12769 vec_full_reg_offset(s
, rn
),
12770 vec_full_reg_offset(s
, rm
), fpst
,
12771 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
12773 ? gen_helper_gvec_fcmlas_idx
12774 : gen_helper_gvec_fcmlah_idx
);
12775 tcg_temp_free_ptr(fpst
);
12781 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12784 assert(is_fp
&& is_q
&& !is_long
);
12786 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
12788 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12789 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12790 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12792 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12794 switch (16 * u
+ opcode
) {
12795 case 0x05: /* FMLS */
12796 /* As usual for ARM, separate negation for fused multiply-add */
12797 gen_helper_vfp_negd(tcg_op
, tcg_op
);
12799 case 0x01: /* FMLA */
12800 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12801 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
12803 case 0x09: /* FMUL */
12804 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12806 case 0x19: /* FMULX */
12807 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12810 g_assert_not_reached();
12813 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12814 tcg_temp_free_i64(tcg_op
);
12815 tcg_temp_free_i64(tcg_res
);
12818 tcg_temp_free_i64(tcg_idx
);
12819 clear_vec_high(s
, !is_scalar
, rd
);
12820 } else if (!is_long
) {
12821 /* 32 bit floating point, or 16 or 32 bit integer.
12822 * For the 16 bit scalar case we use the usual Neon helpers and
12823 * rely on the fact that 0 op 0 == 0 with no side effects.
12825 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
12826 int pass
, maxpasses
;
12831 maxpasses
= is_q
? 4 : 2;
12834 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
12836 if (size
== 1 && !is_scalar
) {
12837 /* The simplest way to handle the 16x16 indexed ops is to duplicate
12838 * the index into both halves of the 32 bit tcg_idx and then use
12839 * the usual Neon helpers.
12841 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
12844 for (pass
= 0; pass
< maxpasses
; pass
++) {
12845 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12846 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12848 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
12850 switch (16 * u
+ opcode
) {
12851 case 0x08: /* MUL */
12852 case 0x10: /* MLA */
12853 case 0x14: /* MLS */
12855 static NeonGenTwoOpFn
* const fns
[2][2] = {
12856 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
12857 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
12859 NeonGenTwoOpFn
*genfn
;
12860 bool is_sub
= opcode
== 0x4;
12863 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
12865 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
12867 if (opcode
== 0x8) {
12870 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
12871 genfn
= fns
[size
- 1][is_sub
];
12872 genfn(tcg_res
, tcg_op
, tcg_res
);
12875 case 0x05: /* FMLS */
12876 case 0x01: /* FMLA */
12877 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12878 is_scalar
? size
: MO_32
);
12881 if (opcode
== 0x5) {
12882 /* As usual for ARM, separate negation for fused
12884 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
12887 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
12890 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
12895 if (opcode
== 0x5) {
12896 /* As usual for ARM, separate negation for
12897 * fused multiply-add */
12898 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
12900 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
12904 g_assert_not_reached();
12907 case 0x09: /* FMUL */
12911 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
12914 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
12919 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12922 g_assert_not_reached();
12925 case 0x19: /* FMULX */
12929 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
12932 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
12937 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12940 g_assert_not_reached();
12943 case 0x0c: /* SQDMULH */
12945 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
12948 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
12952 case 0x0d: /* SQRDMULH */
12954 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
12957 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
12961 case 0x1d: /* SQRDMLAH */
12962 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12963 is_scalar
? size
: MO_32
);
12965 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
12966 tcg_op
, tcg_idx
, tcg_res
);
12968 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
12969 tcg_op
, tcg_idx
, tcg_res
);
12972 case 0x1f: /* SQRDMLSH */
12973 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12974 is_scalar
? size
: MO_32
);
12976 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
12977 tcg_op
, tcg_idx
, tcg_res
);
12979 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
12980 tcg_op
, tcg_idx
, tcg_res
);
12984 g_assert_not_reached();
12988 write_fp_sreg(s
, rd
, tcg_res
);
12990 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12993 tcg_temp_free_i32(tcg_op
);
12994 tcg_temp_free_i32(tcg_res
);
12997 tcg_temp_free_i32(tcg_idx
);
12998 clear_vec_high(s
, is_q
, rd
);
13000 /* long ops: 16x16->32 or 32x32->64 */
13001 TCGv_i64 tcg_res
[2];
13003 bool satop
= extract32(opcode
, 0, 1);
13004 TCGMemOp memop
= MO_32
;
13011 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13013 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13015 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13016 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13017 TCGv_i64 tcg_passres
;
13023 passelt
= pass
+ (is_q
* 2);
13026 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13028 tcg_res
[pass
] = tcg_temp_new_i64();
13030 if (opcode
== 0xa || opcode
== 0xb) {
13031 /* Non-accumulating ops */
13032 tcg_passres
= tcg_res
[pass
];
13034 tcg_passres
= tcg_temp_new_i64();
13037 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13038 tcg_temp_free_i64(tcg_op
);
13041 /* saturating, doubling */
13042 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13043 tcg_passres
, tcg_passres
);
13046 if (opcode
== 0xa || opcode
== 0xb) {
13050 /* Accumulating op: handle accumulate step */
13051 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13054 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13055 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13057 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13058 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13060 case 0x7: /* SQDMLSL, SQDMLSL2 */
13061 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13063 case 0x3: /* SQDMLAL, SQDMLAL2 */
13064 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13069 g_assert_not_reached();
13071 tcg_temp_free_i64(tcg_passres
);
13073 tcg_temp_free_i64(tcg_idx
);
13075 clear_vec_high(s
, !is_scalar
, rd
);
13077 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13080 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13083 /* The simplest way to handle the 16x16 indexed ops is to
13084 * duplicate the index into both halves of the 32 bit tcg_idx
13085 * and then use the usual Neon helpers.
13087 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13090 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13091 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13092 TCGv_i64 tcg_passres
;
13095 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13097 read_vec_element_i32(s
, tcg_op
, rn
,
13098 pass
+ (is_q
* 2), MO_32
);
13101 tcg_res
[pass
] = tcg_temp_new_i64();
13103 if (opcode
== 0xa || opcode
== 0xb) {
13104 /* Non-accumulating ops */
13105 tcg_passres
= tcg_res
[pass
];
13107 tcg_passres
= tcg_temp_new_i64();
13110 if (memop
& MO_SIGN
) {
13111 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13113 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13116 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13117 tcg_passres
, tcg_passres
);
13119 tcg_temp_free_i32(tcg_op
);
13121 if (opcode
== 0xa || opcode
== 0xb) {
13125 /* Accumulating op: handle accumulate step */
13126 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13129 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13130 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13133 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13134 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13137 case 0x7: /* SQDMLSL, SQDMLSL2 */
13138 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13140 case 0x3: /* SQDMLAL, SQDMLAL2 */
13141 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13146 g_assert_not_reached();
13148 tcg_temp_free_i64(tcg_passres
);
13150 tcg_temp_free_i32(tcg_idx
);
13153 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13158 tcg_res
[1] = tcg_const_i64(0);
13161 for (pass
= 0; pass
< 2; pass
++) {
13162 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13163 tcg_temp_free_i64(tcg_res
[pass
]);
13168 tcg_temp_free_ptr(fpst
);
13173 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13174 * +-----------------+------+-----------+--------+-----+------+------+
13175 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13176 * +-----------------+------+-----------+--------+-----+------+------+
13178 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13180 int size
= extract32(insn
, 22, 2);
13181 int opcode
= extract32(insn
, 12, 5);
13182 int rn
= extract32(insn
, 5, 5);
13183 int rd
= extract32(insn
, 0, 5);
13185 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13186 TCGv_i32 tcg_decrypt
;
13187 CryptoThreeOpIntFn
*genfn
;
13189 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13190 unallocated_encoding(s
);
13195 case 0x4: /* AESE */
13197 genfn
= gen_helper_crypto_aese
;
13199 case 0x6: /* AESMC */
13201 genfn
= gen_helper_crypto_aesmc
;
13203 case 0x5: /* AESD */
13205 genfn
= gen_helper_crypto_aese
;
13207 case 0x7: /* AESIMC */
13209 genfn
= gen_helper_crypto_aesmc
;
13212 unallocated_encoding(s
);
13216 if (!fp_access_check(s
)) {
13220 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13221 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13222 tcg_decrypt
= tcg_const_i32(decrypt
);
13224 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
13226 tcg_temp_free_ptr(tcg_rd_ptr
);
13227 tcg_temp_free_ptr(tcg_rn_ptr
);
13228 tcg_temp_free_i32(tcg_decrypt
);
13231 /* Crypto three-reg SHA
13232 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13233 * +-----------------+------+---+------+---+--------+-----+------+------+
13234 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13235 * +-----------------+------+---+------+---+--------+-----+------+------+
13237 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13239 int size
= extract32(insn
, 22, 2);
13240 int opcode
= extract32(insn
, 12, 3);
13241 int rm
= extract32(insn
, 16, 5);
13242 int rn
= extract32(insn
, 5, 5);
13243 int rd
= extract32(insn
, 0, 5);
13244 CryptoThreeOpFn
*genfn
;
13245 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13249 unallocated_encoding(s
);
13254 case 0: /* SHA1C */
13255 case 1: /* SHA1P */
13256 case 2: /* SHA1M */
13257 case 3: /* SHA1SU0 */
13259 feature
= dc_isar_feature(aa64_sha1
, s
);
13261 case 4: /* SHA256H */
13262 genfn
= gen_helper_crypto_sha256h
;
13263 feature
= dc_isar_feature(aa64_sha256
, s
);
13265 case 5: /* SHA256H2 */
13266 genfn
= gen_helper_crypto_sha256h2
;
13267 feature
= dc_isar_feature(aa64_sha256
, s
);
13269 case 6: /* SHA256SU1 */
13270 genfn
= gen_helper_crypto_sha256su1
;
13271 feature
= dc_isar_feature(aa64_sha256
, s
);
13274 unallocated_encoding(s
);
13279 unallocated_encoding(s
);
13283 if (!fp_access_check(s
)) {
13287 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13288 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13289 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13292 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13294 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13296 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13297 tcg_rm_ptr
, tcg_opcode
);
13298 tcg_temp_free_i32(tcg_opcode
);
13301 tcg_temp_free_ptr(tcg_rd_ptr
);
13302 tcg_temp_free_ptr(tcg_rn_ptr
);
13303 tcg_temp_free_ptr(tcg_rm_ptr
);
13306 /* Crypto two-reg SHA
13307 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13308 * +-----------------+------+-----------+--------+-----+------+------+
13309 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13310 * +-----------------+------+-----------+--------+-----+------+------+
13312 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13314 int size
= extract32(insn
, 22, 2);
13315 int opcode
= extract32(insn
, 12, 5);
13316 int rn
= extract32(insn
, 5, 5);
13317 int rd
= extract32(insn
, 0, 5);
13318 CryptoTwoOpFn
*genfn
;
13320 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13323 unallocated_encoding(s
);
13328 case 0: /* SHA1H */
13329 feature
= dc_isar_feature(aa64_sha1
, s
);
13330 genfn
= gen_helper_crypto_sha1h
;
13332 case 1: /* SHA1SU1 */
13333 feature
= dc_isar_feature(aa64_sha1
, s
);
13334 genfn
= gen_helper_crypto_sha1su1
;
13336 case 2: /* SHA256SU0 */
13337 feature
= dc_isar_feature(aa64_sha256
, s
);
13338 genfn
= gen_helper_crypto_sha256su0
;
13341 unallocated_encoding(s
);
13346 unallocated_encoding(s
);
13350 if (!fp_access_check(s
)) {
13354 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13355 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13357 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13359 tcg_temp_free_ptr(tcg_rd_ptr
);
13360 tcg_temp_free_ptr(tcg_rn_ptr
);
13363 /* Crypto three-reg SHA512
13364 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13365 * +-----------------------+------+---+---+-----+--------+------+------+
13366 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13367 * +-----------------------+------+---+---+-----+--------+------+------+
13369 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13371 int opcode
= extract32(insn
, 10, 2);
13372 int o
= extract32(insn
, 14, 1);
13373 int rm
= extract32(insn
, 16, 5);
13374 int rn
= extract32(insn
, 5, 5);
13375 int rd
= extract32(insn
, 0, 5);
13377 CryptoThreeOpFn
*genfn
;
13381 case 0: /* SHA512H */
13382 feature
= dc_isar_feature(aa64_sha512
, s
);
13383 genfn
= gen_helper_crypto_sha512h
;
13385 case 1: /* SHA512H2 */
13386 feature
= dc_isar_feature(aa64_sha512
, s
);
13387 genfn
= gen_helper_crypto_sha512h2
;
13389 case 2: /* SHA512SU1 */
13390 feature
= dc_isar_feature(aa64_sha512
, s
);
13391 genfn
= gen_helper_crypto_sha512su1
;
13394 feature
= dc_isar_feature(aa64_sha3
, s
);
13400 case 0: /* SM3PARTW1 */
13401 feature
= dc_isar_feature(aa64_sm3
, s
);
13402 genfn
= gen_helper_crypto_sm3partw1
;
13404 case 1: /* SM3PARTW2 */
13405 feature
= dc_isar_feature(aa64_sm3
, s
);
13406 genfn
= gen_helper_crypto_sm3partw2
;
13408 case 2: /* SM4EKEY */
13409 feature
= dc_isar_feature(aa64_sm4
, s
);
13410 genfn
= gen_helper_crypto_sm4ekey
;
13413 unallocated_encoding(s
);
13419 unallocated_encoding(s
);
13423 if (!fp_access_check(s
)) {
13428 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13430 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13431 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13432 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13434 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13436 tcg_temp_free_ptr(tcg_rd_ptr
);
13437 tcg_temp_free_ptr(tcg_rn_ptr
);
13438 tcg_temp_free_ptr(tcg_rm_ptr
);
13440 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13443 tcg_op1
= tcg_temp_new_i64();
13444 tcg_op2
= tcg_temp_new_i64();
13445 tcg_res
[0] = tcg_temp_new_i64();
13446 tcg_res
[1] = tcg_temp_new_i64();
13448 for (pass
= 0; pass
< 2; pass
++) {
13449 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13450 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13452 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13453 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13455 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13456 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13458 tcg_temp_free_i64(tcg_op1
);
13459 tcg_temp_free_i64(tcg_op2
);
13460 tcg_temp_free_i64(tcg_res
[0]);
13461 tcg_temp_free_i64(tcg_res
[1]);
13465 /* Crypto two-reg SHA512
13466 * 31 12 11 10 9 5 4 0
13467 * +-----------------------------------------+--------+------+------+
13468 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13469 * +-----------------------------------------+--------+------+------+
13471 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13473 int opcode
= extract32(insn
, 10, 2);
13474 int rn
= extract32(insn
, 5, 5);
13475 int rd
= extract32(insn
, 0, 5);
13476 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13478 CryptoTwoOpFn
*genfn
;
13481 case 0: /* SHA512SU0 */
13482 feature
= dc_isar_feature(aa64_sha512
, s
);
13483 genfn
= gen_helper_crypto_sha512su0
;
13486 feature
= dc_isar_feature(aa64_sm4
, s
);
13487 genfn
= gen_helper_crypto_sm4e
;
13490 unallocated_encoding(s
);
13495 unallocated_encoding(s
);
13499 if (!fp_access_check(s
)) {
13503 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13504 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13506 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13508 tcg_temp_free_ptr(tcg_rd_ptr
);
13509 tcg_temp_free_ptr(tcg_rn_ptr
);
13512 /* Crypto four-register
13513 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13514 * +-------------------+-----+------+---+------+------+------+
13515 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13516 * +-------------------+-----+------+---+------+------+------+
13518 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13520 int op0
= extract32(insn
, 21, 2);
13521 int rm
= extract32(insn
, 16, 5);
13522 int ra
= extract32(insn
, 10, 5);
13523 int rn
= extract32(insn
, 5, 5);
13524 int rd
= extract32(insn
, 0, 5);
13530 feature
= dc_isar_feature(aa64_sha3
, s
);
13532 case 2: /* SM3SS1 */
13533 feature
= dc_isar_feature(aa64_sm3
, s
);
13536 unallocated_encoding(s
);
13541 unallocated_encoding(s
);
13545 if (!fp_access_check(s
)) {
13550 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13553 tcg_op1
= tcg_temp_new_i64();
13554 tcg_op2
= tcg_temp_new_i64();
13555 tcg_op3
= tcg_temp_new_i64();
13556 tcg_res
[0] = tcg_temp_new_i64();
13557 tcg_res
[1] = tcg_temp_new_i64();
13559 for (pass
= 0; pass
< 2; pass
++) {
13560 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13561 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13562 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13566 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13569 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13571 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13573 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13574 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13576 tcg_temp_free_i64(tcg_op1
);
13577 tcg_temp_free_i64(tcg_op2
);
13578 tcg_temp_free_i64(tcg_op3
);
13579 tcg_temp_free_i64(tcg_res
[0]);
13580 tcg_temp_free_i64(tcg_res
[1]);
13582 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13584 tcg_op1
= tcg_temp_new_i32();
13585 tcg_op2
= tcg_temp_new_i32();
13586 tcg_op3
= tcg_temp_new_i32();
13587 tcg_res
= tcg_temp_new_i32();
13588 tcg_zero
= tcg_const_i32(0);
13590 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13591 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13592 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13594 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13595 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13596 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13597 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13599 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13600 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13601 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13602 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13604 tcg_temp_free_i32(tcg_op1
);
13605 tcg_temp_free_i32(tcg_op2
);
13606 tcg_temp_free_i32(tcg_op3
);
13607 tcg_temp_free_i32(tcg_res
);
13608 tcg_temp_free_i32(tcg_zero
);
13613 * 31 21 20 16 15 10 9 5 4 0
13614 * +-----------------------+------+--------+------+------+
13615 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13616 * +-----------------------+------+--------+------+------+
13618 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13620 int rm
= extract32(insn
, 16, 5);
13621 int imm6
= extract32(insn
, 10, 6);
13622 int rn
= extract32(insn
, 5, 5);
13623 int rd
= extract32(insn
, 0, 5);
13624 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13627 if (!dc_isar_feature(aa64_sha3
, s
)) {
13628 unallocated_encoding(s
);
13632 if (!fp_access_check(s
)) {
13636 tcg_op1
= tcg_temp_new_i64();
13637 tcg_op2
= tcg_temp_new_i64();
13638 tcg_res
[0] = tcg_temp_new_i64();
13639 tcg_res
[1] = tcg_temp_new_i64();
13641 for (pass
= 0; pass
< 2; pass
++) {
13642 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13643 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13645 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13646 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13648 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13649 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13651 tcg_temp_free_i64(tcg_op1
);
13652 tcg_temp_free_i64(tcg_op2
);
13653 tcg_temp_free_i64(tcg_res
[0]);
13654 tcg_temp_free_i64(tcg_res
[1]);
13657 /* Crypto three-reg imm2
13658 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13659 * +-----------------------+------+-----+------+--------+------+------+
13660 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13661 * +-----------------------+------+-----+------+--------+------+------+
13663 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13665 int opcode
= extract32(insn
, 10, 2);
13666 int imm2
= extract32(insn
, 12, 2);
13667 int rm
= extract32(insn
, 16, 5);
13668 int rn
= extract32(insn
, 5, 5);
13669 int rd
= extract32(insn
, 0, 5);
13670 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13671 TCGv_i32 tcg_imm2
, tcg_opcode
;
13673 if (!dc_isar_feature(aa64_sm3
, s
)) {
13674 unallocated_encoding(s
);
13678 if (!fp_access_check(s
)) {
13682 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13683 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13684 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13685 tcg_imm2
= tcg_const_i32(imm2
);
13686 tcg_opcode
= tcg_const_i32(opcode
);
13688 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
13691 tcg_temp_free_ptr(tcg_rd_ptr
);
13692 tcg_temp_free_ptr(tcg_rn_ptr
);
13693 tcg_temp_free_ptr(tcg_rm_ptr
);
13694 tcg_temp_free_i32(tcg_imm2
);
13695 tcg_temp_free_i32(tcg_opcode
);
13698 /* C3.6 Data processing - SIMD, inc Crypto
13700 * As the decode gets a little complex we are using a table based
13701 * approach for this part of the decode.
13703 static const AArch64DecodeTable data_proc_simd
[] = {
13704 /* pattern , mask , fn */
13705 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13706 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13707 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13708 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13709 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13710 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13711 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13712 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13713 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13714 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13715 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13716 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13717 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13718 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13719 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13720 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13721 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13722 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13723 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13724 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13725 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13726 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13727 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13728 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13729 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13730 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13731 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13732 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13733 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13734 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13735 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13736 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13737 { 0x00000000, 0x00000000, NULL
}
13740 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13742 /* Note that this is called with all non-FP cases from
13743 * table C3-6 so it must UNDEF for entries not specifically
13744 * allocated to instructions in that table.
13746 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13750 unallocated_encoding(s
);
13754 /* C3.6 Data processing - SIMD and floating point */
13755 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13757 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13758 disas_data_proc_fp(s
, insn
);
13760 /* SIMD, including crypto */
13761 disas_data_proc_simd(s
, insn
);
13765 /* C3.1 A64 instruction index by encoding */
13766 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
13770 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
13774 s
->fp_access_checked
= false;
13776 switch (extract32(insn
, 25, 4)) {
13777 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
13778 unallocated_encoding(s
);
13781 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
13782 unallocated_encoding(s
);
13785 case 0x8: case 0x9: /* Data processing - immediate */
13786 disas_data_proc_imm(s
, insn
);
13788 case 0xa: case 0xb: /* Branch, exception generation and system insns */
13789 disas_b_exc_sys(s
, insn
);
13794 case 0xe: /* Loads and stores */
13795 disas_ldst(s
, insn
);
13798 case 0xd: /* Data processing - register */
13799 disas_data_proc_reg(s
, insn
);
13802 case 0xf: /* Data processing - SIMD and floating point */
13803 disas_data_proc_simd_fp(s
, insn
);
13806 assert(FALSE
); /* all 15 cases should be handled above */
13810 /* if we allocated any temporaries, free them here */
13814 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
13817 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13818 CPUARMState
*env
= cpu
->env_ptr
;
13819 ARMCPU
*arm_cpu
= arm_env_get_cpu(env
);
13822 dc
->isar
= &arm_cpu
->isar
;
13823 dc
->pc
= dc
->base
.pc_first
;
13827 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
13828 * there is no secure EL1, so we route exceptions to EL3.
13830 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
13831 !arm_el_is_aa64(env
, 3);
13834 dc
->be_data
= ARM_TBFLAG_BE_DATA(dc
->base
.tb
->flags
) ? MO_BE
: MO_LE
;
13835 dc
->condexec_mask
= 0;
13836 dc
->condexec_cond
= 0;
13837 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, ARM_TBFLAG_MMUIDX(dc
->base
.tb
->flags
));
13838 dc
->tbi0
= ARM_TBFLAG_TBI0(dc
->base
.tb
->flags
);
13839 dc
->tbi1
= ARM_TBFLAG_TBI1(dc
->base
.tb
->flags
);
13840 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
13841 #if !defined(CONFIG_USER_ONLY)
13842 dc
->user
= (dc
->current_el
== 0);
13844 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(dc
->base
.tb
->flags
);
13845 dc
->sve_excp_el
= ARM_TBFLAG_SVEEXC_EL(dc
->base
.tb
->flags
);
13846 dc
->sve_len
= (ARM_TBFLAG_ZCR_LEN(dc
->base
.tb
->flags
) + 1) * 16;
13848 dc
->vec_stride
= 0;
13849 dc
->cp_regs
= arm_cpu
->cp_regs
;
13850 dc
->features
= env
->features
;
13852 /* Single step state. The code-generation logic here is:
13854 * generate code with no special handling for single-stepping (except
13855 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
13856 * this happens anyway because those changes are all system register or
13858 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
13859 * emit code for one insn
13860 * emit code to clear PSTATE.SS
13861 * emit code to generate software step exception for completed step
13862 * end TB (as usual for having generated an exception)
13863 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
13864 * emit code to generate a software step exception
13867 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(dc
->base
.tb
->flags
);
13868 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(dc
->base
.tb
->flags
);
13869 dc
->is_ldex
= false;
13870 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
13872 /* Bound the number of insns to execute to those left on the page. */
13873 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
13875 /* If architectural single step active, limit to 1. */
13876 if (dc
->ss_active
) {
13879 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
13881 init_tmp_a64_array(dc
);
13884 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
13888 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
13890 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13892 tcg_gen_insn_start(dc
->pc
, 0, 0);
13893 dc
->insn_start
= tcg_last_op();
13896 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
13897 const CPUBreakpoint
*bp
)
13899 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13901 if (bp
->flags
& BP_CPU
) {
13902 gen_a64_set_pc_im(dc
->pc
);
13903 gen_helper_check_breakpoints(cpu_env
);
13904 /* End the TB early; it likely won't be executed */
13905 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
13907 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
13908 /* The address covered by the breakpoint must be
13909 included in [tb->pc, tb->pc + tb->size) in order
13910 to for it to be properly cleared -- thus we
13911 increment the PC here so that the logic setting
13912 tb->size below does the right thing. */
13914 dc
->base
.is_jmp
= DISAS_NORETURN
;
13920 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
13922 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13923 CPUARMState
*env
= cpu
->env_ptr
;
13925 if (dc
->ss_active
&& !dc
->pstate_ss
) {
13926 /* Singlestep state is Active-pending.
13927 * If we're in this state at the start of a TB then either
13928 * a) we just took an exception to an EL which is being debugged
13929 * and this is the first insn in the exception handler
13930 * b) debug exceptions were masked and we just unmasked them
13931 * without changing EL (eg by clearing PSTATE.D)
13932 * In either case we're going to take a swstep exception in the
13933 * "did not step an insn" case, and so the syndrome ISV and EX
13934 * bits should be zero.
13936 assert(dc
->base
.num_insns
== 1);
13937 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
13938 default_exception_el(dc
));
13939 dc
->base
.is_jmp
= DISAS_NORETURN
;
13941 disas_a64_insn(env
, dc
);
13944 dc
->base
.pc_next
= dc
->pc
;
13945 translator_loop_temp_check(&dc
->base
);
13948 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
13950 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13952 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
13953 /* Note that this means single stepping WFI doesn't halt the CPU.
13954 * For conditional branch insns this is harmless unreachable code as
13955 * gen_goto_tb() has already handled emitting the debug exception
13956 * (and thus a tb-jump is not possible when singlestepping).
13958 switch (dc
->base
.is_jmp
) {
13960 gen_a64_set_pc_im(dc
->pc
);
13964 if (dc
->base
.singlestep_enabled
) {
13965 gen_exception_internal(EXCP_DEBUG
);
13967 gen_step_complete_exception(dc
);
13970 case DISAS_NORETURN
:
13974 switch (dc
->base
.is_jmp
) {
13976 case DISAS_TOO_MANY
:
13977 gen_goto_tb(dc
, 1, dc
->pc
);
13981 gen_a64_set_pc_im(dc
->pc
);
13984 tcg_gen_exit_tb(NULL
, 0);
13987 tcg_gen_lookup_and_goto_ptr();
13989 case DISAS_NORETURN
:
13993 gen_a64_set_pc_im(dc
->pc
);
13994 gen_helper_wfe(cpu_env
);
13997 gen_a64_set_pc_im(dc
->pc
);
13998 gen_helper_yield(cpu_env
);
14002 /* This is a special case because we don't want to just halt the CPU
14003 * if trying to debug across a WFI.
14005 TCGv_i32 tmp
= tcg_const_i32(4);
14007 gen_a64_set_pc_im(dc
->pc
);
14008 gen_helper_wfi(cpu_env
, tmp
);
14009 tcg_temp_free_i32(tmp
);
14010 /* The helper doesn't necessarily throw an exception, but we
14011 * must go back to the main loop to check for interrupts anyway.
14013 tcg_gen_exit_tb(NULL
, 0);
14019 /* Functions above can change dc->pc, so re-align db->pc_next */
14020 dc
->base
.pc_next
= dc
->pc
;
14023 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14026 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14028 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14029 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14032 const TranslatorOps aarch64_translator_ops
= {
14033 .init_disas_context
= aarch64_tr_init_disas_context
,
14034 .tb_start
= aarch64_tr_tb_start
,
14035 .insn_start
= aarch64_tr_insn_start
,
14036 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14037 .translate_insn
= aarch64_tr_translate_insn
,
14038 .tb_stop
= aarch64_tr_tb_stop
,
14039 .disas_log
= aarch64_tr_disas_log
,