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target-arm: Implement ISR_EL1 register
[qemu/ar7.git] / target-arm / helper.c
blob825c8c99ebfd62ac93791db4867554c9ed888667
1 #include "cpu.h"
2 #include "internals.h"
3 #include "exec/gdbstub.h"
4 #include "helper.h"
5 #include "qemu/host-utils.h"
6 #include "sysemu/arch_init.h"
7 #include "sysemu/sysemu.h"
8 #include "qemu/bitops.h"
9 #include "qemu/crc32c.h"
10 #include <zlib.h> /* For crc32 */
11
12 #ifndef CONFIG_USER_ONLY
13 #include "exec/softmmu_exec.h"
14
15 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
16 int access_type, int is_user,
17 hwaddr *phys_ptr, int *prot,
18 target_ulong *page_size);
19
20 /* Definitions for the PMCCNTR and PMCR registers */
21 #define PMCRD 0x8
22 #define PMCRC 0x4
23 #define PMCRE 0x1
24 #endif
25
26 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
27 {
28 int nregs;
29
30 /* VFP data registers are always little-endian. */
31 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
32 if (reg < nregs) {
33 stfq_le_p(buf, env->vfp.regs[reg]);
34 return 8;
35 }
36 if (arm_feature(env, ARM_FEATURE_NEON)) {
37 /* Aliases for Q regs. */
38 nregs += 16;
39 if (reg < nregs) {
40 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
41 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
42 return 16;
43 }
44 }
45 switch (reg - nregs) {
46 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
47 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
48 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
49 }
50 return 0;
51 }
52
53 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
54 {
55 int nregs;
56
57 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
58 if (reg < nregs) {
59 env->vfp.regs[reg] = ldfq_le_p(buf);
60 return 8;
61 }
62 if (arm_feature(env, ARM_FEATURE_NEON)) {
63 nregs += 16;
64 if (reg < nregs) {
65 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
66 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
67 return 16;
68 }
69 }
70 switch (reg - nregs) {
71 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
72 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
73 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
74 }
75 return 0;
76 }
77
78 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
79 {
80 switch (reg) {
81 case 0 ... 31:
82 /* 128 bit FP register */
83 stfq_le_p(buf, env->vfp.regs[reg * 2]);
84 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
85 return 16;
86 case 32:
87 /* FPSR */
88 stl_p(buf, vfp_get_fpsr(env));
89 return 4;
90 case 33:
91 /* FPCR */
92 stl_p(buf, vfp_get_fpcr(env));
93 return 4;
94 default:
95 return 0;
96 }
97 }
98
99 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
100 {
101 switch (reg) {
102 case 0 ... 31:
103 /* 128 bit FP register */
104 env->vfp.regs[reg * 2] = ldfq_le_p(buf);
105 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
106 return 16;
107 case 32:
108 /* FPSR */
109 vfp_set_fpsr(env, ldl_p(buf));
110 return 4;
111 case 33:
112 /* FPCR */
113 vfp_set_fpcr(env, ldl_p(buf));
114 return 4;
115 default:
116 return 0;
117 }
118 }
119
120 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
121 {
122 if (cpreg_field_is_64bit(ri)) {
123 return CPREG_FIELD64(env, ri);
124 } else {
125 return CPREG_FIELD32(env, ri);
126 }
127 }
128
129 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
130 uint64_t value)
131 {
132 if (cpreg_field_is_64bit(ri)) {
133 CPREG_FIELD64(env, ri) = value;
134 } else {
135 CPREG_FIELD32(env, ri) = value;
136 }
137 }
138
139 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
140 {
141 /* Raw read of a coprocessor register (as needed for migration, etc). */
142 if (ri->type & ARM_CP_CONST) {
143 return ri->resetvalue;
144 } else if (ri->raw_readfn) {
145 return ri->raw_readfn(env, ri);
146 } else if (ri->readfn) {
147 return ri->readfn(env, ri);
148 } else {
149 return raw_read(env, ri);
150 }
151 }
152
153 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
154 uint64_t v)
155 {
156 /* Raw write of a coprocessor register (as needed for migration, etc).
157 * Note that constant registers are treated as write-ignored; the
158 * caller should check for success by whether a readback gives the
159 * value written.
160 */
161 if (ri->type & ARM_CP_CONST) {
162 return;
163 } else if (ri->raw_writefn) {
164 ri->raw_writefn(env, ri, v);
165 } else if (ri->writefn) {
166 ri->writefn(env, ri, v);
167 } else {
168 raw_write(env, ri, v);
169 }
170 }
171
172 bool write_cpustate_to_list(ARMCPU *cpu)
173 {
174 /* Write the coprocessor state from cpu->env to the (index,value) list. */
175 int i;
176 bool ok = true;
177
178 for (i = 0; i < cpu->cpreg_array_len; i++) {
179 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
180 const ARMCPRegInfo *ri;
181
182 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
183 if (!ri) {
184 ok = false;
185 continue;
186 }
187 if (ri->type & ARM_CP_NO_MIGRATE) {
188 continue;
189 }
190 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
191 }
192 return ok;
193 }
194
195 bool write_list_to_cpustate(ARMCPU *cpu)
196 {
197 int i;
198 bool ok = true;
199
200 for (i = 0; i < cpu->cpreg_array_len; i++) {
201 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
202 uint64_t v = cpu->cpreg_values[i];
203 const ARMCPRegInfo *ri;
204
205 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
206 if (!ri) {
207 ok = false;
208 continue;
209 }
210 if (ri->type & ARM_CP_NO_MIGRATE) {
211 continue;
212 }
213 /* Write value and confirm it reads back as written
214 * (to catch read-only registers and partially read-only
215 * registers where the incoming migration value doesn't match)
216 */
217 write_raw_cp_reg(&cpu->env, ri, v);
218 if (read_raw_cp_reg(&cpu->env, ri) != v) {
219 ok = false;
220 }
221 }
222 return ok;
223 }
224
225 static void add_cpreg_to_list(gpointer key, gpointer opaque)
226 {
227 ARMCPU *cpu = opaque;
228 uint64_t regidx;
229 const ARMCPRegInfo *ri;
230
231 regidx = *(uint32_t *)key;
232 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
233
234 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
235 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
236 /* The value array need not be initialized at this point */
237 cpu->cpreg_array_len++;
238 }
239 }
240
241 static void count_cpreg(gpointer key, gpointer opaque)
242 {
243 ARMCPU *cpu = opaque;
244 uint64_t regidx;
245 const ARMCPRegInfo *ri;
246
247 regidx = *(uint32_t *)key;
248 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
249
250 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
251 cpu->cpreg_array_len++;
252 }
253 }
254
255 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
256 {
257 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
258 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
259
260 if (aidx > bidx) {
261 return 1;
262 }
263 if (aidx < bidx) {
264 return -1;
265 }
266 return 0;
267 }
268
269 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
270 {
271 GList **plist = udata;
272
273 *plist = g_list_prepend(*plist, key);
274 }
275
276 void init_cpreg_list(ARMCPU *cpu)
277 {
278 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
279 * Note that we require cpreg_tuples[] to be sorted by key ID.
280 */
281 GList *keys = NULL;
282 int arraylen;
283
284 g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
285
286 keys = g_list_sort(keys, cpreg_key_compare);
287
288 cpu->cpreg_array_len = 0;
289
290 g_list_foreach(keys, count_cpreg, cpu);
291
292 arraylen = cpu->cpreg_array_len;
293 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
294 cpu->cpreg_values = g_new(uint64_t, arraylen);
295 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
296 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
297 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
298 cpu->cpreg_array_len = 0;
299
300 g_list_foreach(keys, add_cpreg_to_list, cpu);
301
302 assert(cpu->cpreg_array_len == arraylen);
303
304 g_list_free(keys);
305 }
306
307 /* Return true if extended addresses are enabled.
308 * This is always the case if our translation regime is 64 bit,
309 * but depends on TTBCR.EAE for 32 bit.
310 */
311 static inline bool extended_addresses_enabled(CPUARMState *env)
312 {
313 return arm_el_is_aa64(env, 1)
314 || ((arm_feature(env, ARM_FEATURE_LPAE)
315 && (env->cp15.c2_control & (1U << 31))));
316 }
317
318 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
319 {
320 ARMCPU *cpu = arm_env_get_cpu(env);
321
322 env->cp15.c3 = value;
323 tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
324 }
325
326 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
327 {
328 ARMCPU *cpu = arm_env_get_cpu(env);
329
330 if (env->cp15.c13_fcse != value) {
331 /* Unlike real hardware the qemu TLB uses virtual addresses,
332 * not modified virtual addresses, so this causes a TLB flush.
333 */
334 tlb_flush(CPU(cpu), 1);
335 env->cp15.c13_fcse = value;
336 }
337 }
338
339 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
340 uint64_t value)
341 {
342 ARMCPU *cpu = arm_env_get_cpu(env);
343
344 if (env->cp15.contextidr_el1 != value && !arm_feature(env, ARM_FEATURE_MPU)
345 && !extended_addresses_enabled(env)) {
346 /* For VMSA (when not using the LPAE long descriptor page table
347 * format) this register includes the ASID, so do a TLB flush.
348 * For PMSA it is purely a process ID and no action is needed.
349 */
350 tlb_flush(CPU(cpu), 1);
351 }
352 env->cp15.contextidr_el1 = value;
353 }
354
355 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
356 uint64_t value)
357 {
358 /* Invalidate all (TLBIALL) */
359 ARMCPU *cpu = arm_env_get_cpu(env);
360
361 tlb_flush(CPU(cpu), 1);
362 }
363
364 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
365 uint64_t value)
366 {
367 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
368 ARMCPU *cpu = arm_env_get_cpu(env);
369
370 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
371 }
372
373 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
374 uint64_t value)
375 {
376 /* Invalidate by ASID (TLBIASID) */
377 ARMCPU *cpu = arm_env_get_cpu(env);
378
379 tlb_flush(CPU(cpu), value == 0);
380 }
381
382 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
383 uint64_t value)
384 {
385 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
386 ARMCPU *cpu = arm_env_get_cpu(env);
387
388 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
389 }
390
391 static const ARMCPRegInfo cp_reginfo[] = {
392 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
393 * version" bits will read as a reserved value, which should cause
394 * Linux to not try to use the debug hardware.
395 */
396 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
397 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
398 /* MMU Domain access control / MPU write buffer control */
399 { .name = "DACR", .cp = 15,
400 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
401 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
402 .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
403 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
404 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
405 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
406 { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH,
407 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
408 .access = PL1_RW,
409 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1),
410 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
411 /* ??? This covers not just the impdef TLB lockdown registers but also
412 * some v7VMSA registers relating to TEX remap, so it is overly broad.
413 */
414 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
415 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
416 /* MMU TLB control. Note that the wildcarding means we cover not just
417 * the unified TLB ops but also the dside/iside/inner-shareable variants.
418 */
419 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
420 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
421 .type = ARM_CP_NO_MIGRATE },
422 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
423 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
424 .type = ARM_CP_NO_MIGRATE },
425 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
426 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
427 .type = ARM_CP_NO_MIGRATE },
428 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
429 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
430 .type = ARM_CP_NO_MIGRATE },
431 /* Cache maintenance ops; some of this space may be overridden later. */
432 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
433 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
434 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
435 REGINFO_SENTINEL
436 };
437
438 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
439 /* Not all pre-v6 cores implemented this WFI, so this is slightly
440 * over-broad.
441 */
442 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
443 .access = PL1_W, .type = ARM_CP_WFI },
444 REGINFO_SENTINEL
445 };
446
447 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
448 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
449 * is UNPREDICTABLE; we choose to NOP as most implementations do).
450 */
451 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
452 .access = PL1_W, .type = ARM_CP_WFI },
453 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
454 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
455 * OMAPCP will override this space.
456 */
457 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
458 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
459 .resetvalue = 0 },
460 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
461 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
462 .resetvalue = 0 },
463 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
464 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
465 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
466 .resetvalue = 0 },
467 REGINFO_SENTINEL
468 };
469
470 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
471 uint64_t value)
472 {
473 if (env->cp15.c1_coproc != value) {
474 env->cp15.c1_coproc = value;
475 /* ??? Is this safe when called from within a TB? */
476 tb_flush(env);
477 }
478 }
479
480 static const ARMCPRegInfo v6_cp_reginfo[] = {
481 /* prefetch by MVA in v6, NOP in v7 */
482 { .name = "MVA_prefetch",
483 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
484 .access = PL1_W, .type = ARM_CP_NOP },
485 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
486 .access = PL0_W, .type = ARM_CP_NOP },
487 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
488 .access = PL0_W, .type = ARM_CP_NOP },
489 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
490 .access = PL0_W, .type = ARM_CP_NOP },
491 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
492 .access = PL1_RW,
493 .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1),
494 .resetvalue = 0, },
495 /* Watchpoint Fault Address Register : should actually only be present
496 * for 1136, 1176, 11MPCore.
497 */
498 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
499 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
500 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
501 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
502 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
503 .resetvalue = 0, .writefn = cpacr_write },
504 REGINFO_SENTINEL
505 };
506
507 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
508 {
509 /* Performance monitor registers user accessibility is controlled
510 * by PMUSERENR.
511 */
512 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
513 return CP_ACCESS_TRAP;
514 }
515 return CP_ACCESS_OK;
516 }
517
518 #ifndef CONFIG_USER_ONLY
519 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
520 uint64_t value)
521 {
522 /* Don't computer the number of ticks in user mode */
523 uint32_t temp_ticks;
524
525 temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
526 get_ticks_per_sec() / 1000000;
527
528 if (env->cp15.c9_pmcr & PMCRE) {
529 /* If the counter is enabled */
530 if (env->cp15.c9_pmcr & PMCRD) {
531 /* Increment once every 64 processor clock cycles */
532 env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
533 } else {
534 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
535 }
536 }
537
538 if (value & PMCRC) {
539 /* The counter has been reset */
540 env->cp15.c15_ccnt = 0;
541 }
542
543 /* only the DP, X, D and E bits are writable */
544 env->cp15.c9_pmcr &= ~0x39;
545 env->cp15.c9_pmcr |= (value & 0x39);
546
547 if (env->cp15.c9_pmcr & PMCRE) {
548 if (env->cp15.c9_pmcr & PMCRD) {
549 /* Increment once every 64 processor clock cycles */
550 temp_ticks /= 64;
551 }
552 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
553 }
554 }
555
556 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
557 {
558 uint32_t total_ticks;
559
560 if (!(env->cp15.c9_pmcr & PMCRE)) {
561 /* Counter is disabled, do not change value */
562 return env->cp15.c15_ccnt;
563 }
564
565 total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
566 get_ticks_per_sec() / 1000000;
567
568 if (env->cp15.c9_pmcr & PMCRD) {
569 /* Increment once every 64 processor clock cycles */
570 total_ticks /= 64;
571 }
572 return total_ticks - env->cp15.c15_ccnt;
573 }
574
575 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
576 uint64_t value)
577 {
578 uint32_t total_ticks;
579
580 if (!(env->cp15.c9_pmcr & PMCRE)) {
581 /* Counter is disabled, set the absolute value */
582 env->cp15.c15_ccnt = value;
583 return;
584 }
585
586 total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
587 get_ticks_per_sec() / 1000000;
588
589 if (env->cp15.c9_pmcr & PMCRD) {
590 /* Increment once every 64 processor clock cycles */
591 total_ticks /= 64;
592 }
593 env->cp15.c15_ccnt = total_ticks - value;
594 }
595 #endif
596
597 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
598 uint64_t value)
599 {
600 value &= (1 << 31);
601 env->cp15.c9_pmcnten |= value;
602 }
603
604 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
605 uint64_t value)
606 {
607 value &= (1 << 31);
608 env->cp15.c9_pmcnten &= ~value;
609 }
610
611 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
612 uint64_t value)
613 {
614 env->cp15.c9_pmovsr &= ~value;
615 }
616
617 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
618 uint64_t value)
619 {
620 env->cp15.c9_pmxevtyper = value & 0xff;
621 }
622
623 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
624 uint64_t value)
625 {
626 env->cp15.c9_pmuserenr = value & 1;
627 }
628
629 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
630 uint64_t value)
631 {
632 /* We have no event counters so only the C bit can be changed */
633 value &= (1 << 31);
634 env->cp15.c9_pminten |= value;
635 }
636
637 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
638 uint64_t value)
639 {
640 value &= (1 << 31);
641 env->cp15.c9_pminten &= ~value;
642 }
643
644 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
645 uint64_t value)
646 {
647 /* Note that even though the AArch64 view of this register has bits
648 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
649 * architectural requirements for bits which are RES0 only in some
650 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
651 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
652 */
653 env->cp15.c12_vbar = value & ~0x1Ful;
654 }
655
656 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
657 {
658 ARMCPU *cpu = arm_env_get_cpu(env);
659 return cpu->ccsidr[env->cp15.c0_cssel];
660 }
661
662 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
663 uint64_t value)
664 {
665 env->cp15.c0_cssel = value & 0xf;
666 }
667
668 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
669 {
670 CPUState *cs = ENV_GET_CPU(env);
671 uint64_t ret = 0;
672
673 if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
674 ret |= CPSR_I;
675 }
676 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
677 ret |= CPSR_F;
678 }
679 /* External aborts are not possible in QEMU so A bit is always clear */
680 return ret;
681 }
682
683 static const ARMCPRegInfo v7_cp_reginfo[] = {
684 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
685 * debug components
686 */
687 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
688 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
689 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
690 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
691 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
692 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
693 .access = PL1_W, .type = ARM_CP_NOP },
694 /* Performance monitors are implementation defined in v7,
695 * but with an ARM recommended set of registers, which we
696 * follow (although we don't actually implement any counters)
697 *
698 * Performance registers fall into three categories:
699 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
700 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
701 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
702 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
703 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
704 */
705 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
706 .access = PL0_RW, .resetvalue = 0,
707 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
708 .writefn = pmcntenset_write,
709 .accessfn = pmreg_access,
710 .raw_writefn = raw_write },
711 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
712 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
713 .accessfn = pmreg_access,
714 .writefn = pmcntenclr_write,
715 .type = ARM_CP_NO_MIGRATE },
716 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
717 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
718 .accessfn = pmreg_access,
719 .writefn = pmovsr_write,
720 .raw_writefn = raw_write },
721 /* Unimplemented so WI. */
722 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
723 .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
724 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
725 * We choose to RAZ/WI.
726 */
727 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
728 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
729 .accessfn = pmreg_access },
730 #ifndef CONFIG_USER_ONLY
731 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
732 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
733 .readfn = pmccntr_read, .writefn = pmccntr_write,
734 .accessfn = pmreg_access },
735 #endif
736 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
737 .access = PL0_RW,
738 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
739 .accessfn = pmreg_access, .writefn = pmxevtyper_write,
740 .raw_writefn = raw_write },
741 /* Unimplemented, RAZ/WI. */
742 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
743 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
744 .accessfn = pmreg_access },
745 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
746 .access = PL0_R | PL1_RW,
747 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
748 .resetvalue = 0,
749 .writefn = pmuserenr_write, .raw_writefn = raw_write },
750 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
751 .access = PL1_RW,
752 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
753 .resetvalue = 0,
754 .writefn = pmintenset_write, .raw_writefn = raw_write },
755 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
756 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
757 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
758 .resetvalue = 0, .writefn = pmintenclr_write, },
759 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
760 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
761 .access = PL1_RW, .writefn = vbar_write,
762 .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
763 .resetvalue = 0 },
764 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
765 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
766 .resetvalue = 0, },
767 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
768 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
769 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
770 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
771 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
772 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
773 .writefn = csselr_write, .resetvalue = 0 },
774 /* Auxiliary ID register: this actually has an IMPDEF value but for now
775 * just RAZ for all cores:
776 */
777 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
778 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
779 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
780 /* MAIR can just read-as-written because we don't implement caches
781 * and so don't need to care about memory attributes.
782 */
783 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
784 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
785 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
786 .resetvalue = 0 },
787 /* For non-long-descriptor page tables these are PRRR and NMRR;
788 * regardless they still act as reads-as-written for QEMU.
789 * The override is necessary because of the overly-broad TLB_LOCKDOWN
790 * definition.
791 */
792 { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
793 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
794 .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
795 .resetfn = arm_cp_reset_ignore },
796 { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
797 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
798 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
799 .resetfn = arm_cp_reset_ignore },
800 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
801 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
802 .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
803 REGINFO_SENTINEL
804 };
805
806 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
807 uint64_t value)
808 {
809 value &= 1;
810 env->teecr = value;
811 }
812
813 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
814 {
815 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
816 return CP_ACCESS_TRAP;
817 }
818 return CP_ACCESS_OK;
819 }
820
821 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
822 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
823 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
824 .resetvalue = 0,
825 .writefn = teecr_write },
826 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
827 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
828 .accessfn = teehbr_access, .resetvalue = 0 },
829 REGINFO_SENTINEL
830 };
831
832 static const ARMCPRegInfo v6k_cp_reginfo[] = {
833 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
834 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
835 .access = PL0_RW,
836 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
837 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
838 .access = PL0_RW,
839 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
840 .resetfn = arm_cp_reset_ignore },
841 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
842 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
843 .access = PL0_R|PL1_W,
844 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
845 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
846 .access = PL0_R|PL1_W,
847 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
848 .resetfn = arm_cp_reset_ignore },
849 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
850 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
851 .access = PL1_RW,
852 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
853 REGINFO_SENTINEL
854 };
855
856 #ifndef CONFIG_USER_ONLY
857
858 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
859 {
860 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
861 if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
862 return CP_ACCESS_TRAP;
863 }
864 return CP_ACCESS_OK;
865 }
866
867 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
868 {
869 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
870 if (arm_current_pl(env) == 0 &&
871 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
872 return CP_ACCESS_TRAP;
873 }
874 return CP_ACCESS_OK;
875 }
876
877 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
878 {
879 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
880 * EL0[PV]TEN is zero.
881 */
882 if (arm_current_pl(env) == 0 &&
883 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
884 return CP_ACCESS_TRAP;
885 }
886 return CP_ACCESS_OK;
887 }
888
889 static CPAccessResult gt_pct_access(CPUARMState *env,
890 const ARMCPRegInfo *ri)
891 {
892 return gt_counter_access(env, GTIMER_PHYS);
893 }
894
895 static CPAccessResult gt_vct_access(CPUARMState *env,
896 const ARMCPRegInfo *ri)
897 {
898 return gt_counter_access(env, GTIMER_VIRT);
899 }
900
901 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
902 {
903 return gt_timer_access(env, GTIMER_PHYS);
904 }
905
906 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
907 {
908 return gt_timer_access(env, GTIMER_VIRT);
909 }
910
911 static uint64_t gt_get_countervalue(CPUARMState *env)
912 {
913 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
914 }
915
916 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
917 {
918 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
919
920 if (gt->ctl & 1) {
921 /* Timer enabled: calculate and set current ISTATUS, irq, and
922 * reset timer to when ISTATUS next has to change
923 */
924 uint64_t count = gt_get_countervalue(&cpu->env);
925 /* Note that this must be unsigned 64 bit arithmetic: */
926 int istatus = count >= gt->cval;
927 uint64_t nexttick;
928
929 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
930 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
931 (istatus && !(gt->ctl & 2)));
932 if (istatus) {
933 /* Next transition is when count rolls back over to zero */
934 nexttick = UINT64_MAX;
935 } else {
936 /* Next transition is when we hit cval */
937 nexttick = gt->cval;
938 }
939 /* Note that the desired next expiry time might be beyond the
940 * signed-64-bit range of a QEMUTimer -- in this case we just
941 * set the timer for as far in the future as possible. When the
942 * timer expires we will reset the timer for any remaining period.
943 */
944 if (nexttick > INT64_MAX / GTIMER_SCALE) {
945 nexttick = INT64_MAX / GTIMER_SCALE;
946 }
947 timer_mod(cpu->gt_timer[timeridx], nexttick);
948 } else {
949 /* Timer disabled: ISTATUS and timer output always clear */
950 gt->ctl &= ~4;
951 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
952 timer_del(cpu->gt_timer[timeridx]);
953 }
954 }
955
956 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
957 {
958 ARMCPU *cpu = arm_env_get_cpu(env);
959 int timeridx = ri->opc1 & 1;
960
961 timer_del(cpu->gt_timer[timeridx]);
962 }
963
964 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
965 {
966 return gt_get_countervalue(env);
967 }
968
969 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
970 uint64_t value)
971 {
972 int timeridx = ri->opc1 & 1;
973
974 env->cp15.c14_timer[timeridx].cval = value;
975 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
976 }
977
978 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
979 {
980 int timeridx = ri->crm & 1;
981
982 return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
983 gt_get_countervalue(env));
984 }
985
986 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
987 uint64_t value)
988 {
989 int timeridx = ri->crm & 1;
990
991 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
992 + sextract64(value, 0, 32);
993 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
994 }
995
996 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
997 uint64_t value)
998 {
999 ARMCPU *cpu = arm_env_get_cpu(env);
1000 int timeridx = ri->crm & 1;
1001 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1002
1003 env->cp15.c14_timer[timeridx].ctl = value & 3;
1004 if ((oldval ^ value) & 1) {
1005 /* Enable toggled */
1006 gt_recalc_timer(cpu, timeridx);
1007 } else if ((oldval & value) & 2) {
1008 /* IMASK toggled: don't need to recalculate,
1009 * just set the interrupt line based on ISTATUS
1010 */
1011 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1012 (oldval & 4) && (value & 2));
1013 }
1014 }
1015
1016 void arm_gt_ptimer_cb(void *opaque)
1017 {
1018 ARMCPU *cpu = opaque;
1019
1020 gt_recalc_timer(cpu, GTIMER_PHYS);
1021 }
1022
1023 void arm_gt_vtimer_cb(void *opaque)
1024 {
1025 ARMCPU *cpu = opaque;
1026
1027 gt_recalc_timer(cpu, GTIMER_VIRT);
1028 }
1029
1030 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1031 /* Note that CNTFRQ is purely reads-as-written for the benefit
1032 * of software; writing it doesn't actually change the timer frequency.
1033 * Our reset value matches the fixed frequency we implement the timer at.
1034 */
1035 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1036 .type = ARM_CP_NO_MIGRATE,
1037 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1038 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1039 .resetfn = arm_cp_reset_ignore,
1040 },
1041 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1042 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1043 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1044 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1045 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1046 },
1047 /* overall control: mostly access permissions */
1048 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1049 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1050 .access = PL1_RW,
1051 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1052 .resetvalue = 0,
1053 },
1054 /* per-timer control */
1055 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1056 .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1057 .accessfn = gt_ptimer_access,
1058 .fieldoffset = offsetoflow32(CPUARMState,
1059 cp15.c14_timer[GTIMER_PHYS].ctl),
1060 .resetfn = arm_cp_reset_ignore,
1061 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1062 },
1063 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1064 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1065 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1066 .accessfn = gt_ptimer_access,
1067 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1068 .resetvalue = 0,
1069 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1070 },
1071 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1072 .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1073 .accessfn = gt_vtimer_access,
1074 .fieldoffset = offsetoflow32(CPUARMState,
1075 cp15.c14_timer[GTIMER_VIRT].ctl),
1076 .resetfn = arm_cp_reset_ignore,
1077 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1078 },
1079 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1080 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1081 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1082 .accessfn = gt_vtimer_access,
1083 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1084 .resetvalue = 0,
1085 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1086 },
1087 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1088 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1089 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1090 .accessfn = gt_ptimer_access,
1091 .readfn = gt_tval_read, .writefn = gt_tval_write,
1092 },
1093 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1094 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1095 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1096 .readfn = gt_tval_read, .writefn = gt_tval_write,
1097 },
1098 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1099 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1100 .accessfn = gt_vtimer_access,
1101 .readfn = gt_tval_read, .writefn = gt_tval_write,
1102 },
1103 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1104 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1105 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1106 .readfn = gt_tval_read, .writefn = gt_tval_write,
1107 },
1108 /* The counter itself */
1109 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1110 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1111 .accessfn = gt_pct_access,
1112 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1113 },
1114 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1115 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1116 .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1117 .accessfn = gt_pct_access,
1118 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1119 },
1120 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1121 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1122 .accessfn = gt_vct_access,
1123 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1124 },
1125 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1126 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1127 .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1128 .accessfn = gt_vct_access,
1129 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1130 },
1131 /* Comparison value, indicating when the timer goes off */
1132 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1133 .access = PL1_RW | PL0_R,
1134 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1135 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1136 .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1137 .writefn = gt_cval_write, .raw_writefn = raw_write,
1138 },
1139 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1140 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1141 .access = PL1_RW | PL0_R,
1142 .type = ARM_CP_IO,
1143 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1144 .resetvalue = 0, .accessfn = gt_vtimer_access,
1145 .writefn = gt_cval_write, .raw_writefn = raw_write,
1146 },
1147 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1148 .access = PL1_RW | PL0_R,
1149 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1150 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1151 .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1152 .writefn = gt_cval_write, .raw_writefn = raw_write,
1153 },
1154 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1155 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1156 .access = PL1_RW | PL0_R,
1157 .type = ARM_CP_IO,
1158 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1159 .resetvalue = 0, .accessfn = gt_vtimer_access,
1160 .writefn = gt_cval_write, .raw_writefn = raw_write,
1161 },
1162 REGINFO_SENTINEL
1163 };
1164
1165 #else
1166 /* In user-mode none of the generic timer registers are accessible,
1167 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1168 * so instead just don't register any of them.
1169 */
1170 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1171 REGINFO_SENTINEL
1172 };
1173
1174 #endif
1175
1176 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1177 {
1178 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1179 env->cp15.c7_par = value;
1180 } else if (arm_feature(env, ARM_FEATURE_V7)) {
1181 env->cp15.c7_par = value & 0xfffff6ff;
1182 } else {
1183 env->cp15.c7_par = value & 0xfffff1ff;
1184 }
1185 }
1186
1187 #ifndef CONFIG_USER_ONLY
1188 /* get_phys_addr() isn't present for user-mode-only targets */
1189
1190 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1191 {
1192 if (ri->opc2 & 4) {
1193 /* Other states are only available with TrustZone; in
1194 * a non-TZ implementation these registers don't exist
1195 * at all, which is an Uncategorized trap. This underdecoding
1196 * is safe because the reginfo is NO_MIGRATE.
1197 */
1198 return CP_ACCESS_TRAP_UNCATEGORIZED;
1199 }
1200 return CP_ACCESS_OK;
1201 }
1202
1203 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1204 {
1205 hwaddr phys_addr;
1206 target_ulong page_size;
1207 int prot;
1208 int ret, is_user = ri->opc2 & 2;
1209 int access_type = ri->opc2 & 1;
1210
1211 ret = get_phys_addr(env, value, access_type, is_user,
1212 &phys_addr, &prot, &page_size);
1213 if (extended_addresses_enabled(env)) {
1214 /* ret is a DFSR/IFSR value for the long descriptor
1215 * translation table format, but with WnR always clear.
1216 * Convert it to a 64-bit PAR.
1217 */
1218 uint64_t par64 = (1 << 11); /* LPAE bit always set */
1219 if (ret == 0) {
1220 par64 |= phys_addr & ~0xfffULL;
1221 /* We don't set the ATTR or SH fields in the PAR. */
1222 } else {
1223 par64 |= 1; /* F */
1224 par64 |= (ret & 0x3f) << 1; /* FS */
1225 /* Note that S2WLK and FSTAGE are always zero, because we don't
1226 * implement virtualization and therefore there can't be a stage 2
1227 * fault.
1228 */
1229 }
1230 env->cp15.c7_par = par64;
1231 env->cp15.c7_par_hi = par64 >> 32;
1232 } else {
1233 /* ret is a DFSR/IFSR value for the short descriptor
1234 * translation table format (with WnR always clear).
1235 * Convert it to a 32-bit PAR.
1236 */
1237 if (ret == 0) {
1238 /* We do not set any attribute bits in the PAR */
1239 if (page_size == (1 << 24)
1240 && arm_feature(env, ARM_FEATURE_V7)) {
1241 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1242 } else {
1243 env->cp15.c7_par = phys_addr & 0xfffff000;
1244 }
1245 } else {
1246 env->cp15.c7_par = ((ret & (1 << 10)) >> 5) |
1247 ((ret & (1 << 12)) >> 6) |
1248 ((ret & 0xf) << 1) | 1;
1249 }
1250 env->cp15.c7_par_hi = 0;
1251 }
1252 }
1253 #endif
1254
1255 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1256 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1257 .access = PL1_RW, .resetvalue = 0,
1258 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
1259 .writefn = par_write },
1260 #ifndef CONFIG_USER_ONLY
1261 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1262 .access = PL1_W, .accessfn = ats_access,
1263 .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1264 #endif
1265 REGINFO_SENTINEL
1266 };
1267
1268 /* Return basic MPU access permission bits. */
1269 static uint32_t simple_mpu_ap_bits(uint32_t val)
1270 {
1271 uint32_t ret;
1272 uint32_t mask;
1273 int i;
1274 ret = 0;
1275 mask = 3;
1276 for (i = 0; i < 16; i += 2) {
1277 ret |= (val >> i) & mask;
1278 mask <<= 2;
1279 }
1280 return ret;
1281 }
1282
1283 /* Pad basic MPU access permission bits to extended format. */
1284 static uint32_t extended_mpu_ap_bits(uint32_t val)
1285 {
1286 uint32_t ret;
1287 uint32_t mask;
1288 int i;
1289 ret = 0;
1290 mask = 3;
1291 for (i = 0; i < 16; i += 2) {
1292 ret |= (val & mask) << i;
1293 mask <<= 2;
1294 }
1295 return ret;
1296 }
1297
1298 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1299 uint64_t value)
1300 {
1301 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1302 }
1303
1304 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1305 {
1306 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1307 }
1308
1309 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1310 uint64_t value)
1311 {
1312 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1313 }
1314
1315 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1316 {
1317 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1318 }
1319
1320 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1321 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1322 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1323 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1324 .resetvalue = 0,
1325 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1326 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1327 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1328 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1329 .resetvalue = 0,
1330 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1331 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1332 .access = PL1_RW,
1333 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1334 .resetvalue = 0, },
1335 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1336 .access = PL1_RW,
1337 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1338 .resetvalue = 0, },
1339 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1340 .access = PL1_RW,
1341 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1342 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1343 .access = PL1_RW,
1344 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1345 /* Protection region base and size registers */
1346 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1347 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1348 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1349 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1350 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1351 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1352 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1353 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1354 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1355 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1356 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1357 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1358 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1359 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1360 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1361 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1362 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1363 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1364 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1365 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1366 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1367 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1368 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1369 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1370 REGINFO_SENTINEL
1371 };
1372
1373 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1374 uint64_t value)
1375 {
1376 int maskshift = extract32(value, 0, 3);
1377
1378 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) {
1379 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1380 } else {
1381 value &= 7;
1382 }
1383 /* Note that we always calculate c2_mask and c2_base_mask, but
1384 * they are only used for short-descriptor tables (ie if EAE is 0);
1385 * for long-descriptor tables the TTBCR fields are used differently
1386 * and the c2_mask and c2_base_mask values are meaningless.
1387 */
1388 env->cp15.c2_control = value;
1389 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1390 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1391 }
1392
1393 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1394 uint64_t value)
1395 {
1396 ARMCPU *cpu = arm_env_get_cpu(env);
1397
1398 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1399 /* With LPAE the TTBCR could result in a change of ASID
1400 * via the TTBCR.A1 bit, so do a TLB flush.
1401 */
1402 tlb_flush(CPU(cpu), 1);
1403 }
1404 vmsa_ttbcr_raw_write(env, ri, value);
1405 }
1406
1407 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1408 {
1409 env->cp15.c2_base_mask = 0xffffc000u;
1410 env->cp15.c2_control = 0;
1411 env->cp15.c2_mask = 0;
1412 }
1413
1414 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1415 uint64_t value)
1416 {
1417 ARMCPU *cpu = arm_env_get_cpu(env);
1418
1419 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1420 tlb_flush(CPU(cpu), 1);
1421 env->cp15.c2_control = value;
1422 }
1423
1424 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1425 uint64_t value)
1426 {
1427 /* 64 bit accesses to the TTBRs can change the ASID and so we
1428 * must flush the TLB.
1429 */
1430 if (cpreg_field_is_64bit(ri)) {
1431 ARMCPU *cpu = arm_env_get_cpu(env);
1432
1433 tlb_flush(CPU(cpu), 1);
1434 }
1435 raw_write(env, ri, value);
1436 }
1437
1438 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1439 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1440 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1441 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el1),
1442 .resetfn = arm_cp_reset_ignore, },
1443 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1444 .access = PL1_RW,
1445 .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, },
1446 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
1447 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
1448 .access = PL1_RW,
1449 .fieldoffset = offsetof(CPUARMState, cp15.esr_el1), .resetvalue = 0, },
1450 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1451 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1452 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1453 .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1454 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1455 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1456 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1457 .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1458 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1459 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1460 .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1461 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1462 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1463 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1464 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
1465 .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1466 .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
1467 /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
1468 { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
1469 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1470 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el1),
1471 .resetvalue = 0, },
1472 REGINFO_SENTINEL
1473 };
1474
1475 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1476 uint64_t value)
1477 {
1478 env->cp15.c15_ticonfig = value & 0xe7;
1479 /* The OS_TYPE bit in this register changes the reported CPUID! */
1480 env->cp15.c0_cpuid = (value & (1 << 5)) ?
1481 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1482 }
1483
1484 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1485 uint64_t value)
1486 {
1487 env->cp15.c15_threadid = value & 0xffff;
1488 }
1489
1490 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1491 uint64_t value)
1492 {
1493 /* Wait-for-interrupt (deprecated) */
1494 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1495 }
1496
1497 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1498 uint64_t value)
1499 {
1500 /* On OMAP there are registers indicating the max/min index of dcache lines
1501 * containing a dirty line; cache flush operations have to reset these.
1502 */
1503 env->cp15.c15_i_max = 0x000;
1504 env->cp15.c15_i_min = 0xff0;
1505 }
1506
1507 static const ARMCPRegInfo omap_cp_reginfo[] = {
1508 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1509 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1510 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el1),
1511 .resetvalue = 0, },
1512 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1513 .access = PL1_RW, .type = ARM_CP_NOP },
1514 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1515 .access = PL1_RW,
1516 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1517 .writefn = omap_ticonfig_write },
1518 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1519 .access = PL1_RW,
1520 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1521 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1522 .access = PL1_RW, .resetvalue = 0xff0,
1523 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1524 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1525 .access = PL1_RW,
1526 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1527 .writefn = omap_threadid_write },
1528 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1529 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1530 .type = ARM_CP_NO_MIGRATE,
1531 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1532 /* TODO: Peripheral port remap register:
1533 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1534 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1535 * when MMU is off.
1536 */
1537 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1538 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1539 .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1540 .writefn = omap_cachemaint_write },
1541 { .name = "C9", .cp = 15, .crn = 9,
1542 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1543 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1544 REGINFO_SENTINEL
1545 };
1546
1547 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1548 uint64_t value)
1549 {
1550 value &= 0x3fff;
1551 if (env->cp15.c15_cpar != value) {
1552 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1553 tb_flush(env);
1554 env->cp15.c15_cpar = value;
1555 }
1556 }
1557
1558 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1559 { .name = "XSCALE_CPAR",
1560 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1561 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1562 .writefn = xscale_cpar_write, },
1563 { .name = "XSCALE_AUXCR",
1564 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1565 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1566 .resetvalue = 0, },
1567 REGINFO_SENTINEL
1568 };
1569
1570 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1571 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1572 * implementation of this implementation-defined space.
1573 * Ideally this should eventually disappear in favour of actually
1574 * implementing the correct behaviour for all cores.
1575 */
1576 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1577 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1578 .access = PL1_RW,
1579 .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1580 .resetvalue = 0 },
1581 REGINFO_SENTINEL
1582 };
1583
1584 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1585 /* Cache status: RAZ because we have no cache so it's always clean */
1586 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1587 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1588 .resetvalue = 0 },
1589 REGINFO_SENTINEL
1590 };
1591
1592 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1593 /* We never have a a block transfer operation in progress */
1594 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1595 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1596 .resetvalue = 0 },
1597 /* The cache ops themselves: these all NOP for QEMU */
1598 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1599 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1600 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1601 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1602 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1603 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1604 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1605 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1606 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1607 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1608 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1609 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1610 REGINFO_SENTINEL
1611 };
1612
1613 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1614 /* The cache test-and-clean instructions always return (1 << 30)
1615 * to indicate that there are no dirty cache lines.
1616 */
1617 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1618 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1619 .resetvalue = (1 << 30) },
1620 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1621 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1622 .resetvalue = (1 << 30) },
1623 REGINFO_SENTINEL
1624 };
1625
1626 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1627 /* Ignore ReadBuffer accesses */
1628 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1629 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1630 .access = PL1_RW, .resetvalue = 0,
1631 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1632 REGINFO_SENTINEL
1633 };
1634
1635 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1636 {
1637 CPUState *cs = CPU(arm_env_get_cpu(env));
1638 uint32_t mpidr = cs->cpu_index;
1639 /* We don't support setting cluster ID ([8..11]) (known as Aff1
1640 * in later ARM ARM versions), or any of the higher affinity level fields,
1641 * so these bits always RAZ.
1642 */
1643 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1644 mpidr |= (1U << 31);
1645 /* Cores which are uniprocessor (non-coherent)
1646 * but still implement the MP extensions set
1647 * bit 30. (For instance, A9UP.) However we do
1648 * not currently model any of those cores.
1649 */
1650 }
1651 return mpidr;
1652 }
1653
1654 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1655 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
1656 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1657 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1658 REGINFO_SENTINEL
1659 };
1660
1661 static uint64_t par64_read(CPUARMState *env, const ARMCPRegInfo *ri)
1662 {
1663 return ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1664 }
1665
1666 static void par64_write(CPUARMState *env, const ARMCPRegInfo *ri,
1667 uint64_t value)
1668 {
1669 env->cp15.c7_par_hi = value >> 32;
1670 env->cp15.c7_par = value;
1671 }
1672
1673 static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1674 {
1675 env->cp15.c7_par_hi = 0;
1676 env->cp15.c7_par = 0;
1677 }
1678
1679 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1680 /* NOP AMAIR0/1: the override is because these clash with the rather
1681 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1682 */
1683 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
1684 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1685 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1686 .resetvalue = 0 },
1687 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1688 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1689 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1690 .resetvalue = 0 },
1691 /* 64 bit access versions of the (dummy) debug registers */
1692 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1693 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1694 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1695 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1696 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1697 .access = PL1_RW, .type = ARM_CP_64BIT,
1698 .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1699 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1700 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1701 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1702 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1703 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1704 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1705 .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1706 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1707 REGINFO_SENTINEL
1708 };
1709
1710 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1711 {
1712 return vfp_get_fpcr(env);
1713 }
1714
1715 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1716 uint64_t value)
1717 {
1718 vfp_set_fpcr(env, value);
1719 }
1720
1721 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1722 {
1723 return vfp_get_fpsr(env);
1724 }
1725
1726 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1727 uint64_t value)
1728 {
1729 vfp_set_fpsr(env, value);
1730 }
1731
1732 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
1733 {
1734 if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
1735 return CP_ACCESS_TRAP;
1736 }
1737 return CP_ACCESS_OK;
1738 }
1739
1740 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
1741 uint64_t value)
1742 {
1743 env->daif = value & PSTATE_DAIF;
1744 }
1745
1746 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
1747 const ARMCPRegInfo *ri)
1748 {
1749 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1750 * SCTLR_EL1.UCI is set.
1751 */
1752 if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
1753 return CP_ACCESS_TRAP;
1754 }
1755 return CP_ACCESS_OK;
1756 }
1757
1758 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
1759 uint64_t value)
1760 {
1761 /* Invalidate by VA (AArch64 version) */
1762 ARMCPU *cpu = arm_env_get_cpu(env);
1763 uint64_t pageaddr = value << 12;
1764 tlb_flush_page(CPU(cpu), pageaddr);
1765 }
1766
1767 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
1768 uint64_t value)
1769 {
1770 /* Invalidate by VA, all ASIDs (AArch64 version) */
1771 ARMCPU *cpu = arm_env_get_cpu(env);
1772 uint64_t pageaddr = value << 12;
1773 tlb_flush_page(CPU(cpu), pageaddr);
1774 }
1775
1776 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1777 uint64_t value)
1778 {
1779 /* Invalidate by ASID (AArch64 version) */
1780 ARMCPU *cpu = arm_env_get_cpu(env);
1781 int asid = extract64(value, 48, 16);
1782 tlb_flush(CPU(cpu), asid == 0);
1783 }
1784
1785 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
1786 {
1787 /* We don't implement EL2, so the only control on DC ZVA is the
1788 * bit in the SCTLR which can prohibit access for EL0.
1789 */
1790 if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_DZE)) {
1791 return CP_ACCESS_TRAP;
1792 }
1793 return CP_ACCESS_OK;
1794 }
1795
1796 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
1797 {
1798 ARMCPU *cpu = arm_env_get_cpu(env);
1799 int dzp_bit = 1 << 4;
1800
1801 /* DZP indicates whether DC ZVA access is allowed */
1802 if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) {
1803 dzp_bit = 0;
1804 }
1805 return cpu->dcz_blocksize | dzp_bit;
1806 }
1807
1808 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
1809 {
1810 if (!env->pstate & PSTATE_SP) {
1811 /* Access to SP_EL0 is undefined if it's being used as
1812 * the stack pointer.
1813 */
1814 return CP_ACCESS_TRAP_UNCATEGORIZED;
1815 }
1816 return CP_ACCESS_OK;
1817 }
1818
1819 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
1820 {
1821 return env->pstate & PSTATE_SP;
1822 }
1823
1824 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
1825 {
1826 update_spsel(env, val);
1827 }
1828
1829 static const ARMCPRegInfo v8_cp_reginfo[] = {
1830 /* Minimal set of EL0-visible registers. This will need to be expanded
1831 * significantly for system emulation of AArch64 CPUs.
1832 */
1833 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1834 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1835 .access = PL0_RW, .type = ARM_CP_NZCV },
1836 { .name = "DAIF", .state = ARM_CP_STATE_AA64,
1837 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
1838 .type = ARM_CP_NO_MIGRATE,
1839 .access = PL0_RW, .accessfn = aa64_daif_access,
1840 .fieldoffset = offsetof(CPUARMState, daif),
1841 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
1842 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1843 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1844 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1845 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1846 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1847 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1848 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1849 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1850 .access = PL0_R, .type = ARM_CP_NO_MIGRATE,
1851 .readfn = aa64_dczid_read },
1852 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
1853 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
1854 .access = PL0_W, .type = ARM_CP_DC_ZVA,
1855 #ifndef CONFIG_USER_ONLY
1856 /* Avoid overhead of an access check that always passes in user-mode */
1857 .accessfn = aa64_zva_access,
1858 #endif
1859 },
1860 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
1861 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
1862 .access = PL1_R, .type = ARM_CP_CURRENTEL },
1863 /* Cache ops: all NOPs since we don't emulate caches */
1864 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
1865 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
1866 .access = PL1_W, .type = ARM_CP_NOP },
1867 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
1868 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
1869 .access = PL1_W, .type = ARM_CP_NOP },
1870 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
1871 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
1872 .access = PL0_W, .type = ARM_CP_NOP,
1873 .accessfn = aa64_cacheop_access },
1874 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
1875 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
1876 .access = PL1_W, .type = ARM_CP_NOP },
1877 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
1878 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
1879 .access = PL1_W, .type = ARM_CP_NOP },
1880 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
1881 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
1882 .access = PL0_W, .type = ARM_CP_NOP,
1883 .accessfn = aa64_cacheop_access },
1884 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
1885 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
1886 .access = PL1_W, .type = ARM_CP_NOP },
1887 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
1888 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
1889 .access = PL0_W, .type = ARM_CP_NOP,
1890 .accessfn = aa64_cacheop_access },
1891 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
1892 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
1893 .access = PL0_W, .type = ARM_CP_NOP,
1894 .accessfn = aa64_cacheop_access },
1895 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
1896 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
1897 .access = PL1_W, .type = ARM_CP_NOP },
1898 /* TLBI operations */
1899 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
1900 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1901 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1902 .writefn = tlbiall_write },
1903 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
1904 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1905 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1906 .writefn = tlbi_aa64_va_write },
1907 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
1908 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1909 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1910 .writefn = tlbi_aa64_asid_write },
1911 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
1912 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1913 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1914 .writefn = tlbi_aa64_vaa_write },
1915 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
1916 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 5,
1917 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1918 .writefn = tlbi_aa64_va_write },
1919 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
1920 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 7,
1921 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1922 .writefn = tlbi_aa64_vaa_write },
1923 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
1924 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1925 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1926 .writefn = tlbiall_write },
1927 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
1928 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1929 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1930 .writefn = tlbi_aa64_va_write },
1931 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
1932 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1933 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1934 .writefn = tlbi_aa64_asid_write },
1935 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
1936 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1937 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1938 .writefn = tlbi_aa64_vaa_write },
1939 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
1940 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 5,
1941 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1942 .writefn = tlbi_aa64_va_write },
1943 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
1944 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7,
1945 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1946 .writefn = tlbi_aa64_vaa_write },
1947 /* Dummy implementation of monitor debug system control register:
1948 * we don't support debug.
1949 */
1950 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
1951 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
1952 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1953 /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
1954 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
1955 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
1956 .access = PL1_W, .type = ARM_CP_NOP },
1957 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
1958 .type = ARM_CP_NO_MIGRATE,
1959 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
1960 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, elr_el1) },
1961 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
1962 .type = ARM_CP_NO_MIGRATE,
1963 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
1964 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
1965 /* We rely on the access checks not allowing the guest to write to the
1966 * state field when SPSel indicates that it's being used as the stack
1967 * pointer.
1968 */
1969 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
1970 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
1971 .access = PL1_RW, .accessfn = sp_el0_access,
1972 .type = ARM_CP_NO_MIGRATE,
1973 .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
1974 { .name = "SPSel", .state = ARM_CP_STATE_AA64,
1975 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
1976 .type = ARM_CP_NO_MIGRATE,
1977 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
1978 REGINFO_SENTINEL
1979 };
1980
1981 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1982 uint64_t value)
1983 {
1984 ARMCPU *cpu = arm_env_get_cpu(env);
1985
1986 env->cp15.c1_sys = value;
1987 /* ??? Lots of these bits are not implemented. */
1988 /* This may enable/disable the MMU, so do a TLB flush. */
1989 tlb_flush(CPU(cpu), 1);
1990 }
1991
1992 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
1993 {
1994 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
1995 * but the AArch32 CTR has its own reginfo struct)
1996 */
1997 if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {
1998 return CP_ACCESS_TRAP;
1999 }
2000 return CP_ACCESS_OK;
2001 }
2002
2003 static void define_aarch64_debug_regs(ARMCPU *cpu)
2004 {
2005 /* Define breakpoint and watchpoint registers. These do nothing
2006 * but read as written, for now.
2007 */
2008 int i;
2009
2010 for (i = 0; i < 16; i++) {
2011 ARMCPRegInfo dbgregs[] = {
2012 { .name = "DBGBVR", .state = ARM_CP_STATE_AA64,
2013 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
2014 .access = PL1_RW,
2015 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },
2016 { .name = "DBGBCR", .state = ARM_CP_STATE_AA64,
2017 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
2018 .access = PL1_RW,
2019 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
2020 { .name = "DBGWVR", .state = ARM_CP_STATE_AA64,
2021 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
2022 .access = PL1_RW,
2023 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },
2024 { .name = "DBGWCR", .state = ARM_CP_STATE_AA64,
2025 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
2026 .access = PL1_RW,
2027 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },
2028 REGINFO_SENTINEL
2029 };
2030 define_arm_cp_regs(cpu, dbgregs);
2031 }
2032 }
2033
2034 void register_cp_regs_for_features(ARMCPU *cpu)
2035 {
2036 /* Register all the coprocessor registers based on feature bits */
2037 CPUARMState *env = &cpu->env;
2038 if (arm_feature(env, ARM_FEATURE_M)) {
2039 /* M profile has no coprocessor registers */
2040 return;
2041 }
2042
2043 define_arm_cp_regs(cpu, cp_reginfo);
2044 if (arm_feature(env, ARM_FEATURE_V6)) {
2045 /* The ID registers all have impdef reset values */
2046 ARMCPRegInfo v6_idregs[] = {
2047 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
2048 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2049 .access = PL1_R, .type = ARM_CP_CONST,
2050 .resetvalue = cpu->id_pfr0 },
2051 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
2052 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
2053 .access = PL1_R, .type = ARM_CP_CONST,
2054 .resetvalue = cpu->id_pfr1 },
2055 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
2056 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
2057 .access = PL1_R, .type = ARM_CP_CONST,
2058 .resetvalue = cpu->id_dfr0 },
2059 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
2060 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
2061 .access = PL1_R, .type = ARM_CP_CONST,
2062 .resetvalue = cpu->id_afr0 },
2063 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
2064 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
2065 .access = PL1_R, .type = ARM_CP_CONST,
2066 .resetvalue = cpu->id_mmfr0 },
2067 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
2068 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
2069 .access = PL1_R, .type = ARM_CP_CONST,
2070 .resetvalue = cpu->id_mmfr1 },
2071 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
2072 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
2073 .access = PL1_R, .type = ARM_CP_CONST,
2074 .resetvalue = cpu->id_mmfr2 },
2075 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
2076 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
2077 .access = PL1_R, .type = ARM_CP_CONST,
2078 .resetvalue = cpu->id_mmfr3 },
2079 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
2080 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
2081 .access = PL1_R, .type = ARM_CP_CONST,
2082 .resetvalue = cpu->id_isar0 },
2083 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
2084 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
2085 .access = PL1_R, .type = ARM_CP_CONST,
2086 .resetvalue = cpu->id_isar1 },
2087 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
2088 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2089 .access = PL1_R, .type = ARM_CP_CONST,
2090 .resetvalue = cpu->id_isar2 },
2091 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
2092 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
2093 .access = PL1_R, .type = ARM_CP_CONST,
2094 .resetvalue = cpu->id_isar3 },
2095 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
2096 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
2097 .access = PL1_R, .type = ARM_CP_CONST,
2098 .resetvalue = cpu->id_isar4 },
2099 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
2100 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
2101 .access = PL1_R, .type = ARM_CP_CONST,
2102 .resetvalue = cpu->id_isar5 },
2103 /* 6..7 are as yet unallocated and must RAZ */
2104 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
2105 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
2106 .resetvalue = 0 },
2107 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
2108 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
2109 .resetvalue = 0 },
2110 REGINFO_SENTINEL
2111 };
2112 define_arm_cp_regs(cpu, v6_idregs);
2113 define_arm_cp_regs(cpu, v6_cp_reginfo);
2114 } else {
2115 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
2116 }
2117 if (arm_feature(env, ARM_FEATURE_V6K)) {
2118 define_arm_cp_regs(cpu, v6k_cp_reginfo);
2119 }
2120 if (arm_feature(env, ARM_FEATURE_V7)) {
2121 /* v7 performance monitor control register: same implementor
2122 * field as main ID register, and we implement only the cycle
2123 * count register.
2124 */
2125 #ifndef CONFIG_USER_ONLY
2126 ARMCPRegInfo pmcr = {
2127 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
2128 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
2129 .type = ARM_CP_IO,
2130 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
2131 .accessfn = pmreg_access, .writefn = pmcr_write,
2132 .raw_writefn = raw_write,
2133 };
2134 define_one_arm_cp_reg(cpu, &pmcr);
2135 #endif
2136 ARMCPRegInfo clidr = {
2137 .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
2138 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
2139 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
2140 };
2141 define_one_arm_cp_reg(cpu, &clidr);
2142 define_arm_cp_regs(cpu, v7_cp_reginfo);
2143 } else {
2144 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
2145 }
2146 if (arm_feature(env, ARM_FEATURE_V8)) {
2147 /* AArch64 ID registers, which all have impdef reset values */
2148 ARMCPRegInfo v8_idregs[] = {
2149 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
2150 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
2151 .access = PL1_R, .type = ARM_CP_CONST,
2152 .resetvalue = cpu->id_aa64pfr0 },
2153 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
2154 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
2155 .access = PL1_R, .type = ARM_CP_CONST,
2156 .resetvalue = cpu->id_aa64pfr1},
2157 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
2158 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
2159 .access = PL1_R, .type = ARM_CP_CONST,
2160 /* We mask out the PMUVer field, beacuse we don't currently
2161 * implement the PMU. Not advertising it prevents the guest
2162 * from trying to use it and getting UNDEFs on registers we
2163 * don't implement.
2164 */
2165 .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
2166 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
2167 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
2168 .access = PL1_R, .type = ARM_CP_CONST,
2169 .resetvalue = cpu->id_aa64dfr1 },
2170 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
2171 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
2172 .access = PL1_R, .type = ARM_CP_CONST,
2173 .resetvalue = cpu->id_aa64afr0 },
2174 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
2175 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
2176 .access = PL1_R, .type = ARM_CP_CONST,
2177 .resetvalue = cpu->id_aa64afr1 },
2178 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
2179 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
2180 .access = PL1_R, .type = ARM_CP_CONST,
2181 .resetvalue = cpu->id_aa64isar0 },
2182 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
2183 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
2184 .access = PL1_R, .type = ARM_CP_CONST,
2185 .resetvalue = cpu->id_aa64isar1 },
2186 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
2187 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2188 .access = PL1_R, .type = ARM_CP_CONST,
2189 .resetvalue = cpu->id_aa64mmfr0 },
2190 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
2191 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
2192 .access = PL1_R, .type = ARM_CP_CONST,
2193 .resetvalue = cpu->id_aa64mmfr1 },
2194 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
2195 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
2196 .access = PL1_R, .type = ARM_CP_CONST,
2197 .resetvalue = cpu->mvfr0 },
2198 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
2199 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
2200 .access = PL1_R, .type = ARM_CP_CONST,
2201 .resetvalue = cpu->mvfr1 },
2202 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
2203 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
2204 .access = PL1_R, .type = ARM_CP_CONST,
2205 .resetvalue = cpu->mvfr2 },
2206 REGINFO_SENTINEL
2207 };
2208 define_arm_cp_regs(cpu, v8_idregs);
2209 define_arm_cp_regs(cpu, v8_cp_reginfo);
2210 define_aarch64_debug_regs(cpu);
2211 }
2212 if (arm_feature(env, ARM_FEATURE_MPU)) {
2213 /* These are the MPU registers prior to PMSAv6. Any new
2214 * PMSA core later than the ARM946 will require that we
2215 * implement the PMSAv6 or PMSAv7 registers, which are
2216 * completely different.
2217 */
2218 assert(!arm_feature(env, ARM_FEATURE_V6));
2219 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
2220 } else {
2221 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
2222 }
2223 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
2224 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
2225 }
2226 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
2227 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
2228 }
2229 if (arm_feature(env, ARM_FEATURE_VAPA)) {
2230 define_arm_cp_regs(cpu, vapa_cp_reginfo);
2231 }
2232 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
2233 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
2234 }
2235 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
2236 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
2237 }
2238 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
2239 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
2240 }
2241 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2242 define_arm_cp_regs(cpu, omap_cp_reginfo);
2243 }
2244 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
2245 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
2246 }
2247 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2248 define_arm_cp_regs(cpu, xscale_cp_reginfo);
2249 }
2250 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
2251 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
2252 }
2253 if (arm_feature(env, ARM_FEATURE_LPAE)) {
2254 define_arm_cp_regs(cpu, lpae_cp_reginfo);
2255 }
2256 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
2257 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
2258 * be read-only (ie write causes UNDEF exception).
2259 */
2260 {
2261 ARMCPRegInfo id_cp_reginfo[] = {
2262 /* Note that the MIDR isn't a simple constant register because
2263 * of the TI925 behaviour where writes to another register can
2264 * cause the MIDR value to change.
2265 *
2266 * Unimplemented registers in the c15 0 0 0 space default to
2267 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
2268 * and friends override accordingly.
2269 */
2270 { .name = "MIDR",
2271 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
2272 .access = PL1_R, .resetvalue = cpu->midr,
2273 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
2274 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
2275 .type = ARM_CP_OVERRIDE },
2276 { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64,
2277 .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0,
2278 .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST },
2279 { .name = "CTR",
2280 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
2281 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2282 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
2283 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
2284 .access = PL0_R, .accessfn = ctr_el0_access,
2285 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2286 { .name = "TCMTR",
2287 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
2288 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2289 { .name = "TLBTR",
2290 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
2291 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2292 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
2293 { .name = "DUMMY",
2294 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
2295 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2296 { .name = "DUMMY",
2297 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
2298 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2299 { .name = "DUMMY",
2300 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
2301 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2302 { .name = "DUMMY",
2303 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
2304 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2305 { .name = "DUMMY",
2306 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
2307 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2308 REGINFO_SENTINEL
2309 };
2310 ARMCPRegInfo crn0_wi_reginfo = {
2311 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
2312 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
2313 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
2314 };
2315 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
2316 arm_feature(env, ARM_FEATURE_STRONGARM)) {
2317 ARMCPRegInfo *r;
2318 /* Register the blanket "writes ignored" value first to cover the
2319 * whole space. Then update the specific ID registers to allow write
2320 * access, so that they ignore writes rather than causing them to
2321 * UNDEF.
2322 */
2323 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
2324 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
2325 r->access = PL1_RW;
2326 }
2327 }
2328 define_arm_cp_regs(cpu, id_cp_reginfo);
2329 }
2330
2331 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
2332 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
2333 }
2334
2335 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
2336 ARMCPRegInfo auxcr = {
2337 .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
2338 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
2339 .access = PL1_RW, .type = ARM_CP_CONST,
2340 .resetvalue = cpu->reset_auxcr
2341 };
2342 define_one_arm_cp_reg(cpu, &auxcr);
2343 }
2344
2345 if (arm_feature(env, ARM_FEATURE_CBAR)) {
2346 ARMCPRegInfo cbar = {
2347 .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2348 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
2349 .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
2350 };
2351 define_one_arm_cp_reg(cpu, &cbar);
2352 }
2353
2354 /* Generic registers whose values depend on the implementation */
2355 {
2356 ARMCPRegInfo sctlr = {
2357 .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
2358 .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2359 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
2360 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
2361 .raw_writefn = raw_write,
2362 };
2363 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2364 /* Normally we would always end the TB on an SCTLR write, but Linux
2365 * arch/arm/mach-pxa/sleep.S expects two instructions following
2366 * an MMU enable to execute from cache. Imitate this behaviour.
2367 */
2368 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
2369 }
2370 define_one_arm_cp_reg(cpu, &sctlr);
2371 }
2372 }
2373
2374 ARMCPU *cpu_arm_init(const char *cpu_model)
2375 {
2376 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
2377 }
2378
2379 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
2380 {
2381 CPUState *cs = CPU(cpu);
2382 CPUARMState *env = &cpu->env;
2383
2384 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2385 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
2386 aarch64_fpu_gdb_set_reg,
2387 34, "aarch64-fpu.xml", 0);
2388 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
2389 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2390 51, "arm-neon.xml", 0);
2391 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
2392 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2393 35, "arm-vfp3.xml", 0);
2394 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
2395 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2396 19, "arm-vfp.xml", 0);
2397 }
2398 }
2399
2400 /* Sort alphabetically by type name, except for "any". */
2401 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
2402 {
2403 ObjectClass *class_a = (ObjectClass *)a;
2404 ObjectClass *class_b = (ObjectClass *)b;
2405 const char *name_a, *name_b;
2406
2407 name_a = object_class_get_name(class_a);
2408 name_b = object_class_get_name(class_b);
2409 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
2410 return 1;
2411 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
2412 return -1;
2413 } else {
2414 return strcmp(name_a, name_b);
2415 }
2416 }
2417
2418 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
2419 {
2420 ObjectClass *oc = data;
2421 CPUListState *s = user_data;
2422 const char *typename;
2423 char *name;
2424
2425 typename = object_class_get_name(oc);
2426 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
2427 (*s->cpu_fprintf)(s->file, " %s\n",
2428 name);
2429 g_free(name);
2430 }
2431
2432 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
2433 {
2434 CPUListState s = {
2435 .file = f,
2436 .cpu_fprintf = cpu_fprintf,
2437 };
2438 GSList *list;
2439
2440 list = object_class_get_list(TYPE_ARM_CPU, false);
2441 list = g_slist_sort(list, arm_cpu_list_compare);
2442 (*cpu_fprintf)(f, "Available CPUs:\n");
2443 g_slist_foreach(list, arm_cpu_list_entry, &s);
2444 g_slist_free(list);
2445 #ifdef CONFIG_KVM
2446 /* The 'host' CPU type is dynamically registered only if KVM is
2447 * enabled, so we have to special-case it here:
2448 */
2449 (*cpu_fprintf)(f, " host (only available in KVM mode)\n");
2450 #endif
2451 }
2452
2453 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
2454 {
2455 ObjectClass *oc = data;
2456 CpuDefinitionInfoList **cpu_list = user_data;
2457 CpuDefinitionInfoList *entry;
2458 CpuDefinitionInfo *info;
2459 const char *typename;
2460
2461 typename = object_class_get_name(oc);
2462 info = g_malloc0(sizeof(*info));
2463 info->name = g_strndup(typename,
2464 strlen(typename) - strlen("-" TYPE_ARM_CPU));
2465
2466 entry = g_malloc0(sizeof(*entry));
2467 entry->value = info;
2468 entry->next = *cpu_list;
2469 *cpu_list = entry;
2470 }
2471
2472 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2473 {
2474 CpuDefinitionInfoList *cpu_list = NULL;
2475 GSList *list;
2476
2477 list = object_class_get_list(TYPE_ARM_CPU, false);
2478 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
2479 g_slist_free(list);
2480
2481 return cpu_list;
2482 }
2483
2484 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2485 void *opaque, int state,
2486 int crm, int opc1, int opc2)
2487 {
2488 /* Private utility function for define_one_arm_cp_reg_with_opaque():
2489 * add a single reginfo struct to the hash table.
2490 */
2491 uint32_t *key = g_new(uint32_t, 1);
2492 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2493 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2494 if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2495 /* The AArch32 view of a shared register sees the lower 32 bits
2496 * of a 64 bit backing field. It is not migratable as the AArch64
2497 * view handles that. AArch64 also handles reset.
2498 * We assume it is a cp15 register.
2499 */
2500 r2->cp = 15;
2501 r2->type |= ARM_CP_NO_MIGRATE;
2502 r2->resetfn = arm_cp_reset_ignore;
2503 #ifdef HOST_WORDS_BIGENDIAN
2504 if (r2->fieldoffset) {
2505 r2->fieldoffset += sizeof(uint32_t);
2506 }
2507 #endif
2508 }
2509 if (state == ARM_CP_STATE_AA64) {
2510 /* To allow abbreviation of ARMCPRegInfo
2511 * definitions, we treat cp == 0 as equivalent to
2512 * the value for "standard guest-visible sysreg".
2513 */
2514 if (r->cp == 0) {
2515 r2->cp = CP_REG_ARM64_SYSREG_CP;
2516 }
2517 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2518 r2->opc0, opc1, opc2);
2519 } else {
2520 *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2521 }
2522 if (opaque) {
2523 r2->opaque = opaque;
2524 }
2525 /* reginfo passed to helpers is correct for the actual access,
2526 * and is never ARM_CP_STATE_BOTH:
2527 */
2528 r2->state = state;
2529 /* Make sure reginfo passed to helpers for wildcarded regs
2530 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2531 */
2532 r2->crm = crm;
2533 r2->opc1 = opc1;
2534 r2->opc2 = opc2;
2535 /* By convention, for wildcarded registers only the first
2536 * entry is used for migration; the others are marked as
2537 * NO_MIGRATE so we don't try to transfer the register
2538 * multiple times. Special registers (ie NOP/WFI) are
2539 * never migratable.
2540 */
2541 if ((r->type & ARM_CP_SPECIAL) ||
2542 ((r->crm == CP_ANY) && crm != 0) ||
2543 ((r->opc1 == CP_ANY) && opc1 != 0) ||
2544 ((r->opc2 == CP_ANY) && opc2 != 0)) {
2545 r2->type |= ARM_CP_NO_MIGRATE;
2546 }
2547
2548 /* Overriding of an existing definition must be explicitly
2549 * requested.
2550 */
2551 if (!(r->type & ARM_CP_OVERRIDE)) {
2552 ARMCPRegInfo *oldreg;
2553 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2554 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2555 fprintf(stderr, "Register redefined: cp=%d %d bit "
2556 "crn=%d crm=%d opc1=%d opc2=%d, "
2557 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2558 r2->crn, r2->crm, r2->opc1, r2->opc2,
2559 oldreg->name, r2->name);
2560 g_assert_not_reached();
2561 }
2562 }
2563 g_hash_table_insert(cpu->cp_regs, key, r2);
2564 }
2565
2566
2567 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2568 const ARMCPRegInfo *r, void *opaque)
2569 {
2570 /* Define implementations of coprocessor registers.
2571 * We store these in a hashtable because typically
2572 * there are less than 150 registers in a space which
2573 * is 16*16*16*8*8 = 262144 in size.
2574 * Wildcarding is supported for the crm, opc1 and opc2 fields.
2575 * If a register is defined twice then the second definition is
2576 * used, so this can be used to define some generic registers and
2577 * then override them with implementation specific variations.
2578 * At least one of the original and the second definition should
2579 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2580 * against accidental use.
2581 *
2582 * The state field defines whether the register is to be
2583 * visible in the AArch32 or AArch64 execution state. If the
2584 * state is set to ARM_CP_STATE_BOTH then we synthesise a
2585 * reginfo structure for the AArch32 view, which sees the lower
2586 * 32 bits of the 64 bit register.
2587 *
2588 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2589 * be wildcarded. AArch64 registers are always considered to be 64
2590 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2591 * the register, if any.
2592 */
2593 int crm, opc1, opc2, state;
2594 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2595 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2596 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2597 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2598 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2599 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2600 /* 64 bit registers have only CRm and Opc1 fields */
2601 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2602 /* op0 only exists in the AArch64 encodings */
2603 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2604 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2605 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2606 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2607 * encodes a minimum access level for the register. We roll this
2608 * runtime check into our general permission check code, so check
2609 * here that the reginfo's specified permissions are strict enough
2610 * to encompass the generic architectural permission check.
2611 */
2612 if (r->state != ARM_CP_STATE_AA32) {
2613 int mask = 0;
2614 switch (r->opc1) {
2615 case 0: case 1: case 2:
2616 /* min_EL EL1 */
2617 mask = PL1_RW;
2618 break;
2619 case 3:
2620 /* min_EL EL0 */
2621 mask = PL0_RW;
2622 break;
2623 case 4:
2624 /* min_EL EL2 */
2625 mask = PL2_RW;
2626 break;
2627 case 5:
2628 /* unallocated encoding, so not possible */
2629 assert(false);
2630 break;
2631 case 6:
2632 /* min_EL EL3 */
2633 mask = PL3_RW;
2634 break;
2635 case 7:
2636 /* min_EL EL1, secure mode only (we don't check the latter) */
2637 mask = PL1_RW;
2638 break;
2639 default:
2640 /* broken reginfo with out-of-range opc1 */
2641 assert(false);
2642 break;
2643 }
2644 /* assert our permissions are not too lax (stricter is fine) */
2645 assert((r->access & ~mask) == 0);
2646 }
2647
2648 /* Check that the register definition has enough info to handle
2649 * reads and writes if they are permitted.
2650 */
2651 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
2652 if (r->access & PL3_R) {
2653 assert(r->fieldoffset || r->readfn);
2654 }
2655 if (r->access & PL3_W) {
2656 assert(r->fieldoffset || r->writefn);
2657 }
2658 }
2659 /* Bad type field probably means missing sentinel at end of reg list */
2660 assert(cptype_valid(r->type));
2661 for (crm = crmmin; crm <= crmmax; crm++) {
2662 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
2663 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
2664 for (state = ARM_CP_STATE_AA32;
2665 state <= ARM_CP_STATE_AA64; state++) {
2666 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
2667 continue;
2668 }
2669 add_cpreg_to_hashtable(cpu, r, opaque, state,
2670 crm, opc1, opc2);
2671 }
2672 }
2673 }
2674 }
2675 }
2676
2677 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2678 const ARMCPRegInfo *regs, void *opaque)
2679 {
2680 /* Define a whole list of registers */
2681 const ARMCPRegInfo *r;
2682 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
2683 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
2684 }
2685 }
2686
2687 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
2688 {
2689 return g_hash_table_lookup(cpregs, &encoded_cp);
2690 }
2691
2692 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2693 uint64_t value)
2694 {
2695 /* Helper coprocessor write function for write-ignore registers */
2696 }
2697
2698 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
2699 {
2700 /* Helper coprocessor write function for read-as-zero registers */
2701 return 0;
2702 }
2703
2704 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
2705 {
2706 /* Helper coprocessor reset function for do-nothing-on-reset registers */
2707 }
2708
2709 static int bad_mode_switch(CPUARMState *env, int mode)
2710 {
2711 /* Return true if it is not valid for us to switch to
2712 * this CPU mode (ie all the UNPREDICTABLE cases in
2713 * the ARM ARM CPSRWriteByInstr pseudocode).
2714 */
2715 switch (mode) {
2716 case ARM_CPU_MODE_USR:
2717 case ARM_CPU_MODE_SYS:
2718 case ARM_CPU_MODE_SVC:
2719 case ARM_CPU_MODE_ABT:
2720 case ARM_CPU_MODE_UND:
2721 case ARM_CPU_MODE_IRQ:
2722 case ARM_CPU_MODE_FIQ:
2723 return 0;
2724 default:
2725 return 1;
2726 }
2727 }
2728
2729 uint32_t cpsr_read(CPUARMState *env)
2730 {
2731 int ZF;
2732 ZF = (env->ZF == 0);
2733 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2734 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
2735 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
2736 | ((env->condexec_bits & 0xfc) << 8)
2737 | (env->GE << 16) | (env->daif & CPSR_AIF);
2738 }
2739
2740 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
2741 {
2742 if (mask & CPSR_NZCV) {
2743 env->ZF = (~val) & CPSR_Z;
2744 env->NF = val;
2745 env->CF = (val >> 29) & 1;
2746 env->VF = (val << 3) & 0x80000000;
2747 }
2748 if (mask & CPSR_Q)
2749 env->QF = ((val & CPSR_Q) != 0);
2750 if (mask & CPSR_T)
2751 env->thumb = ((val & CPSR_T) != 0);
2752 if (mask & CPSR_IT_0_1) {
2753 env->condexec_bits &= ~3;
2754 env->condexec_bits |= (val >> 25) & 3;
2755 }
2756 if (mask & CPSR_IT_2_7) {
2757 env->condexec_bits &= 3;
2758 env->condexec_bits |= (val >> 8) & 0xfc;
2759 }
2760 if (mask & CPSR_GE) {
2761 env->GE = (val >> 16) & 0xf;
2762 }
2763
2764 env->daif &= ~(CPSR_AIF & mask);
2765 env->daif |= val & CPSR_AIF & mask;
2766
2767 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
2768 if (bad_mode_switch(env, val & CPSR_M)) {
2769 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2770 * We choose to ignore the attempt and leave the CPSR M field
2771 * untouched.
2772 */
2773 mask &= ~CPSR_M;
2774 } else {
2775 switch_mode(env, val & CPSR_M);
2776 }
2777 }
2778 mask &= ~CACHED_CPSR_BITS;
2779 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
2780 }
2781
2782 /* Sign/zero extend */
2783 uint32_t HELPER(sxtb16)(uint32_t x)
2784 {
2785 uint32_t res;
2786 res = (uint16_t)(int8_t)x;
2787 res |= (uint32_t)(int8_t)(x >> 16) << 16;
2788 return res;
2789 }
2790
2791 uint32_t HELPER(uxtb16)(uint32_t x)
2792 {
2793 uint32_t res;
2794 res = (uint16_t)(uint8_t)x;
2795 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
2796 return res;
2797 }
2798
2799 uint32_t HELPER(clz)(uint32_t x)
2800 {
2801 return clz32(x);
2802 }
2803
2804 int32_t HELPER(sdiv)(int32_t num, int32_t den)
2805 {
2806 if (den == 0)
2807 return 0;
2808 if (num == INT_MIN && den == -1)
2809 return INT_MIN;
2810 return num / den;
2811 }
2812
2813 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
2814 {
2815 if (den == 0)
2816 return 0;
2817 return num / den;
2818 }
2819
2820 uint32_t HELPER(rbit)(uint32_t x)
2821 {
2822 x = ((x & 0xff000000) >> 24)
2823 | ((x & 0x00ff0000) >> 8)
2824 | ((x & 0x0000ff00) << 8)
2825 | ((x & 0x000000ff) << 24);
2826 x = ((x & 0xf0f0f0f0) >> 4)
2827 | ((x & 0x0f0f0f0f) << 4);
2828 x = ((x & 0x88888888) >> 3)
2829 | ((x & 0x44444444) >> 1)
2830 | ((x & 0x22222222) << 1)
2831 | ((x & 0x11111111) << 3);
2832 return x;
2833 }
2834
2835 #if defined(CONFIG_USER_ONLY)
2836
2837 void arm_cpu_do_interrupt(CPUState *cs)
2838 {
2839 cs->exception_index = -1;
2840 }
2841
2842 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
2843 int mmu_idx)
2844 {
2845 ARMCPU *cpu = ARM_CPU(cs);
2846 CPUARMState *env = &cpu->env;
2847
2848 env->exception.vaddress = address;
2849 if (rw == 2) {
2850 cs->exception_index = EXCP_PREFETCH_ABORT;
2851 } else {
2852 cs->exception_index = EXCP_DATA_ABORT;
2853 }
2854 return 1;
2855 }
2856
2857 /* These should probably raise undefined insn exceptions. */
2858 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
2859 {
2860 ARMCPU *cpu = arm_env_get_cpu(env);
2861
2862 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
2863 }
2864
2865 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
2866 {
2867 ARMCPU *cpu = arm_env_get_cpu(env);
2868
2869 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
2870 return 0;
2871 }
2872
2873 void switch_mode(CPUARMState *env, int mode)
2874 {
2875 ARMCPU *cpu = arm_env_get_cpu(env);
2876
2877 if (mode != ARM_CPU_MODE_USR) {
2878 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
2879 }
2880 }
2881
2882 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
2883 {
2884 ARMCPU *cpu = arm_env_get_cpu(env);
2885
2886 cpu_abort(CPU(cpu), "banked r13 write\n");
2887 }
2888
2889 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
2890 {
2891 ARMCPU *cpu = arm_env_get_cpu(env);
2892
2893 cpu_abort(CPU(cpu), "banked r13 read\n");
2894 return 0;
2895 }
2896
2897 #else
2898
2899 /* Map CPU modes onto saved register banks. */
2900 int bank_number(int mode)
2901 {
2902 switch (mode) {
2903 case ARM_CPU_MODE_USR:
2904 case ARM_CPU_MODE_SYS:
2905 return 0;
2906 case ARM_CPU_MODE_SVC:
2907 return 1;
2908 case ARM_CPU_MODE_ABT:
2909 return 2;
2910 case ARM_CPU_MODE_UND:
2911 return 3;
2912 case ARM_CPU_MODE_IRQ:
2913 return 4;
2914 case ARM_CPU_MODE_FIQ:
2915 return 5;
2916 }
2917 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
2918 }
2919
2920 void switch_mode(CPUARMState *env, int mode)
2921 {
2922 int old_mode;
2923 int i;
2924
2925 old_mode = env->uncached_cpsr & CPSR_M;
2926 if (mode == old_mode)
2927 return;
2928
2929 if (old_mode == ARM_CPU_MODE_FIQ) {
2930 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
2931 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
2932 } else if (mode == ARM_CPU_MODE_FIQ) {
2933 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
2934 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
2935 }
2936
2937 i = bank_number(old_mode);
2938 env->banked_r13[i] = env->regs[13];
2939 env->banked_r14[i] = env->regs[14];
2940 env->banked_spsr[i] = env->spsr;
2941
2942 i = bank_number(mode);
2943 env->regs[13] = env->banked_r13[i];
2944 env->regs[14] = env->banked_r14[i];
2945 env->spsr = env->banked_spsr[i];
2946 }
2947
2948 static void v7m_push(CPUARMState *env, uint32_t val)
2949 {
2950 CPUState *cs = CPU(arm_env_get_cpu(env));
2951
2952 env->regs[13] -= 4;
2953 stl_phys(cs->as, env->regs[13], val);
2954 }
2955
2956 static uint32_t v7m_pop(CPUARMState *env)
2957 {
2958 CPUState *cs = CPU(arm_env_get_cpu(env));
2959 uint32_t val;
2960
2961 val = ldl_phys(cs->as, env->regs[13]);
2962 env->regs[13] += 4;
2963 return val;
2964 }
2965
2966 /* Switch to V7M main or process stack pointer. */
2967 static void switch_v7m_sp(CPUARMState *env, int process)
2968 {
2969 uint32_t tmp;
2970 if (env->v7m.current_sp != process) {
2971 tmp = env->v7m.other_sp;
2972 env->v7m.other_sp = env->regs[13];
2973 env->regs[13] = tmp;
2974 env->v7m.current_sp = process;
2975 }
2976 }
2977
2978 static void do_v7m_exception_exit(CPUARMState *env)
2979 {
2980 uint32_t type;
2981 uint32_t xpsr;
2982
2983 type = env->regs[15];
2984 if (env->v7m.exception != 0)
2985 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
2986
2987 /* Switch to the target stack. */
2988 switch_v7m_sp(env, (type & 4) != 0);
2989 /* Pop registers. */
2990 env->regs[0] = v7m_pop(env);
2991 env->regs[1] = v7m_pop(env);
2992 env->regs[2] = v7m_pop(env);
2993 env->regs[3] = v7m_pop(env);
2994 env->regs[12] = v7m_pop(env);
2995 env->regs[14] = v7m_pop(env);
2996 env->regs[15] = v7m_pop(env);
2997 xpsr = v7m_pop(env);
2998 xpsr_write(env, xpsr, 0xfffffdff);
2999 /* Undo stack alignment. */
3000 if (xpsr & 0x200)
3001 env->regs[13] |= 4;
3002 /* ??? The exception return type specifies Thread/Handler mode. However
3003 this is also implied by the xPSR value. Not sure what to do
3004 if there is a mismatch. */
3005 /* ??? Likewise for mismatches between the CONTROL register and the stack
3006 pointer. */
3007 }
3008
3009 void arm_v7m_cpu_do_interrupt(CPUState *cs)
3010 {
3011 ARMCPU *cpu = ARM_CPU(cs);
3012 CPUARMState *env = &cpu->env;
3013 uint32_t xpsr = xpsr_read(env);
3014 uint32_t lr;
3015 uint32_t addr;
3016
3017 arm_log_exception(cs->exception_index);
3018
3019 lr = 0xfffffff1;
3020 if (env->v7m.current_sp)
3021 lr |= 4;
3022 if (env->v7m.exception == 0)
3023 lr |= 8;
3024
3025 /* For exceptions we just mark as pending on the NVIC, and let that
3026 handle it. */
3027 /* TODO: Need to escalate if the current priority is higher than the
3028 one we're raising. */
3029 switch (cs->exception_index) {
3030 case EXCP_UDEF:
3031 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
3032 return;
3033 case EXCP_SWI:
3034 /* The PC already points to the next instruction. */
3035 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
3036 return;
3037 case EXCP_PREFETCH_ABORT:
3038 case EXCP_DATA_ABORT:
3039 /* TODO: if we implemented the MPU registers, this is where we
3040 * should set the MMFAR, etc from exception.fsr and exception.vaddress.
3041 */
3042 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
3043 return;
3044 case EXCP_BKPT:
3045 if (semihosting_enabled) {
3046 int nr;
3047 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3048 if (nr == 0xab) {
3049 env->regs[15] += 2;
3050 env->regs[0] = do_arm_semihosting(env);
3051 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3052 return;
3053 }
3054 }
3055 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
3056 return;
3057 case EXCP_IRQ:
3058 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
3059 break;
3060 case EXCP_EXCEPTION_EXIT:
3061 do_v7m_exception_exit(env);
3062 return;
3063 default:
3064 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3065 return; /* Never happens. Keep compiler happy. */
3066 }
3067
3068 /* Align stack pointer. */
3069 /* ??? Should only do this if Configuration Control Register
3070 STACKALIGN bit is set. */
3071 if (env->regs[13] & 4) {
3072 env->regs[13] -= 4;
3073 xpsr |= 0x200;
3074 }
3075 /* Switch to the handler mode. */
3076 v7m_push(env, xpsr);
3077 v7m_push(env, env->regs[15]);
3078 v7m_push(env, env->regs[14]);
3079 v7m_push(env, env->regs[12]);
3080 v7m_push(env, env->regs[3]);
3081 v7m_push(env, env->regs[2]);
3082 v7m_push(env, env->regs[1]);
3083 v7m_push(env, env->regs[0]);
3084 switch_v7m_sp(env, 0);
3085 /* Clear IT bits */
3086 env->condexec_bits = 0;
3087 env->regs[14] = lr;
3088 addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
3089 env->regs[15] = addr & 0xfffffffe;
3090 env->thumb = addr & 1;
3091 }
3092
3093 /* Handle a CPU exception. */
3094 void arm_cpu_do_interrupt(CPUState *cs)
3095 {
3096 ARMCPU *cpu = ARM_CPU(cs);
3097 CPUARMState *env = &cpu->env;
3098 uint32_t addr;
3099 uint32_t mask;
3100 int new_mode;
3101 uint32_t offset;
3102
3103 assert(!IS_M(env));
3104
3105 arm_log_exception(cs->exception_index);
3106
3107 /* TODO: Vectored interrupt controller. */
3108 switch (cs->exception_index) {
3109 case EXCP_UDEF:
3110 new_mode = ARM_CPU_MODE_UND;
3111 addr = 0x04;
3112 mask = CPSR_I;
3113 if (env->thumb)
3114 offset = 2;
3115 else
3116 offset = 4;
3117 break;
3118 case EXCP_SWI:
3119 if (semihosting_enabled) {
3120 /* Check for semihosting interrupt. */
3121 if (env->thumb) {
3122 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
3123 & 0xff;
3124 } else {
3125 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
3126 & 0xffffff;
3127 }
3128 /* Only intercept calls from privileged modes, to provide some
3129 semblance of security. */
3130 if (((mask == 0x123456 && !env->thumb)
3131 || (mask == 0xab && env->thumb))
3132 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3133 env->regs[0] = do_arm_semihosting(env);
3134 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3135 return;
3136 }
3137 }
3138 new_mode = ARM_CPU_MODE_SVC;
3139 addr = 0x08;
3140 mask = CPSR_I;
3141 /* The PC already points to the next instruction. */
3142 offset = 0;
3143 break;
3144 case EXCP_BKPT:
3145 /* See if this is a semihosting syscall. */
3146 if (env->thumb && semihosting_enabled) {
3147 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3148 if (mask == 0xab
3149 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3150 env->regs[15] += 2;
3151 env->regs[0] = do_arm_semihosting(env);
3152 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3153 return;
3154 }
3155 }
3156 env->exception.fsr = 2;
3157 /* Fall through to prefetch abort. */
3158 case EXCP_PREFETCH_ABORT:
3159 env->cp15.ifsr_el2 = env->exception.fsr;
3160 env->cp15.far_el1 = deposit64(env->cp15.far_el1, 32, 32,
3161 env->exception.vaddress);
3162 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
3163 env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress);
3164 new_mode = ARM_CPU_MODE_ABT;
3165 addr = 0x0c;
3166 mask = CPSR_A | CPSR_I;
3167 offset = 4;
3168 break;
3169 case EXCP_DATA_ABORT:
3170 env->cp15.esr_el1 = env->exception.fsr;
3171 env->cp15.far_el1 = deposit64(env->cp15.far_el1, 0, 32,
3172 env->exception.vaddress);
3173 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
3174 (uint32_t)env->cp15.esr_el1,
3175 (uint32_t)env->exception.vaddress);
3176 new_mode = ARM_CPU_MODE_ABT;
3177 addr = 0x10;
3178 mask = CPSR_A | CPSR_I;
3179 offset = 8;
3180 break;
3181 case EXCP_IRQ:
3182 new_mode = ARM_CPU_MODE_IRQ;
3183 addr = 0x18;
3184 /* Disable IRQ and imprecise data aborts. */
3185 mask = CPSR_A | CPSR_I;
3186 offset = 4;
3187 break;
3188 case EXCP_FIQ:
3189 new_mode = ARM_CPU_MODE_FIQ;
3190 addr = 0x1c;
3191 /* Disable FIQ, IRQ and imprecise data aborts. */
3192 mask = CPSR_A | CPSR_I | CPSR_F;
3193 offset = 4;
3194 break;
3195 default:
3196 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3197 return; /* Never happens. Keep compiler happy. */
3198 }
3199 /* High vectors. */
3200 if (env->cp15.c1_sys & SCTLR_V) {
3201 /* when enabled, base address cannot be remapped. */
3202 addr += 0xffff0000;
3203 } else {
3204 /* ARM v7 architectures provide a vector base address register to remap
3205 * the interrupt vector table.
3206 * This register is only followed in non-monitor mode, and has a secure
3207 * and un-secure copy. Since the cpu is always in a un-secure operation
3208 * and is never in monitor mode this feature is always active.
3209 * Note: only bits 31:5 are valid.
3210 */
3211 addr += env->cp15.c12_vbar;
3212 }
3213 switch_mode (env, new_mode);
3214 env->spsr = cpsr_read(env);
3215 /* Clear IT bits. */
3216 env->condexec_bits = 0;
3217 /* Switch to the new mode, and to the correct instruction set. */
3218 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
3219 env->daif |= mask;
3220 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
3221 * and we should just guard the thumb mode on V4 */
3222 if (arm_feature(env, ARM_FEATURE_V4T)) {
3223 env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0;
3224 }
3225 env->regs[14] = env->regs[15] + offset;
3226 env->regs[15] = addr;
3227 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
3228 }
3229
3230 /* Check section/page access permissions.
3231 Returns the page protection flags, or zero if the access is not
3232 permitted. */
3233 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
3234 int access_type, int is_user)
3235 {
3236 int prot_ro;
3237
3238 if (domain_prot == 3) {
3239 return PAGE_READ | PAGE_WRITE;
3240 }
3241
3242 if (access_type == 1)
3243 prot_ro = 0;
3244 else
3245 prot_ro = PAGE_READ;
3246
3247 switch (ap) {
3248 case 0:
3249 if (arm_feature(env, ARM_FEATURE_V7)) {
3250 return 0;
3251 }
3252 if (access_type == 1)
3253 return 0;
3254 switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) {
3255 case SCTLR_S:
3256 return is_user ? 0 : PAGE_READ;
3257 case SCTLR_R:
3258 return PAGE_READ;
3259 default:
3260 return 0;
3261 }
3262 case 1:
3263 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
3264 case 2:
3265 if (is_user)
3266 return prot_ro;
3267 else
3268 return PAGE_READ | PAGE_WRITE;
3269 case 3:
3270 return PAGE_READ | PAGE_WRITE;
3271 case 4: /* Reserved. */
3272 return 0;
3273 case 5:
3274 return is_user ? 0 : prot_ro;
3275 case 6:
3276 return prot_ro;
3277 case 7:
3278 if (!arm_feature (env, ARM_FEATURE_V6K))
3279 return 0;
3280 return prot_ro;
3281 default:
3282 abort();
3283 }
3284 }
3285
3286 static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
3287 {
3288 uint32_t table;
3289
3290 if (address & env->cp15.c2_mask)
3291 table = env->cp15.ttbr1_el1 & 0xffffc000;
3292 else
3293 table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask;
3294
3295 table |= (address >> 18) & 0x3ffc;
3296 return table;
3297 }
3298
3299 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
3300 int is_user, hwaddr *phys_ptr,
3301 int *prot, target_ulong *page_size)
3302 {
3303 CPUState *cs = CPU(arm_env_get_cpu(env));
3304 int code;
3305 uint32_t table;
3306 uint32_t desc;
3307 int type;
3308 int ap;
3309 int domain;
3310 int domain_prot;
3311 hwaddr phys_addr;
3312
3313 /* Pagetable walk. */
3314 /* Lookup l1 descriptor. */
3315 table = get_level1_table_address(env, address);
3316 desc = ldl_phys(cs->as, table);
3317 type = (desc & 3);
3318 domain = (desc >> 5) & 0x0f;
3319 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3320 if (type == 0) {
3321 /* Section translation fault. */
3322 code = 5;
3323 goto do_fault;
3324 }
3325 if (domain_prot == 0 || domain_prot == 2) {
3326 if (type == 2)
3327 code = 9; /* Section domain fault. */
3328 else
3329 code = 11; /* Page domain fault. */
3330 goto do_fault;
3331 }
3332 if (type == 2) {
3333 /* 1Mb section. */
3334 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3335 ap = (desc >> 10) & 3;
3336 code = 13;
3337 *page_size = 1024 * 1024;
3338 } else {
3339 /* Lookup l2 entry. */
3340 if (type == 1) {
3341 /* Coarse pagetable. */
3342 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3343 } else {
3344 /* Fine pagetable. */
3345 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
3346 }
3347 desc = ldl_phys(cs->as, table);
3348 switch (desc & 3) {
3349 case 0: /* Page translation fault. */
3350 code = 7;
3351 goto do_fault;
3352 case 1: /* 64k page. */
3353 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3354 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
3355 *page_size = 0x10000;
3356 break;
3357 case 2: /* 4k page. */
3358 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3359 ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
3360 *page_size = 0x1000;
3361 break;
3362 case 3: /* 1k page. */
3363 if (type == 1) {
3364 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3365 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3366 } else {
3367 /* Page translation fault. */
3368 code = 7;
3369 goto do_fault;
3370 }
3371 } else {
3372 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
3373 }
3374 ap = (desc >> 4) & 3;
3375 *page_size = 0x400;
3376 break;
3377 default:
3378 /* Never happens, but compiler isn't smart enough to tell. */
3379 abort();
3380 }
3381 code = 15;
3382 }
3383 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3384 if (!*prot) {
3385 /* Access permission fault. */
3386 goto do_fault;
3387 }
3388 *prot |= PAGE_EXEC;
3389 *phys_ptr = phys_addr;
3390 return 0;
3391 do_fault:
3392 return code | (domain << 4);
3393 }
3394
3395 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
3396 int is_user, hwaddr *phys_ptr,
3397 int *prot, target_ulong *page_size)
3398 {
3399 CPUState *cs = CPU(arm_env_get_cpu(env));
3400 int code;
3401 uint32_t table;
3402 uint32_t desc;
3403 uint32_t xn;
3404 uint32_t pxn = 0;
3405 int type;
3406 int ap;
3407 int domain = 0;
3408 int domain_prot;
3409 hwaddr phys_addr;
3410
3411 /* Pagetable walk. */
3412 /* Lookup l1 descriptor. */
3413 table = get_level1_table_address(env, address);
3414 desc = ldl_phys(cs->as, table);
3415 type = (desc & 3);
3416 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
3417 /* Section translation fault, or attempt to use the encoding
3418 * which is Reserved on implementations without PXN.
3419 */
3420 code = 5;
3421 goto do_fault;
3422 }
3423 if ((type == 1) || !(desc & (1 << 18))) {
3424 /* Page or Section. */
3425 domain = (desc >> 5) & 0x0f;
3426 }
3427 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3428 if (domain_prot == 0 || domain_prot == 2) {
3429 if (type != 1) {
3430 code = 9; /* Section domain fault. */
3431 } else {
3432 code = 11; /* Page domain fault. */
3433 }
3434 goto do_fault;
3435 }
3436 if (type != 1) {
3437 if (desc & (1 << 18)) {
3438 /* Supersection. */
3439 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
3440 *page_size = 0x1000000;
3441 } else {
3442 /* Section. */
3443 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3444 *page_size = 0x100000;
3445 }
3446 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
3447 xn = desc & (1 << 4);
3448 pxn = desc & 1;
3449 code = 13;
3450 } else {
3451 if (arm_feature(env, ARM_FEATURE_PXN)) {
3452 pxn = (desc >> 2) & 1;
3453 }
3454 /* Lookup l2 entry. */
3455 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3456 desc = ldl_phys(cs->as, table);
3457 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
3458 switch (desc & 3) {
3459 case 0: /* Page translation fault. */
3460 code = 7;
3461 goto do_fault;
3462 case 1: /* 64k page. */
3463 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3464 xn = desc & (1 << 15);
3465 *page_size = 0x10000;
3466 break;
3467 case 2: case 3: /* 4k page. */
3468 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3469 xn = desc & 1;
3470 *page_size = 0x1000;
3471 break;
3472 default:
3473 /* Never happens, but compiler isn't smart enough to tell. */
3474 abort();
3475 }
3476 code = 15;
3477 }
3478 if (domain_prot == 3) {
3479 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3480 } else {
3481 if (pxn && !is_user) {
3482 xn = 1;
3483 }
3484 if (xn && access_type == 2)
3485 goto do_fault;
3486
3487 /* The simplified model uses AP[0] as an access control bit. */
3488 if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) {
3489 /* Access flag fault. */
3490 code = (code == 15) ? 6 : 3;
3491 goto do_fault;
3492 }
3493 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3494 if (!*prot) {
3495 /* Access permission fault. */
3496 goto do_fault;
3497 }
3498 if (!xn) {
3499 *prot |= PAGE_EXEC;
3500 }
3501 }
3502 *phys_ptr = phys_addr;
3503 return 0;
3504 do_fault:
3505 return code | (domain << 4);
3506 }
3507
3508 /* Fault type for long-descriptor MMU fault reporting; this corresponds
3509 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3510 */
3511 typedef enum {
3512 translation_fault = 1,
3513 access_fault = 2,
3514 permission_fault = 3,
3515 } MMUFaultType;
3516
3517 static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
3518 int access_type, int is_user,
3519 hwaddr *phys_ptr, int *prot,
3520 target_ulong *page_size_ptr)
3521 {
3522 CPUState *cs = CPU(arm_env_get_cpu(env));
3523 /* Read an LPAE long-descriptor translation table. */
3524 MMUFaultType fault_type = translation_fault;
3525 uint32_t level = 1;
3526 uint32_t epd;
3527 int32_t tsz;
3528 uint32_t tg;
3529 uint64_t ttbr;
3530 int ttbr_select;
3531 hwaddr descaddr, descmask;
3532 uint32_t tableattrs;
3533 target_ulong page_size;
3534 uint32_t attrs;
3535 int32_t granule_sz = 9;
3536 int32_t va_size = 32;
3537 int32_t tbi = 0;
3538
3539 if (arm_el_is_aa64(env, 1)) {
3540 va_size = 64;
3541 if (extract64(address, 55, 1))
3542 tbi = extract64(env->cp15.c2_control, 38, 1);
3543 else
3544 tbi = extract64(env->cp15.c2_control, 37, 1);
3545 tbi *= 8;
3546 }
3547
3548 /* Determine whether this address is in the region controlled by
3549 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3550 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3551 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3552 */
3553 uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6);
3554 if (arm_el_is_aa64(env, 1)) {
3555 t0sz = MIN(t0sz, 39);
3556 t0sz = MAX(t0sz, 16);
3557 }
3558 uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6);
3559 if (arm_el_is_aa64(env, 1)) {
3560 t1sz = MIN(t1sz, 39);
3561 t1sz = MAX(t1sz, 16);
3562 }
3563 if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
3564 /* there is a ttbr0 region and we are in it (high bits all zero) */
3565 ttbr_select = 0;
3566 } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) {
3567 /* there is a ttbr1 region and we are in it (high bits all one) */
3568 ttbr_select = 1;
3569 } else if (!t0sz) {
3570 /* ttbr0 region is "everything not in the ttbr1 region" */
3571 ttbr_select = 0;
3572 } else if (!t1sz) {
3573 /* ttbr1 region is "everything not in the ttbr0 region" */
3574 ttbr_select = 1;
3575 } else {
3576 /* in the gap between the two regions, this is a Translation fault */
3577 fault_type = translation_fault;
3578 goto do_fault;
3579 }
3580
3581 /* Note that QEMU ignores shareability and cacheability attributes,
3582 * so we don't need to do anything with the SH, ORGN, IRGN fields
3583 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
3584 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3585 * implement any ASID-like capability so we can ignore it (instead
3586 * we will always flush the TLB any time the ASID is changed).
3587 */
3588 if (ttbr_select == 0) {
3589 ttbr = env->cp15.ttbr0_el1;
3590 epd = extract32(env->cp15.c2_control, 7, 1);
3591 tsz = t0sz;
3592
3593 tg = extract32(env->cp15.c2_control, 14, 2);
3594 if (tg == 1) { /* 64KB pages */
3595 granule_sz = 13;
3596 }
3597 if (tg == 2) { /* 16KB pages */
3598 granule_sz = 11;
3599 }
3600 } else {
3601 ttbr = env->cp15.ttbr1_el1;
3602 epd = extract32(env->cp15.c2_control, 23, 1);
3603 tsz = t1sz;
3604
3605 tg = extract32(env->cp15.c2_control, 30, 2);
3606 if (tg == 3) { /* 64KB pages */
3607 granule_sz = 13;
3608 }
3609 if (tg == 1) { /* 16KB pages */
3610 granule_sz = 11;
3611 }
3612 }
3613
3614 if (epd) {
3615 /* Translation table walk disabled => Translation fault on TLB miss */
3616 goto do_fault;
3617 }
3618
3619 /* The starting level depends on the virtual address size which can be
3620 * up to 48-bits and the translation granule size.
3621 */
3622 if ((va_size - tsz) > (granule_sz * 4 + 3)) {
3623 level = 0;
3624 } else if ((va_size - tsz) > (granule_sz * 3 + 3)) {
3625 level = 1;
3626 } else {
3627 level = 2;
3628 }
3629
3630 /* Clear the vaddr bits which aren't part of the within-region address,
3631 * so that we don't have to special case things when calculating the
3632 * first descriptor address.
3633 */
3634 if (tsz) {
3635 address &= (1ULL << (va_size - tsz)) - 1;
3636 }
3637
3638 descmask = (1ULL << (granule_sz + 3)) - 1;
3639
3640 /* Now we can extract the actual base address from the TTBR */
3641 descaddr = extract64(ttbr, 0, 48);
3642 descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
3643
3644 tableattrs = 0;
3645 for (;;) {
3646 uint64_t descriptor;
3647
3648 descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
3649 descaddr &= ~7ULL;
3650 descriptor = ldq_phys(cs->as, descaddr);
3651 if (!(descriptor & 1) ||
3652 (!(descriptor & 2) && (level == 3))) {
3653 /* Invalid, or the Reserved level 3 encoding */
3654 goto do_fault;
3655 }
3656 descaddr = descriptor & 0xfffffff000ULL;
3657
3658 if ((descriptor & 2) && (level < 3)) {
3659 /* Table entry. The top five bits are attributes which may
3660 * propagate down through lower levels of the table (and
3661 * which are all arranged so that 0 means "no effect", so
3662 * we can gather them up by ORing in the bits at each level).
3663 */
3664 tableattrs |= extract64(descriptor, 59, 5);
3665 level++;
3666 continue;
3667 }
3668 /* Block entry at level 1 or 2, or page entry at level 3.
3669 * These are basically the same thing, although the number
3670 * of bits we pull in from the vaddr varies.
3671 */
3672 page_size = (1 << ((granule_sz * (4 - level)) + 3));
3673 descaddr |= (address & (page_size - 1));
3674 /* Extract attributes from the descriptor and merge with table attrs */
3675 if (arm_feature(env, ARM_FEATURE_V8)) {
3676 attrs = extract64(descriptor, 2, 10)
3677 | (extract64(descriptor, 53, 11) << 10);
3678 } else {
3679 attrs = extract64(descriptor, 2, 10)
3680 | (extract64(descriptor, 52, 12) << 10);
3681 }
3682 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
3683 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
3684 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
3685 * means "force PL1 access only", which means forcing AP[1] to 0.
3686 */
3687 if (extract32(tableattrs, 2, 1)) {
3688 attrs &= ~(1 << 4);
3689 }
3690 /* Since we're always in the Non-secure state, NSTable is ignored. */
3691 break;
3692 }
3693 /* Here descaddr is the final physical address, and attributes
3694 * are all in attrs.
3695 */
3696 fault_type = access_fault;
3697 if ((attrs & (1 << 8)) == 0) {
3698 /* Access flag */
3699 goto do_fault;
3700 }
3701 fault_type = permission_fault;
3702 if (is_user && !(attrs & (1 << 4))) {
3703 /* Unprivileged access not enabled */
3704 goto do_fault;
3705 }
3706 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3707 if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
3708 /* XN or PXN */
3709 if (access_type == 2) {
3710 goto do_fault;
3711 }
3712 *prot &= ~PAGE_EXEC;
3713 }
3714 if (attrs & (1 << 5)) {
3715 /* Write access forbidden */
3716 if (access_type == 1) {
3717 goto do_fault;
3718 }
3719 *prot &= ~PAGE_WRITE;
3720 }
3721
3722 *phys_ptr = descaddr;
3723 *page_size_ptr = page_size;
3724 return 0;
3725
3726 do_fault:
3727 /* Long-descriptor format IFSR/DFSR value */
3728 return (1 << 9) | (fault_type << 2) | level;
3729 }
3730
3731 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
3732 int access_type, int is_user,
3733 hwaddr *phys_ptr, int *prot)
3734 {
3735 int n;
3736 uint32_t mask;
3737 uint32_t base;
3738
3739 *phys_ptr = address;
3740 for (n = 7; n >= 0; n--) {
3741 base = env->cp15.c6_region[n];
3742 if ((base & 1) == 0)
3743 continue;
3744 mask = 1 << ((base >> 1) & 0x1f);
3745 /* Keep this shift separate from the above to avoid an
3746 (undefined) << 32. */
3747 mask = (mask << 1) - 1;
3748 if (((base ^ address) & ~mask) == 0)
3749 break;
3750 }
3751 if (n < 0)
3752 return 2;
3753
3754 if (access_type == 2) {
3755 mask = env->cp15.pmsav5_insn_ap;
3756 } else {
3757 mask = env->cp15.pmsav5_data_ap;
3758 }
3759 mask = (mask >> (n * 4)) & 0xf;
3760 switch (mask) {
3761 case 0:
3762 return 1;
3763 case 1:
3764 if (is_user)
3765 return 1;
3766 *prot = PAGE_READ | PAGE_WRITE;
3767 break;
3768 case 2:
3769 *prot = PAGE_READ;
3770 if (!is_user)
3771 *prot |= PAGE_WRITE;
3772 break;
3773 case 3:
3774 *prot = PAGE_READ | PAGE_WRITE;
3775 break;
3776 case 5:
3777 if (is_user)
3778 return 1;
3779 *prot = PAGE_READ;
3780 break;
3781 case 6:
3782 *prot = PAGE_READ;
3783 break;
3784 default:
3785 /* Bad permission. */
3786 return 1;
3787 }
3788 *prot |= PAGE_EXEC;
3789 return 0;
3790 }
3791
3792 /* get_phys_addr - get the physical address for this virtual address
3793 *
3794 * Find the physical address corresponding to the given virtual address,
3795 * by doing a translation table walk on MMU based systems or using the
3796 * MPU state on MPU based systems.
3797 *
3798 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
3799 * prot and page_size are not filled in, and the return value provides
3800 * information on why the translation aborted, in the format of a
3801 * DFSR/IFSR fault register, with the following caveats:
3802 * * we honour the short vs long DFSR format differences.
3803 * * the WnR bit is never set (the caller must do this).
3804 * * for MPU based systems we don't bother to return a full FSR format
3805 * value.
3806 *
3807 * @env: CPUARMState
3808 * @address: virtual address to get physical address for
3809 * @access_type: 0 for read, 1 for write, 2 for execute
3810 * @is_user: 0 for privileged access, 1 for user
3811 * @phys_ptr: set to the physical address corresponding to the virtual address
3812 * @prot: set to the permissions for the page containing phys_ptr
3813 * @page_size: set to the size of the page containing phys_ptr
3814 */
3815 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
3816 int access_type, int is_user,
3817 hwaddr *phys_ptr, int *prot,
3818 target_ulong *page_size)
3819 {
3820 /* Fast Context Switch Extension. */
3821 if (address < 0x02000000)
3822 address += env->cp15.c13_fcse;
3823
3824 if ((env->cp15.c1_sys & SCTLR_M) == 0) {
3825 /* MMU/MPU disabled. */
3826 *phys_ptr = address;
3827 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3828 *page_size = TARGET_PAGE_SIZE;
3829 return 0;
3830 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
3831 *page_size = TARGET_PAGE_SIZE;
3832 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
3833 prot);
3834 } else if (extended_addresses_enabled(env)) {
3835 return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
3836 prot, page_size);
3837 } else if (env->cp15.c1_sys & SCTLR_XP) {
3838 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
3839 prot, page_size);
3840 } else {
3841 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
3842 prot, page_size);
3843 }
3844 }
3845
3846 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
3847 int access_type, int mmu_idx)
3848 {
3849 ARMCPU *cpu = ARM_CPU(cs);
3850 CPUARMState *env = &cpu->env;
3851 hwaddr phys_addr;
3852 target_ulong page_size;
3853 int prot;
3854 int ret, is_user;
3855 uint32_t syn;
3856 bool same_el = (arm_current_pl(env) != 0);
3857
3858 is_user = mmu_idx == MMU_USER_IDX;
3859 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
3860 &page_size);
3861 if (ret == 0) {
3862 /* Map a single [sub]page. */
3863 phys_addr &= ~(hwaddr)0x3ff;
3864 address &= ~(target_ulong)0x3ff;
3865 tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
3866 return 0;
3867 }
3868
3869 /* AArch64 syndrome does not have an LPAE bit */
3870 syn = ret & ~(1 << 9);
3871
3872 /* For insn and data aborts we assume there is no instruction syndrome
3873 * information; this is always true for exceptions reported to EL1.
3874 */
3875 if (access_type == 2) {
3876 syn = syn_insn_abort(same_el, 0, 0, syn);
3877 cs->exception_index = EXCP_PREFETCH_ABORT;
3878 } else {
3879 syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn);
3880 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
3881 ret |= (1 << 11);
3882 }
3883 cs->exception_index = EXCP_DATA_ABORT;
3884 }
3885
3886 env->exception.syndrome = syn;
3887 env->exception.vaddress = address;
3888 env->exception.fsr = ret;
3889 return 1;
3890 }
3891
3892 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
3893 {
3894 ARMCPU *cpu = ARM_CPU(cs);
3895 hwaddr phys_addr;
3896 target_ulong page_size;
3897 int prot;
3898 int ret;
3899
3900 ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
3901
3902 if (ret != 0) {
3903 return -1;
3904 }
3905
3906 return phys_addr;
3907 }
3908
3909 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3910 {
3911 if ((env->uncached_cpsr & CPSR_M) == mode) {
3912 env->regs[13] = val;
3913 } else {
3914 env->banked_r13[bank_number(mode)] = val;
3915 }
3916 }
3917
3918 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3919 {
3920 if ((env->uncached_cpsr & CPSR_M) == mode) {
3921 return env->regs[13];
3922 } else {
3923 return env->banked_r13[bank_number(mode)];
3924 }
3925 }
3926
3927 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3928 {
3929 ARMCPU *cpu = arm_env_get_cpu(env);
3930
3931 switch (reg) {
3932 case 0: /* APSR */
3933 return xpsr_read(env) & 0xf8000000;
3934 case 1: /* IAPSR */
3935 return xpsr_read(env) & 0xf80001ff;
3936 case 2: /* EAPSR */
3937 return xpsr_read(env) & 0xff00fc00;
3938 case 3: /* xPSR */
3939 return xpsr_read(env) & 0xff00fdff;
3940 case 5: /* IPSR */
3941 return xpsr_read(env) & 0x000001ff;
3942 case 6: /* EPSR */
3943 return xpsr_read(env) & 0x0700fc00;
3944 case 7: /* IEPSR */
3945 return xpsr_read(env) & 0x0700edff;
3946 case 8: /* MSP */
3947 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
3948 case 9: /* PSP */
3949 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
3950 case 16: /* PRIMASK */
3951 return (env->daif & PSTATE_I) != 0;
3952 case 17: /* BASEPRI */
3953 case 18: /* BASEPRI_MAX */
3954 return env->v7m.basepri;
3955 case 19: /* FAULTMASK */
3956 return (env->daif & PSTATE_F) != 0;
3957 case 20: /* CONTROL */
3958 return env->v7m.control;
3959 default:
3960 /* ??? For debugging only. */
3961 cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
3962 return 0;
3963 }
3964 }
3965
3966 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3967 {
3968 ARMCPU *cpu = arm_env_get_cpu(env);
3969
3970 switch (reg) {
3971 case 0: /* APSR */
3972 xpsr_write(env, val, 0xf8000000);
3973 break;
3974 case 1: /* IAPSR */
3975 xpsr_write(env, val, 0xf8000000);
3976 break;
3977 case 2: /* EAPSR */
3978 xpsr_write(env, val, 0xfe00fc00);
3979 break;
3980 case 3: /* xPSR */
3981 xpsr_write(env, val, 0xfe00fc00);
3982 break;
3983 case 5: /* IPSR */
3984 /* IPSR bits are readonly. */
3985 break;
3986 case 6: /* EPSR */
3987 xpsr_write(env, val, 0x0600fc00);
3988 break;
3989 case 7: /* IEPSR */
3990 xpsr_write(env, val, 0x0600fc00);
3991 break;
3992 case 8: /* MSP */
3993 if (env->v7m.current_sp)
3994 env->v7m.other_sp = val;
3995 else
3996 env->regs[13] = val;
3997 break;
3998 case 9: /* PSP */
3999 if (env->v7m.current_sp)
4000 env->regs[13] = val;
4001 else
4002 env->v7m.other_sp = val;
4003 break;
4004 case 16: /* PRIMASK */
4005 if (val & 1) {
4006 env->daif |= PSTATE_I;
4007 } else {
4008 env->daif &= ~PSTATE_I;
4009 }
4010 break;
4011 case 17: /* BASEPRI */
4012 env->v7m.basepri = val & 0xff;
4013 break;
4014 case 18: /* BASEPRI_MAX */
4015 val &= 0xff;
4016 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
4017 env->v7m.basepri = val;
4018 break;
4019 case 19: /* FAULTMASK */
4020 if (val & 1) {
4021 env->daif |= PSTATE_F;
4022 } else {
4023 env->daif &= ~PSTATE_F;
4024 }
4025 break;
4026 case 20: /* CONTROL */
4027 env->v7m.control = val & 3;
4028 switch_v7m_sp(env, (val & 2) != 0);
4029 break;
4030 default:
4031 /* ??? For debugging only. */
4032 cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
4033 return;
4034 }
4035 }
4036
4037 #endif
4038
4039 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
4040 {
4041 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
4042 * Note that we do not implement the (architecturally mandated)
4043 * alignment fault for attempts to use this on Device memory
4044 * (which matches the usual QEMU behaviour of not implementing either
4045 * alignment faults or any memory attribute handling).
4046 */
4047
4048 ARMCPU *cpu = arm_env_get_cpu(env);
4049 uint64_t blocklen = 4 << cpu->dcz_blocksize;
4050 uint64_t vaddr = vaddr_in & ~(blocklen - 1);
4051
4052 #ifndef CONFIG_USER_ONLY
4053 {
4054 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
4055 * the block size so we might have to do more than one TLB lookup.
4056 * We know that in fact for any v8 CPU the page size is at least 4K
4057 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
4058 * 1K as an artefact of legacy v5 subpage support being present in the
4059 * same QEMU executable.
4060 */
4061 int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
4062 void *hostaddr[maxidx];
4063 int try, i;
4064
4065 for (try = 0; try < 2; try++) {
4066
4067 for (i = 0; i < maxidx; i++) {
4068 hostaddr[i] = tlb_vaddr_to_host(env,
4069 vaddr + TARGET_PAGE_SIZE * i,
4070 1, cpu_mmu_index(env));
4071 if (!hostaddr[i]) {
4072 break;
4073 }
4074 }
4075 if (i == maxidx) {
4076 /* If it's all in the TLB it's fair game for just writing to;
4077 * we know we don't need to update dirty status, etc.
4078 */
4079 for (i = 0; i < maxidx - 1; i++) {
4080 memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
4081 }
4082 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
4083 return;
4084 }
4085 /* OK, try a store and see if we can populate the tlb. This
4086 * might cause an exception if the memory isn't writable,
4087 * in which case we will longjmp out of here. We must for
4088 * this purpose use the actual register value passed to us
4089 * so that we get the fault address right.
4090 */
4091 helper_ret_stb_mmu(env, vaddr_in, 0, cpu_mmu_index(env), GETRA());
4092 /* Now we can populate the other TLB entries, if any */
4093 for (i = 0; i < maxidx; i++) {
4094 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
4095 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
4096 helper_ret_stb_mmu(env, va, 0, cpu_mmu_index(env), GETRA());
4097 }
4098 }
4099 }
4100
4101 /* Slow path (probably attempt to do this to an I/O device or
4102 * similar, or clearing of a block of code we have translations
4103 * cached for). Just do a series of byte writes as the architecture
4104 * demands. It's not worth trying to use a cpu_physical_memory_map(),
4105 * memset(), unmap() sequence here because:
4106 * + we'd need to account for the blocksize being larger than a page
4107 * + the direct-RAM access case is almost always going to be dealt
4108 * with in the fastpath code above, so there's no speed benefit
4109 * + we would have to deal with the map returning NULL because the
4110 * bounce buffer was in use
4111 */
4112 for (i = 0; i < blocklen; i++) {
4113 helper_ret_stb_mmu(env, vaddr + i, 0, cpu_mmu_index(env), GETRA());
4114 }
4115 }
4116 #else
4117 memset(g2h(vaddr), 0, blocklen);
4118 #endif
4119 }
4120
4121 /* Note that signed overflow is undefined in C. The following routines are
4122 careful to use unsigned types where modulo arithmetic is required.
4123 Failure to do so _will_ break on newer gcc. */
4124
4125 /* Signed saturating arithmetic. */
4126
4127 /* Perform 16-bit signed saturating addition. */
4128 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
4129 {
4130 uint16_t res;
4131
4132 res = a + b;
4133 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
4134 if (a & 0x8000)
4135 res = 0x8000;
4136 else
4137 res = 0x7fff;
4138 }
4139 return res;
4140 }
4141
4142 /* Perform 8-bit signed saturating addition. */
4143 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
4144 {
4145 uint8_t res;
4146
4147 res = a + b;
4148 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
4149 if (a & 0x80)
4150 res = 0x80;
4151 else
4152 res = 0x7f;
4153 }
4154 return res;
4155 }
4156
4157 /* Perform 16-bit signed saturating subtraction. */
4158 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
4159 {
4160 uint16_t res;
4161
4162 res = a - b;
4163 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
4164 if (a & 0x8000)
4165 res = 0x8000;
4166 else
4167 res = 0x7fff;
4168 }
4169 return res;
4170 }
4171
4172 /* Perform 8-bit signed saturating subtraction. */
4173 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
4174 {
4175 uint8_t res;
4176
4177 res = a - b;
4178 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
4179 if (a & 0x80)
4180 res = 0x80;
4181 else
4182 res = 0x7f;
4183 }
4184 return res;
4185 }
4186
4187 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
4188 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
4189 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
4190 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
4191 #define PFX q
4192
4193 #include "op_addsub.h"
4194
4195 /* Unsigned saturating arithmetic. */
4196 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
4197 {
4198 uint16_t res;
4199 res = a + b;
4200 if (res < a)
4201 res = 0xffff;
4202 return res;
4203 }
4204
4205 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
4206 {
4207 if (a > b)
4208 return a - b;
4209 else
4210 return 0;
4211 }
4212
4213 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
4214 {
4215 uint8_t res;
4216 res = a + b;
4217 if (res < a)
4218 res = 0xff;
4219 return res;
4220 }
4221
4222 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
4223 {
4224 if (a > b)
4225 return a - b;
4226 else
4227 return 0;
4228 }
4229
4230 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
4231 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
4232 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
4233 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
4234 #define PFX uq
4235
4236 #include "op_addsub.h"
4237
4238 /* Signed modulo arithmetic. */
4239 #define SARITH16(a, b, n, op) do { \
4240 int32_t sum; \
4241 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
4242 RESULT(sum, n, 16); \
4243 if (sum >= 0) \
4244 ge |= 3 << (n * 2); \
4245 } while(0)
4246
4247 #define SARITH8(a, b, n, op) do { \
4248 int32_t sum; \
4249 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
4250 RESULT(sum, n, 8); \
4251 if (sum >= 0) \
4252 ge |= 1 << n; \
4253 } while(0)
4254
4255
4256 #define ADD16(a, b, n) SARITH16(a, b, n, +)
4257 #define SUB16(a, b, n) SARITH16(a, b, n, -)
4258 #define ADD8(a, b, n) SARITH8(a, b, n, +)
4259 #define SUB8(a, b, n) SARITH8(a, b, n, -)
4260 #define PFX s
4261 #define ARITH_GE
4262
4263 #include "op_addsub.h"
4264
4265 /* Unsigned modulo arithmetic. */
4266 #define ADD16(a, b, n) do { \
4267 uint32_t sum; \
4268 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
4269 RESULT(sum, n, 16); \
4270 if ((sum >> 16) == 1) \
4271 ge |= 3 << (n * 2); \
4272 } while(0)
4273
4274 #define ADD8(a, b, n) do { \
4275 uint32_t sum; \
4276 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
4277 RESULT(sum, n, 8); \
4278 if ((sum >> 8) == 1) \
4279 ge |= 1 << n; \
4280 } while(0)
4281
4282 #define SUB16(a, b, n) do { \
4283 uint32_t sum; \
4284 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
4285 RESULT(sum, n, 16); \
4286 if ((sum >> 16) == 0) \
4287 ge |= 3 << (n * 2); \
4288 } while(0)
4289
4290 #define SUB8(a, b, n) do { \
4291 uint32_t sum; \
4292 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
4293 RESULT(sum, n, 8); \
4294 if ((sum >> 8) == 0) \
4295 ge |= 1 << n; \
4296 } while(0)
4297
4298 #define PFX u
4299 #define ARITH_GE
4300
4301 #include "op_addsub.h"
4302
4303 /* Halved signed arithmetic. */
4304 #define ADD16(a, b, n) \
4305 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
4306 #define SUB16(a, b, n) \
4307 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
4308 #define ADD8(a, b, n) \
4309 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
4310 #define SUB8(a, b, n) \
4311 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
4312 #define PFX sh
4313
4314 #include "op_addsub.h"
4315
4316 /* Halved unsigned arithmetic. */
4317 #define ADD16(a, b, n) \
4318 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4319 #define SUB16(a, b, n) \
4320 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4321 #define ADD8(a, b, n) \
4322 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4323 #define SUB8(a, b, n) \
4324 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4325 #define PFX uh
4326
4327 #include "op_addsub.h"
4328
4329 static inline uint8_t do_usad(uint8_t a, uint8_t b)
4330 {
4331 if (a > b)
4332 return a - b;
4333 else
4334 return b - a;
4335 }
4336
4337 /* Unsigned sum of absolute byte differences. */
4338 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
4339 {
4340 uint32_t sum;
4341 sum = do_usad(a, b);
4342 sum += do_usad(a >> 8, b >> 8);
4343 sum += do_usad(a >> 16, b >>16);
4344 sum += do_usad(a >> 24, b >> 24);
4345 return sum;
4346 }
4347
4348 /* For ARMv6 SEL instruction. */
4349 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
4350 {
4351 uint32_t mask;
4352
4353 mask = 0;
4354 if (flags & 1)
4355 mask |= 0xff;
4356 if (flags & 2)
4357 mask |= 0xff00;
4358 if (flags & 4)
4359 mask |= 0xff0000;
4360 if (flags & 8)
4361 mask |= 0xff000000;
4362 return (a & mask) | (b & ~mask);
4363 }
4364
4365 /* VFP support. We follow the convention used for VFP instructions:
4366 Single precision routines have a "s" suffix, double precision a
4367 "d" suffix. */
4368
4369 /* Convert host exception flags to vfp form. */
4370 static inline int vfp_exceptbits_from_host(int host_bits)
4371 {
4372 int target_bits = 0;
4373
4374 if (host_bits & float_flag_invalid)
4375 target_bits |= 1;
4376 if (host_bits & float_flag_divbyzero)
4377 target_bits |= 2;
4378 if (host_bits & float_flag_overflow)
4379 target_bits |= 4;
4380 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4381 target_bits |= 8;
4382 if (host_bits & float_flag_inexact)
4383 target_bits |= 0x10;
4384 if (host_bits & float_flag_input_denormal)
4385 target_bits |= 0x80;
4386 return target_bits;
4387 }
4388
4389 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4390 {
4391 int i;
4392 uint32_t fpscr;
4393
4394 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
4395 | (env->vfp.vec_len << 16)
4396 | (env->vfp.vec_stride << 20);
4397 i = get_float_exception_flags(&env->vfp.fp_status);
4398 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4399 fpscr |= vfp_exceptbits_from_host(i);
4400 return fpscr;
4401 }
4402
4403 uint32_t vfp_get_fpscr(CPUARMState *env)
4404 {
4405 return HELPER(vfp_get_fpscr)(env);
4406 }
4407
4408 /* Convert vfp exception flags to target form. */
4409 static inline int vfp_exceptbits_to_host(int target_bits)
4410 {
4411 int host_bits = 0;
4412
4413 if (target_bits & 1)
4414 host_bits |= float_flag_invalid;
4415 if (target_bits & 2)
4416 host_bits |= float_flag_divbyzero;
4417 if (target_bits & 4)
4418 host_bits |= float_flag_overflow;
4419 if (target_bits & 8)
4420 host_bits |= float_flag_underflow;
4421 if (target_bits & 0x10)
4422 host_bits |= float_flag_inexact;
4423 if (target_bits & 0x80)
4424 host_bits |= float_flag_input_denormal;
4425 return host_bits;
4426 }
4427
4428 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4429 {
4430 int i;
4431 uint32_t changed;
4432
4433 changed = env->vfp.xregs[ARM_VFP_FPSCR];
4434 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
4435 env->vfp.vec_len = (val >> 16) & 7;
4436 env->vfp.vec_stride = (val >> 20) & 3;
4437
4438 changed ^= val;
4439 if (changed & (3 << 22)) {
4440 i = (val >> 22) & 3;
4441 switch (i) {
4442 case FPROUNDING_TIEEVEN:
4443 i = float_round_nearest_even;
4444 break;
4445 case FPROUNDING_POSINF:
4446 i = float_round_up;
4447 break;
4448 case FPROUNDING_NEGINF:
4449 i = float_round_down;
4450 break;
4451 case FPROUNDING_ZERO:
4452 i = float_round_to_zero;
4453 break;
4454 }
4455 set_float_rounding_mode(i, &env->vfp.fp_status);
4456 }
4457 if (changed & (1 << 24)) {
4458 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4459 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4460 }
4461 if (changed & (1 << 25))
4462 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4463
4464 i = vfp_exceptbits_to_host(val);
4465 set_float_exception_flags(i, &env->vfp.fp_status);
4466 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4467 }
4468
4469 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
4470 {
4471 HELPER(vfp_set_fpscr)(env, val);
4472 }
4473
4474 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
4475
4476 #define VFP_BINOP(name) \
4477 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4478 { \
4479 float_status *fpst = fpstp; \
4480 return float32_ ## name(a, b, fpst); \
4481 } \
4482 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4483 { \
4484 float_status *fpst = fpstp; \
4485 return float64_ ## name(a, b, fpst); \
4486 }
4487 VFP_BINOP(add)
4488 VFP_BINOP(sub)
4489 VFP_BINOP(mul)
4490 VFP_BINOP(div)
4491 VFP_BINOP(min)
4492 VFP_BINOP(max)
4493 VFP_BINOP(minnum)
4494 VFP_BINOP(maxnum)
4495 #undef VFP_BINOP
4496
4497 float32 VFP_HELPER(neg, s)(float32 a)
4498 {
4499 return float32_chs(a);
4500 }
4501
4502 float64 VFP_HELPER(neg, d)(float64 a)
4503 {
4504 return float64_chs(a);
4505 }
4506
4507 float32 VFP_HELPER(abs, s)(float32 a)
4508 {
4509 return float32_abs(a);
4510 }
4511
4512 float64 VFP_HELPER(abs, d)(float64 a)
4513 {
4514 return float64_abs(a);
4515 }
4516
4517 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4518 {
4519 return float32_sqrt(a, &env->vfp.fp_status);
4520 }
4521
4522 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4523 {
4524 return float64_sqrt(a, &env->vfp.fp_status);
4525 }
4526
4527 /* XXX: check quiet/signaling case */
4528 #define DO_VFP_cmp(p, type) \
4529 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4530 { \
4531 uint32_t flags; \
4532 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
4533 case 0: flags = 0x6; break; \
4534 case -1: flags = 0x8; break; \
4535 case 1: flags = 0x2; break; \
4536 default: case 2: flags = 0x3; break; \
4537 } \
4538 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4539 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4540 } \
4541 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4542 { \
4543 uint32_t flags; \
4544 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
4545 case 0: flags = 0x6; break; \
4546 case -1: flags = 0x8; break; \
4547 case 1: flags = 0x2; break; \
4548 default: case 2: flags = 0x3; break; \
4549 } \
4550 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4551 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4552 }
4553 DO_VFP_cmp(s, float32)
4554 DO_VFP_cmp(d, float64)
4555 #undef DO_VFP_cmp
4556
4557 /* Integer to float and float to integer conversions */
4558
4559 #define CONV_ITOF(name, fsz, sign) \
4560 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
4561 { \
4562 float_status *fpst = fpstp; \
4563 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4564 }
4565
4566 #define CONV_FTOI(name, fsz, sign, round) \
4567 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
4568 { \
4569 float_status *fpst = fpstp; \
4570 if (float##fsz##_is_any_nan(x)) { \
4571 float_raise(float_flag_invalid, fpst); \
4572 return 0; \
4573 } \
4574 return float##fsz##_to_##sign##int32##round(x, fpst); \
4575 }
4576
4577 #define FLOAT_CONVS(name, p, fsz, sign) \
4578 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
4579 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
4580 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4581
4582 FLOAT_CONVS(si, s, 32, )
4583 FLOAT_CONVS(si, d, 64, )
4584 FLOAT_CONVS(ui, s, 32, u)
4585 FLOAT_CONVS(ui, d, 64, u)
4586
4587 #undef CONV_ITOF
4588 #undef CONV_FTOI
4589 #undef FLOAT_CONVS
4590
4591 /* floating point conversion */
4592 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4593 {
4594 float64 r = float32_to_float64(x, &env->vfp.fp_status);
4595 /* ARM requires that S<->D conversion of any kind of NaN generates
4596 * a quiet NaN by forcing the most significant frac bit to 1.
4597 */
4598 return float64_maybe_silence_nan(r);
4599 }
4600
4601 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4602 {
4603 float32 r = float64_to_float32(x, &env->vfp.fp_status);
4604 /* ARM requires that S<->D conversion of any kind of NaN generates
4605 * a quiet NaN by forcing the most significant frac bit to 1.
4606 */
4607 return float32_maybe_silence_nan(r);
4608 }
4609
4610 /* VFP3 fixed point conversion. */
4611 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4612 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
4613 void *fpstp) \
4614 { \
4615 float_status *fpst = fpstp; \
4616 float##fsz tmp; \
4617 tmp = itype##_to_##float##fsz(x, fpst); \
4618 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4619 }
4620
4621 /* Notice that we want only input-denormal exception flags from the
4622 * scalbn operation: the other possible flags (overflow+inexact if
4623 * we overflow to infinity, output-denormal) aren't correct for the
4624 * complete scale-and-convert operation.
4625 */
4626 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
4627 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
4628 uint32_t shift, \
4629 void *fpstp) \
4630 { \
4631 float_status *fpst = fpstp; \
4632 int old_exc_flags = get_float_exception_flags(fpst); \
4633 float##fsz tmp; \
4634 if (float##fsz##_is_any_nan(x)) { \
4635 float_raise(float_flag_invalid, fpst); \
4636 return 0; \
4637 } \
4638 tmp = float##fsz##_scalbn(x, shift, fpst); \
4639 old_exc_flags |= get_float_exception_flags(fpst) \
4640 & float_flag_input_denormal; \
4641 set_float_exception_flags(old_exc_flags, fpst); \
4642 return float##fsz##_to_##itype##round(tmp, fpst); \
4643 }
4644
4645 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
4646 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4647 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
4648 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4649
4650 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
4651 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4652 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4653
4654 VFP_CONV_FIX(sh, d, 64, 64, int16)
4655 VFP_CONV_FIX(sl, d, 64, 64, int32)
4656 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
4657 VFP_CONV_FIX(uh, d, 64, 64, uint16)
4658 VFP_CONV_FIX(ul, d, 64, 64, uint32)
4659 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
4660 VFP_CONV_FIX(sh, s, 32, 32, int16)
4661 VFP_CONV_FIX(sl, s, 32, 32, int32)
4662 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
4663 VFP_CONV_FIX(uh, s, 32, 32, uint16)
4664 VFP_CONV_FIX(ul, s, 32, 32, uint32)
4665 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
4666 #undef VFP_CONV_FIX
4667 #undef VFP_CONV_FIX_FLOAT
4668 #undef VFP_CONV_FLOAT_FIX_ROUND
4669
4670 /* Set the current fp rounding mode and return the old one.
4671 * The argument is a softfloat float_round_ value.
4672 */
4673 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
4674 {
4675 float_status *fp_status = &env->vfp.fp_status;
4676
4677 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4678 set_float_rounding_mode(rmode, fp_status);
4679
4680 return prev_rmode;
4681 }
4682
4683 /* Set the current fp rounding mode in the standard fp status and return
4684 * the old one. This is for NEON instructions that need to change the
4685 * rounding mode but wish to use the standard FPSCR values for everything
4686 * else. Always set the rounding mode back to the correct value after
4687 * modifying it.
4688 * The argument is a softfloat float_round_ value.
4689 */
4690 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
4691 {
4692 float_status *fp_status = &env->vfp.standard_fp_status;
4693
4694 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4695 set_float_rounding_mode(rmode, fp_status);
4696
4697 return prev_rmode;
4698 }
4699
4700 /* Half precision conversions. */
4701 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
4702 {
4703 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4704 float32 r = float16_to_float32(make_float16(a), ieee, s);
4705 if (ieee) {
4706 return float32_maybe_silence_nan(r);
4707 }
4708 return r;
4709 }
4710
4711 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
4712 {
4713 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4714 float16 r = float32_to_float16(a, ieee, s);
4715 if (ieee) {
4716 r = float16_maybe_silence_nan(r);
4717 }
4718 return float16_val(r);
4719 }
4720
4721 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4722 {
4723 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
4724 }
4725
4726 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4727 {
4728 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
4729 }
4730
4731 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4732 {
4733 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
4734 }
4735
4736 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4737 {
4738 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
4739 }
4740
4741 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
4742 {
4743 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4744 float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
4745 if (ieee) {
4746 return float64_maybe_silence_nan(r);
4747 }
4748 return r;
4749 }
4750
4751 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
4752 {
4753 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4754 float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
4755 if (ieee) {
4756 r = float16_maybe_silence_nan(r);
4757 }
4758 return float16_val(r);
4759 }
4760
4761 #define float32_two make_float32(0x40000000)
4762 #define float32_three make_float32(0x40400000)
4763 #define float32_one_point_five make_float32(0x3fc00000)
4764
4765 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4766 {
4767 float_status *s = &env->vfp.standard_fp_status;
4768 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4769 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4770 if (!(float32_is_zero(a) || float32_is_zero(b))) {
4771 float_raise(float_flag_input_denormal, s);
4772 }
4773 return float32_two;
4774 }
4775 return float32_sub(float32_two, float32_mul(a, b, s), s);
4776 }
4777
4778 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4779 {
4780 float_status *s = &env->vfp.standard_fp_status;
4781 float32 product;
4782 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4783 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4784 if (!(float32_is_zero(a) || float32_is_zero(b))) {
4785 float_raise(float_flag_input_denormal, s);
4786 }
4787 return float32_one_point_five;
4788 }
4789 product = float32_mul(a, b, s);
4790 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4791 }
4792
4793 /* NEON helpers. */
4794
4795 /* Constants 256 and 512 are used in some helpers; we avoid relying on
4796 * int->float conversions at run-time. */
4797 #define float64_256 make_float64(0x4070000000000000LL)
4798 #define float64_512 make_float64(0x4080000000000000LL)
4799 #define float32_maxnorm make_float32(0x7f7fffff)
4800 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
4801
4802 /* Reciprocal functions
4803 *
4804 * The algorithm that must be used to calculate the estimate
4805 * is specified by the ARM ARM, see FPRecipEstimate()
4806 */
4807
4808 static float64 recip_estimate(float64 a, float_status *real_fp_status)
4809 {
4810 /* These calculations mustn't set any fp exception flags,
4811 * so we use a local copy of the fp_status.
4812 */
4813 float_status dummy_status = *real_fp_status;
4814 float_status *s = &dummy_status;
4815 /* q = (int)(a * 512.0) */
4816 float64 q = float64_mul(float64_512, a, s);
4817 int64_t q_int = float64_to_int64_round_to_zero(q, s);
4818
4819 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
4820 q = int64_to_float64(q_int, s);
4821 q = float64_add(q, float64_half, s);
4822 q = float64_div(q, float64_512, s);
4823 q = float64_div(float64_one, q, s);
4824
4825 /* s = (int)(256.0 * r + 0.5) */
4826 q = float64_mul(q, float64_256, s);
4827 q = float64_add(q, float64_half, s);
4828 q_int = float64_to_int64_round_to_zero(q, s);
4829
4830 /* return (double)s / 256.0 */
4831 return float64_div(int64_to_float64(q_int, s), float64_256, s);
4832 }
4833
4834 /* Common wrapper to call recip_estimate */
4835 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
4836 {
4837 uint64_t val64 = float64_val(num);
4838 uint64_t frac = extract64(val64, 0, 52);
4839 int64_t exp = extract64(val64, 52, 11);
4840 uint64_t sbit;
4841 float64 scaled, estimate;
4842
4843 /* Generate the scaled number for the estimate function */
4844 if (exp == 0) {
4845 if (extract64(frac, 51, 1) == 0) {
4846 exp = -1;
4847 frac = extract64(frac, 0, 50) << 2;
4848 } else {
4849 frac = extract64(frac, 0, 51) << 1;
4850 }
4851 }
4852
4853 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
4854 scaled = make_float64((0x3feULL << 52)
4855 | extract64(frac, 44, 8) << 44);
4856
4857 estimate = recip_estimate(scaled, fpst);
4858
4859 /* Build new result */
4860 val64 = float64_val(estimate);
4861 sbit = 0x8000000000000000ULL & val64;
4862 exp = off - exp;
4863 frac = extract64(val64, 0, 52);
4864
4865 if (exp == 0) {
4866 frac = 1ULL << 51 | extract64(frac, 1, 51);
4867 } else if (exp == -1) {
4868 frac = 1ULL << 50 | extract64(frac, 2, 50);
4869 exp = 0;
4870 }
4871
4872 return make_float64(sbit | (exp << 52) | frac);
4873 }
4874
4875 static bool round_to_inf(float_status *fpst, bool sign_bit)
4876 {
4877 switch (fpst->float_rounding_mode) {
4878 case float_round_nearest_even: /* Round to Nearest */
4879 return true;
4880 case float_round_up: /* Round to +Inf */
4881 return !sign_bit;
4882 case float_round_down: /* Round to -Inf */
4883 return sign_bit;
4884 case float_round_to_zero: /* Round to Zero */
4885 return false;
4886 }
4887
4888 g_assert_not_reached();
4889 }
4890
4891 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
4892 {
4893 float_status *fpst = fpstp;
4894 float32 f32 = float32_squash_input_denormal(input, fpst);
4895 uint32_t f32_val = float32_val(f32);
4896 uint32_t f32_sbit = 0x80000000ULL & f32_val;
4897 int32_t f32_exp = extract32(f32_val, 23, 8);
4898 uint32_t f32_frac = extract32(f32_val, 0, 23);
4899 float64 f64, r64;
4900 uint64_t r64_val;
4901 int64_t r64_exp;
4902 uint64_t r64_frac;
4903
4904 if (float32_is_any_nan(f32)) {
4905 float32 nan = f32;
4906 if (float32_is_signaling_nan(f32)) {
4907 float_raise(float_flag_invalid, fpst);
4908 nan = float32_maybe_silence_nan(f32);
4909 }
4910 if (fpst->default_nan_mode) {
4911 nan = float32_default_nan;
4912 }
4913 return nan;
4914 } else if (float32_is_infinity(f32)) {
4915 return float32_set_sign(float32_zero, float32_is_neg(f32));
4916 } else if (float32_is_zero(f32)) {
4917 float_raise(float_flag_divbyzero, fpst);
4918 return float32_set_sign(float32_infinity, float32_is_neg(f32));
4919 } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
4920 /* Abs(value) < 2.0^-128 */
4921 float_raise(float_flag_overflow | float_flag_inexact, fpst);
4922 if (round_to_inf(fpst, f32_sbit)) {
4923 return float32_set_sign(float32_infinity, float32_is_neg(f32));
4924 } else {
4925 return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
4926 }
4927 } else if (f32_exp >= 253 && fpst->flush_to_zero) {
4928 float_raise(float_flag_underflow, fpst);
4929 return float32_set_sign(float32_zero, float32_is_neg(f32));
4930 }
4931
4932
4933 f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
4934 r64 = call_recip_estimate(f64, 253, fpst);
4935 r64_val = float64_val(r64);
4936 r64_exp = extract64(r64_val, 52, 11);
4937 r64_frac = extract64(r64_val, 0, 52);
4938
4939 /* result = sign : result_exp<7:0> : fraction<51:29>; */
4940 return make_float32(f32_sbit |
4941 (r64_exp & 0xff) << 23 |
4942 extract64(r64_frac, 29, 24));
4943 }
4944
4945 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
4946 {
4947 float_status *fpst = fpstp;
4948 float64 f64 = float64_squash_input_denormal(input, fpst);
4949 uint64_t f64_val = float64_val(f64);
4950 uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
4951 int64_t f64_exp = extract64(f64_val, 52, 11);
4952 float64 r64;
4953 uint64_t r64_val;
4954 int64_t r64_exp;
4955 uint64_t r64_frac;
4956
4957 /* Deal with any special cases */
4958 if (float64_is_any_nan(f64)) {
4959 float64 nan = f64;
4960 if (float64_is_signaling_nan(f64)) {
4961 float_raise(float_flag_invalid, fpst);
4962 nan = float64_maybe_silence_nan(f64);
4963 }
4964 if (fpst->default_nan_mode) {
4965 nan = float64_default_nan;
4966 }
4967 return nan;
4968 } else if (float64_is_infinity(f64)) {
4969 return float64_set_sign(float64_zero, float64_is_neg(f64));
4970 } else if (float64_is_zero(f64)) {
4971 float_raise(float_flag_divbyzero, fpst);
4972 return float64_set_sign(float64_infinity, float64_is_neg(f64));
4973 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
4974 /* Abs(value) < 2.0^-1024 */
4975 float_raise(float_flag_overflow | float_flag_inexact, fpst);
4976 if (round_to_inf(fpst, f64_sbit)) {
4977 return float64_set_sign(float64_infinity, float64_is_neg(f64));
4978 } else {
4979 return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
4980 }
4981 } else if (f64_exp >= 1023 && fpst->flush_to_zero) {
4982 float_raise(float_flag_underflow, fpst);
4983 return float64_set_sign(float64_zero, float64_is_neg(f64));
4984 }
4985
4986 r64 = call_recip_estimate(f64, 2045, fpst);
4987 r64_val = float64_val(r64);
4988 r64_exp = extract64(r64_val, 52, 11);
4989 r64_frac = extract64(r64_val, 0, 52);
4990
4991 /* result = sign : result_exp<10:0> : fraction<51:0> */
4992 return make_float64(f64_sbit |
4993 ((r64_exp & 0x7ff) << 52) |
4994 r64_frac);
4995 }
4996
4997 /* The algorithm that must be used to calculate the estimate
4998 * is specified by the ARM ARM.
4999 */
5000 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
5001 {
5002 /* These calculations mustn't set any fp exception flags,
5003 * so we use a local copy of the fp_status.
5004 */
5005 float_status dummy_status = *real_fp_status;
5006 float_status *s = &dummy_status;
5007 float64 q;
5008 int64_t q_int;
5009
5010 if (float64_lt(a, float64_half, s)) {
5011 /* range 0.25 <= a < 0.5 */
5012
5013 /* a in units of 1/512 rounded down */
5014 /* q0 = (int)(a * 512.0); */
5015 q = float64_mul(float64_512, a, s);
5016 q_int = float64_to_int64_round_to_zero(q, s);
5017
5018 /* reciprocal root r */
5019 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
5020 q = int64_to_float64(q_int, s);
5021 q = float64_add(q, float64_half, s);
5022 q = float64_div(q, float64_512, s);
5023 q = float64_sqrt(q, s);
5024 q = float64_div(float64_one, q, s);
5025 } else {
5026 /* range 0.5 <= a < 1.0 */
5027
5028 /* a in units of 1/256 rounded down */
5029 /* q1 = (int)(a * 256.0); */
5030 q = float64_mul(float64_256, a, s);
5031 int64_t q_int = float64_to_int64_round_to_zero(q, s);
5032
5033 /* reciprocal root r */
5034 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
5035 q = int64_to_float64(q_int, s);
5036 q = float64_add(q, float64_half, s);
5037 q = float64_div(q, float64_256, s);
5038 q = float64_sqrt(q, s);
5039 q = float64_div(float64_one, q, s);
5040 }
5041 /* r in units of 1/256 rounded to nearest */
5042 /* s = (int)(256.0 * r + 0.5); */
5043
5044 q = float64_mul(q, float64_256,s );
5045 q = float64_add(q, float64_half, s);
5046 q_int = float64_to_int64_round_to_zero(q, s);
5047
5048 /* return (double)s / 256.0;*/
5049 return float64_div(int64_to_float64(q_int, s), float64_256, s);
5050 }
5051
5052 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
5053 {
5054 float_status *s = fpstp;
5055 float32 f32 = float32_squash_input_denormal(input, s);
5056 uint32_t val = float32_val(f32);
5057 uint32_t f32_sbit = 0x80000000 & val;
5058 int32_t f32_exp = extract32(val, 23, 8);
5059 uint32_t f32_frac = extract32(val, 0, 23);
5060 uint64_t f64_frac;
5061 uint64_t val64;
5062 int result_exp;
5063 float64 f64;
5064
5065 if (float32_is_any_nan(f32)) {
5066 float32 nan = f32;
5067 if (float32_is_signaling_nan(f32)) {
5068 float_raise(float_flag_invalid, s);
5069 nan = float32_maybe_silence_nan(f32);
5070 }
5071 if (s->default_nan_mode) {
5072 nan = float32_default_nan;
5073 }
5074 return nan;
5075 } else if (float32_is_zero(f32)) {
5076 float_raise(float_flag_divbyzero, s);
5077 return float32_set_sign(float32_infinity, float32_is_neg(f32));
5078 } else if (float32_is_neg(f32)) {
5079 float_raise(float_flag_invalid, s);
5080 return float32_default_nan;
5081 } else if (float32_is_infinity(f32)) {
5082 return float32_zero;
5083 }
5084
5085 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5086 * preserving the parity of the exponent. */
5087
5088 f64_frac = ((uint64_t) f32_frac) << 29;
5089 if (f32_exp == 0) {
5090 while (extract64(f64_frac, 51, 1) == 0) {
5091 f64_frac = f64_frac << 1;
5092 f32_exp = f32_exp-1;
5093 }
5094 f64_frac = extract64(f64_frac, 0, 51) << 1;
5095 }
5096
5097 if (extract64(f32_exp, 0, 1) == 0) {
5098 f64 = make_float64(((uint64_t) f32_sbit) << 32
5099 | (0x3feULL << 52)
5100 | f64_frac);
5101 } else {
5102 f64 = make_float64(((uint64_t) f32_sbit) << 32
5103 | (0x3fdULL << 52)
5104 | f64_frac);
5105 }
5106
5107 result_exp = (380 - f32_exp) / 2;
5108
5109 f64 = recip_sqrt_estimate(f64, s);
5110
5111 val64 = float64_val(f64);
5112
5113 val = ((result_exp & 0xff) << 23)
5114 | ((val64 >> 29) & 0x7fffff);
5115 return make_float32(val);
5116 }
5117
5118 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
5119 {
5120 float_status *s = fpstp;
5121 float64 f64 = float64_squash_input_denormal(input, s);
5122 uint64_t val = float64_val(f64);
5123 uint64_t f64_sbit = 0x8000000000000000ULL & val;
5124 int64_t f64_exp = extract64(val, 52, 11);
5125 uint64_t f64_frac = extract64(val, 0, 52);
5126 int64_t result_exp;
5127 uint64_t result_frac;
5128
5129 if (float64_is_any_nan(f64)) {
5130 float64 nan = f64;
5131 if (float64_is_signaling_nan(f64)) {
5132 float_raise(float_flag_invalid, s);
5133 nan = float64_maybe_silence_nan(f64);
5134 }
5135 if (s->default_nan_mode) {
5136 nan = float64_default_nan;
5137 }
5138 return nan;
5139 } else if (float64_is_zero(f64)) {
5140 float_raise(float_flag_divbyzero, s);
5141 return float64_set_sign(float64_infinity, float64_is_neg(f64));
5142 } else if (float64_is_neg(f64)) {
5143 float_raise(float_flag_invalid, s);
5144 return float64_default_nan;
5145 } else if (float64_is_infinity(f64)) {
5146 return float64_zero;
5147 }
5148
5149 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5150 * preserving the parity of the exponent. */
5151
5152 if (f64_exp == 0) {
5153 while (extract64(f64_frac, 51, 1) == 0) {
5154 f64_frac = f64_frac << 1;
5155 f64_exp = f64_exp - 1;
5156 }
5157 f64_frac = extract64(f64_frac, 0, 51) << 1;
5158 }
5159
5160 if (extract64(f64_exp, 0, 1) == 0) {
5161 f64 = make_float64(f64_sbit
5162 | (0x3feULL << 52)
5163 | f64_frac);
5164 } else {
5165 f64 = make_float64(f64_sbit
5166 | (0x3fdULL << 52)
5167 | f64_frac);
5168 }
5169
5170 result_exp = (3068 - f64_exp) / 2;
5171
5172 f64 = recip_sqrt_estimate(f64, s);
5173
5174 result_frac = extract64(float64_val(f64), 0, 52);
5175
5176 return make_float64(f64_sbit |
5177 ((result_exp & 0x7ff) << 52) |
5178 result_frac);
5179 }
5180
5181 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
5182 {
5183 float_status *s = fpstp;
5184 float64 f64;
5185
5186 if ((a & 0x80000000) == 0) {
5187 return 0xffffffff;
5188 }
5189
5190 f64 = make_float64((0x3feULL << 52)
5191 | ((int64_t)(a & 0x7fffffff) << 21));
5192
5193 f64 = recip_estimate(f64, s);
5194
5195 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5196 }
5197
5198 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
5199 {
5200 float_status *fpst = fpstp;
5201 float64 f64;
5202
5203 if ((a & 0xc0000000) == 0) {
5204 return 0xffffffff;
5205 }
5206
5207 if (a & 0x80000000) {
5208 f64 = make_float64((0x3feULL << 52)
5209 | ((uint64_t)(a & 0x7fffffff) << 21));
5210 } else { /* bits 31-30 == '01' */
5211 f64 = make_float64((0x3fdULL << 52)
5212 | ((uint64_t)(a & 0x3fffffff) << 22));
5213 }
5214
5215 f64 = recip_sqrt_estimate(f64, fpst);
5216
5217 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5218 }
5219
5220 /* VFPv4 fused multiply-accumulate */
5221 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
5222 {
5223 float_status *fpst = fpstp;
5224 return float32_muladd(a, b, c, 0, fpst);
5225 }
5226
5227 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
5228 {
5229 float_status *fpst = fpstp;
5230 return float64_muladd(a, b, c, 0, fpst);
5231 }
5232
5233 /* ARMv8 round to integral */
5234 float32 HELPER(rints_exact)(float32 x, void *fp_status)
5235 {
5236 return float32_round_to_int(x, fp_status);
5237 }
5238
5239 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
5240 {
5241 return float64_round_to_int(x, fp_status);
5242 }
5243
5244 float32 HELPER(rints)(float32 x, void *fp_status)
5245 {
5246 int old_flags = get_float_exception_flags(fp_status), new_flags;
5247 float32 ret;
5248
5249 ret = float32_round_to_int(x, fp_status);
5250
5251 /* Suppress any inexact exceptions the conversion produced */
5252 if (!(old_flags & float_flag_inexact)) {
5253 new_flags = get_float_exception_flags(fp_status);
5254 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5255 }
5256
5257 return ret;
5258 }
5259
5260 float64 HELPER(rintd)(float64 x, void *fp_status)
5261 {
5262 int old_flags = get_float_exception_flags(fp_status), new_flags;
5263 float64 ret;
5264
5265 ret = float64_round_to_int(x, fp_status);
5266
5267 new_flags = get_float_exception_flags(fp_status);
5268
5269 /* Suppress any inexact exceptions the conversion produced */
5270 if (!(old_flags & float_flag_inexact)) {
5271 new_flags = get_float_exception_flags(fp_status);
5272 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5273 }
5274
5275 return ret;
5276 }
5277
5278 /* Convert ARM rounding mode to softfloat */
5279 int arm_rmode_to_sf(int rmode)
5280 {
5281 switch (rmode) {
5282 case FPROUNDING_TIEAWAY:
5283 rmode = float_round_ties_away;
5284 break;
5285 case FPROUNDING_ODD:
5286 /* FIXME: add support for TIEAWAY and ODD */
5287 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
5288 rmode);
5289 case FPROUNDING_TIEEVEN:
5290 default:
5291 rmode = float_round_nearest_even;
5292 break;
5293 case FPROUNDING_POSINF:
5294 rmode = float_round_up;
5295 break;
5296 case FPROUNDING_NEGINF:
5297 rmode = float_round_down;
5298 break;
5299 case FPROUNDING_ZERO:
5300 rmode = float_round_to_zero;
5301 break;
5302 }
5303 return rmode;
5304 }
5305
5306 static void crc_init_buffer(uint8_t *buf, uint32_t val, uint32_t bytes)
5307 {
5308 memset(buf, 0, 4);
5309
5310 if (bytes == 1) {
5311 buf[0] = val & 0xff;
5312 } else if (bytes == 2) {
5313 buf[0] = val & 0xff;
5314 buf[1] = (val >> 8) & 0xff;
5315 } else {
5316 buf[0] = val & 0xff;
5317 buf[1] = (val >> 8) & 0xff;
5318 buf[2] = (val >> 16) & 0xff;
5319 buf[3] = (val >> 24) & 0xff;
5320 }
5321 }
5322
5323 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
5324 {
5325 uint8_t buf[4];
5326
5327 crc_init_buffer(buf, val, bytes);
5328
5329 /* zlib crc32 converts the accumulator and output to one's complement. */
5330 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
5331 }
5332
5333 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
5334 {
5335 uint8_t buf[4];
5336
5337 crc_init_buffer(buf, val, bytes);
5338
5339 /* Linux crc32c converts the output to one's complement. */
5340 return crc32c(acc, buf, bytes) ^ 0xffffffff;
5341 }
AR7 emulation for QEMU