include/hw/ppc/xive_regs.h

   1 /*
   2  * QEMU PowerPC XIVE internal structure definitions
   3  *
   4  *
   5  * The XIVE structures are accessed by the HW and their format is
   6  * architected to be big-endian. Some macros are provided to ease
   7  * access to the different fields.
   8  *
   9  *
  10  * Copyright (c) 2016-2018, IBM Corporation.
  11  *
  12  * This code is licensed under the GPL version 2 or later. See the
  13  * COPYING file in the top-level directory.
  14  */
  15
  16 #ifndef PPC_XIVE_REGS_H
  17 #define PPC_XIVE_REGS_H
  18
  19 #include "qemu/bswap.h"
  20 #include "qemu/host-utils.h"
  21
  22 /*
  23  * Interrupt source number encoding on PowerBUS
  24  */
  25 /*
  26  * Trigger data definition
  27  *
  28  * The trigger definition is used for triggers both for HW source
  29  * interrupts (PHB, PSI), as well as for rerouting interrupts between
  30  * Interrupt Controller.
  31  *
  32  * HW source controllers set bit0 of word0 to ‘0’ as they provide EAS
  33  * information (EAS block + EAS index) in the 8 byte data and not END
  34  * information, which is use for rerouting interrupts.
  35  *
  36  * bit1 of word0 to ‘1’ signals that the state bit check has been
  37  * performed.
  38  */
  39 #define XIVE_TRIGGER_END        PPC_BIT(0)
  40 #define XIVE_TRIGGER_PQ         PPC_BIT(1)
  41
  42 /*
  43  * QEMU macros to manipulate the trigger payload in native endian
  44  */
  45 #define XIVE_EAS_BLOCK(n)       (((n) >> 28) & 0xf)
  46 #define XIVE_EAS_INDEX(n)       ((n) & 0x0fffffff)
  47 #define XIVE_EAS(blk, idx)      ((uint32_t)(blk) << 28 | (idx))
  48
  49 #define TM_SHIFT                16
  50
  51 /* TM register offsets */
  52 #define TM_QW0_USER             0x000 /* All rings */
  53 #define TM_QW1_OS               0x010 /* Ring 0..2 */
  54 #define TM_QW2_HV_POOL          0x020 /* Ring 0..1 */
  55 #define TM_QW3_HV_PHYS          0x030 /* Ring 0..1 */
  56
  57 /* Byte offsets inside a QW             QW0 QW1 QW2 QW3 */
  58 #define TM_NSR                  0x0  /*  +   +   -   +  */
  59 #define TM_CPPR                 0x1  /*  -   +   -   +  */
  60 #define TM_IPB                  0x2  /*  -   +   +   +  */
  61 #define TM_LSMFB                0x3  /*  -   +   +   +  */
  62 #define TM_ACK_CNT              0x4  /*  -   +   -   -  */
  63 #define TM_INC                  0x5  /*  -   +   -   +  */
  64 #define TM_AGE                  0x6  /*  -   +   -   +  */
  65 #define TM_PIPR                 0x7  /*  -   +   -   +  */
  66
  67 #define TM_WORD0                0x0
  68 #define TM_WORD1                0x4
  69
  70 /*
  71  * QW word 2 contains the valid bit at the top and other fields
  72  * depending on the QW.
  73  */
  74 #define TM_WORD2                0x8
  75 #define   TM_QW0W2_VU           PPC_BIT32(0)
  76 #define   TM_QW0W2_LOGIC_SERV   PPC_BITMASK32(1, 31) /* XX 2,31 ? */
  77 #define   TM_QW1W2_VO           PPC_BIT32(0)
  78 #define   TM_QW1W2_OS_CAM       PPC_BITMASK32(8, 31)
  79 #define   TM_QW2W2_VP           PPC_BIT32(0)
  80 #define   TM_QW2W2_POOL_CAM     PPC_BITMASK32(8, 31)
  81 #define   TM_QW3W2_VT           PPC_BIT32(0)
  82 #define   TM_QW3W2_LP           PPC_BIT32(6)
  83 #define   TM_QW3W2_LE           PPC_BIT32(7)
  84 #define   TM_QW3W2_T            PPC_BIT32(31)
  85
  86 /*
  87  * In addition to normal loads to "peek" and writes (only when invalid)
  88  * using 4 and 8 bytes accesses, the above registers support these
  89  * "special" byte operations:
  90  *
  91  *   - Byte load from QW0[NSR] - User level NSR (EBB)
  92  *   - Byte store to QW0[NSR] - User level NSR (EBB)
  93  *   - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access
  94  *   - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0
  95  *                                    otherwise VT||0000000
  96  *   - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present)
  97  *
  98  * Then we have all these "special" CI ops at these offset that trigger
  99  * all sorts of side effects:
 100  */
 101 #define TM_SPC_ACK_EBB          0x800   /* Load8 ack EBB to reg*/
 102 #define TM_SPC_ACK_OS_REG       0x810   /* Load16 ack OS irq to reg */
 103 #define TM_SPC_PUSH_USR_CTX     0x808   /* Store32 Push/Validate user context */
 104 #define TM_SPC_PULL_USR_CTX     0x808   /* Load32 Pull/Invalidate user
 105                                          * context */
 106 #define TM_SPC_SET_OS_PENDING   0x812   /* Store8 Set OS irq pending bit */
 107 #define TM_SPC_PULL_OS_CTX      0x818   /* Load32/Load64 Pull/Invalidate OS
 108                                          * context to reg */
 109 #define TM_SPC_PULL_POOL_CTX    0x828   /* Load32/Load64 Pull/Invalidate Pool
 110                                          * context to reg*/
 111 #define TM_SPC_ACK_HV_REG       0x830   /* Load16 ack HV irq to reg */
 112 #define TM_SPC_PULL_USR_CTX_OL  0xc08   /* Store8 Pull/Inval usr ctx to odd
 113                                          * line */
 114 #define TM_SPC_ACK_OS_EL        0xc10   /* Store8 ack OS irq to even line */
 115 #define TM_SPC_ACK_HV_POOL_EL   0xc20   /* Store8 ack HV evt pool to even
 116                                          * line */
 117 #define TM_SPC_ACK_HV_EL        0xc30   /* Store8 ack HV irq to even line */
 118 /* XXX more... */
 119
 120 /* NSR fields for the various QW ack types */
 121 #define TM_QW0_NSR_EB           PPC_BIT8(0)
 122 #define TM_QW1_NSR_EO           PPC_BIT8(0)
 123 #define TM_QW3_NSR_HE           PPC_BITMASK8(0, 1)
 124 #define  TM_QW3_NSR_HE_NONE     0
 125 #define  TM_QW3_NSR_HE_POOL     1
 126 #define  TM_QW3_NSR_HE_PHYS     2
 127 #define  TM_QW3_NSR_HE_LSI      3
 128 #define TM_QW3_NSR_I            PPC_BIT8(2)
 129 #define TM_QW3_NSR_GRP_LVL      PPC_BIT8(3, 7)
 130
 131 /*
 132  * EAS (Event Assignment Structure)
 133  *
 134  * One per interrupt source. Targets an interrupt to a given Event
 135  * Notification Descriptor (END) and provides the corresponding
 136  * logical interrupt number (END data)
 137  */
 138 typedef struct XiveEAS {
 139         /*
 140          * Use a single 64-bit definition to make it easier to perform
 141          * atomic updates
 142          */
 143         uint64_t        w;
 144 #define EAS_VALID       PPC_BIT(0)
 145 #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
 146 #define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
 147 #define EAS_MASKED      PPC_BIT(32)              /* Masked */
 148 #define EAS_END_DATA    PPC_BITMASK(33, 63)      /* Data written to the END */
 149 } XiveEAS;
 150
 151 #define xive_eas_is_valid(eas)   (be64_to_cpu((eas)->w) & EAS_VALID)
 152 #define xive_eas_is_masked(eas)  (be64_to_cpu((eas)->w) & EAS_MASKED)
 153
 154 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon);
 155
 156 static inline uint64_t xive_get_field64(uint64_t mask, uint64_t word)
 157 {
 158     return (be64_to_cpu(word) & mask) >> ctz64(mask);
 159 }
 160
 161 static inline uint64_t xive_set_field64(uint64_t mask, uint64_t word,
 162                                         uint64_t value)
 163 {
 164     uint64_t tmp =
 165         (be64_to_cpu(word) & ~mask) | ((value << ctz64(mask)) & mask);
 166     return cpu_to_be64(tmp);
 167 }
 168
 169 static inline uint32_t xive_get_field32(uint32_t mask, uint32_t word)
 170 {
 171     return (be32_to_cpu(word) & mask) >> ctz32(mask);
 172 }
 173
 174 static inline uint32_t xive_set_field32(uint32_t mask, uint32_t word,
 175                                         uint32_t value)
 176 {
 177     uint32_t tmp =
 178         (be32_to_cpu(word) & ~mask) | ((value << ctz32(mask)) & mask);
 179     return cpu_to_be32(tmp);
 180 }
 181
 182 /* Event Notification Descriptor (END) */
 183 typedef struct XiveEND {
 184         uint32_t        w0;
 185 #define END_W0_VALID             PPC_BIT32(0) /* "v" bit */
 186 #define END_W0_ENQUEUE           PPC_BIT32(1) /* "q" bit */
 187 #define END_W0_UCOND_NOTIFY      PPC_BIT32(2) /* "n" bit */
 188 #define END_W0_BACKLOG           PPC_BIT32(3) /* "b" bit */
 189 #define END_W0_PRECL_ESC_CTL     PPC_BIT32(4) /* "p" bit */
 190 #define END_W0_ESCALATE_CTL      PPC_BIT32(5) /* "e" bit */
 191 #define END_W0_UNCOND_ESCALATE   PPC_BIT32(6) /* "u" bit - DD2.0 */
 192 #define END_W0_SILENT_ESCALATE   PPC_BIT32(7) /* "s" bit - DD2.0 */
 193 #define END_W0_QSIZE             PPC_BITMASK32(12, 15)
 194 #define END_W0_SW0               PPC_BIT32(16)
 195 #define END_W0_FIRMWARE          END_W0_SW0 /* Owned by FW */
 196 #define END_QSIZE_4K             0
 197 #define END_QSIZE_64K            4
 198 #define END_W0_HWDEP             PPC_BITMASK32(24, 31)
 199         uint32_t        w1;
 200 #define END_W1_ESn               PPC_BITMASK32(0, 1)
 201 #define END_W1_ESn_P             PPC_BIT32(0)
 202 #define END_W1_ESn_Q             PPC_BIT32(1)
 203 #define END_W1_ESe               PPC_BITMASK32(2, 3)
 204 #define END_W1_ESe_P             PPC_BIT32(2)
 205 #define END_W1_ESe_Q             PPC_BIT32(3)
 206 #define END_W1_GENERATION        PPC_BIT32(9)
 207 #define END_W1_PAGE_OFF          PPC_BITMASK32(10, 31)
 208         uint32_t        w2;
 209 #define END_W2_MIGRATION_REG     PPC_BITMASK32(0, 3)
 210 #define END_W2_OP_DESC_HI        PPC_BITMASK32(4, 31)
 211         uint32_t        w3;
 212 #define END_W3_OP_DESC_LO        PPC_BITMASK32(0, 31)
 213         uint32_t        w4;
 214 #define END_W4_ESC_END_BLOCK     PPC_BITMASK32(4, 7)
 215 #define END_W4_ESC_END_INDEX     PPC_BITMASK32(8, 31)
 216         uint32_t        w5;
 217 #define END_W5_ESC_END_DATA      PPC_BITMASK32(1, 31)
 218         uint32_t        w6;
 219 #define END_W6_FORMAT_BIT        PPC_BIT32(8)
 220 #define END_W6_NVT_BLOCK         PPC_BITMASK32(9, 12)
 221 #define END_W6_NVT_INDEX         PPC_BITMASK32(13, 31)
 222         uint32_t        w7;
 223 #define END_W7_F0_IGNORE         PPC_BIT32(0)
 224 #define END_W7_F0_BLK_GROUPING   PPC_BIT32(1)
 225 #define END_W7_F0_PRIORITY       PPC_BITMASK32(8, 15)
 226 #define END_W7_F1_WAKEZ          PPC_BIT32(0)
 227 #define END_W7_F1_LOG_SERVER_ID  PPC_BITMASK32(1, 31)
 228 } XiveEND;
 229
 230 #define xive_end_is_valid(end)    (be32_to_cpu((end)->w0) & END_W0_VALID)
 231 #define xive_end_is_enqueue(end)  (be32_to_cpu((end)->w0) & END_W0_ENQUEUE)
 232 #define xive_end_is_notify(end)   (be32_to_cpu((end)->w0) & END_W0_UCOND_NOTIFY)
 233 #define xive_end_is_backlog(end)  (be32_to_cpu((end)->w0) & END_W0_BACKLOG)
 234 #define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALATE_CTL)
 235 #define xive_end_is_uncond_escalation(end)              \
 236     (be32_to_cpu((end)->w0) & END_W0_UNCOND_ESCALATE)
 237 #define xive_end_is_silent_escalation(end)              \
 238     (be32_to_cpu((end)->w0) & END_W0_SILENT_ESCALATE)
 239
 240 static inline uint64_t xive_end_qaddr(XiveEND *end)
 241 {
 242     return ((uint64_t) be32_to_cpu(end->w2) & 0x0fffffff) << 32 |
 243         be32_to_cpu(end->w3);
 244 }
 245
 246 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
 247 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon);
 248 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
 249
 250 /* Notification Virtual Target (NVT) */
 251 typedef struct XiveNVT {
 252         uint32_t        w0;
 253 #define NVT_W0_VALID             PPC_BIT32(0)
 254         uint32_t        w1;
 255         uint32_t        w2;
 256         uint32_t        w3;
 257         uint32_t        w4;
 258         uint32_t        w5;
 259         uint32_t        w6;
 260         uint32_t        w7;
 261         uint32_t        w8;
 262 #define NVT_W8_GRP_VALID         PPC_BIT32(0)
 263         uint32_t        w9;
 264         uint32_t        wa;
 265         uint32_t        wb;
 266         uint32_t        wc;
 267         uint32_t        wd;
 268         uint32_t        we;
 269         uint32_t        wf;
 270 } XiveNVT;
 271
 272 #define xive_nvt_is_valid(nvt)    (be32_to_cpu((nvt)->w0) & NVT_W0_VALID)
 273
 274 #endif /* PPC_XIVE_REGS_H */