target-moxie/translate.c

   1 /*
   2  *  Moxie emulation for qemu: main translation routines.
   3  *
   4  *  Copyright (c) 2009, 2013 Anthony Green
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public License
   8  * as published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /* For information on the Moxie architecture, see
  21  *    http://moxielogic.org/wiki
  22  */
  23
  24 #include "qemu/osdep.h"
  25
  26 #include "cpu.h"
  27 #include "exec/exec-all.h"
  28 #include "disas/disas.h"
  29 #include "tcg-op.h"
  30 #include "exec/cpu_ldst.h"
  31
  32 #include "exec/helper-proto.h"
  33 #include "exec/helper-gen.h"
  34
  35 /* This is the state at translation time.  */
  36 typedef struct DisasContext {
  37     struct TranslationBlock *tb;
  38     target_ulong pc, saved_pc;
  39     uint32_t opcode;
  40     uint32_t fp_status;
  41     /* Routine used to access memory */
  42     int memidx;
  43     int bstate;
  44     target_ulong btarget;
  45     int singlestep_enabled;
  46 } DisasContext;
  47
  48 enum {
  49     BS_NONE     = 0, /* We go out of the TB without reaching a branch or an
  50                       * exception condition */
  51     BS_STOP     = 1, /* We want to stop translation for any reason */
  52     BS_BRANCH   = 2, /* We reached a branch condition     */
  53     BS_EXCP     = 3, /* We reached an exception condition */
  54 };
  55
  56 static TCGv cpu_pc;
  57 static TCGv cpu_gregs[16];
  58 static TCGv_ptr cpu_env;
  59 static TCGv cc_a, cc_b;
  60
  61 #include "exec/gen-icount.h"
  62
  63 #define REG(x) (cpu_gregs[x])
  64
  65 /* Extract the signed 10-bit offset from a 16-bit branch
  66    instruction.  */
  67 static int extract_branch_offset(int opcode)
  68 {
  69   return (((signed short)((opcode & ((1 << 10) - 1)) << 6)) >> 6) << 1;
  70 }
  71
  72 void moxie_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
  73                           int flags)
  74 {
  75     MoxieCPU *cpu = MOXIE_CPU(cs);
  76     CPUMoxieState *env = &cpu->env;
  77     int i;
  78     cpu_fprintf(f, "pc=0x%08x\n", env->pc);
  79     cpu_fprintf(f, "$fp=0x%08x $sp=0x%08x $r0=0x%08x $r1=0x%08x\n",
  80                 env->gregs[0], env->gregs[1], env->gregs[2], env->gregs[3]);
  81     for (i = 4; i < 16; i += 4) {
  82         cpu_fprintf(f, "$r%d=0x%08x $r%d=0x%08x $r%d=0x%08x $r%d=0x%08x\n",
  83                     i-2, env->gregs[i], i-1, env->gregs[i + 1],
  84                     i, env->gregs[i + 2], i+1, env->gregs[i + 3]);
  85     }
  86     for (i = 4; i < 16; i += 4) {
  87         cpu_fprintf(f, "sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x\n",
  88                     i-2, env->sregs[i], i-1, env->sregs[i + 1],
  89                     i, env->sregs[i + 2], i+1, env->sregs[i + 3]);
  90     }
  91 }
  92
  93 void moxie_translate_init(void)
  94 {
  95     int i;
  96     static int done_init;
  97     static const char * const gregnames[16] = {
  98         "$fp", "$sp", "$r0", "$r1",
  99         "$r2", "$r3", "$r4", "$r5",
 100         "$r6", "$r7", "$r8", "$r9",
 101         "$r10", "$r11", "$r12", "$r13"
 102     };
 103
 104     if (done_init) {
 105         return;
 106     }
 107     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
 108     cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
 109                                     offsetof(CPUMoxieState, pc), "$pc");
 110     for (i = 0; i < 16; i++)
 111         cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
 112                                               offsetof(CPUMoxieState, gregs[i]),
 113                                               gregnames[i]);
 114
 115     cc_a = tcg_global_mem_new_i32(TCG_AREG0,
 116                                   offsetof(CPUMoxieState, cc_a), "cc_a");
 117     cc_b = tcg_global_mem_new_i32(TCG_AREG0,
 118                                   offsetof(CPUMoxieState, cc_b), "cc_b");
 119
 120     done_init = 1;
 121 }
 122
 123 static inline void gen_goto_tb(CPUMoxieState *env, DisasContext *ctx,
 124                                int n, target_ulong dest)
 125 {
 126     TranslationBlock *tb;
 127     tb = ctx->tb;
 128
 129     if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
 130         !ctx->singlestep_enabled) {
 131         tcg_gen_goto_tb(n);
 132         tcg_gen_movi_i32(cpu_pc, dest);
 133         tcg_gen_exit_tb((uintptr_t)tb + n);
 134     } else {
 135         tcg_gen_movi_i32(cpu_pc, dest);
 136         if (ctx->singlestep_enabled) {
 137             gen_helper_debug(cpu_env);
 138         }
 139         tcg_gen_exit_tb(0);
 140     }
 141 }
 142
 143 static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
 144 {
 145     CPUMoxieState *env = &cpu->env;
 146
 147     /* Local cache for the instruction opcode.  */
 148     int opcode;
 149     /* Set the default instruction length.  */
 150     int length = 2;
 151
 152     /* Examine the 16-bit opcode.  */
 153     opcode = ctx->opcode;
 154
 155     /* Decode instruction.  */
 156     if (opcode & (1 << 15)) {
 157         if (opcode & (1 << 14)) {
 158             /* This is a Form 3 instruction.  */
 159             int inst = (opcode >> 10 & 0xf);
 160
 161 #define BRANCH(cond)                                                         \
 162     do {                                                                     \
 163         TCGLabel *l1 = gen_new_label();                                      \
 164         tcg_gen_brcond_i32(cond, cc_a, cc_b, l1);                            \
 165         gen_goto_tb(env, ctx, 1, ctx->pc+2);                                 \
 166         gen_set_label(l1);                                                   \
 167         gen_goto_tb(env, ctx, 0, extract_branch_offset(opcode) + ctx->pc+2); \
 168         ctx->bstate = BS_BRANCH;                                             \
 169     } while (0)
 170
 171             switch (inst) {
 172             case 0x00: /* beq */
 173                 BRANCH(TCG_COND_EQ);
 174                 break;
 175             case 0x01: /* bne */
 176                 BRANCH(TCG_COND_NE);
 177                 break;
 178             case 0x02: /* blt */
 179                 BRANCH(TCG_COND_LT);
 180                 break;
 181             case 0x03: /* bgt */
 182                 BRANCH(TCG_COND_GT);
 183                 break;
 184             case 0x04: /* bltu */
 185                 BRANCH(TCG_COND_LTU);
 186                 break;
 187             case 0x05: /* bgtu */
 188                 BRANCH(TCG_COND_GTU);
 189                 break;
 190             case 0x06: /* bge */
 191                 BRANCH(TCG_COND_GE);
 192                 break;
 193             case 0x07: /* ble */
 194                 BRANCH(TCG_COND_LE);
 195                 break;
 196             case 0x08: /* bgeu */
 197                 BRANCH(TCG_COND_GEU);
 198                 break;
 199             case 0x09: /* bleu */
 200                 BRANCH(TCG_COND_LEU);
 201                 break;
 202             default:
 203                 {
 204                     TCGv temp = tcg_temp_new_i32();
 205                     tcg_gen_movi_i32(cpu_pc, ctx->pc);
 206                     tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
 207                     gen_helper_raise_exception(cpu_env, temp);
 208                     tcg_temp_free_i32(temp);
 209                 }
 210                 break;
 211             }
 212         } else {
 213             /* This is a Form 2 instruction.  */
 214             int inst = (opcode >> 12 & 0x3);
 215             switch (inst) {
 216             case 0x00: /* inc */
 217                 {
 218                     int a = (opcode >> 8) & 0xf;
 219                     unsigned int v = (opcode & 0xff);
 220                     tcg_gen_addi_i32(REG(a), REG(a), v);
 221                 }
 222                 break;
 223             case 0x01: /* dec */
 224                 {
 225                     int a = (opcode >> 8) & 0xf;
 226                     unsigned int v = (opcode & 0xff);
 227                     tcg_gen_subi_i32(REG(a), REG(a), v);
 228                 }
 229                 break;
 230             case 0x02: /* gsr */
 231                 {
 232                     int a = (opcode >> 8) & 0xf;
 233                     unsigned v = (opcode & 0xff);
 234                     tcg_gen_ld_i32(REG(a), cpu_env,
 235                                    offsetof(CPUMoxieState, sregs[v]));
 236                 }
 237                 break;
 238             case 0x03: /* ssr */
 239                 {
 240                     int a = (opcode >> 8) & 0xf;
 241                     unsigned v = (opcode & 0xff);
 242                     tcg_gen_st_i32(REG(a), cpu_env,
 243                                    offsetof(CPUMoxieState, sregs[v]));
 244                 }
 245                 break;
 246             default:
 247                 {
 248                     TCGv temp = tcg_temp_new_i32();
 249                     tcg_gen_movi_i32(cpu_pc, ctx->pc);
 250                     tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
 251                     gen_helper_raise_exception(cpu_env, temp);
 252                     tcg_temp_free_i32(temp);
 253                 }
 254                 break;
 255             }
 256         }
 257     } else {
 258         /* This is a Form 1 instruction.  */
 259         int inst = opcode >> 8;
 260         switch (inst) {
 261         case 0x00: /* nop */
 262             break;
 263         case 0x01: /* ldi.l (immediate) */
 264             {
 265                 int reg = (opcode >> 4) & 0xf;
 266                 int val = cpu_ldl_code(env, ctx->pc+2);
 267                 tcg_gen_movi_i32(REG(reg), val);
 268                 length = 6;
 269             }
 270             break;
 271         case 0x02: /* mov (register-to-register) */
 272             {
 273                 int dest  = (opcode >> 4) & 0xf;
 274                 int src = opcode & 0xf;
 275                 tcg_gen_mov_i32(REG(dest), REG(src));
 276             }
 277             break;
 278         case 0x03: /* jsra */
 279             {
 280                 TCGv t1 = tcg_temp_new_i32();
 281                 TCGv t2 = tcg_temp_new_i32();
 282
 283                 tcg_gen_movi_i32(t1, ctx->pc + 6);
 284
 285                 /* Make space for the static chain and return address.  */
 286                 tcg_gen_subi_i32(t2, REG(1), 8);
 287                 tcg_gen_mov_i32(REG(1), t2);
 288                 tcg_gen_qemu_st32(t1, REG(1), ctx->memidx);
 289
 290                 /* Push the current frame pointer.  */
 291                 tcg_gen_subi_i32(t2, REG(1), 4);
 292                 tcg_gen_mov_i32(REG(1), t2);
 293                 tcg_gen_qemu_st32(REG(0), REG(1), ctx->memidx);
 294
 295                 /* Set the pc and $fp.  */
 296                 tcg_gen_mov_i32(REG(0), REG(1));
 297
 298                 gen_goto_tb(env, ctx, 0, cpu_ldl_code(env, ctx->pc+2));
 299
 300                 tcg_temp_free_i32(t1);
 301                 tcg_temp_free_i32(t2);
 302
 303                 ctx->bstate = BS_BRANCH;
 304                 length = 6;
 305             }
 306             break;
 307         case 0x04: /* ret */
 308             {
 309                 TCGv t1 = tcg_temp_new_i32();
 310
 311                 /* The new $sp is the old $fp.  */
 312                 tcg_gen_mov_i32(REG(1), REG(0));
 313
 314                 /* Pop the frame pointer.  */
 315                 tcg_gen_qemu_ld32u(REG(0), REG(1), ctx->memidx);
 316                 tcg_gen_addi_i32(t1, REG(1), 4);
 317                 tcg_gen_mov_i32(REG(1), t1);
 318
 319
 320                 /* Pop the return address and skip over the static chain
 321                    slot.  */
 322                 tcg_gen_qemu_ld32u(cpu_pc, REG(1), ctx->memidx);
 323                 tcg_gen_addi_i32(t1, REG(1), 8);
 324                 tcg_gen_mov_i32(REG(1), t1);
 325
 326                 tcg_temp_free_i32(t1);
 327
 328                 /* Jump... */
 329                 tcg_gen_exit_tb(0);
 330
 331                 ctx->bstate = BS_BRANCH;
 332             }
 333             break;
 334         case 0x05: /* add.l */
 335             {
 336                 int a = (opcode >> 4) & 0xf;
 337                 int b = opcode & 0xf;
 338
 339                 tcg_gen_add_i32(REG(a), REG(a), REG(b));
 340             }
 341             break;
 342         case 0x06: /* push */
 343             {
 344                 int a = (opcode >> 4) & 0xf;
 345                 int b = opcode & 0xf;
 346
 347                 TCGv t1 = tcg_temp_new_i32();
 348                 tcg_gen_subi_i32(t1, REG(a), 4);
 349                 tcg_gen_mov_i32(REG(a), t1);
 350                 tcg_gen_qemu_st32(REG(b), REG(a), ctx->memidx);
 351                 tcg_temp_free_i32(t1);
 352             }
 353             break;
 354         case 0x07: /* pop */
 355             {
 356                 int a = (opcode >> 4) & 0xf;
 357                 int b = opcode & 0xf;
 358                 TCGv t1 = tcg_temp_new_i32();
 359
 360                 tcg_gen_qemu_ld32u(REG(b), REG(a), ctx->memidx);
 361                 tcg_gen_addi_i32(t1, REG(a), 4);
 362                 tcg_gen_mov_i32(REG(a), t1);
 363                 tcg_temp_free_i32(t1);
 364             }
 365             break;
 366         case 0x08: /* lda.l */
 367             {
 368                 int reg = (opcode >> 4) & 0xf;
 369
 370                 TCGv ptr = tcg_temp_new_i32();
 371                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 372                 tcg_gen_qemu_ld32u(REG(reg), ptr, ctx->memidx);
 373                 tcg_temp_free_i32(ptr);
 374
 375                 length = 6;
 376             }
 377             break;
 378         case 0x09: /* sta.l */
 379             {
 380                 int val = (opcode >> 4) & 0xf;
 381
 382                 TCGv ptr = tcg_temp_new_i32();
 383                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 384                 tcg_gen_qemu_st32(REG(val), ptr, ctx->memidx);
 385                 tcg_temp_free_i32(ptr);
 386
 387                 length = 6;
 388             }
 389             break;
 390         case 0x0a: /* ld.l (register indirect) */
 391             {
 392                 int src  = opcode & 0xf;
 393                 int dest = (opcode >> 4) & 0xf;
 394
 395                 tcg_gen_qemu_ld32u(REG(dest), REG(src), ctx->memidx);
 396             }
 397             break;
 398         case 0x0b: /* st.l */
 399             {
 400                 int dest = (opcode >> 4) & 0xf;
 401                 int val  = opcode & 0xf;
 402
 403                 tcg_gen_qemu_st32(REG(val), REG(dest), ctx->memidx);
 404             }
 405             break;
 406         case 0x0c: /* ldo.l */
 407             {
 408                 int a = (opcode >> 4) & 0xf;
 409                 int b = opcode & 0xf;
 410
 411                 TCGv t1 = tcg_temp_new_i32();
 412                 TCGv t2 = tcg_temp_new_i32();
 413                 tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
 414                 tcg_gen_qemu_ld32u(t2, t1, ctx->memidx);
 415                 tcg_gen_mov_i32(REG(a), t2);
 416
 417                 tcg_temp_free_i32(t1);
 418                 tcg_temp_free_i32(t2);
 419
 420                 length = 6;
 421             }
 422             break;
 423         case 0x0d: /* sto.l */
 424             {
 425                 int a = (opcode >> 4) & 0xf;
 426                 int b = opcode & 0xf;
 427
 428                 TCGv t1 = tcg_temp_new_i32();
 429                 TCGv t2 = tcg_temp_new_i32();
 430                 tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
 431                 tcg_gen_qemu_st32(REG(b), t1, ctx->memidx);
 432
 433                 tcg_temp_free_i32(t1);
 434                 tcg_temp_free_i32(t2);
 435
 436                 length = 6;
 437             }
 438             break;
 439         case 0x0e: /* cmp */
 440             {
 441                 int a  = (opcode >> 4) & 0xf;
 442                 int b  = opcode & 0xf;
 443
 444                 tcg_gen_mov_i32(cc_a, REG(a));
 445                 tcg_gen_mov_i32(cc_b, REG(b));
 446             }
 447             break;
 448         case 0x19: /* jsr */
 449             {
 450                 int fnreg = (opcode >> 4) & 0xf;
 451
 452                 /* Load the stack pointer into T0.  */
 453                 TCGv t1 = tcg_temp_new_i32();
 454                 TCGv t2 = tcg_temp_new_i32();
 455
 456                 tcg_gen_movi_i32(t1, ctx->pc+2);
 457
 458                 /* Make space for the static chain and return address.  */
 459                 tcg_gen_subi_i32(t2, REG(1), 8);
 460                 tcg_gen_mov_i32(REG(1), t2);
 461                 tcg_gen_qemu_st32(t1, REG(1), ctx->memidx);
 462
 463                 /* Push the current frame pointer.  */
 464                 tcg_gen_subi_i32(t2, REG(1), 4);
 465                 tcg_gen_mov_i32(REG(1), t2);
 466                 tcg_gen_qemu_st32(REG(0), REG(1), ctx->memidx);
 467
 468                 /* Set the pc and $fp.  */
 469                 tcg_gen_mov_i32(REG(0), REG(1));
 470                 tcg_gen_mov_i32(cpu_pc, REG(fnreg));
 471                 tcg_temp_free_i32(t1);
 472                 tcg_temp_free_i32(t2);
 473                 tcg_gen_exit_tb(0);
 474                 ctx->bstate = BS_BRANCH;
 475             }
 476             break;
 477         case 0x1a: /* jmpa */
 478             {
 479                 tcg_gen_movi_i32(cpu_pc, cpu_ldl_code(env, ctx->pc+2));
 480                 tcg_gen_exit_tb(0);
 481                 ctx->bstate = BS_BRANCH;
 482                 length = 6;
 483             }
 484             break;
 485         case 0x1b: /* ldi.b (immediate) */
 486             {
 487                 int reg = (opcode >> 4) & 0xf;
 488                 int val = cpu_ldl_code(env, ctx->pc+2);
 489                 tcg_gen_movi_i32(REG(reg), val);
 490                 length = 6;
 491             }
 492             break;
 493         case 0x1c: /* ld.b (register indirect) */
 494             {
 495                 int src  = opcode & 0xf;
 496                 int dest = (opcode >> 4) & 0xf;
 497
 498                 tcg_gen_qemu_ld8u(REG(dest), REG(src), ctx->memidx);
 499             }
 500             break;
 501         case 0x1d: /* lda.b */
 502             {
 503                 int reg = (opcode >> 4) & 0xf;
 504
 505                 TCGv ptr = tcg_temp_new_i32();
 506                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 507                 tcg_gen_qemu_ld8u(REG(reg), ptr, ctx->memidx);
 508                 tcg_temp_free_i32(ptr);
 509
 510                 length = 6;
 511             }
 512             break;
 513         case 0x1e: /* st.b */
 514             {
 515                 int dest = (opcode >> 4) & 0xf;
 516                 int val  = opcode & 0xf;
 517
 518                 tcg_gen_qemu_st8(REG(val), REG(dest), ctx->memidx);
 519             }
 520             break;
 521         case 0x1f: /* sta.b */
 522             {
 523                 int val = (opcode >> 4) & 0xf;
 524
 525                 TCGv ptr = tcg_temp_new_i32();
 526                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 527                 tcg_gen_qemu_st8(REG(val), ptr, ctx->memidx);
 528                 tcg_temp_free_i32(ptr);
 529
 530                 length = 6;
 531             }
 532             break;
 533         case 0x20: /* ldi.s (immediate) */
 534             {
 535                 int reg = (opcode >> 4) & 0xf;
 536                 int val = cpu_ldl_code(env, ctx->pc+2);
 537                 tcg_gen_movi_i32(REG(reg), val);
 538                 length = 6;
 539             }
 540             break;
 541         case 0x21: /* ld.s (register indirect) */
 542             {
 543                 int src  = opcode & 0xf;
 544                 int dest = (opcode >> 4) & 0xf;
 545
 546                 tcg_gen_qemu_ld16u(REG(dest), REG(src), ctx->memidx);
 547             }
 548             break;
 549         case 0x22: /* lda.s */
 550             {
 551                 int reg = (opcode >> 4) & 0xf;
 552
 553                 TCGv ptr = tcg_temp_new_i32();
 554                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 555                 tcg_gen_qemu_ld16u(REG(reg), ptr, ctx->memidx);
 556                 tcg_temp_free_i32(ptr);
 557
 558                 length = 6;
 559             }
 560             break;
 561         case 0x23: /* st.s */
 562             {
 563                 int dest = (opcode >> 4) & 0xf;
 564                 int val  = opcode & 0xf;
 565
 566                 tcg_gen_qemu_st16(REG(val), REG(dest), ctx->memidx);
 567             }
 568             break;
 569         case 0x24: /* sta.s */
 570             {
 571                 int val = (opcode >> 4) & 0xf;
 572
 573                 TCGv ptr = tcg_temp_new_i32();
 574                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 575                 tcg_gen_qemu_st16(REG(val), ptr, ctx->memidx);
 576                 tcg_temp_free_i32(ptr);
 577
 578                 length = 6;
 579             }
 580             break;
 581         case 0x25: /* jmp */
 582             {
 583                 int reg = (opcode >> 4) & 0xf;
 584                 tcg_gen_mov_i32(cpu_pc, REG(reg));
 585                 tcg_gen_exit_tb(0);
 586                 ctx->bstate = BS_BRANCH;
 587             }
 588             break;
 589         case 0x26: /* and */
 590             {
 591                 int a = (opcode >> 4) & 0xf;
 592                 int b = opcode & 0xf;
 593
 594                 tcg_gen_and_i32(REG(a), REG(a), REG(b));
 595             }
 596             break;
 597         case 0x27: /* lshr */
 598             {
 599                 int a = (opcode >> 4) & 0xf;
 600                 int b = opcode & 0xf;
 601
 602                 TCGv sv = tcg_temp_new_i32();
 603                 tcg_gen_andi_i32(sv, REG(b), 0x1f);
 604                 tcg_gen_shr_i32(REG(a), REG(a), sv);
 605                 tcg_temp_free_i32(sv);
 606             }
 607             break;
 608         case 0x28: /* ashl */
 609             {
 610                 int a = (opcode >> 4) & 0xf;
 611                 int b = opcode & 0xf;
 612
 613                 TCGv sv = tcg_temp_new_i32();
 614                 tcg_gen_andi_i32(sv, REG(b), 0x1f);
 615                 tcg_gen_shl_i32(REG(a), REG(a), sv);
 616                 tcg_temp_free_i32(sv);
 617             }
 618             break;
 619         case 0x29: /* sub.l */
 620             {
 621                 int a = (opcode >> 4) & 0xf;
 622                 int b = opcode & 0xf;
 623
 624                 tcg_gen_sub_i32(REG(a), REG(a), REG(b));
 625             }
 626             break;
 627         case 0x2a: /* neg */
 628             {
 629                 int a = (opcode >> 4) & 0xf;
 630                 int b = opcode & 0xf;
 631
 632                 tcg_gen_neg_i32(REG(a), REG(b));
 633             }
 634             break;
 635         case 0x2b: /* or */
 636             {
 637                 int a = (opcode >> 4) & 0xf;
 638                 int b = opcode & 0xf;
 639
 640                 tcg_gen_or_i32(REG(a), REG(a), REG(b));
 641             }
 642             break;
 643         case 0x2c: /* not */
 644             {
 645                 int a = (opcode >> 4) & 0xf;
 646                 int b = opcode & 0xf;
 647
 648                 tcg_gen_not_i32(REG(a), REG(b));
 649             }
 650             break;
 651         case 0x2d: /* ashr */
 652             {
 653                 int a = (opcode >> 4) & 0xf;
 654                 int b = opcode & 0xf;
 655
 656                 TCGv sv = tcg_temp_new_i32();
 657                 tcg_gen_andi_i32(sv, REG(b), 0x1f);
 658                 tcg_gen_sar_i32(REG(a), REG(a), sv);
 659                 tcg_temp_free_i32(sv);
 660             }
 661             break;
 662         case 0x2e: /* xor */
 663             {
 664                 int a = (opcode >> 4) & 0xf;
 665                 int b = opcode & 0xf;
 666
 667                 tcg_gen_xor_i32(REG(a), REG(a), REG(b));
 668             }
 669             break;
 670         case 0x2f: /* mul.l */
 671             {
 672                 int a = (opcode >> 4) & 0xf;
 673                 int b = opcode & 0xf;
 674
 675                 tcg_gen_mul_i32(REG(a), REG(a), REG(b));
 676             }
 677             break;
 678         case 0x30: /* swi */
 679             {
 680                 int val = cpu_ldl_code(env, ctx->pc+2);
 681
 682                 TCGv temp = tcg_temp_new_i32();
 683                 tcg_gen_movi_i32(temp, val);
 684                 tcg_gen_st_i32(temp, cpu_env,
 685                                offsetof(CPUMoxieState, sregs[3]));
 686                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 687                 tcg_gen_movi_i32(temp, MOXIE_EX_SWI);
 688                 gen_helper_raise_exception(cpu_env, temp);
 689                 tcg_temp_free_i32(temp);
 690
 691                 length = 6;
 692             }
 693             break;
 694         case 0x31: /* div.l */
 695             {
 696                 int a = (opcode >> 4) & 0xf;
 697                 int b = opcode & 0xf;
 698                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 699                 gen_helper_div(REG(a), cpu_env, REG(a), REG(b));
 700             }
 701             break;
 702         case 0x32: /* udiv.l */
 703             {
 704                 int a = (opcode >> 4) & 0xf;
 705                 int b = opcode & 0xf;
 706                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 707                 gen_helper_udiv(REG(a), cpu_env, REG(a), REG(b));
 708             }
 709             break;
 710         case 0x33: /* mod.l */
 711             {
 712                 int a = (opcode >> 4) & 0xf;
 713                 int b = opcode & 0xf;
 714                 tcg_gen_rem_i32(REG(a), REG(a), REG(b));
 715             }
 716             break;
 717         case 0x34: /* umod.l */
 718             {
 719                 int a = (opcode >> 4) & 0xf;
 720                 int b = opcode & 0xf;
 721                 tcg_gen_remu_i32(REG(a), REG(a), REG(b));
 722             }
 723             break;
 724         case 0x35: /* brk */
 725             {
 726                 TCGv temp = tcg_temp_new_i32();
 727                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 728                 tcg_gen_movi_i32(temp, MOXIE_EX_BREAK);
 729                 gen_helper_raise_exception(cpu_env, temp);
 730                 tcg_temp_free_i32(temp);
 731             }
 732             break;
 733         case 0x36: /* ldo.b */
 734             {
 735                 int a = (opcode >> 4) & 0xf;
 736                 int b = opcode & 0xf;
 737
 738                 TCGv t1 = tcg_temp_new_i32();
 739                 TCGv t2 = tcg_temp_new_i32();
 740                 tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
 741                 tcg_gen_qemu_ld8u(t2, t1, ctx->memidx);
 742                 tcg_gen_mov_i32(REG(a), t2);
 743
 744                 tcg_temp_free_i32(t1);
 745                 tcg_temp_free_i32(t2);
 746
 747                 length = 6;
 748             }
 749             break;
 750         case 0x37: /* sto.b */
 751             {
 752                 int a = (opcode >> 4) & 0xf;
 753                 int b = opcode & 0xf;
 754
 755                 TCGv t1 = tcg_temp_new_i32();
 756                 TCGv t2 = tcg_temp_new_i32();
 757                 tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
 758                 tcg_gen_qemu_st8(REG(b), t1, ctx->memidx);
 759
 760                 tcg_temp_free_i32(t1);
 761                 tcg_temp_free_i32(t2);
 762
 763                 length = 6;
 764             }
 765             break;
 766         case 0x38: /* ldo.s */
 767             {
 768                 int a = (opcode >> 4) & 0xf;
 769                 int b = opcode & 0xf;
 770
 771                 TCGv t1 = tcg_temp_new_i32();
 772                 TCGv t2 = tcg_temp_new_i32();
 773                 tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
 774                 tcg_gen_qemu_ld16u(t2, t1, ctx->memidx);
 775                 tcg_gen_mov_i32(REG(a), t2);
 776
 777                 tcg_temp_free_i32(t1);
 778                 tcg_temp_free_i32(t2);
 779
 780                 length = 6;
 781             }
 782             break;
 783         case 0x39: /* sto.s */
 784             {
 785                 int a = (opcode >> 4) & 0xf;
 786                 int b = opcode & 0xf;
 787
 788                 TCGv t1 = tcg_temp_new_i32();
 789                 TCGv t2 = tcg_temp_new_i32();
 790                 tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
 791                 tcg_gen_qemu_st16(REG(b), t1, ctx->memidx);
 792                 tcg_temp_free_i32(t1);
 793                 tcg_temp_free_i32(t2);
 794
 795                 length = 6;
 796             }
 797             break;
 798         default:
 799             {
 800                 TCGv temp = tcg_temp_new_i32();
 801                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 802                 tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
 803                 gen_helper_raise_exception(cpu_env, temp);
 804                 tcg_temp_free_i32(temp);
 805              }
 806             break;
 807         }
 808     }
 809
 810     return length;
 811 }
 812
 813 /* generate intermediate code for basic block 'tb'.  */
 814 void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
 815 {
 816     MoxieCPU *cpu = moxie_env_get_cpu(env);
 817     CPUState *cs = CPU(cpu);
 818     DisasContext ctx;
 819     target_ulong pc_start;
 820     int num_insns, max_insns;
 821
 822     pc_start = tb->pc;
 823     ctx.pc = pc_start;
 824     ctx.saved_pc = -1;
 825     ctx.tb = tb;
 826     ctx.memidx = 0;
 827     ctx.singlestep_enabled = 0;
 828     ctx.bstate = BS_NONE;
 829     num_insns = 0;
 830     max_insns = tb->cflags & CF_COUNT_MASK;
 831     if (max_insns == 0) {
 832         max_insns = CF_COUNT_MASK;
 833     }
 834     if (max_insns > TCG_MAX_INSNS) {
 835         max_insns = TCG_MAX_INSNS;
 836     }
 837
 838     gen_tb_start(tb);
 839     do {
 840         tcg_gen_insn_start(ctx.pc);
 841         num_insns++;
 842
 843         if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
 844             tcg_gen_movi_i32(cpu_pc, ctx.pc);
 845             gen_helper_debug(cpu_env);
 846             ctx.bstate = BS_EXCP;
 847             /* The address covered by the breakpoint must be included in
 848                [tb->pc, tb->pc + tb->size) in order to for it to be
 849                properly cleared -- thus we increment the PC here so that
 850                the logic setting tb->size below does the right thing.  */
 851             ctx.pc += 2;
 852             goto done_generating;
 853         }
 854
 855         ctx.opcode = cpu_lduw_code(env, ctx.pc);
 856         ctx.pc += decode_opc(cpu, &ctx);
 857
 858         if (num_insns >= max_insns) {
 859             break;
 860         }
 861         if (cs->singlestep_enabled) {
 862             break;
 863         }
 864         if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) {
 865             break;
 866         }
 867     } while (ctx.bstate == BS_NONE && !tcg_op_buf_full());
 868
 869     if (cs->singlestep_enabled) {
 870         tcg_gen_movi_tl(cpu_pc, ctx.pc);
 871         gen_helper_debug(cpu_env);
 872     } else {
 873         switch (ctx.bstate) {
 874         case BS_STOP:
 875         case BS_NONE:
 876             gen_goto_tb(env, &ctx, 0, ctx.pc);
 877             break;
 878         case BS_EXCP:
 879             tcg_gen_exit_tb(0);
 880             break;
 881         case BS_BRANCH:
 882         default:
 883             break;
 884         }
 885     }
 886  done_generating:
 887     gen_tb_end(tb, num_insns);
 888
 889     tb->size = ctx.pc - pc_start;
 890     tb->icount = num_insns;
 891 }
 892
 893 void restore_state_to_opc(CPUMoxieState *env, TranslationBlock *tb,
 894                           target_ulong *data)
 895 {
 896     env->pc = data[0];
 897 }