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target/mips: Add CP0 PWCtl register
[qemu/ar7.git] / target / mips / op_helper.c
blobada22e6a07bf53c91717dd84771c6301bce1b869
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
21 #include "cpu.h"
22 #include "internal.h"
23 #include "qemu/host-utils.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
27 #include "sysemu/kvm.h"
28
29 /*****************************************************************************/
30 /* Exceptions processing helpers */
31
32 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
33 int error_code)
34 {
35 do_raise_exception_err(env, exception, error_code, 0);
36 }
37
38 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
39 {
40 do_raise_exception(env, exception, GETPC());
41 }
42
43 void helper_raise_exception_debug(CPUMIPSState *env)
44 {
45 do_raise_exception(env, EXCP_DEBUG, 0);
46 }
47
48 static void raise_exception(CPUMIPSState *env, uint32_t exception)
49 {
50 do_raise_exception(env, exception, 0);
51 }
52
53 #if defined(CONFIG_USER_ONLY)
54 #define HELPER_LD(name, insn, type) \
55 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
56 int mem_idx, uintptr_t retaddr) \
57 { \
58 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
59 }
60 #else
61 #define HELPER_LD(name, insn, type) \
62 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
63 int mem_idx, uintptr_t retaddr) \
64 { \
65 switch (mem_idx) \
66 { \
67 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
68 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
69 default: \
70 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
71 case 3: return (type) cpu_##insn##_error_ra(env, addr, retaddr); \
72 } \
73 }
74 #endif
75 HELPER_LD(lw, ldl, int32_t)
76 #if defined(TARGET_MIPS64)
77 HELPER_LD(ld, ldq, int64_t)
78 #endif
79 #undef HELPER_LD
80
81 #if defined(CONFIG_USER_ONLY)
82 #define HELPER_ST(name, insn, type) \
83 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
84 type val, int mem_idx, uintptr_t retaddr) \
85 { \
86 cpu_##insn##_data_ra(env, addr, val, retaddr); \
87 }
88 #else
89 #define HELPER_ST(name, insn, type) \
90 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
91 type val, int mem_idx, uintptr_t retaddr) \
92 { \
93 switch (mem_idx) \
94 { \
95 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
96 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
97 default: \
98 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
99 case 3: \
100 cpu_##insn##_error_ra(env, addr, val, retaddr); \
101 break; \
102 } \
103 }
104 #endif
105 HELPER_ST(sb, stb, uint8_t)
106 HELPER_ST(sw, stl, uint32_t)
107 #if defined(TARGET_MIPS64)
108 HELPER_ST(sd, stq, uint64_t)
109 #endif
110 #undef HELPER_ST
111
112 /* 64 bits arithmetic for 32 bits hosts */
113 static inline uint64_t get_HILO(CPUMIPSState *env)
114 {
115 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
116 }
117
118 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
119 {
120 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
121 return env->active_tc.HI[0] = (int32_t)(HILO >> 32);
122 }
123
124 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
125 {
126 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
127 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
128 return tmp;
129 }
130
131 /* Multiplication variants of the vr54xx. */
132 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
133 target_ulong arg2)
134 {
135 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
136 (int64_t)(int32_t)arg2));
137 }
138
139 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
140 target_ulong arg2)
141 {
142 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
143 (uint64_t)(uint32_t)arg2);
144 }
145
146 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
147 target_ulong arg2)
148 {
149 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
150 (int64_t)(int32_t)arg2);
151 }
152
153 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
154 target_ulong arg2)
155 {
156 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
157 (int64_t)(int32_t)arg2);
158 }
159
160 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
161 target_ulong arg2)
162 {
163 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
164 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
165 }
166
167 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
168 target_ulong arg2)
169 {
170 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
171 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
172 }
173
174 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
175 target_ulong arg2)
176 {
177 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
178 (int64_t)(int32_t)arg2);
179 }
180
181 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
182 target_ulong arg2)
183 {
184 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
185 (int64_t)(int32_t)arg2);
186 }
187
188 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
189 target_ulong arg2)
190 {
191 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
192 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
193 }
194
195 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
196 target_ulong arg2)
197 {
198 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
199 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
200 }
201
202 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
203 target_ulong arg2)
204 {
205 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
206 }
207
208 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
209 target_ulong arg2)
210 {
211 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
212 (uint64_t)(uint32_t)arg2);
213 }
214
215 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
216 target_ulong arg2)
217 {
218 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
219 (int64_t)(int32_t)arg2);
220 }
221
222 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
223 target_ulong arg2)
224 {
225 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
226 (uint64_t)(uint32_t)arg2);
227 }
228
229 static inline target_ulong bitswap(target_ulong v)
230 {
231 v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
232 ((v & (target_ulong)0x5555555555555555ULL) << 1);
233 v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
234 ((v & (target_ulong)0x3333333333333333ULL) << 2);
235 v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
236 ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
237 return v;
238 }
239
240 #ifdef TARGET_MIPS64
241 target_ulong helper_dbitswap(target_ulong rt)
242 {
243 return bitswap(rt);
244 }
245 #endif
246
247 target_ulong helper_bitswap(target_ulong rt)
248 {
249 return (int32_t)bitswap(rt);
250 }
251
252 target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
253 uint32_t stripe)
254 {
255 int i;
256 uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff);
257 uint64_t tmp1 = tmp0;
258 for (i = 0; i <= 46; i++) {
259 int s;
260 if (i & 0x8) {
261 s = shift;
262 } else {
263 s = shiftx;
264 }
265
266 if (stripe != 0 && !(i & 0x4)) {
267 s = ~s;
268 }
269 if (s & 0x10) {
270 if (tmp0 & (1LL << (i + 16))) {
271 tmp1 |= 1LL << i;
272 } else {
273 tmp1 &= ~(1LL << i);
274 }
275 }
276 }
277
278 uint64_t tmp2 = tmp1;
279 for (i = 0; i <= 38; i++) {
280 int s;
281 if (i & 0x4) {
282 s = shift;
283 } else {
284 s = shiftx;
285 }
286
287 if (s & 0x8) {
288 if (tmp1 & (1LL << (i + 8))) {
289 tmp2 |= 1LL << i;
290 } else {
291 tmp2 &= ~(1LL << i);
292 }
293 }
294 }
295
296 uint64_t tmp3 = tmp2;
297 for (i = 0; i <= 34; i++) {
298 int s;
299 if (i & 0x2) {
300 s = shift;
301 } else {
302 s = shiftx;
303 }
304 if (s & 0x4) {
305 if (tmp2 & (1LL << (i + 4))) {
306 tmp3 |= 1LL << i;
307 } else {
308 tmp3 &= ~(1LL << i);
309 }
310 }
311 }
312
313 uint64_t tmp4 = tmp3;
314 for (i = 0; i <= 32; i++) {
315 int s;
316 if (i & 0x1) {
317 s = shift;
318 } else {
319 s = shiftx;
320 }
321 if (s & 0x2) {
322 if (tmp3 & (1LL << (i + 2))) {
323 tmp4 |= 1LL << i;
324 } else {
325 tmp4 &= ~(1LL << i);
326 }
327 }
328 }
329
330 uint64_t tmp5 = tmp4;
331 for (i = 0; i <= 31; i++) {
332 int s;
333 s = shift;
334 if (s & 0x1) {
335 if (tmp4 & (1LL << (i + 1))) {
336 tmp5 |= 1LL << i;
337 } else {
338 tmp5 &= ~(1LL << i);
339 }
340 }
341 }
342
343 return (int64_t)(int32_t)(uint32_t)tmp5;
344 }
345
346 #ifndef CONFIG_USER_ONLY
347
348 static inline hwaddr do_translate_address(CPUMIPSState *env,
349 target_ulong address,
350 int rw, uintptr_t retaddr)
351 {
352 hwaddr lladdr;
353 CPUState *cs = CPU(mips_env_get_cpu(env));
354
355 lladdr = cpu_mips_translate_address(env, address, rw);
356
357 if (lladdr == -1LL) {
358 cpu_loop_exit_restore(cs, retaddr);
359 } else {
360 return lladdr;
361 }
362 }
363
364 #define HELPER_LD_ATOMIC(name, insn, almask) \
365 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
366 { \
367 if (arg & almask) { \
368 if (!(env->hflags & MIPS_HFLAG_DM)) { \
369 env->CP0_BadVAddr = arg; \
370 } \
371 do_raise_exception(env, EXCP_AdEL, GETPC()); \
372 } \
373 env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
374 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
375 return env->llval; \
376 }
377 HELPER_LD_ATOMIC(ll, lw, 0x3)
378 #ifdef TARGET_MIPS64
379 HELPER_LD_ATOMIC(lld, ld, 0x7)
380 #endif
381 #undef HELPER_LD_ATOMIC
382
383 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
384 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
385 target_ulong arg2, int mem_idx) \
386 { \
387 target_long tmp; \
388 \
389 if (arg2 & almask) { \
390 if (!(env->hflags & MIPS_HFLAG_DM)) { \
391 env->CP0_BadVAddr = arg2; \
392 } \
393 do_raise_exception(env, EXCP_AdES, GETPC()); \
394 } \
395 if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
396 tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \
397 if (tmp == env->llval) { \
398 do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \
399 return 1; \
400 } \
401 } \
402 return 0; \
403 }
404 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
405 #ifdef TARGET_MIPS64
406 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
407 #endif
408 #undef HELPER_ST_ATOMIC
409 #endif
410
411 #ifdef TARGET_WORDS_BIGENDIAN
412 #define GET_LMASK(v) ((v) & 3)
413 #define GET_OFFSET(addr, offset) (addr + (offset))
414 #else
415 #define GET_LMASK(v) (((v) & 3) ^ 3)
416 #define GET_OFFSET(addr, offset) (addr - (offset))
417 #endif
418
419 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
420 int mem_idx)
421 {
422 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
423
424 if (GET_LMASK(arg2) <= 2) {
425 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
426 GETPC());
427 }
428
429 if (GET_LMASK(arg2) <= 1) {
430 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
431 GETPC());
432 }
433
434 if (GET_LMASK(arg2) == 0) {
435 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
436 GETPC());
437 }
438 }
439
440 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
441 int mem_idx)
442 {
443 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
444
445 if (GET_LMASK(arg2) >= 1) {
446 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
447 GETPC());
448 }
449
450 if (GET_LMASK(arg2) >= 2) {
451 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
452 GETPC());
453 }
454
455 if (GET_LMASK(arg2) == 3) {
456 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
457 GETPC());
458 }
459 }
460
461 #if defined(TARGET_MIPS64)
462 /* "half" load and stores. We must do the memory access inline,
463 or fault handling won't work. */
464
465 #ifdef TARGET_WORDS_BIGENDIAN
466 #define GET_LMASK64(v) ((v) & 7)
467 #else
468 #define GET_LMASK64(v) (((v) & 7) ^ 7)
469 #endif
470
471 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
472 int mem_idx)
473 {
474 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
475
476 if (GET_LMASK64(arg2) <= 6) {
477 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
478 GETPC());
479 }
480
481 if (GET_LMASK64(arg2) <= 5) {
482 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
483 GETPC());
484 }
485
486 if (GET_LMASK64(arg2) <= 4) {
487 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
488 GETPC());
489 }
490
491 if (GET_LMASK64(arg2) <= 3) {
492 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
493 GETPC());
494 }
495
496 if (GET_LMASK64(arg2) <= 2) {
497 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
498 GETPC());
499 }
500
501 if (GET_LMASK64(arg2) <= 1) {
502 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
503 GETPC());
504 }
505
506 if (GET_LMASK64(arg2) <= 0) {
507 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
508 GETPC());
509 }
510 }
511
512 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
513 int mem_idx)
514 {
515 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
516
517 if (GET_LMASK64(arg2) >= 1) {
518 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
519 GETPC());
520 }
521
522 if (GET_LMASK64(arg2) >= 2) {
523 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
524 GETPC());
525 }
526
527 if (GET_LMASK64(arg2) >= 3) {
528 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
529 GETPC());
530 }
531
532 if (GET_LMASK64(arg2) >= 4) {
533 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
534 GETPC());
535 }
536
537 if (GET_LMASK64(arg2) >= 5) {
538 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
539 GETPC());
540 }
541
542 if (GET_LMASK64(arg2) >= 6) {
543 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
544 GETPC());
545 }
546
547 if (GET_LMASK64(arg2) == 7) {
548 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
549 GETPC());
550 }
551 }
552 #endif /* TARGET_MIPS64 */
553
554 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
555
556 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
557 uint32_t mem_idx)
558 {
559 target_ulong base_reglist = reglist & 0xf;
560 target_ulong do_r31 = reglist & 0x10;
561
562 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
563 target_ulong i;
564
565 for (i = 0; i < base_reglist; i++) {
566 env->active_tc.gpr[multiple_regs[i]] =
567 (target_long)do_lw(env, addr, mem_idx, GETPC());
568 addr += 4;
569 }
570 }
571
572 if (do_r31) {
573 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
574 GETPC());
575 }
576 }
577
578 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
579 uint32_t mem_idx)
580 {
581 target_ulong base_reglist = reglist & 0xf;
582 target_ulong do_r31 = reglist & 0x10;
583
584 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
585 target_ulong i;
586
587 for (i = 0; i < base_reglist; i++) {
588 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
589 GETPC());
590 addr += 4;
591 }
592 }
593
594 if (do_r31) {
595 do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
596 }
597 }
598
599 #if defined(TARGET_MIPS64)
600 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
601 uint32_t mem_idx)
602 {
603 target_ulong base_reglist = reglist & 0xf;
604 target_ulong do_r31 = reglist & 0x10;
605
606 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
607 target_ulong i;
608
609 for (i = 0; i < base_reglist; i++) {
610 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
611 GETPC());
612 addr += 8;
613 }
614 }
615
616 if (do_r31) {
617 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
618 }
619 }
620
621 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
622 uint32_t mem_idx)
623 {
624 target_ulong base_reglist = reglist & 0xf;
625 target_ulong do_r31 = reglist & 0x10;
626
627 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
628 target_ulong i;
629
630 for (i = 0; i < base_reglist; i++) {
631 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
632 GETPC());
633 addr += 8;
634 }
635 }
636
637 if (do_r31) {
638 do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
639 }
640 }
641 #endif
642
643 #ifndef CONFIG_USER_ONLY
644 /* SMP helpers. */
645 static bool mips_vpe_is_wfi(MIPSCPU *c)
646 {
647 CPUState *cpu = CPU(c);
648 CPUMIPSState *env = &c->env;
649
650 /* If the VPE is halted but otherwise active, it means it's waiting for
651 an interrupt. */
652 return cpu->halted && mips_vpe_active(env);
653 }
654
655 static bool mips_vp_is_wfi(MIPSCPU *c)
656 {
657 CPUState *cpu = CPU(c);
658 CPUMIPSState *env = &c->env;
659
660 return cpu->halted && mips_vp_active(env);
661 }
662
663 static inline void mips_vpe_wake(MIPSCPU *c)
664 {
665 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
666 because there might be other conditions that state that c should
667 be sleeping. */
668 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
669 }
670
671 static inline void mips_vpe_sleep(MIPSCPU *cpu)
672 {
673 CPUState *cs = CPU(cpu);
674
675 /* The VPE was shut off, really go to bed.
676 Reset any old _WAKE requests. */
677 cs->halted = 1;
678 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
679 }
680
681 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
682 {
683 CPUMIPSState *c = &cpu->env;
684
685 /* FIXME: TC reschedule. */
686 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
687 mips_vpe_wake(cpu);
688 }
689 }
690
691 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
692 {
693 CPUMIPSState *c = &cpu->env;
694
695 /* FIXME: TC reschedule. */
696 if (!mips_vpe_active(c)) {
697 mips_vpe_sleep(cpu);
698 }
699 }
700
701 /**
702 * mips_cpu_map_tc:
703 * @env: CPU from which mapping is performed.
704 * @tc: Should point to an int with the value of the global TC index.
705 *
706 * This function will transform @tc into a local index within the
707 * returned #CPUMIPSState.
708 */
709 /* FIXME: This code assumes that all VPEs have the same number of TCs,
710 which depends on runtime setup. Can probably be fixed by
711 walking the list of CPUMIPSStates. */
712 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
713 {
714 MIPSCPU *cpu;
715 CPUState *cs;
716 CPUState *other_cs;
717 int vpe_idx;
718 int tc_idx = *tc;
719
720 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
721 /* Not allowed to address other CPUs. */
722 *tc = env->current_tc;
723 return env;
724 }
725
726 cs = CPU(mips_env_get_cpu(env));
727 vpe_idx = tc_idx / cs->nr_threads;
728 *tc = tc_idx % cs->nr_threads;
729 other_cs = qemu_get_cpu(vpe_idx);
730 if (other_cs == NULL) {
731 return env;
732 }
733 cpu = MIPS_CPU(other_cs);
734 return &cpu->env;
735 }
736
737 /* The per VPE CP0_Status register shares some fields with the per TC
738 CP0_TCStatus registers. These fields are wired to the same registers,
739 so changes to either of them should be reflected on both registers.
740
741 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
742
743 These helper call synchronizes the regs for a given cpu. */
744
745 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
746 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
747 int tc); */
748
749 /* Called for updates to CP0_TCStatus. */
750 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
751 target_ulong v)
752 {
753 uint32_t status;
754 uint32_t tcu, tmx, tasid, tksu;
755 uint32_t mask = ((1U << CP0St_CU3)
756 | (1 << CP0St_CU2)
757 | (1 << CP0St_CU1)
758 | (1 << CP0St_CU0)
759 | (1 << CP0St_MX)
760 | (3 << CP0St_KSU));
761
762 tcu = (v >> CP0TCSt_TCU0) & 0xf;
763 tmx = (v >> CP0TCSt_TMX) & 0x1;
764 tasid = v & cpu->CP0_EntryHi_ASID_mask;
765 tksu = (v >> CP0TCSt_TKSU) & 0x3;
766
767 status = tcu << CP0St_CU0;
768 status |= tmx << CP0St_MX;
769 status |= tksu << CP0St_KSU;
770
771 cpu->CP0_Status &= ~mask;
772 cpu->CP0_Status |= status;
773
774 /* Sync the TASID with EntryHi. */
775 cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask;
776 cpu->CP0_EntryHi |= tasid;
777
778 compute_hflags(cpu);
779 }
780
781 /* Called for updates to CP0_EntryHi. */
782 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
783 {
784 int32_t *tcst;
785 uint32_t asid, v = cpu->CP0_EntryHi;
786
787 asid = v & cpu->CP0_EntryHi_ASID_mask;
788
789 if (tc == cpu->current_tc) {
790 tcst = &cpu->active_tc.CP0_TCStatus;
791 } else {
792 tcst = &cpu->tcs[tc].CP0_TCStatus;
793 }
794
795 *tcst &= ~cpu->CP0_EntryHi_ASID_mask;
796 *tcst |= asid;
797 }
798
799 /* CP0 helpers */
800 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
801 {
802 return env->mvp->CP0_MVPControl;
803 }
804
805 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
806 {
807 return env->mvp->CP0_MVPConf0;
808 }
809
810 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
811 {
812 return env->mvp->CP0_MVPConf1;
813 }
814
815 target_ulong helper_mfc0_random(CPUMIPSState *env)
816 {
817 return (int32_t)cpu_mips_get_random(env);
818 }
819
820 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
821 {
822 return env->active_tc.CP0_TCStatus;
823 }
824
825 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
826 {
827 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
828 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
829
830 if (other_tc == other->current_tc)
831 return other->active_tc.CP0_TCStatus;
832 else
833 return other->tcs[other_tc].CP0_TCStatus;
834 }
835
836 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
837 {
838 return env->active_tc.CP0_TCBind;
839 }
840
841 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
842 {
843 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
844 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
845
846 if (other_tc == other->current_tc)
847 return other->active_tc.CP0_TCBind;
848 else
849 return other->tcs[other_tc].CP0_TCBind;
850 }
851
852 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
853 {
854 return env->active_tc.PC;
855 }
856
857 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
858 {
859 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
860 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
861
862 if (other_tc == other->current_tc)
863 return other->active_tc.PC;
864 else
865 return other->tcs[other_tc].PC;
866 }
867
868 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
869 {
870 return env->active_tc.CP0_TCHalt;
871 }
872
873 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
874 {
875 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
876 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
877
878 if (other_tc == other->current_tc)
879 return other->active_tc.CP0_TCHalt;
880 else
881 return other->tcs[other_tc].CP0_TCHalt;
882 }
883
884 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
885 {
886 return env->active_tc.CP0_TCContext;
887 }
888
889 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
890 {
891 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
892 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
893
894 if (other_tc == other->current_tc)
895 return other->active_tc.CP0_TCContext;
896 else
897 return other->tcs[other_tc].CP0_TCContext;
898 }
899
900 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
901 {
902 return env->active_tc.CP0_TCSchedule;
903 }
904
905 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
906 {
907 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
908 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
909
910 if (other_tc == other->current_tc)
911 return other->active_tc.CP0_TCSchedule;
912 else
913 return other->tcs[other_tc].CP0_TCSchedule;
914 }
915
916 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
917 {
918 return env->active_tc.CP0_TCScheFBack;
919 }
920
921 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
922 {
923 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
924 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
925
926 if (other_tc == other->current_tc)
927 return other->active_tc.CP0_TCScheFBack;
928 else
929 return other->tcs[other_tc].CP0_TCScheFBack;
930 }
931
932 target_ulong helper_mfc0_count(CPUMIPSState *env)
933 {
934 int32_t count;
935 qemu_mutex_lock_iothread();
936 count = (int32_t) cpu_mips_get_count(env);
937 qemu_mutex_unlock_iothread();
938 return count;
939 }
940
941 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
942 {
943 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
944 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
945
946 return other->CP0_EntryHi;
947 }
948
949 target_ulong helper_mftc0_cause(CPUMIPSState *env)
950 {
951 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
952 int32_t tccause;
953 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
954
955 if (other_tc == other->current_tc) {
956 tccause = other->CP0_Cause;
957 } else {
958 tccause = other->CP0_Cause;
959 }
960
961 return tccause;
962 }
963
964 target_ulong helper_mftc0_status(CPUMIPSState *env)
965 {
966 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
967 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
968
969 return other->CP0_Status;
970 }
971
972 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
973 {
974 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
975 }
976
977 target_ulong helper_mfc0_maar(CPUMIPSState *env)
978 {
979 return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
980 }
981
982 target_ulong helper_mfhc0_maar(CPUMIPSState *env)
983 {
984 return env->CP0_MAAR[env->CP0_MAARI] >> 32;
985 }
986
987 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
988 {
989 return (int32_t)env->CP0_WatchLo[sel];
990 }
991
992 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
993 {
994 return env->CP0_WatchHi[sel];
995 }
996
997 target_ulong helper_mfc0_debug(CPUMIPSState *env)
998 {
999 target_ulong t0 = env->CP0_Debug;
1000 if (env->hflags & MIPS_HFLAG_DM)
1001 t0 |= 1 << CP0DB_DM;
1002
1003 return t0;
1004 }
1005
1006 target_ulong helper_mftc0_debug(CPUMIPSState *env)
1007 {
1008 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1009 int32_t tcstatus;
1010 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1011
1012 if (other_tc == other->current_tc)
1013 tcstatus = other->active_tc.CP0_Debug_tcstatus;
1014 else
1015 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
1016
1017 /* XXX: Might be wrong, check with EJTAG spec. */
1018 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1019 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1020 }
1021
1022 #if defined(TARGET_MIPS64)
1023 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
1024 {
1025 return env->active_tc.PC;
1026 }
1027
1028 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
1029 {
1030 return env->active_tc.CP0_TCHalt;
1031 }
1032
1033 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
1034 {
1035 return env->active_tc.CP0_TCContext;
1036 }
1037
1038 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
1039 {
1040 return env->active_tc.CP0_TCSchedule;
1041 }
1042
1043 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
1044 {
1045 return env->active_tc.CP0_TCScheFBack;
1046 }
1047
1048 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
1049 {
1050 return env->lladdr >> env->CP0_LLAddr_shift;
1051 }
1052
1053 target_ulong helper_dmfc0_maar(CPUMIPSState *env)
1054 {
1055 return env->CP0_MAAR[env->CP0_MAARI];
1056 }
1057
1058 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
1059 {
1060 return env->CP0_WatchLo[sel];
1061 }
1062 #endif /* TARGET_MIPS64 */
1063
1064 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
1065 {
1066 uint32_t index_p = env->CP0_Index & 0x80000000;
1067 uint32_t tlb_index = arg1 & 0x7fffffff;
1068 if (tlb_index < env->tlb->nb_tlb) {
1069 if (env->insn_flags & ISA_MIPS32R6) {
1070 index_p |= arg1 & 0x80000000;
1071 }
1072 env->CP0_Index = index_p | tlb_index;
1073 }
1074 }
1075
1076 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
1077 {
1078 uint32_t mask = 0;
1079 uint32_t newval;
1080
1081 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
1082 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
1083 (1 << CP0MVPCo_EVP);
1084 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1085 mask |= (1 << CP0MVPCo_STLB);
1086 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
1087
1088 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1089
1090 env->mvp->CP0_MVPControl = newval;
1091 }
1092
1093 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1094 {
1095 uint32_t mask;
1096 uint32_t newval;
1097
1098 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1099 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1100 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1101
1102 /* Yield scheduler intercept not implemented. */
1103 /* Gating storage scheduler intercept not implemented. */
1104
1105 // TODO: Enable/disable TCs.
1106
1107 env->CP0_VPEControl = newval;
1108 }
1109
1110 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1111 {
1112 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1113 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1114 uint32_t mask;
1115 uint32_t newval;
1116
1117 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1118 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1119 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1120
1121 /* TODO: Enable/disable TCs. */
1122
1123 other->CP0_VPEControl = newval;
1124 }
1125
1126 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1127 {
1128 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1129 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1130 /* FIXME: Mask away return zero on read bits. */
1131 return other->CP0_VPEControl;
1132 }
1133
1134 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1135 {
1136 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1137 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1138
1139 return other->CP0_VPEConf0;
1140 }
1141
1142 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1143 {
1144 uint32_t mask = 0;
1145 uint32_t newval;
1146
1147 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1148 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1149 mask |= (0xff << CP0VPEC0_XTC);
1150 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1151 }
1152 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1153
1154 // TODO: TC exclusive handling due to ERL/EXL.
1155
1156 env->CP0_VPEConf0 = newval;
1157 }
1158
1159 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1160 {
1161 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1162 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1163 uint32_t mask = 0;
1164 uint32_t newval;
1165
1166 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1167 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1168
1169 /* TODO: TC exclusive handling due to ERL/EXL. */
1170 other->CP0_VPEConf0 = newval;
1171 }
1172
1173 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1174 {
1175 uint32_t mask = 0;
1176 uint32_t newval;
1177
1178 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1179 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1180 (0xff << CP0VPEC1_NCP1);
1181 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1182
1183 /* UDI not implemented. */
1184 /* CP2 not implemented. */
1185
1186 // TODO: Handle FPU (CP1) binding.
1187
1188 env->CP0_VPEConf1 = newval;
1189 }
1190
1191 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1192 {
1193 /* Yield qualifier inputs not implemented. */
1194 env->CP0_YQMask = 0x00000000;
1195 }
1196
1197 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1198 {
1199 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1200 }
1201
1202 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1203
1204 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1205 {
1206 /* 1k pages not implemented */
1207 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1208 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1209 | (rxi << (CP0EnLo_XI - 30));
1210 }
1211
1212 #if defined(TARGET_MIPS64)
1213 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1214
1215 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1216 {
1217 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1218 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1219 }
1220 #endif
1221
1222 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1223 {
1224 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1225 uint32_t newval;
1226
1227 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1228
1229 env->active_tc.CP0_TCStatus = newval;
1230 sync_c0_tcstatus(env, env->current_tc, newval);
1231 }
1232
1233 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1234 {
1235 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1236 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1237
1238 if (other_tc == other->current_tc)
1239 other->active_tc.CP0_TCStatus = arg1;
1240 else
1241 other->tcs[other_tc].CP0_TCStatus = arg1;
1242 sync_c0_tcstatus(other, other_tc, arg1);
1243 }
1244
1245 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1246 {
1247 uint32_t mask = (1 << CP0TCBd_TBE);
1248 uint32_t newval;
1249
1250 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1251 mask |= (1 << CP0TCBd_CurVPE);
1252 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1253 env->active_tc.CP0_TCBind = newval;
1254 }
1255
1256 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1257 {
1258 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1259 uint32_t mask = (1 << CP0TCBd_TBE);
1260 uint32_t newval;
1261 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1262
1263 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1264 mask |= (1 << CP0TCBd_CurVPE);
1265 if (other_tc == other->current_tc) {
1266 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1267 other->active_tc.CP0_TCBind = newval;
1268 } else {
1269 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1270 other->tcs[other_tc].CP0_TCBind = newval;
1271 }
1272 }
1273
1274 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1275 {
1276 env->active_tc.PC = arg1;
1277 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1278 env->lladdr = 0ULL;
1279 /* MIPS16 not implemented. */
1280 }
1281
1282 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1283 {
1284 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1285 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1286
1287 if (other_tc == other->current_tc) {
1288 other->active_tc.PC = arg1;
1289 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1290 other->lladdr = 0ULL;
1291 /* MIPS16 not implemented. */
1292 } else {
1293 other->tcs[other_tc].PC = arg1;
1294 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1295 other->lladdr = 0ULL;
1296 /* MIPS16 not implemented. */
1297 }
1298 }
1299
1300 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1301 {
1302 MIPSCPU *cpu = mips_env_get_cpu(env);
1303
1304 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1305
1306 // TODO: Halt TC / Restart (if allocated+active) TC.
1307 if (env->active_tc.CP0_TCHalt & 1) {
1308 mips_tc_sleep(cpu, env->current_tc);
1309 } else {
1310 mips_tc_wake(cpu, env->current_tc);
1311 }
1312 }
1313
1314 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1315 {
1316 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1317 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1318 MIPSCPU *other_cpu = mips_env_get_cpu(other);
1319
1320 // TODO: Halt TC / Restart (if allocated+active) TC.
1321
1322 if (other_tc == other->current_tc)
1323 other->active_tc.CP0_TCHalt = arg1;
1324 else
1325 other->tcs[other_tc].CP0_TCHalt = arg1;
1326
1327 if (arg1 & 1) {
1328 mips_tc_sleep(other_cpu, other_tc);
1329 } else {
1330 mips_tc_wake(other_cpu, other_tc);
1331 }
1332 }
1333
1334 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1335 {
1336 env->active_tc.CP0_TCContext = arg1;
1337 }
1338
1339 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1340 {
1341 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1342 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1343
1344 if (other_tc == other->current_tc)
1345 other->active_tc.CP0_TCContext = arg1;
1346 else
1347 other->tcs[other_tc].CP0_TCContext = arg1;
1348 }
1349
1350 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1351 {
1352 env->active_tc.CP0_TCSchedule = arg1;
1353 }
1354
1355 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1356 {
1357 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1358 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1359
1360 if (other_tc == other->current_tc)
1361 other->active_tc.CP0_TCSchedule = arg1;
1362 else
1363 other->tcs[other_tc].CP0_TCSchedule = arg1;
1364 }
1365
1366 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1367 {
1368 env->active_tc.CP0_TCScheFBack = arg1;
1369 }
1370
1371 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1372 {
1373 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1374 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1375
1376 if (other_tc == other->current_tc)
1377 other->active_tc.CP0_TCScheFBack = arg1;
1378 else
1379 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1380 }
1381
1382 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1383 {
1384 /* 1k pages not implemented */
1385 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1386 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1387 | (rxi << (CP0EnLo_XI - 30));
1388 }
1389
1390 #if defined(TARGET_MIPS64)
1391 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1392 {
1393 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1394 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1395 }
1396 #endif
1397
1398 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1399 {
1400 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1401 }
1402
1403 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1404 {
1405 uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1406 if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1407 (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1408 mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1409 mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1410 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1411 }
1412 }
1413
1414 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1415 {
1416 /* SmartMIPS not implemented */
1417 /* 1k pages not implemented */
1418 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1419 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1420 compute_hflags(env);
1421 restore_pamask(env);
1422 }
1423
1424 void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
1425 {
1426 CPUState *cs = CPU(mips_env_get_cpu(env));
1427
1428 env->CP0_SegCtl0 = arg1 & CP0SC0_MASK;
1429 tlb_flush(cs);
1430 }
1431
1432 void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
1433 {
1434 CPUState *cs = CPU(mips_env_get_cpu(env));
1435
1436 env->CP0_SegCtl1 = arg1 & CP0SC1_MASK;
1437 tlb_flush(cs);
1438 }
1439
1440 void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1)
1441 {
1442 CPUState *cs = CPU(mips_env_get_cpu(env));
1443
1444 env->CP0_SegCtl2 = arg1 & CP0SC2_MASK;
1445 tlb_flush(cs);
1446 }
1447
1448 void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
1449 {
1450 #if defined(TARGET_MIPS64)
1451 uint64_t mask = 0x3F3FFFFFFFULL;
1452 uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL;
1453 uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3FULL;
1454
1455 if ((env->insn_flags & ISA_MIPS32R6)) {
1456 if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) {
1457 mask &= ~(0x3FULL << CP0PF_BDI);
1458 }
1459 if (((arg1 >> CP0PF_GDI) & 0x3FULL) < 12) {
1460 mask &= ~(0x3FULL << CP0PF_GDI);
1461 }
1462 if (((arg1 >> CP0PF_UDI) & 0x3FULL) < 12) {
1463 mask &= ~(0x3FULL << CP0PF_UDI);
1464 }
1465 if (((arg1 >> CP0PF_MDI) & 0x3FULL) < 12) {
1466 mask &= ~(0x3FULL << CP0PF_MDI);
1467 }
1468 if (((arg1 >> CP0PF_PTI) & 0x3FULL) < 12) {
1469 mask &= ~(0x3FULL << CP0PF_PTI);
1470 }
1471 }
1472 env->CP0_PWField = arg1 & mask;
1473
1474 if ((new_ptei >= 32) ||
1475 ((env->insn_flags & ISA_MIPS32R6) &&
1476 (new_ptei == 0 || new_ptei == 1))) {
1477 env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) |
1478 (old_ptei << CP0PF_PTEI);
1479 }
1480 #else
1481 uint32_t mask = 0x3FFFFFFF;
1482 uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
1483 uint32_t new_ptew = (arg1 >> CP0PF_PTEW) & 0x3F;
1484
1485 if ((env->insn_flags & ISA_MIPS32R6)) {
1486 if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) {
1487 mask &= ~(0x3F << CP0PF_GDW);
1488 }
1489 if (((arg1 >> CP0PF_UDW) & 0x3F) < 12) {
1490 mask &= ~(0x3F << CP0PF_UDW);
1491 }
1492 if (((arg1 >> CP0PF_MDW) & 0x3F) < 12) {
1493 mask &= ~(0x3F << CP0PF_MDW);
1494 }
1495 if (((arg1 >> CP0PF_PTW) & 0x3F) < 12) {
1496 mask &= ~(0x3F << CP0PF_PTW);
1497 }
1498 }
1499 env->CP0_PWField = arg1 & mask;
1500
1501 if ((new_ptew >= 32) ||
1502 ((env->insn_flags & ISA_MIPS32R6) &&
1503 (new_ptew == 0 || new_ptew == 1))) {
1504 env->CP0_PWField = (env->CP0_PWField & ~0x3F) |
1505 (old_ptew << CP0PF_PTEW);
1506 }
1507 #endif
1508 }
1509
1510 void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
1511 {
1512 #if defined(TARGET_MIPS64)
1513 env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL;
1514 #else
1515 env->CP0_PWSize = arg1 & 0x3FFFFFFF;
1516 #endif
1517 }
1518
1519 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1520 {
1521 if (env->insn_flags & ISA_MIPS32R6) {
1522 if (arg1 < env->tlb->nb_tlb) {
1523 env->CP0_Wired = arg1;
1524 }
1525 } else {
1526 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1527 }
1528 }
1529
1530 void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1)
1531 {
1532 #if defined(TARGET_MIPS64)
1533 /* PWEn = 0. Hardware page table walking is not implemented. */
1534 env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F);
1535 #else
1536 env->CP0_PWCtl = (arg1 & 0x800000FF);
1537 #endif
1538 }
1539
1540 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1541 {
1542 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1543 }
1544
1545 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1546 {
1547 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1548 }
1549
1550 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1551 {
1552 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1553 }
1554
1555 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1556 {
1557 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1558 }
1559
1560 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1561 {
1562 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1563 }
1564
1565 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1566 {
1567 uint32_t mask = 0x0000000F;
1568
1569 if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1570 (env->insn_flags & ISA_MIPS32R6)) {
1571 mask |= (1 << 4);
1572 }
1573 if (env->insn_flags & ISA_MIPS32R6) {
1574 mask |= (1 << 5);
1575 }
1576 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1577 mask |= (1 << 29);
1578
1579 if (arg1 & (1 << 29)) {
1580 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1581 } else {
1582 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1583 }
1584 }
1585
1586 env->CP0_HWREna = arg1 & mask;
1587 }
1588
1589 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1590 {
1591 qemu_mutex_lock_iothread();
1592 cpu_mips_store_count(env, arg1);
1593 qemu_mutex_unlock_iothread();
1594 }
1595
1596 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1597 {
1598 target_ulong old, val, mask;
1599 mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
1600 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1601 mask |= 1 << CP0EnHi_EHINV;
1602 }
1603
1604 /* 1k pages not implemented */
1605 #if defined(TARGET_MIPS64)
1606 if (env->insn_flags & ISA_MIPS32R6) {
1607 int entryhi_r = extract64(arg1, 62, 2);
1608 int config0_at = extract32(env->CP0_Config0, 13, 2);
1609 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1610 if ((entryhi_r == 2) ||
1611 (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1612 /* skip EntryHi.R field if new value is reserved */
1613 mask &= ~(0x3ull << 62);
1614 }
1615 }
1616 mask &= env->SEGMask;
1617 #endif
1618 old = env->CP0_EntryHi;
1619 val = (arg1 & mask) | (old & ~mask);
1620 env->CP0_EntryHi = val;
1621 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1622 sync_c0_entryhi(env, env->current_tc);
1623 }
1624 /* If the ASID changes, flush qemu's TLB. */
1625 if ((old & env->CP0_EntryHi_ASID_mask) !=
1626 (val & env->CP0_EntryHi_ASID_mask)) {
1627 tlb_flush(CPU(mips_env_get_cpu(env)));
1628 }
1629 }
1630
1631 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1632 {
1633 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1634 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1635
1636 other->CP0_EntryHi = arg1;
1637 sync_c0_entryhi(other, other_tc);
1638 }
1639
1640 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1641 {
1642 qemu_mutex_lock_iothread();
1643 cpu_mips_store_compare(env, arg1);
1644 qemu_mutex_unlock_iothread();
1645 }
1646
1647 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1648 {
1649 MIPSCPU *cpu = mips_env_get_cpu(env);
1650 uint32_t val, old;
1651
1652 old = env->CP0_Status;
1653 cpu_mips_store_status(env, arg1);
1654 val = env->CP0_Status;
1655
1656 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1657 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1658 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1659 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1660 env->CP0_Cause);
1661 switch (cpu_mmu_index(env, false)) {
1662 case 3:
1663 qemu_log(", ERL\n");
1664 break;
1665 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1666 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1667 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1668 default:
1669 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1670 break;
1671 }
1672 }
1673 }
1674
1675 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1676 {
1677 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1678 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1679 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1680
1681 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1682 sync_c0_status(env, other, other_tc);
1683 }
1684
1685 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1686 {
1687 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1688 }
1689
1690 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1691 {
1692 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1693 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1694 }
1695
1696 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1697 {
1698 qemu_mutex_lock_iothread();
1699 cpu_mips_store_cause(env, arg1);
1700 qemu_mutex_unlock_iothread();
1701 }
1702
1703 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1704 {
1705 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1706 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1707
1708 cpu_mips_store_cause(other, arg1);
1709 }
1710
1711 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1712 {
1713 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1714 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1715
1716 return other->CP0_EPC;
1717 }
1718
1719 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1720 {
1721 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1722 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1723
1724 return other->CP0_EBase;
1725 }
1726
1727 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1728 {
1729 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1730 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1731 mask |= ~0x3FFFFFFF;
1732 }
1733 env->CP0_EBase = (env->CP0_EBase & ~mask) | (arg1 & mask);
1734 }
1735
1736 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1737 {
1738 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1739 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1740 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1741 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1742 mask |= ~0x3FFFFFFF;
1743 }
1744 other->CP0_EBase = (other->CP0_EBase & ~mask) | (arg1 & mask);
1745 }
1746
1747 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1748 {
1749 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1750 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1751
1752 switch (idx) {
1753 case 0: return other->CP0_Config0;
1754 case 1: return other->CP0_Config1;
1755 case 2: return other->CP0_Config2;
1756 case 3: return other->CP0_Config3;
1757 /* 4 and 5 are reserved. */
1758 case 6: return other->CP0_Config6;
1759 case 7: return other->CP0_Config7;
1760 default:
1761 break;
1762 }
1763 return 0;
1764 }
1765
1766 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1767 {
1768 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1769 }
1770
1771 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1772 {
1773 /* tertiary/secondary caches not implemented */
1774 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1775 }
1776
1777 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1778 {
1779 if (env->insn_flags & ASE_MICROMIPS) {
1780 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1781 (arg1 & (1 << CP0C3_ISA_ON_EXC));
1782 }
1783 }
1784
1785 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1786 {
1787 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1788 (arg1 & env->CP0_Config4_rw_bitmask);
1789 }
1790
1791 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1792 {
1793 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1794 (arg1 & env->CP0_Config5_rw_bitmask);
1795 compute_hflags(env);
1796 }
1797
1798 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1799 {
1800 target_long mask = env->CP0_LLAddr_rw_bitmask;
1801 arg1 = arg1 << env->CP0_LLAddr_shift;
1802 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1803 }
1804
1805 #define MTC0_MAAR_MASK(env) \
1806 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1807
1808 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1809 {
1810 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1811 }
1812
1813 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1814 {
1815 env->CP0_MAAR[env->CP0_MAARI] =
1816 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1817 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1818 }
1819
1820 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1821 {
1822 int index = arg1 & 0x3f;
1823 if (index == 0x3f) {
1824 /* Software may write all ones to INDEX to determine the
1825 maximum value supported. */
1826 env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1827 } else if (index < MIPS_MAAR_MAX) {
1828 env->CP0_MAARI = index;
1829 }
1830 /* Other than the all ones, if the
1831 value written is not supported, then INDEX is unchanged
1832 from its previous value. */
1833 }
1834
1835 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1836 {
1837 /* Watch exceptions for instructions, data loads, data stores
1838 not implemented. */
1839 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1840 }
1841
1842 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1843 {
1844 int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
1845 env->CP0_WatchHi[sel] = arg1 & mask;
1846 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1847 }
1848
1849 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1850 {
1851 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1852 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1853 }
1854
1855 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1856 {
1857 env->CP0_Framemask = arg1; /* XXX */
1858 }
1859
1860 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1861 {
1862 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1863 if (arg1 & (1 << CP0DB_DM))
1864 env->hflags |= MIPS_HFLAG_DM;
1865 else
1866 env->hflags &= ~MIPS_HFLAG_DM;
1867 }
1868
1869 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1870 {
1871 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1872 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1873 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1874
1875 /* XXX: Might be wrong, check with EJTAG spec. */
1876 if (other_tc == other->current_tc)
1877 other->active_tc.CP0_Debug_tcstatus = val;
1878 else
1879 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1880 other->CP0_Debug = (other->CP0_Debug &
1881 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1882 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1883 }
1884
1885 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1886 {
1887 env->CP0_Performance0 = arg1 & 0x000007ff;
1888 }
1889
1890 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1891 {
1892 int32_t wst = arg1 & (1 << CP0EC_WST);
1893 int32_t spr = arg1 & (1 << CP0EC_SPR);
1894 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1895
1896 env->CP0_ErrCtl = wst | spr | itc;
1897
1898 if (itc && !wst && !spr) {
1899 env->hflags |= MIPS_HFLAG_ITC_CACHE;
1900 } else {
1901 env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1902 }
1903 }
1904
1905 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1906 {
1907 if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1908 /* If CACHE instruction is configured for ITC tags then make all
1909 CP0.TagLo bits writable. The actual write to ITC Configuration
1910 Tag will take care of the read-only bits. */
1911 env->CP0_TagLo = arg1;
1912 } else {
1913 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1914 }
1915 }
1916
1917 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1918 {
1919 env->CP0_DataLo = arg1; /* XXX */
1920 }
1921
1922 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1923 {
1924 env->CP0_TagHi = arg1; /* XXX */
1925 }
1926
1927 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1928 {
1929 env->CP0_DataHi = arg1; /* XXX */
1930 }
1931
1932 /* MIPS MT functions */
1933 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1934 {
1935 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1936 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1937
1938 if (other_tc == other->current_tc)
1939 return other->active_tc.gpr[sel];
1940 else
1941 return other->tcs[other_tc].gpr[sel];
1942 }
1943
1944 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1945 {
1946 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1947 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1948
1949 if (other_tc == other->current_tc)
1950 return other->active_tc.LO[sel];
1951 else
1952 return other->tcs[other_tc].LO[sel];
1953 }
1954
1955 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1956 {
1957 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1958 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1959
1960 if (other_tc == other->current_tc)
1961 return other->active_tc.HI[sel];
1962 else
1963 return other->tcs[other_tc].HI[sel];
1964 }
1965
1966 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1967 {
1968 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1969 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1970
1971 if (other_tc == other->current_tc)
1972 return other->active_tc.ACX[sel];
1973 else
1974 return other->tcs[other_tc].ACX[sel];
1975 }
1976
1977 target_ulong helper_mftdsp(CPUMIPSState *env)
1978 {
1979 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1980 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1981
1982 if (other_tc == other->current_tc)
1983 return other->active_tc.DSPControl;
1984 else
1985 return other->tcs[other_tc].DSPControl;
1986 }
1987
1988 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1989 {
1990 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1991 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1992
1993 if (other_tc == other->current_tc)
1994 other->active_tc.gpr[sel] = arg1;
1995 else
1996 other->tcs[other_tc].gpr[sel] = arg1;
1997 }
1998
1999 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2000 {
2001 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2002 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2003
2004 if (other_tc == other->current_tc)
2005 other->active_tc.LO[sel] = arg1;
2006 else
2007 other->tcs[other_tc].LO[sel] = arg1;
2008 }
2009
2010 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2011 {
2012 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2013 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2014
2015 if (other_tc == other->current_tc)
2016 other->active_tc.HI[sel] = arg1;
2017 else
2018 other->tcs[other_tc].HI[sel] = arg1;
2019 }
2020
2021 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2022 {
2023 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2024 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2025
2026 if (other_tc == other->current_tc)
2027 other->active_tc.ACX[sel] = arg1;
2028 else
2029 other->tcs[other_tc].ACX[sel] = arg1;
2030 }
2031
2032 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
2033 {
2034 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2035 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2036
2037 if (other_tc == other->current_tc)
2038 other->active_tc.DSPControl = arg1;
2039 else
2040 other->tcs[other_tc].DSPControl = arg1;
2041 }
2042
2043 /* MIPS MT functions */
2044 target_ulong helper_dmt(void)
2045 {
2046 // TODO
2047 return 0;
2048 }
2049
2050 target_ulong helper_emt(void)
2051 {
2052 // TODO
2053 return 0;
2054 }
2055
2056 target_ulong helper_dvpe(CPUMIPSState *env)
2057 {
2058 CPUState *other_cs = first_cpu;
2059 target_ulong prev = env->mvp->CP0_MVPControl;
2060
2061 CPU_FOREACH(other_cs) {
2062 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2063 /* Turn off all VPEs except the one executing the dvpe. */
2064 if (&other_cpu->env != env) {
2065 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
2066 mips_vpe_sleep(other_cpu);
2067 }
2068 }
2069 return prev;
2070 }
2071
2072 target_ulong helper_evpe(CPUMIPSState *env)
2073 {
2074 CPUState *other_cs = first_cpu;
2075 target_ulong prev = env->mvp->CP0_MVPControl;
2076
2077 CPU_FOREACH(other_cs) {
2078 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2079
2080 if (&other_cpu->env != env
2081 /* If the VPE is WFI, don't disturb its sleep. */
2082 && !mips_vpe_is_wfi(other_cpu)) {
2083 /* Enable the VPE. */
2084 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
2085 mips_vpe_wake(other_cpu); /* And wake it up. */
2086 }
2087 }
2088 return prev;
2089 }
2090 #endif /* !CONFIG_USER_ONLY */
2091
2092 void helper_fork(target_ulong arg1, target_ulong arg2)
2093 {
2094 // arg1 = rt, arg2 = rs
2095 // TODO: store to TC register
2096 }
2097
2098 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
2099 {
2100 target_long arg1 = arg;
2101
2102 if (arg1 < 0) {
2103 /* No scheduling policy implemented. */
2104 if (arg1 != -2) {
2105 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
2106 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
2107 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2108 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
2109 do_raise_exception(env, EXCP_THREAD, GETPC());
2110 }
2111 }
2112 } else if (arg1 == 0) {
2113 if (0 /* TODO: TC underflow */) {
2114 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2115 do_raise_exception(env, EXCP_THREAD, GETPC());
2116 } else {
2117 // TODO: Deallocate TC
2118 }
2119 } else if (arg1 > 0) {
2120 /* Yield qualifier inputs not implemented. */
2121 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2122 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
2123 do_raise_exception(env, EXCP_THREAD, GETPC());
2124 }
2125 return env->CP0_YQMask;
2126 }
2127
2128 /* R6 Multi-threading */
2129 #ifndef CONFIG_USER_ONLY
2130 target_ulong helper_dvp(CPUMIPSState *env)
2131 {
2132 CPUState *other_cs = first_cpu;
2133 target_ulong prev = env->CP0_VPControl;
2134
2135 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
2136 CPU_FOREACH(other_cs) {
2137 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2138 /* Turn off all VPs except the one executing the dvp. */
2139 if (&other_cpu->env != env) {
2140 mips_vpe_sleep(other_cpu);
2141 }
2142 }
2143 env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
2144 }
2145 return prev;
2146 }
2147
2148 target_ulong helper_evp(CPUMIPSState *env)
2149 {
2150 CPUState *other_cs = first_cpu;
2151 target_ulong prev = env->CP0_VPControl;
2152
2153 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
2154 CPU_FOREACH(other_cs) {
2155 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2156 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
2157 /* If the VP is WFI, don't disturb its sleep.
2158 * Otherwise, wake it up. */
2159 mips_vpe_wake(other_cpu);
2160 }
2161 }
2162 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
2163 }
2164 return prev;
2165 }
2166 #endif /* !CONFIG_USER_ONLY */
2167
2168 #ifndef CONFIG_USER_ONLY
2169 /* TLB management */
2170 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
2171 {
2172 /* Discard entries from env->tlb[first] onwards. */
2173 while (env->tlb->tlb_in_use > first) {
2174 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
2175 }
2176 }
2177
2178 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
2179 {
2180 #if defined(TARGET_MIPS64)
2181 return extract64(entrylo, 6, 54);
2182 #else
2183 return extract64(entrylo, 6, 24) | /* PFN */
2184 (extract64(entrylo, 32, 32) << 24); /* PFNX */
2185 #endif
2186 }
2187
2188 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
2189 {
2190 r4k_tlb_t *tlb;
2191 uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);
2192
2193 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
2194 tlb = &env->tlb->mmu.r4k.tlb[idx];
2195 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
2196 tlb->EHINV = 1;
2197 return;
2198 }
2199 tlb->EHINV = 0;
2200 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2201 #if defined(TARGET_MIPS64)
2202 tlb->VPN &= env->SEGMask;
2203 #endif
2204 tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2205 tlb->PageMask = env->CP0_PageMask;
2206 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2207 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
2208 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
2209 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
2210 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
2211 tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
2212 tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12;
2213 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
2214 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
2215 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
2216 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
2217 tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
2218 tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12;
2219 }
2220
2221 void r4k_helper_tlbinv(CPUMIPSState *env)
2222 {
2223 int idx;
2224 r4k_tlb_t *tlb;
2225 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2226
2227 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2228 tlb = &env->tlb->mmu.r4k.tlb[idx];
2229 if (!tlb->G && tlb->ASID == ASID) {
2230 tlb->EHINV = 1;
2231 }
2232 }
2233 cpu_mips_tlb_flush(env);
2234 }
2235
2236 void r4k_helper_tlbinvf(CPUMIPSState *env)
2237 {
2238 int idx;
2239
2240 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2241 env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
2242 }
2243 cpu_mips_tlb_flush(env);
2244 }
2245
2246 void r4k_helper_tlbwi(CPUMIPSState *env)
2247 {
2248 r4k_tlb_t *tlb;
2249 int idx;
2250 target_ulong VPN;
2251 uint16_t ASID;
2252 bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1;
2253
2254 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2255 tlb = &env->tlb->mmu.r4k.tlb[idx];
2256 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2257 #if defined(TARGET_MIPS64)
2258 VPN &= env->SEGMask;
2259 #endif
2260 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2261 EHINV = (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) != 0;
2262 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2263 V0 = (env->CP0_EntryLo0 & 2) != 0;
2264 D0 = (env->CP0_EntryLo0 & 4) != 0;
2265 XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) &1;
2266 RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) &1;
2267 V1 = (env->CP0_EntryLo1 & 2) != 0;
2268 D1 = (env->CP0_EntryLo1 & 4) != 0;
2269 XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1;
2270 RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1;
2271
2272 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2273 permissions on the current entry. */
2274 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
2275 (!tlb->EHINV && EHINV) ||
2276 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
2277 (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) ||
2278 (tlb->V1 && !V1) || (tlb->D1 && !D1) ||
2279 (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) {
2280 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2281 }
2282
2283 r4k_invalidate_tlb(env, idx, 0);
2284 r4k_fill_tlb(env, idx);
2285 }
2286
2287 void r4k_helper_tlbwr(CPUMIPSState *env)
2288 {
2289 int r = cpu_mips_get_random(env);
2290
2291 r4k_invalidate_tlb(env, r, 1);
2292 r4k_fill_tlb(env, r);
2293 }
2294
2295 void r4k_helper_tlbp(CPUMIPSState *env)
2296 {
2297 r4k_tlb_t *tlb;
2298 target_ulong mask;
2299 target_ulong tag;
2300 target_ulong VPN;
2301 uint16_t ASID;
2302 int i;
2303
2304 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2305 for (i = 0; i < env->tlb->nb_tlb; i++) {
2306 tlb = &env->tlb->mmu.r4k.tlb[i];
2307 /* 1k pages are not supported. */
2308 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2309 tag = env->CP0_EntryHi & ~mask;
2310 VPN = tlb->VPN & ~mask;
2311 #if defined(TARGET_MIPS64)
2312 tag &= env->SEGMask;
2313 #endif
2314 /* Check ASID, virtual page number & size */
2315 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
2316 /* TLB match */
2317 env->CP0_Index = i;
2318 break;
2319 }
2320 }
2321 if (i == env->tlb->nb_tlb) {
2322 /* No match. Discard any shadow entries, if any of them match. */
2323 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2324 tlb = &env->tlb->mmu.r4k.tlb[i];
2325 /* 1k pages are not supported. */
2326 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2327 tag = env->CP0_EntryHi & ~mask;
2328 VPN = tlb->VPN & ~mask;
2329 #if defined(TARGET_MIPS64)
2330 tag &= env->SEGMask;
2331 #endif
2332 /* Check ASID, virtual page number & size */
2333 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2334 r4k_mips_tlb_flush_extra (env, i);
2335 break;
2336 }
2337 }
2338
2339 env->CP0_Index |= 0x80000000;
2340 }
2341 }
2342
2343 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2344 {
2345 #if defined(TARGET_MIPS64)
2346 return tlb_pfn << 6;
2347 #else
2348 return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2349 (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2350 #endif
2351 }
2352
2353 void r4k_helper_tlbr(CPUMIPSState *env)
2354 {
2355 r4k_tlb_t *tlb;
2356 uint16_t ASID;
2357 int idx;
2358
2359 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2360 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2361 tlb = &env->tlb->mmu.r4k.tlb[idx];
2362
2363 /* If this will change the current ASID, flush qemu's TLB. */
2364 if (ASID != tlb->ASID)
2365 cpu_mips_tlb_flush(env);
2366
2367 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2368
2369 if (tlb->EHINV) {
2370 env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2371 env->CP0_PageMask = 0;
2372 env->CP0_EntryLo0 = 0;
2373 env->CP0_EntryLo1 = 0;
2374 } else {
2375 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2376 env->CP0_PageMask = tlb->PageMask;
2377 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2378 ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2379 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2380 get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2381 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2382 ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2383 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2384 get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2385 }
2386 }
2387
2388 void helper_tlbwi(CPUMIPSState *env)
2389 {
2390 env->tlb->helper_tlbwi(env);
2391 }
2392
2393 void helper_tlbwr(CPUMIPSState *env)
2394 {
2395 env->tlb->helper_tlbwr(env);
2396 }
2397
2398 void helper_tlbp(CPUMIPSState *env)
2399 {
2400 env->tlb->helper_tlbp(env);
2401 }
2402
2403 void helper_tlbr(CPUMIPSState *env)
2404 {
2405 env->tlb->helper_tlbr(env);
2406 }
2407
2408 void helper_tlbinv(CPUMIPSState *env)
2409 {
2410 env->tlb->helper_tlbinv(env);
2411 }
2412
2413 void helper_tlbinvf(CPUMIPSState *env)
2414 {
2415 env->tlb->helper_tlbinvf(env);
2416 }
2417
2418 /* Specials */
2419 target_ulong helper_di(CPUMIPSState *env)
2420 {
2421 target_ulong t0 = env->CP0_Status;
2422
2423 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2424 return t0;
2425 }
2426
2427 target_ulong helper_ei(CPUMIPSState *env)
2428 {
2429 target_ulong t0 = env->CP0_Status;
2430
2431 env->CP0_Status = t0 | (1 << CP0St_IE);
2432 return t0;
2433 }
2434
2435 static void debug_pre_eret(CPUMIPSState *env)
2436 {
2437 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2438 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2439 env->active_tc.PC, env->CP0_EPC);
2440 if (env->CP0_Status & (1 << CP0St_ERL))
2441 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2442 if (env->hflags & MIPS_HFLAG_DM)
2443 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2444 qemu_log("\n");
2445 }
2446 }
2447
2448 static void debug_post_eret(CPUMIPSState *env)
2449 {
2450 MIPSCPU *cpu = mips_env_get_cpu(env);
2451
2452 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2453 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2454 env->active_tc.PC, env->CP0_EPC);
2455 if (env->CP0_Status & (1 << CP0St_ERL))
2456 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2457 if (env->hflags & MIPS_HFLAG_DM)
2458 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2459 switch (cpu_mmu_index(env, false)) {
2460 case 3:
2461 qemu_log(", ERL\n");
2462 break;
2463 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2464 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2465 case MIPS_HFLAG_KM: qemu_log("\n"); break;
2466 default:
2467 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2468 break;
2469 }
2470 }
2471 }
2472
2473 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2474 {
2475 env->active_tc.PC = error_pc & ~(target_ulong)1;
2476 if (error_pc & 1) {
2477 env->hflags |= MIPS_HFLAG_M16;
2478 } else {
2479 env->hflags &= ~(MIPS_HFLAG_M16);
2480 }
2481 }
2482
2483 static inline void exception_return(CPUMIPSState *env)
2484 {
2485 debug_pre_eret(env);
2486 if (env->CP0_Status & (1 << CP0St_ERL)) {
2487 set_pc(env, env->CP0_ErrorEPC);
2488 env->CP0_Status &= ~(1 << CP0St_ERL);
2489 } else {
2490 set_pc(env, env->CP0_EPC);
2491 env->CP0_Status &= ~(1 << CP0St_EXL);
2492 }
2493 compute_hflags(env);
2494 debug_post_eret(env);
2495 }
2496
2497 void helper_eret(CPUMIPSState *env)
2498 {
2499 exception_return(env);
2500 env->lladdr = 1;
2501 }
2502
2503 void helper_eretnc(CPUMIPSState *env)
2504 {
2505 exception_return(env);
2506 }
2507
2508 void helper_deret(CPUMIPSState *env)
2509 {
2510 debug_pre_eret(env);
2511
2512 env->hflags &= ~MIPS_HFLAG_DM;
2513 compute_hflags(env);
2514
2515 set_pc(env, env->CP0_DEPC);
2516
2517 debug_post_eret(env);
2518 }
2519 #endif /* !CONFIG_USER_ONLY */
2520
2521 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
2522 {
2523 if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
2524 return;
2525 }
2526 do_raise_exception(env, EXCP_RI, pc);
2527 }
2528
2529 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2530 {
2531 check_hwrena(env, 0, GETPC());
2532 return env->CP0_EBase & 0x3ff;
2533 }
2534
2535 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2536 {
2537 check_hwrena(env, 1, GETPC());
2538 return env->SYNCI_Step;
2539 }
2540
2541 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2542 {
2543 int32_t count;
2544 check_hwrena(env, 2, GETPC());
2545 #ifdef CONFIG_USER_ONLY
2546 count = env->CP0_Count;
2547 #else
2548 qemu_mutex_lock_iothread();
2549 count = (int32_t)cpu_mips_get_count(env);
2550 qemu_mutex_unlock_iothread();
2551 #endif
2552 return count;
2553 }
2554
2555 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2556 {
2557 check_hwrena(env, 3, GETPC());
2558 return env->CCRes;
2559 }
2560
2561 target_ulong helper_rdhwr_performance(CPUMIPSState *env)
2562 {
2563 check_hwrena(env, 4, GETPC());
2564 return env->CP0_Performance0;
2565 }
2566
2567 target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
2568 {
2569 check_hwrena(env, 5, GETPC());
2570 return (env->CP0_Config5 >> CP0C5_XNP) & 1;
2571 }
2572
2573 void helper_pmon(CPUMIPSState *env, int function)
2574 {
2575 function /= 2;
2576 switch (function) {
2577 case 2: /* TODO: char inbyte(int waitflag); */
2578 if (env->active_tc.gpr[4] == 0)
2579 env->active_tc.gpr[2] = -1;
2580 /* Fall through */
2581 case 11: /* TODO: char inbyte (void); */
2582 env->active_tc.gpr[2] = -1;
2583 break;
2584 case 3:
2585 case 12:
2586 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2587 break;
2588 case 17:
2589 break;
2590 case 158:
2591 {
2592 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2593 printf("%s", fmt);
2594 }
2595 break;
2596 }
2597 }
2598
2599 void helper_wait(CPUMIPSState *env)
2600 {
2601 CPUState *cs = CPU(mips_env_get_cpu(env));
2602
2603 cs->halted = 1;
2604 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2605 /* Last instruction in the block, PC was updated before
2606 - no need to recover PC and icount */
2607 raise_exception(env, EXCP_HLT);
2608 }
2609
2610 #if !defined(CONFIG_USER_ONLY)
2611
2612 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2613 MMUAccessType access_type,
2614 int mmu_idx, uintptr_t retaddr)
2615 {
2616 MIPSCPU *cpu = MIPS_CPU(cs);
2617 CPUMIPSState *env = &cpu->env;
2618 int error_code = 0;
2619 int excp;
2620
2621 if (!(env->hflags & MIPS_HFLAG_DM)) {
2622 env->CP0_BadVAddr = addr;
2623 }
2624
2625 if (access_type == MMU_DATA_STORE) {
2626 excp = EXCP_AdES;
2627 } else {
2628 excp = EXCP_AdEL;
2629 if (access_type == MMU_INST_FETCH) {
2630 error_code |= EXCP_INST_NOTAVAIL;
2631 }
2632 }
2633
2634 do_raise_exception_err(env, excp, error_code, retaddr);
2635 }
2636
2637 void tlb_fill(CPUState *cs, target_ulong addr, int size,
2638 MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
2639 {
2640 int ret;
2641
2642 ret = mips_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
2643 if (ret) {
2644 MIPSCPU *cpu = MIPS_CPU(cs);
2645 CPUMIPSState *env = &cpu->env;
2646
2647 do_raise_exception_err(env, cs->exception_index,
2648 env->error_code, retaddr);
2649 }
2650 }
2651
2652 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2653 bool is_write, bool is_exec, int unused,
2654 unsigned size)
2655 {
2656 MIPSCPU *cpu = MIPS_CPU(cs);
2657 CPUMIPSState *env = &cpu->env;
2658
2659 /*
2660 * Raising an exception with KVM enabled will crash because it won't be from
2661 * the main execution loop so the longjmp won't have a matching setjmp.
2662 * Until we can trigger a bus error exception through KVM lets just ignore
2663 * the access.
2664 */
2665 if (kvm_enabled()) {
2666 return;
2667 }
2668
2669 if (is_exec) {
2670 raise_exception(env, EXCP_IBE);
2671 } else {
2672 raise_exception(env, EXCP_DBE);
2673 }
2674 }
2675 #endif /* !CONFIG_USER_ONLY */
2676
2677 /* Complex FPU operations which may need stack space. */
2678
2679 #define FLOAT_TWO32 make_float32(1 << 30)
2680 #define FLOAT_TWO64 make_float64(1ULL << 62)
2681
2682 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2683 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2684
2685 /* convert MIPS rounding mode in FCR31 to IEEE library */
2686 unsigned int ieee_rm[] = {
2687 float_round_nearest_even,
2688 float_round_to_zero,
2689 float_round_up,
2690 float_round_down
2691 };
2692
2693 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2694 {
2695 target_ulong arg1 = 0;
2696
2697 switch (reg) {
2698 case 0:
2699 arg1 = (int32_t)env->active_fpu.fcr0;
2700 break;
2701 case 1:
2702 /* UFR Support - Read Status FR */
2703 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2704 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2705 arg1 = (int32_t)
2706 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2707 } else {
2708 do_raise_exception(env, EXCP_RI, GETPC());
2709 }
2710 }
2711 break;
2712 case 5:
2713 /* FRE Support - read Config5.FRE bit */
2714 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2715 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2716 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2717 } else {
2718 helper_raise_exception(env, EXCP_RI);
2719 }
2720 }
2721 break;
2722 case 25:
2723 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2724 break;
2725 case 26:
2726 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2727 break;
2728 case 28:
2729 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2730 break;
2731 default:
2732 arg1 = (int32_t)env->active_fpu.fcr31;
2733 break;
2734 }
2735
2736 return arg1;
2737 }
2738
2739 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2740 {
2741 switch (fs) {
2742 case 1:
2743 /* UFR Alias - Reset Status FR */
2744 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2745 return;
2746 }
2747 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2748 env->CP0_Status &= ~(1 << CP0St_FR);
2749 compute_hflags(env);
2750 } else {
2751 do_raise_exception(env, EXCP_RI, GETPC());
2752 }
2753 break;
2754 case 4:
2755 /* UNFR Alias - Set Status FR */
2756 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2757 return;
2758 }
2759 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2760 env->CP0_Status |= (1 << CP0St_FR);
2761 compute_hflags(env);
2762 } else {
2763 do_raise_exception(env, EXCP_RI, GETPC());
2764 }
2765 break;
2766 case 5:
2767 /* FRE Support - clear Config5.FRE bit */
2768 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2769 return;
2770 }
2771 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2772 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2773 compute_hflags(env);
2774 } else {
2775 helper_raise_exception(env, EXCP_RI);
2776 }
2777 break;
2778 case 6:
2779 /* FRE Support - set Config5.FRE bit */
2780 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2781 return;
2782 }
2783 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2784 env->CP0_Config5 |= (1 << CP0C5_FRE);
2785 compute_hflags(env);
2786 } else {
2787 helper_raise_exception(env, EXCP_RI);
2788 }
2789 break;
2790 case 25:
2791 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2792 return;
2793 }
2794 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2795 ((arg1 & 0x1) << 23);
2796 break;
2797 case 26:
2798 if (arg1 & 0x007c0000)
2799 return;
2800 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2801 break;
2802 case 28:
2803 if (arg1 & 0x007c0000)
2804 return;
2805 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2806 ((arg1 & 0x4) << 22);
2807 break;
2808 case 31:
2809 env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
2810 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
2811 break;
2812 default:
2813 if (env->insn_flags & ISA_MIPS32R6) {
2814 do_raise_exception(env, EXCP_RI, GETPC());
2815 }
2816 return;
2817 }
2818 restore_fp_status(env);
2819 set_float_exception_flags(0, &env->active_fpu.fp_status);
2820 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2821 do_raise_exception(env, EXCP_FPE, GETPC());
2822 }
2823
2824 int ieee_ex_to_mips(int xcpt)
2825 {
2826 int ret = 0;
2827 if (xcpt) {
2828 if (xcpt & float_flag_invalid) {
2829 ret |= FP_INVALID;
2830 }
2831 if (xcpt & float_flag_overflow) {
2832 ret |= FP_OVERFLOW;
2833 }
2834 if (xcpt & float_flag_underflow) {
2835 ret |= FP_UNDERFLOW;
2836 }
2837 if (xcpt & float_flag_divbyzero) {
2838 ret |= FP_DIV0;
2839 }
2840 if (xcpt & float_flag_inexact) {
2841 ret |= FP_INEXACT;
2842 }
2843 }
2844 return ret;
2845 }
2846
2847 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2848 {
2849 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2850
2851 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2852
2853 if (tmp) {
2854 set_float_exception_flags(0, &env->active_fpu.fp_status);
2855
2856 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2857 do_raise_exception(env, EXCP_FPE, pc);
2858 } else {
2859 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2860 }
2861 }
2862 }
2863
2864 /* Float support.
2865 Single precition routines have a "s" suffix, double precision a
2866 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2867 paired single lower "pl", paired single upper "pu". */
2868
2869 /* unary operations, modifying fp status */
2870 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2871 {
2872 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2873 update_fcr31(env, GETPC());
2874 return fdt0;
2875 }
2876
2877 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2878 {
2879 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2880 update_fcr31(env, GETPC());
2881 return fst0;
2882 }
2883
2884 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2885 {
2886 uint64_t fdt2;
2887
2888 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2889 update_fcr31(env, GETPC());
2890 return fdt2;
2891 }
2892
2893 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2894 {
2895 uint64_t fdt2;
2896
2897 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2898 update_fcr31(env, GETPC());
2899 return fdt2;
2900 }
2901
2902 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2903 {
2904 uint64_t fdt2;
2905
2906 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2907 update_fcr31(env, GETPC());
2908 return fdt2;
2909 }
2910
2911 uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
2912 {
2913 uint64_t dt2;
2914
2915 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2916 if (get_float_exception_flags(&env->active_fpu.fp_status)
2917 & (float_flag_invalid | float_flag_overflow)) {
2918 dt2 = FP_TO_INT64_OVERFLOW;
2919 }
2920 update_fcr31(env, GETPC());
2921 return dt2;
2922 }
2923
2924 uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
2925 {
2926 uint64_t dt2;
2927
2928 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2929 if (get_float_exception_flags(&env->active_fpu.fp_status)
2930 & (float_flag_invalid | float_flag_overflow)) {
2931 dt2 = FP_TO_INT64_OVERFLOW;
2932 }
2933 update_fcr31(env, GETPC());
2934 return dt2;
2935 }
2936
2937 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2938 {
2939 uint32_t fst2;
2940 uint32_t fsth2;
2941
2942 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2943 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2944 update_fcr31(env, GETPC());
2945 return ((uint64_t)fsth2 << 32) | fst2;
2946 }
2947
2948 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2949 {
2950 uint32_t wt2;
2951 uint32_t wth2;
2952 int excp, excph;
2953
2954 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2955 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2956 if (excp & (float_flag_overflow | float_flag_invalid)) {
2957 wt2 = FP_TO_INT32_OVERFLOW;
2958 }
2959
2960 set_float_exception_flags(0, &env->active_fpu.fp_status);
2961 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2962 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2963 if (excph & (float_flag_overflow | float_flag_invalid)) {
2964 wth2 = FP_TO_INT32_OVERFLOW;
2965 }
2966
2967 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2968 update_fcr31(env, GETPC());
2969
2970 return ((uint64_t)wth2 << 32) | wt2;
2971 }
2972
2973 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2974 {
2975 uint32_t fst2;
2976
2977 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2978 update_fcr31(env, GETPC());
2979 return fst2;
2980 }
2981
2982 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2983 {
2984 uint32_t fst2;
2985
2986 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2987 update_fcr31(env, GETPC());
2988 return fst2;
2989 }
2990
2991 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2992 {
2993 uint32_t fst2;
2994
2995 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2996 update_fcr31(env, GETPC());
2997 return fst2;
2998 }
2999
3000 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
3001 {
3002 uint32_t wt2;
3003
3004 wt2 = wt0;
3005 update_fcr31(env, GETPC());
3006 return wt2;
3007 }
3008
3009 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
3010 {
3011 uint32_t wt2;
3012
3013 wt2 = wth0;
3014 update_fcr31(env, GETPC());
3015 return wt2;
3016 }
3017
3018 uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
3019 {
3020 uint32_t wt2;
3021
3022 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3023 if (get_float_exception_flags(&env->active_fpu.fp_status)
3024 & (float_flag_invalid | float_flag_overflow)) {
3025 wt2 = FP_TO_INT32_OVERFLOW;
3026 }
3027 update_fcr31(env, GETPC());
3028 return wt2;
3029 }
3030
3031 uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
3032 {
3033 uint32_t wt2;
3034
3035 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3036 if (get_float_exception_flags(&env->active_fpu.fp_status)
3037 & (float_flag_invalid | float_flag_overflow)) {
3038 wt2 = FP_TO_INT32_OVERFLOW;
3039 }
3040 update_fcr31(env, GETPC());
3041 return wt2;
3042 }
3043
3044 uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
3045 {
3046 uint64_t dt2;
3047
3048 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3049 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3050 restore_rounding_mode(env);
3051 if (get_float_exception_flags(&env->active_fpu.fp_status)
3052 & (float_flag_invalid | float_flag_overflow)) {
3053 dt2 = FP_TO_INT64_OVERFLOW;
3054 }
3055 update_fcr31(env, GETPC());
3056 return dt2;
3057 }
3058
3059 uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
3060 {
3061 uint64_t dt2;
3062
3063 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3064 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3065 restore_rounding_mode(env);
3066 if (get_float_exception_flags(&env->active_fpu.fp_status)
3067 & (float_flag_invalid | float_flag_overflow)) {
3068 dt2 = FP_TO_INT64_OVERFLOW;
3069 }
3070 update_fcr31(env, GETPC());
3071 return dt2;
3072 }
3073
3074 uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
3075 {
3076 uint32_t wt2;
3077
3078 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3079 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3080 restore_rounding_mode(env);
3081 if (get_float_exception_flags(&env->active_fpu.fp_status)
3082 & (float_flag_invalid | float_flag_overflow)) {
3083 wt2 = FP_TO_INT32_OVERFLOW;
3084 }
3085 update_fcr31(env, GETPC());
3086 return wt2;
3087 }
3088
3089 uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
3090 {
3091 uint32_t wt2;
3092
3093 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3094 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3095 restore_rounding_mode(env);
3096 if (get_float_exception_flags(&env->active_fpu.fp_status)
3097 & (float_flag_invalid | float_flag_overflow)) {
3098 wt2 = FP_TO_INT32_OVERFLOW;
3099 }
3100 update_fcr31(env, GETPC());
3101 return wt2;
3102 }
3103
3104 uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
3105 {
3106 uint64_t dt2;
3107
3108 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3109 if (get_float_exception_flags(&env->active_fpu.fp_status)
3110 & (float_flag_invalid | float_flag_overflow)) {
3111 dt2 = FP_TO_INT64_OVERFLOW;
3112 }
3113 update_fcr31(env, GETPC());
3114 return dt2;
3115 }
3116
3117 uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0)
3118 {
3119 uint64_t dt2;
3120
3121 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3122 if (get_float_exception_flags(&env->active_fpu.fp_status)
3123 & (float_flag_invalid | float_flag_overflow)) {
3124 dt2 = FP_TO_INT64_OVERFLOW;
3125 }
3126 update_fcr31(env, GETPC());
3127 return dt2;
3128 }
3129
3130 uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0)
3131 {
3132 uint32_t wt2;
3133
3134 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3135 if (get_float_exception_flags(&env->active_fpu.fp_status)
3136 & (float_flag_invalid | float_flag_overflow)) {
3137 wt2 = FP_TO_INT32_OVERFLOW;
3138 }
3139 update_fcr31(env, GETPC());
3140 return wt2;
3141 }
3142
3143 uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0)
3144 {
3145 uint32_t wt2;
3146
3147 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3148 if (get_float_exception_flags(&env->active_fpu.fp_status)
3149 & (float_flag_invalid | float_flag_overflow)) {
3150 wt2 = FP_TO_INT32_OVERFLOW;
3151 }
3152 update_fcr31(env, GETPC());
3153 return wt2;
3154 }
3155
3156 uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0)
3157 {
3158 uint64_t dt2;
3159
3160 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3161 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3162 restore_rounding_mode(env);
3163 if (get_float_exception_flags(&env->active_fpu.fp_status)
3164 & (float_flag_invalid | float_flag_overflow)) {
3165 dt2 = FP_TO_INT64_OVERFLOW;
3166 }
3167 update_fcr31(env, GETPC());
3168 return dt2;
3169 }
3170
3171 uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0)
3172 {
3173 uint64_t dt2;
3174
3175 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3176 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3177 restore_rounding_mode(env);
3178 if (get_float_exception_flags(&env->active_fpu.fp_status)
3179 & (float_flag_invalid | float_flag_overflow)) {
3180 dt2 = FP_TO_INT64_OVERFLOW;
3181 }
3182 update_fcr31(env, GETPC());
3183 return dt2;
3184 }
3185
3186 uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0)
3187 {
3188 uint32_t wt2;
3189
3190 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3191 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3192 restore_rounding_mode(env);
3193 if (get_float_exception_flags(&env->active_fpu.fp_status)
3194 & (float_flag_invalid | float_flag_overflow)) {
3195 wt2 = FP_TO_INT32_OVERFLOW;
3196 }
3197 update_fcr31(env, GETPC());
3198 return wt2;
3199 }
3200
3201 uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0)
3202 {
3203 uint32_t wt2;
3204
3205 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3206 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3207 restore_rounding_mode(env);
3208 if (get_float_exception_flags(&env->active_fpu.fp_status)
3209 & (float_flag_invalid | float_flag_overflow)) {
3210 wt2 = FP_TO_INT32_OVERFLOW;
3211 }
3212 update_fcr31(env, GETPC());
3213 return wt2;
3214 }
3215
3216 uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0)
3217 {
3218 uint64_t dt2;
3219
3220 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3221 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3222 restore_rounding_mode(env);
3223 if (get_float_exception_flags(&env->active_fpu.fp_status)
3224 & (float_flag_invalid | float_flag_overflow)) {
3225 dt2 = FP_TO_INT64_OVERFLOW;
3226 }
3227 update_fcr31(env, GETPC());
3228 return dt2;
3229 }
3230
3231 uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0)
3232 {
3233 uint64_t dt2;
3234
3235 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3236 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3237 restore_rounding_mode(env);
3238 if (get_float_exception_flags(&env->active_fpu.fp_status)
3239 & (float_flag_invalid | float_flag_overflow)) {
3240 dt2 = FP_TO_INT64_OVERFLOW;
3241 }
3242 update_fcr31(env, GETPC());
3243 return dt2;
3244 }
3245
3246 uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0)
3247 {
3248 uint32_t wt2;
3249
3250 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3251 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3252 restore_rounding_mode(env);
3253 if (get_float_exception_flags(&env->active_fpu.fp_status)
3254 & (float_flag_invalid | float_flag_overflow)) {
3255 wt2 = FP_TO_INT32_OVERFLOW;
3256 }
3257 update_fcr31(env, GETPC());
3258 return wt2;
3259 }
3260
3261 uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0)
3262 {
3263 uint32_t wt2;
3264
3265 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3266 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3267 restore_rounding_mode(env);
3268 if (get_float_exception_flags(&env->active_fpu.fp_status)
3269 & (float_flag_invalid | float_flag_overflow)) {
3270 wt2 = FP_TO_INT32_OVERFLOW;
3271 }
3272 update_fcr31(env, GETPC());
3273 return wt2;
3274 }
3275
3276 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3277 {
3278 uint64_t dt2;
3279
3280 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3281 if (get_float_exception_flags(&env->active_fpu.fp_status)
3282 & float_flag_invalid) {
3283 if (float64_is_any_nan(fdt0)) {
3284 dt2 = 0;
3285 }
3286 }
3287 update_fcr31(env, GETPC());
3288 return dt2;
3289 }
3290
3291 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3292 {
3293 uint64_t dt2;
3294
3295 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3296 if (get_float_exception_flags(&env->active_fpu.fp_status)
3297 & float_flag_invalid) {
3298 if (float32_is_any_nan(fst0)) {
3299 dt2 = 0;
3300 }
3301 }
3302 update_fcr31(env, GETPC());
3303 return dt2;
3304 }
3305
3306 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3307 {
3308 uint32_t wt2;
3309
3310 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3311 if (get_float_exception_flags(&env->active_fpu.fp_status)
3312 & float_flag_invalid) {
3313 if (float64_is_any_nan(fdt0)) {
3314 wt2 = 0;
3315 }
3316 }
3317 update_fcr31(env, GETPC());
3318 return wt2;
3319 }
3320
3321 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3322 {
3323 uint32_t wt2;
3324
3325 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3326 if (get_float_exception_flags(&env->active_fpu.fp_status)
3327 & float_flag_invalid) {
3328 if (float32_is_any_nan(fst0)) {
3329 wt2 = 0;
3330 }
3331 }
3332 update_fcr31(env, GETPC());
3333 return wt2;
3334 }
3335
3336 uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3337 {
3338 uint64_t dt2;
3339
3340 set_float_rounding_mode(float_round_nearest_even,
3341 &env->active_fpu.fp_status);
3342 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3343 restore_rounding_mode(env);
3344 if (get_float_exception_flags(&env->active_fpu.fp_status)
3345 & float_flag_invalid) {
3346 if (float64_is_any_nan(fdt0)) {
3347 dt2 = 0;
3348 }
3349 }
3350 update_fcr31(env, GETPC());
3351 return dt2;
3352 }
3353
3354 uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3355 {
3356 uint64_t dt2;
3357
3358 set_float_rounding_mode(float_round_nearest_even,
3359 &env->active_fpu.fp_status);
3360 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3361 restore_rounding_mode(env);
3362 if (get_float_exception_flags(&env->active_fpu.fp_status)
3363 & float_flag_invalid) {
3364 if (float32_is_any_nan(fst0)) {
3365 dt2 = 0;
3366 }
3367 }
3368 update_fcr31(env, GETPC());
3369 return dt2;
3370 }
3371
3372 uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3373 {
3374 uint32_t wt2;
3375
3376 set_float_rounding_mode(float_round_nearest_even,
3377 &env->active_fpu.fp_status);
3378 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3379 restore_rounding_mode(env);
3380 if (get_float_exception_flags(&env->active_fpu.fp_status)
3381 & float_flag_invalid) {
3382 if (float64_is_any_nan(fdt0)) {
3383 wt2 = 0;
3384 }
3385 }
3386 update_fcr31(env, GETPC());
3387 return wt2;
3388 }
3389
3390 uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3391 {
3392 uint32_t wt2;
3393
3394 set_float_rounding_mode(float_round_nearest_even,
3395 &env->active_fpu.fp_status);
3396 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3397 restore_rounding_mode(env);
3398 if (get_float_exception_flags(&env->active_fpu.fp_status)
3399 & float_flag_invalid) {
3400 if (float32_is_any_nan(fst0)) {
3401 wt2 = 0;
3402 }
3403 }
3404 update_fcr31(env, GETPC());
3405 return wt2;
3406 }
3407
3408 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3409 {
3410 uint64_t dt2;
3411
3412 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3413 if (get_float_exception_flags(&env->active_fpu.fp_status)
3414 & float_flag_invalid) {
3415 if (float64_is_any_nan(fdt0)) {
3416 dt2 = 0;
3417 }
3418 }
3419 update_fcr31(env, GETPC());
3420 return dt2;
3421 }
3422
3423 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3424 {
3425 uint64_t dt2;
3426
3427 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3428 if (get_float_exception_flags(&env->active_fpu.fp_status)
3429 & float_flag_invalid) {
3430 if (float32_is_any_nan(fst0)) {
3431 dt2 = 0;
3432 }
3433 }
3434 update_fcr31(env, GETPC());
3435 return dt2;
3436 }
3437
3438 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3439 {
3440 uint32_t wt2;
3441
3442 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3443 if (get_float_exception_flags(&env->active_fpu.fp_status)
3444 & float_flag_invalid) {
3445 if (float64_is_any_nan(fdt0)) {
3446 wt2 = 0;
3447 }
3448 }
3449 update_fcr31(env, GETPC());
3450 return wt2;
3451 }
3452
3453 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3454 {
3455 uint32_t wt2;
3456
3457 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3458 if (get_float_exception_flags(&env->active_fpu.fp_status)
3459 & float_flag_invalid) {
3460 if (float32_is_any_nan(fst0)) {
3461 wt2 = 0;
3462 }
3463 }
3464 update_fcr31(env, GETPC());
3465 return wt2;
3466 }
3467
3468 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3469 {
3470 uint64_t dt2;
3471
3472 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3473 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3474 restore_rounding_mode(env);
3475 if (get_float_exception_flags(&env->active_fpu.fp_status)
3476 & float_flag_invalid) {
3477 if (float64_is_any_nan(fdt0)) {
3478 dt2 = 0;
3479 }
3480 }
3481 update_fcr31(env, GETPC());
3482 return dt2;
3483 }
3484
3485 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3486 {
3487 uint64_t dt2;
3488
3489 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3490 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3491 restore_rounding_mode(env);
3492 if (get_float_exception_flags(&env->active_fpu.fp_status)
3493 & float_flag_invalid) {
3494 if (float32_is_any_nan(fst0)) {
3495 dt2 = 0;
3496 }
3497 }
3498 update_fcr31(env, GETPC());
3499 return dt2;
3500 }
3501
3502 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3503 {
3504 uint32_t wt2;
3505
3506 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3507 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3508 restore_rounding_mode(env);
3509 if (get_float_exception_flags(&env->active_fpu.fp_status)
3510 & float_flag_invalid) {
3511 if (float64_is_any_nan(fdt0)) {
3512 wt2 = 0;
3513 }
3514 }
3515 update_fcr31(env, GETPC());
3516 return wt2;
3517 }
3518
3519 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3520 {
3521 uint32_t wt2;
3522
3523 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3524 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3525 restore_rounding_mode(env);
3526 if (get_float_exception_flags(&env->active_fpu.fp_status)
3527 & float_flag_invalid) {
3528 if (float32_is_any_nan(fst0)) {
3529 wt2 = 0;
3530 }
3531 }
3532 update_fcr31(env, GETPC());
3533 return wt2;
3534 }
3535
3536 uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3537 {
3538 uint64_t dt2;
3539
3540 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3541 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3542 restore_rounding_mode(env);
3543 if (get_float_exception_flags(&env->active_fpu.fp_status)
3544 & float_flag_invalid) {
3545 if (float64_is_any_nan(fdt0)) {
3546 dt2 = 0;
3547 }
3548 }
3549 update_fcr31(env, GETPC());
3550 return dt2;
3551 }
3552
3553 uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3554 {
3555 uint64_t dt2;
3556
3557 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3558 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3559 restore_rounding_mode(env);
3560 if (get_float_exception_flags(&env->active_fpu.fp_status)
3561 & float_flag_invalid) {
3562 if (float32_is_any_nan(fst0)) {
3563 dt2 = 0;
3564 }
3565 }
3566 update_fcr31(env, GETPC());
3567 return dt2;
3568 }
3569
3570 uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3571 {
3572 uint32_t wt2;
3573
3574 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3575 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3576 restore_rounding_mode(env);
3577 if (get_float_exception_flags(&env->active_fpu.fp_status)
3578 & float_flag_invalid) {
3579 if (float64_is_any_nan(fdt0)) {
3580 wt2 = 0;
3581 }
3582 }
3583 update_fcr31(env, GETPC());
3584 return wt2;
3585 }
3586
3587 uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3588 {
3589 uint32_t wt2;
3590
3591 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3592 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3593 restore_rounding_mode(env);
3594 if (get_float_exception_flags(&env->active_fpu.fp_status)
3595 & float_flag_invalid) {
3596 if (float32_is_any_nan(fst0)) {
3597 wt2 = 0;
3598 }
3599 }
3600 update_fcr31(env, GETPC());
3601 return wt2;
3602 }
3603
3604 /* unary operations, not modifying fp status */
3605 #define FLOAT_UNOP(name) \
3606 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3607 { \
3608 return float64_ ## name(fdt0); \
3609 } \
3610 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3611 { \
3612 return float32_ ## name(fst0); \
3613 } \
3614 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3615 { \
3616 uint32_t wt0; \
3617 uint32_t wth0; \
3618 \
3619 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3620 wth0 = float32_ ## name(fdt0 >> 32); \
3621 return ((uint64_t)wth0 << 32) | wt0; \
3622 }
3623 FLOAT_UNOP(abs)
3624 FLOAT_UNOP(chs)
3625 #undef FLOAT_UNOP
3626
3627 /* MIPS specific unary operations */
3628 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3629 {
3630 uint64_t fdt2;
3631
3632 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3633 update_fcr31(env, GETPC());
3634 return fdt2;
3635 }
3636
3637 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3638 {
3639 uint32_t fst2;
3640
3641 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3642 update_fcr31(env, GETPC());
3643 return fst2;
3644 }
3645
3646 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3647 {
3648 uint64_t fdt2;
3649
3650 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3651 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3652 update_fcr31(env, GETPC());
3653 return fdt2;
3654 }
3655
3656 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3657 {
3658 uint32_t fst2;
3659
3660 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3661 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3662 update_fcr31(env, GETPC());
3663 return fst2;
3664 }
3665
3666 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3667 {
3668 uint64_t fdt2;
3669
3670 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3671 update_fcr31(env, GETPC());
3672 return fdt2;
3673 }
3674
3675 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3676 {
3677 uint32_t fst2;
3678
3679 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3680 update_fcr31(env, GETPC());
3681 return fst2;
3682 }
3683
3684 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3685 {
3686 uint32_t fst2;
3687 uint32_t fsth2;
3688
3689 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3690 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3691 update_fcr31(env, GETPC());
3692 return ((uint64_t)fsth2 << 32) | fst2;
3693 }
3694
3695 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3696 {
3697 uint64_t fdt2;
3698
3699 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3700 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3701 update_fcr31(env, GETPC());
3702 return fdt2;
3703 }
3704
3705 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3706 {
3707 uint32_t fst2;
3708
3709 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3710 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3711 update_fcr31(env, GETPC());
3712 return fst2;
3713 }
3714
3715 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3716 {
3717 uint32_t fst2;
3718 uint32_t fsth2;
3719
3720 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3721 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3722 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3723 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3724 update_fcr31(env, GETPC());
3725 return ((uint64_t)fsth2 << 32) | fst2;
3726 }
3727
3728 #define FLOAT_RINT(name, bits) \
3729 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3730 uint ## bits ## _t fs) \
3731 { \
3732 uint ## bits ## _t fdret; \
3733 \
3734 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3735 update_fcr31(env, GETPC()); \
3736 return fdret; \
3737 }
3738
3739 FLOAT_RINT(rint_s, 32)
3740 FLOAT_RINT(rint_d, 64)
3741 #undef FLOAT_RINT
3742
3743 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3744 #define FLOAT_CLASS_QUIET_NAN 0x002
3745 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3746 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3747 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3748 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3749 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3750 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3751 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3752 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3753
3754 #define FLOAT_CLASS(name, bits) \
3755 uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
3756 float_status *status) \
3757 { \
3758 if (float ## bits ## _is_signaling_nan(arg, status)) { \
3759 return FLOAT_CLASS_SIGNALING_NAN; \
3760 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
3761 return FLOAT_CLASS_QUIET_NAN; \
3762 } else if (float ## bits ## _is_neg(arg)) { \
3763 if (float ## bits ## _is_infinity(arg)) { \
3764 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3765 } else if (float ## bits ## _is_zero(arg)) { \
3766 return FLOAT_CLASS_NEGATIVE_ZERO; \
3767 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3768 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3769 } else { \
3770 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3771 } \
3772 } else { \
3773 if (float ## bits ## _is_infinity(arg)) { \
3774 return FLOAT_CLASS_POSITIVE_INFINITY; \
3775 } else if (float ## bits ## _is_zero(arg)) { \
3776 return FLOAT_CLASS_POSITIVE_ZERO; \
3777 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3778 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3779 } else { \
3780 return FLOAT_CLASS_POSITIVE_NORMAL; \
3781 } \
3782 } \
3783 } \
3784 \
3785 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3786 uint ## bits ## _t arg) \
3787 { \
3788 return float_ ## name(arg, &env->active_fpu.fp_status); \
3789 }
3790
3791 FLOAT_CLASS(class_s, 32)
3792 FLOAT_CLASS(class_d, 64)
3793 #undef FLOAT_CLASS
3794
3795 /* binary operations */
3796 #define FLOAT_BINOP(name) \
3797 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3798 uint64_t fdt0, uint64_t fdt1) \
3799 { \
3800 uint64_t dt2; \
3801 \
3802 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3803 update_fcr31(env, GETPC()); \
3804 return dt2; \
3805 } \
3806 \
3807 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3808 uint32_t fst0, uint32_t fst1) \
3809 { \
3810 uint32_t wt2; \
3811 \
3812 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3813 update_fcr31(env, GETPC()); \
3814 return wt2; \
3815 } \
3816 \
3817 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3818 uint64_t fdt0, \
3819 uint64_t fdt1) \
3820 { \
3821 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3822 uint32_t fsth0 = fdt0 >> 32; \
3823 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3824 uint32_t fsth1 = fdt1 >> 32; \
3825 uint32_t wt2; \
3826 uint32_t wth2; \
3827 \
3828 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3829 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3830 update_fcr31(env, GETPC()); \
3831 return ((uint64_t)wth2 << 32) | wt2; \
3832 }
3833
3834 FLOAT_BINOP(add)
3835 FLOAT_BINOP(sub)
3836 FLOAT_BINOP(mul)
3837 FLOAT_BINOP(div)
3838 #undef FLOAT_BINOP
3839
3840 /* MIPS specific binary operations */
3841 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3842 {
3843 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3844 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3845 update_fcr31(env, GETPC());
3846 return fdt2;
3847 }
3848
3849 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3850 {
3851 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3852 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3853 update_fcr31(env, GETPC());
3854 return fst2;
3855 }
3856
3857 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3858 {
3859 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3860 uint32_t fsth0 = fdt0 >> 32;
3861 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3862 uint32_t fsth2 = fdt2 >> 32;
3863
3864 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3865 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3866 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3867 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3868 update_fcr31(env, GETPC());
3869 return ((uint64_t)fsth2 << 32) | fst2;
3870 }
3871
3872 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3873 {
3874 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3875 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3876 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3877 update_fcr31(env, GETPC());
3878 return fdt2;
3879 }
3880
3881 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3882 {
3883 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3884 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3885 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3886 update_fcr31(env, GETPC());
3887 return fst2;
3888 }
3889
3890 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3891 {
3892 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3893 uint32_t fsth0 = fdt0 >> 32;
3894 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3895 uint32_t fsth2 = fdt2 >> 32;
3896
3897 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3898 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3899 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3900 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3901 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3902 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3903 update_fcr31(env, GETPC());
3904 return ((uint64_t)fsth2 << 32) | fst2;
3905 }
3906
3907 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3908 {
3909 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3910 uint32_t fsth0 = fdt0 >> 32;
3911 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3912 uint32_t fsth1 = fdt1 >> 32;
3913 uint32_t fst2;
3914 uint32_t fsth2;
3915
3916 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3917 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3918 update_fcr31(env, GETPC());
3919 return ((uint64_t)fsth2 << 32) | fst2;
3920 }
3921
3922 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3923 {
3924 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3925 uint32_t fsth0 = fdt0 >> 32;
3926 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3927 uint32_t fsth1 = fdt1 >> 32;
3928 uint32_t fst2;
3929 uint32_t fsth2;
3930
3931 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3932 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3933 update_fcr31(env, GETPC());
3934 return ((uint64_t)fsth2 << 32) | fst2;
3935 }
3936
3937 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3938 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3939 uint ## bits ## _t fs, \
3940 uint ## bits ## _t ft) \
3941 { \
3942 uint ## bits ## _t fdret; \
3943 \
3944 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3945 &env->active_fpu.fp_status); \
3946 update_fcr31(env, GETPC()); \
3947 return fdret; \
3948 }
3949
3950 FLOAT_MINMAX(max_s, 32, maxnum)
3951 FLOAT_MINMAX(max_d, 64, maxnum)
3952 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3953 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3954
3955 FLOAT_MINMAX(min_s, 32, minnum)
3956 FLOAT_MINMAX(min_d, 64, minnum)
3957 FLOAT_MINMAX(mina_s, 32, minnummag)
3958 FLOAT_MINMAX(mina_d, 64, minnummag)
3959 #undef FLOAT_MINMAX
3960
3961 /* ternary operations */
3962 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3963 { \
3964 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3965 if ((flags) & float_muladd_negate_c) { \
3966 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3967 } else { \
3968 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3969 } \
3970 if ((flags) & float_muladd_negate_result) { \
3971 a = prefix##_chs(a); \
3972 } \
3973 }
3974
3975 /* FMA based operations */
3976 #define FLOAT_FMA(name, type) \
3977 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3978 uint64_t fdt0, uint64_t fdt1, \
3979 uint64_t fdt2) \
3980 { \
3981 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
3982 update_fcr31(env, GETPC()); \
3983 return fdt0; \
3984 } \
3985 \
3986 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3987 uint32_t fst0, uint32_t fst1, \
3988 uint32_t fst2) \
3989 { \
3990 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3991 update_fcr31(env, GETPC()); \
3992 return fst0; \
3993 } \
3994 \
3995 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3996 uint64_t fdt0, uint64_t fdt1, \
3997 uint64_t fdt2) \
3998 { \
3999 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
4000 uint32_t fsth0 = fdt0 >> 32; \
4001 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
4002 uint32_t fsth1 = fdt1 >> 32; \
4003 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
4004 uint32_t fsth2 = fdt2 >> 32; \
4005 \
4006 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4007 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
4008 update_fcr31(env, GETPC()); \
4009 return ((uint64_t)fsth0 << 32) | fst0; \
4010 }
4011 FLOAT_FMA(madd, 0)
4012 FLOAT_FMA(msub, float_muladd_negate_c)
4013 FLOAT_FMA(nmadd, float_muladd_negate_result)
4014 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
4015 #undef FLOAT_FMA
4016
4017 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
4018 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
4019 uint ## bits ## _t fs, \
4020 uint ## bits ## _t ft, \
4021 uint ## bits ## _t fd) \
4022 { \
4023 uint ## bits ## _t fdret; \
4024 \
4025 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
4026 &env->active_fpu.fp_status); \
4027 update_fcr31(env, GETPC()); \
4028 return fdret; \
4029 }
4030
4031 FLOAT_FMADDSUB(maddf_s, 32, 0)
4032 FLOAT_FMADDSUB(maddf_d, 64, 0)
4033 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
4034 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
4035 #undef FLOAT_FMADDSUB
4036
4037 /* compare operations */
4038 #define FOP_COND_D(op, cond) \
4039 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4040 uint64_t fdt1, int cc) \
4041 { \
4042 int c; \
4043 c = cond; \
4044 update_fcr31(env, GETPC()); \
4045 if (c) \
4046 SET_FP_COND(cc, env->active_fpu); \
4047 else \
4048 CLEAR_FP_COND(cc, env->active_fpu); \
4049 } \
4050 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4051 uint64_t fdt1, int cc) \
4052 { \
4053 int c; \
4054 fdt0 = float64_abs(fdt0); \
4055 fdt1 = float64_abs(fdt1); \
4056 c = cond; \
4057 update_fcr31(env, GETPC()); \
4058 if (c) \
4059 SET_FP_COND(cc, env->active_fpu); \
4060 else \
4061 CLEAR_FP_COND(cc, env->active_fpu); \
4062 }
4063
4064 /* NOTE: the comma operator will make "cond" to eval to false,
4065 * but float64_unordered_quiet() is still called. */
4066 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4067 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
4068 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4069 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4070 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4071 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4072 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4073 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4074 /* NOTE: the comma operator will make "cond" to eval to false,
4075 * but float64_unordered() is still called. */
4076 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4077 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
4078 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
4079 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
4080 FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
4081 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
4082 FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
4083 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
4084
4085 #define FOP_COND_S(op, cond) \
4086 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4087 uint32_t fst1, int cc) \
4088 { \
4089 int c; \
4090 c = cond; \
4091 update_fcr31(env, GETPC()); \
4092 if (c) \
4093 SET_FP_COND(cc, env->active_fpu); \
4094 else \
4095 CLEAR_FP_COND(cc, env->active_fpu); \
4096 } \
4097 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4098 uint32_t fst1, int cc) \
4099 { \
4100 int c; \
4101 fst0 = float32_abs(fst0); \
4102 fst1 = float32_abs(fst1); \
4103 c = cond; \
4104 update_fcr31(env, GETPC()); \
4105 if (c) \
4106 SET_FP_COND(cc, env->active_fpu); \
4107 else \
4108 CLEAR_FP_COND(cc, env->active_fpu); \
4109 }
4110
4111 /* NOTE: the comma operator will make "cond" to eval to false,
4112 * but float32_unordered_quiet() is still called. */
4113 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
4114 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
4115 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
4116 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
4117 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
4118 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
4119 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
4120 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
4121 /* NOTE: the comma operator will make "cond" to eval to false,
4122 * but float32_unordered() is still called. */
4123 FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
4124 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
4125 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
4126 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
4127 FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
4128 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
4129 FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
4130 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
4131
4132 #define FOP_COND_PS(op, condl, condh) \
4133 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4134 uint64_t fdt1, int cc) \
4135 { \
4136 uint32_t fst0, fsth0, fst1, fsth1; \
4137 int ch, cl; \
4138 fst0 = fdt0 & 0XFFFFFFFF; \
4139 fsth0 = fdt0 >> 32; \
4140 fst1 = fdt1 & 0XFFFFFFFF; \
4141 fsth1 = fdt1 >> 32; \
4142 cl = condl; \
4143 ch = condh; \
4144 update_fcr31(env, GETPC()); \
4145 if (cl) \
4146 SET_FP_COND(cc, env->active_fpu); \
4147 else \
4148 CLEAR_FP_COND(cc, env->active_fpu); \
4149 if (ch) \
4150 SET_FP_COND(cc + 1, env->active_fpu); \
4151 else \
4152 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4153 } \
4154 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4155 uint64_t fdt1, int cc) \
4156 { \
4157 uint32_t fst0, fsth0, fst1, fsth1; \
4158 int ch, cl; \
4159 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
4160 fsth0 = float32_abs(fdt0 >> 32); \
4161 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
4162 fsth1 = float32_abs(fdt1 >> 32); \
4163 cl = condl; \
4164 ch = condh; \
4165 update_fcr31(env, GETPC()); \
4166 if (cl) \
4167 SET_FP_COND(cc, env->active_fpu); \
4168 else \
4169 CLEAR_FP_COND(cc, env->active_fpu); \
4170 if (ch) \
4171 SET_FP_COND(cc + 1, env->active_fpu); \
4172 else \
4173 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4174 }
4175
4176 /* NOTE: the comma operator will make "cond" to eval to false,
4177 * but float32_unordered_quiet() is still called. */
4178 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
4179 (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
4180 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
4181 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
4182 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
4183 float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4184 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
4185 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4186 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
4187 float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4188 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
4189 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4190 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
4191 float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4192 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
4193 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4194 /* NOTE: the comma operator will make "cond" to eval to false,
4195 * but float32_unordered() is still called. */
4196 FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
4197 (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
4198 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
4199 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
4200 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
4201 float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
4202 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
4203 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
4204 FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
4205 float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
4206 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
4207 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
4208 FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
4209 float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
4210 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
4211 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
4212
4213 /* R6 compare operations */
4214 #define FOP_CONDN_D(op, cond) \
4215 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
4216 uint64_t fdt1) \
4217 { \
4218 uint64_t c; \
4219 c = cond; \
4220 update_fcr31(env, GETPC()); \
4221 if (c) { \
4222 return -1; \
4223 } else { \
4224 return 0; \
4225 } \
4226 }
4227
4228 /* NOTE: the comma operator will make "cond" to eval to false,
4229 * but float64_unordered_quiet() is still called. */
4230 FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4231 FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
4232 FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4233 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4234 || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4235 FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4236 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4237 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4238 FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4239 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4240 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4241 /* NOTE: the comma operator will make "cond" to eval to false,
4242 * but float64_unordered() is still called. */
4243 FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4244 FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
4245 FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4246 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4247 || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4248 FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4249 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4250 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4251 FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4252 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4253 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4254 FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4255 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4256 FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4257 || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4258 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4259 FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4260 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4261 FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
4262 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4263 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4264 || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4265 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4266 FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4267 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4268
4269 #define FOP_CONDN_S(op, cond) \
4270 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
4271 uint32_t fst1) \
4272 { \
4273 uint64_t c; \
4274 c = cond; \
4275 update_fcr31(env, GETPC()); \
4276 if (c) { \
4277 return -1; \
4278 } else { \
4279 return 0; \
4280 } \
4281 }
4282
4283 /* NOTE: the comma operator will make "cond" to eval to false,
4284 * but float32_unordered_quiet() is still called. */
4285 FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
4286 FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
4287 FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4288 FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4289 || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4290 FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4291 FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4292 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4293 FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4294 FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4295 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4296 /* NOTE: the comma operator will make "cond" to eval to false,
4297 * but float32_unordered() is still called. */
4298 FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
4299 FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
4300 FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4301 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4302 || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4303 FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4304 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4305 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4306 FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4307 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4308 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4309 FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
4310 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4311 FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4312 || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4313 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4314 FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4315 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4316 FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status)
4317 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4318 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4319 || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4320 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4321 FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4322 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4323
4324 /* MSA */
4325 /* Data format min and max values */
4326 #define DF_BITS(df) (1 << ((df) + 3))
4327
4328 /* Element-by-element access macros */
4329 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4330
4331 #if !defined(CONFIG_USER_ONLY)
4332 #define MEMOP_IDX(DF) \
4333 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
4334 cpu_mmu_index(env, false));
4335 #else
4336 #define MEMOP_IDX(DF)
4337 #endif
4338
4339 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
4340 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4341 target_ulong addr) \
4342 { \
4343 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4344 wr_t wx; \
4345 int i; \
4346 MEMOP_IDX(DF) \
4347 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4348 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
4349 } \
4350 memcpy(pwd, &wx, sizeof(wr_t)); \
4351 }
4352
4353 #if !defined(CONFIG_USER_ONLY)
4354 MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETPC())
4355 MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETPC())
4356 MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETPC())
4357 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETPC())
4358 #else
4359 MSA_LD_DF(DF_BYTE, b, cpu_ldub_data)
4360 MSA_LD_DF(DF_HALF, h, cpu_lduw_data)
4361 MSA_LD_DF(DF_WORD, w, cpu_ldl_data)
4362 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
4363 #endif
4364
4365 #define MSA_PAGESPAN(x) \
4366 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
4367
4368 static inline void ensure_writable_pages(CPUMIPSState *env,
4369 target_ulong addr,
4370 int mmu_idx,
4371 uintptr_t retaddr)
4372 {
4373 #if !defined(CONFIG_USER_ONLY)
4374 target_ulong page_addr;
4375 if (unlikely(MSA_PAGESPAN(addr))) {
4376 /* first page */
4377 probe_write(env, addr, 0, mmu_idx, retaddr);
4378 /* second page */
4379 page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4380 probe_write(env, page_addr, 0, mmu_idx, retaddr);
4381 }
4382 #endif
4383 }
4384
4385 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
4386 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4387 target_ulong addr) \
4388 { \
4389 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4390 int mmu_idx = cpu_mmu_index(env, false); \
4391 int i; \
4392 MEMOP_IDX(DF) \
4393 ensure_writable_pages(env, addr, mmu_idx, GETPC()); \
4394 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4395 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
4396 } \
4397 }
4398
4399 #if !defined(CONFIG_USER_ONLY)
4400 MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETPC())
4401 MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETPC())
4402 MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETPC())
4403 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETPC())
4404 #else
4405 MSA_ST_DF(DF_BYTE, b, cpu_stb_data)
4406 MSA_ST_DF(DF_HALF, h, cpu_stw_data)
4407 MSA_ST_DF(DF_WORD, w, cpu_stl_data)
4408 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
4409 #endif
4410
4411 void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
4412 {
4413 #ifndef CONFIG_USER_ONLY
4414 target_ulong index = addr & 0x1fffffff;
4415 if (op == 9) {
4416 /* Index Store Tag */
4417 memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
4418 8, MEMTXATTRS_UNSPECIFIED);
4419 } else if (op == 5) {
4420 /* Index Load Tag */
4421 memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
4422 8, MEMTXATTRS_UNSPECIFIED);
4423 }
4424 #endif
4425 }
AR7 emulation for QEMU