target/mips/cpu.h

   1 #ifndef MIPS_CPU_H
   2 #define MIPS_CPU_H
   3
   4 #define ALIGNED_ONLY
   5
   6 #define CPUArchState struct CPUMIPSState
   7
   8 #include "qemu-common.h"
   9 #include "cpu-qom.h"
  10 #include "mips-defs.h"
  11 #include "exec/cpu-defs.h"
  12 #include "fpu/softfloat.h"
  13
  14 struct CPUMIPSState;
  15
  16 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  17
  18 /* MSA Context */
  19 #define MSA_WRLEN (128)
  20
  21 typedef union wr_t wr_t;
  22 union wr_t {
  23     int8_t  b[MSA_WRLEN/8];
  24     int16_t h[MSA_WRLEN/16];
  25     int32_t w[MSA_WRLEN/32];
  26     int64_t d[MSA_WRLEN/64];
  27 };
  28
  29 typedef union fpr_t fpr_t;
  30 union fpr_t {
  31     float64  fd;   /* ieee double precision */
  32     float32  fs[2];/* ieee single precision */
  33     uint64_t d;    /* binary double fixed-point */
  34     uint32_t w[2]; /* binary single fixed-point */
  35 /* FPU/MSA register mapping is not tested on big-endian hosts. */
  36     wr_t     wr;   /* vector data */
  37 };
  38 /* define FP_ENDIAN_IDX to access the same location
  39  * in the fpr_t union regardless of the host endianness
  40  */
  41 #if defined(HOST_WORDS_BIGENDIAN)
  42 #  define FP_ENDIAN_IDX 1
  43 #else
  44 #  define FP_ENDIAN_IDX 0
  45 #endif
  46
  47 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  48 struct CPUMIPSFPUContext {
  49     /* Floating point registers */
  50     fpr_t fpr[32];
  51     float_status fp_status;
  52     /* fpu implementation/revision register (fir) */
  53     uint32_t fcr0;
  54 #define FCR0_FREP 29
  55 #define FCR0_UFRP 28
  56 #define FCR0_HAS2008 23
  57 #define FCR0_F64 22
  58 #define FCR0_L 21
  59 #define FCR0_W 20
  60 #define FCR0_3D 19
  61 #define FCR0_PS 18
  62 #define FCR0_D 17
  63 #define FCR0_S 16
  64 #define FCR0_PRID 8
  65 #define FCR0_REV 0
  66     /* fcsr */
  67     uint32_t fcr31_rw_bitmask;
  68     uint32_t fcr31;
  69 #define FCR31_FS 24
  70 #define FCR31_ABS2008 19
  71 #define FCR31_NAN2008 18
  72 #define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  73 #define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  74 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
  75 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
  76 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
  77 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
  78 #define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
  79 #define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
  80 #define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
  81 #define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
  82 #define FP_INEXACT        1
  83 #define FP_UNDERFLOW      2
  84 #define FP_OVERFLOW       4
  85 #define FP_DIV0           8
  86 #define FP_INVALID        16
  87 #define FP_UNIMPLEMENTED  32
  88 };
  89
  90 #define NB_MMU_MODES 4
  91 #define TARGET_INSN_START_EXTRA_WORDS 2
  92
  93 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
  94 struct CPUMIPSMVPContext {
  95     int32_t CP0_MVPControl;
  96 #define CP0MVPCo_CPA    3
  97 #define CP0MVPCo_STLB   2
  98 #define CP0MVPCo_VPC    1
  99 #define CP0MVPCo_EVP    0
 100     int32_t CP0_MVPConf0;
 101 #define CP0MVPC0_M      31
 102 #define CP0MVPC0_TLBS   29
 103 #define CP0MVPC0_GS     28
 104 #define CP0MVPC0_PCP    27
 105 #define CP0MVPC0_PTLBE  16
 106 #define CP0MVPC0_TCA    15
 107 #define CP0MVPC0_PVPE   10
 108 #define CP0MVPC0_PTC    0
 109     int32_t CP0_MVPConf1;
 110 #define CP0MVPC1_CIM    31
 111 #define CP0MVPC1_CIF    30
 112 #define CP0MVPC1_PCX    20
 113 #define CP0MVPC1_PCP2   10
 114 #define CP0MVPC1_PCP1   0
 115 };
 116
 117 typedef struct mips_def_t mips_def_t;
 118
 119 #define MIPS_SHADOW_SET_MAX 16
 120 #define MIPS_TC_MAX 5
 121 #define MIPS_FPU_MAX 1
 122 #define MIPS_DSP_ACC 4
 123 #define MIPS_KSCRATCH_NUM 6
 124 #define MIPS_MAAR_MAX 16 /* Must be an even number. */
 125
 126 typedef struct TCState TCState;
 127 struct TCState {
 128     target_ulong gpr[32];
 129     target_ulong PC;
 130     target_ulong HI[MIPS_DSP_ACC];
 131     target_ulong LO[MIPS_DSP_ACC];
 132     target_ulong ACX[MIPS_DSP_ACC];
 133     target_ulong DSPControl;
 134     int32_t CP0_TCStatus;
 135 #define CP0TCSt_TCU3    31
 136 #define CP0TCSt_TCU2    30
 137 #define CP0TCSt_TCU1    29
 138 #define CP0TCSt_TCU0    28
 139 #define CP0TCSt_TMX     27
 140 #define CP0TCSt_RNST    23
 141 #define CP0TCSt_TDS     21
 142 #define CP0TCSt_DT      20
 143 #define CP0TCSt_DA      15
 144 #define CP0TCSt_A       13
 145 #define CP0TCSt_TKSU    11
 146 #define CP0TCSt_IXMT    10
 147 #define CP0TCSt_TASID   0
 148     int32_t CP0_TCBind;
 149 #define CP0TCBd_CurTC   21
 150 #define CP0TCBd_TBE     17
 151 #define CP0TCBd_CurVPE  0
 152     target_ulong CP0_TCHalt;
 153     target_ulong CP0_TCContext;
 154     target_ulong CP0_TCSchedule;
 155     target_ulong CP0_TCScheFBack;
 156     int32_t CP0_Debug_tcstatus;
 157     target_ulong CP0_UserLocal;
 158
 159     int32_t msacsr;
 160
 161 #define MSACSR_FS       24
 162 #define MSACSR_FS_MASK  (1 << MSACSR_FS)
 163 #define MSACSR_NX       18
 164 #define MSACSR_NX_MASK  (1 << MSACSR_NX)
 165 #define MSACSR_CEF      2
 166 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
 167 #define MSACSR_RM       0
 168 #define MSACSR_RM_MASK  (0x3 << MSACSR_RM)
 169 #define MSACSR_MASK     (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
 170         MSACSR_FS_MASK)
 171
 172     float_status msa_fp_status;
 173 };
 174
 175 typedef struct CPUMIPSState CPUMIPSState;
 176 struct CPUMIPSState {
 177     TCState active_tc;
 178     CPUMIPSFPUContext active_fpu;
 179
 180     uint32_t current_tc;
 181     uint32_t current_fpu;
 182
 183     uint32_t SEGBITS;
 184     uint32_t PABITS;
 185 #if defined(TARGET_MIPS64)
 186 # define PABITS_BASE 36
 187 #else
 188 # define PABITS_BASE 32
 189 #endif
 190     target_ulong SEGMask;
 191     uint64_t PAMask;
 192 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
 193
 194     int32_t msair;
 195 #define MSAIR_ProcID    8
 196 #define MSAIR_Rev       0
 197
 198 /*
 199  *     Summary of CP0 registers
 200  *     ========================
 201  *
 202  *
 203  *     Register 0        Register 1        Register 2        Register 3
 204  *     ----------        ----------        ----------        ----------
 205  *
 206  * 0   Index             Random            EntryLo0          EntryLo1
 207  * 1   MVPControl        VPEControl        TCStatus          GlobalNumber
 208  * 2   MVPConf0          VPEConf0          TCBind
 209  * 3   MVPConf1          VPEConf1          TCRestart
 210  * 4   VPControl         YQMask            TCHalt
 211  * 5                     VPESchedule       TCContext
 212  * 6                     VPEScheFBack      TCSchedule
 213  * 7                     VPEOpt            TCScheFBack       TCOpt
 214  *
 215  *
 216  *     Register 4        Register 5        Register 6        Register 7
 217  *     ----------        ----------        ----------        ----------
 218  *
 219  * 0   Context           PageMask          Wired             HWREna
 220  * 1   ContextConfig     PageGrain         SRSConf0
 221  * 2   UserLocal         SegCtl0           SRSConf1
 222  * 3   XContextConfig    SegCtl1           SRSConf2
 223  * 4   DebugContextID    SegCtl2           SRSConf3
 224  * 5   MemoryMapID       PWBase            SRSConf4
 225  * 6                     PWField           PWCtl
 226  * 7                     PWSize
 227  *
 228  *
 229  *     Register 8        Register 9        Register 10       Register 11
 230  *     ----------        ----------        -----------       -----------
 231  *
 232  * 0   BadVAddr          Count             EntryHi           Compare
 233  * 1   BadInstr
 234  * 2   BadInstrP
 235  * 3   BadInstrX
 236  * 4                                       GuestCtl1         GuestCtl0Ext
 237  * 5                                       GuestCtl2
 238  * 6                                       GuestCtl3
 239  * 7
 240  *
 241  *
 242  *     Register 12       Register 13       Register 14       Register 15
 243  *     -----------       -----------       -----------       -----------
 244  *
 245  * 0   Status            Cause             EPC               PRId
 246  * 1   IntCtl                                                EBase
 247  * 2   SRSCtl                              NestedEPC         CDMMBase
 248  * 3   SRSMap                                                CMGCRBase
 249  * 4   View_IPL          View_RIPL                           BEVVA
 250  * 5   SRSMap2           NestedExc
 251  * 6   GuestCtl0
 252  * 7   GTOffset
 253  *
 254  *
 255  *     Register 16       Register 17       Register 18       Register 19
 256  *     -----------       -----------       -----------       -----------
 257  *
 258  * 0   Config            LLAddr            WatchLo           WatchHi
 259  * 1   Config1           MAAR              WatchLo           WatchHi
 260  * 2   Config2           MAARI             WatchLo           WatchHi
 261  * 3   Config3                             WatchLo           WatchHi
 262  * 4   Config4                             WatchLo           WatchHi
 263  * 5   Config5                             WatchLo           WatchHi
 264  * 6                                       WatchLo           WatchHi
 265  * 7                                       WatchLo           WatchHi
 266  *
 267  *
 268  *     Register 20       Register 21       Register 22       Register 23
 269  *     -----------       -----------       -----------       -----------
 270  *
 271  * 0   XContext                                              Debug
 272  * 1                                                         TraceControl
 273  * 2                                                         TraceControl2
 274  * 3                                                         UserTraceData1
 275  * 4                                                         TraceIBPC
 276  * 5                                                         TraceDBPC
 277  * 6                                                         Debug2
 278  * 7
 279  *
 280  *
 281  *     Register 24       Register 25       Register 26       Register 27
 282  *     -----------       -----------       -----------       -----------
 283  *
 284  * 0   DEPC              PerfCnt            ErrCtl          CacheErr
 285  * 1                     PerfCnt
 286  * 2   TraceControl3     PerfCnt
 287  * 3   UserTraceData2    PerfCnt
 288  * 4                     PerfCnt
 289  * 5                     PerfCnt
 290  * 6                     PerfCnt
 291  * 7                     PerfCnt
 292  *
 293  *
 294  *     Register 28       Register 29       Register 30       Register 31
 295  *     -----------       -----------       -----------       -----------
 296  *
 297  * 0   DataLo            DataHi            ErrorEPC          DESAVE
 298  * 1   TagLo             TagHi
 299  * 2   DataLo            DataHi                              KScratch<n>
 300  * 3   TagLo             TagHi                               KScratch<n>
 301  * 4   DataLo            DataHi                              KScratch<n>
 302  * 5   TagLo             TagHi                               KScratch<n>
 303  * 6   DataLo            DataHi                              KScratch<n>
 304  * 7   TagLo             TagHi                               KScratch<n>
 305  *
 306  */
 307 /*
 308  * CP0 Register 0
 309  */
 310     int32_t CP0_Index;
 311     /* CP0_MVP* are per MVP registers. */
 312     int32_t CP0_VPControl;
 313 #define CP0VPCtl_DIS    0
 314 /*
 315  * CP0 Register 1
 316  */
 317     int32_t CP0_Random;
 318     int32_t CP0_VPEControl;
 319 #define CP0VPECo_YSI    21
 320 #define CP0VPECo_GSI    20
 321 #define CP0VPECo_EXCPT  16
 322 #define CP0VPECo_TE     15
 323 #define CP0VPECo_TargTC 0
 324     int32_t CP0_VPEConf0;
 325 #define CP0VPEC0_M      31
 326 #define CP0VPEC0_XTC    21
 327 #define CP0VPEC0_TCS    19
 328 #define CP0VPEC0_SCS    18
 329 #define CP0VPEC0_DSC    17
 330 #define CP0VPEC0_ICS    16
 331 #define CP0VPEC0_MVP    1
 332 #define CP0VPEC0_VPA    0
 333     int32_t CP0_VPEConf1;
 334 #define CP0VPEC1_NCX    20
 335 #define CP0VPEC1_NCP2   10
 336 #define CP0VPEC1_NCP1   0
 337     target_ulong CP0_YQMask;
 338     target_ulong CP0_VPESchedule;
 339     target_ulong CP0_VPEScheFBack;
 340     int32_t CP0_VPEOpt;
 341 #define CP0VPEOpt_IWX7  15
 342 #define CP0VPEOpt_IWX6  14
 343 #define CP0VPEOpt_IWX5  13
 344 #define CP0VPEOpt_IWX4  12
 345 #define CP0VPEOpt_IWX3  11
 346 #define CP0VPEOpt_IWX2  10
 347 #define CP0VPEOpt_IWX1  9
 348 #define CP0VPEOpt_IWX0  8
 349 #define CP0VPEOpt_DWX7  7
 350 #define CP0VPEOpt_DWX6  6
 351 #define CP0VPEOpt_DWX5  5
 352 #define CP0VPEOpt_DWX4  4
 353 #define CP0VPEOpt_DWX3  3
 354 #define CP0VPEOpt_DWX2  2
 355 #define CP0VPEOpt_DWX1  1
 356 #define CP0VPEOpt_DWX0  0
 357 /*
 358  * CP0 Register 2
 359  */
 360     uint64_t CP0_EntryLo0;
 361 /*
 362  * CP0 Register 3
 363  */
 364     uint64_t CP0_EntryLo1;
 365 #if defined(TARGET_MIPS64)
 366 # define CP0EnLo_RI 63
 367 # define CP0EnLo_XI 62
 368 #else
 369 # define CP0EnLo_RI 31
 370 # define CP0EnLo_XI 30
 371 #endif
 372     int32_t CP0_GlobalNumber;
 373 #define CP0GN_VPId 0
 374 /*
 375  * CP0 Register 4
 376  */
 377     target_ulong CP0_Context;
 378     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
 379 /*
 380  * CP0 Register 5
 381  */
 382     int32_t CP0_PageMask;
 383     int32_t CP0_PageGrain_rw_bitmask;
 384     int32_t CP0_PageGrain;
 385 #define CP0PG_RIE 31
 386 #define CP0PG_XIE 30
 387 #define CP0PG_ELPA 29
 388 #define CP0PG_IEC 27
 389     target_ulong CP0_SegCtl0;
 390     target_ulong CP0_SegCtl1;
 391     target_ulong CP0_SegCtl2;
 392 #define CP0SC_PA        9
 393 #define CP0SC_PA_MASK   (0x7FULL << CP0SC_PA)
 394 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA)
 395 #define CP0SC_AM        4
 396 #define CP0SC_AM_MASK   (0x7ULL << CP0SC_AM)
 397 #define CP0SC_AM_UK     0ULL
 398 #define CP0SC_AM_MK     1ULL
 399 #define CP0SC_AM_MSK    2ULL
 400 #define CP0SC_AM_MUSK   3ULL
 401 #define CP0SC_AM_MUSUK  4ULL
 402 #define CP0SC_AM_USK    5ULL
 403 #define CP0SC_AM_UUSK   7ULL
 404 #define CP0SC_EU        3
 405 #define CP0SC_EU_MASK   (1ULL << CP0SC_EU)
 406 #define CP0SC_C         0
 407 #define CP0SC_C_MASK    (0x7ULL << CP0SC_C)
 408 #define CP0SC_MASK      (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
 409                          CP0SC_PA_MASK)
 410 #define CP0SC_1GMASK    (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
 411                          CP0SC_PA_1GMASK)
 412 #define CP0SC0_MASK     (CP0SC_MASK | (CP0SC_MASK << 16))
 413 #define CP0SC1_XAM      59
 414 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM)
 415 #define CP0SC1_MASK     (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK)
 416 #define CP0SC2_XR       56
 417 #define CP0SC2_XR_MASK  (0xFFULL << CP0SC2_XR)
 418 #define CP0SC2_MASK     (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
 419     target_ulong CP0_PWBase;
 420     target_ulong CP0_PWField;
 421 #if defined(TARGET_MIPS64)
 422 #define CP0PF_BDI  32    /* 37..32 */
 423 #define CP0PF_GDI  24    /* 29..24 */
 424 #define CP0PF_UDI  18    /* 23..18 */
 425 #define CP0PF_MDI  12    /* 17..12 */
 426 #define CP0PF_PTI  6     /* 11..6  */
 427 #define CP0PF_PTEI 0     /*  5..0  */
 428 #else
 429 #define CP0PF_GDW  24    /* 29..24 */
 430 #define CP0PF_UDW  18    /* 23..18 */
 431 #define CP0PF_MDW  12    /* 17..12 */
 432 #define CP0PF_PTW  6     /* 11..6  */
 433 #define CP0PF_PTEW 0     /*  5..0  */
 434 #endif
 435     target_ulong CP0_PWSize;
 436 #if defined(TARGET_MIPS64)
 437 #define CP0PS_BDW  32    /* 37..32 */
 438 #endif
 439 #define CP0PS_PS   30
 440 #define CP0PS_GDW  24    /* 29..24 */
 441 #define CP0PS_UDW  18    /* 23..18 */
 442 #define CP0PS_MDW  12    /* 17..12 */
 443 #define CP0PS_PTW  6     /* 11..6  */
 444 #define CP0PS_PTEW 0     /*  5..0  */
 445 /*
 446  * CP0 Register 6
 447  */
 448     int32_t CP0_Wired;
 449     int32_t CP0_PWCtl;
 450 #define CP0PC_PWEN      31
 451 #if defined(TARGET_MIPS64)
 452 #define CP0PC_PWDIREXT  30
 453 #define CP0PC_XK        28
 454 #define CP0PC_XS        27
 455 #define CP0PC_XU        26
 456 #endif
 457 #define CP0PC_DPH       7
 458 #define CP0PC_HUGEPG    6
 459 #define CP0PC_PSN       0     /*  5..0  */
 460     int32_t CP0_SRSConf0_rw_bitmask;
 461     int32_t CP0_SRSConf0;
 462 #define CP0SRSC0_M      31
 463 #define CP0SRSC0_SRS3   20
 464 #define CP0SRSC0_SRS2   10
 465 #define CP0SRSC0_SRS1   0
 466     int32_t CP0_SRSConf1_rw_bitmask;
 467     int32_t CP0_SRSConf1;
 468 #define CP0SRSC1_M      31
 469 #define CP0SRSC1_SRS6   20
 470 #define CP0SRSC1_SRS5   10
 471 #define CP0SRSC1_SRS4   0
 472     int32_t CP0_SRSConf2_rw_bitmask;
 473     int32_t CP0_SRSConf2;
 474 #define CP0SRSC2_M      31
 475 #define CP0SRSC2_SRS9   20
 476 #define CP0SRSC2_SRS8   10
 477 #define CP0SRSC2_SRS7   0
 478     int32_t CP0_SRSConf3_rw_bitmask;
 479     int32_t CP0_SRSConf3;
 480 #define CP0SRSC3_M      31
 481 #define CP0SRSC3_SRS12  20
 482 #define CP0SRSC3_SRS11  10
 483 #define CP0SRSC3_SRS10  0
 484     int32_t CP0_SRSConf4_rw_bitmask;
 485     int32_t CP0_SRSConf4;
 486 #define CP0SRSC4_SRS15  20
 487 #define CP0SRSC4_SRS14  10
 488 #define CP0SRSC4_SRS13  0
 489 /*
 490  * CP0 Register 7
 491  */
 492     int32_t CP0_HWREna;
 493 /*
 494  * CP0 Register 8
 495  */
 496     target_ulong CP0_BadVAddr;
 497     uint32_t CP0_BadInstr;
 498     uint32_t CP0_BadInstrP;
 499     uint32_t CP0_BadInstrX;
 500 /*
 501  * CP0 Register 9
 502  */
 503     int32_t CP0_Count;
 504 /*
 505  * CP0 Register 10
 506  */
 507     target_ulong CP0_EntryHi;
 508 #define CP0EnHi_EHINV 10
 509     target_ulong CP0_EntryHi_ASID_mask;
 510 /*
 511  * CP0 Register 11
 512  */
 513     int32_t CP0_Compare;
 514 /*
 515  * CP0 Register 12
 516  */
 517     int32_t CP0_Status;
 518 #define CP0St_CU3   31
 519 #define CP0St_CU2   30
 520 #define CP0St_CU1   29
 521 #define CP0St_CU0   28
 522 #define CP0St_RP    27
 523 #define CP0St_FR    26
 524 #define CP0St_RE    25
 525 #define CP0St_MX    24
 526 #define CP0St_PX    23
 527 #define CP0St_BEV   22
 528 #define CP0St_TS    21
 529 #define CP0St_SR    20
 530 #define CP0St_NMI   19
 531 #define CP0St_IM    8
 532 #define CP0St_KX    7
 533 #define CP0St_SX    6
 534 #define CP0St_UX    5
 535 #define CP0St_KSU   3
 536 #define CP0St_ERL   2
 537 #define CP0St_EXL   1
 538 #define CP0St_IE    0
 539     int32_t CP0_IntCtl;
 540 #define CP0IntCtl_IPTI 29
 541 #define CP0IntCtl_IPPCI 26
 542 #define CP0IntCtl_VS 5
 543     int32_t CP0_SRSCtl;
 544 #define CP0SRSCtl_HSS 26
 545 #define CP0SRSCtl_EICSS 18
 546 #define CP0SRSCtl_ESS 12
 547 #define CP0SRSCtl_PSS 6
 548 #define CP0SRSCtl_CSS 0
 549     int32_t CP0_SRSMap;
 550 #define CP0SRSMap_SSV7 28
 551 #define CP0SRSMap_SSV6 24
 552 #define CP0SRSMap_SSV5 20
 553 #define CP0SRSMap_SSV4 16
 554 #define CP0SRSMap_SSV3 12
 555 #define CP0SRSMap_SSV2 8
 556 #define CP0SRSMap_SSV1 4
 557 #define CP0SRSMap_SSV0 0
 558 /*
 559  * CP0 Register 13
 560  */
 561     int32_t CP0_Cause;
 562 #define CP0Ca_BD   31
 563 #define CP0Ca_TI   30
 564 #define CP0Ca_CE   28
 565 #define CP0Ca_DC   27
 566 #define CP0Ca_PCI  26
 567 #define CP0Ca_IV   23
 568 #define CP0Ca_WP   22
 569 #define CP0Ca_IP    8
 570 #define CP0Ca_IP_mask 0x0000FF00
 571 #define CP0Ca_EC    2
 572 /*
 573  * CP0 Register 14
 574  */
 575     target_ulong CP0_EPC;
 576 /*
 577  * CP0 Register 15
 578  */
 579     int32_t CP0_PRid;
 580     target_ulong CP0_EBase;
 581     target_ulong CP0_EBaseWG_rw_bitmask;
 582 #define CP0EBase_WG 11
 583     target_ulong CP0_CMGCRBase;
 584 /*
 585  * CP0 Register 16
 586  */
 587     int32_t CP0_Config0;
 588 #define CP0C0_M    31
 589 #define CP0C0_K23  28    /* 30..28 */
 590 #define CP0C0_KU   25    /* 27..25 */
 591 #define CP0C0_MDU  20
 592 #define CP0C0_MM   18
 593 #define CP0C0_BM   16
 594 #define CP0C0_Impl 16    /* 24..16 */
 595 #define CP0C0_BE   15
 596 #define CP0C0_AT   13    /* 14..13 */
 597 #define CP0C0_AR   10    /* 12..10 */
 598 #define CP0C0_MT   7     /*  9..7  */
 599 #define CP0C0_VI   3
 600 #define CP0C0_K0   0     /*  2..0  */
 601     int32_t CP0_Config1;
 602 #define CP0C1_M    31
 603 #define CP0C1_MMU  25    /* 30..25 */
 604 #define CP0C1_IS   22    /* 24..22 */
 605 #define CP0C1_IL   19    /* 21..19 */
 606 #define CP0C1_IA   16    /* 18..16 */
 607 #define CP0C1_DS   13    /* 15..13 */
 608 #define CP0C1_DL   10    /* 12..10 */
 609 #define CP0C1_DA   7     /*  9..7  */
 610 #define CP0C1_C2   6
 611 #define CP0C1_MD   5
 612 #define CP0C1_PC   4
 613 #define CP0C1_WR   3
 614 #define CP0C1_CA   2
 615 #define CP0C1_EP   1
 616 #define CP0C1_FP   0
 617     int32_t CP0_Config2;
 618 #define CP0C2_M    31
 619 #define CP0C2_TU   28    /* 30..28 */
 620 #define CP0C2_TS   24    /* 27..24 */
 621 #define CP0C2_TL   20    /* 23..20 */
 622 #define CP0C2_TA   16    /* 19..16 */
 623 #define CP0C2_SU   12    /* 15..12 */
 624 #define CP0C2_SS   8     /* 11..8  */
 625 #define CP0C2_SL   4     /*  7..4  */
 626 #define CP0C2_SA   0     /*  3..0  */
 627     int32_t CP0_Config3;
 628 #define CP0C3_M            31
 629 #define CP0C3_BPG          30
 630 #define CP0C3_CMGCR        29
 631 #define CP0C3_MSAP         28
 632 #define CP0C3_BP           27
 633 #define CP0C3_BI           26
 634 #define CP0C3_SC           25
 635 #define CP0C3_PW           24
 636 #define CP0C3_VZ           23
 637 #define CP0C3_IPLV         21    /* 22..21 */
 638 #define CP0C3_MMAR         18    /* 20..18 */
 639 #define CP0C3_MCU          17
 640 #define CP0C3_ISA_ON_EXC   16
 641 #define CP0C3_ISA          14    /* 15..14 */
 642 #define CP0C3_ULRI         13
 643 #define CP0C3_RXI          12
 644 #define CP0C3_DSP2P        11
 645 #define CP0C3_DSPP         10
 646 #define CP0C3_CTXTC        9
 647 #define CP0C3_ITL          8
 648 #define CP0C3_LPA          7
 649 #define CP0C3_VEIC         6
 650 #define CP0C3_VInt         5
 651 #define CP0C3_SP           4
 652 #define CP0C3_CDMM         3
 653 #define CP0C3_MT           2
 654 #define CP0C3_SM           1
 655 #define CP0C3_TL           0
 656     int32_t CP0_Config4;
 657     int32_t CP0_Config4_rw_bitmask;
 658 #define CP0C4_M            31
 659 #define CP0C4_IE           29    /* 30..29 */
 660 #define CP0C4_AE           28
 661 #define CP0C4_VTLBSizeExt  24    /* 27..24 */
 662 #define CP0C4_KScrExist    16
 663 #define CP0C4_MMUExtDef    14
 664 #define CP0C4_FTLBPageSize 8     /* 12..8  */
 665 /* bit layout if MMUExtDef=1 */
 666 #define CP0C4_MMUSizeExt   0     /*  7..0  */
 667 /* bit layout if MMUExtDef=2 */
 668 #define CP0C4_FTLBWays     4     /*  7..4  */
 669 #define CP0C4_FTLBSets     0     /*  3..0  */
 670     int32_t CP0_Config5;
 671     int32_t CP0_Config5_rw_bitmask;
 672 #define CP0C5_M            31
 673 #define CP0C5_K            30
 674 #define CP0C5_CV           29
 675 #define CP0C5_EVA          28
 676 #define CP0C5_MSAEn        27
 677 #define CP0C5_PMJ          23    /* 25..23 */
 678 #define CP0C5_WR2          22
 679 #define CP0C5_NMS          21
 680 #define CP0C5_ULS          20
 681 #define CP0C5_XPA          19
 682 #define CP0C5_CRCP         18
 683 #define CP0C5_MI           17
 684 #define CP0C5_GI           15    /* 16..15 */
 685 #define CP0C5_CA2          14
 686 #define CP0C5_XNP          13
 687 #define CP0C5_DEC          11
 688 #define CP0C5_L2C          10
 689 #define CP0C5_UFE          9
 690 #define CP0C5_FRE          8
 691 #define CP0C5_VP           7
 692 #define CP0C5_SBRI         6
 693 #define CP0C5_MVH          5
 694 #define CP0C5_LLB          4
 695 #define CP0C5_MRP          3
 696 #define CP0C5_UFR          2
 697 #define CP0C5_NFExists     0
 698     int32_t CP0_Config6;
 699     int32_t CP0_Config7;
 700     uint64_t CP0_MAAR[MIPS_MAAR_MAX];
 701     int32_t CP0_MAARI;
 702     /* XXX: Maybe make LLAddr per-TC? */
 703 /*
 704  * CP0 Register 17
 705  */
 706     uint64_t lladdr;
 707     target_ulong llval;
 708     target_ulong llnewval;
 709     uint64_t llval_wp;
 710     uint32_t llnewval_wp;
 711     target_ulong llreg;
 712     uint64_t CP0_LLAddr_rw_bitmask;
 713     int CP0_LLAddr_shift;
 714 /*
 715  * CP0 Register 18
 716  */
 717     target_ulong CP0_WatchLo[8];
 718 /*
 719  * CP0 Register 19
 720  */
 721     int32_t CP0_WatchHi[8];
 722 #define CP0WH_ASID 16
 723 /*
 724  * CP0 Register 20
 725  */
 726     target_ulong CP0_XContext;
 727     int32_t CP0_Framemask;
 728 /*
 729  * CP0 Register 23
 730  */
 731     int32_t CP0_Debug;
 732 #define CP0DB_DBD  31
 733 #define CP0DB_DM   30
 734 #define CP0DB_LSNM 28
 735 #define CP0DB_Doze 27
 736 #define CP0DB_Halt 26
 737 #define CP0DB_CNT  25
 738 #define CP0DB_IBEP 24
 739 #define CP0DB_DBEP 21
 740 #define CP0DB_IEXI 20
 741 #define CP0DB_VER  15
 742 #define CP0DB_DEC  10
 743 #define CP0DB_SSt  8
 744 #define CP0DB_DINT 5
 745 #define CP0DB_DIB  4
 746 #define CP0DB_DDBS 3
 747 #define CP0DB_DDBL 2
 748 #define CP0DB_DBp  1
 749 #define CP0DB_DSS  0
 750 /*
 751  * CP0 Register 24
 752  */
 753     target_ulong CP0_DEPC;
 754 /*
 755  * CP0 Register 25
 756  */
 757     int32_t CP0_Performance0;
 758 /*
 759  * CP0 Register 26
 760  */
 761     int32_t CP0_ErrCtl;
 762 #define CP0EC_WST 29
 763 #define CP0EC_SPR 28
 764 #define CP0EC_ITC 26
 765 /*
 766  * CP0 Register 28
 767  */
 768     uint64_t CP0_TagLo;
 769     int32_t CP0_DataLo;
 770 /*
 771  * CP0 Register 29
 772  */
 773     int32_t CP0_TagHi;
 774     int32_t CP0_DataHi;
 775 /*
 776  * CP0 Register 30
 777  */
 778     target_ulong CP0_ErrorEPC;
 779 /*
 780  * CP0 Register 31
 781  */
 782     int32_t CP0_DESAVE;
 783
 784     /* We waste some space so we can handle shadow registers like TCs. */
 785     TCState tcs[MIPS_SHADOW_SET_MAX];
 786     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
 787     /* QEMU */
 788     int error_code;
 789 #define EXCP_TLB_NOMATCH   0x1
 790 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
 791     uint32_t hflags;    /* CPU State */
 792     /* TMASK defines different execution modes */
 793 #define MIPS_HFLAG_TMASK  0x1F5807FF
 794 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
 795     /* The KSU flags must be the lowest bits in hflags. The flag order
 796        must be the same as defined for CP0 Status. This allows to use
 797        the bits as the value of mmu_idx. */
 798 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
 799 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
 800 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
 801 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
 802 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
 803 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
 804 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
 805 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
 806 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
 807     /* True if the MIPS IV COP1X instructions can be used.  This also
 808        controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
 809        and RSQRT.D.  */
 810 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
 811 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
 812 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
 813 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
 814 #define MIPS_HFLAG_M16_SHIFT 10
 815     /* If translation is interrupted between the branch instruction and
 816      * the delay slot, record what type of branch it is so that we can
 817      * resume translation properly.  It might be possible to reduce
 818      * this from three bits to two.  */
 819 #define MIPS_HFLAG_BMASK_BASE  0x803800
 820 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
 821 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
 822 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
 823 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
 824     /* Extra flags about the current pending branch.  */
 825 #define MIPS_HFLAG_BMASK_EXT 0x7C000
 826 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
 827 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
 828 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
 829 #define MIPS_HFLAG_BDS_STRICT  0x20000 /* Strict delay slot size */
 830 #define MIPS_HFLAG_BX     0x40000 /* branch exchanges execution mode    */
 831 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
 832     /* MIPS DSP resources access. */
 833 #define MIPS_HFLAG_DSP    0x080000   /* Enable access to DSP resources.    */
 834 #define MIPS_HFLAG_DSP_R2 0x100000   /* Enable access to DSP R2 resources. */
 835 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */
 836     /* Extra flag about HWREna register. */
 837 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
 838 #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
 839 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot                   */
 840 #define MIPS_HFLAG_MSA   0x1000000
 841 #define MIPS_HFLAG_FRE   0x2000000 /* FRE enabled */
 842 #define MIPS_HFLAG_ELPA  0x4000000
 843 #define MIPS_HFLAG_ITC_CACHE  0x8000000 /* CACHE instr. operates on ITC tag */
 844 #define MIPS_HFLAG_ERL   0x10000000 /* error level flag */
 845     target_ulong btarget;        /* Jump / branch target               */
 846     target_ulong bcond;          /* Branch condition (if needed)       */
 847
 848     int SYNCI_Step; /* Address step size for SYNCI */
 849     int CCRes; /* Cycle count resolution/divisor */
 850     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
 851     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
 852     uint64_t insn_flags; /* Supported instruction set */
 853
 854     /* Fields up to this point are cleared by a CPU reset */
 855     struct {} end_reset_fields;
 856
 857     CPU_COMMON
 858
 859     /* Fields from here on are preserved across CPU reset. */
 860     CPUMIPSMVPContext *mvp;
 861 #if !defined(CONFIG_USER_ONLY)
 862     CPUMIPSTLBContext *tlb;
 863 #endif
 864
 865     const mips_def_t *cpu_model;
 866     void *irq[8];
 867     QEMUTimer *timer; /* Internal timer */
 868     MemoryRegion *itc_tag; /* ITC Configuration Tags */
 869     target_ulong exception_base; /* ExceptionBase input to the core */
 870 };
 871
 872 /**
 873  * MIPSCPU:
 874  * @env: #CPUMIPSState
 875  *
 876  * A MIPS CPU.
 877  */
 878 struct MIPSCPU {
 879     /*< private >*/
 880     CPUState parent_obj;
 881     /*< public >*/
 882
 883     CPUMIPSState env;
 884 };
 885
 886 static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
 887 {
 888     return container_of(env, MIPSCPU, env);
 889 }
 890
 891 #define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e))
 892
 893 #define ENV_OFFSET offsetof(MIPSCPU, env)
 894
 895 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 896
 897 #define cpu_signal_handler cpu_mips_signal_handler
 898 #define cpu_list mips_cpu_list
 899
 900 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
 901 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
 902
 903 /* MMU modes definitions. We carefully match the indices with our
 904    hflags layout. */
 905 #define MMU_MODE0_SUFFIX _kernel
 906 #define MMU_MODE1_SUFFIX _super
 907 #define MMU_MODE2_SUFFIX _user
 908 #define MMU_MODE3_SUFFIX _error
 909 #define MMU_USER_IDX 2
 910
 911 static inline int hflags_mmu_index(uint32_t hflags)
 912 {
 913     if (hflags & MIPS_HFLAG_ERL) {
 914         return 3; /* ERL */
 915     } else {
 916         return hflags & MIPS_HFLAG_KSU;
 917     }
 918 }
 919
 920 static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
 921 {
 922     return hflags_mmu_index(env->hflags);
 923 }
 924
 925 #include "exec/cpu-all.h"
 926
 927 /* Memory access type :
 928  * may be needed for precise access rights control and precise exceptions.
 929  */
 930 enum {
 931     /* 1 bit to define user level / supervisor access */
 932     ACCESS_USER  = 0x00,
 933     ACCESS_SUPER = 0x01,
 934     /* 1 bit to indicate direction */
 935     ACCESS_STORE = 0x02,
 936     /* Type of instruction that generated the access */
 937     ACCESS_CODE  = 0x10, /* Code fetch access                */
 938     ACCESS_INT   = 0x20, /* Integer load/store access        */
 939     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 940 };
 941
 942 /* Exceptions */
 943 enum {
 944     EXCP_NONE          = -1,
 945     EXCP_RESET         = 0,
 946     EXCP_SRESET,
 947     EXCP_DSS,
 948     EXCP_DINT,
 949     EXCP_DDBL,
 950     EXCP_DDBS,
 951     EXCP_NMI,
 952     EXCP_MCHECK,
 953     EXCP_EXT_INTERRUPT, /* 8 */
 954     EXCP_DFWATCH,
 955     EXCP_DIB,
 956     EXCP_IWATCH,
 957     EXCP_AdEL,
 958     EXCP_AdES,
 959     EXCP_TLBF,
 960     EXCP_IBE,
 961     EXCP_DBp, /* 16 */
 962     EXCP_SYSCALL,
 963     EXCP_BREAK,
 964     EXCP_CpU,
 965     EXCP_RI,
 966     EXCP_OVERFLOW,
 967     EXCP_TRAP,
 968     EXCP_FPE,
 969     EXCP_DWATCH, /* 24 */
 970     EXCP_LTLBL,
 971     EXCP_TLBL,
 972     EXCP_TLBS,
 973     EXCP_DBE,
 974     EXCP_THREAD,
 975     EXCP_MDMX,
 976     EXCP_C2E,
 977     EXCP_CACHE, /* 32 */
 978     EXCP_DSPDIS,
 979     EXCP_MSADIS,
 980     EXCP_MSAFPE,
 981     EXCP_TLBXI,
 982     EXCP_TLBRI,
 983
 984     EXCP_LAST = EXCP_TLBRI,
 985 };
 986 /* Dummy exception for conditional stores.  */
 987 #define EXCP_SC 0x100
 988
 989 /*
 990  * This is an internally generated WAKE request line.
 991  * It is driven by the CPU itself. Raised when the MT
 992  * block wants to wake a VPE from an inactive state and
 993  * cleared when VPE goes from active to inactive.
 994  */
 995 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
 996
 997 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 998
 999 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
1000 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
1001 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
1002
1003 bool cpu_supports_cps_smp(const char *cpu_type);
1004 bool cpu_supports_isa(const char *cpu_type, unsigned int isa);
1005 void cpu_set_exception_base(int vp_index, target_ulong address);
1006
1007 /* mips_int.c */
1008 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
1009
1010 /* helper.c */
1011 target_ulong exception_resume_pc (CPUMIPSState *env);
1012
1013 static inline void restore_snan_bit_mode(CPUMIPSState *env)
1014 {
1015     set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
1016                         &env->active_fpu.fp_status);
1017 }
1018
1019 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
1020                                         target_ulong *cs_base, uint32_t *flags)
1021 {
1022     *pc = env->active_tc.PC;
1023     *cs_base = 0;
1024     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
1025                             MIPS_HFLAG_HWRENA_ULR);
1026 }
1027
1028 #endif /* MIPS_CPU_H */