hw/block/pflash_cfi02.c

   1 /*
   2  *  CFI parallel flash with AMD command set emulation
   3  *
   4  *  Copyright (c) 2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /*
  21  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  22  * Supported commands/modes are:
  23  * - flash read
  24  * - flash write
  25  * - flash ID read
  26  * - sector erase
  27  * - chip erase
  28  * - unlock bypass command
  29  * - CFI queries
  30  *
  31  * It does not support flash interleaving.
  32  * It does not implement software data protection as found in many real chips
  33  * It does not implement erase suspend/resume commands
  34  * It does not implement multiple sectors erase
  35  */
  36
  37 #include "qemu/osdep.h"
  38 #include "hw/hw.h"
  39 #include "hw/block/block.h"
  40 #include "hw/block/flash.h"
  41 #include "qapi/error.h"
  42 #include "qemu/timer.h"
  43 #include "sysemu/block-backend.h"
  44 #include "qemu/host-utils.h"
  45 #include "qemu/module.h"
  46 #include "hw/sysbus.h"
  47 #include "trace.h"
  48
  49 #define PFLASH_DEBUG false
  50 #define DPRINTF(fmt, ...)                                  \
  51 do {                                                       \
  52     if (PFLASH_DEBUG) {                                    \
  53         fprintf(stderr, "PFLASH: " fmt, ## __VA_ARGS__);   \
  54     }                                                      \
  55 } while (0)
  56
  57 #define PFLASH_LAZY_ROMD_THRESHOLD 42
  58
  59 /*
  60  * The size of the cfi_table indirectly depends on this and the start of the
  61  * PRI table directly depends on it. 4 is the maximum size (and also what
  62  * seems common) without changing the PRT table address.
  63  */
  64 #define PFLASH_MAX_ERASE_REGIONS 4
  65
  66 /* Special write cycles for CFI queries. */
  67 enum {
  68     WCYCLE_CFI              = 7,
  69 };
  70
  71 struct PFlashCFI02 {
  72     /*< private >*/
  73     SysBusDevice parent_obj;
  74     /*< public >*/
  75
  76     BlockBackend *blk;
  77     uint32_t uniform_nb_blocs;
  78     uint32_t uniform_sector_len;
  79     uint32_t nb_blocs[PFLASH_MAX_ERASE_REGIONS];
  80     uint32_t sector_len[PFLASH_MAX_ERASE_REGIONS];
  81     uint32_t chip_len;
  82     uint8_t mappings;
  83     uint8_t width;
  84     uint8_t be;
  85     int wcycle; /* if 0, the flash is read normally */
  86     int bypass;
  87     int ro;
  88     uint8_t cmd;
  89     uint8_t status;
  90     /* FIXME: implement array device properties */
  91     uint16_t ident0;
  92     uint16_t ident1;
  93     uint16_t ident2;
  94     uint16_t ident3;
  95     uint16_t unlock_addr0;
  96     uint16_t unlock_addr1;
  97     uint8_t cfi_table[0x4d];
  98     QEMUTimer timer;
  99     /* The device replicates the flash memory across its memory space.  Emulate
 100      * that by having a container (.mem) filled with an array of aliases
 101      * (.mem_mappings) pointing to the flash memory (.orig_mem).
 102      */
 103     MemoryRegion mem;
 104     MemoryRegion *mem_mappings;    /* array; one per mapping */
 105     MemoryRegion orig_mem;
 106     int rom_mode;
 107     int read_counter; /* used for lazy switch-back to rom mode */
 108     char *name;
 109     void *storage;
 110 };
 111
 112 /*
 113  * Toggle status bit DQ7.
 114  */
 115 static inline void toggle_dq7(PFlashCFI02 *pfl)
 116 {
 117     pfl->status ^= 0x80;
 118 }
 119
 120 /*
 121  * Set status bit DQ7 to bit 7 of value.
 122  */
 123 static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value)
 124 {
 125     pfl->status &= 0x7F;
 126     pfl->status |= value & 0x80;
 127 }
 128
 129 /*
 130  * Toggle status bit DQ6.
 131  */
 132 static inline void toggle_dq6(PFlashCFI02 *pfl)
 133 {
 134     pfl->status ^= 0x40;
 135 }
 136
 137 /*
 138  * Set up replicated mappings of the same region.
 139  */
 140 static void pflash_setup_mappings(PFlashCFI02 *pfl)
 141 {
 142     unsigned i;
 143     hwaddr size = memory_region_size(&pfl->orig_mem);
 144
 145     memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size);
 146     pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
 147     for (i = 0; i < pfl->mappings; ++i) {
 148         memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl),
 149                                  "pflash-alias", &pfl->orig_mem, 0, size);
 150         memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
 151     }
 152 }
 153
 154 static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode)
 155 {
 156     memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode);
 157     pfl->rom_mode = rom_mode;
 158 }
 159
 160 static size_t pflash_regions_count(PFlashCFI02 *pfl)
 161 {
 162     return pfl->cfi_table[0x2c];
 163 }
 164
 165 static void pflash_timer (void *opaque)
 166 {
 167     PFlashCFI02 *pfl = opaque;
 168
 169     trace_pflash_timer_expired(pfl->cmd);
 170     /* Reset flash */
 171     toggle_dq7(pfl);
 172     if (pfl->bypass) {
 173         pfl->wcycle = 2;
 174     } else {
 175         pflash_register_memory(pfl, 1);
 176         pfl->wcycle = 0;
 177     }
 178     pfl->cmd = 0;
 179 }
 180
 181 /*
 182  * Read data from flash.
 183  */
 184 static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset,
 185                                  unsigned int width)
 186 {
 187     uint8_t *p = (uint8_t *)pfl->storage + offset;
 188     uint64_t ret = pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width);
 189     trace_pflash_data_read(offset, width << 1, ret);
 190     return ret;
 191 }
 192
 193 /*
 194  * offset should be a byte offset of the QEMU device and _not_ a device
 195  * offset.
 196  */
 197 static uint32_t pflash_sector_len(PFlashCFI02 *pfl, hwaddr offset)
 198 {
 199     assert(offset < pfl->chip_len);
 200     hwaddr addr = 0;
 201     for (int i = 0; i < pflash_regions_count(pfl); ++i) {
 202         uint64_t region_size = (uint64_t)pfl->nb_blocs[i] * pfl->sector_len[i];
 203         if (addr <= offset && offset < addr + region_size) {
 204             return pfl->sector_len[i];
 205         }
 206         addr += region_size;
 207     }
 208     abort();
 209 }
 210
 211 static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
 212 {
 213     PFlashCFI02 *pfl = opaque;
 214     hwaddr boff;
 215     uint64_t ret;
 216
 217     ret = -1;
 218     /* Lazy reset to ROMD mode after a certain amount of read accesses */
 219     if (!pfl->rom_mode && pfl->wcycle == 0 &&
 220         ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
 221         pflash_register_memory(pfl, 1);
 222     }
 223     offset &= pfl->chip_len - 1;
 224     boff = offset & 0xFF;
 225     if (pfl->width == 2) {
 226         boff = boff >> 1;
 227     } else if (pfl->width == 4) {
 228         boff = boff >> 2;
 229     }
 230     switch (pfl->cmd) {
 231     default:
 232         /* This should never happen : reset state & treat it as a read*/
 233         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 234         pfl->wcycle = 0;
 235         pfl->cmd = 0;
 236         /* fall through to the read code */
 237     case 0x80:
 238         /* We accept reads during second unlock sequence... */
 239     case 0x00:
 240         /* Flash area read */
 241         ret = pflash_data_read(pfl, offset, width);
 242         break;
 243     case 0x90:
 244         /* flash ID read */
 245         switch (boff) {
 246         case 0x00:
 247         case 0x01:
 248             ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
 249             break;
 250         case 0x02:
 251             ret = 0x00; /* Pretend all sectors are unprotected */
 252             break;
 253         case 0x0E:
 254         case 0x0F:
 255             ret = boff & 0x01 ? pfl->ident3 : pfl->ident2;
 256             if (ret != (uint8_t)-1) {
 257                 break;
 258             }
 259             /* Fall through to data read. */
 260         default:
 261             ret = pflash_data_read(pfl, offset, width);
 262         }
 263         DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__, boff, ret);
 264         break;
 265     case 0xA0:
 266     case 0x10:
 267     case 0x30:
 268         /* Status register read */
 269         ret = pfl->status;
 270         DPRINTF("%s: status %" PRIx64 "\n", __func__, ret);
 271         toggle_dq6(pfl);
 272         break;
 273     case 0x98:
 274         /* CFI query mode */
 275         if (boff < sizeof(pfl->cfi_table)) {
 276             ret = pfl->cfi_table[boff];
 277         } else {
 278             ret = 0;
 279         }
 280         break;
 281     }
 282     trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wcycle);
 283
 284     return ret;
 285 }
 286
 287 /* update flash content on disk */
 288 static void pflash_update(PFlashCFI02 *pfl, int offset, int size)
 289 {
 290     int offset_end;
 291     if (pfl->blk) {
 292         offset_end = offset + size;
 293         /* widen to sector boundaries */
 294         offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
 295         offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
 296         blk_pwrite(pfl->blk, offset, pfl->storage + offset,
 297                    offset_end - offset, 0);
 298     }
 299 }
 300
 301 static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
 302                          unsigned int width)
 303 {
 304     PFlashCFI02 *pfl = opaque;
 305     hwaddr boff;
 306     uint8_t *p;
 307     uint8_t cmd;
 308     uint32_t sector_len;
 309
 310     trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle);
 311     cmd = value;
 312     if (pfl->cmd != 0xA0 && cmd == 0xF0) {
 313         goto reset_flash;
 314     }
 315     offset &= pfl->chip_len - 1;
 316
 317     boff = offset;
 318     if (pfl->width == 2) {
 319         boff = boff >> 1;
 320     } else if (pfl->width == 4) {
 321         boff = boff >> 2;
 322     }
 323     /* Only the least-significant 11 bits are used in most cases. */
 324     boff &= 0x7FF;
 325     switch (pfl->wcycle) {
 326     case 0:
 327         /* Set the device in I/O access mode if required */
 328         if (pfl->rom_mode)
 329             pflash_register_memory(pfl, 0);
 330         pfl->read_counter = 0;
 331         /* We're in read mode */
 332     check_unlock0:
 333         if (boff == 0x55 && cmd == 0x98) {
 334         enter_CFI_mode:
 335             /* Enter CFI query mode */
 336             pfl->wcycle = WCYCLE_CFI;
 337             pfl->cmd = 0x98;
 338             return;
 339         }
 340         if (boff != pfl->unlock_addr0 || cmd != 0xAA) {
 341             DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n",
 342                     __func__, boff, cmd, pfl->unlock_addr0);
 343             goto reset_flash;
 344         }
 345         DPRINTF("%s: unlock sequence started\n", __func__);
 346         break;
 347     case 1:
 348         /* We started an unlock sequence */
 349     check_unlock1:
 350         if (boff != pfl->unlock_addr1 || cmd != 0x55) {
 351             DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__,
 352                     boff, cmd);
 353             goto reset_flash;
 354         }
 355         DPRINTF("%s: unlock sequence done\n", __func__);
 356         break;
 357     case 2:
 358         /* We finished an unlock sequence */
 359         if (!pfl->bypass && boff != pfl->unlock_addr0) {
 360             DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__,
 361                     boff, cmd);
 362             goto reset_flash;
 363         }
 364         switch (cmd) {
 365         case 0x20:
 366             pfl->bypass = 1;
 367             goto do_bypass;
 368         case 0x80:
 369         case 0x90:
 370         case 0xA0:
 371             pfl->cmd = cmd;
 372             DPRINTF("%s: starting command %02x\n", __func__, cmd);
 373             break;
 374         default:
 375             DPRINTF("%s: unknown command %02x\n", __func__, cmd);
 376             goto reset_flash;
 377         }
 378         break;
 379     case 3:
 380         switch (pfl->cmd) {
 381         case 0x80:
 382             /* We need another unlock sequence */
 383             goto check_unlock0;
 384         case 0xA0:
 385             trace_pflash_data_write(offset, width << 1, value, 0);
 386             if (!pfl->ro) {
 387                 p = (uint8_t *)pfl->storage + offset;
 388                 if (pfl->be) {
 389                     uint64_t current = ldn_be_p(p, width);
 390                     stn_be_p(p, width, current & value);
 391                 } else {
 392                     uint64_t current = ldn_le_p(p, width);
 393                     stn_le_p(p, width, current & value);
 394                 }
 395                 pflash_update(pfl, offset, width);
 396             }
 397             /*
 398              * While programming, status bit DQ7 should hold the opposite
 399              * value from how it was programmed.
 400              */
 401             set_dq7(pfl, ~value);
 402             /* Let's pretend write is immediate */
 403             if (pfl->bypass)
 404                 goto do_bypass;
 405             goto reset_flash;
 406         case 0x90:
 407             if (pfl->bypass && cmd == 0x00) {
 408                 /* Unlock bypass reset */
 409                 goto reset_flash;
 410             }
 411             /* We can enter CFI query mode from autoselect mode */
 412             if (boff == 0x55 && cmd == 0x98)
 413                 goto enter_CFI_mode;
 414             /* No break here */
 415         default:
 416             DPRINTF("%s: invalid write for command %02x\n",
 417                     __func__, pfl->cmd);
 418             goto reset_flash;
 419         }
 420     case 4:
 421         switch (pfl->cmd) {
 422         case 0xA0:
 423             /* Ignore writes while flash data write is occurring */
 424             /* As we suppose write is immediate, this should never happen */
 425             return;
 426         case 0x80:
 427             goto check_unlock1;
 428         default:
 429             /* Should never happen */
 430             DPRINTF("%s: invalid command state %02x (wc 4)\n",
 431                     __func__, pfl->cmd);
 432             goto reset_flash;
 433         }
 434         break;
 435     case 5:
 436         switch (cmd) {
 437         case 0x10:
 438             if (boff != pfl->unlock_addr0) {
 439                 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n",
 440                         __func__, offset);
 441                 goto reset_flash;
 442             }
 443             /* Chip erase */
 444             DPRINTF("%s: start chip erase\n", __func__);
 445             if (!pfl->ro) {
 446                 memset(pfl->storage, 0xff, pfl->chip_len);
 447                 pflash_update(pfl, 0, pfl->chip_len);
 448             }
 449             set_dq7(pfl, 0x00);
 450             /* Let's wait 5 seconds before chip erase is done */
 451             timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 452                       (NANOSECONDS_PER_SECOND * 5));
 453             break;
 454         case 0x30:
 455             /* Sector erase */
 456             p = pfl->storage;
 457             sector_len = pflash_sector_len(pfl, offset);
 458             offset &= ~(sector_len - 1);
 459             DPRINTF("%s: start sector erase at %0*" PRIx64 "-%0*" PRIx64 "\n",
 460                     __func__, pfl->width * 2, offset,
 461                     pfl->width * 2, offset + sector_len - 1);
 462             if (!pfl->ro) {
 463                 memset(p + offset, 0xff, sector_len);
 464                 pflash_update(pfl, offset, sector_len);
 465             }
 466             set_dq7(pfl, 0x00);
 467             /* Let's wait 1/2 second before sector erase is done */
 468             timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 469                       (NANOSECONDS_PER_SECOND / 2));
 470             break;
 471         default:
 472             DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
 473             goto reset_flash;
 474         }
 475         pfl->cmd = cmd;
 476         break;
 477     case 6:
 478         switch (pfl->cmd) {
 479         case 0x10:
 480             /* Ignore writes during chip erase */
 481             return;
 482         case 0x30:
 483             /* Ignore writes during sector erase */
 484             return;
 485         default:
 486             /* Should never happen */
 487             DPRINTF("%s: invalid command state %02x (wc 6)\n",
 488                     __func__, pfl->cmd);
 489             goto reset_flash;
 490         }
 491         break;
 492     /* Special values for CFI queries */
 493     case WCYCLE_CFI:
 494         DPRINTF("%s: invalid write in CFI query mode\n", __func__);
 495         goto reset_flash;
 496     default:
 497         /* Should never happen */
 498         DPRINTF("%s: invalid write state (wc 7)\n",  __func__);
 499         goto reset_flash;
 500     }
 501     pfl->wcycle++;
 502
 503     return;
 504
 505     /* Reset flash */
 506  reset_flash:
 507     trace_pflash_reset();
 508     pfl->bypass = 0;
 509     pfl->wcycle = 0;
 510     pfl->cmd = 0;
 511     return;
 512
 513  do_bypass:
 514     pfl->wcycle = 2;
 515     pfl->cmd = 0;
 516 }
 517
 518 static const MemoryRegionOps pflash_cfi02_ops = {
 519     .read = pflash_read,
 520     .write = pflash_write,
 521     .valid.min_access_size = 1,
 522     .valid.max_access_size = 4,
 523     .endianness = DEVICE_NATIVE_ENDIAN,
 524 };
 525
 526 static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
 527 {
 528     PFlashCFI02 *pfl = PFLASH_CFI02(dev);
 529     int ret;
 530     Error *local_err = NULL;
 531
 532     if (pfl->uniform_sector_len == 0 && pfl->sector_len[0] == 0) {
 533         error_setg(errp, "attribute \"sector-length\" not specified or zero.");
 534         return;
 535     }
 536     if (pfl->uniform_nb_blocs == 0 && pfl->nb_blocs[0] == 0) {
 537         error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
 538         return;
 539     }
 540     if (pfl->name == NULL) {
 541         error_setg(errp, "attribute \"name\" not specified.");
 542         return;
 543     }
 544
 545     int nb_regions;
 546     pfl->chip_len = 0;
 547     for (nb_regions = 0; nb_regions < PFLASH_MAX_ERASE_REGIONS; ++nb_regions) {
 548         if (pfl->nb_blocs[nb_regions] == 0) {
 549             break;
 550         }
 551         uint64_t sector_len_per_device = pfl->sector_len[nb_regions];
 552
 553         /*
 554          * The size of each flash sector must be a power of 2 and it must be
 555          * aligned at the same power of 2.
 556          */
 557         if (sector_len_per_device & 0xff ||
 558             sector_len_per_device >= (1 << 24) ||
 559             !is_power_of_2(sector_len_per_device))
 560         {
 561             error_setg(errp, "unsupported configuration: "
 562                        "sector length[%d] per device = %" PRIx64 ".",
 563                        nb_regions, sector_len_per_device);
 564             return;
 565         }
 566         if (pfl->chip_len & (sector_len_per_device - 1)) {
 567             error_setg(errp, "unsupported configuration: "
 568                        "flash region %d not correctly aligned.",
 569                        nb_regions);
 570             return;
 571         }
 572
 573         pfl->chip_len += (uint64_t)pfl->sector_len[nb_regions] *
 574                           pfl->nb_blocs[nb_regions];
 575     }
 576
 577     uint64_t uniform_len = (uint64_t)pfl->uniform_nb_blocs *
 578                            pfl->uniform_sector_len;
 579     if (nb_regions == 0) {
 580         nb_regions = 1;
 581         pfl->nb_blocs[0] = pfl->uniform_nb_blocs;
 582         pfl->sector_len[0] = pfl->uniform_sector_len;
 583         pfl->chip_len = uniform_len;
 584     } else if (uniform_len != 0 && uniform_len != pfl->chip_len) {
 585         error_setg(errp, "\"num-blocks\"*\"sector-length\" "
 586                    "different from \"num-blocks0\"*\'sector-length0\" + ... + "
 587                    "\"num-blocks3\"*\"sector-length3\"");
 588         return;
 589     }
 590
 591     memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl),
 592                                   &pflash_cfi02_ops, pfl, pfl->name,
 593                                   pfl->chip_len, &local_err);
 594     if (local_err) {
 595         error_propagate(errp, local_err);
 596         return;
 597     }
 598
 599     pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
 600
 601     if (pfl->blk) {
 602         uint64_t perm;
 603         pfl->ro = blk_is_read_only(pfl->blk);
 604         perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE);
 605         ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp);
 606         if (ret < 0) {
 607             return;
 608         }
 609     } else {
 610         pfl->ro = 0;
 611     }
 612
 613     if (pfl->blk) {
 614         if (!blk_check_size_and_read_all(pfl->blk, pfl->storage,
 615                                          pfl->chip_len, errp)) {
 616             vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl));
 617             return;
 618         }
 619     }
 620
 621     /* Only 11 bits are used in the comparison. */
 622     pfl->unlock_addr0 &= 0x7FF;
 623     pfl->unlock_addr1 &= 0x7FF;
 624
 625     pflash_setup_mappings(pfl);
 626     pfl->rom_mode = 1;
 627     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
 628
 629     timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
 630     pfl->wcycle = 0;
 631     pfl->cmd = 0;
 632     pfl->status = 0;
 633
 634     /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
 635     const uint16_t pri_ofs = 0x40;
 636     /* Standard "QRY" string */
 637     pfl->cfi_table[0x10] = 'Q';
 638     pfl->cfi_table[0x11] = 'R';
 639     pfl->cfi_table[0x12] = 'Y';
 640     /* Command set (AMD/Fujitsu) */
 641     pfl->cfi_table[0x13] = 0x02;
 642     pfl->cfi_table[0x14] = 0x00;
 643     /* Primary extended table address */
 644     pfl->cfi_table[0x15] = pri_ofs;
 645     pfl->cfi_table[0x16] = pri_ofs >> 8;
 646     /* Alternate command set (none) */
 647     pfl->cfi_table[0x17] = 0x00;
 648     pfl->cfi_table[0x18] = 0x00;
 649     /* Alternate extended table (none) */
 650     pfl->cfi_table[0x19] = 0x00;
 651     pfl->cfi_table[0x1A] = 0x00;
 652     /* Vcc min */
 653     pfl->cfi_table[0x1B] = 0x27;
 654     /* Vcc max */
 655     pfl->cfi_table[0x1C] = 0x36;
 656     /* Vpp min (no Vpp pin) */
 657     pfl->cfi_table[0x1D] = 0x00;
 658     /* Vpp max (no Vpp pin) */
 659     pfl->cfi_table[0x1E] = 0x00;
 660     /* Timeout per single byte/word write (128 ms) */
 661     pfl->cfi_table[0x1F] = 0x07;
 662     /* Timeout for min size buffer write (NA) */
 663     pfl->cfi_table[0x20] = 0x00;
 664     /* Typical timeout for block erase (512 ms) */
 665     pfl->cfi_table[0x21] = 0x09;
 666     /* Typical timeout for full chip erase (4096 ms) */
 667     pfl->cfi_table[0x22] = 0x0C;
 668     /* Reserved */
 669     pfl->cfi_table[0x23] = 0x01;
 670     /* Max timeout for buffer write (NA) */
 671     pfl->cfi_table[0x24] = 0x00;
 672     /* Max timeout for block erase */
 673     pfl->cfi_table[0x25] = 0x0A;
 674     /* Max timeout for chip erase */
 675     pfl->cfi_table[0x26] = 0x0D;
 676     /* Device size */
 677     pfl->cfi_table[0x27] = ctz32(pfl->chip_len);
 678     /* Flash device interface (8 & 16 bits) */
 679     pfl->cfi_table[0x28] = 0x02;
 680     pfl->cfi_table[0x29] = 0x00;
 681     /* Max number of bytes in multi-bytes write */
 682     /* XXX: disable buffered write as it's not supported */
 683     //    pfl->cfi_table[0x2A] = 0x05;
 684     pfl->cfi_table[0x2A] = 0x00;
 685     pfl->cfi_table[0x2B] = 0x00;
 686     /* Number of erase block regions */
 687     pfl->cfi_table[0x2c] = nb_regions;
 688     /* Erase block regions */
 689     for (int i = 0; i < nb_regions; ++i) {
 690         uint32_t sector_len_per_device = pfl->sector_len[i];
 691         pfl->cfi_table[0x2d + 4 * i] = pfl->nb_blocs[i] - 1;
 692         pfl->cfi_table[0x2e + 4 * i] = (pfl->nb_blocs[i] - 1) >> 8;
 693         pfl->cfi_table[0x2f + 4 * i] = sector_len_per_device >> 8;
 694         pfl->cfi_table[0x30 + 4 * i] = sector_len_per_device >> 16;
 695     }
 696     assert(0x2c + 4 * nb_regions < pri_ofs);
 697
 698     /* Extended */
 699     pfl->cfi_table[0x00 + pri_ofs] = 'P';
 700     pfl->cfi_table[0x01 + pri_ofs] = 'R';
 701     pfl->cfi_table[0x02 + pri_ofs] = 'I';
 702
 703     /* Extended version 1.0 */
 704     pfl->cfi_table[0x03 + pri_ofs] = '1';
 705     pfl->cfi_table[0x04 + pri_ofs] = '0';
 706
 707     /* Address sensitive unlock required. */
 708     pfl->cfi_table[0x05 + pri_ofs] = 0x00;
 709     /* Erase suspend not supported. */
 710     pfl->cfi_table[0x06 + pri_ofs] = 0x00;
 711     /* Sector protect not supported. */
 712     pfl->cfi_table[0x07 + pri_ofs] = 0x00;
 713     /* Temporary sector unprotect not supported. */
 714     pfl->cfi_table[0x08 + pri_ofs] = 0x00;
 715
 716     /* Sector protect/unprotect scheme. */
 717     pfl->cfi_table[0x09 + pri_ofs] = 0x00;
 718
 719     /* Simultaneous operation not supported. */
 720     pfl->cfi_table[0x0a + pri_ofs] = 0x00;
 721     /* Burst mode not supported. */
 722     pfl->cfi_table[0x0b + pri_ofs] = 0x00;
 723     /* Page mode not supported. */
 724     pfl->cfi_table[0x0c + pri_ofs] = 0x00;
 725     assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table));
 726 }
 727
 728 static Property pflash_cfi02_properties[] = {
 729     DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk),
 730     DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, uniform_nb_blocs, 0),
 731     DEFINE_PROP_UINT32("sector-length", PFlashCFI02, uniform_sector_len, 0),
 732     DEFINE_PROP_UINT32("num-blocks0", PFlashCFI02, nb_blocs[0], 0),
 733     DEFINE_PROP_UINT32("sector-length0", PFlashCFI02, sector_len[0], 0),
 734     DEFINE_PROP_UINT32("num-blocks1", PFlashCFI02, nb_blocs[1], 0),
 735     DEFINE_PROP_UINT32("sector-length1", PFlashCFI02, sector_len[1], 0),
 736     DEFINE_PROP_UINT32("num-blocks2", PFlashCFI02, nb_blocs[2], 0),
 737     DEFINE_PROP_UINT32("sector-length2", PFlashCFI02, sector_len[2], 0),
 738     DEFINE_PROP_UINT32("num-blocks3", PFlashCFI02, nb_blocs[3], 0),
 739     DEFINE_PROP_UINT32("sector-length3", PFlashCFI02, sector_len[3], 0),
 740     DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0),
 741     DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0),
 742     DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0),
 743     DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0),
 744     DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0),
 745     DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0),
 746     DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0),
 747     DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0),
 748     DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0),
 749     DEFINE_PROP_STRING("name", PFlashCFI02, name),
 750     DEFINE_PROP_END_OF_LIST(),
 751 };
 752
 753 static void pflash_cfi02_unrealize(DeviceState *dev, Error **errp)
 754 {
 755     PFlashCFI02 *pfl = PFLASH_CFI02(dev);
 756     timer_del(&pfl->timer);
 757 }
 758
 759 static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
 760 {
 761     DeviceClass *dc = DEVICE_CLASS(klass);
 762
 763     dc->realize = pflash_cfi02_realize;
 764     dc->unrealize = pflash_cfi02_unrealize;
 765     dc->props = pflash_cfi02_properties;
 766     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 767 }
 768
 769 static const TypeInfo pflash_cfi02_info = {
 770     .name           = TYPE_PFLASH_CFI02,
 771     .parent         = TYPE_SYS_BUS_DEVICE,
 772     .instance_size  = sizeof(PFlashCFI02),
 773     .class_init     = pflash_cfi02_class_init,
 774 };
 775
 776 static void pflash_cfi02_register_types(void)
 777 {
 778     type_register_static(&pflash_cfi02_info);
 779 }
 780
 781 type_init(pflash_cfi02_register_types)
 782
 783 PFlashCFI02 *pflash_cfi02_register(hwaddr base,
 784                                    const char *name,
 785                                    hwaddr size,
 786                                    BlockBackend *blk,
 787                                    uint32_t sector_len,
 788                                    int nb_mappings, int width,
 789                                    uint16_t id0, uint16_t id1,
 790                                    uint16_t id2, uint16_t id3,
 791                                    uint16_t unlock_addr0,
 792                                    uint16_t unlock_addr1,
 793                                    int be)
 794 {
 795     DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02);
 796
 797     if (blk) {
 798         qdev_prop_set_drive(dev, "drive", blk, &error_abort);
 799     }
 800     assert(size % sector_len == 0);
 801     qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
 802     qdev_prop_set_uint32(dev, "sector-length", sector_len);
 803     qdev_prop_set_uint8(dev, "width", width);
 804     qdev_prop_set_uint8(dev, "mappings", nb_mappings);
 805     qdev_prop_set_uint8(dev, "big-endian", !!be);
 806     qdev_prop_set_uint16(dev, "id0", id0);
 807     qdev_prop_set_uint16(dev, "id1", id1);
 808     qdev_prop_set_uint16(dev, "id2", id2);
 809     qdev_prop_set_uint16(dev, "id3", id3);
 810     qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
 811     qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
 812     qdev_prop_set_string(dev, "name", name);
 813     qdev_init_nofail(dev);
 814
 815     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 816     return PFLASH_CFI02(dev);
 817 }