include/hw/ppc/xics.h

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27 #if !defined(__XICS_H__)
  28 #define __XICS_H__
  29
  30 #include "hw/sysbus.h"
  31
  32 #define TYPE_XICS_COMMON "xics-common"
  33 #define XICS_COMMON(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_COMMON)
  34
  35 #define TYPE_XICS "xics"
  36 #define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS)
  37
  38 #define TYPE_KVM_XICS "xics-kvm"
  39 #define KVM_XICS(obj) OBJECT_CHECK(KVMXICSState, (obj), TYPE_KVM_XICS)
  40
  41 #define XICS_COMMON_CLASS(klass) \
  42      OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON)
  43 #define XICS_CLASS(klass) \
  44      OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS)
  45 #define XICS_COMMON_GET_CLASS(obj) \
  46      OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON)
  47 #define XICS_GET_CLASS(obj) \
  48      OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS)
  49
  50 #define XICS_IPI        0x2
  51 #define XICS_BUID       0x1
  52 #define XICS_IRQ_BASE   (XICS_BUID << 12)
  53
  54 /*
  55  * We currently only support one BUID which is our interrupt base
  56  * (the kernel implementation supports more but we don't exploit
  57  *  that yet)
  58  */
  59 typedef struct XICSStateClass XICSStateClass;
  60 typedef struct XICSState XICSState;
  61 typedef struct ICPStateClass ICPStateClass;
  62 typedef struct ICPState ICPState;
  63 typedef struct ICSStateClass ICSStateClass;
  64 typedef struct ICSState ICSState;
  65 typedef struct ICSIRQState ICSIRQState;
  66
  67 struct XICSStateClass {
  68     DeviceClass parent_class;
  69
  70     void (*cpu_setup)(XICSState *icp, PowerPCCPU *cpu);
  71     void (*set_nr_irqs)(XICSState *icp, uint32_t nr_irqs, Error **errp);
  72     void (*set_nr_servers)(XICSState *icp, uint32_t nr_servers, Error **errp);
  73 };
  74
  75 struct XICSState {
  76     /*< private >*/
  77     SysBusDevice parent_obj;
  78     /*< public >*/
  79     uint32_t nr_servers;
  80     uint32_t nr_irqs;
  81     ICPState *ss;
  82     ICSState *ics;
  83 };
  84
  85 #define TYPE_ICP "icp"
  86 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
  87
  88 #define TYPE_KVM_ICP "icp-kvm"
  89 #define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP)
  90
  91 #define ICP_CLASS(klass) \
  92      OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
  93 #define ICP_GET_CLASS(obj) \
  94      OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
  95
  96 struct ICPStateClass {
  97     DeviceClass parent_class;
  98
  99     void (*pre_save)(ICPState *s);
 100     int (*post_load)(ICPState *s, int version_id);
 101 };
 102
 103 struct ICPState {
 104     /*< private >*/
 105     DeviceState parent_obj;
 106     /*< public >*/
 107     CPUState *cs;
 108     uint32_t xirr;
 109     uint8_t pending_priority;
 110     uint8_t mfrr;
 111     qemu_irq output;
 112 };
 113
 114 #define TYPE_ICS "ics"
 115 #define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS)
 116
 117 #define TYPE_KVM_ICS "icskvm"
 118 #define KVM_ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_KVM_ICS)
 119
 120 #define ICS_CLASS(klass) \
 121      OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS)
 122 #define ICS_GET_CLASS(obj) \
 123      OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS)
 124
 125 struct ICSStateClass {
 126     DeviceClass parent_class;
 127
 128     void (*pre_save)(ICSState *s);
 129     int (*post_load)(ICSState *s, int version_id);
 130 };
 131
 132 struct ICSState {
 133     /*< private >*/
 134     DeviceState parent_obj;
 135     /*< public >*/
 136     uint32_t nr_irqs;
 137     uint32_t offset;
 138     qemu_irq *qirqs;
 139     ICSIRQState *irqs;
 140     XICSState *icp;
 141 };
 142
 143 struct ICSIRQState {
 144     uint32_t server;
 145     uint8_t priority;
 146     uint8_t saved_priority;
 147 #define XICS_STATUS_ASSERTED           0x1
 148 #define XICS_STATUS_SENT               0x2
 149 #define XICS_STATUS_REJECTED           0x4
 150 #define XICS_STATUS_MASKED_PENDING     0x8
 151     uint8_t status;
 152 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
 153 #define XICS_FLAGS_IRQ_LSI             0x1
 154 #define XICS_FLAGS_IRQ_MSI             0x2
 155 #define XICS_FLAGS_IRQ_MASK            0x3
 156     uint8_t flags;
 157 };
 158
 159 #define XICS_IRQS               1024
 160
 161 qemu_irq xics_get_qirq(XICSState *icp, int irq);
 162 void xics_set_irq_type(XICSState *icp, int irq, bool lsi);
 163 int xics_alloc(XICSState *icp, int src, int irq_hint, bool lsi);
 164 int xics_alloc_block(XICSState *icp, int src, int num, bool lsi, bool align);
 165 void xics_free(XICSState *icp, int irq, int num);
 166
 167 void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
 168
 169 #endif /* __XICS_H__ */