include/hw/ppc/ppc.h

   1 #ifndef HW_PPC_H
   2 #define HW_PPC_H 1
   3
   4 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
   5
   6 /* PowerPC hardware exceptions management helpers */
   7 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
   8 typedef struct clk_setup_t clk_setup_t;
   9 struct clk_setup_t {
  10     clk_setup_cb cb;
  11     void *opaque;
  12 };
  13 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
  14 {
  15     if (clk->cb != NULL)
  16         (*clk->cb)(clk->opaque, freq);
  17 }
  18
  19 struct ppc_tb_t {
  20     /* Time base management */
  21     int64_t  tb_offset;    /* Compensation                    */
  22     int64_t  atb_offset;   /* Compensation                    */
  23     uint32_t tb_freq;      /* TB frequency                    */
  24     /* Decrementer management */
  25     uint64_t decr_next;    /* Tick for next decr interrupt    */
  26     uint32_t decr_freq;    /* decrementer frequency           */
  27     QEMUTimer *decr_timer;
  28     /* Hypervisor decrementer management */
  29     uint64_t hdecr_next;    /* Tick for next hdecr interrupt  */
  30     QEMUTimer *hdecr_timer;
  31     uint64_t purr_load;
  32     uint64_t purr_start;
  33     void *opaque;
  34     uint32_t flags;
  35 };
  36
  37 /* PPC Timers flags */
  38 #define PPC_TIMER_BOOKE              (1 << 0) /* Enable Booke support */
  39 #define PPC_TIMER_E500               (1 << 1) /* Enable e500 support */
  40 #define PPC_DECR_UNDERFLOW_TRIGGERED (1 << 2) /* Decr interrupt triggered when
  41                                                * the most significant bit
  42                                                * changes from 0 to 1.
  43                                                */
  44 #define PPC_DECR_ZERO_TRIGGERED      (1 << 3) /* Decr interrupt triggered when
  45                                                * the decrementer reaches zero.
  46                                                */
  47 #define PPC_DECR_UNDERFLOW_LEVEL     (1 << 4) /* Decr interrupt active when
  48                                                * the most significant bit is 1.
  49                                                */
  50
  51 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
  52 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);
  53 /* Embedded PowerPC DCR management */
  54 typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
  55 typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
  56 int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn),
  57                   int (*dcr_write_error)(int dcrn));
  58 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
  59                       dcr_read_cb drc_read, dcr_write_cb dcr_write);
  60 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
  61                                   unsigned int decr_excp);
  62
  63 /* Embedded PowerPC reset */
  64 void ppc40x_core_reset(PowerPCCPU *cpu);
  65 void ppc40x_chip_reset(PowerPCCPU *cpu);
  66 void ppc40x_system_reset(PowerPCCPU *cpu);
  67 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
  68
  69 extern CPUWriteMemoryFunc * const PPC_io_write[];
  70 extern CPUReadMemoryFunc * const PPC_io_read[];
  71 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
  72
  73 void ppc40x_irq_init (CPUPPCState *env);
  74 void ppce500_irq_init (CPUPPCState *env);
  75 void ppc6xx_irq_init (CPUPPCState *env);
  76 void ppc970_irq_init (CPUPPCState *env);
  77 void ppcPOWER7_irq_init (CPUPPCState *env);
  78
  79 /* PPC machines for OpenBIOS */
  80 enum {
  81     ARCH_PREP = 0,
  82     ARCH_MAC99,
  83     ARCH_HEATHROW,
  84     ARCH_MAC99_U3,
  85 };
  86
  87 #define FW_CFG_PPC_WIDTH        (FW_CFG_ARCH_LOCAL + 0x00)
  88 #define FW_CFG_PPC_HEIGHT       (FW_CFG_ARCH_LOCAL + 0x01)
  89 #define FW_CFG_PPC_DEPTH        (FW_CFG_ARCH_LOCAL + 0x02)
  90 #define FW_CFG_PPC_TBFREQ       (FW_CFG_ARCH_LOCAL + 0x03)
  91 #define FW_CFG_PPC_CLOCKFREQ    (FW_CFG_ARCH_LOCAL + 0x04)
  92 #define FW_CFG_PPC_IS_KVM       (FW_CFG_ARCH_LOCAL + 0x05)
  93 #define FW_CFG_PPC_KVM_HC       (FW_CFG_ARCH_LOCAL + 0x06)
  94 #define FW_CFG_PPC_KVM_PID      (FW_CFG_ARCH_LOCAL + 0x07)
  95 #define FW_CFG_PPC_NVRAM_ADDR   (FW_CFG_ARCH_LOCAL + 0x08)
  96 #define FW_CFG_PPC_BUSFREQ      (FW_CFG_ARCH_LOCAL + 0x09)
  97
  98 #define PPC_SERIAL_MM_BAUDBASE 399193
  99
 100 /* ppc_booke.c */
 101 void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags);
 102
 103 #endif