2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qemu/datadir.h"
30 #include "qapi/error.h"
31 #include "qapi/qapi-events-machine.h"
32 #include "qapi/visitor.h"
33 #include "sysemu/sysemu.h"
34 #include "sysemu/hostmem.h"
35 #include "sysemu/numa.h"
36 #include "sysemu/qtest.h"
37 #include "sysemu/reset.h"
38 #include "sysemu/runstate.h"
40 #include "hw/fw-path-provider.h"
43 #include "sysemu/device_tree.h"
44 #include "sysemu/cpus.h"
45 #include "sysemu/hw_accel.h"
47 #include "migration/misc.h"
48 #include "migration/qemu-file-types.h"
49 #include "migration/global_state.h"
50 #include "migration/register.h"
51 #include "migration/blocker.h"
52 #include "mmu-hash64.h"
53 #include "mmu-book3s-v3.h"
54 #include "cpu-models.h"
55 #include "hw/core/cpu.h"
57 #include "hw/boards.h"
58 #include "hw/ppc/ppc.h"
59 #include "hw/loader.h"
61 #include "hw/ppc/fdt.h"
62 #include "hw/ppc/spapr.h"
63 #include "hw/ppc/spapr_vio.h"
64 #include "hw/qdev-properties.h"
65 #include "hw/pci-host/spapr.h"
66 #include "hw/pci/msi.h"
68 #include "hw/pci/pci.h"
69 #include "hw/scsi/scsi.h"
70 #include "hw/virtio/virtio-scsi.h"
71 #include "hw/virtio/vhost-scsi-common.h"
73 #include "exec/address-spaces.h"
74 #include "exec/ram_addr.h"
76 #include "qemu/config-file.h"
77 #include "qemu/error-report.h"
80 #include "hw/intc/intc.h"
82 #include "hw/ppc/spapr_cpu_core.h"
83 #include "hw/mem/memory-device.h"
84 #include "hw/ppc/spapr_tpm_proxy.h"
85 #include "hw/ppc/spapr_nvdimm.h"
86 #include "hw/ppc/spapr_numa.h"
87 #include "hw/ppc/pef.h"
89 #include "monitor/monitor.h"
93 /* SLOF memory layout:
95 * SLOF raw image loaded at 0, copies its romfs right below the flat
96 * device-tree, then position SLOF itself 31M below that
98 * So we set FW_OVERHEAD to 40MB which should account for all of that
101 * We load our kernel at 4M, leaving space for SLOF initial image
103 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
104 #define FW_MAX_SIZE 0x400000
105 #define FW_FILE_NAME "slof.bin"
106 #define FW_OVERHEAD 0x2800000
107 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
109 #define MIN_RMA_SLOF (128 * MiB)
111 #define PHANDLE_INTC 0x00001111
113 /* These two functions implement the VCPU id numbering: one to compute them
114 * all and one to identify thread 0 of a VCORE. Any change to the first one
115 * is likely to have an impact on the second one, so let's keep them close.
117 static int spapr_vcpu_id(SpaprMachineState
*spapr
, int cpu_index
)
119 MachineState
*ms
= MACHINE(spapr
);
120 unsigned int smp_threads
= ms
->smp
.threads
;
124 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
126 static bool spapr_is_thread0_in_vcore(SpaprMachineState
*spapr
,
130 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
133 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
135 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
136 * and newer QEMUs don't even have them. In both cases, we don't want
137 * to send anything on the wire.
142 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
143 .name
= "icp/server",
145 .minimum_version_id
= 1,
146 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
147 .fields
= (VMStateField
[]) {
148 VMSTATE_UNUSED(4), /* uint32_t xirr */
149 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
150 VMSTATE_UNUSED(1), /* uint8_t mfrr */
151 VMSTATE_END_OF_LIST()
155 static void pre_2_10_vmstate_register_dummy_icp(int i
)
157 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
158 (void *)(uintptr_t) i
);
161 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
163 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
164 (void *)(uintptr_t) i
);
167 int spapr_max_server_number(SpaprMachineState
*spapr
)
169 MachineState
*ms
= MACHINE(spapr
);
172 return DIV_ROUND_UP(ms
->smp
.max_cpus
* spapr
->vsmt
, ms
->smp
.threads
);
175 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
179 uint32_t servers_prop
[smt_threads
];
180 uint32_t gservers_prop
[smt_threads
* 2];
181 int index
= spapr_get_vcpu_id(cpu
);
183 if (cpu
->compat_pvr
) {
184 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
190 /* Build interrupt servers and gservers properties */
191 for (i
= 0; i
< smt_threads
; i
++) {
192 servers_prop
[i
] = cpu_to_be32(index
+ i
);
193 /* Hack, direct the group queues back to cpu 0 */
194 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
195 gservers_prop
[i
*2 + 1] = 0;
197 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
198 servers_prop
, sizeof(servers_prop
));
202 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
203 gservers_prop
, sizeof(gservers_prop
));
208 static void spapr_dt_pa_features(SpaprMachineState
*spapr
,
210 void *fdt
, int offset
)
212 uint8_t pa_features_206
[] = { 6, 0,
213 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
214 uint8_t pa_features_207
[] = { 24, 0,
215 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
216 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
217 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
218 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
219 uint8_t pa_features_300
[] = { 66, 0,
220 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
221 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
224 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
226 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
227 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
228 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
229 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
231 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
232 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
233 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
235 /* 42: PM, 44: PC RA, 46: SC vec'd */
236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
237 /* 48: SIMD, 50: QP BFP, 52: String */
238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
239 /* 54: DecFP, 56: DecI, 58: SHA */
240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
241 /* 60: NM atomic, 62: RNG */
242 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
244 uint8_t *pa_features
= NULL
;
247 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
248 pa_features
= pa_features_206
;
249 pa_size
= sizeof(pa_features_206
);
251 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
252 pa_features
= pa_features_207
;
253 pa_size
= sizeof(pa_features_207
);
255 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
256 pa_features
= pa_features_300
;
257 pa_size
= sizeof(pa_features_300
);
263 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
265 * Note: we keep CI large pages off by default because a 64K capable
266 * guest provisioned with large pages might otherwise try to map a qemu
267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
268 * even if that qemu runs on a 4k host.
269 * We dd this bit back here if we are confident this is not an issue
271 pa_features
[3] |= 0x20;
273 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
274 pa_features
[24] |= 0x80; /* Transactional memory support */
276 if (spapr
->cas_pre_isa3_guest
&& pa_size
> 40) {
277 /* Workaround for broken kernels that attempt (guest) radix
278 * mode when they can't handle it, if they see the radix bit set
279 * in pa-features. So hide it from them. */
280 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
283 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
286 static hwaddr
spapr_node0_size(MachineState
*machine
)
288 if (machine
->numa_state
->num_nodes
) {
290 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
291 if (machine
->numa_state
->nodes
[i
].node_mem
) {
292 return MIN(pow2floor(machine
->numa_state
->nodes
[i
].node_mem
),
297 return machine
->ram_size
;
300 static void add_str(GString
*s
, const gchar
*s1
)
302 g_string_append_len(s
, s1
, strlen(s1
) + 1);
305 static int spapr_dt_memory_node(SpaprMachineState
*spapr
, void *fdt
, int nodeid
,
306 hwaddr start
, hwaddr size
)
309 uint64_t mem_reg_property
[2];
312 mem_reg_property
[0] = cpu_to_be64(start
);
313 mem_reg_property
[1] = cpu_to_be64(size
);
315 sprintf(mem_name
, "memory@%" HWADDR_PRIx
, start
);
316 off
= fdt_add_subnode(fdt
, 0, mem_name
);
318 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
319 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
320 sizeof(mem_reg_property
))));
321 spapr_numa_write_associativity_dt(spapr
, fdt
, off
, nodeid
);
325 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
327 MemoryDeviceInfoList
*info
;
329 for (info
= list
; info
; info
= info
->next
) {
330 MemoryDeviceInfo
*value
= info
->value
;
332 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
333 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
335 if (addr
>= pcdimm_info
->addr
&&
336 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
337 return pcdimm_info
->node
;
345 struct sPAPRDrconfCellV2
{
353 typedef struct DrconfCellQueue
{
354 struct sPAPRDrconfCellV2 cell
;
355 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
358 static DrconfCellQueue
*
359 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
360 uint32_t drc_index
, uint32_t aa_index
,
363 DrconfCellQueue
*elem
;
365 elem
= g_malloc0(sizeof(*elem
));
366 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
367 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
368 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
369 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
370 elem
->cell
.flags
= cpu_to_be32(flags
);
375 static int spapr_dt_dynamic_memory_v2(SpaprMachineState
*spapr
, void *fdt
,
376 int offset
, MemoryDeviceInfoList
*dimms
)
378 MachineState
*machine
= MACHINE(spapr
);
379 uint8_t *int_buf
, *cur_index
;
381 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
382 uint64_t addr
, cur_addr
, size
;
383 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
384 uint64_t mem_end
= machine
->device_memory
->base
+
385 memory_region_size(&machine
->device_memory
->mr
);
386 uint32_t node
, buf_len
, nr_entries
= 0;
388 DrconfCellQueue
*elem
, *next
;
389 MemoryDeviceInfoList
*info
;
390 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
391 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
393 /* Entry to cover RAM and the gap area */
394 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
395 SPAPR_LMB_FLAGS_RESERVED
|
396 SPAPR_LMB_FLAGS_DRC_INVALID
);
397 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
400 cur_addr
= machine
->device_memory
->base
;
401 for (info
= dimms
; info
; info
= info
->next
) {
402 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
409 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The
410 * area is marked hotpluggable in the next iteration for the bigger
411 * chunk including the NVDIMM occupied area.
413 if (info
->value
->type
== MEMORY_DEVICE_INFO_KIND_NVDIMM
)
416 /* Entry for hot-pluggable area */
417 if (cur_addr
< addr
) {
418 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
420 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
421 cur_addr
, spapr_drc_index(drc
), -1, 0);
422 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
427 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
429 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
430 spapr_drc_index(drc
), node
,
431 (SPAPR_LMB_FLAGS_ASSIGNED
|
432 SPAPR_LMB_FLAGS_HOTREMOVABLE
));
433 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
435 cur_addr
= addr
+ size
;
438 /* Entry for remaining hotpluggable area */
439 if (cur_addr
< mem_end
) {
440 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
442 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
443 cur_addr
, spapr_drc_index(drc
), -1, 0);
444 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
448 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
449 int_buf
= cur_index
= g_malloc0(buf_len
);
450 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
451 cur_index
+= sizeof(nr_entries
);
453 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
454 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
455 cur_index
+= sizeof(elem
->cell
);
456 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
460 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
468 static int spapr_dt_dynamic_memory(SpaprMachineState
*spapr
, void *fdt
,
469 int offset
, MemoryDeviceInfoList
*dimms
)
471 MachineState
*machine
= MACHINE(spapr
);
473 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
474 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
475 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
476 memory_region_size(&machine
->device_memory
->mr
)) /
478 uint32_t *int_buf
, *cur_index
, buf_len
;
481 * Allocate enough buffer size to fit in ibm,dynamic-memory
483 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
484 cur_index
= int_buf
= g_malloc0(buf_len
);
485 int_buf
[0] = cpu_to_be32(nr_lmbs
);
487 for (i
= 0; i
< nr_lmbs
; i
++) {
488 uint64_t addr
= i
* lmb_size
;
489 uint32_t *dynamic_memory
= cur_index
;
491 if (i
>= device_lmb_start
) {
494 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
497 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
498 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
499 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
500 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
501 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
502 if (memory_region_present(get_system_memory(), addr
)) {
503 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
505 dynamic_memory
[5] = cpu_to_be32(0);
509 * LMB information for RMA, boot time RAM and gap b/n RAM and
510 * device memory region -- all these are marked as reserved
511 * and as having no valid DRC.
513 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
514 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
515 dynamic_memory
[2] = cpu_to_be32(0);
516 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
517 dynamic_memory
[4] = cpu_to_be32(-1);
518 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
519 SPAPR_LMB_FLAGS_DRC_INVALID
);
522 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
524 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
533 * Adds ibm,dynamic-reconfiguration-memory node.
534 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
535 * of this device tree node.
537 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState
*spapr
,
540 MachineState
*machine
= MACHINE(spapr
);
542 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
543 uint32_t prop_lmb_size
[] = {cpu_to_be32(lmb_size
>> 32),
544 cpu_to_be32(lmb_size
& 0xffffffff)};
545 MemoryDeviceInfoList
*dimms
= NULL
;
548 * Don't create the node if there is no device memory
550 if (machine
->ram_size
== machine
->maxram_size
) {
554 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
556 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
557 sizeof(prop_lmb_size
));
562 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
567 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
572 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
573 dimms
= qmp_memory_device_list();
574 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
575 ret
= spapr_dt_dynamic_memory_v2(spapr
, fdt
, offset
, dimms
);
577 ret
= spapr_dt_dynamic_memory(spapr
, fdt
, offset
, dimms
);
579 qapi_free_MemoryDeviceInfoList(dimms
);
585 ret
= spapr_numa_write_assoc_lookup_arrays(spapr
, fdt
, offset
);
590 static int spapr_dt_memory(SpaprMachineState
*spapr
, void *fdt
)
592 MachineState
*machine
= MACHINE(spapr
);
593 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
594 hwaddr mem_start
, node_size
;
595 int i
, nb_nodes
= machine
->numa_state
->num_nodes
;
596 NodeInfo
*nodes
= machine
->numa_state
->nodes
;
598 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
599 if (!nodes
[i
].node_mem
) {
602 if (mem_start
>= machine
->ram_size
) {
605 node_size
= nodes
[i
].node_mem
;
606 if (node_size
> machine
->ram_size
- mem_start
) {
607 node_size
= machine
->ram_size
- mem_start
;
611 /* spapr_machine_init() checks for rma_size <= node0_size
613 spapr_dt_memory_node(spapr
, fdt
, i
, 0, spapr
->rma_size
);
614 mem_start
+= spapr
->rma_size
;
615 node_size
-= spapr
->rma_size
;
617 for ( ; node_size
; ) {
618 hwaddr sizetmp
= pow2floor(node_size
);
620 /* mem_start != 0 here */
621 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
622 sizetmp
= 1ULL << ctzl(mem_start
);
625 spapr_dt_memory_node(spapr
, fdt
, i
, mem_start
, sizetmp
);
626 node_size
-= sizetmp
;
627 mem_start
+= sizetmp
;
631 /* Generate ibm,dynamic-reconfiguration-memory node if required */
632 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRCONF_MEMORY
)) {
635 g_assert(smc
->dr_lmb_enabled
);
636 ret
= spapr_dt_dynamic_reconfiguration_memory(spapr
, fdt
);
645 static void spapr_dt_cpu(CPUState
*cs
, void *fdt
, int offset
,
646 SpaprMachineState
*spapr
)
648 MachineState
*ms
= MACHINE(spapr
);
649 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
650 CPUPPCState
*env
= &cpu
->env
;
651 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
652 int index
= spapr_get_vcpu_id(cpu
);
653 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
654 0xffffffff, 0xffffffff};
655 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
656 : SPAPR_TIMEBASE_FREQ
;
657 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
658 uint32_t page_sizes_prop
[64];
659 size_t page_sizes_prop_size
;
660 unsigned int smp_threads
= ms
->smp
.threads
;
661 uint32_t vcpus_per_socket
= smp_threads
* ms
->smp
.cores
;
662 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
663 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
666 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
669 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
671 drc_index
= spapr_drc_index(drc
);
672 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
675 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
676 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
678 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
679 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
680 env
->dcache_line_size
)));
681 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
682 env
->dcache_line_size
)));
683 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
684 env
->icache_line_size
)));
685 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
686 env
->icache_line_size
)));
688 if (pcc
->l1_dcache_size
) {
689 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
690 pcc
->l1_dcache_size
)));
692 warn_report("Unknown L1 dcache size for cpu");
694 if (pcc
->l1_icache_size
) {
695 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
696 pcc
->l1_icache_size
)));
698 warn_report("Unknown L1 icache size for cpu");
701 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
702 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
703 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
704 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
705 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
706 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
708 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
709 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,purr", 1)));
711 if (env
->spr_cb
[SPR_SPURR
].oea_read
) {
712 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,spurr", 1)));
715 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
716 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
717 segs
, sizeof(segs
))));
720 /* Advertise VSX (vector extensions) if available
721 * 1 == VMX / Altivec available
724 * Only CPUs for which we create core types in spapr_cpu_core.c
725 * are possible, and all of those have VMX */
726 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
727 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
729 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
732 /* Advertise DFP (Decimal Floating Point) if available
733 * 0 / no property == no DFP
734 * 1 == DFP available */
735 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
736 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
739 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
740 sizeof(page_sizes_prop
));
741 if (page_sizes_prop_size
) {
742 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
743 page_sizes_prop
, page_sizes_prop_size
)));
746 spapr_dt_pa_features(spapr
, cpu
, fdt
, offset
);
748 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
749 cs
->cpu_index
/ vcpus_per_socket
)));
751 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
752 pft_size_prop
, sizeof(pft_size_prop
))));
754 if (ms
->numa_state
->num_nodes
> 1) {
755 _FDT(spapr_numa_fixup_cpu_dt(spapr
, fdt
, offset
, cpu
));
758 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
760 if (pcc
->radix_page_info
) {
761 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
762 radix_AP_encodings
[i
] =
763 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
765 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
767 pcc
->radix_page_info
->count
*
768 sizeof(radix_AP_encodings
[0]))));
772 * We set this property to let the guest know that it can use the large
773 * decrementer and its width in bits.
775 if (spapr_get_cap(spapr
, SPAPR_CAP_LARGE_DECREMENTER
) != SPAPR_CAP_OFF
)
776 _FDT((fdt_setprop_u32(fdt
, offset
, "ibm,dec-bits",
777 pcc
->lrg_decr_bits
)));
780 static void spapr_dt_cpus(void *fdt
, SpaprMachineState
*spapr
)
788 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
790 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
791 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
794 * We walk the CPUs in reverse order to ensure that CPU DT nodes
795 * created by fdt_add_subnode() end up in the right order in FDT
796 * for the guest kernel the enumerate the CPUs correctly.
798 * The CPU list cannot be traversed in reverse order, so we need
804 rev
= g_renew(CPUState
*, rev
, n_cpus
+ 1);
808 for (i
= n_cpus
- 1; i
>= 0; i
--) {
809 CPUState
*cs
= rev
[i
];
810 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
811 int index
= spapr_get_vcpu_id(cpu
);
812 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
813 g_autofree
char *nodename
= NULL
;
816 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
820 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
821 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
823 spapr_dt_cpu(cs
, fdt
, offset
, spapr
);
829 static int spapr_dt_rng(void *fdt
)
834 node
= qemu_fdt_add_subnode(fdt
, "/ibm,platform-facilities");
838 ret
= fdt_setprop_string(fdt
, node
, "device_type",
839 "ibm,platform-facilities");
840 ret
|= fdt_setprop_cell(fdt
, node
, "#address-cells", 0x1);
841 ret
|= fdt_setprop_cell(fdt
, node
, "#size-cells", 0x0);
843 node
= fdt_add_subnode(fdt
, node
, "ibm,random-v1");
847 ret
|= fdt_setprop_string(fdt
, node
, "compatible", "ibm,random");
852 static void spapr_dt_rtas(SpaprMachineState
*spapr
, void *fdt
)
854 MachineState
*ms
= MACHINE(spapr
);
856 GString
*hypertas
= g_string_sized_new(256);
857 GString
*qemu_hypertas
= g_string_sized_new(256);
858 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
859 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
860 uint32_t lrdr_capacity
[] = {
861 cpu_to_be32(max_device_addr
>> 32),
862 cpu_to_be32(max_device_addr
& 0xffffffff),
863 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
>> 32),
864 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
& 0xffffffff),
865 cpu_to_be32(ms
->smp
.max_cpus
/ ms
->smp
.threads
),
868 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
871 add_str(hypertas
, "hcall-pft");
872 add_str(hypertas
, "hcall-term");
873 add_str(hypertas
, "hcall-dabr");
874 add_str(hypertas
, "hcall-interrupt");
875 add_str(hypertas
, "hcall-tce");
876 add_str(hypertas
, "hcall-vio");
877 add_str(hypertas
, "hcall-splpar");
878 add_str(hypertas
, "hcall-join");
879 add_str(hypertas
, "hcall-bulk");
880 add_str(hypertas
, "hcall-set-mode");
881 add_str(hypertas
, "hcall-sprg0");
882 add_str(hypertas
, "hcall-copy");
883 add_str(hypertas
, "hcall-debug");
884 add_str(hypertas
, "hcall-vphn");
885 add_str(qemu_hypertas
, "hcall-memop1");
887 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
888 add_str(hypertas
, "hcall-multi-tce");
891 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
892 add_str(hypertas
, "hcall-hpt-resize");
895 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
896 hypertas
->str
, hypertas
->len
));
897 g_string_free(hypertas
, TRUE
);
898 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
899 qemu_hypertas
->str
, qemu_hypertas
->len
));
900 g_string_free(qemu_hypertas
, TRUE
);
902 spapr_numa_write_rtas_dt(spapr
, fdt
, rtas
);
905 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log,
906 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes.
908 * The system reset requirements are driven by existing Linux and PowerVM
909 * implementation which (contrary to PAPR) saves r3 in the error log
910 * structure like machine check, so Linux expects to find the saved r3
911 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and
912 * does not look at the error value).
914 * System reset interrupts are not subject to interlock like machine
915 * check, so this memory area could be corrupted if the sreset is
916 * interrupted by a machine check (or vice versa) if it was shared. To
917 * prevent this, system reset uses per-CPU areas for the sreset save
918 * area. A system reset that interrupts a system reset handler could
919 * still overwrite this area, but Linux doesn't try to recover in that
922 * The extra 8 bytes is required because Linux's FWNMI error log check
925 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-size", RTAS_ERROR_LOG_MAX
+
926 ms
->smp
.max_cpus
* sizeof(uint64_t)*2 + sizeof(uint64_t)));
927 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
928 RTAS_ERROR_LOG_MAX
));
929 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
930 RTAS_EVENT_SCAN_RATE
));
932 g_assert(msi_nonbroken
);
933 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
936 * According to PAPR, rtas ibm,os-term does not guarantee a return
937 * back to the guest cpu.
939 * While an additional ibm,extended-os-term property indicates
940 * that rtas call return will always occur. Set this property.
942 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
944 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
945 lrdr_capacity
, sizeof(lrdr_capacity
)));
947 spapr_dt_rtas_tokens(fdt
, rtas
);
951 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
952 * and the XIVE features that the guest may request and thus the valid
953 * values for bytes 23..26 of option vector 5:
955 static void spapr_dt_ov5_platform_support(SpaprMachineState
*spapr
, void *fdt
,
958 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
961 23, 0x00, /* XICS / XIVE mode */
962 24, 0x00, /* Hash/Radix, filled in below. */
963 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
964 26, 0x40, /* Radix options: GTSE == yes. */
967 if (spapr
->irq
->xics
&& spapr
->irq
->xive
) {
968 val
[1] = SPAPR_OV5_XIVE_BOTH
;
969 } else if (spapr
->irq
->xive
) {
970 val
[1] = SPAPR_OV5_XIVE_EXPLOIT
;
972 assert(spapr
->irq
->xics
);
973 val
[1] = SPAPR_OV5_XIVE_LEGACY
;
976 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
977 first_ppc_cpu
->compat_pvr
)) {
979 * If we're in a pre POWER9 compat mode then the guest should
980 * do hash and use the legacy interrupt mode
982 val
[1] = SPAPR_OV5_XIVE_LEGACY
; /* XICS */
983 val
[3] = 0x00; /* Hash */
984 } else if (kvm_enabled()) {
985 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
986 val
[3] = 0x80; /* OV5_MMU_BOTH */
987 } else if (kvmppc_has_cap_mmu_radix()) {
988 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
990 val
[3] = 0x00; /* Hash */
993 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
996 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
1000 static void spapr_dt_chosen(SpaprMachineState
*spapr
, void *fdt
, bool reset
)
1002 MachineState
*machine
= MACHINE(spapr
);
1003 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1006 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1009 const char *boot_device
= machine
->boot_order
;
1010 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1012 char *bootlist
= get_boot_devices_list(&cb
);
1014 if (machine
->kernel_cmdline
&& machine
->kernel_cmdline
[0]) {
1015 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs",
1016 machine
->kernel_cmdline
));
1019 if (spapr
->initrd_size
) {
1020 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1021 spapr
->initrd_base
));
1022 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1023 spapr
->initrd_base
+ spapr
->initrd_size
));
1026 if (spapr
->kernel_size
) {
1027 uint64_t kprop
[2] = { cpu_to_be64(spapr
->kernel_addr
),
1028 cpu_to_be64(spapr
->kernel_size
) };
1030 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1031 &kprop
, sizeof(kprop
)));
1032 if (spapr
->kernel_le
) {
1033 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1037 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
1039 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1040 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1041 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1043 if (cb
&& bootlist
) {
1046 for (i
= 0; i
< cb
; i
++) {
1047 if (bootlist
[i
] == '\n') {
1051 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1054 if (boot_device
&& strlen(boot_device
)) {
1055 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1058 if (!spapr
->has_graphics
&& stdout_path
) {
1060 * "linux,stdout-path" and "stdout" properties are
1061 * deprecated by linux kernel. New platforms should only
1062 * use the "stdout-path" property. Set the new property
1063 * and continue using older property to remain compatible
1064 * with the existing firmware.
1066 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1067 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1071 * We can deal with BAR reallocation just fine, advertise it
1074 if (smc
->linux_pci_probe
) {
1075 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,pci-probe-only", 0));
1078 spapr_dt_ov5_platform_support(spapr
, fdt
, chosen
);
1080 g_free(stdout_path
);
1084 _FDT(spapr_dt_ovec(fdt
, chosen
, spapr
->ov5_cas
, "ibm,architecture-vec-5"));
1087 static void spapr_dt_hypervisor(SpaprMachineState
*spapr
, void *fdt
)
1089 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1090 * KVM to work under pHyp with some guest co-operation */
1092 uint8_t hypercall
[16];
1094 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1095 /* indicate KVM hypercall interface */
1096 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1097 if (kvmppc_has_cap_fixup_hcalls()) {
1099 * Older KVM versions with older guest kernels were broken
1100 * with the magic page, don't allow the guest to map it.
1102 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1103 sizeof(hypercall
))) {
1104 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1105 hypercall
, sizeof(hypercall
)));
1110 void *spapr_build_fdt(SpaprMachineState
*spapr
, bool reset
, size_t space
)
1112 MachineState
*machine
= MACHINE(spapr
);
1113 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1114 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1115 uint32_t root_drc_type_mask
= 0;
1121 fdt
= g_malloc0(space
);
1122 _FDT((fdt_create_empty_tree(fdt
, space
)));
1125 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1126 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1127 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1129 /* Guest UUID & Name*/
1130 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1131 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1132 if (qemu_uuid_set
) {
1133 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1137 if (qemu_get_vm_name()) {
1138 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1139 qemu_get_vm_name()));
1142 /* Host Model & Serial Number */
1143 if (spapr
->host_model
) {
1144 _FDT(fdt_setprop_string(fdt
, 0, "host-model", spapr
->host_model
));
1145 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_model(&buf
)) {
1146 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1150 if (spapr
->host_serial
) {
1151 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", spapr
->host_serial
));
1152 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_serial(&buf
)) {
1153 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1157 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1158 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1160 /* /interrupt controller */
1161 spapr_irq_dt(spapr
, spapr_max_server_number(spapr
), fdt
, PHANDLE_INTC
);
1163 ret
= spapr_dt_memory(spapr
, fdt
);
1165 error_report("couldn't setup memory nodes in fdt");
1170 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1172 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1173 ret
= spapr_dt_rng(fdt
);
1175 error_report("could not set up rng device in the fdt");
1180 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1181 ret
= spapr_dt_phb(spapr
, phb
, PHANDLE_INTC
, fdt
, NULL
);
1183 error_report("couldn't setup PCI devices in fdt");
1188 spapr_dt_cpus(fdt
, spapr
);
1190 /* ibm,drc-indexes and friends */
1191 if (smc
->dr_lmb_enabled
) {
1192 root_drc_type_mask
|= SPAPR_DR_CONNECTOR_TYPE_LMB
;
1194 if (smc
->dr_phb_enabled
) {
1195 root_drc_type_mask
|= SPAPR_DR_CONNECTOR_TYPE_PHB
;
1197 if (mc
->nvdimm_supported
) {
1198 root_drc_type_mask
|= SPAPR_DR_CONNECTOR_TYPE_PMEM
;
1200 if (root_drc_type_mask
) {
1201 _FDT(spapr_dt_drc(fdt
, 0, NULL
, root_drc_type_mask
));
1204 if (mc
->has_hotpluggable_cpus
) {
1205 int offset
= fdt_path_offset(fdt
, "/cpus");
1206 ret
= spapr_dt_drc(fdt
, offset
, NULL
, SPAPR_DR_CONNECTOR_TYPE_CPU
);
1208 error_report("Couldn't set up CPU DR device tree properties");
1213 /* /event-sources */
1214 spapr_dt_events(spapr
, fdt
);
1217 spapr_dt_rtas(spapr
, fdt
);
1220 spapr_dt_chosen(spapr
, fdt
, reset
);
1223 if (kvm_enabled()) {
1224 spapr_dt_hypervisor(spapr
, fdt
);
1227 /* Build memory reserve map */
1229 if (spapr
->kernel_size
) {
1230 _FDT((fdt_add_mem_rsv(fdt
, spapr
->kernel_addr
,
1231 spapr
->kernel_size
)));
1233 if (spapr
->initrd_size
) {
1234 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
,
1235 spapr
->initrd_size
)));
1239 /* NVDIMM devices */
1240 if (mc
->nvdimm_supported
) {
1241 spapr_dt_persistent_memory(spapr
, fdt
);
1247 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1249 SpaprMachineState
*spapr
= opaque
;
1251 return (addr
& 0x0fffffff) + spapr
->kernel_addr
;
1254 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1257 CPUPPCState
*env
= &cpu
->env
;
1259 /* The TCG path should also be holding the BQL at this point */
1260 g_assert(qemu_mutex_iothread_locked());
1263 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1264 env
->gpr
[3] = H_PRIVILEGE
;
1266 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1270 struct LPCRSyncState
{
1275 static void do_lpcr_sync(CPUState
*cs
, run_on_cpu_data arg
)
1277 struct LPCRSyncState
*s
= arg
.host_ptr
;
1278 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1279 CPUPPCState
*env
= &cpu
->env
;
1282 cpu_synchronize_state(cs
);
1283 lpcr
= env
->spr
[SPR_LPCR
];
1286 ppc_store_lpcr(cpu
, lpcr
);
1289 void spapr_set_all_lpcrs(target_ulong value
, target_ulong mask
)
1292 struct LPCRSyncState s
= {
1297 run_on_cpu(cs
, do_lpcr_sync
, RUN_ON_CPU_HOST_PTR(&s
));
1301 static void spapr_get_pate(PPCVirtualHypervisor
*vhyp
, ppc_v3_pate_t
*entry
)
1303 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1305 /* Copy PATE1:GR into PATE0:HR */
1306 entry
->dw0
= spapr
->patb_entry
& PATE0_HR
;
1307 entry
->dw1
= spapr
->patb_entry
;
1310 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1311 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1312 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1313 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1314 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1317 * Get the fd to access the kernel htab, re-opening it if necessary
1319 static int get_htab_fd(SpaprMachineState
*spapr
)
1321 Error
*local_err
= NULL
;
1323 if (spapr
->htab_fd
>= 0) {
1324 return spapr
->htab_fd
;
1327 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1328 if (spapr
->htab_fd
< 0) {
1329 error_report_err(local_err
);
1332 return spapr
->htab_fd
;
1335 void close_htab_fd(SpaprMachineState
*spapr
)
1337 if (spapr
->htab_fd
>= 0) {
1338 close(spapr
->htab_fd
);
1340 spapr
->htab_fd
= -1;
1343 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1345 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1347 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1350 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1352 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1354 assert(kvm_enabled());
1360 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1363 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1366 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1367 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1371 * HTAB is controlled by KVM. Fetch into temporary buffer
1373 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1374 kvmppc_read_hptes(hptes
, ptex
, n
);
1379 * HTAB is controlled by QEMU. Just point to the internally
1382 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1385 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1386 const ppc_hash_pte64_t
*hptes
,
1389 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1392 g_free((void *)hptes
);
1395 /* Nothing to do for qemu managed HPT */
1398 void spapr_store_hpte(PowerPCCPU
*cpu
, hwaddr ptex
,
1399 uint64_t pte0
, uint64_t pte1
)
1401 SpaprMachineState
*spapr
= SPAPR_MACHINE(cpu
->vhyp
);
1402 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1405 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1407 if (pte0
& HPTE64_V_VALID
) {
1408 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1410 * When setting valid, we write PTE1 first. This ensures
1411 * proper synchronization with the reading code in
1412 * ppc_hash64_pteg_search()
1415 stq_p(spapr
->htab
+ offset
, pte0
);
1417 stq_p(spapr
->htab
+ offset
, pte0
);
1419 * When clearing it we set PTE0 first. This ensures proper
1420 * synchronization with the reading code in
1421 * ppc_hash64_pteg_search()
1424 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1429 static void spapr_hpte_set_c(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1432 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 15;
1433 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1436 /* There should always be a hash table when this is called */
1437 error_report("spapr_hpte_set_c called with no hash table !");
1441 /* The HW performs a non-atomic byte update */
1442 stb_p(spapr
->htab
+ offset
, (pte1
& 0xff) | 0x80);
1445 static void spapr_hpte_set_r(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1448 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 14;
1449 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1452 /* There should always be a hash table when this is called */
1453 error_report("spapr_hpte_set_r called with no hash table !");
1457 /* The HW performs a non-atomic byte update */
1458 stb_p(spapr
->htab
+ offset
, ((pte1
>> 8) & 0xff) | 0x01);
1461 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1465 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1466 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1467 * that's much more than is needed for Linux guests */
1468 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1469 shift
= MAX(shift
, 18); /* Minimum architected size */
1470 shift
= MIN(shift
, 46); /* Maximum architected size */
1474 void spapr_free_hpt(SpaprMachineState
*spapr
)
1476 g_free(spapr
->htab
);
1478 spapr
->htab_shift
= 0;
1479 close_htab_fd(spapr
);
1482 int spapr_reallocate_hpt(SpaprMachineState
*spapr
, int shift
, Error
**errp
)
1487 /* Clean up any HPT info from a previous boot */
1488 spapr_free_hpt(spapr
);
1490 rc
= kvmppc_reset_htab(shift
);
1492 if (rc
== -EOPNOTSUPP
) {
1493 error_setg(errp
, "HPT not supported in nested guests");
1498 /* kernel-side HPT needed, but couldn't allocate one */
1499 error_setg_errno(errp
, errno
, "Failed to allocate KVM HPT of order %d",
1501 error_append_hint(errp
, "Try smaller maxmem?\n");
1503 } else if (rc
> 0) {
1504 /* kernel-side HPT allocated */
1507 "Requested order %d HPT, but kernel allocated order %ld",
1509 error_append_hint(errp
, "Try smaller maxmem?\n");
1513 spapr
->htab_shift
= shift
;
1516 /* kernel-side HPT not needed, allocate in userspace instead */
1517 size_t size
= 1ULL << shift
;
1520 spapr
->htab
= qemu_memalign(size
, size
);
1521 memset(spapr
->htab
, 0, size
);
1522 spapr
->htab_shift
= shift
;
1524 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1525 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1528 /* We're setting up a hash table, so that means we're not radix */
1529 spapr
->patb_entry
= 0;
1530 spapr_set_all_lpcrs(0, LPCR_HR
| LPCR_UPRT
);
1534 void spapr_setup_hpt(SpaprMachineState
*spapr
)
1538 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
) {
1539 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1541 uint64_t current_ram_size
;
1543 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1544 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1546 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1548 if (kvm_enabled()) {
1549 hwaddr vrma_limit
= kvmppc_vrma_limit(spapr
->htab_shift
);
1551 /* Check our RMA fits in the possible VRMA */
1552 if (vrma_limit
< spapr
->rma_size
) {
1553 error_report("Unable to create %" HWADDR_PRIu
1554 "MiB RMA (VRMA only allows %" HWADDR_PRIu
"MiB",
1555 spapr
->rma_size
/ MiB
, vrma_limit
/ MiB
);
1561 static void spapr_machine_reset(MachineState
*machine
)
1563 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
1564 PowerPCCPU
*first_ppc_cpu
;
1569 pef_kvm_reset(machine
->cgs
, &error_fatal
);
1570 spapr_caps_apply(spapr
);
1572 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1573 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1574 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
1575 spapr
->max_compat_pvr
)) {
1577 * If using KVM with radix mode available, VCPUs can be started
1578 * without a HPT because KVM will start them in radix mode.
1579 * Set the GR bit in PATE so that we know there is no HPT.
1581 spapr
->patb_entry
= PATE1_GR
;
1582 spapr_set_all_lpcrs(LPCR_HR
| LPCR_UPRT
, LPCR_HR
| LPCR_UPRT
);
1584 spapr_setup_hpt(spapr
);
1587 qemu_devices_reset();
1589 spapr_ovec_cleanup(spapr
->ov5_cas
);
1590 spapr
->ov5_cas
= spapr_ovec_new();
1592 ppc_set_compat_all(spapr
->max_compat_pvr
, &error_fatal
);
1595 * This is fixing some of the default configuration of the XIVE
1596 * devices. To be called after the reset of the machine devices.
1598 spapr_irq_reset(spapr
, &error_fatal
);
1601 * There is no CAS under qtest. Simulate one to please the code that
1602 * depends on spapr->ov5_cas. This is especially needed to test device
1603 * unplug, so we do that before resetting the DRCs.
1605 if (qtest_enabled()) {
1606 spapr_ovec_cleanup(spapr
->ov5_cas
);
1607 spapr
->ov5_cas
= spapr_ovec_clone(spapr
->ov5
);
1610 /* DRC reset may cause a device to be unplugged. This will cause troubles
1611 * if this device is used by another device (eg, a running vhost backend
1612 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1613 * situations, we reset DRCs after all devices have been reset.
1615 spapr_drc_reset_all(spapr
);
1617 spapr_clear_pending_events(spapr
);
1620 * We place the device tree and RTAS just below either the top of the RMA,
1621 * or just below 2GB, whichever is lower, so that it can be
1622 * processed with 32-bit real mode code if necessary
1624 fdt_addr
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FDT_MAX_SIZE
;
1626 fdt
= spapr_build_fdt(spapr
, true, FDT_MAX_SIZE
);
1630 /* Should only fail if we've built a corrupted tree */
1634 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1635 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1636 g_free(spapr
->fdt_blob
);
1637 spapr
->fdt_size
= fdt_totalsize(fdt
);
1638 spapr
->fdt_initial_size
= spapr
->fdt_size
;
1639 spapr
->fdt_blob
= fdt
;
1641 /* Set up the entry state */
1642 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
, 0, fdt_addr
, 0);
1643 first_ppc_cpu
->env
.gpr
[5] = 0;
1645 spapr
->fwnmi_system_reset_addr
= -1;
1646 spapr
->fwnmi_machine_check_addr
= -1;
1647 spapr
->fwnmi_machine_check_interlock
= -1;
1649 /* Signal all vCPUs waiting on this condition */
1650 qemu_cond_broadcast(&spapr
->fwnmi_machine_check_interlock_cond
);
1652 migrate_del_blocker(spapr
->fwnmi_migration_blocker
);
1655 static void spapr_create_nvram(SpaprMachineState
*spapr
)
1657 DeviceState
*dev
= qdev_new("spapr-nvram");
1658 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1661 qdev_prop_set_drive_err(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1665 qdev_realize_and_unref(dev
, &spapr
->vio_bus
->bus
, &error_fatal
);
1667 spapr
->nvram
= (struct SpaprNvram
*)dev
;
1670 static void spapr_rtc_create(SpaprMachineState
*spapr
)
1672 object_initialize_child_with_props(OBJECT(spapr
), "rtc", &spapr
->rtc
,
1673 sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
,
1674 &error_fatal
, NULL
);
1675 qdev_realize(DEVICE(&spapr
->rtc
), NULL
, &error_fatal
);
1676 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1680 /* Returns whether we want to use VGA or not */
1681 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1683 switch (vga_interface_type
) {
1691 return pci_vga_init(pci_bus
) != NULL
;
1694 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1699 static int spapr_pre_load(void *opaque
)
1703 rc
= spapr_caps_pre_load(opaque
);
1711 static int spapr_post_load(void *opaque
, int version_id
)
1713 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1716 err
= spapr_caps_post_migration(spapr
);
1722 * In earlier versions, there was no separate qdev for the PAPR
1723 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1724 * So when migrating from those versions, poke the incoming offset
1725 * value into the RTC device
1727 if (version_id
< 3) {
1728 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1734 if (kvm_enabled() && spapr
->patb_entry
) {
1735 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1736 bool radix
= !!(spapr
->patb_entry
& PATE1_GR
);
1737 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1740 * Update LPCR:HR and UPRT as they may not be set properly in
1743 spapr_set_all_lpcrs(radix
? (LPCR_HR
| LPCR_UPRT
) : 0,
1744 LPCR_HR
| LPCR_UPRT
);
1746 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1748 error_report("Process table config unsupported by the host");
1753 err
= spapr_irq_post_load(spapr
, version_id
);
1761 static int spapr_pre_save(void *opaque
)
1765 rc
= spapr_caps_pre_save(opaque
);
1773 static bool version_before_3(void *opaque
, int version_id
)
1775 return version_id
< 3;
1778 static bool spapr_pending_events_needed(void *opaque
)
1780 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1781 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1784 static const VMStateDescription vmstate_spapr_event_entry
= {
1785 .name
= "spapr_event_log_entry",
1787 .minimum_version_id
= 1,
1788 .fields
= (VMStateField
[]) {
1789 VMSTATE_UINT32(summary
, SpaprEventLogEntry
),
1790 VMSTATE_UINT32(extended_length
, SpaprEventLogEntry
),
1791 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, SpaprEventLogEntry
, 0,
1792 NULL
, extended_length
),
1793 VMSTATE_END_OF_LIST()
1797 static const VMStateDescription vmstate_spapr_pending_events
= {
1798 .name
= "spapr_pending_events",
1800 .minimum_version_id
= 1,
1801 .needed
= spapr_pending_events_needed
,
1802 .fields
= (VMStateField
[]) {
1803 VMSTATE_QTAILQ_V(pending_events
, SpaprMachineState
, 1,
1804 vmstate_spapr_event_entry
, SpaprEventLogEntry
, next
),
1805 VMSTATE_END_OF_LIST()
1809 static bool spapr_ov5_cas_needed(void *opaque
)
1811 SpaprMachineState
*spapr
= opaque
;
1812 SpaprOptionVector
*ov5_mask
= spapr_ovec_new();
1815 /* Prior to the introduction of SpaprOptionVector, we had two option
1816 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1817 * Both of these options encode machine topology into the device-tree
1818 * in such a way that the now-booted OS should still be able to interact
1819 * appropriately with QEMU regardless of what options were actually
1820 * negotiatied on the source side.
1822 * As such, we can avoid migrating the CAS-negotiated options if these
1823 * are the only options available on the current machine/platform.
1824 * Since these are the only options available for pseries-2.7 and
1825 * earlier, this allows us to maintain old->new/new->old migration
1828 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1829 * via default pseries-2.8 machines and explicit command-line parameters.
1830 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1831 * of the actual CAS-negotiated values to continue working properly. For
1832 * example, availability of memory unplug depends on knowing whether
1833 * OV5_HP_EVT was negotiated via CAS.
1835 * Thus, for any cases where the set of available CAS-negotiatable
1836 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1837 * include the CAS-negotiated options in the migration stream, unless
1838 * if they affect boot time behaviour only.
1840 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
1841 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
1842 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
1844 /* We need extra information if we have any bits outside the mask
1846 cas_needed
= !spapr_ovec_subset(spapr
->ov5
, ov5_mask
);
1848 spapr_ovec_cleanup(ov5_mask
);
1853 static const VMStateDescription vmstate_spapr_ov5_cas
= {
1854 .name
= "spapr_option_vector_ov5_cas",
1856 .minimum_version_id
= 1,
1857 .needed
= spapr_ov5_cas_needed
,
1858 .fields
= (VMStateField
[]) {
1859 VMSTATE_STRUCT_POINTER_V(ov5_cas
, SpaprMachineState
, 1,
1860 vmstate_spapr_ovec
, SpaprOptionVector
),
1861 VMSTATE_END_OF_LIST()
1865 static bool spapr_patb_entry_needed(void *opaque
)
1867 SpaprMachineState
*spapr
= opaque
;
1869 return !!spapr
->patb_entry
;
1872 static const VMStateDescription vmstate_spapr_patb_entry
= {
1873 .name
= "spapr_patb_entry",
1875 .minimum_version_id
= 1,
1876 .needed
= spapr_patb_entry_needed
,
1877 .fields
= (VMStateField
[]) {
1878 VMSTATE_UINT64(patb_entry
, SpaprMachineState
),
1879 VMSTATE_END_OF_LIST()
1883 static bool spapr_irq_map_needed(void *opaque
)
1885 SpaprMachineState
*spapr
= opaque
;
1887 return spapr
->irq_map
&& !bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
);
1890 static const VMStateDescription vmstate_spapr_irq_map
= {
1891 .name
= "spapr_irq_map",
1893 .minimum_version_id
= 1,
1894 .needed
= spapr_irq_map_needed
,
1895 .fields
= (VMStateField
[]) {
1896 VMSTATE_BITMAP(irq_map
, SpaprMachineState
, 0, irq_map_nr
),
1897 VMSTATE_END_OF_LIST()
1901 static bool spapr_dtb_needed(void *opaque
)
1903 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(opaque
);
1905 return smc
->update_dt_enabled
;
1908 static int spapr_dtb_pre_load(void *opaque
)
1910 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1912 g_free(spapr
->fdt_blob
);
1913 spapr
->fdt_blob
= NULL
;
1914 spapr
->fdt_size
= 0;
1919 static const VMStateDescription vmstate_spapr_dtb
= {
1920 .name
= "spapr_dtb",
1922 .minimum_version_id
= 1,
1923 .needed
= spapr_dtb_needed
,
1924 .pre_load
= spapr_dtb_pre_load
,
1925 .fields
= (VMStateField
[]) {
1926 VMSTATE_UINT32(fdt_initial_size
, SpaprMachineState
),
1927 VMSTATE_UINT32(fdt_size
, SpaprMachineState
),
1928 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob
, SpaprMachineState
, 0, NULL
,
1930 VMSTATE_END_OF_LIST()
1934 static bool spapr_fwnmi_needed(void *opaque
)
1936 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1938 return spapr
->fwnmi_machine_check_addr
!= -1;
1941 static int spapr_fwnmi_pre_save(void *opaque
)
1943 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1946 * Check if machine check handling is in progress and print a
1949 if (spapr
->fwnmi_machine_check_interlock
!= -1) {
1950 warn_report("A machine check is being handled during migration. The"
1951 "handler may run and log hardware error on the destination");
1957 static const VMStateDescription vmstate_spapr_fwnmi
= {
1958 .name
= "spapr_fwnmi",
1960 .minimum_version_id
= 1,
1961 .needed
= spapr_fwnmi_needed
,
1962 .pre_save
= spapr_fwnmi_pre_save
,
1963 .fields
= (VMStateField
[]) {
1964 VMSTATE_UINT64(fwnmi_system_reset_addr
, SpaprMachineState
),
1965 VMSTATE_UINT64(fwnmi_machine_check_addr
, SpaprMachineState
),
1966 VMSTATE_INT32(fwnmi_machine_check_interlock
, SpaprMachineState
),
1967 VMSTATE_END_OF_LIST()
1971 static const VMStateDescription vmstate_spapr
= {
1974 .minimum_version_id
= 1,
1975 .pre_load
= spapr_pre_load
,
1976 .post_load
= spapr_post_load
,
1977 .pre_save
= spapr_pre_save
,
1978 .fields
= (VMStateField
[]) {
1979 /* used to be @next_irq */
1980 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
1983 VMSTATE_UINT64_TEST(rtc_offset
, SpaprMachineState
, version_before_3
),
1985 VMSTATE_PPC_TIMEBASE_V(tb
, SpaprMachineState
, 2),
1986 VMSTATE_END_OF_LIST()
1988 .subsections
= (const VMStateDescription
*[]) {
1989 &vmstate_spapr_ov5_cas
,
1990 &vmstate_spapr_patb_entry
,
1991 &vmstate_spapr_pending_events
,
1992 &vmstate_spapr_cap_htm
,
1993 &vmstate_spapr_cap_vsx
,
1994 &vmstate_spapr_cap_dfp
,
1995 &vmstate_spapr_cap_cfpc
,
1996 &vmstate_spapr_cap_sbbc
,
1997 &vmstate_spapr_cap_ibs
,
1998 &vmstate_spapr_cap_hpt_maxpagesize
,
1999 &vmstate_spapr_irq_map
,
2000 &vmstate_spapr_cap_nested_kvm_hv
,
2002 &vmstate_spapr_cap_large_decr
,
2003 &vmstate_spapr_cap_ccf_assist
,
2004 &vmstate_spapr_cap_fwnmi
,
2005 &vmstate_spapr_fwnmi
,
2010 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
2012 SpaprMachineState
*spapr
= opaque
;
2014 /* "Iteration" header */
2015 if (!spapr
->htab_shift
) {
2016 qemu_put_be32(f
, -1);
2018 qemu_put_be32(f
, spapr
->htab_shift
);
2022 spapr
->htab_save_index
= 0;
2023 spapr
->htab_first_pass
= true;
2025 if (spapr
->htab_shift
) {
2026 assert(kvm_enabled());
2034 static void htab_save_chunk(QEMUFile
*f
, SpaprMachineState
*spapr
,
2035 int chunkstart
, int n_valid
, int n_invalid
)
2037 qemu_put_be32(f
, chunkstart
);
2038 qemu_put_be16(f
, n_valid
);
2039 qemu_put_be16(f
, n_invalid
);
2040 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
2041 HASH_PTE_SIZE_64
* n_valid
);
2044 static void htab_save_end_marker(QEMUFile
*f
)
2046 qemu_put_be32(f
, 0);
2047 qemu_put_be16(f
, 0);
2048 qemu_put_be16(f
, 0);
2051 static void htab_save_first_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2054 bool has_timeout
= max_ns
!= -1;
2055 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2056 int index
= spapr
->htab_save_index
;
2057 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2059 assert(spapr
->htab_first_pass
);
2064 /* Consume invalid HPTEs */
2065 while ((index
< htabslots
)
2066 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2067 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2071 /* Consume valid HPTEs */
2073 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2074 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2075 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2079 if (index
> chunkstart
) {
2080 int n_valid
= index
- chunkstart
;
2082 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2085 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2089 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
2091 if (index
>= htabslots
) {
2092 assert(index
== htabslots
);
2094 spapr
->htab_first_pass
= false;
2096 spapr
->htab_save_index
= index
;
2099 static int htab_save_later_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2102 bool final
= max_ns
< 0;
2103 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2104 int examined
= 0, sent
= 0;
2105 int index
= spapr
->htab_save_index
;
2106 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2108 assert(!spapr
->htab_first_pass
);
2111 int chunkstart
, invalidstart
;
2113 /* Consume non-dirty HPTEs */
2114 while ((index
< htabslots
)
2115 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2121 /* Consume valid dirty HPTEs */
2122 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2123 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2124 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2125 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2130 invalidstart
= index
;
2131 /* Consume invalid dirty HPTEs */
2132 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2133 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2134 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2135 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2140 if (index
> chunkstart
) {
2141 int n_valid
= invalidstart
- chunkstart
;
2142 int n_invalid
= index
- invalidstart
;
2144 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2145 sent
+= index
- chunkstart
;
2147 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2152 if (examined
>= htabslots
) {
2156 if (index
>= htabslots
) {
2157 assert(index
== htabslots
);
2160 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
2162 if (index
>= htabslots
) {
2163 assert(index
== htabslots
);
2167 spapr
->htab_save_index
= index
;
2169 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2172 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2173 #define MAX_KVM_BUF_SIZE 2048
2175 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2177 SpaprMachineState
*spapr
= opaque
;
2181 /* Iteration header */
2182 if (!spapr
->htab_shift
) {
2183 qemu_put_be32(f
, -1);
2186 qemu_put_be32(f
, 0);
2190 assert(kvm_enabled());
2192 fd
= get_htab_fd(spapr
);
2197 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2201 } else if (spapr
->htab_first_pass
) {
2202 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2204 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2207 htab_save_end_marker(f
);
2212 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2214 SpaprMachineState
*spapr
= opaque
;
2217 /* Iteration header */
2218 if (!spapr
->htab_shift
) {
2219 qemu_put_be32(f
, -1);
2222 qemu_put_be32(f
, 0);
2228 assert(kvm_enabled());
2230 fd
= get_htab_fd(spapr
);
2235 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2240 if (spapr
->htab_first_pass
) {
2241 htab_save_first_pass(f
, spapr
, -1);
2243 htab_save_later_pass(f
, spapr
, -1);
2247 htab_save_end_marker(f
);
2252 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2254 SpaprMachineState
*spapr
= opaque
;
2255 uint32_t section_hdr
;
2257 Error
*local_err
= NULL
;
2259 if (version_id
< 1 || version_id
> 1) {
2260 error_report("htab_load() bad version");
2264 section_hdr
= qemu_get_be32(f
);
2266 if (section_hdr
== -1) {
2267 spapr_free_hpt(spapr
);
2274 /* First section gives the htab size */
2275 ret
= spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2277 error_report_err(local_err
);
2284 assert(kvm_enabled());
2286 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2288 error_report_err(local_err
);
2295 uint16_t n_valid
, n_invalid
;
2297 index
= qemu_get_be32(f
);
2298 n_valid
= qemu_get_be16(f
);
2299 n_invalid
= qemu_get_be16(f
);
2301 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2306 if ((index
+ n_valid
+ n_invalid
) >
2307 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2308 /* Bad index in stream */
2310 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2311 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2317 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2318 HASH_PTE_SIZE_64
* n_valid
);
2321 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2322 HASH_PTE_SIZE_64
* n_invalid
);
2329 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
,
2332 error_report_err(local_err
);
2346 static void htab_save_cleanup(void *opaque
)
2348 SpaprMachineState
*spapr
= opaque
;
2350 close_htab_fd(spapr
);
2353 static SaveVMHandlers savevm_htab_handlers
= {
2354 .save_setup
= htab_save_setup
,
2355 .save_live_iterate
= htab_save_iterate
,
2356 .save_live_complete_precopy
= htab_save_complete
,
2357 .save_cleanup
= htab_save_cleanup
,
2358 .load_state
= htab_load
,
2361 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2364 MachineState
*machine
= MACHINE(opaque
);
2365 machine
->boot_order
= g_strdup(boot_device
);
2368 static void spapr_create_lmb_dr_connectors(SpaprMachineState
*spapr
)
2370 MachineState
*machine
= MACHINE(spapr
);
2371 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2372 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2375 for (i
= 0; i
< nr_lmbs
; i
++) {
2378 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2379 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2385 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2386 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2387 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2389 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2393 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2394 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2395 " is not aligned to %" PRIu64
" MiB",
2397 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2401 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2402 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2403 " is not aligned to %" PRIu64
" MiB",
2405 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2409 for (i
= 0; i
< machine
->numa_state
->num_nodes
; i
++) {
2410 if (machine
->numa_state
->nodes
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2412 "Node %d memory size 0x%" PRIx64
2413 " is not aligned to %" PRIu64
" MiB",
2414 i
, machine
->numa_state
->nodes
[i
].node_mem
,
2415 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2421 /* find cpu slot in machine->possible_cpus by core_id */
2422 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2424 int index
= id
/ ms
->smp
.threads
;
2426 if (index
>= ms
->possible_cpus
->len
) {
2432 return &ms
->possible_cpus
->cpus
[index
];
2435 static void spapr_set_vsmt_mode(SpaprMachineState
*spapr
, Error
**errp
)
2437 MachineState
*ms
= MACHINE(spapr
);
2438 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
2439 Error
*local_err
= NULL
;
2440 bool vsmt_user
= !!spapr
->vsmt
;
2441 int kvm_smt
= kvmppc_smt_threads();
2443 unsigned int smp_threads
= ms
->smp
.threads
;
2445 if (!kvm_enabled() && (smp_threads
> 1)) {
2446 error_setg(errp
, "TCG cannot support more than 1 thread/core "
2447 "on a pseries machine");
2450 if (!is_power_of_2(smp_threads
)) {
2451 error_setg(errp
, "Cannot support %d threads/core on a pseries "
2452 "machine because it must be a power of 2", smp_threads
);
2456 /* Detemine the VSMT mode to use: */
2458 if (spapr
->vsmt
< smp_threads
) {
2459 error_setg(errp
, "Cannot support VSMT mode %d"
2460 " because it must be >= threads/core (%d)",
2461 spapr
->vsmt
, smp_threads
);
2464 /* In this case, spapr->vsmt has been set by the command line */
2465 } else if (!smc
->smp_threads_vsmt
) {
2467 * Default VSMT value is tricky, because we need it to be as
2468 * consistent as possible (for migration), but this requires
2469 * changing it for at least some existing cases. We pick 8 as
2470 * the value that we'd get with KVM on POWER8, the
2471 * overwhelmingly common case in production systems.
2473 spapr
->vsmt
= MAX(8, smp_threads
);
2475 spapr
->vsmt
= smp_threads
;
2478 /* KVM: If necessary, set the SMT mode: */
2479 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2480 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2482 /* Looks like KVM isn't able to change VSMT mode */
2483 error_setg(&local_err
,
2484 "Failed to set KVM's VSMT mode to %d (errno %d)",
2486 /* We can live with that if the default one is big enough
2487 * for the number of threads, and a submultiple of the one
2488 * we want. In this case we'll waste some vcpu ids, but
2489 * behaviour will be correct */
2490 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2491 warn_report_err(local_err
);
2494 error_append_hint(&local_err
,
2495 "On PPC, a VM with %d threads/core"
2496 " on a host with %d threads/core"
2497 " requires the use of VSMT mode %d.\n",
2498 smp_threads
, kvm_smt
, spapr
->vsmt
);
2500 kvmppc_error_append_smt_possible_hint(&local_err
);
2501 error_propagate(errp
, local_err
);
2505 /* else TCG: nothing to do currently */
2508 static void spapr_init_cpus(SpaprMachineState
*spapr
)
2510 MachineState
*machine
= MACHINE(spapr
);
2511 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2512 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2513 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2514 const CPUArchIdList
*possible_cpus
;
2515 unsigned int smp_cpus
= machine
->smp
.cpus
;
2516 unsigned int smp_threads
= machine
->smp
.threads
;
2517 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2518 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2521 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2522 if (mc
->has_hotpluggable_cpus
) {
2523 if (smp_cpus
% smp_threads
) {
2524 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2525 smp_cpus
, smp_threads
);
2528 if (max_cpus
% smp_threads
) {
2529 error_report("max_cpus (%u) must be multiple of threads (%u)",
2530 max_cpus
, smp_threads
);
2534 if (max_cpus
!= smp_cpus
) {
2535 error_report("This machine version does not support CPU hotplug");
2538 boot_cores_nr
= possible_cpus
->len
;
2541 if (smc
->pre_2_10_has_unused_icps
) {
2544 for (i
= 0; i
< spapr_max_server_number(spapr
); i
++) {
2545 /* Dummy entries get deregistered when real ICPState objects
2546 * are registered during CPU core hotplug.
2548 pre_2_10_vmstate_register_dummy_icp(i
);
2552 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2553 int core_id
= i
* smp_threads
;
2555 if (mc
->has_hotpluggable_cpus
) {
2556 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2557 spapr_vcpu_id(spapr
, core_id
));
2560 if (i
< boot_cores_nr
) {
2561 Object
*core
= object_new(type
);
2562 int nr_threads
= smp_threads
;
2564 /* Handle the partially filled core for older machine types */
2565 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2566 nr_threads
= smp_cpus
- i
* smp_threads
;
2569 object_property_set_int(core
, "nr-threads", nr_threads
,
2571 object_property_set_int(core
, CPU_CORE_PROP_CORE_ID
, core_id
,
2573 qdev_realize(DEVICE(core
), NULL
, &error_fatal
);
2580 static PCIHostState
*spapr_create_default_phb(void)
2584 dev
= qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE
);
2585 qdev_prop_set_uint32(dev
, "index", 0);
2586 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
2588 return PCI_HOST_BRIDGE(dev
);
2591 static hwaddr
spapr_rma_size(SpaprMachineState
*spapr
, Error
**errp
)
2593 MachineState
*machine
= MACHINE(spapr
);
2594 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
2595 hwaddr rma_size
= machine
->ram_size
;
2596 hwaddr node0_size
= spapr_node0_size(machine
);
2598 /* RMA has to fit in the first NUMA node */
2599 rma_size
= MIN(rma_size
, node0_size
);
2602 * VRMA access is via a special 1TiB SLB mapping, so the RMA can
2605 rma_size
= MIN(rma_size
, 1 * TiB
);
2608 * Clamp the RMA size based on machine type. This is for
2609 * migration compatibility with older qemu versions, which limited
2610 * the RMA size for complicated and mostly bad reasons.
2612 if (smc
->rma_limit
) {
2613 rma_size
= MIN(rma_size
, smc
->rma_limit
);
2616 if (rma_size
< MIN_RMA_SLOF
) {
2618 "pSeries SLOF firmware requires >= %" HWADDR_PRIx
2619 "ldMiB guest RMA (Real Mode Area memory)",
2620 MIN_RMA_SLOF
/ MiB
);
2627 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState
*spapr
)
2629 MachineState
*machine
= MACHINE(spapr
);
2632 for (i
= 0; i
< machine
->ram_slots
; i
++) {
2633 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_PMEM
, i
);
2637 /* pSeries LPAR / sPAPR hardware init */
2638 static void spapr_machine_init(MachineState
*machine
)
2640 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
2641 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2642 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2643 const char *bios_name
= machine
->firmware
?: FW_FILE_NAME
;
2644 const char *kernel_filename
= machine
->kernel_filename
;
2645 const char *initrd_filename
= machine
->initrd_filename
;
2648 MemoryRegion
*sysmem
= get_system_memory();
2649 long load_limit
, fw_size
;
2651 Error
*resize_hpt_err
= NULL
;
2654 * if Secure VM (PEF) support is configured, then initialize it
2656 pef_kvm_init(machine
->cgs
, &error_fatal
);
2658 msi_nonbroken
= true;
2660 QLIST_INIT(&spapr
->phbs
);
2661 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2663 /* Determine capabilities to run with */
2664 spapr_caps_init(spapr
);
2666 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2667 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2669 * If the user explicitly requested a mode we should either
2670 * supply it, or fail completely (which we do below). But if
2671 * it's not set explicitly, we reset our mode to something
2674 if (resize_hpt_err
) {
2675 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2676 error_free(resize_hpt_err
);
2677 resize_hpt_err
= NULL
;
2679 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2683 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2685 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2687 * User requested HPT resize, but this host can't supply it. Bail out
2689 error_report_err(resize_hpt_err
);
2692 error_free(resize_hpt_err
);
2694 spapr
->rma_size
= spapr_rma_size(spapr
, &error_fatal
);
2696 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2697 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
2700 * VSMT must be set in order to be able to compute VCPU ids, ie to
2701 * call spapr_max_server_number() or spapr_vcpu_id().
2703 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2705 /* Set up Interrupt Controller before we create the VCPUs */
2706 spapr_irq_init(spapr
, &error_fatal
);
2708 /* Set up containers for ibm,client-architecture-support negotiated options
2710 spapr
->ov5
= spapr_ovec_new();
2711 spapr
->ov5_cas
= spapr_ovec_new();
2713 if (smc
->dr_lmb_enabled
) {
2714 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2715 spapr_validate_node_memory(machine
, &error_fatal
);
2718 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2720 /* advertise support for dedicated HP event source to guests */
2721 if (spapr
->use_hotplug_event_source
) {
2722 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2725 /* advertise support for HPT resizing */
2726 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2727 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2730 /* advertise support for ibm,dyamic-memory-v2 */
2731 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2733 /* advertise XIVE on POWER9 machines */
2734 if (spapr
->irq
->xive
) {
2735 spapr_ovec_set(spapr
->ov5
, OV5_XIVE_EXPLOIT
);
2739 spapr_init_cpus(spapr
);
2742 * check we don't have a memory-less/cpu-less NUMA node
2743 * Firmware relies on the existing memory/cpu topology to provide the
2744 * NUMA topology to the kernel.
2745 * And the linux kernel needs to know the NUMA topology at start
2746 * to be able to hotplug CPUs later.
2748 if (machine
->numa_state
->num_nodes
) {
2749 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
2750 /* check for memory-less node */
2751 if (machine
->numa_state
->nodes
[i
].node_mem
== 0) {
2754 /* check for cpu-less node */
2756 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2757 if (cpu
->node_id
== i
) {
2762 /* memory-less and cpu-less node */
2765 "Memory-less/cpu-less nodes are not supported (node %d)",
2774 spapr
->gpu_numa_id
= spapr_numa_initial_nvgpu_numa_id(machine
);
2776 /* Init numa_assoc_array */
2777 spapr_numa_associativity_init(spapr
, machine
);
2779 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2780 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
2781 spapr
->max_compat_pvr
)) {
2782 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_300
);
2783 /* KVM and TCG always allow GTSE with radix... */
2784 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2786 /* ... but not with hash (currently). */
2788 if (kvm_enabled()) {
2789 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2790 kvmppc_enable_logical_ci_hcalls();
2791 kvmppc_enable_set_mode_hcall();
2793 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2794 kvmppc_enable_clear_ref_mod_hcalls();
2796 /* Enable H_PAGE_INIT */
2797 kvmppc_enable_h_page_init();
2801 memory_region_add_subregion(sysmem
, 0, machine
->ram
);
2803 /* always allocate the device memory information */
2804 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2806 /* initialize hotplug memory address space */
2807 if (machine
->ram_size
< machine
->maxram_size
) {
2808 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2810 * Limit the number of hotpluggable memory slots to half the number
2811 * slots that KVM supports, leaving the other half for PCI and other
2812 * devices. However ensure that number of slots doesn't drop below 32.
2814 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2815 SPAPR_MAX_RAM_SLOTS
;
2817 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2818 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2820 if (machine
->ram_slots
> max_memslots
) {
2821 error_report("Specified number of memory slots %"
2822 PRIu64
" exceeds max supported %d",
2823 machine
->ram_slots
, max_memslots
);
2827 machine
->device_memory
->base
= ROUND_UP(machine
->ram_size
,
2828 SPAPR_DEVICE_MEM_ALIGN
);
2829 memory_region_init(&machine
->device_memory
->mr
, OBJECT(spapr
),
2830 "device-memory", device_mem_size
);
2831 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2832 &machine
->device_memory
->mr
);
2835 if (smc
->dr_lmb_enabled
) {
2836 spapr_create_lmb_dr_connectors(spapr
);
2839 if (spapr_get_cap(spapr
, SPAPR_CAP_FWNMI
) == SPAPR_CAP_ON
) {
2840 /* Create the error string for live migration blocker */
2841 error_setg(&spapr
->fwnmi_migration_blocker
,
2842 "A machine check is being handled during migration. The handler"
2843 "may run and log hardware error on the destination");
2846 if (mc
->nvdimm_supported
) {
2847 spapr_create_nvdimm_dr_connectors(spapr
);
2850 /* Set up RTAS event infrastructure */
2851 spapr_events_init(spapr
);
2853 /* Set up the RTC RTAS interfaces */
2854 spapr_rtc_create(spapr
);
2856 /* Set up VIO bus */
2857 spapr
->vio_bus
= spapr_vio_bus_init();
2859 for (i
= 0; serial_hd(i
); i
++) {
2860 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2863 /* We always have at least the nvram device on VIO */
2864 spapr_create_nvram(spapr
);
2867 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2868 * connectors (described in root DT node's "ibm,drc-types" property)
2869 * are pre-initialized here. additional child connectors (such as
2870 * connectors for a PHBs PCI slots) are added as needed during their
2871 * parent's realization.
2873 if (smc
->dr_phb_enabled
) {
2874 for (i
= 0; i
< SPAPR_MAX_PHBS
; i
++) {
2875 spapr_dr_connector_new(OBJECT(machine
), TYPE_SPAPR_DRC_PHB
, i
);
2880 spapr_pci_rtas_init();
2882 phb
= spapr_create_default_phb();
2884 for (i
= 0; i
< nb_nics
; i
++) {
2885 NICInfo
*nd
= &nd_table
[i
];
2888 nd
->model
= g_strdup("spapr-vlan");
2891 if (g_str_equal(nd
->model
, "spapr-vlan") ||
2892 g_str_equal(nd
->model
, "ibmveth")) {
2893 spapr_vlan_create(spapr
->vio_bus
, nd
);
2895 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2899 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2900 spapr_vscsi_create(spapr
->vio_bus
);
2904 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
2905 spapr
->has_graphics
= true;
2906 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2910 if (smc
->use_ohci_by_default
) {
2911 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2913 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2916 if (spapr
->has_graphics
) {
2917 USBBus
*usb_bus
= usb_bus_find(-1);
2919 usb_create_simple(usb_bus
, "usb-kbd");
2920 usb_create_simple(usb_bus
, "usb-mouse");
2924 if (kernel_filename
) {
2925 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2926 translate_kernel_address
, spapr
,
2927 NULL
, NULL
, NULL
, NULL
, 1,
2928 PPC_ELF_MACHINE
, 0, 0);
2929 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
2930 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2931 translate_kernel_address
, spapr
,
2932 NULL
, NULL
, NULL
, NULL
, 0,
2933 PPC_ELF_MACHINE
, 0, 0);
2934 spapr
->kernel_le
= spapr
->kernel_size
> 0;
2936 if (spapr
->kernel_size
< 0) {
2937 error_report("error loading %s: %s", kernel_filename
,
2938 load_elf_strerror(spapr
->kernel_size
));
2943 if (initrd_filename
) {
2944 /* Try to locate the initrd in the gap between the kernel
2945 * and the firmware. Add a bit of space just in case
2947 spapr
->initrd_base
= (spapr
->kernel_addr
+ spapr
->kernel_size
2948 + 0x1ffff) & ~0xffff;
2949 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
2952 - spapr
->initrd_base
);
2953 if (spapr
->initrd_size
< 0) {
2954 error_report("could not load initial ram disk '%s'",
2961 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
2963 error_report("Could not find LPAR firmware '%s'", bios_name
);
2966 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
2968 error_report("Could not load LPAR firmware '%s'", filename
);
2973 /* FIXME: Should register things through the MachineState's qdev
2974 * interface, this is a legacy from the sPAPREnvironment structure
2975 * which predated MachineState but had a similar function */
2976 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
2977 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY
, 1,
2978 &savevm_htab_handlers
, spapr
);
2980 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine
));
2982 qemu_register_boot_set(spapr_boot_set
, spapr
);
2985 * Nothing needs to be done to resume a suspended guest because
2986 * suspending does not change the machine state, so no need for
2987 * a ->wakeup method.
2989 qemu_register_wakeup_support();
2991 if (kvm_enabled()) {
2992 /* to stop and start vmclock */
2993 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
2996 kvmppc_spapr_enable_inkernel_multitce();
2999 qemu_cond_init(&spapr
->fwnmi_machine_check_interlock_cond
);
3002 #define DEFAULT_KVM_TYPE "auto"
3003 static int spapr_kvm_type(MachineState
*machine
, const char *vm_type
)
3006 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to
3007 * accomodate the 'HV' and 'PV' formats that exists in the
3008 * wild. The 'auto' mode is being introduced already as
3009 * lower-case, thus we don't need to bother checking for
3012 if (!vm_type
|| !strcmp(vm_type
, DEFAULT_KVM_TYPE
)) {
3016 if (!g_ascii_strcasecmp(vm_type
, "hv")) {
3020 if (!g_ascii_strcasecmp(vm_type
, "pr")) {
3024 error_report("Unknown kvm-type specified '%s'", vm_type
);
3029 * Implementation of an interface to adjust firmware path
3030 * for the bootindex property handling.
3032 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
3035 #define CAST(type, obj, name) \
3036 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3037 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
3038 SpaprPhbState
*phb
= CAST(SpaprPhbState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
3039 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
3040 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3043 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
3044 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
3045 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
3049 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3050 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3051 * 0x8000 | (target << 8) | (bus << 5) | lun
3052 * (see the "Logical unit addressing format" table in SAM5)
3054 unsigned id
= 0x8000 | (d
->id
<< 8) | (d
->channel
<< 5) | d
->lun
;
3055 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3056 (uint64_t)id
<< 48);
3057 } else if (virtio
) {
3059 * We use SRP luns of the form 01000000 | (target << 8) | lun
3060 * in the top 32 bits of the 64-bit LUN
3061 * Note: the quote above is from SLOF and it is wrong,
3062 * the actual binding is:
3063 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3065 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
3066 if (d
->lun
>= 256) {
3067 /* Use the LUN "flat space addressing method" */
3070 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3071 (uint64_t)id
<< 32);
3074 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3075 * in the top 32 bits of the 64-bit LUN
3077 unsigned usb_port
= atoi(usb
->port
->path
);
3078 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
3079 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3080 (uint64_t)id
<< 32);
3085 * SLOF probes the USB devices, and if it recognizes that the device is a
3086 * storage device, it changes its name to "storage" instead of "usb-host",
3087 * and additionally adds a child node for the SCSI LUN, so the correct
3088 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3090 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
3091 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
3092 if (usb_host_dev_is_scsi_storage(usbdev
)) {
3093 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
3098 /* Replace "pci" with "pci@800000020000000" */
3099 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
3103 /* Same logic as virtio above */
3104 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
3105 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
3108 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
3109 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3110 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3111 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
3115 return spapr_pci_fw_dev_name(pcidev
);
3121 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
3123 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3125 return g_strdup(spapr
->kvm_type
);
3128 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
3130 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3132 g_free(spapr
->kvm_type
);
3133 spapr
->kvm_type
= g_strdup(value
);
3136 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
3138 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3140 return spapr
->use_hotplug_event_source
;
3143 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
3146 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3148 spapr
->use_hotplug_event_source
= value
;
3151 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
3156 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
3158 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3160 switch (spapr
->resize_hpt
) {
3161 case SPAPR_RESIZE_HPT_DEFAULT
:
3162 return g_strdup("default");
3163 case SPAPR_RESIZE_HPT_DISABLED
:
3164 return g_strdup("disabled");
3165 case SPAPR_RESIZE_HPT_ENABLED
:
3166 return g_strdup("enabled");
3167 case SPAPR_RESIZE_HPT_REQUIRED
:
3168 return g_strdup("required");
3170 g_assert_not_reached();
3173 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3175 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3177 if (strcmp(value
, "default") == 0) {
3178 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3179 } else if (strcmp(value
, "disabled") == 0) {
3180 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3181 } else if (strcmp(value
, "enabled") == 0) {
3182 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3183 } else if (strcmp(value
, "required") == 0) {
3184 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3186 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3190 static char *spapr_get_ic_mode(Object
*obj
, Error
**errp
)
3192 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3194 if (spapr
->irq
== &spapr_irq_xics_legacy
) {
3195 return g_strdup("legacy");
3196 } else if (spapr
->irq
== &spapr_irq_xics
) {
3197 return g_strdup("xics");
3198 } else if (spapr
->irq
== &spapr_irq_xive
) {
3199 return g_strdup("xive");
3200 } else if (spapr
->irq
== &spapr_irq_dual
) {
3201 return g_strdup("dual");
3203 g_assert_not_reached();
3206 static void spapr_set_ic_mode(Object
*obj
, const char *value
, Error
**errp
)
3208 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3210 if (SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
3211 error_setg(errp
, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3215 /* The legacy IRQ backend can not be set */
3216 if (strcmp(value
, "xics") == 0) {
3217 spapr
->irq
= &spapr_irq_xics
;
3218 } else if (strcmp(value
, "xive") == 0) {
3219 spapr
->irq
= &spapr_irq_xive
;
3220 } else if (strcmp(value
, "dual") == 0) {
3221 spapr
->irq
= &spapr_irq_dual
;
3223 error_setg(errp
, "Bad value for \"ic-mode\" property");
3227 static char *spapr_get_host_model(Object
*obj
, Error
**errp
)
3229 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3231 return g_strdup(spapr
->host_model
);
3234 static void spapr_set_host_model(Object
*obj
, const char *value
, Error
**errp
)
3236 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3238 g_free(spapr
->host_model
);
3239 spapr
->host_model
= g_strdup(value
);
3242 static char *spapr_get_host_serial(Object
*obj
, Error
**errp
)
3244 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3246 return g_strdup(spapr
->host_serial
);
3249 static void spapr_set_host_serial(Object
*obj
, const char *value
, Error
**errp
)
3251 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3253 g_free(spapr
->host_serial
);
3254 spapr
->host_serial
= g_strdup(value
);
3257 static void spapr_instance_init(Object
*obj
)
3259 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3260 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3261 MachineState
*ms
= MACHINE(spapr
);
3262 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
3265 * NVDIMM support went live in 5.1 without considering that, in
3266 * other archs, the user needs to enable NVDIMM support with the
3267 * 'nvdimm' machine option and the default behavior is NVDIMM
3268 * support disabled. It is too late to roll back to the standard
3269 * behavior without breaking 5.1 guests.
3271 if (mc
->nvdimm_supported
) {
3272 ms
->nvdimms_state
->is_enabled
= true;
3275 spapr
->htab_fd
= -1;
3276 spapr
->use_hotplug_event_source
= true;
3277 spapr
->kvm_type
= g_strdup(DEFAULT_KVM_TYPE
);
3278 object_property_add_str(obj
, "kvm-type",
3279 spapr_get_kvm_type
, spapr_set_kvm_type
);
3280 object_property_set_description(obj
, "kvm-type",
3281 "Specifies the KVM virtualization mode (auto,"
3282 " hv, pr). Defaults to 'auto'. This mode will use"
3283 " any available KVM module loaded in the host,"
3284 " where kvm_hv takes precedence if both kvm_hv and"
3285 " kvm_pr are loaded.");
3286 object_property_add_bool(obj
, "modern-hotplug-events",
3287 spapr_get_modern_hotplug_events
,
3288 spapr_set_modern_hotplug_events
);
3289 object_property_set_description(obj
, "modern-hotplug-events",
3290 "Use dedicated hotplug event mechanism in"
3291 " place of standard EPOW events when possible"
3292 " (required for memory hot-unplug support)");
3293 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3294 "Maximum permitted CPU compatibility mode");
3296 object_property_add_str(obj
, "resize-hpt",
3297 spapr_get_resize_hpt
, spapr_set_resize_hpt
);
3298 object_property_set_description(obj
, "resize-hpt",
3299 "Resizing of the Hash Page Table (enabled, disabled, required)");
3300 object_property_add_uint32_ptr(obj
, "vsmt",
3301 &spapr
->vsmt
, OBJ_PROP_FLAG_READWRITE
);
3302 object_property_set_description(obj
, "vsmt",
3303 "Virtual SMT: KVM behaves as if this were"
3304 " the host's SMT mode");
3306 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3307 spapr_get_msix_emulation
, NULL
);
3309 object_property_add_uint64_ptr(obj
, "kernel-addr",
3310 &spapr
->kernel_addr
, OBJ_PROP_FLAG_READWRITE
);
3311 object_property_set_description(obj
, "kernel-addr",
3312 stringify(KERNEL_LOAD_ADDR
)
3313 " for -kernel is the default");
3314 spapr
->kernel_addr
= KERNEL_LOAD_ADDR
;
3315 /* The machine class defines the default interrupt controller mode */
3316 spapr
->irq
= smc
->irq
;
3317 object_property_add_str(obj
, "ic-mode", spapr_get_ic_mode
,
3319 object_property_set_description(obj
, "ic-mode",
3320 "Specifies the interrupt controller mode (xics, xive, dual)");
3322 object_property_add_str(obj
, "host-model",
3323 spapr_get_host_model
, spapr_set_host_model
);
3324 object_property_set_description(obj
, "host-model",
3325 "Host model to advertise in guest device tree");
3326 object_property_add_str(obj
, "host-serial",
3327 spapr_get_host_serial
, spapr_set_host_serial
);
3328 object_property_set_description(obj
, "host-serial",
3329 "Host serial number to advertise in guest device tree");
3332 static void spapr_machine_finalizefn(Object
*obj
)
3334 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3336 g_free(spapr
->kvm_type
);
3339 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3341 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
3342 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3343 CPUPPCState
*env
= &cpu
->env
;
3345 cpu_synchronize_state(cs
);
3346 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */
3347 if (spapr
->fwnmi_system_reset_addr
!= -1) {
3348 uint64_t rtas_addr
, addr
;
3350 /* get rtas addr from fdt */
3351 rtas_addr
= spapr_get_rtas_addr();
3353 qemu_system_guest_panicked(NULL
);
3357 addr
= rtas_addr
+ RTAS_ERROR_LOG_MAX
+ cs
->cpu_index
* sizeof(uint64_t)*2;
3358 stq_be_phys(&address_space_memory
, addr
, env
->gpr
[3]);
3359 stq_be_phys(&address_space_memory
, addr
+ sizeof(uint64_t), 0);
3362 ppc_cpu_do_system_reset(cs
);
3363 if (spapr
->fwnmi_system_reset_addr
!= -1) {
3364 env
->nip
= spapr
->fwnmi_system_reset_addr
;
3368 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3373 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3377 int spapr_lmb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3378 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3383 addr
= spapr_drc_index(drc
) * SPAPR_MEMORY_BLOCK_SIZE
;
3384 node
= object_property_get_uint(OBJECT(drc
->dev
), PC_DIMM_NODE_PROP
,
3386 *fdt_start_offset
= spapr_dt_memory_node(spapr
, fdt
, node
, addr
,
3387 SPAPR_MEMORY_BLOCK_SIZE
);
3391 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3392 bool dedicated_hp_event_source
)
3395 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3397 uint64_t addr
= addr_start
;
3398 bool hotplugged
= spapr_drc_hotplugged(dev
);
3400 for (i
= 0; i
< nr_lmbs
; i
++) {
3401 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3402 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3406 * memory_device_get_free_addr() provided a range of free addresses
3407 * that doesn't overlap with any existing mapping at pre-plug. The
3408 * corresponding LMB DRCs are thus assumed to be all attachable.
3410 spapr_drc_attach(drc
, dev
);
3412 spapr_drc_reset(drc
);
3414 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3416 /* send hotplug notification to the
3417 * guest only in case of hotplugged memory
3420 if (dedicated_hp_event_source
) {
3421 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3422 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3424 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3426 spapr_drc_index(drc
));
3428 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3434 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3436 SpaprMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3437 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3438 uint64_t size
, addr
;
3440 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
3442 size
= memory_device_get_region_size(MEMORY_DEVICE(dev
), &error_abort
);
3444 pc_dimm_plug(dimm
, MACHINE(ms
));
3447 addr
= object_property_get_uint(OBJECT(dimm
),
3448 PC_DIMM_ADDR_PROP
, &error_abort
);
3449 spapr_add_lmbs(dev
, addr
, size
,
3450 spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
));
3452 slot
= object_property_get_int(OBJECT(dimm
),
3453 PC_DIMM_SLOT_PROP
, &error_abort
);
3454 /* We should have valid slot number at this point */
3455 g_assert(slot
>= 0);
3456 spapr_add_nvdimm(dev
, slot
);
3460 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3463 const SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3464 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3465 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
3466 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3467 Error
*local_err
= NULL
;
3472 if (!smc
->dr_lmb_enabled
) {
3473 error_setg(errp
, "Memory hotplug not supported for this machine");
3477 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &local_err
);
3479 error_propagate(errp
, local_err
);
3484 if (!spapr_nvdimm_validate(hotplug_dev
, NVDIMM(dev
), size
, errp
)) {
3487 } else if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3488 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3489 "%" PRIu64
" MB", SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
3493 memdev
= object_property_get_link(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
,
3495 pagesize
= host_memory_backend_pagesize(MEMORY_BACKEND(memdev
));
3496 if (!spapr_check_pagesize(spapr
, pagesize
, errp
)) {
3500 pc_dimm_pre_plug(dimm
, MACHINE(hotplug_dev
), NULL
, errp
);
3503 struct SpaprDimmState
{
3506 QTAILQ_ENTRY(SpaprDimmState
) next
;
3509 static SpaprDimmState
*spapr_pending_dimm_unplugs_find(SpaprMachineState
*s
,
3512 SpaprDimmState
*dimm_state
= NULL
;
3514 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3515 if (dimm_state
->dimm
== dimm
) {
3522 static SpaprDimmState
*spapr_pending_dimm_unplugs_add(SpaprMachineState
*spapr
,
3526 SpaprDimmState
*ds
= NULL
;
3529 * If this request is for a DIMM whose removal had failed earlier
3530 * (due to guest's refusal to remove the LMBs), we would have this
3531 * dimm already in the pending_dimm_unplugs list. In that
3532 * case don't add again.
3534 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3536 ds
= g_malloc0(sizeof(SpaprDimmState
));
3537 ds
->nr_lmbs
= nr_lmbs
;
3539 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3544 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState
*spapr
,
3545 SpaprDimmState
*dimm_state
)
3547 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3551 static SpaprDimmState
*spapr_recover_pending_dimm_state(SpaprMachineState
*ms
,
3555 uint64_t size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
),
3557 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3558 uint32_t avail_lmbs
= 0;
3559 uint64_t addr_start
, addr
;
3562 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3566 for (i
= 0; i
< nr_lmbs
; i
++) {
3567 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3568 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3573 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3576 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3579 void spapr_memory_unplug_rollback(SpaprMachineState
*spapr
, DeviceState
*dev
)
3585 uint64_t size
, addr_start
, addr
;
3586 g_autofree
char *qapi_error
= NULL
;
3593 dimm
= PC_DIMM(dev
);
3594 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3597 * 'ds == NULL' would mean that the DIMM doesn't have a pending
3598 * unplug state, but one of its DRC is marked as unplug_requested.
3599 * This is bad and weird enough to g_assert() out.
3603 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3605 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3606 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3608 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3612 for (i
= 0; i
< nr_lmbs
; i
++) {
3613 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3614 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3617 drc
->unplug_requested
= false;
3618 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3622 * Tell QAPI that something happened and the memory
3623 * hotunplug wasn't successful.
3625 qapi_error
= g_strdup_printf("Memory hotunplug rejected by the guest "
3626 "for device %s", dev
->id
);
3627 qapi_event_send_mem_unplug_error(dev
->id
, qapi_error
);
3630 /* Callback to be called during DRC release. */
3631 void spapr_lmb_release(DeviceState
*dev
)
3633 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3634 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3635 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3637 /* This information will get lost if a migration occurs
3638 * during the unplug process. In this case recover it. */
3640 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3642 /* The DRC being examined by the caller at least must be counted */
3643 g_assert(ds
->nr_lmbs
);
3646 if (--ds
->nr_lmbs
) {
3651 * Now that all the LMBs have been removed by the guest, call the
3652 * unplug handler chain. This can never fail.
3654 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3655 object_unparent(OBJECT(dev
));
3658 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3660 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3661 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3663 /* We really shouldn't get this far without anything to unplug */
3666 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(hotplug_dev
));
3667 qdev_unrealize(dev
);
3668 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3671 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3672 DeviceState
*dev
, Error
**errp
)
3674 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3675 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3677 uint64_t size
, addr_start
, addr
;
3681 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
3682 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
3686 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3687 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3689 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3693 * An existing pending dimm state for this DIMM means that there is an
3694 * unplug operation in progress, waiting for the spapr_lmb_release
3695 * callback to complete the job (BQL can't cover that far). In this case,
3696 * bail out to avoid detaching DRCs that were already released.
3698 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3699 error_setg(errp
, "Memory unplug already in progress for device %s",
3704 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3707 for (i
= 0; i
< nr_lmbs
; i
++) {
3708 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3709 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3712 spapr_drc_unplug_request(drc
);
3713 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3716 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3717 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3718 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3719 nr_lmbs
, spapr_drc_index(drc
));
3722 /* Callback to be called during DRC release. */
3723 void spapr_core_release(DeviceState
*dev
)
3725 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3727 /* Call the unplug handler chain. This can never fail. */
3728 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3729 object_unparent(OBJECT(dev
));
3732 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3734 MachineState
*ms
= MACHINE(hotplug_dev
);
3735 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3736 CPUCore
*cc
= CPU_CORE(dev
);
3737 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3739 if (smc
->pre_2_10_has_unused_icps
) {
3740 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3743 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3744 CPUState
*cs
= CPU(sc
->threads
[i
]);
3746 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3751 core_slot
->cpu
= NULL
;
3752 qdev_unrealize(dev
);
3756 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3759 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3762 CPUCore
*cc
= CPU_CORE(dev
);
3764 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3765 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3770 error_setg(errp
, "Boot CPU core may not be unplugged");
3774 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3775 spapr_vcpu_id(spapr
, cc
->core_id
));
3778 if (!spapr_drc_unplug_requested(drc
)) {
3779 spapr_drc_unplug_request(drc
);
3780 spapr_hotplug_req_remove_by_index(drc
);
3782 error_setg(errp
, "core-id %d unplug is still pending, %d seconds "
3783 "timeout remaining",
3784 cc
->core_id
, spapr_drc_unplug_timeout_remaining_sec(drc
));
3788 int spapr_core_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3789 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3791 SpaprCpuCore
*core
= SPAPR_CPU_CORE(drc
->dev
);
3792 CPUState
*cs
= CPU(core
->threads
[0]);
3793 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3794 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3795 int id
= spapr_get_vcpu_id(cpu
);
3796 g_autofree
char *nodename
= NULL
;
3799 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3800 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3802 spapr_dt_cpu(cs
, fdt
, offset
, spapr
);
3805 * spapr_dt_cpu() does not fill the 'name' property in the
3806 * CPU node. The function is called during boot process, before
3807 * and after CAS, and overwriting the 'name' property written
3808 * by SLOF is not allowed.
3810 * Write it manually after spapr_dt_cpu(). This makes the hotplug
3811 * CPUs more compatible with the coldplugged ones, which have
3812 * the 'name' property. Linux Kernel also relies on this
3813 * property to identify CPU nodes.
3815 _FDT((fdt_setprop_string(fdt
, offset
, "name", nodename
)));
3817 *fdt_start_offset
= offset
;
3821 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3823 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3824 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3825 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3826 SpaprCpuCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3827 CPUCore
*cc
= CPU_CORE(dev
);
3830 CPUArchId
*core_slot
;
3832 bool hotplugged
= spapr_drc_hotplugged(dev
);
3835 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3836 g_assert(core_slot
); /* Already checked in spapr_core_pre_plug() */
3838 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3839 spapr_vcpu_id(spapr
, cc
->core_id
));
3841 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3845 * spapr_core_pre_plug() already buys us this is a brand new
3846 * core being plugged into a free slot. Nothing should already
3847 * be attached to the corresponding DRC.
3849 spapr_drc_attach(drc
, dev
);
3853 * Send hotplug notification interrupt to the guest only
3854 * in case of hotplugged CPUs.
3856 spapr_hotplug_req_add_by_index(drc
);
3858 spapr_drc_reset(drc
);
3862 core_slot
->cpu
= OBJECT(dev
);
3865 * Set compatibility mode to match the boot CPU, which was either set
3866 * by the machine reset code or by CAS. This really shouldn't fail at
3870 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3871 ppc_set_compat(core
->threads
[i
], POWERPC_CPU(first_cpu
)->compat_pvr
,
3876 if (smc
->pre_2_10_has_unused_icps
) {
3877 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3878 cs
= CPU(core
->threads
[i
]);
3879 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
3884 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3887 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
3888 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
3889 CPUCore
*cc
= CPU_CORE(dev
);
3890 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3891 const char *type
= object_get_typename(OBJECT(dev
));
3892 CPUArchId
*core_slot
;
3894 unsigned int smp_threads
= machine
->smp
.threads
;
3896 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
3897 error_setg(errp
, "CPU hotplug not supported for this machine");
3901 if (strcmp(base_core_type
, type
)) {
3902 error_setg(errp
, "CPU core type should be %s", base_core_type
);
3906 if (cc
->core_id
% smp_threads
) {
3907 error_setg(errp
, "invalid core id %d", cc
->core_id
);
3912 * In general we should have homogeneous threads-per-core, but old
3913 * (pre hotplug support) machine types allow the last core to have
3914 * reduced threads as a compatibility hack for when we allowed
3915 * total vcpus not a multiple of threads-per-core.
3917 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
3918 error_setg(errp
, "invalid nr-threads %d, must be %d", cc
->nr_threads
,
3923 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3925 error_setg(errp
, "core id %d out of range", cc
->core_id
);
3929 if (core_slot
->cpu
) {
3930 error_setg(errp
, "core %d already populated", cc
->core_id
);
3934 numa_cpu_pre_plug(core_slot
, dev
, errp
);
3937 int spapr_phb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3938 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3940 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(drc
->dev
);
3943 intc_phandle
= spapr_irq_get_phandle(spapr
, spapr
->fdt_blob
, errp
);
3944 if (intc_phandle
<= 0) {
3948 if (spapr_dt_phb(spapr
, sphb
, intc_phandle
, fdt
, fdt_start_offset
)) {
3949 error_setg(errp
, "unable to create FDT node for PHB %d", sphb
->index
);
3953 /* generally SLOF creates these, for hotplug it's up to QEMU */
3954 _FDT(fdt_setprop_string(fdt
, *fdt_start_offset
, "name", "pci"));
3959 static bool spapr_phb_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3962 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3963 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3964 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3965 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
3968 if (dev
->hotplugged
&& !smc
->dr_phb_enabled
) {
3969 error_setg(errp
, "PHB hotplug not supported for this machine");
3973 if (sphb
->index
== (uint32_t)-1) {
3974 error_setg(errp
, "\"index\" for PAPR PHB is mandatory");
3978 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
3979 if (drc
&& drc
->dev
) {
3980 error_setg(errp
, "PHB %d already attached", sphb
->index
);
3985 * This will check that sphb->index doesn't exceed the maximum number of
3986 * PHBs for the current machine type.
3989 smc
->phb_placement(spapr
, sphb
->index
,
3990 &sphb
->buid
, &sphb
->io_win_addr
,
3991 &sphb
->mem_win_addr
, &sphb
->mem64_win_addr
,
3992 windows_supported
, sphb
->dma_liobn
,
3993 &sphb
->nv2_gpa_win_addr
, &sphb
->nv2_atsd_win_addr
,
3997 static void spapr_phb_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3999 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4000 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
4001 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4003 bool hotplugged
= spapr_drc_hotplugged(dev
);
4005 if (!smc
->dr_phb_enabled
) {
4009 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4010 /* hotplug hooks should check it's enabled before getting this far */
4013 /* spapr_phb_pre_plug() already checked the DRC is attachable */
4014 spapr_drc_attach(drc
, dev
);
4017 spapr_hotplug_req_add_by_index(drc
);
4019 spapr_drc_reset(drc
);
4023 void spapr_phb_release(DeviceState
*dev
)
4025 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
4027 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
4028 object_unparent(OBJECT(dev
));
4031 static void spapr_phb_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4033 qdev_unrealize(dev
);
4036 static void spapr_phb_unplug_request(HotplugHandler
*hotplug_dev
,
4037 DeviceState
*dev
, Error
**errp
)
4039 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4042 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4045 if (!spapr_drc_unplug_requested(drc
)) {
4046 spapr_drc_unplug_request(drc
);
4047 spapr_hotplug_req_remove_by_index(drc
);
4050 "PCI Host Bridge unplug already in progress for device %s",
4056 bool spapr_tpm_proxy_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
4059 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4061 if (spapr
->tpm_proxy
!= NULL
) {
4062 error_setg(errp
, "Only one TPM proxy can be specified for this machine");
4069 static void spapr_tpm_proxy_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4071 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4072 SpaprTpmProxy
*tpm_proxy
= SPAPR_TPM_PROXY(dev
);
4074 /* Already checked in spapr_tpm_proxy_pre_plug() */
4075 g_assert(spapr
->tpm_proxy
== NULL
);
4077 spapr
->tpm_proxy
= tpm_proxy
;
4080 static void spapr_tpm_proxy_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4082 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4084 qdev_unrealize(dev
);
4085 object_unparent(OBJECT(dev
));
4086 spapr
->tpm_proxy
= NULL
;
4089 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
4090 DeviceState
*dev
, Error
**errp
)
4092 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4093 spapr_memory_plug(hotplug_dev
, dev
);
4094 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4095 spapr_core_plug(hotplug_dev
, dev
);
4096 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4097 spapr_phb_plug(hotplug_dev
, dev
);
4098 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4099 spapr_tpm_proxy_plug(hotplug_dev
, dev
);
4103 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
4104 DeviceState
*dev
, Error
**errp
)
4106 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4107 spapr_memory_unplug(hotplug_dev
, dev
);
4108 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4109 spapr_core_unplug(hotplug_dev
, dev
);
4110 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4111 spapr_phb_unplug(hotplug_dev
, dev
);
4112 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4113 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4117 bool spapr_memory_hot_unplug_supported(SpaprMachineState
*spapr
)
4119 return spapr_ovec_test(spapr
->ov5_cas
, OV5_HP_EVT
) ||
4121 * CAS will process all pending unplug requests.
4123 * HACK: a guest could theoretically have cleared all bits in OV5,
4124 * but none of the guests we care for do.
4126 spapr_ovec_empty(spapr
->ov5_cas
);
4129 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
4130 DeviceState
*dev
, Error
**errp
)
4132 SpaprMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4133 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
4134 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4136 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4137 if (spapr_memory_hot_unplug_supported(sms
)) {
4138 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
4140 error_setg(errp
, "Memory hot unplug not supported for this guest");
4142 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4143 if (!mc
->has_hotpluggable_cpus
) {
4144 error_setg(errp
, "CPU hot unplug not supported on this machine");
4147 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
4148 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4149 if (!smc
->dr_phb_enabled
) {
4150 error_setg(errp
, "PHB hot unplug not supported on this machine");
4153 spapr_phb_unplug_request(hotplug_dev
, dev
, errp
);
4154 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4155 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4159 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
4160 DeviceState
*dev
, Error
**errp
)
4162 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4163 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
4164 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4165 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
4166 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4167 spapr_phb_pre_plug(hotplug_dev
, dev
, errp
);
4168 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4169 spapr_tpm_proxy_pre_plug(hotplug_dev
, dev
, errp
);
4173 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
4176 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
4177 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
) ||
4178 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
) ||
4179 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4180 return HOTPLUG_HANDLER(machine
);
4182 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_DEVICE
)) {
4183 PCIDevice
*pcidev
= PCI_DEVICE(dev
);
4184 PCIBus
*root
= pci_device_root_bus(pcidev
);
4185 SpaprPhbState
*phb
=
4186 (SpaprPhbState
*)object_dynamic_cast(OBJECT(BUS(root
)->parent
),
4187 TYPE_SPAPR_PCI_HOST_BRIDGE
);
4190 return HOTPLUG_HANDLER(phb
);
4196 static CpuInstanceProperties
4197 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
4199 CPUArchId
*core_slot
;
4200 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4202 /* make sure possible_cpu are intialized */
4203 mc
->possible_cpu_arch_ids(machine
);
4204 /* get CPU core slot containing thread that matches cpu_index */
4205 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
4207 return core_slot
->props
;
4210 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
4212 return idx
/ ms
->smp
.cores
% ms
->numa_state
->num_nodes
;
4215 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
4218 unsigned int smp_threads
= machine
->smp
.threads
;
4219 unsigned int smp_cpus
= machine
->smp
.cpus
;
4220 const char *core_type
;
4221 int spapr_max_cores
= machine
->smp
.max_cpus
/ smp_threads
;
4222 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4224 if (!mc
->has_hotpluggable_cpus
) {
4225 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
4227 if (machine
->possible_cpus
) {
4228 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
4229 return machine
->possible_cpus
;
4232 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
4234 error_report("Unable to find sPAPR CPU Core definition");
4238 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
4239 sizeof(CPUArchId
) * spapr_max_cores
);
4240 machine
->possible_cpus
->len
= spapr_max_cores
;
4241 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
4242 int core_id
= i
* smp_threads
;
4244 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
4245 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
4246 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
4247 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
4248 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
4250 return machine
->possible_cpus
;
4253 static bool spapr_phb_placement(SpaprMachineState
*spapr
, uint32_t index
,
4254 uint64_t *buid
, hwaddr
*pio
,
4255 hwaddr
*mmio32
, hwaddr
*mmio64
,
4256 unsigned n_dma
, uint32_t *liobns
,
4257 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4260 * New-style PHB window placement.
4262 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4263 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4266 * Some guest kernels can't work with MMIO windows above 1<<46
4267 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4269 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4270 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
4271 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
4272 * 1TiB 64-bit MMIO windows for each PHB.
4274 const uint64_t base_buid
= 0x800000020000000ULL
;
4277 /* Sanity check natural alignments */
4278 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4279 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4280 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
4281 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
4282 /* Sanity check bounds */
4283 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
4284 SPAPR_PCI_MEM32_WIN_SIZE
);
4285 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
4286 SPAPR_PCI_MEM64_WIN_SIZE
);
4288 if (index
>= SPAPR_MAX_PHBS
) {
4289 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
4290 SPAPR_MAX_PHBS
- 1);
4294 *buid
= base_buid
+ index
;
4295 for (i
= 0; i
< n_dma
; ++i
) {
4296 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4299 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
4300 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
4301 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
4303 *nv2gpa
= SPAPR_PCI_NV2RAM64_WIN_BASE
+ index
* SPAPR_PCI_NV2RAM64_WIN_SIZE
;
4304 *nv2atsd
= SPAPR_PCI_NV2ATSD_WIN_BASE
+ index
* SPAPR_PCI_NV2ATSD_WIN_SIZE
;
4308 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
4310 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4312 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
4315 static void spapr_ics_resend(XICSFabric
*dev
)
4317 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4319 ics_resend(spapr
->ics
);
4322 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
4324 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
4326 return cpu
? spapr_cpu_state(cpu
)->icp
: NULL
;
4329 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
4332 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
4334 spapr_irq_print_info(spapr
, mon
);
4335 monitor_printf(mon
, "irqchip: %s\n",
4336 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
4340 * This is a XIVE only operation
4342 static int spapr_match_nvt(XiveFabric
*xfb
, uint8_t format
,
4343 uint8_t nvt_blk
, uint32_t nvt_idx
,
4344 bool cam_ignore
, uint8_t priority
,
4345 uint32_t logic_serv
, XiveTCTXMatch
*match
)
4347 SpaprMachineState
*spapr
= SPAPR_MACHINE(xfb
);
4348 XivePresenter
*xptr
= XIVE_PRESENTER(spapr
->active_intc
);
4349 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
4352 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
4353 priority
, logic_serv
, match
);
4359 * When we implement the save and restore of the thread interrupt
4360 * contexts in the enter/exit CPU handlers of the machine and the
4361 * escalations in QEMU, we should be able to handle non dispatched
4364 * Until this is done, the sPAPR machine should find at least one
4365 * matching context always.
4368 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: NVT %x/%x is not dispatched\n",
4375 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
4377 return cpu
->vcpu_id
;
4380 bool spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
4382 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
4383 MachineState
*ms
= MACHINE(spapr
);
4386 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
4388 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
4389 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
4390 error_append_hint(errp
, "Adjust the number of cpus to %d "
4391 "or try to raise the number of threads per core\n",
4392 vcpu_id
* ms
->smp
.threads
/ spapr
->vsmt
);
4396 cpu
->vcpu_id
= vcpu_id
;
4400 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
4405 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
4407 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
4415 static void spapr_cpu_exec_enter(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4417 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4419 /* These are only called by TCG, KVM maintains dispatch state */
4421 spapr_cpu
->prod
= false;
4422 if (spapr_cpu
->vpa_addr
) {
4423 CPUState
*cs
= CPU(cpu
);
4426 dispatch
= ldl_be_phys(cs
->as
,
4427 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4429 if ((dispatch
& 1) != 0) {
4430 qemu_log_mask(LOG_GUEST_ERROR
,
4431 "VPA: incorrect dispatch counter value for "
4432 "dispatched partition %u, correcting.\n", dispatch
);
4436 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4440 static void spapr_cpu_exec_exit(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4442 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4444 if (spapr_cpu
->vpa_addr
) {
4445 CPUState
*cs
= CPU(cpu
);
4448 dispatch
= ldl_be_phys(cs
->as
,
4449 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4451 if ((dispatch
& 1) != 1) {
4452 qemu_log_mask(LOG_GUEST_ERROR
,
4453 "VPA: incorrect dispatch counter value for "
4454 "preempted partition %u, correcting.\n", dispatch
);
4458 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4462 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
4464 MachineClass
*mc
= MACHINE_CLASS(oc
);
4465 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
4466 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
4467 NMIClass
*nc
= NMI_CLASS(oc
);
4468 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
4469 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
4470 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
4471 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
4472 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
4474 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
4475 mc
->ignore_boot_device_suffixes
= true;
4478 * We set up the default / latest behaviour here. The class_init
4479 * functions for the specific versioned machine types can override
4480 * these details for backwards compatibility
4482 mc
->init
= spapr_machine_init
;
4483 mc
->reset
= spapr_machine_reset
;
4484 mc
->block_default_type
= IF_SCSI
;
4485 mc
->max_cpus
= 1024;
4486 mc
->no_parallel
= 1;
4487 mc
->default_boot_order
= "";
4488 mc
->default_ram_size
= 512 * MiB
;
4489 mc
->default_ram_id
= "ppc_spapr.ram";
4490 mc
->default_display
= "std";
4491 mc
->kvm_type
= spapr_kvm_type
;
4492 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
4493 mc
->pci_allow_0_address
= true;
4494 assert(!mc
->get_hotplug_handler
);
4495 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
4496 hc
->pre_plug
= spapr_machine_device_pre_plug
;
4497 hc
->plug
= spapr_machine_device_plug
;
4498 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
4499 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
4500 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
4501 hc
->unplug_request
= spapr_machine_device_unplug_request
;
4502 hc
->unplug
= spapr_machine_device_unplug
;
4504 smc
->dr_lmb_enabled
= true;
4505 smc
->update_dt_enabled
= true;
4506 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
4507 mc
->has_hotpluggable_cpus
= true;
4508 mc
->nvdimm_supported
= true;
4509 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
4510 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
4511 nc
->nmi_monitor_handler
= spapr_nmi
;
4512 smc
->phb_placement
= spapr_phb_placement
;
4513 vhc
->hypercall
= emulate_spapr_hypercall
;
4514 vhc
->hpt_mask
= spapr_hpt_mask
;
4515 vhc
->map_hptes
= spapr_map_hptes
;
4516 vhc
->unmap_hptes
= spapr_unmap_hptes
;
4517 vhc
->hpte_set_c
= spapr_hpte_set_c
;
4518 vhc
->hpte_set_r
= spapr_hpte_set_r
;
4519 vhc
->get_pate
= spapr_get_pate
;
4520 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
4521 vhc
->cpu_exec_enter
= spapr_cpu_exec_enter
;
4522 vhc
->cpu_exec_exit
= spapr_cpu_exec_exit
;
4523 xic
->ics_get
= spapr_ics_get
;
4524 xic
->ics_resend
= spapr_ics_resend
;
4525 xic
->icp_get
= spapr_icp_get
;
4526 ispc
->print_info
= spapr_pic_print_info
;
4527 /* Force NUMA node memory size to be a multiple of
4528 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4529 * in which LMBs are represented and hot-added
4531 mc
->numa_mem_align_shift
= 28;
4532 mc
->auto_enable_numa
= true;
4534 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
4535 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
4536 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
4537 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4538 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4539 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_WORKAROUND
;
4540 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 16; /* 64kiB */
4541 smc
->default_caps
.caps
[SPAPR_CAP_NESTED_KVM_HV
] = SPAPR_CAP_OFF
;
4542 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_ON
;
4543 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_ON
;
4544 smc
->default_caps
.caps
[SPAPR_CAP_FWNMI
] = SPAPR_CAP_ON
;
4545 spapr_caps_add_properties(smc
);
4546 smc
->irq
= &spapr_irq_dual
;
4547 smc
->dr_phb_enabled
= true;
4548 smc
->linux_pci_probe
= true;
4549 smc
->smp_threads_vsmt
= true;
4550 smc
->nr_xirqs
= SPAPR_NR_XIRQS
;
4551 xfc
->match_nvt
= spapr_match_nvt
;
4554 static const TypeInfo spapr_machine_info
= {
4555 .name
= TYPE_SPAPR_MACHINE
,
4556 .parent
= TYPE_MACHINE
,
4558 .instance_size
= sizeof(SpaprMachineState
),
4559 .instance_init
= spapr_instance_init
,
4560 .instance_finalize
= spapr_machine_finalizefn
,
4561 .class_size
= sizeof(SpaprMachineClass
),
4562 .class_init
= spapr_machine_class_init
,
4563 .interfaces
= (InterfaceInfo
[]) {
4564 { TYPE_FW_PATH_PROVIDER
},
4566 { TYPE_HOTPLUG_HANDLER
},
4567 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
4568 { TYPE_XICS_FABRIC
},
4569 { TYPE_INTERRUPT_STATS_PROVIDER
},
4570 { TYPE_XIVE_FABRIC
},
4575 static void spapr_machine_latest_class_options(MachineClass
*mc
)
4577 mc
->alias
= "pseries";
4578 mc
->is_default
= true;
4581 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4582 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4585 MachineClass *mc = MACHINE_CLASS(oc); \
4586 spapr_machine_##suffix##_class_options(mc); \
4588 spapr_machine_latest_class_options(mc); \
4591 static const TypeInfo spapr_machine_##suffix##_info = { \
4592 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4593 .parent = TYPE_SPAPR_MACHINE, \
4594 .class_init = spapr_machine_##suffix##_class_init, \
4596 static void spapr_machine_register_##suffix(void) \
4598 type_register(&spapr_machine_##suffix##_info); \
4600 type_init(spapr_machine_register_##suffix)
4605 static void spapr_machine_6_0_class_options(MachineClass
*mc
)
4607 /* Defaults for the latest behaviour inherited from the base class */
4610 DEFINE_SPAPR_MACHINE(6_0
, "6.0", true);
4615 static void spapr_machine_5_2_class_options(MachineClass
*mc
)
4617 spapr_machine_6_0_class_options(mc
);
4618 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
4621 DEFINE_SPAPR_MACHINE(5_2
, "5.2", false);
4626 static void spapr_machine_5_1_class_options(MachineClass
*mc
)
4628 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4630 spapr_machine_5_2_class_options(mc
);
4631 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
4632 smc
->pre_5_2_numa_associativity
= true;
4635 DEFINE_SPAPR_MACHINE(5_1
, "5.1", false);
4640 static void spapr_machine_5_0_class_options(MachineClass
*mc
)
4642 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4643 static GlobalProperty compat
[] = {
4644 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-5.1-associativity", "on" },
4647 spapr_machine_5_1_class_options(mc
);
4648 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
4649 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4650 mc
->numa_mem_supported
= true;
4651 smc
->pre_5_1_assoc_refpoints
= true;
4654 DEFINE_SPAPR_MACHINE(5_0
, "5.0", false);
4659 static void spapr_machine_4_2_class_options(MachineClass
*mc
)
4661 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4663 spapr_machine_5_0_class_options(mc
);
4664 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
4665 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_OFF
;
4666 smc
->default_caps
.caps
[SPAPR_CAP_FWNMI
] = SPAPR_CAP_OFF
;
4667 smc
->rma_limit
= 16 * GiB
;
4668 mc
->nvdimm_supported
= false;
4671 DEFINE_SPAPR_MACHINE(4_2
, "4.2", false);
4676 static void spapr_machine_4_1_class_options(MachineClass
*mc
)
4678 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4679 static GlobalProperty compat
[] = {
4680 /* Only allow 4kiB and 64kiB IOMMU pagesizes */
4681 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pgsz", "0x11000" },
4684 spapr_machine_4_2_class_options(mc
);
4685 smc
->linux_pci_probe
= false;
4686 smc
->smp_threads_vsmt
= false;
4687 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
4688 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4691 DEFINE_SPAPR_MACHINE(4_1
, "4.1", false);
4696 static bool phb_placement_4_0(SpaprMachineState
*spapr
, uint32_t index
,
4697 uint64_t *buid
, hwaddr
*pio
,
4698 hwaddr
*mmio32
, hwaddr
*mmio64
,
4699 unsigned n_dma
, uint32_t *liobns
,
4700 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4702 if (!spapr_phb_placement(spapr
, index
, buid
, pio
, mmio32
, mmio64
, n_dma
,
4703 liobns
, nv2gpa
, nv2atsd
, errp
)) {
4711 static void spapr_machine_4_0_class_options(MachineClass
*mc
)
4713 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4715 spapr_machine_4_1_class_options(mc
);
4716 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
4717 smc
->phb_placement
= phb_placement_4_0
;
4718 smc
->irq
= &spapr_irq_xics
;
4719 smc
->pre_4_1_migration
= true;
4722 DEFINE_SPAPR_MACHINE(4_0
, "4.0", false);
4727 static void spapr_machine_3_1_class_options(MachineClass
*mc
)
4729 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4731 spapr_machine_4_0_class_options(mc
);
4732 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
4734 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4735 smc
->update_dt_enabled
= false;
4736 smc
->dr_phb_enabled
= false;
4737 smc
->broken_host_serial_model
= true;
4738 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
4739 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
4740 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
4741 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_OFF
;
4744 DEFINE_SPAPR_MACHINE(3_1
, "3.1", false);
4750 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
4752 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4754 spapr_machine_3_1_class_options(mc
);
4755 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
4757 smc
->legacy_irq_allocation
= true;
4758 smc
->nr_xirqs
= 0x400;
4759 smc
->irq
= &spapr_irq_xics_legacy
;
4762 DEFINE_SPAPR_MACHINE(3_0
, "3.0", false);
4767 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
4769 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4770 static GlobalProperty compat
[] = {
4771 { TYPE_POWERPC_CPU
, "pre-3.0-migration", "on" },
4772 { TYPE_SPAPR_CPU_CORE
, "pre-3.0-migration", "on" },
4775 spapr_machine_3_0_class_options(mc
);
4776 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
4777 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4779 /* We depend on kvm_enabled() to choose a default value for the
4780 * hpt-max-page-size capability. Of course we can't do it here
4781 * because this is too early and the HW accelerator isn't initialzed
4782 * yet. Postpone this to machine init (see default_caps_with_cpu()).
4784 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 0;
4787 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
4789 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
4791 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4793 spapr_machine_2_12_class_options(mc
);
4794 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4795 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4796 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
4799 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
4805 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
4807 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4809 spapr_machine_2_12_class_options(mc
);
4810 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
4811 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
4814 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
4820 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
4822 spapr_machine_2_11_class_options(mc
);
4823 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
4826 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
4832 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
4834 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4835 static GlobalProperty compat
[] = {
4836 { TYPE_POWERPC_CPU
, "pre-2.10-migration", "on" },
4839 spapr_machine_2_10_class_options(mc
);
4840 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
4841 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4842 smc
->pre_2_10_has_unused_icps
= true;
4843 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
4846 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
4852 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
4854 static GlobalProperty compat
[] = {
4855 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pcie-extended-configuration-space", "off" },
4858 spapr_machine_2_9_class_options(mc
);
4859 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
4860 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4861 mc
->numa_mem_align_shift
= 23;
4864 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
4870 static bool phb_placement_2_7(SpaprMachineState
*spapr
, uint32_t index
,
4871 uint64_t *buid
, hwaddr
*pio
,
4872 hwaddr
*mmio32
, hwaddr
*mmio64
,
4873 unsigned n_dma
, uint32_t *liobns
,
4874 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4876 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4877 const uint64_t base_buid
= 0x800000020000000ULL
;
4878 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
4879 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
4880 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
4881 const uint32_t max_index
= 255;
4882 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
4884 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
4885 hwaddr phb0_base
, phb_base
;
4888 /* Do we have device memory? */
4889 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
4890 /* Can't just use maxram_size, because there may be an
4891 * alignment gap between normal and device memory regions
4893 ram_top
= MACHINE(spapr
)->device_memory
->base
+
4894 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
4897 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
4899 if (index
> max_index
) {
4900 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
4905 *buid
= base_buid
+ index
;
4906 for (i
= 0; i
< n_dma
; ++i
) {
4907 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4910 phb_base
= phb0_base
+ index
* phb_spacing
;
4911 *pio
= phb_base
+ pio_offset
;
4912 *mmio32
= phb_base
+ mmio_offset
;
4914 * We don't set the 64-bit MMIO window, relying on the PHB's
4915 * fallback behaviour of automatically splitting a large "32-bit"
4916 * window into contiguous 32-bit and 64-bit windows
4924 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
4926 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4927 static GlobalProperty compat
[] = {
4928 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0xf80000000", },
4929 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem64_win_size", "0", },
4930 { TYPE_POWERPC_CPU
, "pre-2.8-migration", "on", },
4931 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-2.8-migration", "on", },
4934 spapr_machine_2_8_class_options(mc
);
4935 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
4936 mc
->default_machine_opts
= "modern-hotplug-events=off";
4937 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
4938 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4939 smc
->phb_placement
= phb_placement_2_7
;
4942 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
4948 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
4950 static GlobalProperty compat
[] = {
4951 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "ddw", "off" },
4954 spapr_machine_2_7_class_options(mc
);
4955 mc
->has_hotpluggable_cpus
= false;
4956 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
4957 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4960 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
4966 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
4968 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4969 static GlobalProperty compat
[] = {
4970 { "spapr-vlan", "use-rx-buffer-pools", "off" },
4973 spapr_machine_2_6_class_options(mc
);
4974 smc
->use_ohci_by_default
= true;
4975 compat_props_add(mc
->compat_props
, hw_compat_2_5
, hw_compat_2_5_len
);
4976 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4979 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
4985 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
4987 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4989 spapr_machine_2_5_class_options(mc
);
4990 smc
->dr_lmb_enabled
= false;
4991 compat_props_add(mc
->compat_props
, hw_compat_2_4
, hw_compat_2_4_len
);
4994 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
5000 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
5002 static GlobalProperty compat
[] = {
5003 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
5005 spapr_machine_2_4_class_options(mc
);
5006 compat_props_add(mc
->compat_props
, hw_compat_2_3
, hw_compat_2_3_len
);
5007 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5009 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
5015 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
5017 static GlobalProperty compat
[] = {
5018 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0x20000000" },
5021 spapr_machine_2_3_class_options(mc
);
5022 compat_props_add(mc
->compat_props
, hw_compat_2_2
, hw_compat_2_2_len
);
5023 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5024 mc
->default_machine_opts
= "modern-hotplug-events=off,suppress-vmdesc=on";
5026 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
5032 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
5034 spapr_machine_2_2_class_options(mc
);
5035 compat_props_add(mc
->compat_props
, hw_compat_2_1
, hw_compat_2_1_len
);
5037 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
5039 static void spapr_machine_register_types(void)
5041 type_register_static(&spapr_machine_info
);
5044 type_init(spapr_machine_register_types
)