4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
23 #include "hw/qdev-core.h"
24 #include "disas/dis-asm.h"
25 #include "exec/cpu-common.h"
26 #include "exec/hwaddr.h"
27 #include "exec/memattrs.h"
28 #include "exec/tlb-common.h"
29 #include "qapi/qapi-types-run-state.h"
30 #include "qemu/bitmap.h"
31 #include "qemu/rcu_queue.h"
32 #include "qemu/queue.h"
33 #include "qemu/thread.h"
34 #include "qemu/plugin-event.h"
35 #include "qom/object.h"
37 typedef int (*WriteCoreDumpFunction
)(const void *buf
, size_t size
,
42 * @section_id: QEMU-cpu
44 * @short_description: Base class for all CPUs
47 #define TYPE_CPU "cpu"
49 /* Since this macro is used a lot in hot code paths and in conjunction with
50 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
53 #define CPU(obj) ((CPUState *)(obj))
56 * The class checkers bring in CPU_GET_CLASS() which is potentially
57 * expensive given the eventual call to
58 * object_class_dynamic_cast_assert(). Because of this the CPUState
59 * has a cached value for the class in cs->cc which is set up in
60 * cpu_exec_realizefn() for use in hot code paths.
62 typedef struct CPUClass CPUClass
;
63 DECLARE_CLASS_CHECKERS(CPUClass
, CPU
,
67 * OBJECT_DECLARE_CPU_TYPE:
68 * @CpuInstanceType: instance struct name
69 * @CpuClassType: class struct name
70 * @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators
72 * This macro is typically used in "cpu-qom.h" header file, and will:
74 * - create the typedefs for the CPU object and class structs
75 * - register the type for use with g_autoptr
76 * - provide three standard type cast functions
78 * The object struct and class struct need to be declared manually.
80 #define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \
81 typedef struct ArchCPU CpuInstanceType; \
82 OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
84 typedef enum MMUAccessType
{
88 #define MMU_ACCESS_COUNT 3
91 typedef struct CPUWatchpoint CPUWatchpoint
;
93 /* see tcg-cpu-ops.h */
99 /* see sysemu-cpu-ops.h */
104 * @class_by_name: Callback to map -cpu command line model name to an
105 * instantiatable CPU type.
106 * @parse_features: Callback to parse command line arguments.
107 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
108 * @has_work: Callback for checking if there is work to do.
109 * @memory_rw_debug: Callback for GDB memory access.
110 * @dump_state: Callback for dumping state.
112 * Fill in target specific information for the "query-cpus-fast"
114 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
115 * @set_pc: Callback for setting the Program Counter register. This
116 * should have the semantics used by the target architecture when
117 * setting the PC from a source such as an ELF file entry point;
118 * for example on Arm it will also set the Thumb mode bit based
119 * on the least significant bit of the new PC value.
120 * If the target behaviour here is anything other than "set
121 * the PC register to the value passed in" then the target must
122 * also implement the synchronize_from_tb hook.
123 * @get_pc: Callback for getting the Program Counter register.
124 * As above, with the semantics of the target architecture.
125 * @gdb_read_register: Callback for letting GDB read a register.
126 * @gdb_write_register: Callback for letting GDB write a register.
127 * @gdb_adjust_breakpoint: Callback for adjusting the address of a
128 * breakpoint. Used by AVR to handle a gdb mis-feature with
129 * its Harvard architecture split code and data.
130 * @gdb_num_core_regs: Number of core registers accessible to GDB.
131 * @gdb_core_xml_file: File name for core registers GDB XML description.
132 * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
133 * before the insn which triggers a watchpoint rather than after it.
134 * @gdb_arch_name: Optional callback that returns the architecture name known
135 * to GDB. The caller must free the returned string with g_free.
136 * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the
137 * gdb stub. Returns a pointer to the XML contents for the specified XML file
138 * or NULL if the CPU doesn't have a dynamically generated content for it.
139 * @disas_set_info: Setup architecture specific components of disassembly info
140 * @adjust_watchpoint_address: Perform a target-specific adjustment to an
141 * address before attempting to match it against watchpoints.
142 * @deprecation_note: If this CPUClass is deprecated, this field provides
143 * related information.
145 * Represents a CPU family or model.
149 DeviceClass parent_class
;
152 ObjectClass
*(*class_by_name
)(const char *cpu_model
);
153 void (*parse_features
)(const char *typename
, char *str
, Error
**errp
);
155 bool (*has_work
)(CPUState
*cpu
);
156 int (*memory_rw_debug
)(CPUState
*cpu
, vaddr addr
,
157 uint8_t *buf
, int len
, bool is_write
);
158 void (*dump_state
)(CPUState
*cpu
, FILE *, int flags
);
159 void (*query_cpu_fast
)(CPUState
*cpu
, CpuInfoFast
*value
);
160 int64_t (*get_arch_id
)(CPUState
*cpu
);
161 void (*set_pc
)(CPUState
*cpu
, vaddr value
);
162 vaddr (*get_pc
)(CPUState
*cpu
);
163 int (*gdb_read_register
)(CPUState
*cpu
, GByteArray
*buf
, int reg
);
164 int (*gdb_write_register
)(CPUState
*cpu
, uint8_t *buf
, int reg
);
165 vaddr (*gdb_adjust_breakpoint
)(CPUState
*cpu
, vaddr addr
);
167 const char *gdb_core_xml_file
;
168 const gchar
* (*gdb_arch_name
)(CPUState
*cpu
);
169 const char * (*gdb_get_dynamic_xml
)(CPUState
*cpu
, const char *xmlname
);
171 void (*disas_set_info
)(CPUState
*cpu
, disassemble_info
*info
);
173 const char *deprecation_note
;
174 struct AccelCPUClass
*accel_cpu
;
176 /* when system emulation is not available, this pointer is NULL */
177 const struct SysemuCPUOps
*sysemu_ops
;
179 /* when TCG is not available, this pointer is NULL */
180 const struct TCGCPUOps
*tcg_ops
;
183 * if not NULL, this is called in order for the CPUClass to initialize
184 * class data that depends on the accelerator, see accel/accel-common.c.
186 void (*init_accel_cpu
)(struct AccelCPUClass
*accel_cpu
, CPUClass
*cc
);
189 * Keep non-pointer data at the end to minimize holes.
191 int reset_dump_flags
;
192 int gdb_num_core_regs
;
193 bool gdb_stop_before_watchpoint
;
197 * Fix the number of mmu modes to 16, which is also the maximum
198 * supported by the softmmu tlb api.
200 #define NB_MMU_MODES 16
202 /* Use a fully associative victim tlb of 8 entries. */
203 #define CPU_VTLB_SIZE 8
206 * The full TLB entry, which is not accessed by generated TCG code,
207 * so the layout is not as critical as that of CPUTLBEntry. This is
208 * also why we don't want to combine the two structs.
210 typedef struct CPUTLBEntryFull
{
212 * @xlat_section contains:
213 * - in the lower TARGET_PAGE_BITS, a physical section number
214 * - with the lower TARGET_PAGE_BITS masked off, an offset which
215 * must be added to the virtual address to obtain:
216 * + the ram_addr_t of the target RAM (if the physical section
217 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
218 * + the offset within the target MemoryRegion (otherwise)
223 * @phys_addr contains the physical address in the address space
224 * given by cpu_asidx_from_attrs(cpu, @attrs).
228 /* @attrs contains the memory transaction attributes for the page. */
231 /* @prot contains the complete protections for the page. */
234 /* @lg_page_size contains the log2 of the page size. */
235 uint8_t lg_page_size
;
238 * Additional tlb flags for use by the slow path. If non-zero,
239 * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW.
241 uint8_t slow_flags
[MMU_ACCESS_COUNT
];
244 * Allow target-specific additions to this structure.
245 * This may be used to cache items from the guest cpu
246 * page tables for later use by the implementation.
250 * Cache the attrs and shareability fields from the page table entry.
252 * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2].
253 * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format.
254 * For shareability and guarded, as in the SH and GP fields respectively
255 * of the VMSAv8-64 PTEs.
259 uint8_t shareability
;
266 * Data elements that are per MMU mode, minus the bits accessed by
269 typedef struct CPUTLBDesc
{
271 * Describe a region covering all of the large pages allocated
272 * into the tlb. When any page within this region is flushed,
273 * we must flush the entire tlb. The region is matched if
274 * (addr & large_page_mask) == large_page_addr.
276 vaddr large_page_addr
;
277 vaddr large_page_mask
;
278 /* host time (in ns) at the beginning of the time window */
279 int64_t window_begin_ns
;
280 /* maximum number of entries observed in the window */
281 size_t window_max_entries
;
282 size_t n_used_entries
;
283 /* The next index to use in the tlb victim table. */
285 /* The tlb victim table, in two parts. */
286 CPUTLBEntry vtable
[CPU_VTLB_SIZE
];
287 CPUTLBEntryFull vfulltlb
[CPU_VTLB_SIZE
];
288 CPUTLBEntryFull
*fulltlb
;
292 * Data elements that are shared between all MMU modes.
294 typedef struct CPUTLBCommon
{
295 /* Serialize updates to f.table and d.vtable, and others as noted. */
298 * Within dirty, for each bit N, modifications have been made to
299 * mmu_idx N since the last time that mmu_idx was flushed.
300 * Protected by tlb_c.lock.
304 * Statistics. These are not lock protected, but are read and
305 * written atomically. This allows the monitor to print a snapshot
306 * of the stats without interfering with the cpu.
308 size_t full_flush_count
;
309 size_t part_flush_count
;
310 size_t elide_flush_count
;
314 * The entire softmmu tlb, for all MMU modes.
315 * The meaning of each of the MMU modes is defined in the target code.
316 * Since this is placed within CPUNegativeOffsetState, the smallest
317 * negative offsets are at the end of the struct.
319 typedef struct CPUTLB
{
322 CPUTLBDesc d
[NB_MMU_MODES
];
323 CPUTLBDescFast f
[NB_MMU_MODES
];
328 * Low 16 bits: number of cycles left, used only in icount mode.
329 * High 16 bits: Set to -1 to force TCG to stop executing linked TBs
330 * for this CPU and return to its top level loop (even in non-icount mode).
331 * This allows a single read-compare-cbranch-write sequence to test
332 * for both decrementer underflow and exceptions.
334 typedef union IcountDecr
{
348 * Elements of CPUState most efficiently accessed from CPUArchState,
349 * via small negative offsets.
351 typedef struct CPUNegativeOffsetState
{
353 IcountDecr icount_decr
;
355 } CPUNegativeOffsetState
;
357 typedef struct CPUBreakpoint
{
359 int flags
; /* BP_* */
360 QTAILQ_ENTRY(CPUBreakpoint
) entry
;
363 struct CPUWatchpoint
{
368 int flags
; /* BP_* */
369 QTAILQ_ENTRY(CPUWatchpoint
) entry
;
377 /* The union type allows passing of 64 bit target pointers on 32 bit
378 * hosts in a single parameter
382 unsigned long host_ulong
;
387 #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)})
388 #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)})
389 #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)})
390 #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)})
391 #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL)
393 typedef void (*run_on_cpu_func
)(CPUState
*cpu
, run_on_cpu_data data
);
395 struct qemu_work_item
;
397 #define CPU_UNSET_NUMA_NODE_ID -1
401 * @cpu_index: CPU index (informative).
402 * @cluster_index: Identifies which cluster this CPU is in.
403 * For boards which don't define clusters or for "loose" CPUs not assigned
404 * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will
405 * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER
407 * Under TCG this value is propagated to @tcg_cflags.
408 * See TranslationBlock::TCG CF_CLUSTER_MASK.
409 * @tcg_cflags: Pre-computed cflags for this cpu.
410 * @nr_cores: Number of cores within this CPU package.
411 * @nr_threads: Number of threads within this CPU core.
412 * @running: #true if CPU is currently running (lockless).
413 * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
414 * valid under cpu_list_lock.
415 * @created: Indicates whether the CPU thread has been successfully created.
416 * @interrupt_request: Indicates a pending interrupt request.
417 * @halted: Nonzero if the CPU is in suspended state.
418 * @stop: Indicates a pending stop request.
419 * @stopped: Indicates the CPU has been artificially stopped.
420 * @unplug: Indicates a pending CPU unplug request.
421 * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
422 * @singlestep_enabled: Flags for single-stepping.
423 * @icount_extra: Instructions until next timer event.
424 * @neg.can_do_io: True if memory-mapped IO is allowed.
425 * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
426 * AddressSpaces this CPU has)
427 * @num_ases: number of CPUAddressSpaces in @cpu_ases
428 * @as: Pointer to the first AddressSpace, for the convenience of targets which
429 * only have a single AddressSpace
430 * @gdb_regs: Additional GDB registers.
431 * @gdb_num_regs: Number of total registers accessible to GDB.
432 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
433 * @next_cpu: Next CPU sharing TB cache.
434 * @opaque: User data.
435 * @mem_io_pc: Host Program Counter at which the memory was accessed.
436 * @accel: Pointer to accelerator specific state.
437 * @kvm_fd: vCPU file descriptor for KVM.
438 * @work_mutex: Lock to prevent multiple access to @work_list.
439 * @work_list: List of pending asynchronous work.
440 * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes
442 * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask).
443 * @plugin_mask: Plugin event bitmap. Modified only via async work.
444 * @ignore_memory_transaction_failures: Cached copy of the MachineState
445 * flag of the same name: allows the board to suppress calling of the
446 * CPU do_transaction_failed hook function.
447 * @kvm_dirty_gfns: Points to the KVM dirty ring for this CPU when KVM dirty
449 * @kvm_fetch_index: Keeps the index that we last fetched from the per-vCPU
450 * dirty ring structure.
452 * State of one CPU core or thread.
454 * Align, in order to match possible alignment required by CPUArchState,
455 * and eliminate a hole between CPUState and CPUArchState within ArchCPU.
459 DeviceState parent_obj
;
460 /* cache to avoid expensive CPU_GET_CLASS */
467 struct QemuThread
*thread
;
472 bool running
, has_waiter
;
473 struct QemuCond
*halt_cond
;
478 /* Endianness, false = little endian, true = big endian. */
481 /* Should CPU start in powered-off state? */
482 bool start_powered_off
;
487 int exclusive_context_count
;
488 uint32_t cflags_next_tb
;
489 /* updates protected by BQL */
490 uint32_t interrupt_request
;
491 int singlestep_enabled
;
492 int64_t icount_budget
;
493 int64_t icount_extra
;
494 uint64_t random_seed
;
497 QemuMutex work_mutex
;
498 QSIMPLEQ_HEAD(, qemu_work_item
) work_list
;
500 CPUAddressSpace
*cpu_ases
;
503 MemoryRegion
*memory
;
505 CPUJumpCache
*tb_jmp_cache
;
510 QTAILQ_ENTRY(CPUState
) node
;
512 /* ice debug support */
513 QTAILQ_HEAD(, CPUBreakpoint
) breakpoints
;
515 QTAILQ_HEAD(, CPUWatchpoint
) watchpoints
;
516 CPUWatchpoint
*watchpoint_hit
;
520 /* In order to avoid passing too many arguments to the MMIO helpers,
521 * we store some rarely used information in the CPU context.
525 /* Only used in KVM */
527 struct KVMState
*kvm_state
;
528 struct kvm_run
*kvm_run
;
529 struct kvm_dirty_gfn
*kvm_dirty_gfns
;
530 uint32_t kvm_fetch_index
;
531 uint64_t dirty_pages
;
532 int kvm_vcpu_stats_fd
;
534 /* Use by accel-block: CPU is executing an ioctl() */
535 QemuLockCnt in_ioctl_lock
;
537 DECLARE_BITMAP(plugin_mask
, QEMU_PLUGIN_EV_MAX
);
540 GArray
*plugin_mem_cbs
;
543 /* TODO Move common fields from CPUArchState here. */
548 int32_t exception_index
;
550 AccelCPUState
*accel
;
551 /* shared by kvm and hvf */
554 /* Used to keep track of an outstanding cpu throttle thread for migration
557 bool throttle_thread_scheduled
;
560 * Sleep throttle_us_per_full microseconds once dirty ring is full
561 * if dirty page rate limit is enabled.
563 int64_t throttle_us_per_full
;
565 bool ignore_memory_transaction_failures
;
567 /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */
568 bool prctl_unalign_sigbus
;
570 /* track IOMMUs whose translations we've cached in the TCG TLB */
571 GArray
*iommu_notifiers
;
574 * MUST BE LAST in order to minimize the displacement to CPUArchState.
576 char neg_align
[-sizeof(CPUNegativeOffsetState
) % 16] QEMU_ALIGNED(16);
577 CPUNegativeOffsetState neg
;
580 /* Validate placement of CPUNegativeOffsetState. */
581 QEMU_BUILD_BUG_ON(offsetof(CPUState
, neg
) !=
582 sizeof(CPUState
) - sizeof(CPUNegativeOffsetState
));
584 static inline CPUArchState
*cpu_env(CPUState
*cpu
)
586 /* We validate that CPUArchState follows CPUState in cpu-all.h. */
587 return (CPUArchState
*)(cpu
+ 1);
590 typedef QTAILQ_HEAD(CPUTailQ
, CPUState
) CPUTailQ
;
591 extern CPUTailQ cpus_queue
;
593 #define first_cpu QTAILQ_FIRST_RCU(&cpus_queue)
594 #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node)
595 #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus_queue, node)
596 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
597 QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus_queue, node, next_cpu)
599 extern __thread CPUState
*current_cpu
;
602 * qemu_tcg_mttcg_enabled:
603 * Check whether we are running MultiThread TCG or not.
605 * Returns: %true if we are in MTTCG mode %false otherwise.
607 extern bool mttcg_enabled
;
608 #define qemu_tcg_mttcg_enabled() (mttcg_enabled)
611 * cpu_paging_enabled:
612 * @cpu: The CPU whose state is to be inspected.
614 * Returns: %true if paging is enabled, %false otherwise.
616 bool cpu_paging_enabled(const CPUState
*cpu
);
619 * cpu_get_memory_mapping:
620 * @cpu: The CPU whose memory mappings are to be obtained.
621 * @list: Where to write the memory mappings to.
622 * @errp: Pointer for reporting an #Error.
624 * Returns: %true on success, %false otherwise.
626 bool cpu_get_memory_mapping(CPUState
*cpu
, MemoryMappingList
*list
,
629 #if !defined(CONFIG_USER_ONLY)
632 * cpu_write_elf64_note:
633 * @f: pointer to a function that writes memory to a file
634 * @cpu: The CPU whose memory is to be dumped
635 * @cpuid: ID number of the CPU
636 * @opaque: pointer to the CPUState struct
638 int cpu_write_elf64_note(WriteCoreDumpFunction f
, CPUState
*cpu
,
639 int cpuid
, void *opaque
);
642 * cpu_write_elf64_qemunote:
643 * @f: pointer to a function that writes memory to a file
644 * @cpu: The CPU whose memory is to be dumped
645 * @cpuid: ID number of the CPU
646 * @opaque: pointer to the CPUState struct
648 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f
, CPUState
*cpu
,
652 * cpu_write_elf32_note:
653 * @f: pointer to a function that writes memory to a file
654 * @cpu: The CPU whose memory is to be dumped
655 * @cpuid: ID number of the CPU
656 * @opaque: pointer to the CPUState struct
658 int cpu_write_elf32_note(WriteCoreDumpFunction f
, CPUState
*cpu
,
659 int cpuid
, void *opaque
);
662 * cpu_write_elf32_qemunote:
663 * @f: pointer to a function that writes memory to a file
664 * @cpu: The CPU whose memory is to be dumped
665 * @cpuid: ID number of the CPU
666 * @opaque: pointer to the CPUState struct
668 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f
, CPUState
*cpu
,
672 * cpu_get_crash_info:
673 * @cpu: The CPU to get crash information for
675 * Gets the previously saved crash information.
676 * Caller is responsible for freeing the data.
678 GuestPanicInformation
*cpu_get_crash_info(CPUState
*cpu
);
680 #endif /* !CONFIG_USER_ONLY */
685 * @CPU_DUMP_FPU: dump FPU register state, not just integer
686 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
687 * @CPU_DUMP_VPU: dump VPU registers
690 CPU_DUMP_CODE
= 0x00010000,
691 CPU_DUMP_FPU
= 0x00020000,
692 CPU_DUMP_CCOP
= 0x00040000,
693 CPU_DUMP_VPU
= 0x00080000,
698 * @cpu: The CPU whose state is to be dumped.
699 * @f: If non-null, dump to this stream, else to current print sink.
703 void cpu_dump_state(CPUState
*cpu
, FILE *f
, int flags
);
705 #ifndef CONFIG_USER_ONLY
707 * cpu_get_phys_page_attrs_debug:
708 * @cpu: The CPU to obtain the physical page address for.
709 * @addr: The virtual address.
710 * @attrs: Updated on return with the memory transaction attributes to use
713 * Obtains the physical page corresponding to a virtual one, together
714 * with the corresponding memory transaction attributes to use for the access.
715 * Use it only for debugging because no protection checks are done.
717 * Returns: Corresponding physical page address or -1 if no page found.
719 hwaddr
cpu_get_phys_page_attrs_debug(CPUState
*cpu
, vaddr addr
,
723 * cpu_get_phys_page_debug:
724 * @cpu: The CPU to obtain the physical page address for.
725 * @addr: The virtual address.
727 * Obtains the physical page corresponding to a virtual one.
728 * Use it only for debugging because no protection checks are done.
730 * Returns: Corresponding physical page address or -1 if no page found.
732 hwaddr
cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
734 /** cpu_asidx_from_attrs:
736 * @attrs: memory transaction attributes
738 * Returns the address space index specifying the CPU AddressSpace
739 * to use for a memory access with the given transaction attributes.
741 int cpu_asidx_from_attrs(CPUState
*cpu
, MemTxAttrs attrs
);
744 * cpu_virtio_is_big_endian:
747 * Returns %true if a CPU which supports runtime configurable endianness
748 * is currently big-endian.
750 bool cpu_virtio_is_big_endian(CPUState
*cpu
);
752 #endif /* CONFIG_USER_ONLY */
756 * @cpu: The CPU to be added to the list of CPUs.
758 void cpu_list_add(CPUState
*cpu
);
762 * @cpu: The CPU to be removed from the list of CPUs.
764 void cpu_list_remove(CPUState
*cpu
);
768 * @cpu: The CPU whose state is to be reset.
770 void cpu_reset(CPUState
*cpu
);
774 * @typename: The CPU base type.
775 * @cpu_model: The model string without any parameters.
777 * Looks up a concrete CPU #ObjectClass matching name @cpu_model.
779 * Returns: A concrete #CPUClass or %NULL if no matching class is found
780 * or if the matching class is abstract.
782 ObjectClass
*cpu_class_by_name(const char *typename
, const char *cpu_model
);
786 * @typename: The CPU type.
788 * Instantiates a CPU and realizes the CPU.
790 * Returns: A #CPUState or %NULL if an error occurred.
792 CPUState
*cpu_create(const char *typename
);
796 * @cpu_option: The -cpu option including optional parameters.
798 * processes optional parameters and registers them as global properties
800 * Returns: type of CPU to create or prints error and terminates process
801 * if an error occurred.
803 const char *parse_cpu_option(const char *cpu_option
);
807 * @cpu: The vCPU to check.
809 * Checks whether the CPU has work to do.
811 * Returns: %true if the CPU has work, %false otherwise.
813 static inline bool cpu_has_work(CPUState
*cpu
)
815 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
817 g_assert(cc
->has_work
);
818 return cc
->has_work(cpu
);
823 * @cpu: The vCPU to check against.
825 * Checks whether the caller is executing on the vCPU thread.
827 * Returns: %true if called from @cpu's thread, %false otherwise.
829 bool qemu_cpu_is_self(CPUState
*cpu
);
833 * @cpu: The vCPU to kick.
835 * Kicks @cpu's thread.
837 void qemu_cpu_kick(CPUState
*cpu
);
841 * @cpu: The CPU to check.
843 * Checks whether the CPU is stopped.
845 * Returns: %true if run state is not running or if artificially stopped;
848 bool cpu_is_stopped(CPUState
*cpu
);
852 * @cpu: The vCPU to run on.
853 * @func: The function to be executed.
854 * @data: Data to pass to the function.
855 * @mutex: Mutex to release while waiting for @func to run.
857 * Used internally in the implementation of run_on_cpu.
859 void do_run_on_cpu(CPUState
*cpu
, run_on_cpu_func func
, run_on_cpu_data data
,
864 * @cpu: The vCPU to run on.
865 * @func: The function to be executed.
866 * @data: Data to pass to the function.
868 * Schedules the function @func for execution on the vCPU @cpu.
870 void run_on_cpu(CPUState
*cpu
, run_on_cpu_func func
, run_on_cpu_data data
);
874 * @cpu: The vCPU to run on.
875 * @func: The function to be executed.
876 * @data: Data to pass to the function.
878 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
880 void async_run_on_cpu(CPUState
*cpu
, run_on_cpu_func func
, run_on_cpu_data data
);
883 * async_safe_run_on_cpu:
884 * @cpu: The vCPU to run on.
885 * @func: The function to be executed.
886 * @data: Data to pass to the function.
888 * Schedules the function @func for execution on the vCPU @cpu asynchronously,
889 * while all other vCPUs are sleeping.
891 * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the
894 void async_safe_run_on_cpu(CPUState
*cpu
, run_on_cpu_func func
, run_on_cpu_data data
);
897 * cpu_in_exclusive_context()
898 * @cpu: The vCPU to check
900 * Returns true if @cpu is an exclusive context, for example running
901 * something which has previously been queued via async_safe_run_on_cpu().
903 static inline bool cpu_in_exclusive_context(const CPUState
*cpu
)
905 return cpu
->exclusive_context_count
;
910 * @index: The CPUState@cpu_index value of the CPU to obtain.
912 * Gets a CPU matching @index.
914 * Returns: The CPU or %NULL if there is no matching CPU.
916 CPUState
*qemu_get_cpu(int index
);
920 * @id: Guest-exposed CPU ID to lookup.
922 * Search for CPU with specified ID.
924 * Returns: %true - CPU is found, %false - CPU isn't found.
926 bool cpu_exists(int64_t id
);
930 * @id: Guest-exposed CPU ID of the CPU to obtain.
932 * Get a CPU with matching @id.
934 * Returns: The CPU or %NULL if there is no matching CPU.
936 CPUState
*cpu_by_arch_id(int64_t id
);
940 * @cpu: The CPU to set an interrupt on.
941 * @mask: The interrupts to set.
943 * Invokes the interrupt handler.
946 void cpu_interrupt(CPUState
*cpu
, int mask
);
950 * @cpu: The CPU to set the program counter for.
951 * @addr: Program counter value.
953 * Sets the program counter for a CPU.
955 static inline void cpu_set_pc(CPUState
*cpu
, vaddr addr
)
957 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
959 cc
->set_pc(cpu
, addr
);
963 * cpu_reset_interrupt:
964 * @cpu: The CPU to clear the interrupt on.
965 * @mask: The interrupt mask to clear.
967 * Resets interrupts on the vCPU @cpu.
969 void cpu_reset_interrupt(CPUState
*cpu
, int mask
);
973 * @cpu: The CPU to exit.
975 * Requests the CPU @cpu to exit execution.
977 void cpu_exit(CPUState
*cpu
);
981 * @cpu: The CPU to resume.
983 * Resumes CPU, i.e. puts CPU into runnable state.
985 void cpu_resume(CPUState
*cpu
);
989 * @cpu: The CPU to remove.
991 * Requests the CPU to be removed and waits till it is removed.
993 void cpu_remove_sync(CPUState
*cpu
);
996 * process_queued_cpu_work() - process all items on CPU work queue
997 * @cpu: The CPU which work queue to process.
999 void process_queued_cpu_work(CPUState
*cpu
);
1003 * @cpu: The CPU for the current thread.
1005 * Record that a CPU has started execution and can be interrupted with
1008 void cpu_exec_start(CPUState
*cpu
);
1012 * @cpu: The CPU for the current thread.
1014 * Record that a CPU has stopped execution and exclusive sections
1015 * can be executed without interrupting it.
1017 void cpu_exec_end(CPUState
*cpu
);
1022 * Wait for a concurrent exclusive section to end, and then start
1023 * a section of work that is run while other CPUs are not running
1024 * between cpu_exec_start and cpu_exec_end. CPUs that are running
1025 * cpu_exec are exited immediately. CPUs that call cpu_exec_start
1026 * during the exclusive section go to sleep until this CPU calls
1029 void start_exclusive(void);
1034 * Concludes an exclusive execution section started by start_exclusive.
1036 void end_exclusive(void);
1040 * @cpu: The vCPU to initialize.
1042 * Initializes a vCPU.
1044 void qemu_init_vcpu(CPUState
*cpu
);
1046 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
1047 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
1048 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
1052 * @cpu: CPU to the flags for.
1053 * @enabled: Flags to enable.
1055 * Enables or disables single-stepping for @cpu.
1057 void cpu_single_step(CPUState
*cpu
, int enabled
);
1059 /* Breakpoint/watchpoint flags */
1060 #define BP_MEM_READ 0x01
1061 #define BP_MEM_WRITE 0x02
1062 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
1063 #define BP_STOP_BEFORE_ACCESS 0x04
1064 /* 0x08 currently unused */
1067 #define BP_ANY (BP_GDB | BP_CPU)
1068 #define BP_HIT_SHIFT 6
1069 #define BP_WATCHPOINT_HIT_READ (BP_MEM_READ << BP_HIT_SHIFT)
1070 #define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT)
1071 #define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT)
1073 int cpu_breakpoint_insert(CPUState
*cpu
, vaddr pc
, int flags
,
1074 CPUBreakpoint
**breakpoint
);
1075 int cpu_breakpoint_remove(CPUState
*cpu
, vaddr pc
, int flags
);
1076 void cpu_breakpoint_remove_by_ref(CPUState
*cpu
, CPUBreakpoint
*breakpoint
);
1077 void cpu_breakpoint_remove_all(CPUState
*cpu
, int mask
);
1079 /* Return true if PC matches an installed breakpoint. */
1080 static inline bool cpu_breakpoint_test(CPUState
*cpu
, vaddr pc
, int mask
)
1084 if (unlikely(!QTAILQ_EMPTY(&cpu
->breakpoints
))) {
1085 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
1086 if (bp
->pc
== pc
&& (bp
->flags
& mask
)) {
1094 #if defined(CONFIG_USER_ONLY)
1095 static inline int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1096 int flags
, CPUWatchpoint
**watchpoint
)
1101 static inline int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
,
1102 vaddr len
, int flags
)
1107 static inline void cpu_watchpoint_remove_by_ref(CPUState
*cpu
,
1112 static inline void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1116 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1117 int flags
, CPUWatchpoint
**watchpoint
);
1118 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
,
1119 vaddr len
, int flags
);
1120 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
);
1121 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
);
1125 * cpu_plugin_mem_cbs_enabled() - are plugin memory callbacks enabled?
1126 * @cs: CPUState pointer
1128 * The memory callbacks are installed if a plugin has instrumented an
1129 * instruction for memory. This can be useful to know if you want to
1130 * force a slow path for a series of memory accesses.
1132 static inline bool cpu_plugin_mem_cbs_enabled(const CPUState
*cpu
)
1134 #ifdef CONFIG_PLUGIN
1135 return !!cpu
->plugin_mem_cbs
;
1142 * cpu_get_address_space:
1143 * @cpu: CPU to get address space from
1144 * @asidx: index identifying which address space to get
1146 * Return the requested address space of this CPU. @asidx
1147 * specifies which address space to read.
1149 AddressSpace
*cpu_get_address_space(CPUState
*cpu
, int asidx
);
1151 G_NORETURN
void cpu_abort(CPUState
*cpu
, const char *fmt
, ...)
1152 G_GNUC_PRINTF(2, 3);
1154 /* $(top_srcdir)/cpu.c */
1155 void cpu_class_init_props(DeviceClass
*dc
);
1156 void cpu_exec_initfn(CPUState
*cpu
);
1157 bool cpu_exec_realizefn(CPUState
*cpu
, Error
**errp
);
1158 void cpu_exec_unrealizefn(CPUState
*cpu
);
1159 void cpu_exec_reset_hold(CPUState
*cpu
);
1162 * target_words_bigendian:
1163 * Returns true if the (default) endianness of the target is big endian,
1164 * false otherwise. Note that in target-specific code, you can use
1165 * TARGET_BIG_ENDIAN directly instead. On the other hand, common
1166 * code should normally never need to know about the endianness of the
1167 * target, so please do *not* use this function unless you know very well
1168 * what you are doing!
1170 bool target_words_bigendian(void);
1172 const char *target_name(void);
1174 void page_size_init(void);
1178 #ifndef CONFIG_USER_ONLY
1180 extern const VMStateDescription vmstate_cpu_common
;
1182 #define VMSTATE_CPU() { \
1183 .name = "parent_obj", \
1184 .size = sizeof(CPUState), \
1185 .vmsd = &vmstate_cpu_common, \
1186 .flags = VMS_STRUCT, \
1189 #endif /* !CONFIG_USER_ONLY */
1191 #endif /* NEED_CPU_H */
1193 #define UNASSIGNED_CPU_INDEX -1
1194 #define UNASSIGNED_CLUSTER_INDEX -1