target-xtensa/op_helper.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "cpu.h"
  29 #include "exec/helper-proto.h"
  30 #include "qemu/host-utils.h"
  31 #include "exec/cpu_ldst.h"
  32 #include "exec/address-spaces.h"
  33 #include "qemu/timer.h"
  34
  35 void xtensa_cpu_do_unaligned_access(CPUState *cs,
  36         vaddr addr, int is_write, int is_user, uintptr_t retaddr)
  37 {
  38     XtensaCPU *cpu = XTENSA_CPU(cs);
  39     CPUXtensaState *env = &cpu->env;
  40
  41     if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
  42             !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
  43         cpu_restore_state(CPU(cpu), retaddr);
  44         HELPER(exception_cause_vaddr)(env,
  45                 env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
  46     }
  47 }
  48
  49 void tlb_fill(CPUState *cs,
  50               target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr)
  51 {
  52     XtensaCPU *cpu = XTENSA_CPU(cs);
  53     CPUXtensaState *env = &cpu->env;
  54     uint32_t paddr;
  55     uint32_t page_size;
  56     unsigned access;
  57     int ret = xtensa_get_physical_addr(env, true, vaddr, is_write, mmu_idx,
  58             &paddr, &page_size, &access);
  59
  60     qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__,
  61             vaddr, is_write, mmu_idx, paddr, ret);
  62
  63     if (ret == 0) {
  64         tlb_set_page(cs,
  65                      vaddr & TARGET_PAGE_MASK,
  66                      paddr & TARGET_PAGE_MASK,
  67                      access, mmu_idx, page_size);
  68     } else {
  69         cpu_restore_state(cs, retaddr);
  70         HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
  71     }
  72 }
  73
  74 static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
  75 {
  76     uint32_t paddr;
  77     uint32_t page_size;
  78     unsigned access;
  79     int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
  80             &paddr, &page_size, &access);
  81     if (ret == 0) {
  82         tb_invalidate_phys_addr(&address_space_memory, paddr);
  83     }
  84 }
  85
  86 void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
  87 {
  88     CPUState *cs = CPU(xtensa_env_get_cpu(env));
  89
  90     cs->exception_index = excp;
  91     if (excp == EXCP_DEBUG) {
  92         env->exception_taken = 0;
  93     }
  94     cpu_loop_exit(cs);
  95 }
  96
  97 void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
  98 {
  99     uint32_t vector;
 100
 101     env->pc = pc;
 102     if (env->sregs[PS] & PS_EXCM) {
 103         if (env->config->ndepc) {
 104             env->sregs[DEPC] = pc;
 105         } else {
 106             env->sregs[EPC1] = pc;
 107         }
 108         vector = EXC_DOUBLE;
 109     } else {
 110         env->sregs[EPC1] = pc;
 111         vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
 112     }
 113
 114     env->sregs[EXCCAUSE] = cause;
 115     env->sregs[PS] |= PS_EXCM;
 116
 117     HELPER(exception)(env, vector);
 118 }
 119
 120 void HELPER(exception_cause_vaddr)(CPUXtensaState *env,
 121         uint32_t pc, uint32_t cause, uint32_t vaddr)
 122 {
 123     env->sregs[EXCVADDR] = vaddr;
 124     HELPER(exception_cause)(env, pc, cause);
 125 }
 126
 127 void debug_exception_env(CPUXtensaState *env, uint32_t cause)
 128 {
 129     if (xtensa_get_cintlevel(env) < env->config->debug_level) {
 130         HELPER(debug_exception)(env, env->pc, cause);
 131     }
 132 }
 133
 134 void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
 135 {
 136     unsigned level = env->config->debug_level;
 137
 138     env->pc = pc;
 139     env->sregs[DEBUGCAUSE] = cause;
 140     env->sregs[EPC1 + level - 1] = pc;
 141     env->sregs[EPS2 + level - 2] = env->sregs[PS];
 142     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM |
 143         (level << PS_INTLEVEL_SHIFT);
 144     HELPER(exception)(env, EXC_DEBUG);
 145 }
 146
 147 uint32_t HELPER(nsa)(uint32_t v)
 148 {
 149     if (v & 0x80000000) {
 150         v = ~v;
 151     }
 152     return v ? clz32(v) - 1 : 31;
 153 }
 154
 155 uint32_t HELPER(nsau)(uint32_t v)
 156 {
 157     return v ? clz32(v) : 32;
 158 }
 159
 160 static void copy_window_from_phys(CPUXtensaState *env,
 161         uint32_t window, uint32_t phys, uint32_t n)
 162 {
 163     assert(phys < env->config->nareg);
 164     if (phys + n <= env->config->nareg) {
 165         memcpy(env->regs + window, env->phys_regs + phys,
 166                 n * sizeof(uint32_t));
 167     } else {
 168         uint32_t n1 = env->config->nareg - phys;
 169         memcpy(env->regs + window, env->phys_regs + phys,
 170                 n1 * sizeof(uint32_t));
 171         memcpy(env->regs + window + n1, env->phys_regs,
 172                 (n - n1) * sizeof(uint32_t));
 173     }
 174 }
 175
 176 static void copy_phys_from_window(CPUXtensaState *env,
 177         uint32_t phys, uint32_t window, uint32_t n)
 178 {
 179     assert(phys < env->config->nareg);
 180     if (phys + n <= env->config->nareg) {
 181         memcpy(env->phys_regs + phys, env->regs + window,
 182                 n * sizeof(uint32_t));
 183     } else {
 184         uint32_t n1 = env->config->nareg - phys;
 185         memcpy(env->phys_regs + phys, env->regs + window,
 186                 n1 * sizeof(uint32_t));
 187         memcpy(env->phys_regs, env->regs + window + n1,
 188                 (n - n1) * sizeof(uint32_t));
 189     }
 190 }
 191
 192
 193 static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env)
 194 {
 195     return a & (env->config->nareg / 4 - 1);
 196 }
 197
 198 static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env)
 199 {
 200     return 1 << windowbase_bound(a, env);
 201 }
 202
 203 void xtensa_sync_window_from_phys(CPUXtensaState *env)
 204 {
 205     copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
 206 }
 207
 208 void xtensa_sync_phys_from_window(CPUXtensaState *env)
 209 {
 210     copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
 211 }
 212
 213 static void rotate_window_abs(CPUXtensaState *env, uint32_t position)
 214 {
 215     xtensa_sync_phys_from_window(env);
 216     env->sregs[WINDOW_BASE] = windowbase_bound(position, env);
 217     xtensa_sync_window_from_phys(env);
 218 }
 219
 220 static void rotate_window(CPUXtensaState *env, uint32_t delta)
 221 {
 222     rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta);
 223 }
 224
 225 void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v)
 226 {
 227     rotate_window_abs(env, v);
 228 }
 229
 230 void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
 231 {
 232     int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
 233     if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 234         qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n",
 235                 pc, env->sregs[PS]);
 236         HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
 237     } else {
 238         uint32_t windowstart = xtensa_replicate_windowstart(env) >>
 239             (env->sregs[WINDOW_BASE] + 1);
 240
 241         if (windowstart & ((1 << callinc) - 1)) {
 242             HELPER(window_check)(env, pc, callinc);
 243         }
 244         env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
 245         rotate_window(env, callinc);
 246         env->sregs[WINDOW_START] |=
 247             windowstart_bit(env->sregs[WINDOW_BASE], env);
 248     }
 249 }
 250
 251 void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w)
 252 {
 253     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 254     uint32_t windowstart = env->sregs[WINDOW_START];
 255     uint32_t m, n;
 256
 257     if ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) {
 258         return;
 259     }
 260
 261     for (n = 1; ; ++n) {
 262         if (n > w) {
 263             return;
 264         }
 265         if (windowstart & windowstart_bit(windowbase + n, env)) {
 266             break;
 267         }
 268     }
 269
 270     m = windowbase_bound(windowbase + n, env);
 271     rotate_window(env, n);
 272     env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 273         (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 274     env->sregs[EPC1] = env->pc = pc;
 275
 276     if (windowstart & windowstart_bit(m + 1, env)) {
 277         HELPER(exception)(env, EXC_WINDOW_OVERFLOW4);
 278     } else if (windowstart & windowstart_bit(m + 2, env)) {
 279         HELPER(exception)(env, EXC_WINDOW_OVERFLOW8);
 280     } else {
 281         HELPER(exception)(env, EXC_WINDOW_OVERFLOW12);
 282     }
 283 }
 284
 285 uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
 286 {
 287     int n = (env->regs[0] >> 30) & 0x3;
 288     int m = 0;
 289     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 290     uint32_t windowstart = env->sregs[WINDOW_START];
 291     uint32_t ret_pc = 0;
 292
 293     if (windowstart & windowstart_bit(windowbase - 1, env)) {
 294         m = 1;
 295     } else if (windowstart & windowstart_bit(windowbase - 2, env)) {
 296         m = 2;
 297     } else if (windowstart & windowstart_bit(windowbase - 3, env)) {
 298         m = 3;
 299     }
 300
 301     if (n == 0 || (m != 0 && m != n) ||
 302             ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 303         qemu_log("Illegal retw instruction(pc = %08x), "
 304                 "PS = %08x, m = %d, n = %d\n",
 305                 pc, env->sregs[PS], m, n);
 306         HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
 307     } else {
 308         int owb = windowbase;
 309
 310         ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
 311
 312         rotate_window(env, -n);
 313         if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
 314             env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
 315         } else {
 316             /* window underflow */
 317             env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 318                 (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 319             env->sregs[EPC1] = env->pc = pc;
 320
 321             if (n == 1) {
 322                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4);
 323             } else if (n == 2) {
 324                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8);
 325             } else if (n == 3) {
 326                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12);
 327             }
 328         }
 329     }
 330     return ret_pc;
 331 }
 332
 333 void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4)
 334 {
 335     rotate_window(env, imm4);
 336 }
 337
 338 void HELPER(restore_owb)(CPUXtensaState *env)
 339 {
 340     rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT);
 341 }
 342
 343 void HELPER(movsp)(CPUXtensaState *env, uint32_t pc)
 344 {
 345     if ((env->sregs[WINDOW_START] &
 346             (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) |
 347              windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) |
 348              windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) {
 349         HELPER(exception_cause)(env, pc, ALLOCA_CAUSE);
 350     }
 351 }
 352
 353 void HELPER(wsr_lbeg)(CPUXtensaState *env, uint32_t v)
 354 {
 355     if (env->sregs[LBEG] != v) {
 356         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 357         env->sregs[LBEG] = v;
 358     }
 359 }
 360
 361 void HELPER(wsr_lend)(CPUXtensaState *env, uint32_t v)
 362 {
 363     if (env->sregs[LEND] != v) {
 364         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 365         env->sregs[LEND] = v;
 366         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 367     }
 368 }
 369
 370 void HELPER(dump_state)(CPUXtensaState *env)
 371 {
 372     XtensaCPU *cpu = xtensa_env_get_cpu(env);
 373
 374     cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
 375 }
 376
 377 void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
 378 {
 379     CPUState *cpu;
 380
 381     env->pc = pc;
 382     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
 383         (intlevel << PS_INTLEVEL_SHIFT);
 384     check_interrupts(env);
 385     if (env->pending_irq_level) {
 386         cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));
 387         return;
 388     }
 389
 390     cpu = CPU(xtensa_env_get_cpu(env));
 391     env->halt_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 392     cpu->halted = 1;
 393     if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
 394         xtensa_rearm_ccompare_timer(env);
 395     }
 396     HELPER(exception)(env, EXCP_HLT);
 397 }
 398
 399 void HELPER(timer_irq)(CPUXtensaState *env, uint32_t id, uint32_t active)
 400 {
 401     xtensa_timer_irq(env, id, active);
 402 }
 403
 404 void HELPER(advance_ccount)(CPUXtensaState *env, uint32_t d)
 405 {
 406     xtensa_advance_ccount(env, d);
 407 }
 408
 409 void HELPER(check_interrupts)(CPUXtensaState *env)
 410 {
 411     check_interrupts(env);
 412 }
 413
 414 void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr)
 415 {
 416     get_page_addr_code(env, vaddr);
 417 }
 418
 419 /*!
 420  * Check vaddr accessibility/cache attributes and raise an exception if
 421  * specified by the ATOMCTL SR.
 422  *
 423  * Note: local memory exclusion is not implemented
 424  */
 425 void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
 426 {
 427     uint32_t paddr, page_size, access;
 428     uint32_t atomctl = env->sregs[ATOMCTL];
 429     int rc = xtensa_get_physical_addr(env, true, vaddr, 1,
 430             xtensa_get_cring(env), &paddr, &page_size, &access);
 431
 432     /*
 433      * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions,
 434      * see opcode description in the ISA
 435      */
 436     if (rc == 0 &&
 437             (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) {
 438         rc = STORE_PROHIBITED_CAUSE;
 439     }
 440
 441     if (rc) {
 442         HELPER(exception_cause_vaddr)(env, pc, rc, vaddr);
 443     }
 444
 445     /*
 446      * When data cache is not configured use ATOMCTL bypass field.
 447      * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL)
 448      * under the Conditional Store Option.
 449      */
 450     if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
 451         access = PAGE_CACHE_BYPASS;
 452     }
 453
 454     switch (access & PAGE_CACHE_MASK) {
 455     case PAGE_CACHE_WB:
 456         atomctl >>= 2;
 457         /* fall through */
 458     case PAGE_CACHE_WT:
 459         atomctl >>= 2;
 460         /* fall through */
 461     case PAGE_CACHE_BYPASS:
 462         if ((atomctl & 0x3) == 0) {
 463             HELPER(exception_cause_vaddr)(env, pc,
 464                     LOAD_STORE_ERROR_CAUSE, vaddr);
 465         }
 466         break;
 467
 468     case PAGE_CACHE_ISOLATE:
 469         HELPER(exception_cause_vaddr)(env, pc,
 470                 LOAD_STORE_ERROR_CAUSE, vaddr);
 471         break;
 472
 473     default:
 474         break;
 475     }
 476 }
 477
 478 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
 479 {
 480     XtensaCPU *cpu = xtensa_env_get_cpu(env);
 481
 482     v = (v & 0xffffff00) | 0x1;
 483     if (v != env->sregs[RASID]) {
 484         env->sregs[RASID] = v;
 485         tlb_flush(CPU(cpu), 1);
 486     }
 487 }
 488
 489 static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way)
 490 {
 491     uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
 492
 493     switch (way) {
 494     case 4:
 495         return (tlbcfg >> 16) & 0x3;
 496
 497     case 5:
 498         return (tlbcfg >> 20) & 0x1;
 499
 500     case 6:
 501         return (tlbcfg >> 24) & 0x1;
 502
 503     default:
 504         return 0;
 505     }
 506 }
 507
 508 /*!
 509  * Get bit mask for the virtual address bits translated by the TLB way
 510  */
 511 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 512 {
 513     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 514         bool varway56 = dtlb ?
 515             env->config->dtlb.varway56 :
 516             env->config->itlb.varway56;
 517
 518         switch (way) {
 519         case 4:
 520             return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
 521
 522         case 5:
 523             if (varway56) {
 524                 return 0xf8000000 << get_page_size(env, dtlb, way);
 525             } else {
 526                 return 0xf8000000;
 527             }
 528
 529         case 6:
 530             if (varway56) {
 531                 return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
 532             } else {
 533                 return 0xf0000000;
 534             }
 535
 536         default:
 537             return 0xfffff000;
 538         }
 539     } else {
 540         return REGION_PAGE_MASK;
 541     }
 542 }
 543
 544 /*!
 545  * Get bit mask for the 'VPN without index' field.
 546  * See ISA, 4.6.5.6, data format for RxTLB0
 547  */
 548 static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 549 {
 550     if (way < 4) {
 551         bool is32 = (dtlb ?
 552                 env->config->dtlb.nrefillentries :
 553                 env->config->itlb.nrefillentries) == 32;
 554         return is32 ? 0xffff8000 : 0xffffc000;
 555     } else if (way == 4) {
 556         return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
 557     } else if (way <= 6) {
 558         uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
 559         bool varway56 = dtlb ?
 560             env->config->dtlb.varway56 :
 561             env->config->itlb.varway56;
 562
 563         if (varway56) {
 564             return mask << (way == 5 ? 2 : 3);
 565         } else {
 566             return mask << 1;
 567         }
 568     } else {
 569         return 0xfffff000;
 570     }
 571 }
 572
 573 /*!
 574  * Split virtual address into VPN (with index) and entry index
 575  * for the given TLB way
 576  */
 577 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
 578         uint32_t *vpn, uint32_t wi, uint32_t *ei)
 579 {
 580     bool varway56 = dtlb ?
 581         env->config->dtlb.varway56 :
 582         env->config->itlb.varway56;
 583
 584     if (!dtlb) {
 585         wi &= 7;
 586     }
 587
 588     if (wi < 4) {
 589         bool is32 = (dtlb ?
 590                 env->config->dtlb.nrefillentries :
 591                 env->config->itlb.nrefillentries) == 32;
 592         *ei = (v >> 12) & (is32 ? 0x7 : 0x3);
 593     } else {
 594         switch (wi) {
 595         case 4:
 596             {
 597                 uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
 598                 *ei = (v >> eibase) & 0x3;
 599             }
 600             break;
 601
 602         case 5:
 603             if (varway56) {
 604                 uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
 605                 *ei = (v >> eibase) & 0x3;
 606             } else {
 607                 *ei = (v >> 27) & 0x1;
 608             }
 609             break;
 610
 611         case 6:
 612             if (varway56) {
 613                 uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
 614                 *ei = (v >> eibase) & 0x7;
 615             } else {
 616                 *ei = (v >> 28) & 0x1;
 617             }
 618             break;
 619
 620         default:
 621             *ei = 0;
 622             break;
 623         }
 624     }
 625     *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 626 }
 627
 628 /*!
 629  * Split TLB address into TLB way, entry index and VPN (with index).
 630  * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
 631  */
 632 static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
 633         uint32_t *vpn, uint32_t *wi, uint32_t *ei)
 634 {
 635     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 636         *wi = v & (dtlb ? 0xf : 0x7);
 637         split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
 638     } else {
 639         *vpn = v & REGION_PAGE_MASK;
 640         *wi = 0;
 641         *ei = (v >> 29) & 0x7;
 642     }
 643 }
 644
 645 static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
 646         uint32_t v, bool dtlb, uint32_t *pwi)
 647 {
 648     uint32_t vpn;
 649     uint32_t wi;
 650     uint32_t ei;
 651
 652     split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
 653     if (pwi) {
 654         *pwi = wi;
 655     }
 656     return xtensa_tlb_get_entry(env, dtlb, wi, ei);
 657 }
 658
 659 uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 660 {
 661     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 662         uint32_t wi;
 663         const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
 664         return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
 665     } else {
 666         return v & REGION_PAGE_MASK;
 667     }
 668 }
 669
 670 uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 671 {
 672     const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
 673     return entry->paddr | entry->attr;
 674 }
 675
 676 void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 677 {
 678     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 679         uint32_t wi;
 680         xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
 681         if (entry->variable && entry->asid) {
 682             tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
 683             entry->asid = 0;
 684         }
 685     }
 686 }
 687
 688 uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 689 {
 690     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 691         uint32_t wi;
 692         uint32_t ei;
 693         uint8_t ring;
 694         int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
 695
 696         switch (res) {
 697         case 0:
 698             if (ring >= xtensa_get_ring(env)) {
 699                 return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
 700             }
 701             break;
 702
 703         case INST_TLB_MULTI_HIT_CAUSE:
 704         case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
 705             HELPER(exception_cause_vaddr)(env, env->pc, res, v);
 706             break;
 707         }
 708         return 0;
 709     } else {
 710         return (v & REGION_PAGE_MASK) | 0x1;
 711     }
 712 }
 713
 714 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
 715         xtensa_tlb_entry *entry, bool dtlb,
 716         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
 717 {
 718     entry->vaddr = vpn;
 719     entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 720     entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
 721     entry->attr = pte & 0xf;
 722 }
 723
 724 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
 725         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
 726 {
 727     XtensaCPU *cpu = xtensa_env_get_cpu(env);
 728     CPUState *cs = CPU(cpu);
 729     xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
 730
 731     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 732         if (entry->variable) {
 733             if (entry->asid) {
 734                 tlb_flush_page(cs, entry->vaddr);
 735             }
 736             xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
 737             tlb_flush_page(cs, entry->vaddr);
 738         } else {
 739             qemu_log("%s %d, %d, %d trying to set immutable entry\n",
 740                     __func__, dtlb, wi, ei);
 741         }
 742     } else {
 743         tlb_flush_page(cs, entry->vaddr);
 744         if (xtensa_option_enabled(env->config,
 745                     XTENSA_OPTION_REGION_TRANSLATION)) {
 746             entry->paddr = pte & REGION_PAGE_MASK;
 747         }
 748         entry->attr = pte & 0xf;
 749     }
 750 }
 751
 752 void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
 753 {
 754     uint32_t vpn;
 755     uint32_t wi;
 756     uint32_t ei;
 757     split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
 758     xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
 759 }
 760
 761
 762 void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
 763 {
 764     uint32_t change = v ^ env->sregs[IBREAKENABLE];
 765     unsigned i;
 766
 767     for (i = 0; i < env->config->nibreak; ++i) {
 768         if (change & (1 << i)) {
 769             tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 770         }
 771     }
 772     env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
 773 }
 774
 775 void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
 776 {
 777     if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
 778         tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 779         tb_invalidate_virtual_addr(env, v);
 780     }
 781     env->sregs[IBREAKA + i] = v;
 782 }
 783
 784 static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
 785         uint32_t dbreakc)
 786 {
 787     CPUState *cs = CPU(xtensa_env_get_cpu(env));
 788     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
 789     uint32_t mask = dbreakc | ~DBREAKC_MASK;
 790
 791     if (env->cpu_watchpoint[i]) {
 792         cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
 793     }
 794     if (dbreakc & DBREAKC_SB) {
 795         flags |= BP_MEM_WRITE;
 796     }
 797     if (dbreakc & DBREAKC_LB) {
 798         flags |= BP_MEM_READ;
 799     }
 800     /* contiguous mask after inversion is one less than some power of 2 */
 801     if ((~mask + 1) & ~mask) {
 802         qemu_log("DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
 803         /* cut mask after the first zero bit */
 804         mask = 0xffffffff << (32 - clo32(mask));
 805     }
 806     if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1,
 807             flags, &env->cpu_watchpoint[i])) {
 808         env->cpu_watchpoint[i] = NULL;
 809         qemu_log("Failed to set data breakpoint at 0x%08x/%d\n",
 810                 dbreaka & mask, ~mask + 1);
 811     }
 812 }
 813
 814 void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
 815 {
 816     uint32_t dbreakc = env->sregs[DBREAKC + i];
 817
 818     if ((dbreakc & DBREAKC_SB_LB) &&
 819             env->sregs[DBREAKA + i] != v) {
 820         set_dbreak(env, i, v, dbreakc);
 821     }
 822     env->sregs[DBREAKA + i] = v;
 823 }
 824
 825 void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
 826 {
 827     if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) {
 828         if (v & DBREAKC_SB_LB) {
 829             set_dbreak(env, i, env->sregs[DBREAKA + i], v);
 830         } else {
 831             if (env->cpu_watchpoint[i]) {
 832                 CPUState *cs = CPU(xtensa_env_get_cpu(env));
 833
 834                 cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
 835                 env->cpu_watchpoint[i] = NULL;
 836             }
 837         }
 838     }
 839     env->sregs[DBREAKC + i] = v;
 840 }
 841
 842 void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v)
 843 {
 844     static const int rounding_mode[] = {
 845         float_round_nearest_even,
 846         float_round_to_zero,
 847         float_round_up,
 848         float_round_down,
 849     };
 850
 851     env->uregs[FCR] = v & 0xfffff07f;
 852     set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status);
 853 }
 854
 855 float32 HELPER(abs_s)(float32 v)
 856 {
 857     return float32_abs(v);
 858 }
 859
 860 float32 HELPER(neg_s)(float32 v)
 861 {
 862     return float32_chs(v);
 863 }
 864
 865 float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
 866 {
 867     return float32_add(a, b, &env->fp_status);
 868 }
 869
 870 float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b)
 871 {
 872     return float32_sub(a, b, &env->fp_status);
 873 }
 874
 875 float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b)
 876 {
 877     return float32_mul(a, b, &env->fp_status);
 878 }
 879
 880 float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
 881 {
 882     return float32_muladd(b, c, a, 0,
 883             &env->fp_status);
 884 }
 885
 886 float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
 887 {
 888     return float32_muladd(b, c, a, float_muladd_negate_product,
 889             &env->fp_status);
 890 }
 891
 892 uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale)
 893 {
 894     float_status fp_status = {0};
 895
 896     set_float_rounding_mode(rounding_mode, &fp_status);
 897     return float32_to_int32(
 898             float32_scalbn(v, scale, &fp_status), &fp_status);
 899 }
 900
 901 uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale)
 902 {
 903     float_status fp_status = {0};
 904     float32 res;
 905
 906     set_float_rounding_mode(rounding_mode, &fp_status);
 907
 908     res = float32_scalbn(v, scale, &fp_status);
 909
 910     if (float32_is_neg(v) && !float32_is_any_nan(v)) {
 911         return float32_to_int32(res, &fp_status);
 912     } else {
 913         return float32_to_uint32(res, &fp_status);
 914     }
 915 }
 916
 917 float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
 918 {
 919     return float32_scalbn(int32_to_float32(v, &env->fp_status),
 920             (int32_t)scale, &env->fp_status);
 921 }
 922
 923 float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
 924 {
 925     return float32_scalbn(uint32_to_float32(v, &env->fp_status),
 926             (int32_t)scale, &env->fp_status);
 927 }
 928
 929 static inline void set_br(CPUXtensaState *env, bool v, uint32_t br)
 930 {
 931     if (v) {
 932         env->sregs[BR] |= br;
 933     } else {
 934         env->sregs[BR] &= ~br;
 935     }
 936 }
 937
 938 void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 939 {
 940     set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br);
 941 }
 942
 943 void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 944 {
 945     set_br(env, float32_eq_quiet(a, b, &env->fp_status), br);
 946 }
 947
 948 void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 949 {
 950     int v = float32_compare_quiet(a, b, &env->fp_status);
 951     set_br(env, v == float_relation_equal || v == float_relation_unordered, br);
 952 }
 953
 954 void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 955 {
 956     set_br(env, float32_lt_quiet(a, b, &env->fp_status), br);
 957 }
 958
 959 void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 960 {
 961     int v = float32_compare_quiet(a, b, &env->fp_status);
 962     set_br(env, v == float_relation_less || v == float_relation_unordered, br);
 963 }
 964
 965 void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 966 {
 967     set_br(env, float32_le_quiet(a, b, &env->fp_status), br);
 968 }
 969
 970 void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 971 {
 972     int v = float32_compare_quiet(a, b, &env->fp_status);
 973     set_br(env, v != float_relation_greater, br);
 974 }