target/riscv/cpu.c

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/qemu-print.h"
  22 #include "qemu/ctype.h"
  23 #include "qemu/log.h"
  24 #include "cpu.h"
  25 #include "internals.h"
  26 #include "exec/exec-all.h"
  27 #include "qapi/error.h"
  28 #include "qemu/error-report.h"
  29 #include "hw/qdev-properties.h"
  30 #include "migration/vmstate.h"
  31 #include "fpu/softfloat-helpers.h"
  32
  33 /* RISC-V CPU definitions */
  34
  35 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
  36
  37 const char * const riscv_int_regnames[] = {
  38   "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
  39   "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
  40   "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
  41   "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
  42   "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
  43 };
  44
  45 const char * const riscv_fpr_regnames[] = {
  46   "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
  47   "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
  48   "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
  49   "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
  50   "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
  51   "f30/ft10", "f31/ft11"
  52 };
  53
  54 static const char * const riscv_excp_names[] = {
  55     "misaligned_fetch",
  56     "fault_fetch",
  57     "illegal_instruction",
  58     "breakpoint",
  59     "misaligned_load",
  60     "fault_load",
  61     "misaligned_store",
  62     "fault_store",
  63     "user_ecall",
  64     "supervisor_ecall",
  65     "hypervisor_ecall",
  66     "machine_ecall",
  67     "exec_page_fault",
  68     "load_page_fault",
  69     "reserved",
  70     "store_page_fault",
  71     "reserved",
  72     "reserved",
  73     "reserved",
  74     "reserved",
  75     "guest_exec_page_fault",
  76     "guest_load_page_fault",
  77     "reserved",
  78     "guest_store_page_fault",
  79 };
  80
  81 static const char * const riscv_intr_names[] = {
  82     "u_software",
  83     "s_software",
  84     "vs_software",
  85     "m_software",
  86     "u_timer",
  87     "s_timer",
  88     "vs_timer",
  89     "m_timer",
  90     "u_external",
  91     "s_external",
  92     "vs_external",
  93     "m_external",
  94     "reserved",
  95     "reserved",
  96     "reserved",
  97     "reserved"
  98 };
  99
 100 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
 101 {
 102     if (async) {
 103         return (cause < ARRAY_SIZE(riscv_intr_names)) ?
 104                riscv_intr_names[cause] : "(unknown)";
 105     } else {
 106         return (cause < ARRAY_SIZE(riscv_excp_names)) ?
 107                riscv_excp_names[cause] : "(unknown)";
 108     }
 109 }
 110
 111 bool riscv_cpu_is_32bit(CPURISCVState *env)
 112 {
 113     if (env->misa & RV64) {
 114         return false;
 115     }
 116
 117     return true;
 118 }
 119
 120 static void set_misa(CPURISCVState *env, target_ulong misa)
 121 {
 122     env->misa_mask = env->misa = misa;
 123 }
 124
 125 static void set_priv_version(CPURISCVState *env, int priv_ver)
 126 {
 127     env->priv_ver = priv_ver;
 128 }
 129
 130 static void set_bext_version(CPURISCVState *env, int bext_ver)
 131 {
 132     env->bext_ver = bext_ver;
 133 }
 134
 135 static void set_vext_version(CPURISCVState *env, int vext_ver)
 136 {
 137     env->vext_ver = vext_ver;
 138 }
 139
 140 static void set_feature(CPURISCVState *env, int feature)
 141 {
 142     env->features |= (1ULL << feature);
 143 }
 144
 145 static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
 146 {
 147 #ifndef CONFIG_USER_ONLY
 148     env->resetvec = resetvec;
 149 #endif
 150 }
 151
 152 static void riscv_any_cpu_init(Object *obj)
 153 {
 154     CPURISCVState *env = &RISCV_CPU(obj)->env;
 155 #if defined(TARGET_RISCV32)
 156     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 157 #elif defined(TARGET_RISCV64)
 158     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 159 #endif
 160     set_priv_version(env, PRIV_VERSION_1_11_0);
 161 }
 162
 163 #if defined(TARGET_RISCV64)
 164 static void rv64_base_cpu_init(Object *obj)
 165 {
 166     CPURISCVState *env = &RISCV_CPU(obj)->env;
 167     /* We set this in the realise function */
 168     set_misa(env, RV64);
 169 }
 170
 171 static void rv64_sifive_u_cpu_init(Object *obj)
 172 {
 173     CPURISCVState *env = &RISCV_CPU(obj)->env;
 174     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 175     set_priv_version(env, PRIV_VERSION_1_10_0);
 176 }
 177
 178 static void rv64_sifive_e_cpu_init(Object *obj)
 179 {
 180     CPURISCVState *env = &RISCV_CPU(obj)->env;
 181     set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
 182     set_priv_version(env, PRIV_VERSION_1_10_0);
 183     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 184 }
 185 #else
 186 static void rv32_base_cpu_init(Object *obj)
 187 {
 188     CPURISCVState *env = &RISCV_CPU(obj)->env;
 189     /* We set this in the realise function */
 190     set_misa(env, RV32);
 191 }
 192
 193 static void rv32_sifive_u_cpu_init(Object *obj)
 194 {
 195     CPURISCVState *env = &RISCV_CPU(obj)->env;
 196     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 197     set_priv_version(env, PRIV_VERSION_1_10_0);
 198 }
 199
 200 static void rv32_sifive_e_cpu_init(Object *obj)
 201 {
 202     CPURISCVState *env = &RISCV_CPU(obj)->env;
 203     set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
 204     set_priv_version(env, PRIV_VERSION_1_10_0);
 205     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 206 }
 207
 208 static void rv32_ibex_cpu_init(Object *obj)
 209 {
 210     CPURISCVState *env = &RISCV_CPU(obj)->env;
 211     set_misa(env, RV32 | RVI | RVM | RVC | RVU);
 212     set_priv_version(env, PRIV_VERSION_1_10_0);
 213     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 214     qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
 215 }
 216
 217 static void rv32_imafcu_nommu_cpu_init(Object *obj)
 218 {
 219     CPURISCVState *env = &RISCV_CPU(obj)->env;
 220     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
 221     set_priv_version(env, PRIV_VERSION_1_10_0);
 222     set_resetvec(env, DEFAULT_RSTVEC);
 223     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 224 }
 225 #endif
 226
 227 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 228 {
 229     ObjectClass *oc;
 230     char *typename;
 231     char **cpuname;
 232
 233     cpuname = g_strsplit(cpu_model, ",", 1);
 234     typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
 235     oc = object_class_by_name(typename);
 236     g_strfreev(cpuname);
 237     g_free(typename);
 238     if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
 239         object_class_is_abstract(oc)) {
 240         return NULL;
 241     }
 242     return oc;
 243 }
 244
 245 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 246 {
 247     RISCVCPU *cpu = RISCV_CPU(cs);
 248     CPURISCVState *env = &cpu->env;
 249     int i;
 250
 251 #if !defined(CONFIG_USER_ONLY)
 252     if (riscv_has_ext(env, RVH)) {
 253         qemu_fprintf(f, " %s %d\n", "V      =  ", riscv_cpu_virt_enabled(env));
 254     }
 255 #endif
 256     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 257 #ifndef CONFIG_USER_ONLY
 258     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
 259     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
 260     if (riscv_cpu_is_32bit(env)) {
 261         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
 262                      (target_ulong)(env->mstatus >> 32));
 263     }
 264     if (riscv_has_ext(env, RVH)) {
 265         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
 266         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
 267                      (target_ulong)env->vsstatus);
 268     }
 269     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
 270     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
 271     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
 272     if (riscv_has_ext(env, RVH)) {
 273         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
 274     }
 275     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
 276     if (riscv_has_ext(env, RVH)) {
 277         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
 278     }
 279     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
 280     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
 281     if (riscv_has_ext(env, RVH)) {
 282         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
 283     }
 284     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
 285     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
 286     if (riscv_has_ext(env, RVH)) {
 287         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
 288     }
 289     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
 290     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
 291     if (riscv_has_ext(env, RVH)) {
 292         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
 293     }
 294     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval   ", env->mtval);
 295     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval   ", env->stval);
 296     if (riscv_has_ext(env, RVH)) {
 297         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
 298         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
 299     }
 300     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
 301     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
 302     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp    ", env->satp);
 303 #endif
 304
 305     for (i = 0; i < 32; i++) {
 306         qemu_fprintf(f, " %s " TARGET_FMT_lx,
 307                      riscv_int_regnames[i], env->gpr[i]);
 308         if ((i & 3) == 3) {
 309             qemu_fprintf(f, "\n");
 310         }
 311     }
 312     if (flags & CPU_DUMP_FPU) {
 313         for (i = 0; i < 32; i++) {
 314             qemu_fprintf(f, " %s %016" PRIx64,
 315                          riscv_fpr_regnames[i], env->fpr[i]);
 316             if ((i & 3) == 3) {
 317                 qemu_fprintf(f, "\n");
 318             }
 319         }
 320     }
 321 }
 322
 323 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
 324 {
 325     RISCVCPU *cpu = RISCV_CPU(cs);
 326     CPURISCVState *env = &cpu->env;
 327     env->pc = value;
 328 }
 329
 330 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
 331                                           const TranslationBlock *tb)
 332 {
 333     RISCVCPU *cpu = RISCV_CPU(cs);
 334     CPURISCVState *env = &cpu->env;
 335     env->pc = tb->pc;
 336 }
 337
 338 static bool riscv_cpu_has_work(CPUState *cs)
 339 {
 340 #ifndef CONFIG_USER_ONLY
 341     RISCVCPU *cpu = RISCV_CPU(cs);
 342     CPURISCVState *env = &cpu->env;
 343     /*
 344      * Definition of the WFI instruction requires it to ignore the privilege
 345      * mode and delegation registers, but respect individual enables
 346      */
 347     return (env->mip & env->mie) != 0;
 348 #else
 349     return true;
 350 #endif
 351 }
 352
 353 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
 354                           target_ulong *data)
 355 {
 356     env->pc = data[0];
 357 }
 358
 359 static void riscv_cpu_reset(DeviceState *dev)
 360 {
 361     CPUState *cs = CPU(dev);
 362     RISCVCPU *cpu = RISCV_CPU(cs);
 363     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 364     CPURISCVState *env = &cpu->env;
 365
 366     mcc->parent_reset(dev);
 367 #ifndef CONFIG_USER_ONLY
 368     env->priv = PRV_M;
 369     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
 370     env->mcause = 0;
 371     env->pc = env->resetvec;
 372     env->two_stage_lookup = false;
 373 #endif
 374     cs->exception_index = RISCV_EXCP_NONE;
 375     env->load_res = -1;
 376     set_default_nan_mode(1, &env->fp_status);
 377 }
 378
 379 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 380 {
 381     RISCVCPU *cpu = RISCV_CPU(s);
 382     if (riscv_cpu_is_32bit(&cpu->env)) {
 383         info->print_insn = print_insn_riscv32;
 384     } else {
 385         info->print_insn = print_insn_riscv64;
 386     }
 387 }
 388
 389 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 390 {
 391     CPUState *cs = CPU(dev);
 392     RISCVCPU *cpu = RISCV_CPU(dev);
 393     CPURISCVState *env = &cpu->env;
 394     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
 395     int priv_version = 0;
 396     target_ulong target_misa = env->misa;
 397     Error *local_err = NULL;
 398
 399     cpu_exec_realizefn(cs, &local_err);
 400     if (local_err != NULL) {
 401         error_propagate(errp, local_err);
 402         return;
 403     }
 404
 405     if (cpu->cfg.priv_spec) {
 406         if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 407             priv_version = PRIV_VERSION_1_11_0;
 408         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 409             priv_version = PRIV_VERSION_1_10_0;
 410         } else {
 411             error_setg(errp,
 412                        "Unsupported privilege spec version '%s'",
 413                        cpu->cfg.priv_spec);
 414             return;
 415         }
 416     }
 417
 418     if (priv_version) {
 419         set_priv_version(env, priv_version);
 420     } else if (!env->priv_ver) {
 421         set_priv_version(env, PRIV_VERSION_1_11_0);
 422     }
 423
 424     if (cpu->cfg.mmu) {
 425         set_feature(env, RISCV_FEATURE_MMU);
 426     }
 427
 428     if (cpu->cfg.pmp) {
 429         set_feature(env, RISCV_FEATURE_PMP);
 430
 431         /*
 432          * Enhanced PMP should only be available
 433          * on harts with PMP support
 434          */
 435         if (cpu->cfg.epmp) {
 436             set_feature(env, RISCV_FEATURE_EPMP);
 437         }
 438     }
 439
 440     set_resetvec(env, cpu->cfg.resetvec);
 441
 442     /* If only XLEN is set for misa, then set misa from properties */
 443     if (env->misa == RV32 || env->misa == RV64) {
 444         /* Do some ISA extension error checking */
 445         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
 446             error_setg(errp,
 447                        "I and E extensions are incompatible");
 448                        return;
 449        }
 450
 451         if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
 452             error_setg(errp,
 453                        "Either I or E extension must be set");
 454                        return;
 455        }
 456
 457        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
 458                                cpu->cfg.ext_a & cpu->cfg.ext_f &
 459                                cpu->cfg.ext_d)) {
 460             warn_report("Setting G will also set IMAFD");
 461             cpu->cfg.ext_i = true;
 462             cpu->cfg.ext_m = true;
 463             cpu->cfg.ext_a = true;
 464             cpu->cfg.ext_f = true;
 465             cpu->cfg.ext_d = true;
 466         }
 467
 468         /* Set the ISA extensions, checks should have happened above */
 469         if (cpu->cfg.ext_i) {
 470             target_misa |= RVI;
 471         }
 472         if (cpu->cfg.ext_e) {
 473             target_misa |= RVE;
 474         }
 475         if (cpu->cfg.ext_m) {
 476             target_misa |= RVM;
 477         }
 478         if (cpu->cfg.ext_a) {
 479             target_misa |= RVA;
 480         }
 481         if (cpu->cfg.ext_f) {
 482             target_misa |= RVF;
 483         }
 484         if (cpu->cfg.ext_d) {
 485             target_misa |= RVD;
 486         }
 487         if (cpu->cfg.ext_c) {
 488             target_misa |= RVC;
 489         }
 490         if (cpu->cfg.ext_s) {
 491             target_misa |= RVS;
 492         }
 493         if (cpu->cfg.ext_u) {
 494             target_misa |= RVU;
 495         }
 496         if (cpu->cfg.ext_h) {
 497             target_misa |= RVH;
 498         }
 499         if (cpu->cfg.ext_b) {
 500             int bext_version = BEXT_VERSION_0_93_0;
 501             target_misa |= RVB;
 502
 503             if (cpu->cfg.bext_spec) {
 504                 if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
 505                     bext_version = BEXT_VERSION_0_93_0;
 506                 } else {
 507                     error_setg(errp,
 508                            "Unsupported bitmanip spec version '%s'",
 509                            cpu->cfg.bext_spec);
 510                     return;
 511                 }
 512             } else {
 513                 qemu_log("bitmanip version is not specified, "
 514                          "use the default value v0.93\n");
 515             }
 516             set_bext_version(env, bext_version);
 517         }
 518         if (cpu->cfg.ext_v) {
 519             int vext_version = VEXT_VERSION_0_07_1;
 520             target_misa |= RVV;
 521             if (!is_power_of_2(cpu->cfg.vlen)) {
 522                 error_setg(errp,
 523                         "Vector extension VLEN must be power of 2");
 524                 return;
 525             }
 526             if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
 527                 error_setg(errp,
 528                         "Vector extension implementation only supports VLEN "
 529                         "in the range [128, %d]", RV_VLEN_MAX);
 530                 return;
 531             }
 532             if (!is_power_of_2(cpu->cfg.elen)) {
 533                 error_setg(errp,
 534                         "Vector extension ELEN must be power of 2");
 535                 return;
 536             }
 537             if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
 538                 error_setg(errp,
 539                         "Vector extension implementation only supports ELEN "
 540                         "in the range [8, 64]");
 541                 return;
 542             }
 543             if (cpu->cfg.vext_spec) {
 544                 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
 545                     vext_version = VEXT_VERSION_0_07_1;
 546                 } else {
 547                     error_setg(errp,
 548                            "Unsupported vector spec version '%s'",
 549                            cpu->cfg.vext_spec);
 550                     return;
 551                 }
 552             } else {
 553                 qemu_log("vector version is not specified, "
 554                         "use the default value v0.7.1\n");
 555             }
 556             set_vext_version(env, vext_version);
 557         }
 558
 559         set_misa(env, target_misa);
 560     }
 561
 562     riscv_cpu_register_gdb_regs_for_features(cs);
 563
 564     qemu_init_vcpu(cs);
 565     cpu_reset(cs);
 566
 567     mcc->parent_realize(dev, errp);
 568 }
 569
 570 #ifndef CONFIG_USER_ONLY
 571 static void riscv_cpu_set_irq(void *opaque, int irq, int level)
 572 {
 573     RISCVCPU *cpu = RISCV_CPU(opaque);
 574
 575     switch (irq) {
 576     case IRQ_U_SOFT:
 577     case IRQ_S_SOFT:
 578     case IRQ_VS_SOFT:
 579     case IRQ_M_SOFT:
 580     case IRQ_U_TIMER:
 581     case IRQ_S_TIMER:
 582     case IRQ_VS_TIMER:
 583     case IRQ_M_TIMER:
 584     case IRQ_U_EXT:
 585     case IRQ_S_EXT:
 586     case IRQ_VS_EXT:
 587     case IRQ_M_EXT:
 588         riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
 589         break;
 590     default:
 591         g_assert_not_reached();
 592     }
 593 }
 594 #endif /* CONFIG_USER_ONLY */
 595
 596 static void riscv_cpu_init(Object *obj)
 597 {
 598     RISCVCPU *cpu = RISCV_CPU(obj);
 599
 600     cpu_set_cpustate_pointers(cpu);
 601
 602 #ifndef CONFIG_USER_ONLY
 603     qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
 604 #endif /* CONFIG_USER_ONLY */
 605 }
 606
 607 static Property riscv_cpu_properties[] = {
 608     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
 609     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
 610     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
 611     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
 612     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
 613     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
 614     DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
 615     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
 616     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
 617     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
 618     /* This is experimental so mark with 'x-' */
 619     DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
 620     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
 621     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
 622     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
 623     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
 624     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 625     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
 626     DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
 627     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
 628     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
 629     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 630     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
 631     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 632     /* ePMP 0.9.3 */
 633     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
 634
 635     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
 636     DEFINE_PROP_END_OF_LIST(),
 637 };
 638
 639 static gchar *riscv_gdb_arch_name(CPUState *cs)
 640 {
 641     RISCVCPU *cpu = RISCV_CPU(cs);
 642     CPURISCVState *env = &cpu->env;
 643
 644     if (riscv_cpu_is_32bit(env)) {
 645         return g_strdup("riscv:rv32");
 646     } else {
 647         return g_strdup("riscv:rv64");
 648     }
 649 }
 650
 651 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 652 {
 653     RISCVCPU *cpu = RISCV_CPU(cs);
 654
 655     if (strcmp(xmlname, "riscv-csr.xml") == 0) {
 656         return cpu->dyn_csr_xml;
 657     }
 658
 659     return NULL;
 660 }
 661
 662 #ifndef CONFIG_USER_ONLY
 663 #include "hw/core/sysemu-cpu-ops.h"
 664
 665 static const struct SysemuCPUOps riscv_sysemu_ops = {
 666     .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
 667     .write_elf64_note = riscv_cpu_write_elf64_note,
 668     .write_elf32_note = riscv_cpu_write_elf32_note,
 669     .legacy_vmsd = &vmstate_riscv_cpu,
 670 };
 671 #endif
 672
 673 #include "hw/core/tcg-cpu-ops.h"
 674
 675 static const struct TCGCPUOps riscv_tcg_ops = {
 676     .initialize = riscv_translate_init,
 677     .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
 678     .tlb_fill = riscv_cpu_tlb_fill,
 679
 680 #ifndef CONFIG_USER_ONLY
 681     .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
 682     .do_interrupt = riscv_cpu_do_interrupt,
 683     .do_transaction_failed = riscv_cpu_do_transaction_failed,
 684     .do_unaligned_access = riscv_cpu_do_unaligned_access,
 685 #endif /* !CONFIG_USER_ONLY */
 686 };
 687
 688 static void riscv_cpu_class_init(ObjectClass *c, void *data)
 689 {
 690     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
 691     CPUClass *cc = CPU_CLASS(c);
 692     DeviceClass *dc = DEVICE_CLASS(c);
 693
 694     device_class_set_parent_realize(dc, riscv_cpu_realize,
 695                                     &mcc->parent_realize);
 696
 697     device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
 698
 699     cc->class_by_name = riscv_cpu_class_by_name;
 700     cc->has_work = riscv_cpu_has_work;
 701     cc->dump_state = riscv_cpu_dump_state;
 702     cc->set_pc = riscv_cpu_set_pc;
 703     cc->gdb_read_register = riscv_cpu_gdb_read_register;
 704     cc->gdb_write_register = riscv_cpu_gdb_write_register;
 705     cc->gdb_num_core_regs = 33;
 706 #if defined(TARGET_RISCV32)
 707     cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 708 #elif defined(TARGET_RISCV64)
 709     cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 710 #endif
 711     cc->gdb_stop_before_watchpoint = true;
 712     cc->disas_set_info = riscv_cpu_disas_set_info;
 713 #ifndef CONFIG_USER_ONLY
 714     cc->sysemu_ops = &riscv_sysemu_ops;
 715 #endif
 716     cc->gdb_arch_name = riscv_gdb_arch_name;
 717     cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
 718     cc->tcg_ops = &riscv_tcg_ops;
 719
 720     device_class_set_props(dc, riscv_cpu_properties);
 721 }
 722
 723 char *riscv_isa_string(RISCVCPU *cpu)
 724 {
 725     int i;
 726     const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
 727     char *isa_str = g_new(char, maxlen);
 728     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
 729     for (i = 0; i < sizeof(riscv_exts); i++) {
 730         if (cpu->env.misa & RV(riscv_exts[i])) {
 731             *p++ = qemu_tolower(riscv_exts[i]);
 732         }
 733     }
 734     *p = '\0';
 735     return isa_str;
 736 }
 737
 738 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
 739 {
 740     ObjectClass *class_a = (ObjectClass *)a;
 741     ObjectClass *class_b = (ObjectClass *)b;
 742     const char *name_a, *name_b;
 743
 744     name_a = object_class_get_name(class_a);
 745     name_b = object_class_get_name(class_b);
 746     return strcmp(name_a, name_b);
 747 }
 748
 749 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
 750 {
 751     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 752     int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
 753
 754     qemu_printf("%.*s\n", len, typename);
 755 }
 756
 757 void riscv_cpu_list(void)
 758 {
 759     GSList *list;
 760
 761     list = object_class_get_list(TYPE_RISCV_CPU, false);
 762     list = g_slist_sort(list, riscv_cpu_list_compare);
 763     g_slist_foreach(list, riscv_cpu_list_entry, NULL);
 764     g_slist_free(list);
 765 }
 766
 767 #define DEFINE_CPU(type_name, initfn)      \
 768     {                                      \
 769         .name = type_name,                 \
 770         .parent = TYPE_RISCV_CPU,          \
 771         .instance_init = initfn            \
 772     }
 773
 774 static const TypeInfo riscv_cpu_type_infos[] = {
 775     {
 776         .name = TYPE_RISCV_CPU,
 777         .parent = TYPE_CPU,
 778         .instance_size = sizeof(RISCVCPU),
 779         .instance_align = __alignof__(RISCVCPU),
 780         .instance_init = riscv_cpu_init,
 781         .abstract = true,
 782         .class_size = sizeof(RISCVCPUClass),
 783         .class_init = riscv_cpu_class_init,
 784     },
 785     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
 786 #if defined(TARGET_RISCV32)
 787     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           rv32_base_cpu_init),
 788     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
 789     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32_sifive_e_cpu_init),
 790     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),
 791     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32_sifive_u_cpu_init),
 792 #elif defined(TARGET_RISCV64)
 793     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           rv64_base_cpu_init),
 794     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
 795     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
 796     DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C,         rv64_sifive_u_cpu_init),
 797 #endif
 798 };
 799
 800 DEFINE_TYPES(riscv_cpu_type_infos)