target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22 #ifndef CPU_S390X_H
  23 #define CPU_S390X_H
  24
  25 #include "config.h"
  26 #include "qemu-common.h"
  27
  28 #define TARGET_LONG_BITS 64
  29
  30 #define ELF_MACHINE_UNAME "S390X"
  31
  32 #define CPUArchState struct CPUS390XState
  33
  34 #include "exec/cpu-defs.h"
  35 #define TARGET_PAGE_BITS 12
  36
  37 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  38 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  39
  40 #include "exec/cpu-all.h"
  41
  42 #include "fpu/softfloat.h"
  43
  44 #define NB_MMU_MODES 3
  45 #define TARGET_INSN_START_EXTRA_WORDS 1
  46
  47 #define MMU_MODE0_SUFFIX _primary
  48 #define MMU_MODE1_SUFFIX _secondary
  49 #define MMU_MODE2_SUFFIX _home
  50
  51 #define MMU_USER_IDX 0
  52
  53 #define MAX_EXT_QUEUE 16
  54 #define MAX_IO_QUEUE 16
  55 #define MAX_MCHK_QUEUE 16
  56
  57 #define PSW_MCHK_MASK 0x0004000000000000
  58 #define PSW_IO_MASK 0x0200000000000000
  59
  60 typedef struct PSW {
  61     uint64_t mask;
  62     uint64_t addr;
  63 } PSW;
  64
  65 typedef struct ExtQueue {
  66     uint32_t code;
  67     uint32_t param;
  68     uint32_t param64;
  69 } ExtQueue;
  70
  71 typedef struct IOIntQueue {
  72     uint16_t id;
  73     uint16_t nr;
  74     uint32_t parm;
  75     uint32_t word;
  76 } IOIntQueue;
  77
  78 typedef struct MchkQueue {
  79     uint16_t type;
  80 } MchkQueue;
  81
  82 typedef struct CPUS390XState {
  83     uint64_t regs[16];     /* GP registers */
  84     /*
  85      * The floating point registers are part of the vector registers.
  86      * vregs[0][0] -> vregs[15][0] are 16 floating point registers
  87      */
  88     CPU_DoubleU vregs[32][2];  /* vector registers */
  89     uint32_t aregs[16];    /* access registers */
  90
  91     uint32_t fpc;          /* floating-point control register */
  92     uint32_t cc_op;
  93
  94     float_status fpu_status; /* passed to softfloat lib */
  95
  96     /* The low part of a 128-bit return, or remainder of a divide.  */
  97     uint64_t retxl;
  98
  99     PSW psw;
 100
 101     uint64_t cc_src;
 102     uint64_t cc_dst;
 103     uint64_t cc_vr;
 104
 105     uint64_t __excp_addr;
 106     uint64_t psa;
 107
 108     uint32_t int_pgm_code;
 109     uint32_t int_pgm_ilen;
 110
 111     uint32_t int_svc_code;
 112     uint32_t int_svc_ilen;
 113
 114     uint64_t per_address;
 115     uint16_t per_perc_atmid;
 116
 117     uint64_t cregs[16]; /* control registers */
 118
 119     ExtQueue ext_queue[MAX_EXT_QUEUE];
 120     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 121     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 122
 123     int pending_int;
 124     int ext_index;
 125     int io_index[8];
 126     int mchk_index;
 127
 128     uint64_t ckc;
 129     uint64_t cputm;
 130     uint32_t todpr;
 131
 132     uint64_t pfault_token;
 133     uint64_t pfault_compare;
 134     uint64_t pfault_select;
 135
 136     uint64_t gbea;
 137     uint64_t pp;
 138
 139     CPU_COMMON
 140
 141     /* reset does memset(0) up to here */
 142
 143     uint32_t cpu_num;
 144     uint32_t machine_type;
 145
 146     uint64_t tod_offset;
 147     uint64_t tod_basetime;
 148     QEMUTimer *tod_timer;
 149
 150     QEMUTimer *cpu_timer;
 151
 152     /*
 153      * The cpu state represents the logical state of a cpu. In contrast to other
 154      * architectures, there is a difference between a halt and a stop on s390.
 155      * If all cpus are either stopped (including check stop) or in the disabled
 156      * wait state, the vm can be shut down.
 157      */
 158 #define CPU_STATE_UNINITIALIZED        0x00
 159 #define CPU_STATE_STOPPED              0x01
 160 #define CPU_STATE_CHECK_STOP           0x02
 161 #define CPU_STATE_OPERATING            0x03
 162 #define CPU_STATE_LOAD                 0x04
 163     uint8_t cpu_state;
 164
 165     /* currently processed sigp order */
 166     uint8_t sigp_order;
 167
 168 } CPUS390XState;
 169
 170 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
 171 {
 172     return &cs->vregs[nr][0];
 173 }
 174
 175 #include "cpu-qom.h"
 176 #include <sysemu/kvm.h>
 177
 178 /* distinguish between 24 bit and 31 bit addressing */
 179 #define HIGH_ORDER_BIT 0x80000000
 180
 181 /* Interrupt Codes */
 182 /* Program Interrupts */
 183 #define PGM_OPERATION                   0x0001
 184 #define PGM_PRIVILEGED                  0x0002
 185 #define PGM_EXECUTE                     0x0003
 186 #define PGM_PROTECTION                  0x0004
 187 #define PGM_ADDRESSING                  0x0005
 188 #define PGM_SPECIFICATION               0x0006
 189 #define PGM_DATA                        0x0007
 190 #define PGM_FIXPT_OVERFLOW              0x0008
 191 #define PGM_FIXPT_DIVIDE                0x0009
 192 #define PGM_DEC_OVERFLOW                0x000a
 193 #define PGM_DEC_DIVIDE                  0x000b
 194 #define PGM_HFP_EXP_OVERFLOW            0x000c
 195 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 196 #define PGM_HFP_SIGNIFICANCE            0x000e
 197 #define PGM_HFP_DIVIDE                  0x000f
 198 #define PGM_SEGMENT_TRANS               0x0010
 199 #define PGM_PAGE_TRANS                  0x0011
 200 #define PGM_TRANS_SPEC                  0x0012
 201 #define PGM_SPECIAL_OP                  0x0013
 202 #define PGM_OPERAND                     0x0015
 203 #define PGM_TRACE_TABLE                 0x0016
 204 #define PGM_SPACE_SWITCH                0x001c
 205 #define PGM_HFP_SQRT                    0x001d
 206 #define PGM_PC_TRANS_SPEC               0x001f
 207 #define PGM_AFX_TRANS                   0x0020
 208 #define PGM_ASX_TRANS                   0x0021
 209 #define PGM_LX_TRANS                    0x0022
 210 #define PGM_EX_TRANS                    0x0023
 211 #define PGM_PRIM_AUTH                   0x0024
 212 #define PGM_SEC_AUTH                    0x0025
 213 #define PGM_ALET_SPEC                   0x0028
 214 #define PGM_ALEN_SPEC                   0x0029
 215 #define PGM_ALE_SEQ                     0x002a
 216 #define PGM_ASTE_VALID                  0x002b
 217 #define PGM_ASTE_SEQ                    0x002c
 218 #define PGM_EXT_AUTH                    0x002d
 219 #define PGM_STACK_FULL                  0x0030
 220 #define PGM_STACK_EMPTY                 0x0031
 221 #define PGM_STACK_SPEC                  0x0032
 222 #define PGM_STACK_TYPE                  0x0033
 223 #define PGM_STACK_OP                    0x0034
 224 #define PGM_ASCE_TYPE                   0x0038
 225 #define PGM_REG_FIRST_TRANS             0x0039
 226 #define PGM_REG_SEC_TRANS               0x003a
 227 #define PGM_REG_THIRD_TRANS             0x003b
 228 #define PGM_MONITOR                     0x0040
 229 #define PGM_PER                         0x0080
 230 #define PGM_CRYPTO                      0x0119
 231
 232 /* External Interrupts */
 233 #define EXT_INTERRUPT_KEY               0x0040
 234 #define EXT_CLOCK_COMP                  0x1004
 235 #define EXT_CPU_TIMER                   0x1005
 236 #define EXT_MALFUNCTION                 0x1200
 237 #define EXT_EMERGENCY                   0x1201
 238 #define EXT_EXTERNAL_CALL               0x1202
 239 #define EXT_ETR                         0x1406
 240 #define EXT_SERVICE                     0x2401
 241 #define EXT_VIRTIO                      0x2603
 242
 243 /* PSW defines */
 244 #undef PSW_MASK_PER
 245 #undef PSW_MASK_DAT
 246 #undef PSW_MASK_IO
 247 #undef PSW_MASK_EXT
 248 #undef PSW_MASK_KEY
 249 #undef PSW_SHIFT_KEY
 250 #undef PSW_MASK_MCHECK
 251 #undef PSW_MASK_WAIT
 252 #undef PSW_MASK_PSTATE
 253 #undef PSW_MASK_ASC
 254 #undef PSW_MASK_CC
 255 #undef PSW_MASK_PM
 256 #undef PSW_MASK_64
 257 #undef PSW_MASK_32
 258 #undef PSW_MASK_ESA_ADDR
 259
 260 #define PSW_MASK_PER            0x4000000000000000ULL
 261 #define PSW_MASK_DAT            0x0400000000000000ULL
 262 #define PSW_MASK_IO             0x0200000000000000ULL
 263 #define PSW_MASK_EXT            0x0100000000000000ULL
 264 #define PSW_MASK_KEY            0x00F0000000000000ULL
 265 #define PSW_SHIFT_KEY           56
 266 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 267 #define PSW_MASK_WAIT           0x0002000000000000ULL
 268 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 269 #define PSW_MASK_ASC            0x0000C00000000000ULL
 270 #define PSW_MASK_CC             0x0000300000000000ULL
 271 #define PSW_MASK_PM             0x00000F0000000000ULL
 272 #define PSW_MASK_64             0x0000000100000000ULL
 273 #define PSW_MASK_32             0x0000000080000000ULL
 274 #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 275
 276 #undef PSW_ASC_PRIMARY
 277 #undef PSW_ASC_ACCREG
 278 #undef PSW_ASC_SECONDARY
 279 #undef PSW_ASC_HOME
 280
 281 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 282 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 283 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 284 #define PSW_ASC_HOME            0x0000C00000000000ULL
 285
 286 /* tb flags */
 287
 288 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 289 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 290 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 291 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 292 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 293 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 294 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 295 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 296 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 297 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 298 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 299 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 300 #define FLAG_MASK_32            0x00001000
 301
 302 /* Control register 0 bits */
 303 #define CR0_LOWPROT             0x0000000010000000ULL
 304 #define CR0_EDAT                0x0000000000800000ULL
 305
 306 /* MMU */
 307 #define MMU_PRIMARY_IDX         0
 308 #define MMU_SECONDARY_IDX       1
 309 #define MMU_HOME_IDX            2
 310
 311 static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch)
 312 {
 313     switch (env->psw.mask & PSW_MASK_ASC) {
 314     case PSW_ASC_PRIMARY:
 315         return MMU_PRIMARY_IDX;
 316     case PSW_ASC_SECONDARY:
 317         return MMU_SECONDARY_IDX;
 318     case PSW_ASC_HOME:
 319         return MMU_HOME_IDX;
 320     case PSW_ASC_ACCREG:
 321         /* Fallthrough: access register mode is not yet supported */
 322     default:
 323         abort();
 324     }
 325 }
 326
 327 static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
 328 {
 329     switch (mmu_idx) {
 330     case MMU_PRIMARY_IDX:
 331         return PSW_ASC_PRIMARY;
 332     case MMU_SECONDARY_IDX:
 333         return PSW_ASC_SECONDARY;
 334     case MMU_HOME_IDX:
 335         return PSW_ASC_HOME;
 336     default:
 337         abort();
 338     }
 339 }
 340
 341 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 342                                         target_ulong *cs_base, int *flags)
 343 {
 344     *pc = env->psw.addr;
 345     *cs_base = 0;
 346     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 347              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 348 }
 349
 350 /* While the PoO talks about ILC (a number between 1-3) what is actually
 351    stored in LowCore is shifted left one bit (an even between 2-6).  As
 352    this is the actual length of the insn and therefore more useful, that
 353    is what we want to pass around and manipulate.  To make sure that we
 354    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 355 static inline int get_ilen(uint8_t opc)
 356 {
 357     switch (opc >> 6) {
 358     case 0:
 359         return 2;
 360     case 1:
 361     case 2:
 362         return 4;
 363     default:
 364         return 6;
 365     }
 366 }
 367
 368 /* PER bits from control register 9 */
 369 #define PER_CR9_EVENT_BRANCH           0x80000000
 370 #define PER_CR9_EVENT_IFETCH           0x40000000
 371 #define PER_CR9_EVENT_STORE            0x20000000
 372 #define PER_CR9_EVENT_STORE_REAL       0x08000000
 373 #define PER_CR9_EVENT_NULLIFICATION    0x01000000
 374 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
 375 #define PER_CR9_CONTROL_ALTERATION     0x00200000
 376
 377 /* PER bits from the PER CODE/ATMID/AI in lowcore */
 378 #define PER_CODE_EVENT_BRANCH          0x8000
 379 #define PER_CODE_EVENT_IFETCH          0x4000
 380 #define PER_CODE_EVENT_STORE           0x2000
 381 #define PER_CODE_EVENT_STORE_REAL      0x0800
 382 #define PER_CODE_EVENT_NULLIFICATION   0x0100
 383
 384 /* Compute the ATMID field that is stored in the per_perc_atmid lowcore
 385    entry when a PER exception is triggered.  */
 386 static inline uint8_t get_per_atmid(CPUS390XState *env)
 387 {
 388     return ((env->psw.mask & PSW_MASK_64) ?      (1 << 7) : 0) |
 389            (                                     (1 << 6)    ) |
 390            ((env->psw.mask & PSW_MASK_32) ?      (1 << 5) : 0) |
 391            ((env->psw.mask & PSW_MASK_DAT)?      (1 << 4) : 0) |
 392            ((env->psw.mask & PSW_ASC_SECONDARY)? (1 << 3) : 0) |
 393            ((env->psw.mask & PSW_ASC_ACCREG)?    (1 << 2) : 0);
 394 }
 395
 396 /* Check if an address is within the PER starting address and the PER
 397    ending address.  The address range might loop.  */
 398 static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr)
 399 {
 400     if (env->cregs[10] <= env->cregs[11]) {
 401         return env->cregs[10] <= addr && addr <= env->cregs[11];
 402     } else {
 403         return env->cregs[10] <= addr || addr <= env->cregs[11];
 404     }
 405 }
 406
 407 #ifndef CONFIG_USER_ONLY
 408 /* In several cases of runtime exceptions, we havn't recorded the true
 409    instruction length.  Use these codes when raising exceptions in order
 410    to re-compute the length by examining the insn in memory.  */
 411 #define ILEN_LATER       0x20
 412 #define ILEN_LATER_INC   0x21
 413 void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
 414 #endif
 415
 416 S390CPU *cpu_s390x_init(const char *cpu_model);
 417 void s390x_translate_init(void);
 418 int cpu_s390x_exec(CPUState *cpu);
 419
 420 /* you can call this signal handler from your SIGBUS and SIGSEGV
 421    signal handlers to inform the virtual CPU of exceptions. non zero
 422    is returned if the signal was handled by the virtual CPU.  */
 423 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 424                            void *puc);
 425 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 426                               int mmu_idx);
 427
 428 #include "ioinst.h"
 429
 430
 431 #ifndef CONFIG_USER_ONLY
 432 void do_restart_interrupt(CPUS390XState *env);
 433
 434 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
 435                                        uint8_t *ar)
 436 {
 437     hwaddr addr = 0;
 438     uint8_t reg;
 439
 440     reg = ipb >> 28;
 441     if (reg > 0) {
 442         addr = env->regs[reg];
 443     }
 444     addr += (ipb >> 16) & 0xfff;
 445     if (ar) {
 446         *ar = reg;
 447     }
 448
 449     return addr;
 450 }
 451
 452 /* Base/displacement are at the same locations. */
 453 #define decode_basedisp_rs decode_basedisp_s
 454
 455 /* helper functions for run_on_cpu() */
 456 static inline void s390_do_cpu_reset(void *arg)
 457 {
 458     CPUState *cs = arg;
 459     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 460
 461     scc->cpu_reset(cs);
 462 }
 463 static inline void s390_do_cpu_full_reset(void *arg)
 464 {
 465     CPUState *cs = arg;
 466
 467     cpu_reset(cs);
 468 }
 469
 470 void s390x_tod_timer(void *opaque);
 471 void s390x_cpu_timer(void *opaque);
 472
 473 int s390_virtio_hypercall(CPUS390XState *env);
 474 void s390_virtio_irq(int config_change, uint64_t token);
 475
 476 #ifdef CONFIG_KVM
 477 void kvm_s390_virtio_irq(int config_change, uint64_t token);
 478 void kvm_s390_service_interrupt(uint32_t parm);
 479 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
 480 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
 481 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
 482 void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
 483 int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
 484                     int len, bool is_write);
 485 int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
 486 int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
 487 #else
 488 static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
 489 {
 490 }
 491 static inline void kvm_s390_service_interrupt(uint32_t parm)
 492 {
 493 }
 494 static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 495 {
 496     return -ENOSYS;
 497 }
 498 static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 499 {
 500     return -ENOSYS;
 501 }
 502 static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
 503                                   void *hostbuf, int len, bool is_write)
 504 {
 505     return -ENOSYS;
 506 }
 507 static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
 508                                              uint64_t te_code)
 509 {
 510 }
 511 #endif
 512
 513 static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 514 {
 515     if (kvm_enabled()) {
 516         return kvm_s390_get_clock(tod_high, tod_low);
 517     }
 518     /* Fixme TCG */
 519     *tod_high = 0;
 520     *tod_low = 0;
 521     return 0;
 522 }
 523
 524 static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 525 {
 526     if (kvm_enabled()) {
 527         return kvm_s390_set_clock(tod_high, tod_low);
 528     }
 529     /* Fixme TCG */
 530     return 0;
 531 }
 532
 533 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 534 unsigned int s390_cpu_halt(S390CPU *cpu);
 535 void s390_cpu_unhalt(S390CPU *cpu);
 536 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
 537 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
 538 {
 539     return cpu->env.cpu_state;
 540 }
 541
 542 void gtod_save(QEMUFile *f, void *opaque);
 543 int gtod_load(QEMUFile *f, void *opaque, int version_id);
 544
 545 /* service interrupts are floating therefore we must not pass an cpustate */
 546 void s390_sclp_extint(uint32_t parm);
 547
 548 #else
 549 static inline unsigned int s390_cpu_halt(S390CPU *cpu)
 550 {
 551     return 0;
 552 }
 553
 554 static inline void s390_cpu_unhalt(S390CPU *cpu)
 555 {
 556 }
 557
 558 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 559 {
 560     return 0;
 561 }
 562 #endif
 563 void cpu_lock(void);
 564 void cpu_unlock(void);
 565
 566 typedef struct SubchDev SubchDev;
 567
 568 #ifndef CONFIG_USER_ONLY
 569 extern void subsystem_reset(void);
 570 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 571                          uint16_t schid);
 572 bool css_subch_visible(SubchDev *sch);
 573 void css_conditional_io_interrupt(SubchDev *sch);
 574 int css_do_stsch(SubchDev *sch, SCHIB *schib);
 575 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
 576 int css_do_msch(SubchDev *sch, const SCHIB *schib);
 577 int css_do_xsch(SubchDev *sch);
 578 int css_do_csch(SubchDev *sch);
 579 int css_do_hsch(SubchDev *sch);
 580 int css_do_ssch(SubchDev *sch, ORB *orb);
 581 int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
 582 void css_do_tsch_update_subch(SubchDev *sch);
 583 int css_do_stcrw(CRW *crw);
 584 void css_undo_stcrw(CRW *crw);
 585 int css_do_tpi(IOIntCode *int_code, int lowcore);
 586 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
 587                          int rfmt, void *buf);
 588 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
 589 int css_enable_mcsse(void);
 590 int css_enable_mss(void);
 591 int css_do_rsch(SubchDev *sch);
 592 int css_do_rchp(uint8_t cssid, uint8_t chpid);
 593 bool css_present(uint8_t cssid);
 594 #endif
 595
 596 #define cpu_init(model) CPU(cpu_s390x_init(model))
 597 #define cpu_exec cpu_s390x_exec
 598 #define cpu_signal_handler cpu_s390x_signal_handler
 599
 600 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 601 #define cpu_list s390_cpu_list
 602
 603 #include "exec/exec-all.h"
 604
 605 #define EXCP_EXT 1 /* external interrupt */
 606 #define EXCP_SVC 2 /* supervisor call (syscall) */
 607 #define EXCP_PGM 3 /* program interruption */
 608 #define EXCP_IO  7 /* I/O interrupt */
 609 #define EXCP_MCHK 8 /* machine check */
 610
 611 #define INTERRUPT_EXT        (1 << 0)
 612 #define INTERRUPT_TOD        (1 << 1)
 613 #define INTERRUPT_CPUTIMER   (1 << 2)
 614 #define INTERRUPT_IO         (1 << 3)
 615 #define INTERRUPT_MCHK       (1 << 4)
 616
 617 /* Program Status Word.  */
 618 #define S390_PSWM_REGNUM 0
 619 #define S390_PSWA_REGNUM 1
 620 /* General Purpose Registers.  */
 621 #define S390_R0_REGNUM 2
 622 #define S390_R1_REGNUM 3
 623 #define S390_R2_REGNUM 4
 624 #define S390_R3_REGNUM 5
 625 #define S390_R4_REGNUM 6
 626 #define S390_R5_REGNUM 7
 627 #define S390_R6_REGNUM 8
 628 #define S390_R7_REGNUM 9
 629 #define S390_R8_REGNUM 10
 630 #define S390_R9_REGNUM 11
 631 #define S390_R10_REGNUM 12
 632 #define S390_R11_REGNUM 13
 633 #define S390_R12_REGNUM 14
 634 #define S390_R13_REGNUM 15
 635 #define S390_R14_REGNUM 16
 636 #define S390_R15_REGNUM 17
 637 /* Total Core Registers. */
 638 #define S390_NUM_CORE_REGS 18
 639
 640 /* CC optimization */
 641
 642 enum cc_op {
 643     CC_OP_CONST0 = 0,           /* CC is 0 */
 644     CC_OP_CONST1,               /* CC is 1 */
 645     CC_OP_CONST2,               /* CC is 2 */
 646     CC_OP_CONST3,               /* CC is 3 */
 647
 648     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 649     CC_OP_STATIC,               /* CC value is env->cc_op */
 650
 651     CC_OP_NZ,                   /* env->cc_dst != 0 */
 652     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 653     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 654     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 655     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 656     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 657     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 658
 659     CC_OP_ADD_64,               /* overflow on add (64bit) */
 660     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 661     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 662     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 663     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 664     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 665     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 666     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 667
 668     CC_OP_ADD_32,               /* overflow on add (32bit) */
 669     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 670     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 671     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 672     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 673     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 674     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 675     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 676
 677     CC_OP_COMP_32,              /* complement */
 678     CC_OP_COMP_64,              /* complement */
 679
 680     CC_OP_TM_32,                /* test under mask (32bit) */
 681     CC_OP_TM_64,                /* test under mask (64bit) */
 682
 683     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 684     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 685     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 686
 687     CC_OP_ICM,                  /* insert characters under mask */
 688     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 689     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 690     CC_OP_FLOGR,                /* find leftmost one */
 691     CC_OP_MAX
 692 };
 693
 694 static const char *cc_names[] = {
 695     [CC_OP_CONST0]    = "CC_OP_CONST0",
 696     [CC_OP_CONST1]    = "CC_OP_CONST1",
 697     [CC_OP_CONST2]    = "CC_OP_CONST2",
 698     [CC_OP_CONST3]    = "CC_OP_CONST3",
 699     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 700     [CC_OP_STATIC]    = "CC_OP_STATIC",
 701     [CC_OP_NZ]        = "CC_OP_NZ",
 702     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 703     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 704     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 705     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 706     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 707     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 708     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 709     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 710     [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 711     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 712     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 713     [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 714     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 715     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 716     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 717     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 718     [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 719     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 720     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 721     [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 722     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 723     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 724     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 725     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 726     [CC_OP_TM_32]     = "CC_OP_TM_32",
 727     [CC_OP_TM_64]     = "CC_OP_TM_64",
 728     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 729     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 730     [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 731     [CC_OP_ICM]       = "CC_OP_ICM",
 732     [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 733     [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 734     [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 735 };
 736
 737 static inline const char *cc_name(int cc_op)
 738 {
 739     return cc_names[cc_op];
 740 }
 741
 742 static inline void setcc(S390CPU *cpu, uint64_t cc)
 743 {
 744     CPUS390XState *env = &cpu->env;
 745
 746     env->psw.mask &= ~(3ull << 44);
 747     env->psw.mask |= (cc & 3) << 44;
 748     env->cc_op = cc;
 749 }
 750
 751 typedef struct LowCore
 752 {
 753     /* prefix area: defined by architecture */
 754     uint32_t        ccw1[2];                  /* 0x000 */
 755     uint32_t        ccw2[4];                  /* 0x008 */
 756     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 757     uint32_t        ext_params;               /* 0x080 */
 758     uint16_t        cpu_addr;                 /* 0x084 */
 759     uint16_t        ext_int_code;             /* 0x086 */
 760     uint16_t        svc_ilen;                 /* 0x088 */
 761     uint16_t        svc_code;                 /* 0x08a */
 762     uint16_t        pgm_ilen;                 /* 0x08c */
 763     uint16_t        pgm_code;                 /* 0x08e */
 764     uint32_t        data_exc_code;            /* 0x090 */
 765     uint16_t        mon_class_num;            /* 0x094 */
 766     uint16_t        per_perc_atmid;           /* 0x096 */
 767     uint64_t        per_address;              /* 0x098 */
 768     uint8_t         exc_access_id;            /* 0x0a0 */
 769     uint8_t         per_access_id;            /* 0x0a1 */
 770     uint8_t         op_access_id;             /* 0x0a2 */
 771     uint8_t         ar_access_id;             /* 0x0a3 */
 772     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 773     uint64_t        trans_exc_code;           /* 0x0a8 */
 774     uint64_t        monitor_code;             /* 0x0b0 */
 775     uint16_t        subchannel_id;            /* 0x0b8 */
 776     uint16_t        subchannel_nr;            /* 0x0ba */
 777     uint32_t        io_int_parm;              /* 0x0bc */
 778     uint32_t        io_int_word;              /* 0x0c0 */
 779     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 780     uint32_t        stfl_fac_list;            /* 0x0c8 */
 781     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 782     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 783     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 784     uint32_t        external_damage_code;     /* 0x0f4 */
 785     uint64_t        failing_storage_address;  /* 0x0f8 */
 786     uint8_t         pad6[0x110-0x100];        /* 0x100 */
 787     uint64_t        per_breaking_event_addr;  /* 0x110 */
 788     uint8_t         pad7[0x120-0x118];        /* 0x118 */
 789     PSW             restart_old_psw;          /* 0x120 */
 790     PSW             external_old_psw;         /* 0x130 */
 791     PSW             svc_old_psw;              /* 0x140 */
 792     PSW             program_old_psw;          /* 0x150 */
 793     PSW             mcck_old_psw;             /* 0x160 */
 794     PSW             io_old_psw;               /* 0x170 */
 795     uint8_t         pad8[0x1a0-0x180];        /* 0x180 */
 796     PSW             restart_new_psw;          /* 0x1a0 */
 797     PSW             external_new_psw;         /* 0x1b0 */
 798     PSW             svc_new_psw;              /* 0x1c0 */
 799     PSW             program_new_psw;          /* 0x1d0 */
 800     PSW             mcck_new_psw;             /* 0x1e0 */
 801     PSW             io_new_psw;               /* 0x1f0 */
 802     PSW             return_psw;               /* 0x200 */
 803     uint8_t         irb[64];                  /* 0x210 */
 804     uint64_t        sync_enter_timer;         /* 0x250 */
 805     uint64_t        async_enter_timer;        /* 0x258 */
 806     uint64_t        exit_timer;               /* 0x260 */
 807     uint64_t        last_update_timer;        /* 0x268 */
 808     uint64_t        user_timer;               /* 0x270 */
 809     uint64_t        system_timer;             /* 0x278 */
 810     uint64_t        last_update_clock;        /* 0x280 */
 811     uint64_t        steal_clock;              /* 0x288 */
 812     PSW             return_mcck_psw;          /* 0x290 */
 813     uint8_t         pad9[0xc00-0x2a0];        /* 0x2a0 */
 814     /* System info area */
 815     uint64_t        save_area[16];            /* 0xc00 */
 816     uint8_t         pad10[0xd40-0xc80];       /* 0xc80 */
 817     uint64_t        kernel_stack;             /* 0xd40 */
 818     uint64_t        thread_info;              /* 0xd48 */
 819     uint64_t        async_stack;              /* 0xd50 */
 820     uint64_t        kernel_asce;              /* 0xd58 */
 821     uint64_t        user_asce;                /* 0xd60 */
 822     uint64_t        panic_stack;              /* 0xd68 */
 823     uint64_t        user_exec_asce;           /* 0xd70 */
 824     uint8_t         pad11[0xdc0-0xd78];       /* 0xd78 */
 825
 826     /* SMP info area: defined by DJB */
 827     uint64_t        clock_comparator;         /* 0xdc0 */
 828     uint64_t        ext_call_fast;            /* 0xdc8 */
 829     uint64_t        percpu_offset;            /* 0xdd0 */
 830     uint64_t        current_task;             /* 0xdd8 */
 831     uint32_t        softirq_pending;          /* 0xde0 */
 832     uint32_t        pad_0x0de4;               /* 0xde4 */
 833     uint64_t        int_clock;                /* 0xde8 */
 834     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 835
 836     /* 0xe00 is used as indicator for dump tools */
 837     /* whether the kernel died with panic() or not */
 838     uint32_t        panic_magic;              /* 0xe00 */
 839
 840     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 841
 842     /* 64 bit extparam used for pfault, diag 250 etc  */
 843     uint64_t        ext_params2;               /* 0x11B8 */
 844
 845     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 846
 847     /* System info area */
 848
 849     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 850     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 851     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 852     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 853     uint32_t        prefixreg_save_area;       /* 0x1318 */
 854     uint32_t        fpt_creg_save_area;        /* 0x131c */
 855     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 856     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 857     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 858     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 859     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 860     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 861     uint64_t        cregs_save_area[16];       /* 0x1380 */
 862
 863     /* align to the top of the prefix area */
 864
 865     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 866 } QEMU_PACKED LowCore;
 867
 868 /* STSI */
 869 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 870 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 871 #define STSI_LEVEL_1            0x0000000010000000ULL
 872 #define STSI_LEVEL_2            0x0000000020000000ULL
 873 #define STSI_LEVEL_3            0x0000000030000000ULL
 874 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 875 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 876 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 877 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 878
 879 /* Basic Machine Configuration */
 880 struct sysib_111 {
 881     uint32_t res1[8];
 882     uint8_t  manuf[16];
 883     uint8_t  type[4];
 884     uint8_t  res2[12];
 885     uint8_t  model[16];
 886     uint8_t  sequence[16];
 887     uint8_t  plant[4];
 888     uint8_t  res3[156];
 889 };
 890
 891 /* Basic Machine CPU */
 892 struct sysib_121 {
 893     uint32_t res1[80];
 894     uint8_t  sequence[16];
 895     uint8_t  plant[4];
 896     uint8_t  res2[2];
 897     uint16_t cpu_addr;
 898     uint8_t  res3[152];
 899 };
 900
 901 /* Basic Machine CPUs */
 902 struct sysib_122 {
 903     uint8_t res1[32];
 904     uint32_t capability;
 905     uint16_t total_cpus;
 906     uint16_t active_cpus;
 907     uint16_t standby_cpus;
 908     uint16_t reserved_cpus;
 909     uint16_t adjustments[2026];
 910 };
 911
 912 /* LPAR CPU */
 913 struct sysib_221 {
 914     uint32_t res1[80];
 915     uint8_t  sequence[16];
 916     uint8_t  plant[4];
 917     uint16_t cpu_id;
 918     uint16_t cpu_addr;
 919     uint8_t  res3[152];
 920 };
 921
 922 /* LPAR CPUs */
 923 struct sysib_222 {
 924     uint32_t res1[32];
 925     uint16_t lpar_num;
 926     uint8_t  res2;
 927     uint8_t  lcpuc;
 928     uint16_t total_cpus;
 929     uint16_t conf_cpus;
 930     uint16_t standby_cpus;
 931     uint16_t reserved_cpus;
 932     uint8_t  name[8];
 933     uint32_t caf;
 934     uint8_t  res3[16];
 935     uint16_t dedicated_cpus;
 936     uint16_t shared_cpus;
 937     uint8_t  res4[180];
 938 };
 939
 940 /* VM CPUs */
 941 struct sysib_322 {
 942     uint8_t  res1[31];
 943     uint8_t  count;
 944     struct {
 945         uint8_t  res2[4];
 946         uint16_t total_cpus;
 947         uint16_t conf_cpus;
 948         uint16_t standby_cpus;
 949         uint16_t reserved_cpus;
 950         uint8_t  name[8];
 951         uint32_t caf;
 952         uint8_t  cpi[16];
 953         uint8_t res5[3];
 954         uint8_t ext_name_encoding;
 955         uint32_t res3;
 956         uint8_t uuid[16];
 957     } vm[8];
 958     uint8_t res4[1504];
 959     uint8_t ext_names[8][256];
 960 };
 961
 962 /* MMU defines */
 963 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 964 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 965 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 966 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 967 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 968 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 969 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 970 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 971 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 972 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 973 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 974 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 975
 976 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 977 #define _REGION_ENTRY_RO        0x200     /* region/segment protection bit    */
 978 #define _REGION_ENTRY_TF        0xc0      /* region/segment table offset      */
 979 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 980 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 981 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 982 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 983 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 984 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 985
 986 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 987 #define _SEGMENT_ENTRY_FC       0x400     /* format control                   */
 988 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 989 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 990
 991 #define _PAGE_RO        0x200            /* HW read-only bit  */
 992 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 993 #define _PAGE_RES0      0x800            /* bit must be zero  */
 994
 995 #define SK_C                    (0x1 << 1)
 996 #define SK_R                    (0x1 << 2)
 997 #define SK_F                    (0x1 << 3)
 998 #define SK_ACC_MASK             (0xf << 4)
 999
1000 /* SIGP order codes */
1001 #define SIGP_SENSE             0x01
1002 #define SIGP_EXTERNAL_CALL     0x02
1003 #define SIGP_EMERGENCY         0x03
1004 #define SIGP_START             0x04
1005 #define SIGP_STOP              0x05
1006 #define SIGP_RESTART           0x06
1007 #define SIGP_STOP_STORE_STATUS 0x09
1008 #define SIGP_INITIAL_CPU_RESET 0x0b
1009 #define SIGP_CPU_RESET         0x0c
1010 #define SIGP_SET_PREFIX        0x0d
1011 #define SIGP_STORE_STATUS_ADDR 0x0e
1012 #define SIGP_SET_ARCH          0x12
1013 #define SIGP_STORE_ADTL_STATUS 0x17
1014
1015 /* SIGP condition codes */
1016 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
1017 #define SIGP_CC_STATUS_STORED       1
1018 #define SIGP_CC_BUSY                2
1019 #define SIGP_CC_NOT_OPERATIONAL     3
1020
1021 /* SIGP status bits */
1022 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
1023 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
1024 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
1025 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
1026 #define SIGP_STAT_STOPPED           0x00000040UL
1027 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
1028 #define SIGP_STAT_CHECK_STOP        0x00000010UL
1029 #define SIGP_STAT_INOPERATIVE       0x00000004UL
1030 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
1031 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
1032
1033 /* SIGP SET ARCHITECTURE modes */
1034 #define SIGP_MODE_ESA_S390 0
1035 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
1036 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
1037
1038 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
1039 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
1040                   target_ulong *raddr, int *flags, bool exc);
1041 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
1042 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
1043                  uint64_t vr);
1044 void s390_cpu_recompute_watchpoints(CPUState *cs);
1045
1046 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
1047                          int len, bool is_write);
1048
1049 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len)    \
1050         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
1051 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len)       \
1052         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
1053 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len)   \
1054         s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
1055
1056 /* The value of the TOD clock for 1.1.1970. */
1057 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
1058
1059 /* Converts ns to s390's clock format */
1060 static inline uint64_t time2tod(uint64_t ns) {
1061     return (ns << 9) / 125;
1062 }
1063
1064 /* Converts s390's clock format to ns */
1065 static inline uint64_t tod2time(uint64_t t) {
1066     return (t * 125) >> 9;
1067 }
1068
1069 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
1070                                   uint64_t param64)
1071 {
1072     CPUS390XState *env = &cpu->env;
1073
1074     if (env->ext_index == MAX_EXT_QUEUE - 1) {
1075         /* ugh - can't queue anymore. Let's drop. */
1076         return;
1077     }
1078
1079     env->ext_index++;
1080     assert(env->ext_index < MAX_EXT_QUEUE);
1081
1082     env->ext_queue[env->ext_index].code = code;
1083     env->ext_queue[env->ext_index].param = param;
1084     env->ext_queue[env->ext_index].param64 = param64;
1085
1086     env->pending_int |= INTERRUPT_EXT;
1087     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1088 }
1089
1090 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
1091                                  uint16_t subchannel_number,
1092                                  uint32_t io_int_parm, uint32_t io_int_word)
1093 {
1094     CPUS390XState *env = &cpu->env;
1095     int isc = IO_INT_WORD_ISC(io_int_word);
1096
1097     if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1098         /* ugh - can't queue anymore. Let's drop. */
1099         return;
1100     }
1101
1102     env->io_index[isc]++;
1103     assert(env->io_index[isc] < MAX_IO_QUEUE);
1104
1105     env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1106     env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1107     env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1108     env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1109
1110     env->pending_int |= INTERRUPT_IO;
1111     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1112 }
1113
1114 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1115 {
1116     CPUS390XState *env = &cpu->env;
1117
1118     if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1119         /* ugh - can't queue anymore. Let's drop. */
1120         return;
1121     }
1122
1123     env->mchk_index++;
1124     assert(env->mchk_index < MAX_MCHK_QUEUE);
1125
1126     env->mchk_queue[env->mchk_index].type = 1;
1127
1128     env->pending_int |= INTERRUPT_MCHK;
1129     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1130 }
1131
1132 /* from s390-virtio-ccw */
1133 #define MEM_SECTION_SIZE             0x10000000UL
1134 #define MAX_AVAIL_SLOTS              32
1135
1136 /* fpu_helper.c */
1137 uint32_t set_cc_nz_f32(float32 v);
1138 uint32_t set_cc_nz_f64(float64 v);
1139 uint32_t set_cc_nz_f128(float128 v);
1140
1141 /* misc_helper.c */
1142 #ifndef CONFIG_USER_ONLY
1143 int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
1144 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1145 #endif
1146 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1147 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1148                                      uintptr_t retaddr);
1149
1150 #ifdef CONFIG_KVM
1151 void kvm_s390_io_interrupt(uint16_t subchannel_id,
1152                            uint16_t subchannel_nr, uint32_t io_int_parm,
1153                            uint32_t io_int_word);
1154 void kvm_s390_crw_mchk(void);
1155 void kvm_s390_enable_css_support(S390CPU *cpu);
1156 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1157                                     int vq, bool assign);
1158 int kvm_s390_cpu_restart(S390CPU *cpu);
1159 int kvm_s390_get_memslot_count(KVMState *s);
1160 void kvm_s390_cmma_reset(void);
1161 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1162 void kvm_s390_reset_vcpu(S390CPU *cpu);
1163 int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1164 void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1165 int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1166 void kvm_s390_crypto_reset(void);
1167 #else
1168 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1169                                         uint16_t subchannel_nr,
1170                                         uint32_t io_int_parm,
1171                                         uint32_t io_int_word)
1172 {
1173 }
1174 static inline void kvm_s390_crw_mchk(void)
1175 {
1176 }
1177 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1178 {
1179 }
1180 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1181                                                   uint32_t sch, int vq,
1182                                                   bool assign)
1183 {
1184     return -ENOSYS;
1185 }
1186 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1187 {
1188     return -ENOSYS;
1189 }
1190 static inline void kvm_s390_cmma_reset(void)
1191 {
1192 }
1193 static inline int kvm_s390_get_memslot_count(KVMState *s)
1194 {
1195   return MAX_AVAIL_SLOTS;
1196 }
1197 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1198 {
1199     return -ENOSYS;
1200 }
1201 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1202 {
1203 }
1204 static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1205                                          uint64_t *hw_limit)
1206 {
1207     return 0;
1208 }
1209 static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1210 {
1211 }
1212 static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1213 {
1214     return 0;
1215 }
1216 static inline void kvm_s390_crypto_reset(void)
1217 {
1218 }
1219 #endif
1220
1221 static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1222 {
1223     if (kvm_enabled()) {
1224         return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1225     }
1226     return 0;
1227 }
1228
1229 static inline void s390_cmma_reset(void)
1230 {
1231     if (kvm_enabled()) {
1232         kvm_s390_cmma_reset();
1233     }
1234 }
1235
1236 static inline int s390_cpu_restart(S390CPU *cpu)
1237 {
1238     if (kvm_enabled()) {
1239         return kvm_s390_cpu_restart(cpu);
1240     }
1241     return -ENOSYS;
1242 }
1243
1244 static inline int s390_get_memslot_count(KVMState *s)
1245 {
1246     if (kvm_enabled()) {
1247         return kvm_s390_get_memslot_count(s);
1248     } else {
1249         return MAX_AVAIL_SLOTS;
1250     }
1251 }
1252
1253 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1254                        uint32_t io_int_parm, uint32_t io_int_word);
1255 void s390_crw_mchk(void);
1256
1257 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1258                                               uint32_t sch_id, int vq,
1259                                               bool assign)
1260 {
1261     return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1262 }
1263
1264 static inline void s390_crypto_reset(void)
1265 {
1266     if (kvm_enabled()) {
1267         kvm_s390_crypto_reset();
1268     }
1269 }
1270
1271 #ifdef CONFIG_KVM
1272 static inline bool vregs_needed(void *opaque)
1273 {
1274     if (kvm_enabled()) {
1275         return kvm_check_extension(kvm_state, KVM_CAP_S390_VECTOR_REGISTERS);
1276     }
1277     return 0;
1278 }
1279 #else
1280 static inline bool vregs_needed(void *opaque)
1281 {
1282     return 0;
1283 }
1284 #endif
1285
1286 /* machine check interruption code */
1287
1288 /* subclasses */
1289 #define MCIC_SC_SD 0x8000000000000000ULL
1290 #define MCIC_SC_PD 0x4000000000000000ULL
1291 #define MCIC_SC_SR 0x2000000000000000ULL
1292 #define MCIC_SC_CD 0x0800000000000000ULL
1293 #define MCIC_SC_ED 0x0400000000000000ULL
1294 #define MCIC_SC_DG 0x0100000000000000ULL
1295 #define MCIC_SC_W  0x0080000000000000ULL
1296 #define MCIC_SC_CP 0x0040000000000000ULL
1297 #define MCIC_SC_SP 0x0020000000000000ULL
1298 #define MCIC_SC_CK 0x0010000000000000ULL
1299
1300 /* subclass modifiers */
1301 #define MCIC_SCM_B  0x0002000000000000ULL
1302 #define MCIC_SCM_DA 0x0000000020000000ULL
1303 #define MCIC_SCM_AP 0x0000000000080000ULL
1304
1305 /* storage errors */
1306 #define MCIC_SE_SE 0x0000800000000000ULL
1307 #define MCIC_SE_SC 0x0000400000000000ULL
1308 #define MCIC_SE_KE 0x0000200000000000ULL
1309 #define MCIC_SE_DS 0x0000100000000000ULL
1310 #define MCIC_SE_IE 0x0000000080000000ULL
1311
1312 /* validity bits */
1313 #define MCIC_VB_WP 0x0000080000000000ULL
1314 #define MCIC_VB_MS 0x0000040000000000ULL
1315 #define MCIC_VB_PM 0x0000020000000000ULL
1316 #define MCIC_VB_IA 0x0000010000000000ULL
1317 #define MCIC_VB_FA 0x0000008000000000ULL
1318 #define MCIC_VB_VR 0x0000004000000000ULL
1319 #define MCIC_VB_EC 0x0000002000000000ULL
1320 #define MCIC_VB_FP 0x0000001000000000ULL
1321 #define MCIC_VB_GR 0x0000000800000000ULL
1322 #define MCIC_VB_CR 0x0000000400000000ULL
1323 #define MCIC_VB_ST 0x0000000100000000ULL
1324 #define MCIC_VB_AR 0x0000000040000000ULL
1325 #define MCIC_VB_PR 0x0000000000200000ULL
1326 #define MCIC_VB_FC 0x0000000000100000ULL
1327 #define MCIC_VB_CT 0x0000000000020000ULL
1328 #define MCIC_VB_CC 0x0000000000010000ULL
1329
1330 #endif