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i8257: rename struct dma_regs to I8257Regs
[qemu/ar7.git] / hw / usb / hcd-uhci.c
blob5ccfb8395ab9a14bbeeb2ced5bbef561e20d125e
1 /*
2 * USB UHCI controller emulation
3 *
4 * Copyright (c) 2005 Fabrice Bellard
5 *
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * THE SOFTWARE.
27 */
28 #include "qemu/osdep.h"
29 #include "hw/hw.h"
30 #include "hw/usb.h"
31 #include "hw/usb/uhci-regs.h"
32 #include "hw/pci/pci.h"
33 #include "qemu/timer.h"
34 #include "qemu/iov.h"
35 #include "sysemu/dma.h"
36 #include "trace.h"
37 #include "qemu/main-loop.h"
38
39 #define FRAME_TIMER_FREQ 1000
40
41 #define FRAME_MAX_LOOPS 256
42
43 /* Must be large enough to handle 10 frame delay for initial isoc requests */
44 #define QH_VALID 32
45
46 #define MAX_FRAMES_PER_TICK (QH_VALID / 2)
47
48 #define NB_PORTS 2
49
50 enum {
51 TD_RESULT_STOP_FRAME = 10,
52 TD_RESULT_COMPLETE,
53 TD_RESULT_NEXT_QH,
54 TD_RESULT_ASYNC_START,
55 TD_RESULT_ASYNC_CONT,
56 };
57
58 typedef struct UHCIState UHCIState;
59 typedef struct UHCIAsync UHCIAsync;
60 typedef struct UHCIQueue UHCIQueue;
61 typedef struct UHCIInfo UHCIInfo;
62 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass;
63
64 struct UHCIInfo {
65 const char *name;
66 uint16_t vendor_id;
67 uint16_t device_id;
68 uint8_t revision;
69 uint8_t irq_pin;
70 void (*realize)(PCIDevice *dev, Error **errp);
71 bool unplug;
72 };
73
74 struct UHCIPCIDeviceClass {
75 PCIDeviceClass parent_class;
76 UHCIInfo info;
77 };
78
79 /*
80 * Pending async transaction.
81 * 'packet' must be the first field because completion
82 * handler does "(UHCIAsync *) pkt" cast.
83 */
84
85 struct UHCIAsync {
86 USBPacket packet;
87 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */
88 uint8_t *buf;
89 UHCIQueue *queue;
90 QTAILQ_ENTRY(UHCIAsync) next;
91 uint32_t td_addr;
92 uint8_t done;
93 };
94
95 struct UHCIQueue {
96 uint32_t qh_addr;
97 uint32_t token;
98 UHCIState *uhci;
99 USBEndpoint *ep;
100 QTAILQ_ENTRY(UHCIQueue) next;
101 QTAILQ_HEAD(asyncs_head, UHCIAsync) asyncs;
102 int8_t valid;
103 };
104
105 typedef struct UHCIPort {
106 USBPort port;
107 uint16_t ctrl;
108 } UHCIPort;
109
110 struct UHCIState {
111 PCIDevice dev;
112 MemoryRegion io_bar;
113 USBBus bus; /* Note unused when we're a companion controller */
114 uint16_t cmd; /* cmd register */
115 uint16_t status;
116 uint16_t intr; /* interrupt enable register */
117 uint16_t frnum; /* frame number */
118 uint32_t fl_base_addr; /* frame list base address */
119 uint8_t sof_timing;
120 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
121 int64_t expire_time;
122 QEMUTimer *frame_timer;
123 QEMUBH *bh;
124 uint32_t frame_bytes;
125 uint32_t frame_bandwidth;
126 bool completions_only;
127 UHCIPort ports[NB_PORTS];
128
129 /* Interrupts that should be raised at the end of the current frame. */
130 uint32_t pending_int_mask;
131
132 /* Active packets */
133 QTAILQ_HEAD(, UHCIQueue) queues;
134 uint8_t num_ports_vmstate;
135
136 /* Properties */
137 char *masterbus;
138 uint32_t firstport;
139 uint32_t maxframes;
140 };
141
142 typedef struct UHCI_TD {
143 uint32_t link;
144 uint32_t ctrl; /* see TD_CTRL_xxx */
145 uint32_t token;
146 uint32_t buffer;
147 } UHCI_TD;
148
149 typedef struct UHCI_QH {
150 uint32_t link;
151 uint32_t el_link;
152 } UHCI_QH;
153
154 static void uhci_async_cancel(UHCIAsync *async);
155 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td);
156 static void uhci_resume(void *opaque);
157
158 #define TYPE_UHCI "pci-uhci-usb"
159 #define UHCI(obj) OBJECT_CHECK(UHCIState, (obj), TYPE_UHCI)
160
161 static inline int32_t uhci_queue_token(UHCI_TD *td)
162 {
163 if ((td->token & (0xf << 15)) == 0) {
164 /* ctrl ep, cover ep and dev, not pid! */
165 return td->token & 0x7ff00;
166 } else {
167 /* covers ep, dev, pid -> identifies the endpoint */
168 return td->token & 0x7ffff;
169 }
170 }
171
172 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td,
173 USBEndpoint *ep)
174 {
175 UHCIQueue *queue;
176
177 queue = g_new0(UHCIQueue, 1);
178 queue->uhci = s;
179 queue->qh_addr = qh_addr;
180 queue->token = uhci_queue_token(td);
181 queue->ep = ep;
182 QTAILQ_INIT(&queue->asyncs);
183 QTAILQ_INSERT_HEAD(&s->queues, queue, next);
184 queue->valid = QH_VALID;
185 trace_usb_uhci_queue_add(queue->token);
186 return queue;
187 }
188
189 static void uhci_queue_free(UHCIQueue *queue, const char *reason)
190 {
191 UHCIState *s = queue->uhci;
192 UHCIAsync *async;
193
194 while (!QTAILQ_EMPTY(&queue->asyncs)) {
195 async = QTAILQ_FIRST(&queue->asyncs);
196 uhci_async_cancel(async);
197 }
198 usb_device_ep_stopped(queue->ep->dev, queue->ep);
199
200 trace_usb_uhci_queue_del(queue->token, reason);
201 QTAILQ_REMOVE(&s->queues, queue, next);
202 g_free(queue);
203 }
204
205 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td)
206 {
207 uint32_t token = uhci_queue_token(td);
208 UHCIQueue *queue;
209
210 QTAILQ_FOREACH(queue, &s->queues, next) {
211 if (queue->token == token) {
212 return queue;
213 }
214 }
215 return NULL;
216 }
217
218 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td,
219 uint32_t td_addr, bool queuing)
220 {
221 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs);
222 uint32_t queue_token_addr = (queue->token >> 8) & 0x7f;
223
224 return queue->qh_addr == qh_addr &&
225 queue->token == uhci_queue_token(td) &&
226 queue_token_addr == queue->ep->dev->addr &&
227 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL ||
228 first->td_addr == td_addr);
229 }
230
231 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr)
232 {
233 UHCIAsync *async = g_new0(UHCIAsync, 1);
234
235 async->queue = queue;
236 async->td_addr = td_addr;
237 usb_packet_init(&async->packet);
238 trace_usb_uhci_packet_add(async->queue->token, async->td_addr);
239
240 return async;
241 }
242
243 static void uhci_async_free(UHCIAsync *async)
244 {
245 trace_usb_uhci_packet_del(async->queue->token, async->td_addr);
246 usb_packet_cleanup(&async->packet);
247 if (async->buf != async->static_buf) {
248 g_free(async->buf);
249 }
250 g_free(async);
251 }
252
253 static void uhci_async_link(UHCIAsync *async)
254 {
255 UHCIQueue *queue = async->queue;
256 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next);
257 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr);
258 }
259
260 static void uhci_async_unlink(UHCIAsync *async)
261 {
262 UHCIQueue *queue = async->queue;
263 QTAILQ_REMOVE(&queue->asyncs, async, next);
264 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr);
265 }
266
267 static void uhci_async_cancel(UHCIAsync *async)
268 {
269 uhci_async_unlink(async);
270 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr,
271 async->done);
272 if (!async->done)
273 usb_cancel_packet(&async->packet);
274 uhci_async_free(async);
275 }
276
277 /*
278 * Mark all outstanding async packets as invalid.
279 * This is used for canceling them when TDs are removed by the HCD.
280 */
281 static void uhci_async_validate_begin(UHCIState *s)
282 {
283 UHCIQueue *queue;
284
285 QTAILQ_FOREACH(queue, &s->queues, next) {
286 queue->valid--;
287 }
288 }
289
290 /*
291 * Cancel async packets that are no longer valid
292 */
293 static void uhci_async_validate_end(UHCIState *s)
294 {
295 UHCIQueue *queue, *n;
296
297 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
298 if (!queue->valid) {
299 uhci_queue_free(queue, "validate-end");
300 }
301 }
302 }
303
304 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev)
305 {
306 UHCIQueue *queue, *n;
307
308 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
309 if (queue->ep->dev == dev) {
310 uhci_queue_free(queue, "cancel-device");
311 }
312 }
313 }
314
315 static void uhci_async_cancel_all(UHCIState *s)
316 {
317 UHCIQueue *queue, *nq;
318
319 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) {
320 uhci_queue_free(queue, "cancel-all");
321 }
322 }
323
324 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr)
325 {
326 UHCIQueue *queue;
327 UHCIAsync *async;
328
329 QTAILQ_FOREACH(queue, &s->queues, next) {
330 QTAILQ_FOREACH(async, &queue->asyncs, next) {
331 if (async->td_addr == td_addr) {
332 return async;
333 }
334 }
335 }
336 return NULL;
337 }
338
339 static void uhci_update_irq(UHCIState *s)
340 {
341 int level;
342 if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
343 ((s->status2 & 2) && (s->intr & (1 << 3))) ||
344 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
345 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) ||
346 (s->status & UHCI_STS_HSERR) ||
347 (s->status & UHCI_STS_HCPERR)) {
348 level = 1;
349 } else {
350 level = 0;
351 }
352 pci_set_irq(&s->dev, level);
353 }
354
355 static void uhci_reset(DeviceState *dev)
356 {
357 PCIDevice *d = PCI_DEVICE(dev);
358 UHCIState *s = UHCI(d);
359 uint8_t *pci_conf;
360 int i;
361 UHCIPort *port;
362
363 trace_usb_uhci_reset();
364
365 pci_conf = s->dev.config;
366
367 pci_conf[0x6a] = 0x01; /* usb clock */
368 pci_conf[0x6b] = 0x00;
369 s->cmd = 0;
370 s->status = UHCI_STS_HCHALTED;
371 s->status2 = 0;
372 s->intr = 0;
373 s->fl_base_addr = 0;
374 s->sof_timing = 64;
375
376 for(i = 0; i < NB_PORTS; i++) {
377 port = &s->ports[i];
378 port->ctrl = 0x0080;
379 if (port->port.dev && port->port.dev->attached) {
380 usb_port_reset(&port->port);
381 }
382 }
383
384 uhci_async_cancel_all(s);
385 qemu_bh_cancel(s->bh);
386 uhci_update_irq(s);
387 }
388
389 static const VMStateDescription vmstate_uhci_port = {
390 .name = "uhci port",
391 .version_id = 1,
392 .minimum_version_id = 1,
393 .fields = (VMStateField[]) {
394 VMSTATE_UINT16(ctrl, UHCIPort),
395 VMSTATE_END_OF_LIST()
396 }
397 };
398
399 static int uhci_post_load(void *opaque, int version_id)
400 {
401 UHCIState *s = opaque;
402
403 if (version_id < 2) {
404 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
405 (get_ticks_per_sec() / FRAME_TIMER_FREQ);
406 }
407 return 0;
408 }
409
410 static const VMStateDescription vmstate_uhci = {
411 .name = "uhci",
412 .version_id = 3,
413 .minimum_version_id = 1,
414 .post_load = uhci_post_load,
415 .fields = (VMStateField[]) {
416 VMSTATE_PCI_DEVICE(dev, UHCIState),
417 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState),
418 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
419 vmstate_uhci_port, UHCIPort),
420 VMSTATE_UINT16(cmd, UHCIState),
421 VMSTATE_UINT16(status, UHCIState),
422 VMSTATE_UINT16(intr, UHCIState),
423 VMSTATE_UINT16(frnum, UHCIState),
424 VMSTATE_UINT32(fl_base_addr, UHCIState),
425 VMSTATE_UINT8(sof_timing, UHCIState),
426 VMSTATE_UINT8(status2, UHCIState),
427 VMSTATE_TIMER_PTR(frame_timer, UHCIState),
428 VMSTATE_INT64_V(expire_time, UHCIState, 2),
429 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3),
430 VMSTATE_END_OF_LIST()
431 }
432 };
433
434 static void uhci_port_write(void *opaque, hwaddr addr,
435 uint64_t val, unsigned size)
436 {
437 UHCIState *s = opaque;
438
439 trace_usb_uhci_mmio_writew(addr, val);
440
441 switch(addr) {
442 case 0x00:
443 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
444 /* start frame processing */
445 trace_usb_uhci_schedule_start();
446 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
447 (get_ticks_per_sec() / FRAME_TIMER_FREQ);
448 timer_mod(s->frame_timer, s->expire_time);
449 s->status &= ~UHCI_STS_HCHALTED;
450 } else if (!(val & UHCI_CMD_RS)) {
451 s->status |= UHCI_STS_HCHALTED;
452 }
453 if (val & UHCI_CMD_GRESET) {
454 UHCIPort *port;
455 int i;
456
457 /* send reset on the USB bus */
458 for(i = 0; i < NB_PORTS; i++) {
459 port = &s->ports[i];
460 usb_device_reset(port->port.dev);
461 }
462 uhci_reset(DEVICE(s));
463 return;
464 }
465 if (val & UHCI_CMD_HCRESET) {
466 uhci_reset(DEVICE(s));
467 return;
468 }
469 s->cmd = val;
470 if (val & UHCI_CMD_EGSM) {
471 if ((s->ports[0].ctrl & UHCI_PORT_RD) ||
472 (s->ports[1].ctrl & UHCI_PORT_RD)) {
473 uhci_resume(s);
474 }
475 }
476 break;
477 case 0x02:
478 s->status &= ~val;
479 /* XXX: the chip spec is not coherent, so we add a hidden
480 register to distinguish between IOC and SPD */
481 if (val & UHCI_STS_USBINT)
482 s->status2 = 0;
483 uhci_update_irq(s);
484 break;
485 case 0x04:
486 s->intr = val;
487 uhci_update_irq(s);
488 break;
489 case 0x06:
490 if (s->status & UHCI_STS_HCHALTED)
491 s->frnum = val & 0x7ff;
492 break;
493 case 0x08:
494 s->fl_base_addr &= 0xffff0000;
495 s->fl_base_addr |= val & ~0xfff;
496 break;
497 case 0x0a:
498 s->fl_base_addr &= 0x0000ffff;
499 s->fl_base_addr |= (val << 16);
500 break;
501 case 0x0c:
502 s->sof_timing = val & 0xff;
503 break;
504 case 0x10 ... 0x1f:
505 {
506 UHCIPort *port;
507 USBDevice *dev;
508 int n;
509
510 n = (addr >> 1) & 7;
511 if (n >= NB_PORTS)
512 return;
513 port = &s->ports[n];
514 dev = port->port.dev;
515 if (dev && dev->attached) {
516 /* port reset */
517 if ( (val & UHCI_PORT_RESET) &&
518 !(port->ctrl & UHCI_PORT_RESET) ) {
519 usb_device_reset(dev);
520 }
521 }
522 port->ctrl &= UHCI_PORT_READ_ONLY;
523 /* enabled may only be set if a device is connected */
524 if (!(port->ctrl & UHCI_PORT_CCS)) {
525 val &= ~UHCI_PORT_EN;
526 }
527 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY);
528 /* some bits are reset when a '1' is written to them */
529 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR);
530 }
531 break;
532 }
533 }
534
535 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size)
536 {
537 UHCIState *s = opaque;
538 uint32_t val;
539
540 switch(addr) {
541 case 0x00:
542 val = s->cmd;
543 break;
544 case 0x02:
545 val = s->status;
546 break;
547 case 0x04:
548 val = s->intr;
549 break;
550 case 0x06:
551 val = s->frnum;
552 break;
553 case 0x08:
554 val = s->fl_base_addr & 0xffff;
555 break;
556 case 0x0a:
557 val = (s->fl_base_addr >> 16) & 0xffff;
558 break;
559 case 0x0c:
560 val = s->sof_timing;
561 break;
562 case 0x10 ... 0x1f:
563 {
564 UHCIPort *port;
565 int n;
566 n = (addr >> 1) & 7;
567 if (n >= NB_PORTS)
568 goto read_default;
569 port = &s->ports[n];
570 val = port->ctrl;
571 }
572 break;
573 default:
574 read_default:
575 val = 0xff7f; /* disabled port */
576 break;
577 }
578
579 trace_usb_uhci_mmio_readw(addr, val);
580
581 return val;
582 }
583
584 /* signal resume if controller suspended */
585 static void uhci_resume (void *opaque)
586 {
587 UHCIState *s = (UHCIState *)opaque;
588
589 if (!s)
590 return;
591
592 if (s->cmd & UHCI_CMD_EGSM) {
593 s->cmd |= UHCI_CMD_FGR;
594 s->status |= UHCI_STS_RD;
595 uhci_update_irq(s);
596 }
597 }
598
599 static void uhci_attach(USBPort *port1)
600 {
601 UHCIState *s = port1->opaque;
602 UHCIPort *port = &s->ports[port1->index];
603
604 /* set connect status */
605 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC;
606
607 /* update speed */
608 if (port->port.dev->speed == USB_SPEED_LOW) {
609 port->ctrl |= UHCI_PORT_LSDA;
610 } else {
611 port->ctrl &= ~UHCI_PORT_LSDA;
612 }
613
614 uhci_resume(s);
615 }
616
617 static void uhci_detach(USBPort *port1)
618 {
619 UHCIState *s = port1->opaque;
620 UHCIPort *port = &s->ports[port1->index];
621
622 uhci_async_cancel_device(s, port1->dev);
623
624 /* set connect status */
625 if (port->ctrl & UHCI_PORT_CCS) {
626 port->ctrl &= ~UHCI_PORT_CCS;
627 port->ctrl |= UHCI_PORT_CSC;
628 }
629 /* disable port */
630 if (port->ctrl & UHCI_PORT_EN) {
631 port->ctrl &= ~UHCI_PORT_EN;
632 port->ctrl |= UHCI_PORT_ENC;
633 }
634
635 uhci_resume(s);
636 }
637
638 static void uhci_child_detach(USBPort *port1, USBDevice *child)
639 {
640 UHCIState *s = port1->opaque;
641
642 uhci_async_cancel_device(s, child);
643 }
644
645 static void uhci_wakeup(USBPort *port1)
646 {
647 UHCIState *s = port1->opaque;
648 UHCIPort *port = &s->ports[port1->index];
649
650 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
651 port->ctrl |= UHCI_PORT_RD;
652 uhci_resume(s);
653 }
654 }
655
656 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
657 {
658 USBDevice *dev;
659 int i;
660
661 for (i = 0; i < NB_PORTS; i++) {
662 UHCIPort *port = &s->ports[i];
663 if (!(port->ctrl & UHCI_PORT_EN)) {
664 continue;
665 }
666 dev = usb_find_device(&port->port, addr);
667 if (dev != NULL) {
668 return dev;
669 }
670 }
671 return NULL;
672 }
673
674 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link)
675 {
676 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td));
677 le32_to_cpus(&td->link);
678 le32_to_cpus(&td->ctrl);
679 le32_to_cpus(&td->token);
680 le32_to_cpus(&td->buffer);
681 }
682
683 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr,
684 int status, uint32_t *int_mask)
685 {
686 uint32_t queue_token = uhci_queue_token(td);
687 int ret;
688
689 switch (status) {
690 case USB_RET_NAK:
691 td->ctrl |= TD_CTRL_NAK;
692 return TD_RESULT_NEXT_QH;
693
694 case USB_RET_STALL:
695 td->ctrl |= TD_CTRL_STALL;
696 trace_usb_uhci_packet_complete_stall(queue_token, td_addr);
697 ret = TD_RESULT_NEXT_QH;
698 break;
699
700 case USB_RET_BABBLE:
701 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL;
702 /* frame interrupted */
703 trace_usb_uhci_packet_complete_babble(queue_token, td_addr);
704 ret = TD_RESULT_STOP_FRAME;
705 break;
706
707 case USB_RET_IOERROR:
708 case USB_RET_NODEV:
709 default:
710 td->ctrl |= TD_CTRL_TIMEOUT;
711 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT);
712 trace_usb_uhci_packet_complete_error(queue_token, td_addr);
713 ret = TD_RESULT_NEXT_QH;
714 break;
715 }
716
717 td->ctrl &= ~TD_CTRL_ACTIVE;
718 s->status |= UHCI_STS_USBERR;
719 if (td->ctrl & TD_CTRL_IOC) {
720 *int_mask |= 0x01;
721 }
722 uhci_update_irq(s);
723 return ret;
724 }
725
726 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask)
727 {
728 int len = 0, max_len;
729 uint8_t pid;
730
731 max_len = ((td->token >> 21) + 1) & 0x7ff;
732 pid = td->token & 0xff;
733
734 if (td->ctrl & TD_CTRL_IOS)
735 td->ctrl &= ~TD_CTRL_ACTIVE;
736
737 if (async->packet.status != USB_RET_SUCCESS) {
738 return uhci_handle_td_error(s, td, async->td_addr,
739 async->packet.status, int_mask);
740 }
741
742 len = async->packet.actual_length;
743 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff);
744
745 /* The NAK bit may have been set by a previous frame, so clear it
746 here. The docs are somewhat unclear, but win2k relies on this
747 behavior. */
748 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
749 if (td->ctrl & TD_CTRL_IOC)
750 *int_mask |= 0x01;
751
752 if (pid == USB_TOKEN_IN) {
753 pci_dma_write(&s->dev, td->buffer, async->buf, len);
754 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
755 *int_mask |= 0x02;
756 /* short packet: do not update QH */
757 trace_usb_uhci_packet_complete_shortxfer(async->queue->token,
758 async->td_addr);
759 return TD_RESULT_NEXT_QH;
760 }
761 }
762
763 /* success */
764 trace_usb_uhci_packet_complete_success(async->queue->token,
765 async->td_addr);
766 return TD_RESULT_COMPLETE;
767 }
768
769 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr,
770 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask)
771 {
772 int ret, max_len;
773 bool spd;
774 bool queuing = (q != NULL);
775 uint8_t pid = td->token & 0xff;
776 UHCIAsync *async = uhci_async_find_td(s, td_addr);
777
778 if (async) {
779 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) {
780 assert(q == NULL || q == async->queue);
781 q = async->queue;
782 } else {
783 uhci_queue_free(async->queue, "guest re-used pending td");
784 async = NULL;
785 }
786 }
787
788 if (q == NULL) {
789 q = uhci_queue_find(s, td);
790 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) {
791 uhci_queue_free(q, "guest re-used qh");
792 q = NULL;
793 }
794 }
795
796 if (q) {
797 q->valid = QH_VALID;
798 }
799
800 /* Is active ? */
801 if (!(td->ctrl & TD_CTRL_ACTIVE)) {
802 if (async) {
803 /* Guest marked a pending td non-active, cancel the queue */
804 uhci_queue_free(async->queue, "pending td non-active");
805 }
806 /*
807 * ehci11d spec page 22: "Even if the Active bit in the TD is already
808 * cleared when the TD is fetched ... an IOC interrupt is generated"
809 */
810 if (td->ctrl & TD_CTRL_IOC) {
811 *int_mask |= 0x01;
812 }
813 return TD_RESULT_NEXT_QH;
814 }
815
816 if (async) {
817 if (queuing) {
818 /* we are busy filling the queue, we are not prepared
819 to consume completed packages then, just leave them
820 in async state */
821 return TD_RESULT_ASYNC_CONT;
822 }
823 if (!async->done) {
824 UHCI_TD last_td;
825 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs, asyncs_head);
826 /*
827 * While we are waiting for the current td to complete, the guest
828 * may have added more tds to the queue. Note we re-read the td
829 * rather then caching it, as we want to see guest made changes!
830 */
831 uhci_read_td(s, &last_td, last->td_addr);
832 uhci_queue_fill(async->queue, &last_td);
833
834 return TD_RESULT_ASYNC_CONT;
835 }
836 uhci_async_unlink(async);
837 goto done;
838 }
839
840 if (s->completions_only) {
841 return TD_RESULT_ASYNC_CONT;
842 }
843
844 /* Allocate new packet */
845 if (q == NULL) {
846 USBDevice *dev = uhci_find_device(s, (td->token >> 8) & 0x7f);
847 USBEndpoint *ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf);
848
849 if (ep == NULL) {
850 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV,
851 int_mask);
852 }
853 q = uhci_queue_new(s, qh_addr, td, ep);
854 }
855 async = uhci_async_alloc(q, td_addr);
856
857 max_len = ((td->token >> 21) + 1) & 0x7ff;
858 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0);
859 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd,
860 (td->ctrl & TD_CTRL_IOC) != 0);
861 if (max_len <= sizeof(async->static_buf)) {
862 async->buf = async->static_buf;
863 } else {
864 async->buf = g_malloc(max_len);
865 }
866 usb_packet_addbuf(&async->packet, async->buf, max_len);
867
868 switch(pid) {
869 case USB_TOKEN_OUT:
870 case USB_TOKEN_SETUP:
871 pci_dma_read(&s->dev, td->buffer, async->buf, max_len);
872 usb_handle_packet(q->ep->dev, &async->packet);
873 if (async->packet.status == USB_RET_SUCCESS) {
874 async->packet.actual_length = max_len;
875 }
876 break;
877
878 case USB_TOKEN_IN:
879 usb_handle_packet(q->ep->dev, &async->packet);
880 break;
881
882 default:
883 /* invalid pid : frame interrupted */
884 uhci_async_free(async);
885 s->status |= UHCI_STS_HCPERR;
886 uhci_update_irq(s);
887 return TD_RESULT_STOP_FRAME;
888 }
889
890 if (async->packet.status == USB_RET_ASYNC) {
891 uhci_async_link(async);
892 if (!queuing) {
893 uhci_queue_fill(q, td);
894 }
895 return TD_RESULT_ASYNC_START;
896 }
897
898 done:
899 ret = uhci_complete_td(s, td, async, int_mask);
900 uhci_async_free(async);
901 return ret;
902 }
903
904 static void uhci_async_complete(USBPort *port, USBPacket *packet)
905 {
906 UHCIAsync *async = container_of(packet, UHCIAsync, packet);
907 UHCIState *s = async->queue->uhci;
908
909 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
910 uhci_async_cancel(async);
911 return;
912 }
913
914 async->done = 1;
915 /* Force processing of this packet *now*, needed for migration */
916 s->completions_only = true;
917 qemu_bh_schedule(s->bh);
918 }
919
920 static int is_valid(uint32_t link)
921 {
922 return (link & 1) == 0;
923 }
924
925 static int is_qh(uint32_t link)
926 {
927 return (link & 2) != 0;
928 }
929
930 static int depth_first(uint32_t link)
931 {
932 return (link & 4) != 0;
933 }
934
935 /* QH DB used for detecting QH loops */
936 #define UHCI_MAX_QUEUES 128
937 typedef struct {
938 uint32_t addr[UHCI_MAX_QUEUES];
939 int count;
940 } QhDb;
941
942 static void qhdb_reset(QhDb *db)
943 {
944 db->count = 0;
945 }
946
947 /* Add QH to DB. Returns 1 if already present or DB is full. */
948 static int qhdb_insert(QhDb *db, uint32_t addr)
949 {
950 int i;
951 for (i = 0; i < db->count; i++)
952 if (db->addr[i] == addr)
953 return 1;
954
955 if (db->count >= UHCI_MAX_QUEUES)
956 return 1;
957
958 db->addr[db->count++] = addr;
959 return 0;
960 }
961
962 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td)
963 {
964 uint32_t int_mask = 0;
965 uint32_t plink = td->link;
966 UHCI_TD ptd;
967 int ret;
968
969 while (is_valid(plink)) {
970 uhci_read_td(q->uhci, &ptd, plink);
971 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) {
972 break;
973 }
974 if (uhci_queue_token(&ptd) != q->token) {
975 break;
976 }
977 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token);
978 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask);
979 if (ret == TD_RESULT_ASYNC_CONT) {
980 break;
981 }
982 assert(ret == TD_RESULT_ASYNC_START);
983 assert(int_mask == 0);
984 plink = ptd.link;
985 }
986 usb_device_flush_ep_queue(q->ep->dev, q->ep);
987 }
988
989 static void uhci_process_frame(UHCIState *s)
990 {
991 uint32_t frame_addr, link, old_td_ctrl, val, int_mask;
992 uint32_t curr_qh, td_count = 0;
993 int cnt, ret;
994 UHCI_TD td;
995 UHCI_QH qh;
996 QhDb qhdb;
997
998 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
999
1000 pci_dma_read(&s->dev, frame_addr, &link, 4);
1001 le32_to_cpus(&link);
1002
1003 int_mask = 0;
1004 curr_qh = 0;
1005
1006 qhdb_reset(&qhdb);
1007
1008 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
1009 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) {
1010 /* We've reached the usb 1.1 bandwidth, which is
1011 1280 bytes/frame, stop processing */
1012 trace_usb_uhci_frame_stop_bandwidth();
1013 break;
1014 }
1015 if (is_qh(link)) {
1016 /* QH */
1017 trace_usb_uhci_qh_load(link & ~0xf);
1018
1019 if (qhdb_insert(&qhdb, link)) {
1020 /*
1021 * We're going in circles. Which is not a bug because
1022 * HCD is allowed to do that as part of the BW management.
1023 *
1024 * Stop processing here if no transaction has been done
1025 * since we've been here last time.
1026 */
1027 if (td_count == 0) {
1028 trace_usb_uhci_frame_loop_stop_idle();
1029 break;
1030 } else {
1031 trace_usb_uhci_frame_loop_continue();
1032 td_count = 0;
1033 qhdb_reset(&qhdb);
1034 qhdb_insert(&qhdb, link);
1035 }
1036 }
1037
1038 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh));
1039 le32_to_cpus(&qh.link);
1040 le32_to_cpus(&qh.el_link);
1041
1042 if (!is_valid(qh.el_link)) {
1043 /* QH w/o elements */
1044 curr_qh = 0;
1045 link = qh.link;
1046 } else {
1047 /* QH with elements */
1048 curr_qh = link;
1049 link = qh.el_link;
1050 }
1051 continue;
1052 }
1053
1054 /* TD */
1055 uhci_read_td(s, &td, link);
1056 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token);
1057
1058 old_td_ctrl = td.ctrl;
1059 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask);
1060 if (old_td_ctrl != td.ctrl) {
1061 /* update the status bits of the TD */
1062 val = cpu_to_le32(td.ctrl);
1063 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
1064 }
1065
1066 switch (ret) {
1067 case TD_RESULT_STOP_FRAME: /* interrupted frame */
1068 goto out;
1069
1070 case TD_RESULT_NEXT_QH:
1071 case TD_RESULT_ASYNC_CONT:
1072 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf);
1073 link = curr_qh ? qh.link : td.link;
1074 continue;
1075
1076 case TD_RESULT_ASYNC_START:
1077 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf);
1078 link = curr_qh ? qh.link : td.link;
1079 continue;
1080
1081 case TD_RESULT_COMPLETE:
1082 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf);
1083 link = td.link;
1084 td_count++;
1085 s->frame_bytes += (td.ctrl & 0x7ff) + 1;
1086
1087 if (curr_qh) {
1088 /* update QH element link */
1089 qh.el_link = link;
1090 val = cpu_to_le32(qh.el_link);
1091 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val));
1092
1093 if (!depth_first(link)) {
1094 /* done with this QH */
1095 curr_qh = 0;
1096 link = qh.link;
1097 }
1098 }
1099 break;
1100
1101 default:
1102 assert(!"unknown return code");
1103 }
1104
1105 /* go to the next entry */
1106 }
1107
1108 out:
1109 s->pending_int_mask |= int_mask;
1110 }
1111
1112 static void uhci_bh(void *opaque)
1113 {
1114 UHCIState *s = opaque;
1115 uhci_process_frame(s);
1116 }
1117
1118 static void uhci_frame_timer(void *opaque)
1119 {
1120 UHCIState *s = opaque;
1121 uint64_t t_now, t_last_run;
1122 int i, frames;
1123 const uint64_t frame_t = get_ticks_per_sec() / FRAME_TIMER_FREQ;
1124
1125 s->completions_only = false;
1126 qemu_bh_cancel(s->bh);
1127
1128 if (!(s->cmd & UHCI_CMD_RS)) {
1129 /* Full stop */
1130 trace_usb_uhci_schedule_stop();
1131 timer_del(s->frame_timer);
1132 uhci_async_cancel_all(s);
1133 /* set hchalted bit in status - UHCI11D 2.1.2 */
1134 s->status |= UHCI_STS_HCHALTED;
1135 return;
1136 }
1137
1138 /* We still store expire_time in our state, for migration */
1139 t_last_run = s->expire_time - frame_t;
1140 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1141
1142 /* Process up to MAX_FRAMES_PER_TICK frames */
1143 frames = (t_now - t_last_run) / frame_t;
1144 if (frames > s->maxframes) {
1145 int skipped = frames - s->maxframes;
1146 s->expire_time += skipped * frame_t;
1147 s->frnum = (s->frnum + skipped) & 0x7ff;
1148 frames -= skipped;
1149 }
1150 if (frames > MAX_FRAMES_PER_TICK) {
1151 frames = MAX_FRAMES_PER_TICK;
1152 }
1153
1154 for (i = 0; i < frames; i++) {
1155 s->frame_bytes = 0;
1156 trace_usb_uhci_frame_start(s->frnum);
1157 uhci_async_validate_begin(s);
1158 uhci_process_frame(s);
1159 uhci_async_validate_end(s);
1160 /* The spec says frnum is the frame currently being processed, and
1161 * the guest must look at frnum - 1 on interrupt, so inc frnum now */
1162 s->frnum = (s->frnum + 1) & 0x7ff;
1163 s->expire_time += frame_t;
1164 }
1165
1166 /* Complete the previous frame(s) */
1167 if (s->pending_int_mask) {
1168 s->status2 |= s->pending_int_mask;
1169 s->status |= UHCI_STS_USBINT;
1170 uhci_update_irq(s);
1171 }
1172 s->pending_int_mask = 0;
1173
1174 timer_mod(s->frame_timer, t_now + frame_t);
1175 }
1176
1177 static const MemoryRegionOps uhci_ioport_ops = {
1178 .read = uhci_port_read,
1179 .write = uhci_port_write,
1180 .valid.min_access_size = 1,
1181 .valid.max_access_size = 4,
1182 .impl.min_access_size = 2,
1183 .impl.max_access_size = 2,
1184 .endianness = DEVICE_LITTLE_ENDIAN,
1185 };
1186
1187 static USBPortOps uhci_port_ops = {
1188 .attach = uhci_attach,
1189 .detach = uhci_detach,
1190 .child_detach = uhci_child_detach,
1191 .wakeup = uhci_wakeup,
1192 .complete = uhci_async_complete,
1193 };
1194
1195 static USBBusOps uhci_bus_ops = {
1196 };
1197
1198 static void usb_uhci_common_realize(PCIDevice *dev, Error **errp)
1199 {
1200 Error *err = NULL;
1201 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
1202 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class);
1203 UHCIState *s = UHCI(dev);
1204 uint8_t *pci_conf = s->dev.config;
1205 int i;
1206
1207 pci_conf[PCI_CLASS_PROG] = 0x00;
1208 /* TODO: reset value should be 0. */
1209 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
1210
1211 pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1);
1212
1213 if (s->masterbus) {
1214 USBPort *ports[NB_PORTS];
1215 for(i = 0; i < NB_PORTS; i++) {
1216 ports[i] = &s->ports[i].port;
1217 }
1218 usb_register_companion(s->masterbus, ports, NB_PORTS,
1219 s->firstport, s, &uhci_port_ops,
1220 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL,
1221 &err);
1222 if (err) {
1223 error_propagate(errp, err);
1224 return;
1225 }
1226 } else {
1227 usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev));
1228 for (i = 0; i < NB_PORTS; i++) {
1229 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops,
1230 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1231 }
1232 }
1233 s->bh = qemu_bh_new(uhci_bh, s);
1234 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s);
1235 s->num_ports_vmstate = NB_PORTS;
1236 QTAILQ_INIT(&s->queues);
1237
1238 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s,
1239 "uhci", 0x20);
1240
1241 /* Use region 4 for consistency with real hardware. BSD guests seem
1242 to rely on this. */
1243 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1244 }
1245
1246 static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp)
1247 {
1248 UHCIState *s = UHCI(dev);
1249 uint8_t *pci_conf = s->dev.config;
1250
1251 /* USB misc control 1/2 */
1252 pci_set_long(pci_conf + 0x40,0x00001000);
1253 /* PM capability */
1254 pci_set_long(pci_conf + 0x80,0x00020001);
1255 /* USB legacy support */
1256 pci_set_long(pci_conf + 0xc0,0x00002000);
1257
1258 usb_uhci_common_realize(dev, errp);
1259 }
1260
1261 static void usb_uhci_exit(PCIDevice *dev)
1262 {
1263 UHCIState *s = UHCI(dev);
1264
1265 trace_usb_uhci_exit();
1266
1267 if (s->frame_timer) {
1268 timer_del(s->frame_timer);
1269 timer_free(s->frame_timer);
1270 s->frame_timer = NULL;
1271 }
1272
1273 if (s->bh) {
1274 qemu_bh_delete(s->bh);
1275 }
1276
1277 uhci_async_cancel_all(s);
1278
1279 if (!s->masterbus) {
1280 usb_bus_release(&s->bus);
1281 }
1282 }
1283
1284 static Property uhci_properties_companion[] = {
1285 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
1286 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0),
1287 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
1288 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128),
1289 DEFINE_PROP_END_OF_LIST(),
1290 };
1291 static Property uhci_properties_standalone[] = {
1292 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
1293 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128),
1294 DEFINE_PROP_END_OF_LIST(),
1295 };
1296
1297 static void uhci_class_init(ObjectClass *klass, void *data)
1298 {
1299 DeviceClass *dc = DEVICE_CLASS(klass);
1300 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1301
1302 k->class_id = PCI_CLASS_SERIAL_USB;
1303 dc->vmsd = &vmstate_uhci;
1304 dc->reset = uhci_reset;
1305 set_bit(DEVICE_CATEGORY_USB, dc->categories);
1306 }
1307
1308 static const TypeInfo uhci_pci_type_info = {
1309 .name = TYPE_UHCI,
1310 .parent = TYPE_PCI_DEVICE,
1311 .instance_size = sizeof(UHCIState),
1312 .class_size = sizeof(UHCIPCIDeviceClass),
1313 .abstract = true,
1314 .class_init = uhci_class_init,
1315 };
1316
1317 static void uhci_data_class_init(ObjectClass *klass, void *data)
1318 {
1319 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1320 DeviceClass *dc = DEVICE_CLASS(klass);
1321 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class);
1322 UHCIInfo *info = data;
1323
1324 k->realize = info->realize ? info->realize : usb_uhci_common_realize;
1325 k->exit = info->unplug ? usb_uhci_exit : NULL;
1326 k->vendor_id = info->vendor_id;
1327 k->device_id = info->device_id;
1328 k->revision = info->revision;
1329 if (!info->unplug) {
1330 /* uhci controllers in companion setups can't be hotplugged */
1331 dc->hotpluggable = false;
1332 dc->props = uhci_properties_companion;
1333 } else {
1334 dc->props = uhci_properties_standalone;
1335 }
1336 u->info = *info;
1337 }
1338
1339 static UHCIInfo uhci_info[] = {
1340 {
1341 .name = "piix3-usb-uhci",
1342 .vendor_id = PCI_VENDOR_ID_INTEL,
1343 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2,
1344 .revision = 0x01,
1345 .irq_pin = 3,
1346 .unplug = true,
1347 },{
1348 .name = "piix4-usb-uhci",
1349 .vendor_id = PCI_VENDOR_ID_INTEL,
1350 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2,
1351 .revision = 0x01,
1352 .irq_pin = 3,
1353 .unplug = true,
1354 },{
1355 .name = "vt82c686b-usb-uhci",
1356 .vendor_id = PCI_VENDOR_ID_VIA,
1357 .device_id = PCI_DEVICE_ID_VIA_UHCI,
1358 .revision = 0x01,
1359 .irq_pin = 3,
1360 .realize = usb_uhci_vt82c686b_realize,
1361 .unplug = true,
1362 },{
1363 .name = "ich9-usb-uhci1", /* 00:1d.0 */
1364 .vendor_id = PCI_VENDOR_ID_INTEL,
1365 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1,
1366 .revision = 0x03,
1367 .irq_pin = 0,
1368 .unplug = false,
1369 },{
1370 .name = "ich9-usb-uhci2", /* 00:1d.1 */
1371 .vendor_id = PCI_VENDOR_ID_INTEL,
1372 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2,
1373 .revision = 0x03,
1374 .irq_pin = 1,
1375 .unplug = false,
1376 },{
1377 .name = "ich9-usb-uhci3", /* 00:1d.2 */
1378 .vendor_id = PCI_VENDOR_ID_INTEL,
1379 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3,
1380 .revision = 0x03,
1381 .irq_pin = 2,
1382 .unplug = false,
1383 },{
1384 .name = "ich9-usb-uhci4", /* 00:1a.0 */
1385 .vendor_id = PCI_VENDOR_ID_INTEL,
1386 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4,
1387 .revision = 0x03,
1388 .irq_pin = 0,
1389 .unplug = false,
1390 },{
1391 .name = "ich9-usb-uhci5", /* 00:1a.1 */
1392 .vendor_id = PCI_VENDOR_ID_INTEL,
1393 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5,
1394 .revision = 0x03,
1395 .irq_pin = 1,
1396 .unplug = false,
1397 },{
1398 .name = "ich9-usb-uhci6", /* 00:1a.2 */
1399 .vendor_id = PCI_VENDOR_ID_INTEL,
1400 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6,
1401 .revision = 0x03,
1402 .irq_pin = 2,
1403 .unplug = false,
1404 }
1405 };
1406
1407 static void uhci_register_types(void)
1408 {
1409 TypeInfo uhci_type_info = {
1410 .parent = TYPE_UHCI,
1411 .class_init = uhci_data_class_init,
1412 };
1413 int i;
1414
1415 type_register_static(&uhci_pci_type_info);
1416
1417 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) {
1418 uhci_type_info.name = uhci_info[i].name;
1419 uhci_type_info.class_data = uhci_info + i;
1420 type_register(&uhci_type_info);
1421 }
1422 }
1423
1424 type_init(uhci_register_types)
AR7 emulation for QEMU