hw/pci/msi.c

   1 /*
   2  * msi.c
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/pci/msi.h"
  23 #include "qemu/range.h"
  24
  25 /* PCI_MSI_ADDRESS_LO */
  26 #define PCI_MSI_ADDRESS_LO_MASK         (~0x3)
  27
  28 /* If we get rid of cap allocator, we won't need those. */
  29 #define PCI_MSI_32_SIZEOF       0x0a
  30 #define PCI_MSI_64_SIZEOF       0x0e
  31 #define PCI_MSI_32M_SIZEOF      0x14
  32 #define PCI_MSI_64M_SIZEOF      0x18
  33
  34 #define PCI_MSI_VECTORS_MAX     32
  35
  36 /* Flag for interrupt controller to declare MSI/MSI-X support */
  37 bool msi_supported;
  38
  39 /* If we get rid of cap allocator, we won't need this. */
  40 static inline uint8_t msi_cap_sizeof(uint16_t flags)
  41 {
  42     switch (flags & (PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT)) {
  43     case PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT:
  44         return PCI_MSI_64M_SIZEOF;
  45     case PCI_MSI_FLAGS_64BIT:
  46         return PCI_MSI_64_SIZEOF;
  47     case PCI_MSI_FLAGS_MASKBIT:
  48         return PCI_MSI_32M_SIZEOF;
  49     case 0:
  50         return PCI_MSI_32_SIZEOF;
  51     default:
  52         abort();
  53         break;
  54     }
  55     return 0;
  56 }
  57
  58 //#define MSI_DEBUG
  59
  60 #ifdef MSI_DEBUG
  61 # define MSI_DPRINTF(fmt, ...)                                          \
  62     fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
  63 #else
  64 # define MSI_DPRINTF(fmt, ...)  do { } while (0)
  65 #endif
  66 #define MSI_DEV_PRINTF(dev, fmt, ...)                                   \
  67     MSI_DPRINTF("%s:%x " fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
  68
  69 static inline unsigned int msi_nr_vectors(uint16_t flags)
  70 {
  71     return 1U <<
  72         ((flags & PCI_MSI_FLAGS_QSIZE) >> ctz32(PCI_MSI_FLAGS_QSIZE));
  73 }
  74
  75 static inline uint8_t msi_flags_off(const PCIDevice* dev)
  76 {
  77     return dev->msi_cap + PCI_MSI_FLAGS;
  78 }
  79
  80 static inline uint8_t msi_address_lo_off(const PCIDevice* dev)
  81 {
  82     return dev->msi_cap + PCI_MSI_ADDRESS_LO;
  83 }
  84
  85 static inline uint8_t msi_address_hi_off(const PCIDevice* dev)
  86 {
  87     return dev->msi_cap + PCI_MSI_ADDRESS_HI;
  88 }
  89
  90 static inline uint8_t msi_data_off(const PCIDevice* dev, bool msi64bit)
  91 {
  92     return dev->msi_cap + (msi64bit ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32);
  93 }
  94
  95 static inline uint8_t msi_mask_off(const PCIDevice* dev, bool msi64bit)
  96 {
  97     return dev->msi_cap + (msi64bit ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32);
  98 }
  99
 100 static inline uint8_t msi_pending_off(const PCIDevice* dev, bool msi64bit)
 101 {
 102     return dev->msi_cap + (msi64bit ? PCI_MSI_PENDING_64 : PCI_MSI_PENDING_32);
 103 }
 104
 105 /*
 106  * Special API for POWER to configure the vectors through
 107  * a side channel. Should never be used by devices.
 108  */
 109 void msi_set_message(PCIDevice *dev, MSIMessage msg)
 110 {
 111     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 112     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 113
 114     if (msi64bit) {
 115         pci_set_quad(dev->config + msi_address_lo_off(dev), msg.address);
 116     } else {
 117         pci_set_long(dev->config + msi_address_lo_off(dev), msg.address);
 118     }
 119     pci_set_word(dev->config + msi_data_off(dev, msi64bit), msg.data);
 120 }
 121
 122 MSIMessage msi_get_message(PCIDevice *dev, unsigned int vector)
 123 {
 124     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 125     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 126     unsigned int nr_vectors = msi_nr_vectors(flags);
 127     MSIMessage msg;
 128
 129     assert(vector < nr_vectors);
 130
 131     if (msi64bit) {
 132         msg.address = pci_get_quad(dev->config + msi_address_lo_off(dev));
 133     } else {
 134         msg.address = pci_get_long(dev->config + msi_address_lo_off(dev));
 135     }
 136
 137     /* upper bit 31:16 is zero */
 138     msg.data = pci_get_word(dev->config + msi_data_off(dev, msi64bit));
 139     if (nr_vectors > 1) {
 140         msg.data &= ~(nr_vectors - 1);
 141         msg.data |= vector;
 142     }
 143
 144     return msg;
 145 }
 146
 147 bool msi_enabled(const PCIDevice *dev)
 148 {
 149     return msi_present(dev) &&
 150         (pci_get_word(dev->config + msi_flags_off(dev)) &
 151          PCI_MSI_FLAGS_ENABLE);
 152 }
 153
 154 int msi_init(struct PCIDevice *dev, uint8_t offset,
 155              unsigned int nr_vectors, bool msi64bit, bool msi_per_vector_mask)
 156 {
 157     unsigned int vectors_order;
 158     uint16_t flags;
 159     uint8_t cap_size;
 160     int config_offset;
 161
 162     if (!msi_supported) {
 163         return -ENOTSUP;
 164     }
 165
 166     MSI_DEV_PRINTF(dev,
 167                    "init offset: 0x%"PRIx8" vector: %"PRId8
 168                    " 64bit %d mask %d\n",
 169                    offset, nr_vectors, msi64bit, msi_per_vector_mask);
 170
 171     assert(!(nr_vectors & (nr_vectors - 1)));   /* power of 2 */
 172     assert(nr_vectors > 0);
 173     assert(nr_vectors <= PCI_MSI_VECTORS_MAX);
 174     /* the nr of MSI vectors is up to 32 */
 175     vectors_order = ctz32(nr_vectors);
 176
 177     flags = vectors_order << ctz32(PCI_MSI_FLAGS_QMASK);
 178     if (msi64bit) {
 179         flags |= PCI_MSI_FLAGS_64BIT;
 180     }
 181     if (msi_per_vector_mask) {
 182         flags |= PCI_MSI_FLAGS_MASKBIT;
 183     }
 184
 185     cap_size = msi_cap_sizeof(flags);
 186     config_offset = pci_add_capability(dev, PCI_CAP_ID_MSI, offset, cap_size);
 187     if (config_offset < 0) {
 188         return config_offset;
 189     }
 190
 191     dev->msi_cap = config_offset;
 192     dev->cap_present |= QEMU_PCI_CAP_MSI;
 193
 194     pci_set_word(dev->config + msi_flags_off(dev), flags);
 195     pci_set_word(dev->wmask + msi_flags_off(dev),
 196                  PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
 197     pci_set_long(dev->wmask + msi_address_lo_off(dev),
 198                  PCI_MSI_ADDRESS_LO_MASK);
 199     if (msi64bit) {
 200         pci_set_long(dev->wmask + msi_address_hi_off(dev), 0xffffffff);
 201     }
 202     pci_set_word(dev->wmask + msi_data_off(dev, msi64bit), 0xffff);
 203
 204     if (msi_per_vector_mask) {
 205         /* Make mask bits 0 to nr_vectors - 1 writable. */
 206         pci_set_long(dev->wmask + msi_mask_off(dev, msi64bit),
 207                      0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors));
 208     }
 209     return config_offset;
 210 }
 211
 212 void msi_uninit(struct PCIDevice *dev)
 213 {
 214     uint16_t flags;
 215     uint8_t cap_size;
 216
 217     if (!msi_present(dev)) {
 218         return;
 219     }
 220     flags = pci_get_word(dev->config + msi_flags_off(dev));
 221     cap_size = msi_cap_sizeof(flags);
 222     pci_del_capability(dev, PCI_CAP_ID_MSI, cap_size);
 223     dev->cap_present &= ~QEMU_PCI_CAP_MSI;
 224
 225     MSI_DEV_PRINTF(dev, "uninit\n");
 226 }
 227
 228 void msi_reset(PCIDevice *dev)
 229 {
 230     uint16_t flags;
 231     bool msi64bit;
 232
 233     if (!msi_present(dev)) {
 234         return;
 235     }
 236
 237     flags = pci_get_word(dev->config + msi_flags_off(dev));
 238     flags &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
 239     msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 240
 241     pci_set_word(dev->config + msi_flags_off(dev), flags);
 242     pci_set_long(dev->config + msi_address_lo_off(dev), 0);
 243     if (msi64bit) {
 244         pci_set_long(dev->config + msi_address_hi_off(dev), 0);
 245     }
 246     pci_set_word(dev->config + msi_data_off(dev, msi64bit), 0);
 247     if (flags & PCI_MSI_FLAGS_MASKBIT) {
 248         pci_set_long(dev->config + msi_mask_off(dev, msi64bit), 0);
 249         pci_set_long(dev->config + msi_pending_off(dev, msi64bit), 0);
 250     }
 251     MSI_DEV_PRINTF(dev, "reset\n");
 252 }
 253
 254 static bool msi_is_masked(const PCIDevice *dev, unsigned int vector)
 255 {
 256     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 257     uint32_t mask;
 258     assert(vector < PCI_MSI_VECTORS_MAX);
 259
 260     if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
 261         return false;
 262     }
 263
 264     mask = pci_get_long(dev->config +
 265                         msi_mask_off(dev, flags & PCI_MSI_FLAGS_64BIT));
 266     return mask & (1U << vector);
 267 }
 268
 269 void msi_notify(PCIDevice *dev, unsigned int vector)
 270 {
 271     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 272     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 273     unsigned int nr_vectors = msi_nr_vectors(flags);
 274     MSIMessage msg;
 275
 276     assert(vector < nr_vectors);
 277     if (msi_is_masked(dev, vector)) {
 278         assert(flags & PCI_MSI_FLAGS_MASKBIT);
 279         pci_long_test_and_set_mask(
 280             dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
 281         MSI_DEV_PRINTF(dev, "pending vector 0x%x\n", vector);
 282         return;
 283     }
 284
 285     msg = msi_get_message(dev, vector);
 286
 287     MSI_DEV_PRINTF(dev,
 288                    "notify vector 0x%x"
 289                    " address: 0x%"PRIx64" data: 0x%"PRIx32"\n",
 290                    vector, msg.address, msg.data);
 291     msi_send_message(dev, msg);
 292 }
 293
 294 void msi_send_message(PCIDevice *dev, MSIMessage msg)
 295 {
 296     MemTxAttrs attrs = {};
 297
 298     attrs.requester_id = pci_requester_id(dev);
 299     address_space_stl_le(&dev->bus_master_as, msg.address, msg.data,
 300                          attrs, NULL);
 301 }
 302
 303 /* Normally called by pci_default_write_config(). */
 304 void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len)
 305 {
 306     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 307     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 308     bool msi_per_vector_mask = flags & PCI_MSI_FLAGS_MASKBIT;
 309     unsigned int nr_vectors;
 310     uint8_t log_num_vecs;
 311     uint8_t log_max_vecs;
 312     unsigned int vector;
 313     uint32_t pending;
 314
 315     if (!msi_present(dev) ||
 316         !ranges_overlap(addr, len, dev->msi_cap, msi_cap_sizeof(flags))) {
 317         return;
 318     }
 319
 320 #ifdef MSI_DEBUG
 321     MSI_DEV_PRINTF(dev, "addr 0x%"PRIx32" val 0x%"PRIx32" len %d\n",
 322                    addr, val, len);
 323     MSI_DEV_PRINTF(dev, "ctrl: 0x%"PRIx16" address: 0x%"PRIx32,
 324                    flags,
 325                    pci_get_long(dev->config + msi_address_lo_off(dev)));
 326     if (msi64bit) {
 327         fprintf(stderr, " address-hi: 0x%"PRIx32,
 328                 pci_get_long(dev->config + msi_address_hi_off(dev)));
 329     }
 330     fprintf(stderr, " data: 0x%"PRIx16,
 331             pci_get_word(dev->config + msi_data_off(dev, msi64bit)));
 332     if (flags & PCI_MSI_FLAGS_MASKBIT) {
 333         fprintf(stderr, " mask 0x%"PRIx32" pending 0x%"PRIx32,
 334                 pci_get_long(dev->config + msi_mask_off(dev, msi64bit)),
 335                 pci_get_long(dev->config + msi_pending_off(dev, msi64bit)));
 336     }
 337     fprintf(stderr, "\n");
 338 #endif
 339
 340     if (!(flags & PCI_MSI_FLAGS_ENABLE)) {
 341         return;
 342     }
 343
 344     /*
 345      * Now MSI is enabled, clear INTx# interrupts.
 346      * the driver is prohibited from writing enable bit to mask
 347      * a service request. But the guest OS could do this.
 348      * So we just discard the interrupts as moderate fallback.
 349      *
 350      * 6.8.3.3. Enabling Operation
 351      *   While enabled for MSI or MSI-X operation, a function is prohibited
 352      *   from using its INTx# pin (if implemented) to request
 353      *   service (MSI, MSI-X, and INTx# are mutually exclusive).
 354      */
 355     pci_device_deassert_intx(dev);
 356
 357     /*
 358      * nr_vectors might be set bigger than capable. So clamp it.
 359      * This is not legal by spec, so we can do anything we like,
 360      * just don't crash the host
 361      */
 362     log_num_vecs =
 363         (flags & PCI_MSI_FLAGS_QSIZE) >> ctz32(PCI_MSI_FLAGS_QSIZE);
 364     log_max_vecs =
 365         (flags & PCI_MSI_FLAGS_QMASK) >> ctz32(PCI_MSI_FLAGS_QMASK);
 366     if (log_num_vecs > log_max_vecs) {
 367         flags &= ~PCI_MSI_FLAGS_QSIZE;
 368         flags |= log_max_vecs << ctz32(PCI_MSI_FLAGS_QSIZE);
 369         pci_set_word(dev->config + msi_flags_off(dev), flags);
 370     }
 371
 372     if (!msi_per_vector_mask) {
 373         /* if per vector masking isn't supported,
 374            there is no pending interrupt. */
 375         return;
 376     }
 377
 378     nr_vectors = msi_nr_vectors(flags);
 379
 380     /* This will discard pending interrupts, if any. */
 381     pending = pci_get_long(dev->config + msi_pending_off(dev, msi64bit));
 382     pending &= 0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors);
 383     pci_set_long(dev->config + msi_pending_off(dev, msi64bit), pending);
 384
 385     /* deliver pending interrupts which are unmasked */
 386     for (vector = 0; vector < nr_vectors; ++vector) {
 387         if (msi_is_masked(dev, vector) || !(pending & (1U << vector))) {
 388             continue;
 389         }
 390
 391         pci_long_test_and_clear_mask(
 392             dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
 393         msi_notify(dev, vector);
 394     }
 395 }
 396
 397 unsigned int msi_nr_vectors_allocated(const PCIDevice *dev)
 398 {
 399     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 400     return msi_nr_vectors(flags);
 401 }