2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/visitor.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/hostmem.h"
33 #include "sysemu/numa.h"
34 #include "sysemu/qtest.h"
35 #include "sysemu/reset.h"
36 #include "sysemu/runstate.h"
38 #include "hw/fw-path-provider.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/cpus.h"
43 #include "sysemu/hw_accel.h"
45 #include "migration/misc.h"
46 #include "migration/qemu-file-types.h"
47 #include "migration/global_state.h"
48 #include "migration/register.h"
49 #include "migration/blocker.h"
50 #include "mmu-hash64.h"
51 #include "mmu-book3s-v3.h"
52 #include "cpu-models.h"
53 #include "hw/core/cpu.h"
55 #include "hw/boards.h"
56 #include "hw/ppc/ppc.h"
57 #include "hw/loader.h"
59 #include "hw/ppc/fdt.h"
60 #include "hw/ppc/spapr.h"
61 #include "hw/ppc/spapr_vio.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/pci-host/spapr.h"
64 #include "hw/pci/msi.h"
66 #include "hw/pci/pci.h"
67 #include "hw/scsi/scsi.h"
68 #include "hw/virtio/virtio-scsi.h"
69 #include "hw/virtio/vhost-scsi-common.h"
71 #include "exec/address-spaces.h"
72 #include "exec/ram_addr.h"
74 #include "qemu/config-file.h"
75 #include "qemu/error-report.h"
78 #include "hw/intc/intc.h"
80 #include "hw/ppc/spapr_cpu_core.h"
81 #include "hw/mem/memory-device.h"
82 #include "hw/ppc/spapr_tpm_proxy.h"
83 #include "hw/ppc/spapr_nvdimm.h"
84 #include "hw/ppc/spapr_numa.h"
86 #include "monitor/monitor.h"
90 /* SLOF memory layout:
92 * SLOF raw image loaded at 0, copies its romfs right below the flat
93 * device-tree, then position SLOF itself 31M below that
95 * So we set FW_OVERHEAD to 40MB which should account for all of that
98 * We load our kernel at 4M, leaving space for SLOF initial image
100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
101 #define FW_MAX_SIZE 0x400000
102 #define FW_FILE_NAME "slof.bin"
103 #define FW_OVERHEAD 0x2800000
104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
106 #define MIN_RMA_SLOF (128 * MiB)
108 #define PHANDLE_INTC 0x00001111
110 /* These two functions implement the VCPU id numbering: one to compute them
111 * all and one to identify thread 0 of a VCORE. Any change to the first one
112 * is likely to have an impact on the second one, so let's keep them close.
114 static int spapr_vcpu_id(SpaprMachineState
*spapr
, int cpu_index
)
116 MachineState
*ms
= MACHINE(spapr
);
117 unsigned int smp_threads
= ms
->smp
.threads
;
121 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
123 static bool spapr_is_thread0_in_vcore(SpaprMachineState
*spapr
,
127 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
132 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
133 * and newer QEMUs don't even have them. In both cases, we don't want
134 * to send anything on the wire.
139 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
140 .name
= "icp/server",
142 .minimum_version_id
= 1,
143 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
144 .fields
= (VMStateField
[]) {
145 VMSTATE_UNUSED(4), /* uint32_t xirr */
146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
147 VMSTATE_UNUSED(1), /* uint8_t mfrr */
148 VMSTATE_END_OF_LIST()
152 static void pre_2_10_vmstate_register_dummy_icp(int i
)
154 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
155 (void *)(uintptr_t) i
);
158 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
160 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
161 (void *)(uintptr_t) i
);
164 int spapr_max_server_number(SpaprMachineState
*spapr
)
166 MachineState
*ms
= MACHINE(spapr
);
169 return DIV_ROUND_UP(ms
->smp
.max_cpus
* spapr
->vsmt
, ms
->smp
.threads
);
172 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
176 uint32_t servers_prop
[smt_threads
];
177 uint32_t gservers_prop
[smt_threads
* 2];
178 int index
= spapr_get_vcpu_id(cpu
);
180 if (cpu
->compat_pvr
) {
181 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
187 /* Build interrupt servers and gservers properties */
188 for (i
= 0; i
< smt_threads
; i
++) {
189 servers_prop
[i
] = cpu_to_be32(index
+ i
);
190 /* Hack, direct the group queues back to cpu 0 */
191 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
192 gservers_prop
[i
*2 + 1] = 0;
194 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
195 servers_prop
, sizeof(servers_prop
));
199 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
200 gservers_prop
, sizeof(gservers_prop
));
205 static void spapr_dt_pa_features(SpaprMachineState
*spapr
,
207 void *fdt
, int offset
)
209 uint8_t pa_features_206
[] = { 6, 0,
210 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
211 uint8_t pa_features_207
[] = { 24, 0,
212 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
213 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
214 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
215 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
216 uint8_t pa_features_300
[] = { 66, 0,
217 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
218 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
219 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
221 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
223 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
224 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
225 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
226 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
227 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
228 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
229 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
230 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
231 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
232 /* 42: PM, 44: PC RA, 46: SC vec'd */
233 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
234 /* 48: SIMD, 50: QP BFP, 52: String */
235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
236 /* 54: DecFP, 56: DecI, 58: SHA */
237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
238 /* 60: NM atomic, 62: RNG */
239 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
241 uint8_t *pa_features
= NULL
;
244 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
245 pa_features
= pa_features_206
;
246 pa_size
= sizeof(pa_features_206
);
248 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
249 pa_features
= pa_features_207
;
250 pa_size
= sizeof(pa_features_207
);
252 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
253 pa_features
= pa_features_300
;
254 pa_size
= sizeof(pa_features_300
);
260 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
262 * Note: we keep CI large pages off by default because a 64K capable
263 * guest provisioned with large pages might otherwise try to map a qemu
264 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
265 * even if that qemu runs on a 4k host.
266 * We dd this bit back here if we are confident this is not an issue
268 pa_features
[3] |= 0x20;
270 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
271 pa_features
[24] |= 0x80; /* Transactional memory support */
273 if (spapr
->cas_pre_isa3_guest
&& pa_size
> 40) {
274 /* Workaround for broken kernels that attempt (guest) radix
275 * mode when they can't handle it, if they see the radix bit set
276 * in pa-features. So hide it from them. */
277 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
280 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
283 static hwaddr
spapr_node0_size(MachineState
*machine
)
285 if (machine
->numa_state
->num_nodes
) {
287 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
288 if (machine
->numa_state
->nodes
[i
].node_mem
) {
289 return MIN(pow2floor(machine
->numa_state
->nodes
[i
].node_mem
),
294 return machine
->ram_size
;
297 static void add_str(GString
*s
, const gchar
*s1
)
299 g_string_append_len(s
, s1
, strlen(s1
) + 1);
302 static int spapr_dt_memory_node(SpaprMachineState
*spapr
, void *fdt
, int nodeid
,
303 hwaddr start
, hwaddr size
)
306 uint64_t mem_reg_property
[2];
309 mem_reg_property
[0] = cpu_to_be64(start
);
310 mem_reg_property
[1] = cpu_to_be64(size
);
312 sprintf(mem_name
, "memory@%" HWADDR_PRIx
, start
);
313 off
= fdt_add_subnode(fdt
, 0, mem_name
);
315 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
316 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
317 sizeof(mem_reg_property
))));
318 spapr_numa_write_associativity_dt(spapr
, fdt
, off
, nodeid
);
322 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
324 MemoryDeviceInfoList
*info
;
326 for (info
= list
; info
; info
= info
->next
) {
327 MemoryDeviceInfo
*value
= info
->value
;
329 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
330 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
332 if (addr
>= pcdimm_info
->addr
&&
333 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
334 return pcdimm_info
->node
;
342 struct sPAPRDrconfCellV2
{
350 typedef struct DrconfCellQueue
{
351 struct sPAPRDrconfCellV2 cell
;
352 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
355 static DrconfCellQueue
*
356 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
357 uint32_t drc_index
, uint32_t aa_index
,
360 DrconfCellQueue
*elem
;
362 elem
= g_malloc0(sizeof(*elem
));
363 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
364 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
365 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
366 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
367 elem
->cell
.flags
= cpu_to_be32(flags
);
372 static int spapr_dt_dynamic_memory_v2(SpaprMachineState
*spapr
, void *fdt
,
373 int offset
, MemoryDeviceInfoList
*dimms
)
375 MachineState
*machine
= MACHINE(spapr
);
376 uint8_t *int_buf
, *cur_index
;
378 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
379 uint64_t addr
, cur_addr
, size
;
380 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
381 uint64_t mem_end
= machine
->device_memory
->base
+
382 memory_region_size(&machine
->device_memory
->mr
);
383 uint32_t node
, buf_len
, nr_entries
= 0;
385 DrconfCellQueue
*elem
, *next
;
386 MemoryDeviceInfoList
*info
;
387 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
388 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
390 /* Entry to cover RAM and the gap area */
391 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
392 SPAPR_LMB_FLAGS_RESERVED
|
393 SPAPR_LMB_FLAGS_DRC_INVALID
);
394 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
397 cur_addr
= machine
->device_memory
->base
;
398 for (info
= dimms
; info
; info
= info
->next
) {
399 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
406 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The
407 * area is marked hotpluggable in the next iteration for the bigger
408 * chunk including the NVDIMM occupied area.
410 if (info
->value
->type
== MEMORY_DEVICE_INFO_KIND_NVDIMM
)
413 /* Entry for hot-pluggable area */
414 if (cur_addr
< addr
) {
415 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
417 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
418 cur_addr
, spapr_drc_index(drc
), -1, 0);
419 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
424 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
426 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
427 spapr_drc_index(drc
), node
,
428 (SPAPR_LMB_FLAGS_ASSIGNED
|
429 SPAPR_LMB_FLAGS_HOTREMOVABLE
));
430 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
432 cur_addr
= addr
+ size
;
435 /* Entry for remaining hotpluggable area */
436 if (cur_addr
< mem_end
) {
437 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
439 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
440 cur_addr
, spapr_drc_index(drc
), -1, 0);
441 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
445 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
446 int_buf
= cur_index
= g_malloc0(buf_len
);
447 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
448 cur_index
+= sizeof(nr_entries
);
450 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
451 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
452 cur_index
+= sizeof(elem
->cell
);
453 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
457 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
465 static int spapr_dt_dynamic_memory(SpaprMachineState
*spapr
, void *fdt
,
466 int offset
, MemoryDeviceInfoList
*dimms
)
468 MachineState
*machine
= MACHINE(spapr
);
470 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
471 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
472 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
473 memory_region_size(&machine
->device_memory
->mr
)) /
475 uint32_t *int_buf
, *cur_index
, buf_len
;
478 * Allocate enough buffer size to fit in ibm,dynamic-memory
480 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
481 cur_index
= int_buf
= g_malloc0(buf_len
);
482 int_buf
[0] = cpu_to_be32(nr_lmbs
);
484 for (i
= 0; i
< nr_lmbs
; i
++) {
485 uint64_t addr
= i
* lmb_size
;
486 uint32_t *dynamic_memory
= cur_index
;
488 if (i
>= device_lmb_start
) {
491 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
494 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
495 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
496 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
497 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
498 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
499 if (memory_region_present(get_system_memory(), addr
)) {
500 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
502 dynamic_memory
[5] = cpu_to_be32(0);
506 * LMB information for RMA, boot time RAM and gap b/n RAM and
507 * device memory region -- all these are marked as reserved
508 * and as having no valid DRC.
510 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
511 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
512 dynamic_memory
[2] = cpu_to_be32(0);
513 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
514 dynamic_memory
[4] = cpu_to_be32(-1);
515 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
516 SPAPR_LMB_FLAGS_DRC_INVALID
);
519 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
521 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
530 * Adds ibm,dynamic-reconfiguration-memory node.
531 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
532 * of this device tree node.
534 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState
*spapr
,
537 MachineState
*machine
= MACHINE(spapr
);
539 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
540 uint32_t prop_lmb_size
[] = {cpu_to_be32(lmb_size
>> 32),
541 cpu_to_be32(lmb_size
& 0xffffffff)};
542 MemoryDeviceInfoList
*dimms
= NULL
;
545 * Don't create the node if there is no device memory
547 if (machine
->ram_size
== machine
->maxram_size
) {
551 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
553 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
554 sizeof(prop_lmb_size
));
559 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
564 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
569 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
570 dimms
= qmp_memory_device_list();
571 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
572 ret
= spapr_dt_dynamic_memory_v2(spapr
, fdt
, offset
, dimms
);
574 ret
= spapr_dt_dynamic_memory(spapr
, fdt
, offset
, dimms
);
576 qapi_free_MemoryDeviceInfoList(dimms
);
582 ret
= spapr_numa_write_assoc_lookup_arrays(spapr
, fdt
, offset
);
587 static int spapr_dt_memory(SpaprMachineState
*spapr
, void *fdt
)
589 MachineState
*machine
= MACHINE(spapr
);
590 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
591 hwaddr mem_start
, node_size
;
592 int i
, nb_nodes
= machine
->numa_state
->num_nodes
;
593 NodeInfo
*nodes
= machine
->numa_state
->nodes
;
595 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
596 if (!nodes
[i
].node_mem
) {
599 if (mem_start
>= machine
->ram_size
) {
602 node_size
= nodes
[i
].node_mem
;
603 if (node_size
> machine
->ram_size
- mem_start
) {
604 node_size
= machine
->ram_size
- mem_start
;
608 /* spapr_machine_init() checks for rma_size <= node0_size
610 spapr_dt_memory_node(spapr
, fdt
, i
, 0, spapr
->rma_size
);
611 mem_start
+= spapr
->rma_size
;
612 node_size
-= spapr
->rma_size
;
614 for ( ; node_size
; ) {
615 hwaddr sizetmp
= pow2floor(node_size
);
617 /* mem_start != 0 here */
618 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
619 sizetmp
= 1ULL << ctzl(mem_start
);
622 spapr_dt_memory_node(spapr
, fdt
, i
, mem_start
, sizetmp
);
623 node_size
-= sizetmp
;
624 mem_start
+= sizetmp
;
628 /* Generate ibm,dynamic-reconfiguration-memory node if required */
629 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRCONF_MEMORY
)) {
632 g_assert(smc
->dr_lmb_enabled
);
633 ret
= spapr_dt_dynamic_reconfiguration_memory(spapr
, fdt
);
642 static void spapr_dt_cpu(CPUState
*cs
, void *fdt
, int offset
,
643 SpaprMachineState
*spapr
)
645 MachineState
*ms
= MACHINE(spapr
);
646 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
647 CPUPPCState
*env
= &cpu
->env
;
648 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
649 int index
= spapr_get_vcpu_id(cpu
);
650 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
651 0xffffffff, 0xffffffff};
652 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
653 : SPAPR_TIMEBASE_FREQ
;
654 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
655 uint32_t page_sizes_prop
[64];
656 size_t page_sizes_prop_size
;
657 unsigned int smp_threads
= ms
->smp
.threads
;
658 uint32_t vcpus_per_socket
= smp_threads
* ms
->smp
.cores
;
659 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
660 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
663 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
666 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
668 drc_index
= spapr_drc_index(drc
);
669 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
672 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
673 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
675 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
676 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
677 env
->dcache_line_size
)));
678 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
679 env
->dcache_line_size
)));
680 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
681 env
->icache_line_size
)));
682 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
683 env
->icache_line_size
)));
685 if (pcc
->l1_dcache_size
) {
686 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
687 pcc
->l1_dcache_size
)));
689 warn_report("Unknown L1 dcache size for cpu");
691 if (pcc
->l1_icache_size
) {
692 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
693 pcc
->l1_icache_size
)));
695 warn_report("Unknown L1 icache size for cpu");
698 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
699 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
700 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
701 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
702 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
703 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
705 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
706 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,purr", 1)));
708 if (env
->spr_cb
[SPR_SPURR
].oea_read
) {
709 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,spurr", 1)));
712 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
713 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
714 segs
, sizeof(segs
))));
717 /* Advertise VSX (vector extensions) if available
718 * 1 == VMX / Altivec available
721 * Only CPUs for which we create core types in spapr_cpu_core.c
722 * are possible, and all of those have VMX */
723 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
724 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
726 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
729 /* Advertise DFP (Decimal Floating Point) if available
730 * 0 / no property == no DFP
731 * 1 == DFP available */
732 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
733 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
736 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
737 sizeof(page_sizes_prop
));
738 if (page_sizes_prop_size
) {
739 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
740 page_sizes_prop
, page_sizes_prop_size
)));
743 spapr_dt_pa_features(spapr
, cpu
, fdt
, offset
);
745 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
746 cs
->cpu_index
/ vcpus_per_socket
)));
748 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
749 pft_size_prop
, sizeof(pft_size_prop
))));
751 if (ms
->numa_state
->num_nodes
> 1) {
752 _FDT(spapr_numa_fixup_cpu_dt(spapr
, fdt
, offset
, cpu
));
755 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
757 if (pcc
->radix_page_info
) {
758 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
759 radix_AP_encodings
[i
] =
760 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
762 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
764 pcc
->radix_page_info
->count
*
765 sizeof(radix_AP_encodings
[0]))));
769 * We set this property to let the guest know that it can use the large
770 * decrementer and its width in bits.
772 if (spapr_get_cap(spapr
, SPAPR_CAP_LARGE_DECREMENTER
) != SPAPR_CAP_OFF
)
773 _FDT((fdt_setprop_u32(fdt
, offset
, "ibm,dec-bits",
774 pcc
->lrg_decr_bits
)));
777 static void spapr_dt_cpus(void *fdt
, SpaprMachineState
*spapr
)
786 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
788 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
789 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
792 * We walk the CPUs in reverse order to ensure that CPU DT nodes
793 * created by fdt_add_subnode() end up in the right order in FDT
794 * for the guest kernel the enumerate the CPUs correctly.
796 * The CPU list cannot be traversed in reverse order, so we need
802 rev
= g_renew(CPUState
*, rev
, n_cpus
+ 1);
806 for (i
= n_cpus
- 1; i
>= 0; i
--) {
807 CPUState
*cs
= rev
[i
];
808 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
809 int index
= spapr_get_vcpu_id(cpu
);
810 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
813 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
817 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
818 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
821 spapr_dt_cpu(cs
, fdt
, offset
, spapr
);
827 static int spapr_dt_rng(void *fdt
)
832 node
= qemu_fdt_add_subnode(fdt
, "/ibm,platform-facilities");
836 ret
= fdt_setprop_string(fdt
, node
, "device_type",
837 "ibm,platform-facilities");
838 ret
|= fdt_setprop_cell(fdt
, node
, "#address-cells", 0x1);
839 ret
|= fdt_setprop_cell(fdt
, node
, "#size-cells", 0x0);
841 node
= fdt_add_subnode(fdt
, node
, "ibm,random-v1");
845 ret
|= fdt_setprop_string(fdt
, node
, "compatible", "ibm,random");
850 static void spapr_dt_rtas(SpaprMachineState
*spapr
, void *fdt
)
852 MachineState
*ms
= MACHINE(spapr
);
854 GString
*hypertas
= g_string_sized_new(256);
855 GString
*qemu_hypertas
= g_string_sized_new(256);
856 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
857 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
858 uint32_t lrdr_capacity
[] = {
859 cpu_to_be32(max_device_addr
>> 32),
860 cpu_to_be32(max_device_addr
& 0xffffffff),
861 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
>> 32),
862 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
& 0xffffffff),
863 cpu_to_be32(ms
->smp
.max_cpus
/ ms
->smp
.threads
),
866 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
869 add_str(hypertas
, "hcall-pft");
870 add_str(hypertas
, "hcall-term");
871 add_str(hypertas
, "hcall-dabr");
872 add_str(hypertas
, "hcall-interrupt");
873 add_str(hypertas
, "hcall-tce");
874 add_str(hypertas
, "hcall-vio");
875 add_str(hypertas
, "hcall-splpar");
876 add_str(hypertas
, "hcall-join");
877 add_str(hypertas
, "hcall-bulk");
878 add_str(hypertas
, "hcall-set-mode");
879 add_str(hypertas
, "hcall-sprg0");
880 add_str(hypertas
, "hcall-copy");
881 add_str(hypertas
, "hcall-debug");
882 add_str(hypertas
, "hcall-vphn");
883 add_str(qemu_hypertas
, "hcall-memop1");
885 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
886 add_str(hypertas
, "hcall-multi-tce");
889 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
890 add_str(hypertas
, "hcall-hpt-resize");
893 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
894 hypertas
->str
, hypertas
->len
));
895 g_string_free(hypertas
, TRUE
);
896 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
897 qemu_hypertas
->str
, qemu_hypertas
->len
));
898 g_string_free(qemu_hypertas
, TRUE
);
900 spapr_numa_write_rtas_dt(spapr
, fdt
, rtas
);
903 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log,
904 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes.
906 * The system reset requirements are driven by existing Linux and PowerVM
907 * implementation which (contrary to PAPR) saves r3 in the error log
908 * structure like machine check, so Linux expects to find the saved r3
909 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and
910 * does not look at the error value).
912 * System reset interrupts are not subject to interlock like machine
913 * check, so this memory area could be corrupted if the sreset is
914 * interrupted by a machine check (or vice versa) if it was shared. To
915 * prevent this, system reset uses per-CPU areas for the sreset save
916 * area. A system reset that interrupts a system reset handler could
917 * still overwrite this area, but Linux doesn't try to recover in that
920 * The extra 8 bytes is required because Linux's FWNMI error log check
923 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-size", RTAS_ERROR_LOG_MAX
+
924 ms
->smp
.max_cpus
* sizeof(uint64_t)*2 + sizeof(uint64_t)));
925 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
926 RTAS_ERROR_LOG_MAX
));
927 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
928 RTAS_EVENT_SCAN_RATE
));
930 g_assert(msi_nonbroken
);
931 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
934 * According to PAPR, rtas ibm,os-term does not guarantee a return
935 * back to the guest cpu.
937 * While an additional ibm,extended-os-term property indicates
938 * that rtas call return will always occur. Set this property.
940 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
942 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
943 lrdr_capacity
, sizeof(lrdr_capacity
)));
945 spapr_dt_rtas_tokens(fdt
, rtas
);
949 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
950 * and the XIVE features that the guest may request and thus the valid
951 * values for bytes 23..26 of option vector 5:
953 static void spapr_dt_ov5_platform_support(SpaprMachineState
*spapr
, void *fdt
,
956 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
959 23, 0x00, /* XICS / XIVE mode */
960 24, 0x00, /* Hash/Radix, filled in below. */
961 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
962 26, 0x40, /* Radix options: GTSE == yes. */
965 if (spapr
->irq
->xics
&& spapr
->irq
->xive
) {
966 val
[1] = SPAPR_OV5_XIVE_BOTH
;
967 } else if (spapr
->irq
->xive
) {
968 val
[1] = SPAPR_OV5_XIVE_EXPLOIT
;
970 assert(spapr
->irq
->xics
);
971 val
[1] = SPAPR_OV5_XIVE_LEGACY
;
974 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
975 first_ppc_cpu
->compat_pvr
)) {
977 * If we're in a pre POWER9 compat mode then the guest should
978 * do hash and use the legacy interrupt mode
980 val
[1] = SPAPR_OV5_XIVE_LEGACY
; /* XICS */
981 val
[3] = 0x00; /* Hash */
982 } else if (kvm_enabled()) {
983 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
984 val
[3] = 0x80; /* OV5_MMU_BOTH */
985 } else if (kvmppc_has_cap_mmu_radix()) {
986 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
988 val
[3] = 0x00; /* Hash */
991 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
994 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
998 static void spapr_dt_chosen(SpaprMachineState
*spapr
, void *fdt
, bool reset
)
1000 MachineState
*machine
= MACHINE(spapr
);
1001 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1004 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1007 const char *boot_device
= machine
->boot_order
;
1008 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1010 char *bootlist
= get_boot_devices_list(&cb
);
1012 if (machine
->kernel_cmdline
&& machine
->kernel_cmdline
[0]) {
1013 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs",
1014 machine
->kernel_cmdline
));
1017 if (spapr
->initrd_size
) {
1018 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1019 spapr
->initrd_base
));
1020 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1021 spapr
->initrd_base
+ spapr
->initrd_size
));
1024 if (spapr
->kernel_size
) {
1025 uint64_t kprop
[2] = { cpu_to_be64(spapr
->kernel_addr
),
1026 cpu_to_be64(spapr
->kernel_size
) };
1028 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1029 &kprop
, sizeof(kprop
)));
1030 if (spapr
->kernel_le
) {
1031 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1035 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
1037 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1038 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1039 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1041 if (cb
&& bootlist
) {
1044 for (i
= 0; i
< cb
; i
++) {
1045 if (bootlist
[i
] == '\n') {
1049 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1052 if (boot_device
&& strlen(boot_device
)) {
1053 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1056 if (!spapr
->has_graphics
&& stdout_path
) {
1058 * "linux,stdout-path" and "stdout" properties are
1059 * deprecated by linux kernel. New platforms should only
1060 * use the "stdout-path" property. Set the new property
1061 * and continue using older property to remain compatible
1062 * with the existing firmware.
1064 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1065 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1069 * We can deal with BAR reallocation just fine, advertise it
1072 if (smc
->linux_pci_probe
) {
1073 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,pci-probe-only", 0));
1076 spapr_dt_ov5_platform_support(spapr
, fdt
, chosen
);
1078 g_free(stdout_path
);
1082 _FDT(spapr_dt_ovec(fdt
, chosen
, spapr
->ov5_cas
, "ibm,architecture-vec-5"));
1085 static void spapr_dt_hypervisor(SpaprMachineState
*spapr
, void *fdt
)
1087 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1088 * KVM to work under pHyp with some guest co-operation */
1090 uint8_t hypercall
[16];
1092 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1093 /* indicate KVM hypercall interface */
1094 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1095 if (kvmppc_has_cap_fixup_hcalls()) {
1097 * Older KVM versions with older guest kernels were broken
1098 * with the magic page, don't allow the guest to map it.
1100 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1101 sizeof(hypercall
))) {
1102 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1103 hypercall
, sizeof(hypercall
)));
1108 void *spapr_build_fdt(SpaprMachineState
*spapr
, bool reset
, size_t space
)
1110 MachineState
*machine
= MACHINE(spapr
);
1111 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1112 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1118 fdt
= g_malloc0(space
);
1119 _FDT((fdt_create_empty_tree(fdt
, space
)));
1122 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1123 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1124 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1126 /* Guest UUID & Name*/
1127 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1128 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1129 if (qemu_uuid_set
) {
1130 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1134 if (qemu_get_vm_name()) {
1135 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1136 qemu_get_vm_name()));
1139 /* Host Model & Serial Number */
1140 if (spapr
->host_model
) {
1141 _FDT(fdt_setprop_string(fdt
, 0, "host-model", spapr
->host_model
));
1142 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_model(&buf
)) {
1143 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1147 if (spapr
->host_serial
) {
1148 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", spapr
->host_serial
));
1149 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_serial(&buf
)) {
1150 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1154 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1155 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1157 /* /interrupt controller */
1158 spapr_irq_dt(spapr
, spapr_max_server_number(spapr
), fdt
, PHANDLE_INTC
);
1160 ret
= spapr_dt_memory(spapr
, fdt
);
1162 error_report("couldn't setup memory nodes in fdt");
1167 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1169 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1170 ret
= spapr_dt_rng(fdt
);
1172 error_report("could not set up rng device in the fdt");
1177 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1178 ret
= spapr_dt_phb(spapr
, phb
, PHANDLE_INTC
, fdt
, NULL
);
1180 error_report("couldn't setup PCI devices in fdt");
1185 spapr_dt_cpus(fdt
, spapr
);
1187 if (smc
->dr_lmb_enabled
) {
1188 _FDT(spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_LMB
));
1191 if (mc
->has_hotpluggable_cpus
) {
1192 int offset
= fdt_path_offset(fdt
, "/cpus");
1193 ret
= spapr_dt_drc(fdt
, offset
, NULL
, SPAPR_DR_CONNECTOR_TYPE_CPU
);
1195 error_report("Couldn't set up CPU DR device tree properties");
1200 /* /event-sources */
1201 spapr_dt_events(spapr
, fdt
);
1204 spapr_dt_rtas(spapr
, fdt
);
1207 spapr_dt_chosen(spapr
, fdt
, reset
);
1210 if (kvm_enabled()) {
1211 spapr_dt_hypervisor(spapr
, fdt
);
1214 /* Build memory reserve map */
1216 if (spapr
->kernel_size
) {
1217 _FDT((fdt_add_mem_rsv(fdt
, spapr
->kernel_addr
,
1218 spapr
->kernel_size
)));
1220 if (spapr
->initrd_size
) {
1221 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
,
1222 spapr
->initrd_size
)));
1226 if (smc
->dr_phb_enabled
) {
1227 ret
= spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_PHB
);
1229 error_report("Couldn't set up PHB DR device tree properties");
1234 /* NVDIMM devices */
1235 if (mc
->nvdimm_supported
) {
1236 spapr_dt_persistent_memory(spapr
, fdt
);
1242 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1244 SpaprMachineState
*spapr
= opaque
;
1246 return (addr
& 0x0fffffff) + spapr
->kernel_addr
;
1249 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1252 CPUPPCState
*env
= &cpu
->env
;
1254 /* The TCG path should also be holding the BQL at this point */
1255 g_assert(qemu_mutex_iothread_locked());
1258 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1259 env
->gpr
[3] = H_PRIVILEGE
;
1261 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1265 struct LPCRSyncState
{
1270 static void do_lpcr_sync(CPUState
*cs
, run_on_cpu_data arg
)
1272 struct LPCRSyncState
*s
= arg
.host_ptr
;
1273 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1274 CPUPPCState
*env
= &cpu
->env
;
1277 cpu_synchronize_state(cs
);
1278 lpcr
= env
->spr
[SPR_LPCR
];
1281 ppc_store_lpcr(cpu
, lpcr
);
1284 void spapr_set_all_lpcrs(target_ulong value
, target_ulong mask
)
1287 struct LPCRSyncState s
= {
1292 run_on_cpu(cs
, do_lpcr_sync
, RUN_ON_CPU_HOST_PTR(&s
));
1296 static void spapr_get_pate(PPCVirtualHypervisor
*vhyp
, ppc_v3_pate_t
*entry
)
1298 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1300 /* Copy PATE1:GR into PATE0:HR */
1301 entry
->dw0
= spapr
->patb_entry
& PATE0_HR
;
1302 entry
->dw1
= spapr
->patb_entry
;
1305 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1306 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1307 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1308 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1309 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1312 * Get the fd to access the kernel htab, re-opening it if necessary
1314 static int get_htab_fd(SpaprMachineState
*spapr
)
1316 Error
*local_err
= NULL
;
1318 if (spapr
->htab_fd
>= 0) {
1319 return spapr
->htab_fd
;
1322 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1323 if (spapr
->htab_fd
< 0) {
1324 error_report_err(local_err
);
1327 return spapr
->htab_fd
;
1330 void close_htab_fd(SpaprMachineState
*spapr
)
1332 if (spapr
->htab_fd
>= 0) {
1333 close(spapr
->htab_fd
);
1335 spapr
->htab_fd
= -1;
1338 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1340 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1342 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1345 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1347 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1349 assert(kvm_enabled());
1355 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1358 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1361 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1362 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1366 * HTAB is controlled by KVM. Fetch into temporary buffer
1368 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1369 kvmppc_read_hptes(hptes
, ptex
, n
);
1374 * HTAB is controlled by QEMU. Just point to the internally
1377 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1380 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1381 const ppc_hash_pte64_t
*hptes
,
1384 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1387 g_free((void *)hptes
);
1390 /* Nothing to do for qemu managed HPT */
1393 void spapr_store_hpte(PowerPCCPU
*cpu
, hwaddr ptex
,
1394 uint64_t pte0
, uint64_t pte1
)
1396 SpaprMachineState
*spapr
= SPAPR_MACHINE(cpu
->vhyp
);
1397 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1400 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1402 if (pte0
& HPTE64_V_VALID
) {
1403 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1405 * When setting valid, we write PTE1 first. This ensures
1406 * proper synchronization with the reading code in
1407 * ppc_hash64_pteg_search()
1410 stq_p(spapr
->htab
+ offset
, pte0
);
1412 stq_p(spapr
->htab
+ offset
, pte0
);
1414 * When clearing it we set PTE0 first. This ensures proper
1415 * synchronization with the reading code in
1416 * ppc_hash64_pteg_search()
1419 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1424 static void spapr_hpte_set_c(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1427 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 15;
1428 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1431 /* There should always be a hash table when this is called */
1432 error_report("spapr_hpte_set_c called with no hash table !");
1436 /* The HW performs a non-atomic byte update */
1437 stb_p(spapr
->htab
+ offset
, (pte1
& 0xff) | 0x80);
1440 static void spapr_hpte_set_r(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1443 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 14;
1444 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1447 /* There should always be a hash table when this is called */
1448 error_report("spapr_hpte_set_r called with no hash table !");
1452 /* The HW performs a non-atomic byte update */
1453 stb_p(spapr
->htab
+ offset
, ((pte1
>> 8) & 0xff) | 0x01);
1456 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1460 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1461 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1462 * that's much more than is needed for Linux guests */
1463 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1464 shift
= MAX(shift
, 18); /* Minimum architected size */
1465 shift
= MIN(shift
, 46); /* Maximum architected size */
1469 void spapr_free_hpt(SpaprMachineState
*spapr
)
1471 g_free(spapr
->htab
);
1473 spapr
->htab_shift
= 0;
1474 close_htab_fd(spapr
);
1477 void spapr_reallocate_hpt(SpaprMachineState
*spapr
, int shift
,
1482 /* Clean up any HPT info from a previous boot */
1483 spapr_free_hpt(spapr
);
1485 rc
= kvmppc_reset_htab(shift
);
1487 /* kernel-side HPT needed, but couldn't allocate one */
1488 error_setg_errno(errp
, errno
,
1489 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1491 /* This is almost certainly fatal, but if the caller really
1492 * wants to carry on with shift == 0, it's welcome to try */
1493 } else if (rc
> 0) {
1494 /* kernel-side HPT allocated */
1497 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1501 spapr
->htab_shift
= shift
;
1504 /* kernel-side HPT not needed, allocate in userspace instead */
1505 size_t size
= 1ULL << shift
;
1508 spapr
->htab
= qemu_memalign(size
, size
);
1510 error_setg_errno(errp
, errno
,
1511 "Could not allocate HPT of order %d", shift
);
1515 memset(spapr
->htab
, 0, size
);
1516 spapr
->htab_shift
= shift
;
1518 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1519 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1522 /* We're setting up a hash table, so that means we're not radix */
1523 spapr
->patb_entry
= 0;
1524 spapr_set_all_lpcrs(0, LPCR_HR
| LPCR_UPRT
);
1527 void spapr_setup_hpt(SpaprMachineState
*spapr
)
1531 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
) {
1532 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1534 uint64_t current_ram_size
;
1536 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1537 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1539 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1541 if (kvm_enabled()) {
1542 hwaddr vrma_limit
= kvmppc_vrma_limit(spapr
->htab_shift
);
1544 /* Check our RMA fits in the possible VRMA */
1545 if (vrma_limit
< spapr
->rma_size
) {
1546 error_report("Unable to create %" HWADDR_PRIu
1547 "MiB RMA (VRMA only allows %" HWADDR_PRIu
"MiB",
1548 spapr
->rma_size
/ MiB
, vrma_limit
/ MiB
);
1554 static int spapr_reset_drcs(Object
*child
, void *opaque
)
1557 (SpaprDrc
*) object_dynamic_cast(child
,
1558 TYPE_SPAPR_DR_CONNECTOR
);
1561 spapr_drc_reset(drc
);
1567 static void spapr_machine_reset(MachineState
*machine
)
1569 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
1570 PowerPCCPU
*first_ppc_cpu
;
1575 kvmppc_svm_off(&error_fatal
);
1576 spapr_caps_apply(spapr
);
1578 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1579 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1580 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
1581 spapr
->max_compat_pvr
)) {
1583 * If using KVM with radix mode available, VCPUs can be started
1584 * without a HPT because KVM will start them in radix mode.
1585 * Set the GR bit in PATE so that we know there is no HPT.
1587 spapr
->patb_entry
= PATE1_GR
;
1588 spapr_set_all_lpcrs(LPCR_HR
| LPCR_UPRT
, LPCR_HR
| LPCR_UPRT
);
1590 spapr_setup_hpt(spapr
);
1593 qemu_devices_reset();
1595 spapr_ovec_cleanup(spapr
->ov5_cas
);
1596 spapr
->ov5_cas
= spapr_ovec_new();
1598 ppc_set_compat_all(spapr
->max_compat_pvr
, &error_fatal
);
1601 * This is fixing some of the default configuration of the XIVE
1602 * devices. To be called after the reset of the machine devices.
1604 spapr_irq_reset(spapr
, &error_fatal
);
1607 * There is no CAS under qtest. Simulate one to please the code that
1608 * depends on spapr->ov5_cas. This is especially needed to test device
1609 * unplug, so we do that before resetting the DRCs.
1611 if (qtest_enabled()) {
1612 spapr_ovec_cleanup(spapr
->ov5_cas
);
1613 spapr
->ov5_cas
= spapr_ovec_clone(spapr
->ov5
);
1616 /* DRC reset may cause a device to be unplugged. This will cause troubles
1617 * if this device is used by another device (eg, a running vhost backend
1618 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1619 * situations, we reset DRCs after all devices have been reset.
1621 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs
, NULL
);
1623 spapr_clear_pending_events(spapr
);
1626 * We place the device tree and RTAS just below either the top of the RMA,
1627 * or just below 2GB, whichever is lower, so that it can be
1628 * processed with 32-bit real mode code if necessary
1630 fdt_addr
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FDT_MAX_SIZE
;
1632 fdt
= spapr_build_fdt(spapr
, true, FDT_MAX_SIZE
);
1636 /* Should only fail if we've built a corrupted tree */
1640 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1641 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1642 g_free(spapr
->fdt_blob
);
1643 spapr
->fdt_size
= fdt_totalsize(fdt
);
1644 spapr
->fdt_initial_size
= spapr
->fdt_size
;
1645 spapr
->fdt_blob
= fdt
;
1647 /* Set up the entry state */
1648 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
, 0, fdt_addr
, 0);
1649 first_ppc_cpu
->env
.gpr
[5] = 0;
1651 spapr
->fwnmi_system_reset_addr
= -1;
1652 spapr
->fwnmi_machine_check_addr
= -1;
1653 spapr
->fwnmi_machine_check_interlock
= -1;
1655 /* Signal all vCPUs waiting on this condition */
1656 qemu_cond_broadcast(&spapr
->fwnmi_machine_check_interlock_cond
);
1658 migrate_del_blocker(spapr
->fwnmi_migration_blocker
);
1661 static void spapr_create_nvram(SpaprMachineState
*spapr
)
1663 DeviceState
*dev
= qdev_new("spapr-nvram");
1664 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1667 qdev_prop_set_drive_err(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1671 qdev_realize_and_unref(dev
, &spapr
->vio_bus
->bus
, &error_fatal
);
1673 spapr
->nvram
= (struct SpaprNvram
*)dev
;
1676 static void spapr_rtc_create(SpaprMachineState
*spapr
)
1678 object_initialize_child_with_props(OBJECT(spapr
), "rtc", &spapr
->rtc
,
1679 sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
,
1680 &error_fatal
, NULL
);
1681 qdev_realize(DEVICE(&spapr
->rtc
), NULL
, &error_fatal
);
1682 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1686 /* Returns whether we want to use VGA or not */
1687 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1689 switch (vga_interface_type
) {
1697 return pci_vga_init(pci_bus
) != NULL
;
1700 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1705 static int spapr_pre_load(void *opaque
)
1709 rc
= spapr_caps_pre_load(opaque
);
1717 static int spapr_post_load(void *opaque
, int version_id
)
1719 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1722 err
= spapr_caps_post_migration(spapr
);
1728 * In earlier versions, there was no separate qdev for the PAPR
1729 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1730 * So when migrating from those versions, poke the incoming offset
1731 * value into the RTC device
1733 if (version_id
< 3) {
1734 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1740 if (kvm_enabled() && spapr
->patb_entry
) {
1741 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1742 bool radix
= !!(spapr
->patb_entry
& PATE1_GR
);
1743 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1746 * Update LPCR:HR and UPRT as they may not be set properly in
1749 spapr_set_all_lpcrs(radix
? (LPCR_HR
| LPCR_UPRT
) : 0,
1750 LPCR_HR
| LPCR_UPRT
);
1752 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1754 error_report("Process table config unsupported by the host");
1759 err
= spapr_irq_post_load(spapr
, version_id
);
1767 static int spapr_pre_save(void *opaque
)
1771 rc
= spapr_caps_pre_save(opaque
);
1779 static bool version_before_3(void *opaque
, int version_id
)
1781 return version_id
< 3;
1784 static bool spapr_pending_events_needed(void *opaque
)
1786 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1787 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1790 static const VMStateDescription vmstate_spapr_event_entry
= {
1791 .name
= "spapr_event_log_entry",
1793 .minimum_version_id
= 1,
1794 .fields
= (VMStateField
[]) {
1795 VMSTATE_UINT32(summary
, SpaprEventLogEntry
),
1796 VMSTATE_UINT32(extended_length
, SpaprEventLogEntry
),
1797 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, SpaprEventLogEntry
, 0,
1798 NULL
, extended_length
),
1799 VMSTATE_END_OF_LIST()
1803 static const VMStateDescription vmstate_spapr_pending_events
= {
1804 .name
= "spapr_pending_events",
1806 .minimum_version_id
= 1,
1807 .needed
= spapr_pending_events_needed
,
1808 .fields
= (VMStateField
[]) {
1809 VMSTATE_QTAILQ_V(pending_events
, SpaprMachineState
, 1,
1810 vmstate_spapr_event_entry
, SpaprEventLogEntry
, next
),
1811 VMSTATE_END_OF_LIST()
1815 static bool spapr_ov5_cas_needed(void *opaque
)
1817 SpaprMachineState
*spapr
= opaque
;
1818 SpaprOptionVector
*ov5_mask
= spapr_ovec_new();
1821 /* Prior to the introduction of SpaprOptionVector, we had two option
1822 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1823 * Both of these options encode machine topology into the device-tree
1824 * in such a way that the now-booted OS should still be able to interact
1825 * appropriately with QEMU regardless of what options were actually
1826 * negotiatied on the source side.
1828 * As such, we can avoid migrating the CAS-negotiated options if these
1829 * are the only options available on the current machine/platform.
1830 * Since these are the only options available for pseries-2.7 and
1831 * earlier, this allows us to maintain old->new/new->old migration
1834 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1835 * via default pseries-2.8 machines and explicit command-line parameters.
1836 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1837 * of the actual CAS-negotiated values to continue working properly. For
1838 * example, availability of memory unplug depends on knowing whether
1839 * OV5_HP_EVT was negotiated via CAS.
1841 * Thus, for any cases where the set of available CAS-negotiatable
1842 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1843 * include the CAS-negotiated options in the migration stream, unless
1844 * if they affect boot time behaviour only.
1846 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
1847 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
1848 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
1850 /* We need extra information if we have any bits outside the mask
1852 cas_needed
= !spapr_ovec_subset(spapr
->ov5
, ov5_mask
);
1854 spapr_ovec_cleanup(ov5_mask
);
1859 static const VMStateDescription vmstate_spapr_ov5_cas
= {
1860 .name
= "spapr_option_vector_ov5_cas",
1862 .minimum_version_id
= 1,
1863 .needed
= spapr_ov5_cas_needed
,
1864 .fields
= (VMStateField
[]) {
1865 VMSTATE_STRUCT_POINTER_V(ov5_cas
, SpaprMachineState
, 1,
1866 vmstate_spapr_ovec
, SpaprOptionVector
),
1867 VMSTATE_END_OF_LIST()
1871 static bool spapr_patb_entry_needed(void *opaque
)
1873 SpaprMachineState
*spapr
= opaque
;
1875 return !!spapr
->patb_entry
;
1878 static const VMStateDescription vmstate_spapr_patb_entry
= {
1879 .name
= "spapr_patb_entry",
1881 .minimum_version_id
= 1,
1882 .needed
= spapr_patb_entry_needed
,
1883 .fields
= (VMStateField
[]) {
1884 VMSTATE_UINT64(patb_entry
, SpaprMachineState
),
1885 VMSTATE_END_OF_LIST()
1889 static bool spapr_irq_map_needed(void *opaque
)
1891 SpaprMachineState
*spapr
= opaque
;
1893 return spapr
->irq_map
&& !bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
);
1896 static const VMStateDescription vmstate_spapr_irq_map
= {
1897 .name
= "spapr_irq_map",
1899 .minimum_version_id
= 1,
1900 .needed
= spapr_irq_map_needed
,
1901 .fields
= (VMStateField
[]) {
1902 VMSTATE_BITMAP(irq_map
, SpaprMachineState
, 0, irq_map_nr
),
1903 VMSTATE_END_OF_LIST()
1907 static bool spapr_dtb_needed(void *opaque
)
1909 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(opaque
);
1911 return smc
->update_dt_enabled
;
1914 static int spapr_dtb_pre_load(void *opaque
)
1916 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1918 g_free(spapr
->fdt_blob
);
1919 spapr
->fdt_blob
= NULL
;
1920 spapr
->fdt_size
= 0;
1925 static const VMStateDescription vmstate_spapr_dtb
= {
1926 .name
= "spapr_dtb",
1928 .minimum_version_id
= 1,
1929 .needed
= spapr_dtb_needed
,
1930 .pre_load
= spapr_dtb_pre_load
,
1931 .fields
= (VMStateField
[]) {
1932 VMSTATE_UINT32(fdt_initial_size
, SpaprMachineState
),
1933 VMSTATE_UINT32(fdt_size
, SpaprMachineState
),
1934 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob
, SpaprMachineState
, 0, NULL
,
1936 VMSTATE_END_OF_LIST()
1940 static bool spapr_fwnmi_needed(void *opaque
)
1942 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1944 return spapr
->fwnmi_machine_check_addr
!= -1;
1947 static int spapr_fwnmi_pre_save(void *opaque
)
1949 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1952 * Check if machine check handling is in progress and print a
1955 if (spapr
->fwnmi_machine_check_interlock
!= -1) {
1956 warn_report("A machine check is being handled during migration. The"
1957 "handler may run and log hardware error on the destination");
1963 static const VMStateDescription vmstate_spapr_fwnmi
= {
1964 .name
= "spapr_fwnmi",
1966 .minimum_version_id
= 1,
1967 .needed
= spapr_fwnmi_needed
,
1968 .pre_save
= spapr_fwnmi_pre_save
,
1969 .fields
= (VMStateField
[]) {
1970 VMSTATE_UINT64(fwnmi_system_reset_addr
, SpaprMachineState
),
1971 VMSTATE_UINT64(fwnmi_machine_check_addr
, SpaprMachineState
),
1972 VMSTATE_INT32(fwnmi_machine_check_interlock
, SpaprMachineState
),
1973 VMSTATE_END_OF_LIST()
1977 static const VMStateDescription vmstate_spapr
= {
1980 .minimum_version_id
= 1,
1981 .pre_load
= spapr_pre_load
,
1982 .post_load
= spapr_post_load
,
1983 .pre_save
= spapr_pre_save
,
1984 .fields
= (VMStateField
[]) {
1985 /* used to be @next_irq */
1986 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
1989 VMSTATE_UINT64_TEST(rtc_offset
, SpaprMachineState
, version_before_3
),
1991 VMSTATE_PPC_TIMEBASE_V(tb
, SpaprMachineState
, 2),
1992 VMSTATE_END_OF_LIST()
1994 .subsections
= (const VMStateDescription
*[]) {
1995 &vmstate_spapr_ov5_cas
,
1996 &vmstate_spapr_patb_entry
,
1997 &vmstate_spapr_pending_events
,
1998 &vmstate_spapr_cap_htm
,
1999 &vmstate_spapr_cap_vsx
,
2000 &vmstate_spapr_cap_dfp
,
2001 &vmstate_spapr_cap_cfpc
,
2002 &vmstate_spapr_cap_sbbc
,
2003 &vmstate_spapr_cap_ibs
,
2004 &vmstate_spapr_cap_hpt_maxpagesize
,
2005 &vmstate_spapr_irq_map
,
2006 &vmstate_spapr_cap_nested_kvm_hv
,
2008 &vmstate_spapr_cap_large_decr
,
2009 &vmstate_spapr_cap_ccf_assist
,
2010 &vmstate_spapr_cap_fwnmi
,
2011 &vmstate_spapr_fwnmi
,
2016 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
2018 SpaprMachineState
*spapr
= opaque
;
2020 /* "Iteration" header */
2021 if (!spapr
->htab_shift
) {
2022 qemu_put_be32(f
, -1);
2024 qemu_put_be32(f
, spapr
->htab_shift
);
2028 spapr
->htab_save_index
= 0;
2029 spapr
->htab_first_pass
= true;
2031 if (spapr
->htab_shift
) {
2032 assert(kvm_enabled());
2040 static void htab_save_chunk(QEMUFile
*f
, SpaprMachineState
*spapr
,
2041 int chunkstart
, int n_valid
, int n_invalid
)
2043 qemu_put_be32(f
, chunkstart
);
2044 qemu_put_be16(f
, n_valid
);
2045 qemu_put_be16(f
, n_invalid
);
2046 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
2047 HASH_PTE_SIZE_64
* n_valid
);
2050 static void htab_save_end_marker(QEMUFile
*f
)
2052 qemu_put_be32(f
, 0);
2053 qemu_put_be16(f
, 0);
2054 qemu_put_be16(f
, 0);
2057 static void htab_save_first_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2060 bool has_timeout
= max_ns
!= -1;
2061 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2062 int index
= spapr
->htab_save_index
;
2063 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2065 assert(spapr
->htab_first_pass
);
2070 /* Consume invalid HPTEs */
2071 while ((index
< htabslots
)
2072 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2073 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2077 /* Consume valid HPTEs */
2079 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2080 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2081 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2085 if (index
> chunkstart
) {
2086 int n_valid
= index
- chunkstart
;
2088 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2091 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2095 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
2097 if (index
>= htabslots
) {
2098 assert(index
== htabslots
);
2100 spapr
->htab_first_pass
= false;
2102 spapr
->htab_save_index
= index
;
2105 static int htab_save_later_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2108 bool final
= max_ns
< 0;
2109 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2110 int examined
= 0, sent
= 0;
2111 int index
= spapr
->htab_save_index
;
2112 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2114 assert(!spapr
->htab_first_pass
);
2117 int chunkstart
, invalidstart
;
2119 /* Consume non-dirty HPTEs */
2120 while ((index
< htabslots
)
2121 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2127 /* Consume valid dirty HPTEs */
2128 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2129 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2130 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2131 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2136 invalidstart
= index
;
2137 /* Consume invalid dirty HPTEs */
2138 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2139 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2140 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2141 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2146 if (index
> chunkstart
) {
2147 int n_valid
= invalidstart
- chunkstart
;
2148 int n_invalid
= index
- invalidstart
;
2150 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2151 sent
+= index
- chunkstart
;
2153 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2158 if (examined
>= htabslots
) {
2162 if (index
>= htabslots
) {
2163 assert(index
== htabslots
);
2166 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
2168 if (index
>= htabslots
) {
2169 assert(index
== htabslots
);
2173 spapr
->htab_save_index
= index
;
2175 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2178 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2179 #define MAX_KVM_BUF_SIZE 2048
2181 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2183 SpaprMachineState
*spapr
= opaque
;
2187 /* Iteration header */
2188 if (!spapr
->htab_shift
) {
2189 qemu_put_be32(f
, -1);
2192 qemu_put_be32(f
, 0);
2196 assert(kvm_enabled());
2198 fd
= get_htab_fd(spapr
);
2203 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2207 } else if (spapr
->htab_first_pass
) {
2208 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2210 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2213 htab_save_end_marker(f
);
2218 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2220 SpaprMachineState
*spapr
= opaque
;
2223 /* Iteration header */
2224 if (!spapr
->htab_shift
) {
2225 qemu_put_be32(f
, -1);
2228 qemu_put_be32(f
, 0);
2234 assert(kvm_enabled());
2236 fd
= get_htab_fd(spapr
);
2241 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2246 if (spapr
->htab_first_pass
) {
2247 htab_save_first_pass(f
, spapr
, -1);
2249 htab_save_later_pass(f
, spapr
, -1);
2253 htab_save_end_marker(f
);
2258 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2260 SpaprMachineState
*spapr
= opaque
;
2261 uint32_t section_hdr
;
2263 Error
*local_err
= NULL
;
2265 if (version_id
< 1 || version_id
> 1) {
2266 error_report("htab_load() bad version");
2270 section_hdr
= qemu_get_be32(f
);
2272 if (section_hdr
== -1) {
2273 spapr_free_hpt(spapr
);
2278 /* First section gives the htab size */
2279 spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2281 error_report_err(local_err
);
2288 assert(kvm_enabled());
2290 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2292 error_report_err(local_err
);
2299 uint16_t n_valid
, n_invalid
;
2301 index
= qemu_get_be32(f
);
2302 n_valid
= qemu_get_be16(f
);
2303 n_invalid
= qemu_get_be16(f
);
2305 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2310 if ((index
+ n_valid
+ n_invalid
) >
2311 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2312 /* Bad index in stream */
2314 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2315 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2321 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2322 HASH_PTE_SIZE_64
* n_valid
);
2325 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2326 HASH_PTE_SIZE_64
* n_invalid
);
2333 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
2348 static void htab_save_cleanup(void *opaque
)
2350 SpaprMachineState
*spapr
= opaque
;
2352 close_htab_fd(spapr
);
2355 static SaveVMHandlers savevm_htab_handlers
= {
2356 .save_setup
= htab_save_setup
,
2357 .save_live_iterate
= htab_save_iterate
,
2358 .save_live_complete_precopy
= htab_save_complete
,
2359 .save_cleanup
= htab_save_cleanup
,
2360 .load_state
= htab_load
,
2363 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2366 MachineState
*machine
= MACHINE(opaque
);
2367 machine
->boot_order
= g_strdup(boot_device
);
2370 static void spapr_create_lmb_dr_connectors(SpaprMachineState
*spapr
)
2372 MachineState
*machine
= MACHINE(spapr
);
2373 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2374 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2377 for (i
= 0; i
< nr_lmbs
; i
++) {
2380 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2381 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2387 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2388 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2389 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2391 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2395 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2396 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2397 " is not aligned to %" PRIu64
" MiB",
2399 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2403 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2404 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2405 " is not aligned to %" PRIu64
" MiB",
2407 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2411 for (i
= 0; i
< machine
->numa_state
->num_nodes
; i
++) {
2412 if (machine
->numa_state
->nodes
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2414 "Node %d memory size 0x%" PRIx64
2415 " is not aligned to %" PRIu64
" MiB",
2416 i
, machine
->numa_state
->nodes
[i
].node_mem
,
2417 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2423 /* find cpu slot in machine->possible_cpus by core_id */
2424 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2426 int index
= id
/ ms
->smp
.threads
;
2428 if (index
>= ms
->possible_cpus
->len
) {
2434 return &ms
->possible_cpus
->cpus
[index
];
2437 static void spapr_set_vsmt_mode(SpaprMachineState
*spapr
, Error
**errp
)
2439 MachineState
*ms
= MACHINE(spapr
);
2440 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
2441 Error
*local_err
= NULL
;
2442 bool vsmt_user
= !!spapr
->vsmt
;
2443 int kvm_smt
= kvmppc_smt_threads();
2445 unsigned int smp_threads
= ms
->smp
.threads
;
2447 if (!kvm_enabled() && (smp_threads
> 1)) {
2448 error_setg(errp
, "TCG cannot support more than 1 thread/core "
2449 "on a pseries machine");
2452 if (!is_power_of_2(smp_threads
)) {
2453 error_setg(errp
, "Cannot support %d threads/core on a pseries "
2454 "machine because it must be a power of 2", smp_threads
);
2458 /* Detemine the VSMT mode to use: */
2460 if (spapr
->vsmt
< smp_threads
) {
2461 error_setg(errp
, "Cannot support VSMT mode %d"
2462 " because it must be >= threads/core (%d)",
2463 spapr
->vsmt
, smp_threads
);
2466 /* In this case, spapr->vsmt has been set by the command line */
2467 } else if (!smc
->smp_threads_vsmt
) {
2469 * Default VSMT value is tricky, because we need it to be as
2470 * consistent as possible (for migration), but this requires
2471 * changing it for at least some existing cases. We pick 8 as
2472 * the value that we'd get with KVM on POWER8, the
2473 * overwhelmingly common case in production systems.
2475 spapr
->vsmt
= MAX(8, smp_threads
);
2477 spapr
->vsmt
= smp_threads
;
2480 /* KVM: If necessary, set the SMT mode: */
2481 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2482 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2484 /* Looks like KVM isn't able to change VSMT mode */
2485 error_setg(&local_err
,
2486 "Failed to set KVM's VSMT mode to %d (errno %d)",
2488 /* We can live with that if the default one is big enough
2489 * for the number of threads, and a submultiple of the one
2490 * we want. In this case we'll waste some vcpu ids, but
2491 * behaviour will be correct */
2492 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2493 warn_report_err(local_err
);
2496 error_append_hint(&local_err
,
2497 "On PPC, a VM with %d threads/core"
2498 " on a host with %d threads/core"
2499 " requires the use of VSMT mode %d.\n",
2500 smp_threads
, kvm_smt
, spapr
->vsmt
);
2502 kvmppc_error_append_smt_possible_hint(&local_err
);
2503 error_propagate(errp
, local_err
);
2507 /* else TCG: nothing to do currently */
2510 static void spapr_init_cpus(SpaprMachineState
*spapr
)
2512 MachineState
*machine
= MACHINE(spapr
);
2513 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2514 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2515 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2516 const CPUArchIdList
*possible_cpus
;
2517 unsigned int smp_cpus
= machine
->smp
.cpus
;
2518 unsigned int smp_threads
= machine
->smp
.threads
;
2519 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2520 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2523 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2524 if (mc
->has_hotpluggable_cpus
) {
2525 if (smp_cpus
% smp_threads
) {
2526 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2527 smp_cpus
, smp_threads
);
2530 if (max_cpus
% smp_threads
) {
2531 error_report("max_cpus (%u) must be multiple of threads (%u)",
2532 max_cpus
, smp_threads
);
2536 if (max_cpus
!= smp_cpus
) {
2537 error_report("This machine version does not support CPU hotplug");
2540 boot_cores_nr
= possible_cpus
->len
;
2543 if (smc
->pre_2_10_has_unused_icps
) {
2546 for (i
= 0; i
< spapr_max_server_number(spapr
); i
++) {
2547 /* Dummy entries get deregistered when real ICPState objects
2548 * are registered during CPU core hotplug.
2550 pre_2_10_vmstate_register_dummy_icp(i
);
2554 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2555 int core_id
= i
* smp_threads
;
2557 if (mc
->has_hotpluggable_cpus
) {
2558 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2559 spapr_vcpu_id(spapr
, core_id
));
2562 if (i
< boot_cores_nr
) {
2563 Object
*core
= object_new(type
);
2564 int nr_threads
= smp_threads
;
2566 /* Handle the partially filled core for older machine types */
2567 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2568 nr_threads
= smp_cpus
- i
* smp_threads
;
2571 object_property_set_int(core
, "nr-threads", nr_threads
,
2573 object_property_set_int(core
, CPU_CORE_PROP_CORE_ID
, core_id
,
2575 qdev_realize(DEVICE(core
), NULL
, &error_fatal
);
2582 static PCIHostState
*spapr_create_default_phb(void)
2586 dev
= qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE
);
2587 qdev_prop_set_uint32(dev
, "index", 0);
2588 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
2590 return PCI_HOST_BRIDGE(dev
);
2593 static hwaddr
spapr_rma_size(SpaprMachineState
*spapr
, Error
**errp
)
2595 MachineState
*machine
= MACHINE(spapr
);
2596 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
2597 hwaddr rma_size
= machine
->ram_size
;
2598 hwaddr node0_size
= spapr_node0_size(machine
);
2600 /* RMA has to fit in the first NUMA node */
2601 rma_size
= MIN(rma_size
, node0_size
);
2604 * VRMA access is via a special 1TiB SLB mapping, so the RMA can
2607 rma_size
= MIN(rma_size
, 1 * TiB
);
2610 * Clamp the RMA size based on machine type. This is for
2611 * migration compatibility with older qemu versions, which limited
2612 * the RMA size for complicated and mostly bad reasons.
2614 if (smc
->rma_limit
) {
2615 rma_size
= MIN(rma_size
, smc
->rma_limit
);
2618 if (rma_size
< MIN_RMA_SLOF
) {
2620 "pSeries SLOF firmware requires >= %" HWADDR_PRIx
2621 "ldMiB guest RMA (Real Mode Area memory)",
2622 MIN_RMA_SLOF
/ MiB
);
2629 /* pSeries LPAR / sPAPR hardware init */
2630 static void spapr_machine_init(MachineState
*machine
)
2632 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
2633 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2634 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2635 const char *kernel_filename
= machine
->kernel_filename
;
2636 const char *initrd_filename
= machine
->initrd_filename
;
2639 MemoryRegion
*sysmem
= get_system_memory();
2640 long load_limit
, fw_size
;
2642 Error
*resize_hpt_err
= NULL
;
2644 msi_nonbroken
= true;
2646 QLIST_INIT(&spapr
->phbs
);
2647 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2649 /* Determine capabilities to run with */
2650 spapr_caps_init(spapr
);
2652 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2653 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2655 * If the user explicitly requested a mode we should either
2656 * supply it, or fail completely (which we do below). But if
2657 * it's not set explicitly, we reset our mode to something
2660 if (resize_hpt_err
) {
2661 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2662 error_free(resize_hpt_err
);
2663 resize_hpt_err
= NULL
;
2665 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2669 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2671 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2673 * User requested HPT resize, but this host can't supply it. Bail out
2675 error_report_err(resize_hpt_err
);
2678 error_free(resize_hpt_err
);
2680 spapr
->rma_size
= spapr_rma_size(spapr
, &error_fatal
);
2682 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2683 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
2686 * VSMT must be set in order to be able to compute VCPU ids, ie to
2687 * call spapr_max_server_number() or spapr_vcpu_id().
2689 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2691 /* Set up Interrupt Controller before we create the VCPUs */
2692 spapr_irq_init(spapr
, &error_fatal
);
2694 /* Set up containers for ibm,client-architecture-support negotiated options
2696 spapr
->ov5
= spapr_ovec_new();
2697 spapr
->ov5_cas
= spapr_ovec_new();
2699 if (smc
->dr_lmb_enabled
) {
2700 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2701 spapr_validate_node_memory(machine
, &error_fatal
);
2704 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2706 /* advertise support for dedicated HP event source to guests */
2707 if (spapr
->use_hotplug_event_source
) {
2708 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2711 /* advertise support for HPT resizing */
2712 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2713 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2716 /* advertise support for ibm,dyamic-memory-v2 */
2717 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2719 /* advertise XIVE on POWER9 machines */
2720 if (spapr
->irq
->xive
) {
2721 spapr_ovec_set(spapr
->ov5
, OV5_XIVE_EXPLOIT
);
2725 spapr_init_cpus(spapr
);
2728 * check we don't have a memory-less/cpu-less NUMA node
2729 * Firmware relies on the existing memory/cpu topology to provide the
2730 * NUMA topology to the kernel.
2731 * And the linux kernel needs to know the NUMA topology at start
2732 * to be able to hotplug CPUs later.
2734 if (machine
->numa_state
->num_nodes
) {
2735 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
2736 /* check for memory-less node */
2737 if (machine
->numa_state
->nodes
[i
].node_mem
== 0) {
2740 /* check for cpu-less node */
2742 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2743 if (cpu
->node_id
== i
) {
2748 /* memory-less and cpu-less node */
2751 "Memory-less/cpu-less nodes are not supported (node %d)",
2761 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
2762 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
2763 * called from vPHB reset handler so we initialize the counter here.
2764 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
2765 * must be equally distant from any other node.
2766 * The final value of spapr->gpu_numa_id is going to be written to
2767 * max-associativity-domains in spapr_build_fdt().
2769 spapr
->gpu_numa_id
= MAX(1, machine
->numa_state
->num_nodes
);
2771 /* Init numa_assoc_array */
2772 spapr_numa_associativity_init(spapr
, machine
);
2774 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2775 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
2776 spapr
->max_compat_pvr
)) {
2777 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_300
);
2778 /* KVM and TCG always allow GTSE with radix... */
2779 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2781 /* ... but not with hash (currently). */
2783 if (kvm_enabled()) {
2784 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2785 kvmppc_enable_logical_ci_hcalls();
2786 kvmppc_enable_set_mode_hcall();
2788 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2789 kvmppc_enable_clear_ref_mod_hcalls();
2791 /* Enable H_PAGE_INIT */
2792 kvmppc_enable_h_page_init();
2796 memory_region_add_subregion(sysmem
, 0, machine
->ram
);
2798 /* always allocate the device memory information */
2799 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2801 /* initialize hotplug memory address space */
2802 if (machine
->ram_size
< machine
->maxram_size
) {
2803 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2805 * Limit the number of hotpluggable memory slots to half the number
2806 * slots that KVM supports, leaving the other half for PCI and other
2807 * devices. However ensure that number of slots doesn't drop below 32.
2809 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2810 SPAPR_MAX_RAM_SLOTS
;
2812 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2813 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2815 if (machine
->ram_slots
> max_memslots
) {
2816 error_report("Specified number of memory slots %"
2817 PRIu64
" exceeds max supported %d",
2818 machine
->ram_slots
, max_memslots
);
2822 machine
->device_memory
->base
= ROUND_UP(machine
->ram_size
,
2823 SPAPR_DEVICE_MEM_ALIGN
);
2824 memory_region_init(&machine
->device_memory
->mr
, OBJECT(spapr
),
2825 "device-memory", device_mem_size
);
2826 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2827 &machine
->device_memory
->mr
);
2830 if (smc
->dr_lmb_enabled
) {
2831 spapr_create_lmb_dr_connectors(spapr
);
2834 if (spapr_get_cap(spapr
, SPAPR_CAP_FWNMI
) == SPAPR_CAP_ON
) {
2835 /* Create the error string for live migration blocker */
2836 error_setg(&spapr
->fwnmi_migration_blocker
,
2837 "A machine check is being handled during migration. The handler"
2838 "may run and log hardware error on the destination");
2841 if (mc
->nvdimm_supported
) {
2842 spapr_create_nvdimm_dr_connectors(spapr
);
2845 /* Set up RTAS event infrastructure */
2846 spapr_events_init(spapr
);
2848 /* Set up the RTC RTAS interfaces */
2849 spapr_rtc_create(spapr
);
2851 /* Set up VIO bus */
2852 spapr
->vio_bus
= spapr_vio_bus_init();
2854 for (i
= 0; i
< serial_max_hds(); i
++) {
2856 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2860 /* We always have at least the nvram device on VIO */
2861 spapr_create_nvram(spapr
);
2864 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2865 * connectors (described in root DT node's "ibm,drc-types" property)
2866 * are pre-initialized here. additional child connectors (such as
2867 * connectors for a PHBs PCI slots) are added as needed during their
2868 * parent's realization.
2870 if (smc
->dr_phb_enabled
) {
2871 for (i
= 0; i
< SPAPR_MAX_PHBS
; i
++) {
2872 spapr_dr_connector_new(OBJECT(machine
), TYPE_SPAPR_DRC_PHB
, i
);
2877 spapr_pci_rtas_init();
2879 phb
= spapr_create_default_phb();
2881 for (i
= 0; i
< nb_nics
; i
++) {
2882 NICInfo
*nd
= &nd_table
[i
];
2885 nd
->model
= g_strdup("spapr-vlan");
2888 if (g_str_equal(nd
->model
, "spapr-vlan") ||
2889 g_str_equal(nd
->model
, "ibmveth")) {
2890 spapr_vlan_create(spapr
->vio_bus
, nd
);
2892 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2896 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2897 spapr_vscsi_create(spapr
->vio_bus
);
2901 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
2902 spapr
->has_graphics
= true;
2903 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2907 if (smc
->use_ohci_by_default
) {
2908 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2910 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2913 if (spapr
->has_graphics
) {
2914 USBBus
*usb_bus
= usb_bus_find(-1);
2916 usb_create_simple(usb_bus
, "usb-kbd");
2917 usb_create_simple(usb_bus
, "usb-mouse");
2921 if (kernel_filename
) {
2922 uint64_t lowaddr
= 0;
2924 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2925 translate_kernel_address
, spapr
,
2926 NULL
, &lowaddr
, NULL
, NULL
, 1,
2927 PPC_ELF_MACHINE
, 0, 0);
2928 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
2929 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2930 translate_kernel_address
, spapr
, NULL
,
2931 &lowaddr
, NULL
, NULL
, 0,
2934 spapr
->kernel_le
= spapr
->kernel_size
> 0;
2936 if (spapr
->kernel_size
< 0) {
2937 error_report("error loading %s: %s", kernel_filename
,
2938 load_elf_strerror(spapr
->kernel_size
));
2943 if (initrd_filename
) {
2944 /* Try to locate the initrd in the gap between the kernel
2945 * and the firmware. Add a bit of space just in case
2947 spapr
->initrd_base
= (spapr
->kernel_addr
+ spapr
->kernel_size
2948 + 0x1ffff) & ~0xffff;
2949 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
2952 - spapr
->initrd_base
);
2953 if (spapr
->initrd_size
< 0) {
2954 error_report("could not load initial ram disk '%s'",
2961 if (bios_name
== NULL
) {
2962 bios_name
= FW_FILE_NAME
;
2964 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
2966 error_report("Could not find LPAR firmware '%s'", bios_name
);
2969 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
2971 error_report("Could not load LPAR firmware '%s'", filename
);
2976 /* FIXME: Should register things through the MachineState's qdev
2977 * interface, this is a legacy from the sPAPREnvironment structure
2978 * which predated MachineState but had a similar function */
2979 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
2980 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY
, 1,
2981 &savevm_htab_handlers
, spapr
);
2983 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine
));
2985 qemu_register_boot_set(spapr_boot_set
, spapr
);
2988 * Nothing needs to be done to resume a suspended guest because
2989 * suspending does not change the machine state, so no need for
2990 * a ->wakeup method.
2992 qemu_register_wakeup_support();
2994 if (kvm_enabled()) {
2995 /* to stop and start vmclock */
2996 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
2999 kvmppc_spapr_enable_inkernel_multitce();
3002 qemu_cond_init(&spapr
->fwnmi_machine_check_interlock_cond
);
3005 static int spapr_kvm_type(MachineState
*machine
, const char *vm_type
)
3011 if (!strcmp(vm_type
, "HV")) {
3015 if (!strcmp(vm_type
, "PR")) {
3019 error_report("Unknown kvm-type specified '%s'", vm_type
);
3024 * Implementation of an interface to adjust firmware path
3025 * for the bootindex property handling.
3027 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
3030 #define CAST(type, obj, name) \
3031 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3032 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
3033 SpaprPhbState
*phb
= CAST(SpaprPhbState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
3034 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
3037 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
3038 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
3039 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
3043 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3044 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3045 * 0x8000 | (target << 8) | (bus << 5) | lun
3046 * (see the "Logical unit addressing format" table in SAM5)
3048 unsigned id
= 0x8000 | (d
->id
<< 8) | (d
->channel
<< 5) | d
->lun
;
3049 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3050 (uint64_t)id
<< 48);
3051 } else if (virtio
) {
3053 * We use SRP luns of the form 01000000 | (target << 8) | lun
3054 * in the top 32 bits of the 64-bit LUN
3055 * Note: the quote above is from SLOF and it is wrong,
3056 * the actual binding is:
3057 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3059 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
3060 if (d
->lun
>= 256) {
3061 /* Use the LUN "flat space addressing method" */
3064 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3065 (uint64_t)id
<< 32);
3068 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3069 * in the top 32 bits of the 64-bit LUN
3071 unsigned usb_port
= atoi(usb
->port
->path
);
3072 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
3073 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3074 (uint64_t)id
<< 32);
3079 * SLOF probes the USB devices, and if it recognizes that the device is a
3080 * storage device, it changes its name to "storage" instead of "usb-host",
3081 * and additionally adds a child node for the SCSI LUN, so the correct
3082 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3084 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
3085 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
3086 if (usb_host_dev_is_scsi_storage(usbdev
)) {
3087 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
3092 /* Replace "pci" with "pci@800000020000000" */
3093 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
3097 /* Same logic as virtio above */
3098 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
3099 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
3102 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
3103 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3104 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3105 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
3111 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
3113 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3115 return g_strdup(spapr
->kvm_type
);
3118 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
3120 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3122 g_free(spapr
->kvm_type
);
3123 spapr
->kvm_type
= g_strdup(value
);
3126 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
3128 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3130 return spapr
->use_hotplug_event_source
;
3133 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
3136 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3138 spapr
->use_hotplug_event_source
= value
;
3141 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
3146 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
3148 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3150 switch (spapr
->resize_hpt
) {
3151 case SPAPR_RESIZE_HPT_DEFAULT
:
3152 return g_strdup("default");
3153 case SPAPR_RESIZE_HPT_DISABLED
:
3154 return g_strdup("disabled");
3155 case SPAPR_RESIZE_HPT_ENABLED
:
3156 return g_strdup("enabled");
3157 case SPAPR_RESIZE_HPT_REQUIRED
:
3158 return g_strdup("required");
3160 g_assert_not_reached();
3163 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3165 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3167 if (strcmp(value
, "default") == 0) {
3168 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3169 } else if (strcmp(value
, "disabled") == 0) {
3170 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3171 } else if (strcmp(value
, "enabled") == 0) {
3172 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3173 } else if (strcmp(value
, "required") == 0) {
3174 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3176 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3180 static char *spapr_get_ic_mode(Object
*obj
, Error
**errp
)
3182 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3184 if (spapr
->irq
== &spapr_irq_xics_legacy
) {
3185 return g_strdup("legacy");
3186 } else if (spapr
->irq
== &spapr_irq_xics
) {
3187 return g_strdup("xics");
3188 } else if (spapr
->irq
== &spapr_irq_xive
) {
3189 return g_strdup("xive");
3190 } else if (spapr
->irq
== &spapr_irq_dual
) {
3191 return g_strdup("dual");
3193 g_assert_not_reached();
3196 static void spapr_set_ic_mode(Object
*obj
, const char *value
, Error
**errp
)
3198 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3200 if (SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
3201 error_setg(errp
, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3205 /* The legacy IRQ backend can not be set */
3206 if (strcmp(value
, "xics") == 0) {
3207 spapr
->irq
= &spapr_irq_xics
;
3208 } else if (strcmp(value
, "xive") == 0) {
3209 spapr
->irq
= &spapr_irq_xive
;
3210 } else if (strcmp(value
, "dual") == 0) {
3211 spapr
->irq
= &spapr_irq_dual
;
3213 error_setg(errp
, "Bad value for \"ic-mode\" property");
3217 static char *spapr_get_host_model(Object
*obj
, Error
**errp
)
3219 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3221 return g_strdup(spapr
->host_model
);
3224 static void spapr_set_host_model(Object
*obj
, const char *value
, Error
**errp
)
3226 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3228 g_free(spapr
->host_model
);
3229 spapr
->host_model
= g_strdup(value
);
3232 static char *spapr_get_host_serial(Object
*obj
, Error
**errp
)
3234 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3236 return g_strdup(spapr
->host_serial
);
3239 static void spapr_set_host_serial(Object
*obj
, const char *value
, Error
**errp
)
3241 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3243 g_free(spapr
->host_serial
);
3244 spapr
->host_serial
= g_strdup(value
);
3247 static void spapr_instance_init(Object
*obj
)
3249 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3250 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3252 spapr
->htab_fd
= -1;
3253 spapr
->use_hotplug_event_source
= true;
3254 object_property_add_str(obj
, "kvm-type",
3255 spapr_get_kvm_type
, spapr_set_kvm_type
);
3256 object_property_set_description(obj
, "kvm-type",
3257 "Specifies the KVM virtualization mode (HV, PR)");
3258 object_property_add_bool(obj
, "modern-hotplug-events",
3259 spapr_get_modern_hotplug_events
,
3260 spapr_set_modern_hotplug_events
);
3261 object_property_set_description(obj
, "modern-hotplug-events",
3262 "Use dedicated hotplug event mechanism in"
3263 " place of standard EPOW events when possible"
3264 " (required for memory hot-unplug support)");
3265 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3266 "Maximum permitted CPU compatibility mode");
3268 object_property_add_str(obj
, "resize-hpt",
3269 spapr_get_resize_hpt
, spapr_set_resize_hpt
);
3270 object_property_set_description(obj
, "resize-hpt",
3271 "Resizing of the Hash Page Table (enabled, disabled, required)");
3272 object_property_add_uint32_ptr(obj
, "vsmt",
3273 &spapr
->vsmt
, OBJ_PROP_FLAG_READWRITE
);
3274 object_property_set_description(obj
, "vsmt",
3275 "Virtual SMT: KVM behaves as if this were"
3276 " the host's SMT mode");
3278 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3279 spapr_get_msix_emulation
, NULL
);
3281 object_property_add_uint64_ptr(obj
, "kernel-addr",
3282 &spapr
->kernel_addr
, OBJ_PROP_FLAG_READWRITE
);
3283 object_property_set_description(obj
, "kernel-addr",
3284 stringify(KERNEL_LOAD_ADDR
)
3285 " for -kernel is the default");
3286 spapr
->kernel_addr
= KERNEL_LOAD_ADDR
;
3287 /* The machine class defines the default interrupt controller mode */
3288 spapr
->irq
= smc
->irq
;
3289 object_property_add_str(obj
, "ic-mode", spapr_get_ic_mode
,
3291 object_property_set_description(obj
, "ic-mode",
3292 "Specifies the interrupt controller mode (xics, xive, dual)");
3294 object_property_add_str(obj
, "host-model",
3295 spapr_get_host_model
, spapr_set_host_model
);
3296 object_property_set_description(obj
, "host-model",
3297 "Host model to advertise in guest device tree");
3298 object_property_add_str(obj
, "host-serial",
3299 spapr_get_host_serial
, spapr_set_host_serial
);
3300 object_property_set_description(obj
, "host-serial",
3301 "Host serial number to advertise in guest device tree");
3304 static void spapr_machine_finalizefn(Object
*obj
)
3306 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3308 g_free(spapr
->kvm_type
);
3311 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3313 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
3314 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3315 CPUPPCState
*env
= &cpu
->env
;
3317 cpu_synchronize_state(cs
);
3318 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */
3319 if (spapr
->fwnmi_system_reset_addr
!= -1) {
3320 uint64_t rtas_addr
, addr
;
3322 /* get rtas addr from fdt */
3323 rtas_addr
= spapr_get_rtas_addr();
3325 qemu_system_guest_panicked(NULL
);
3329 addr
= rtas_addr
+ RTAS_ERROR_LOG_MAX
+ cs
->cpu_index
* sizeof(uint64_t)*2;
3330 stq_be_phys(&address_space_memory
, addr
, env
->gpr
[3]);
3331 stq_be_phys(&address_space_memory
, addr
+ sizeof(uint64_t), 0);
3334 ppc_cpu_do_system_reset(cs
);
3335 if (spapr
->fwnmi_system_reset_addr
!= -1) {
3336 env
->nip
= spapr
->fwnmi_system_reset_addr
;
3340 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3345 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3349 int spapr_lmb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3350 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3355 addr
= spapr_drc_index(drc
) * SPAPR_MEMORY_BLOCK_SIZE
;
3356 node
= object_property_get_uint(OBJECT(drc
->dev
), PC_DIMM_NODE_PROP
,
3358 *fdt_start_offset
= spapr_dt_memory_node(spapr
, fdt
, node
, addr
,
3359 SPAPR_MEMORY_BLOCK_SIZE
);
3363 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3364 bool dedicated_hp_event_source
, Error
**errp
)
3367 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3369 uint64_t addr
= addr_start
;
3370 bool hotplugged
= spapr_drc_hotplugged(dev
);
3371 Error
*local_err
= NULL
;
3373 for (i
= 0; i
< nr_lmbs
; i
++) {
3374 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3375 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3378 spapr_drc_attach(drc
, dev
, &local_err
);
3380 while (addr
> addr_start
) {
3381 addr
-= SPAPR_MEMORY_BLOCK_SIZE
;
3382 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3383 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3384 spapr_drc_detach(drc
);
3386 error_propagate(errp
, local_err
);
3390 spapr_drc_reset(drc
);
3392 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3394 /* send hotplug notification to the
3395 * guest only in case of hotplugged memory
3398 if (dedicated_hp_event_source
) {
3399 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3400 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3401 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3403 spapr_drc_index(drc
));
3405 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3411 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3414 Error
*local_err
= NULL
;
3415 SpaprMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3416 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3417 uint64_t size
, addr
, slot
;
3418 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
3420 size
= memory_device_get_region_size(MEMORY_DEVICE(dev
), &error_abort
);
3422 pc_dimm_plug(dimm
, MACHINE(ms
), &local_err
);
3428 addr
= object_property_get_uint(OBJECT(dimm
),
3429 PC_DIMM_ADDR_PROP
, &local_err
);
3433 spapr_add_lmbs(dev
, addr
, size
,
3434 spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
),
3437 slot
= object_property_get_uint(OBJECT(dimm
),
3438 PC_DIMM_SLOT_PROP
, &local_err
);
3442 spapr_add_nvdimm(dev
, slot
, &local_err
);
3452 pc_dimm_unplug(dimm
, MACHINE(ms
));
3454 error_propagate(errp
, local_err
);
3457 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3460 const SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3461 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3462 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
3463 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3464 Error
*local_err
= NULL
;
3469 if (!smc
->dr_lmb_enabled
) {
3470 error_setg(errp
, "Memory hotplug not supported for this machine");
3474 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &local_err
);
3476 error_propagate(errp
, local_err
);
3481 spapr_nvdimm_validate(hotplug_dev
, NVDIMM(dev
), size
, &local_err
);
3483 error_propagate(errp
, local_err
);
3486 } else if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3487 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3488 "%" PRIu64
" MB", SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
3492 memdev
= object_property_get_link(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
,
3494 pagesize
= host_memory_backend_pagesize(MEMORY_BACKEND(memdev
));
3495 spapr_check_pagesize(spapr
, pagesize
, &local_err
);
3497 error_propagate(errp
, local_err
);
3501 pc_dimm_pre_plug(dimm
, MACHINE(hotplug_dev
), NULL
, errp
);
3504 struct SpaprDimmState
{
3507 QTAILQ_ENTRY(SpaprDimmState
) next
;
3510 static SpaprDimmState
*spapr_pending_dimm_unplugs_find(SpaprMachineState
*s
,
3513 SpaprDimmState
*dimm_state
= NULL
;
3515 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3516 if (dimm_state
->dimm
== dimm
) {
3523 static SpaprDimmState
*spapr_pending_dimm_unplugs_add(SpaprMachineState
*spapr
,
3527 SpaprDimmState
*ds
= NULL
;
3530 * If this request is for a DIMM whose removal had failed earlier
3531 * (due to guest's refusal to remove the LMBs), we would have this
3532 * dimm already in the pending_dimm_unplugs list. In that
3533 * case don't add again.
3535 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3537 ds
= g_malloc0(sizeof(SpaprDimmState
));
3538 ds
->nr_lmbs
= nr_lmbs
;
3540 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3545 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState
*spapr
,
3546 SpaprDimmState
*dimm_state
)
3548 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3552 static SpaprDimmState
*spapr_recover_pending_dimm_state(SpaprMachineState
*ms
,
3556 uint64_t size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
),
3558 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3559 uint32_t avail_lmbs
= 0;
3560 uint64_t addr_start
, addr
;
3563 addr_start
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3567 for (i
= 0; i
< nr_lmbs
; i
++) {
3568 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3569 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3574 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3577 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3580 /* Callback to be called during DRC release. */
3581 void spapr_lmb_release(DeviceState
*dev
)
3583 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3584 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3585 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3587 /* This information will get lost if a migration occurs
3588 * during the unplug process. In this case recover it. */
3590 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3592 /* The DRC being examined by the caller at least must be counted */
3593 g_assert(ds
->nr_lmbs
);
3596 if (--ds
->nr_lmbs
) {
3601 * Now that all the LMBs have been removed by the guest, call the
3602 * unplug handler chain. This can never fail.
3604 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3605 object_unparent(OBJECT(dev
));
3608 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3610 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3611 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3613 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(hotplug_dev
));
3614 qdev_unrealize(dev
);
3615 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3618 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3619 DeviceState
*dev
, Error
**errp
)
3621 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3622 Error
*local_err
= NULL
;
3623 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3625 uint64_t size
, addr_start
, addr
;
3629 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
3630 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
3634 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3635 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3637 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3640 error_propagate(errp
, local_err
);
3645 * An existing pending dimm state for this DIMM means that there is an
3646 * unplug operation in progress, waiting for the spapr_lmb_release
3647 * callback to complete the job (BQL can't cover that far). In this case,
3648 * bail out to avoid detaching DRCs that were already released.
3650 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3651 error_setg(errp
, "Memory unplug already in progress for device %s",
3656 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3659 for (i
= 0; i
< nr_lmbs
; i
++) {
3660 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3661 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3664 spapr_drc_detach(drc
);
3665 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3668 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3669 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3670 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3671 nr_lmbs
, spapr_drc_index(drc
));
3674 /* Callback to be called during DRC release. */
3675 void spapr_core_release(DeviceState
*dev
)
3677 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3679 /* Call the unplug handler chain. This can never fail. */
3680 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3681 object_unparent(OBJECT(dev
));
3684 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3686 MachineState
*ms
= MACHINE(hotplug_dev
);
3687 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3688 CPUCore
*cc
= CPU_CORE(dev
);
3689 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3691 if (smc
->pre_2_10_has_unused_icps
) {
3692 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3695 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3696 CPUState
*cs
= CPU(sc
->threads
[i
]);
3698 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3703 core_slot
->cpu
= NULL
;
3704 qdev_unrealize(dev
);
3708 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3711 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3714 CPUCore
*cc
= CPU_CORE(dev
);
3716 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3717 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3722 error_setg(errp
, "Boot CPU core may not be unplugged");
3726 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3727 spapr_vcpu_id(spapr
, cc
->core_id
));
3730 if (!spapr_drc_unplug_requested(drc
)) {
3731 spapr_drc_detach(drc
);
3732 spapr_hotplug_req_remove_by_index(drc
);
3736 int spapr_core_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3737 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3739 SpaprCpuCore
*core
= SPAPR_CPU_CORE(drc
->dev
);
3740 CPUState
*cs
= CPU(core
->threads
[0]);
3741 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3742 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3743 int id
= spapr_get_vcpu_id(cpu
);
3747 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3748 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3751 spapr_dt_cpu(cs
, fdt
, offset
, spapr
);
3753 *fdt_start_offset
= offset
;
3757 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3760 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3761 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3762 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3763 SpaprCpuCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3764 CPUCore
*cc
= CPU_CORE(dev
);
3767 Error
*local_err
= NULL
;
3768 CPUArchId
*core_slot
;
3770 bool hotplugged
= spapr_drc_hotplugged(dev
);
3773 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3775 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3779 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3780 spapr_vcpu_id(spapr
, cc
->core_id
));
3782 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3785 spapr_drc_attach(drc
, dev
, &local_err
);
3787 error_propagate(errp
, local_err
);
3793 * Send hotplug notification interrupt to the guest only
3794 * in case of hotplugged CPUs.
3796 spapr_hotplug_req_add_by_index(drc
);
3798 spapr_drc_reset(drc
);
3802 core_slot
->cpu
= OBJECT(dev
);
3804 if (smc
->pre_2_10_has_unused_icps
) {
3805 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3806 cs
= CPU(core
->threads
[i
]);
3807 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
3812 * Set compatibility mode to match the boot CPU, which was either set
3813 * by the machine reset code or by CAS.
3816 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3817 ppc_set_compat(core
->threads
[i
], POWERPC_CPU(first_cpu
)->compat_pvr
,
3820 error_propagate(errp
, local_err
);
3827 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3830 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
3831 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
3832 CPUCore
*cc
= CPU_CORE(dev
);
3833 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3834 const char *type
= object_get_typename(OBJECT(dev
));
3835 CPUArchId
*core_slot
;
3837 unsigned int smp_threads
= machine
->smp
.threads
;
3839 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
3840 error_setg(errp
, "CPU hotplug not supported for this machine");
3844 if (strcmp(base_core_type
, type
)) {
3845 error_setg(errp
, "CPU core type should be %s", base_core_type
);
3849 if (cc
->core_id
% smp_threads
) {
3850 error_setg(errp
, "invalid core id %d", cc
->core_id
);
3855 * In general we should have homogeneous threads-per-core, but old
3856 * (pre hotplug support) machine types allow the last core to have
3857 * reduced threads as a compatibility hack for when we allowed
3858 * total vcpus not a multiple of threads-per-core.
3860 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
3861 error_setg(errp
, "invalid nr-threads %d, must be %d", cc
->nr_threads
,
3866 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3868 error_setg(errp
, "core id %d out of range", cc
->core_id
);
3872 if (core_slot
->cpu
) {
3873 error_setg(errp
, "core %d already populated", cc
->core_id
);
3877 numa_cpu_pre_plug(core_slot
, dev
, errp
);
3880 int spapr_phb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3881 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3883 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(drc
->dev
);
3886 intc_phandle
= spapr_irq_get_phandle(spapr
, spapr
->fdt_blob
, errp
);
3887 if (intc_phandle
<= 0) {
3891 if (spapr_dt_phb(spapr
, sphb
, intc_phandle
, fdt
, fdt_start_offset
)) {
3892 error_setg(errp
, "unable to create FDT node for PHB %d", sphb
->index
);
3896 /* generally SLOF creates these, for hotplug it's up to QEMU */
3897 _FDT(fdt_setprop_string(fdt
, *fdt_start_offset
, "name", "pci"));
3902 static void spapr_phb_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3905 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3906 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3907 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3908 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
3910 if (dev
->hotplugged
&& !smc
->dr_phb_enabled
) {
3911 error_setg(errp
, "PHB hotplug not supported for this machine");
3915 if (sphb
->index
== (uint32_t)-1) {
3916 error_setg(errp
, "\"index\" for PAPR PHB is mandatory");
3921 * This will check that sphb->index doesn't exceed the maximum number of
3922 * PHBs for the current machine type.
3924 smc
->phb_placement(spapr
, sphb
->index
,
3925 &sphb
->buid
, &sphb
->io_win_addr
,
3926 &sphb
->mem_win_addr
, &sphb
->mem64_win_addr
,
3927 windows_supported
, sphb
->dma_liobn
,
3928 &sphb
->nv2_gpa_win_addr
, &sphb
->nv2_atsd_win_addr
,
3932 static void spapr_phb_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3935 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3936 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3937 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3939 bool hotplugged
= spapr_drc_hotplugged(dev
);
3940 Error
*local_err
= NULL
;
3942 if (!smc
->dr_phb_enabled
) {
3946 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
3947 /* hotplug hooks should check it's enabled before getting this far */
3950 spapr_drc_attach(drc
, dev
, &local_err
);
3952 error_propagate(errp
, local_err
);
3957 spapr_hotplug_req_add_by_index(drc
);
3959 spapr_drc_reset(drc
);
3963 void spapr_phb_release(DeviceState
*dev
)
3965 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3967 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3968 object_unparent(OBJECT(dev
));
3971 static void spapr_phb_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3973 qdev_unrealize(dev
);
3976 static void spapr_phb_unplug_request(HotplugHandler
*hotplug_dev
,
3977 DeviceState
*dev
, Error
**errp
)
3979 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3982 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
3985 if (!spapr_drc_unplug_requested(drc
)) {
3986 spapr_drc_detach(drc
);
3987 spapr_hotplug_req_remove_by_index(drc
);
3991 static void spapr_tpm_proxy_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3994 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3995 SpaprTpmProxy
*tpm_proxy
= SPAPR_TPM_PROXY(dev
);
3997 if (spapr
->tpm_proxy
!= NULL
) {
3998 error_setg(errp
, "Only one TPM proxy can be specified for this machine");
4002 spapr
->tpm_proxy
= tpm_proxy
;
4005 static void spapr_tpm_proxy_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4007 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4009 qdev_unrealize(dev
);
4010 object_unparent(OBJECT(dev
));
4011 spapr
->tpm_proxy
= NULL
;
4014 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
4015 DeviceState
*dev
, Error
**errp
)
4017 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4018 spapr_memory_plug(hotplug_dev
, dev
, errp
);
4019 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4020 spapr_core_plug(hotplug_dev
, dev
, errp
);
4021 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4022 spapr_phb_plug(hotplug_dev
, dev
, errp
);
4023 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4024 spapr_tpm_proxy_plug(hotplug_dev
, dev
, errp
);
4028 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
4029 DeviceState
*dev
, Error
**errp
)
4031 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4032 spapr_memory_unplug(hotplug_dev
, dev
);
4033 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4034 spapr_core_unplug(hotplug_dev
, dev
);
4035 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4036 spapr_phb_unplug(hotplug_dev
, dev
);
4037 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4038 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4042 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
4043 DeviceState
*dev
, Error
**errp
)
4045 SpaprMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4046 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
4047 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4049 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4050 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
4051 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
4053 /* NOTE: this means there is a window after guest reset, prior to
4054 * CAS negotiation, where unplug requests will fail due to the
4055 * capability not being detected yet. This is a bit different than
4056 * the case with PCI unplug, where the events will be queued and
4057 * eventually handled by the guest after boot
4059 error_setg(errp
, "Memory hot unplug not supported for this guest");
4061 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4062 if (!mc
->has_hotpluggable_cpus
) {
4063 error_setg(errp
, "CPU hot unplug not supported on this machine");
4066 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
4067 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4068 if (!smc
->dr_phb_enabled
) {
4069 error_setg(errp
, "PHB hot unplug not supported on this machine");
4072 spapr_phb_unplug_request(hotplug_dev
, dev
, errp
);
4073 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4074 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4078 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
4079 DeviceState
*dev
, Error
**errp
)
4081 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4082 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
4083 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4084 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
4085 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4086 spapr_phb_pre_plug(hotplug_dev
, dev
, errp
);
4090 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
4093 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
4094 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
) ||
4095 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
) ||
4096 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4097 return HOTPLUG_HANDLER(machine
);
4099 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_DEVICE
)) {
4100 PCIDevice
*pcidev
= PCI_DEVICE(dev
);
4101 PCIBus
*root
= pci_device_root_bus(pcidev
);
4102 SpaprPhbState
*phb
=
4103 (SpaprPhbState
*)object_dynamic_cast(OBJECT(BUS(root
)->parent
),
4104 TYPE_SPAPR_PCI_HOST_BRIDGE
);
4107 return HOTPLUG_HANDLER(phb
);
4113 static CpuInstanceProperties
4114 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
4116 CPUArchId
*core_slot
;
4117 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4119 /* make sure possible_cpu are intialized */
4120 mc
->possible_cpu_arch_ids(machine
);
4121 /* get CPU core slot containing thread that matches cpu_index */
4122 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
4124 return core_slot
->props
;
4127 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
4129 return idx
/ ms
->smp
.cores
% ms
->numa_state
->num_nodes
;
4132 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
4135 unsigned int smp_threads
= machine
->smp
.threads
;
4136 unsigned int smp_cpus
= machine
->smp
.cpus
;
4137 const char *core_type
;
4138 int spapr_max_cores
= machine
->smp
.max_cpus
/ smp_threads
;
4139 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4141 if (!mc
->has_hotpluggable_cpus
) {
4142 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
4144 if (machine
->possible_cpus
) {
4145 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
4146 return machine
->possible_cpus
;
4149 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
4151 error_report("Unable to find sPAPR CPU Core definition");
4155 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
4156 sizeof(CPUArchId
) * spapr_max_cores
);
4157 machine
->possible_cpus
->len
= spapr_max_cores
;
4158 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
4159 int core_id
= i
* smp_threads
;
4161 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
4162 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
4163 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
4164 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
4165 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
4167 return machine
->possible_cpus
;
4170 static void spapr_phb_placement(SpaprMachineState
*spapr
, uint32_t index
,
4171 uint64_t *buid
, hwaddr
*pio
,
4172 hwaddr
*mmio32
, hwaddr
*mmio64
,
4173 unsigned n_dma
, uint32_t *liobns
,
4174 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4177 * New-style PHB window placement.
4179 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4180 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4183 * Some guest kernels can't work with MMIO windows above 1<<46
4184 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4186 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4187 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
4188 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
4189 * 1TiB 64-bit MMIO windows for each PHB.
4191 const uint64_t base_buid
= 0x800000020000000ULL
;
4194 /* Sanity check natural alignments */
4195 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4196 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4197 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
4198 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
4199 /* Sanity check bounds */
4200 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
4201 SPAPR_PCI_MEM32_WIN_SIZE
);
4202 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
4203 SPAPR_PCI_MEM64_WIN_SIZE
);
4205 if (index
>= SPAPR_MAX_PHBS
) {
4206 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
4207 SPAPR_MAX_PHBS
- 1);
4211 *buid
= base_buid
+ index
;
4212 for (i
= 0; i
< n_dma
; ++i
) {
4213 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4216 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
4217 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
4218 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
4220 *nv2gpa
= SPAPR_PCI_NV2RAM64_WIN_BASE
+ index
* SPAPR_PCI_NV2RAM64_WIN_SIZE
;
4221 *nv2atsd
= SPAPR_PCI_NV2ATSD_WIN_BASE
+ index
* SPAPR_PCI_NV2ATSD_WIN_SIZE
;
4224 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
4226 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4228 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
4231 static void spapr_ics_resend(XICSFabric
*dev
)
4233 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4235 ics_resend(spapr
->ics
);
4238 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
4240 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
4242 return cpu
? spapr_cpu_state(cpu
)->icp
: NULL
;
4245 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
4248 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
4250 spapr_irq_print_info(spapr
, mon
);
4251 monitor_printf(mon
, "irqchip: %s\n",
4252 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
4256 * This is a XIVE only operation
4258 static int spapr_match_nvt(XiveFabric
*xfb
, uint8_t format
,
4259 uint8_t nvt_blk
, uint32_t nvt_idx
,
4260 bool cam_ignore
, uint8_t priority
,
4261 uint32_t logic_serv
, XiveTCTXMatch
*match
)
4263 SpaprMachineState
*spapr
= SPAPR_MACHINE(xfb
);
4264 XivePresenter
*xptr
= XIVE_PRESENTER(spapr
->active_intc
);
4265 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
4268 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
4269 priority
, logic_serv
, match
);
4275 * When we implement the save and restore of the thread interrupt
4276 * contexts in the enter/exit CPU handlers of the machine and the
4277 * escalations in QEMU, we should be able to handle non dispatched
4280 * Until this is done, the sPAPR machine should find at least one
4281 * matching context always.
4284 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: NVT %x/%x is not dispatched\n",
4291 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
4293 return cpu
->vcpu_id
;
4296 void spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
4298 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
4299 MachineState
*ms
= MACHINE(spapr
);
4302 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
4304 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
4305 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
4306 error_append_hint(errp
, "Adjust the number of cpus to %d "
4307 "or try to raise the number of threads per core\n",
4308 vcpu_id
* ms
->smp
.threads
/ spapr
->vsmt
);
4312 cpu
->vcpu_id
= vcpu_id
;
4315 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
4320 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
4322 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
4330 static void spapr_cpu_exec_enter(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4332 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4334 /* These are only called by TCG, KVM maintains dispatch state */
4336 spapr_cpu
->prod
= false;
4337 if (spapr_cpu
->vpa_addr
) {
4338 CPUState
*cs
= CPU(cpu
);
4341 dispatch
= ldl_be_phys(cs
->as
,
4342 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4344 if ((dispatch
& 1) != 0) {
4345 qemu_log_mask(LOG_GUEST_ERROR
,
4346 "VPA: incorrect dispatch counter value for "
4347 "dispatched partition %u, correcting.\n", dispatch
);
4351 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4355 static void spapr_cpu_exec_exit(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4357 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4359 if (spapr_cpu
->vpa_addr
) {
4360 CPUState
*cs
= CPU(cpu
);
4363 dispatch
= ldl_be_phys(cs
->as
,
4364 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4366 if ((dispatch
& 1) != 1) {
4367 qemu_log_mask(LOG_GUEST_ERROR
,
4368 "VPA: incorrect dispatch counter value for "
4369 "preempted partition %u, correcting.\n", dispatch
);
4373 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4377 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
4379 MachineClass
*mc
= MACHINE_CLASS(oc
);
4380 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
4381 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
4382 NMIClass
*nc
= NMI_CLASS(oc
);
4383 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
4384 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
4385 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
4386 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
4387 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
4389 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
4390 mc
->ignore_boot_device_suffixes
= true;
4393 * We set up the default / latest behaviour here. The class_init
4394 * functions for the specific versioned machine types can override
4395 * these details for backwards compatibility
4397 mc
->init
= spapr_machine_init
;
4398 mc
->reset
= spapr_machine_reset
;
4399 mc
->block_default_type
= IF_SCSI
;
4400 mc
->max_cpus
= 1024;
4401 mc
->no_parallel
= 1;
4402 mc
->default_boot_order
= "";
4403 mc
->default_ram_size
= 512 * MiB
;
4404 mc
->default_ram_id
= "ppc_spapr.ram";
4405 mc
->default_display
= "std";
4406 mc
->kvm_type
= spapr_kvm_type
;
4407 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
4408 mc
->pci_allow_0_address
= true;
4409 assert(!mc
->get_hotplug_handler
);
4410 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
4411 hc
->pre_plug
= spapr_machine_device_pre_plug
;
4412 hc
->plug
= spapr_machine_device_plug
;
4413 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
4414 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
4415 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
4416 hc
->unplug_request
= spapr_machine_device_unplug_request
;
4417 hc
->unplug
= spapr_machine_device_unplug
;
4419 smc
->dr_lmb_enabled
= true;
4420 smc
->update_dt_enabled
= true;
4421 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
4422 mc
->has_hotpluggable_cpus
= true;
4423 mc
->nvdimm_supported
= true;
4424 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
4425 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
4426 nc
->nmi_monitor_handler
= spapr_nmi
;
4427 smc
->phb_placement
= spapr_phb_placement
;
4428 vhc
->hypercall
= emulate_spapr_hypercall
;
4429 vhc
->hpt_mask
= spapr_hpt_mask
;
4430 vhc
->map_hptes
= spapr_map_hptes
;
4431 vhc
->unmap_hptes
= spapr_unmap_hptes
;
4432 vhc
->hpte_set_c
= spapr_hpte_set_c
;
4433 vhc
->hpte_set_r
= spapr_hpte_set_r
;
4434 vhc
->get_pate
= spapr_get_pate
;
4435 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
4436 vhc
->cpu_exec_enter
= spapr_cpu_exec_enter
;
4437 vhc
->cpu_exec_exit
= spapr_cpu_exec_exit
;
4438 xic
->ics_get
= spapr_ics_get
;
4439 xic
->ics_resend
= spapr_ics_resend
;
4440 xic
->icp_get
= spapr_icp_get
;
4441 ispc
->print_info
= spapr_pic_print_info
;
4442 /* Force NUMA node memory size to be a multiple of
4443 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4444 * in which LMBs are represented and hot-added
4446 mc
->numa_mem_align_shift
= 28;
4447 mc
->auto_enable_numa
= true;
4449 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
4450 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
4451 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
4452 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4453 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4454 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_WORKAROUND
;
4455 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 16; /* 64kiB */
4456 smc
->default_caps
.caps
[SPAPR_CAP_NESTED_KVM_HV
] = SPAPR_CAP_OFF
;
4457 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_ON
;
4458 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_ON
;
4459 smc
->default_caps
.caps
[SPAPR_CAP_FWNMI
] = SPAPR_CAP_ON
;
4460 spapr_caps_add_properties(smc
);
4461 smc
->irq
= &spapr_irq_dual
;
4462 smc
->dr_phb_enabled
= true;
4463 smc
->linux_pci_probe
= true;
4464 smc
->smp_threads_vsmt
= true;
4465 smc
->nr_xirqs
= SPAPR_NR_XIRQS
;
4466 xfc
->match_nvt
= spapr_match_nvt
;
4469 static const TypeInfo spapr_machine_info
= {
4470 .name
= TYPE_SPAPR_MACHINE
,
4471 .parent
= TYPE_MACHINE
,
4473 .instance_size
= sizeof(SpaprMachineState
),
4474 .instance_init
= spapr_instance_init
,
4475 .instance_finalize
= spapr_machine_finalizefn
,
4476 .class_size
= sizeof(SpaprMachineClass
),
4477 .class_init
= spapr_machine_class_init
,
4478 .interfaces
= (InterfaceInfo
[]) {
4479 { TYPE_FW_PATH_PROVIDER
},
4481 { TYPE_HOTPLUG_HANDLER
},
4482 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
4483 { TYPE_XICS_FABRIC
},
4484 { TYPE_INTERRUPT_STATS_PROVIDER
},
4485 { TYPE_XIVE_FABRIC
},
4490 static void spapr_machine_latest_class_options(MachineClass
*mc
)
4492 mc
->alias
= "pseries";
4493 mc
->is_default
= true;
4496 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4497 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4500 MachineClass *mc = MACHINE_CLASS(oc); \
4501 spapr_machine_##suffix##_class_options(mc); \
4503 spapr_machine_latest_class_options(mc); \
4506 static const TypeInfo spapr_machine_##suffix##_info = { \
4507 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4508 .parent = TYPE_SPAPR_MACHINE, \
4509 .class_init = spapr_machine_##suffix##_class_init, \
4511 static void spapr_machine_register_##suffix(void) \
4513 type_register(&spapr_machine_##suffix##_info); \
4515 type_init(spapr_machine_register_##suffix)
4520 static void spapr_machine_5_2_class_options(MachineClass
*mc
)
4522 /* Defaults for the latest behaviour inherited from the base class */
4525 DEFINE_SPAPR_MACHINE(5_2
, "5.2", true);
4530 static void spapr_machine_5_1_class_options(MachineClass
*mc
)
4532 spapr_machine_5_2_class_options(mc
);
4533 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
4536 DEFINE_SPAPR_MACHINE(5_1
, "5.1", false);
4541 static void spapr_machine_5_0_class_options(MachineClass
*mc
)
4543 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4544 static GlobalProperty compat
[] = {
4545 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-5.1-associativity", "on" },
4548 spapr_machine_5_1_class_options(mc
);
4549 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
4550 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4551 mc
->numa_mem_supported
= true;
4552 smc
->pre_5_1_assoc_refpoints
= true;
4555 DEFINE_SPAPR_MACHINE(5_0
, "5.0", false);
4560 static void spapr_machine_4_2_class_options(MachineClass
*mc
)
4562 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4564 spapr_machine_5_0_class_options(mc
);
4565 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
4566 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_OFF
;
4567 smc
->default_caps
.caps
[SPAPR_CAP_FWNMI
] = SPAPR_CAP_OFF
;
4568 smc
->rma_limit
= 16 * GiB
;
4569 mc
->nvdimm_supported
= false;
4572 DEFINE_SPAPR_MACHINE(4_2
, "4.2", false);
4577 static void spapr_machine_4_1_class_options(MachineClass
*mc
)
4579 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4580 static GlobalProperty compat
[] = {
4581 /* Only allow 4kiB and 64kiB IOMMU pagesizes */
4582 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pgsz", "0x11000" },
4585 spapr_machine_4_2_class_options(mc
);
4586 smc
->linux_pci_probe
= false;
4587 smc
->smp_threads_vsmt
= false;
4588 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
4589 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4592 DEFINE_SPAPR_MACHINE(4_1
, "4.1", false);
4597 static void phb_placement_4_0(SpaprMachineState
*spapr
, uint32_t index
,
4598 uint64_t *buid
, hwaddr
*pio
,
4599 hwaddr
*mmio32
, hwaddr
*mmio64
,
4600 unsigned n_dma
, uint32_t *liobns
,
4601 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4603 spapr_phb_placement(spapr
, index
, buid
, pio
, mmio32
, mmio64
, n_dma
, liobns
,
4604 nv2gpa
, nv2atsd
, errp
);
4609 static void spapr_machine_4_0_class_options(MachineClass
*mc
)
4611 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4613 spapr_machine_4_1_class_options(mc
);
4614 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
4615 smc
->phb_placement
= phb_placement_4_0
;
4616 smc
->irq
= &spapr_irq_xics
;
4617 smc
->pre_4_1_migration
= true;
4620 DEFINE_SPAPR_MACHINE(4_0
, "4.0", false);
4625 static void spapr_machine_3_1_class_options(MachineClass
*mc
)
4627 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4629 spapr_machine_4_0_class_options(mc
);
4630 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
4632 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4633 smc
->update_dt_enabled
= false;
4634 smc
->dr_phb_enabled
= false;
4635 smc
->broken_host_serial_model
= true;
4636 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
4637 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
4638 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
4639 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_OFF
;
4642 DEFINE_SPAPR_MACHINE(3_1
, "3.1", false);
4648 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
4650 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4652 spapr_machine_3_1_class_options(mc
);
4653 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
4655 smc
->legacy_irq_allocation
= true;
4656 smc
->nr_xirqs
= 0x400;
4657 smc
->irq
= &spapr_irq_xics_legacy
;
4660 DEFINE_SPAPR_MACHINE(3_0
, "3.0", false);
4665 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
4667 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4668 static GlobalProperty compat
[] = {
4669 { TYPE_POWERPC_CPU
, "pre-3.0-migration", "on" },
4670 { TYPE_SPAPR_CPU_CORE
, "pre-3.0-migration", "on" },
4673 spapr_machine_3_0_class_options(mc
);
4674 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
4675 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4677 /* We depend on kvm_enabled() to choose a default value for the
4678 * hpt-max-page-size capability. Of course we can't do it here
4679 * because this is too early and the HW accelerator isn't initialzed
4680 * yet. Postpone this to machine init (see default_caps_with_cpu()).
4682 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 0;
4685 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
4687 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
4689 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4691 spapr_machine_2_12_class_options(mc
);
4692 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4693 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4694 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
4697 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
4703 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
4705 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4707 spapr_machine_2_12_class_options(mc
);
4708 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
4709 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
4712 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
4718 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
4720 spapr_machine_2_11_class_options(mc
);
4721 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
4724 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
4730 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
4732 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4733 static GlobalProperty compat
[] = {
4734 { TYPE_POWERPC_CPU
, "pre-2.10-migration", "on" },
4737 spapr_machine_2_10_class_options(mc
);
4738 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
4739 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4740 mc
->numa_auto_assign_ram
= numa_legacy_auto_assign_ram
;
4741 smc
->pre_2_10_has_unused_icps
= true;
4742 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
4745 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
4751 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
4753 static GlobalProperty compat
[] = {
4754 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pcie-extended-configuration-space", "off" },
4757 spapr_machine_2_9_class_options(mc
);
4758 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
4759 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4760 mc
->numa_mem_align_shift
= 23;
4763 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
4769 static void phb_placement_2_7(SpaprMachineState
*spapr
, uint32_t index
,
4770 uint64_t *buid
, hwaddr
*pio
,
4771 hwaddr
*mmio32
, hwaddr
*mmio64
,
4772 unsigned n_dma
, uint32_t *liobns
,
4773 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4775 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4776 const uint64_t base_buid
= 0x800000020000000ULL
;
4777 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
4778 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
4779 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
4780 const uint32_t max_index
= 255;
4781 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
4783 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
4784 hwaddr phb0_base
, phb_base
;
4787 /* Do we have device memory? */
4788 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
4789 /* Can't just use maxram_size, because there may be an
4790 * alignment gap between normal and device memory regions
4792 ram_top
= MACHINE(spapr
)->device_memory
->base
+
4793 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
4796 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
4798 if (index
> max_index
) {
4799 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
4804 *buid
= base_buid
+ index
;
4805 for (i
= 0; i
< n_dma
; ++i
) {
4806 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4809 phb_base
= phb0_base
+ index
* phb_spacing
;
4810 *pio
= phb_base
+ pio_offset
;
4811 *mmio32
= phb_base
+ mmio_offset
;
4813 * We don't set the 64-bit MMIO window, relying on the PHB's
4814 * fallback behaviour of automatically splitting a large "32-bit"
4815 * window into contiguous 32-bit and 64-bit windows
4822 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
4824 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4825 static GlobalProperty compat
[] = {
4826 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0xf80000000", },
4827 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem64_win_size", "0", },
4828 { TYPE_POWERPC_CPU
, "pre-2.8-migration", "on", },
4829 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-2.8-migration", "on", },
4832 spapr_machine_2_8_class_options(mc
);
4833 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
4834 mc
->default_machine_opts
= "modern-hotplug-events=off";
4835 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
4836 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4837 smc
->phb_placement
= phb_placement_2_7
;
4840 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
4846 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
4848 static GlobalProperty compat
[] = {
4849 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "ddw", "off" },
4852 spapr_machine_2_7_class_options(mc
);
4853 mc
->has_hotpluggable_cpus
= false;
4854 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
4855 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4858 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
4864 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
4866 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4867 static GlobalProperty compat
[] = {
4868 { "spapr-vlan", "use-rx-buffer-pools", "off" },
4871 spapr_machine_2_6_class_options(mc
);
4872 smc
->use_ohci_by_default
= true;
4873 compat_props_add(mc
->compat_props
, hw_compat_2_5
, hw_compat_2_5_len
);
4874 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4877 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
4883 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
4885 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4887 spapr_machine_2_5_class_options(mc
);
4888 smc
->dr_lmb_enabled
= false;
4889 compat_props_add(mc
->compat_props
, hw_compat_2_4
, hw_compat_2_4_len
);
4892 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
4898 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
4900 static GlobalProperty compat
[] = {
4901 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4903 spapr_machine_2_4_class_options(mc
);
4904 compat_props_add(mc
->compat_props
, hw_compat_2_3
, hw_compat_2_3_len
);
4905 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4907 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
4913 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
4915 static GlobalProperty compat
[] = {
4916 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0x20000000" },
4919 spapr_machine_2_3_class_options(mc
);
4920 compat_props_add(mc
->compat_props
, hw_compat_2_2
, hw_compat_2_2_len
);
4921 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4922 mc
->default_machine_opts
= "modern-hotplug-events=off,suppress-vmdesc=on";
4924 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
4930 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
4932 spapr_machine_2_2_class_options(mc
);
4933 compat_props_add(mc
->compat_props
, hw_compat_2_1
, hw_compat_2_1_len
);
4935 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
4937 static void spapr_machine_register_types(void)
4939 type_register_static(&spapr_machine_info
);
4942 type_init(spapr_machine_register_types
)