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Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / target-i386 / cpu.c
blobe94613fcd7596fb0aa811d96667c60fab3f31f39
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu-common.h"
21 #include "cpu.h"
22 #include "sysemu/kvm.h"
23 #include "sysemu/cpus.h"
24 #include "kvm_i386.h"
25 #include "topology.h"
26
27 #include "qemu/option.h"
28 #include "qemu/config-file.h"
29 #include "qapi/qmp/qerror.h"
30
31 #include "qapi-types.h"
32 #include "qapi-visit.h"
33 #include "qapi/visitor.h"
34 #include "sysemu/arch_init.h"
35
36 #include "hw/hw.h"
37 #if defined(CONFIG_KVM)
38 #include <linux/kvm_para.h>
39 #endif
40
41 #include "sysemu/sysemu.h"
42 #include "hw/qdev-properties.h"
43 #include "hw/cpu/icc_bus.h"
44 #ifndef CONFIG_USER_ONLY
45 #include "hw/xen/xen.h"
46 #include "hw/i386/apic_internal.h"
47 #endif
48
49
50 /* Cache topology CPUID constants: */
51
52 /* CPUID Leaf 2 Descriptors */
53
54 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
55 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
56 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
57
58
59 /* CPUID Leaf 4 constants: */
60
61 /* EAX: */
62 #define CPUID_4_TYPE_DCACHE 1
63 #define CPUID_4_TYPE_ICACHE 2
64 #define CPUID_4_TYPE_UNIFIED 3
65
66 #define CPUID_4_LEVEL(l) ((l) << 5)
67
68 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
69 #define CPUID_4_FULLY_ASSOC (1 << 9)
70
71 /* EDX: */
72 #define CPUID_4_NO_INVD_SHARING (1 << 0)
73 #define CPUID_4_INCLUSIVE (1 << 1)
74 #define CPUID_4_COMPLEX_IDX (1 << 2)
75
76 #define ASSOC_FULL 0xFF
77
78 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
79 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
80 a == 2 ? 0x2 : \
81 a == 4 ? 0x4 : \
82 a == 8 ? 0x6 : \
83 a == 16 ? 0x8 : \
84 a == 32 ? 0xA : \
85 a == 48 ? 0xB : \
86 a == 64 ? 0xC : \
87 a == 96 ? 0xD : \
88 a == 128 ? 0xE : \
89 a == ASSOC_FULL ? 0xF : \
90 0 /* invalid value */)
91
92
93 /* Definitions of the hardcoded cache entries we expose: */
94
95 /* L1 data cache: */
96 #define L1D_LINE_SIZE 64
97 #define L1D_ASSOCIATIVITY 8
98 #define L1D_SETS 64
99 #define L1D_PARTITIONS 1
100 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
101 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
102 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
103 #define L1D_LINES_PER_TAG 1
104 #define L1D_SIZE_KB_AMD 64
105 #define L1D_ASSOCIATIVITY_AMD 2
106
107 /* L1 instruction cache: */
108 #define L1I_LINE_SIZE 64
109 #define L1I_ASSOCIATIVITY 8
110 #define L1I_SETS 64
111 #define L1I_PARTITIONS 1
112 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
113 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
114 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
115 #define L1I_LINES_PER_TAG 1
116 #define L1I_SIZE_KB_AMD 64
117 #define L1I_ASSOCIATIVITY_AMD 2
118
119 /* Level 2 unified cache: */
120 #define L2_LINE_SIZE 64
121 #define L2_ASSOCIATIVITY 16
122 #define L2_SETS 4096
123 #define L2_PARTITIONS 1
124 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
125 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
126 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
127 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
128 #define L2_LINES_PER_TAG 1
129 #define L2_SIZE_KB_AMD 512
130
131 /* No L3 cache: */
132 #define L3_SIZE_KB 0 /* disabled */
133 #define L3_ASSOCIATIVITY 0 /* disabled */
134 #define L3_LINES_PER_TAG 0 /* disabled */
135 #define L3_LINE_SIZE 0 /* disabled */
136
137 /* TLB definitions: */
138
139 #define L1_DTLB_2M_ASSOC 1
140 #define L1_DTLB_2M_ENTRIES 255
141 #define L1_DTLB_4K_ASSOC 1
142 #define L1_DTLB_4K_ENTRIES 255
143
144 #define L1_ITLB_2M_ASSOC 1
145 #define L1_ITLB_2M_ENTRIES 255
146 #define L1_ITLB_4K_ASSOC 1
147 #define L1_ITLB_4K_ENTRIES 255
148
149 #define L2_DTLB_2M_ASSOC 0 /* disabled */
150 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
151 #define L2_DTLB_4K_ASSOC 4
152 #define L2_DTLB_4K_ENTRIES 512
153
154 #define L2_ITLB_2M_ASSOC 0 /* disabled */
155 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
156 #define L2_ITLB_4K_ASSOC 4
157 #define L2_ITLB_4K_ENTRIES 512
158
159
160
161 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
162 uint32_t vendor2, uint32_t vendor3)
163 {
164 int i;
165 for (i = 0; i < 4; i++) {
166 dst[i] = vendor1 >> (8 * i);
167 dst[i + 4] = vendor2 >> (8 * i);
168 dst[i + 8] = vendor3 >> (8 * i);
169 }
170 dst[CPUID_VENDOR_SZ] = '\0';
171 }
172
173 /* feature flags taken from "Intel Processor Identification and the CPUID
174 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
175 * between feature naming conventions, aliases may be added.
176 */
177 static const char *feature_name[] = {
178 "fpu", "vme", "de", "pse",
179 "tsc", "msr", "pae", "mce",
180 "cx8", "apic", NULL, "sep",
181 "mtrr", "pge", "mca", "cmov",
182 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
183 NULL, "ds" /* Intel dts */, "acpi", "mmx",
184 "fxsr", "sse", "sse2", "ss",
185 "ht" /* Intel htt */, "tm", "ia64", "pbe",
186 };
187 static const char *ext_feature_name[] = {
188 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
189 "ds_cpl", "vmx", "smx", "est",
190 "tm2", "ssse3", "cid", NULL,
191 "fma", "cx16", "xtpr", "pdcm",
192 NULL, "pcid", "dca", "sse4.1|sse4_1",
193 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
194 "tsc-deadline", "aes", "xsave", "osxsave",
195 "avx", "f16c", "rdrand", "hypervisor",
196 };
197 /* Feature names that are already defined on feature_name[] but are set on
198 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
199 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
200 * if and only if CPU vendor is AMD.
201 */
202 static const char *ext2_feature_name[] = {
203 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
204 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
205 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
206 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
207 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
208 "nx|xd", NULL, "mmxext", NULL /* mmx */,
209 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
210 NULL, "lm|i64", "3dnowext", "3dnow",
211 };
212 static const char *ext3_feature_name[] = {
213 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
214 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
215 "3dnowprefetch", "osvw", "ibs", "xop",
216 "skinit", "wdt", NULL, "lwp",
217 "fma4", "tce", NULL, "nodeid_msr",
218 NULL, "tbm", "topoext", "perfctr_core",
219 "perfctr_nb", NULL, NULL, NULL,
220 NULL, NULL, NULL, NULL,
221 };
222
223 static const char *ext4_feature_name[] = {
224 NULL, NULL, "xstore", "xstore-en",
225 NULL, NULL, "xcrypt", "xcrypt-en",
226 "ace2", "ace2-en", "phe", "phe-en",
227 "pmm", "pmm-en", NULL, NULL,
228 NULL, NULL, NULL, NULL,
229 NULL, NULL, NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 };
233
234 static const char *kvm_feature_name[] = {
235 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
236 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
237 NULL, NULL, NULL, NULL,
238 NULL, NULL, NULL, NULL,
239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 "kvmclock-stable-bit", NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 };
244
245 static const char *svm_feature_name[] = {
246 "npt", "lbrv", "svm_lock", "nrip_save",
247 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
248 NULL, NULL, "pause_filter", NULL,
249 "pfthreshold", NULL, NULL, NULL,
250 NULL, NULL, NULL, NULL,
251 NULL, NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 };
255
256 static const char *cpuid_7_0_ebx_feature_name[] = {
257 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
258 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
259 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
260 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
261 };
262
263 static const char *cpuid_apm_edx_feature_name[] = {
264 NULL, NULL, NULL, NULL,
265 NULL, NULL, NULL, NULL,
266 "invtsc", NULL, NULL, NULL,
267 NULL, NULL, NULL, NULL,
268 NULL, NULL, NULL, NULL,
269 NULL, NULL, NULL, NULL,
270 NULL, NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 };
273
274 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
275 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
276 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
277 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
278 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
279 CPUID_PSE36 | CPUID_FXSR)
280 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
281 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
282 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
283 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
284 CPUID_PAE | CPUID_SEP | CPUID_APIC)
285
286 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
287 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
288 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
289 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
290 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
291 /* partly implemented:
292 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
293 /* missing:
294 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
295 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
296 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
297 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
298 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
299 /* missing:
300 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
301 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
302 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
303 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
304 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
305 CPUID_EXT_RDRAND */
306
307 #ifdef TARGET_X86_64
308 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
309 #else
310 #define TCG_EXT2_X86_64_FEATURES 0
311 #endif
312
313 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
314 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
315 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
316 TCG_EXT2_X86_64_FEATURES)
317 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
318 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
319 #define TCG_EXT4_FEATURES 0
320 #define TCG_SVM_FEATURES 0
321 #define TCG_KVM_FEATURES 0
322 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
323 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
324 /* missing:
325 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
326 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
327 CPUID_7_0_EBX_RDSEED */
328 #define TCG_APM_FEATURES 0
329
330
331 typedef struct FeatureWordInfo {
332 const char **feat_names;
333 uint32_t cpuid_eax; /* Input EAX for CPUID */
334 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
335 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
336 int cpuid_reg; /* output register (R_* constant) */
337 uint32_t tcg_features; /* Feature flags supported by TCG */
338 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
339 } FeatureWordInfo;
340
341 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
342 [FEAT_1_EDX] = {
343 .feat_names = feature_name,
344 .cpuid_eax = 1, .cpuid_reg = R_EDX,
345 .tcg_features = TCG_FEATURES,
346 },
347 [FEAT_1_ECX] = {
348 .feat_names = ext_feature_name,
349 .cpuid_eax = 1, .cpuid_reg = R_ECX,
350 .tcg_features = TCG_EXT_FEATURES,
351 },
352 [FEAT_8000_0001_EDX] = {
353 .feat_names = ext2_feature_name,
354 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
355 .tcg_features = TCG_EXT2_FEATURES,
356 },
357 [FEAT_8000_0001_ECX] = {
358 .feat_names = ext3_feature_name,
359 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
360 .tcg_features = TCG_EXT3_FEATURES,
361 },
362 [FEAT_C000_0001_EDX] = {
363 .feat_names = ext4_feature_name,
364 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
365 .tcg_features = TCG_EXT4_FEATURES,
366 },
367 [FEAT_KVM] = {
368 .feat_names = kvm_feature_name,
369 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
370 .tcg_features = TCG_KVM_FEATURES,
371 },
372 [FEAT_SVM] = {
373 .feat_names = svm_feature_name,
374 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
375 .tcg_features = TCG_SVM_FEATURES,
376 },
377 [FEAT_7_0_EBX] = {
378 .feat_names = cpuid_7_0_ebx_feature_name,
379 .cpuid_eax = 7,
380 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
381 .cpuid_reg = R_EBX,
382 .tcg_features = TCG_7_0_EBX_FEATURES,
383 },
384 [FEAT_8000_0007_EDX] = {
385 .feat_names = cpuid_apm_edx_feature_name,
386 .cpuid_eax = 0x80000007,
387 .cpuid_reg = R_EDX,
388 .tcg_features = TCG_APM_FEATURES,
389 .unmigratable_flags = CPUID_APM_INVTSC,
390 },
391 };
392
393 typedef struct X86RegisterInfo32 {
394 /* Name of register */
395 const char *name;
396 /* QAPI enum value register */
397 X86CPURegister32 qapi_enum;
398 } X86RegisterInfo32;
399
400 #define REGISTER(reg) \
401 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
402 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
403 REGISTER(EAX),
404 REGISTER(ECX),
405 REGISTER(EDX),
406 REGISTER(EBX),
407 REGISTER(ESP),
408 REGISTER(EBP),
409 REGISTER(ESI),
410 REGISTER(EDI),
411 };
412 #undef REGISTER
413
414 typedef struct ExtSaveArea {
415 uint32_t feature, bits;
416 uint32_t offset, size;
417 } ExtSaveArea;
418
419 static const ExtSaveArea ext_save_areas[] = {
420 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
421 .offset = 0x240, .size = 0x100 },
422 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
423 .offset = 0x3c0, .size = 0x40 },
424 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
425 .offset = 0x400, .size = 0x40 },
426 };
427
428 const char *get_register_name_32(unsigned int reg)
429 {
430 if (reg >= CPU_NB_REGS32) {
431 return NULL;
432 }
433 return x86_reg_info_32[reg].name;
434 }
435
436 /* collects per-function cpuid data
437 */
438 typedef struct model_features_t {
439 uint32_t *guest_feat;
440 uint32_t *host_feat;
441 FeatureWord feat_word;
442 } model_features_t;
443
444 /* KVM-specific features that are automatically added to all CPU models
445 * when KVM is enabled.
446 */
447 static uint32_t kvm_default_features[FEATURE_WORDS] = {
448 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
449 (1 << KVM_FEATURE_NOP_IO_DELAY) |
450 (1 << KVM_FEATURE_CLOCKSOURCE2) |
451 (1 << KVM_FEATURE_ASYNC_PF) |
452 (1 << KVM_FEATURE_STEAL_TIME) |
453 (1 << KVM_FEATURE_PV_EOI) |
454 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
455 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
456 };
457
458 /* Features that are not added by default to any CPU model when KVM is enabled.
459 */
460 static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
461 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
462 };
463
464 void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
465 {
466 kvm_default_features[w] &= ~features;
467 }
468
469 /*
470 * Returns the set of feature flags that are supported and migratable by
471 * QEMU, for a given FeatureWord.
472 */
473 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
474 {
475 FeatureWordInfo *wi = &feature_word_info[w];
476 uint32_t r = 0;
477 int i;
478
479 for (i = 0; i < 32; i++) {
480 uint32_t f = 1U << i;
481 /* If the feature name is unknown, it is not supported by QEMU yet */
482 if (!wi->feat_names[i]) {
483 continue;
484 }
485 /* Skip features known to QEMU, but explicitly marked as unmigratable */
486 if (wi->unmigratable_flags & f) {
487 continue;
488 }
489 r |= f;
490 }
491 return r;
492 }
493
494 void host_cpuid(uint32_t function, uint32_t count,
495 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
496 {
497 uint32_t vec[4];
498
499 #ifdef __x86_64__
500 asm volatile("cpuid"
501 : "=a"(vec[0]), "=b"(vec[1]),
502 "=c"(vec[2]), "=d"(vec[3])
503 : "0"(function), "c"(count) : "cc");
504 #elif defined(__i386__)
505 asm volatile("pusha \n\t"
506 "cpuid \n\t"
507 "mov %%eax, 0(%2) \n\t"
508 "mov %%ebx, 4(%2) \n\t"
509 "mov %%ecx, 8(%2) \n\t"
510 "mov %%edx, 12(%2) \n\t"
511 "popa"
512 : : "a"(function), "c"(count), "S"(vec)
513 : "memory", "cc");
514 #else
515 abort();
516 #endif
517
518 if (eax)
519 *eax = vec[0];
520 if (ebx)
521 *ebx = vec[1];
522 if (ecx)
523 *ecx = vec[2];
524 if (edx)
525 *edx = vec[3];
526 }
527
528 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
529
530 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
531 * a substring. ex if !NULL points to the first char after a substring,
532 * otherwise the string is assumed to sized by a terminating nul.
533 * Return lexical ordering of *s1:*s2.
534 */
535 static int sstrcmp(const char *s1, const char *e1, const char *s2,
536 const char *e2)
537 {
538 for (;;) {
539 if (!*s1 || !*s2 || *s1 != *s2)
540 return (*s1 - *s2);
541 ++s1, ++s2;
542 if (s1 == e1 && s2 == e2)
543 return (0);
544 else if (s1 == e1)
545 return (*s2);
546 else if (s2 == e2)
547 return (*s1);
548 }
549 }
550
551 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
552 * '|' delimited (possibly empty) strings in which case search for a match
553 * within the alternatives proceeds left to right. Return 0 for success,
554 * non-zero otherwise.
555 */
556 static int altcmp(const char *s, const char *e, const char *altstr)
557 {
558 const char *p, *q;
559
560 for (q = p = altstr; ; ) {
561 while (*p && *p != '|')
562 ++p;
563 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
564 return (0);
565 if (!*p)
566 return (1);
567 else
568 q = ++p;
569 }
570 }
571
572 /* search featureset for flag *[s..e), if found set corresponding bit in
573 * *pval and return true, otherwise return false
574 */
575 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
576 const char **featureset)
577 {
578 uint32_t mask;
579 const char **ppc;
580 bool found = false;
581
582 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
583 if (*ppc && !altcmp(s, e, *ppc)) {
584 *pval |= mask;
585 found = true;
586 }
587 }
588 return found;
589 }
590
591 static void add_flagname_to_bitmaps(const char *flagname,
592 FeatureWordArray words,
593 Error **errp)
594 {
595 FeatureWord w;
596 for (w = 0; w < FEATURE_WORDS; w++) {
597 FeatureWordInfo *wi = &feature_word_info[w];
598 if (wi->feat_names &&
599 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
600 break;
601 }
602 }
603 if (w == FEATURE_WORDS) {
604 error_setg(errp, "CPU feature %s not found", flagname);
605 }
606 }
607
608 /* CPU class name definitions: */
609
610 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
611 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
612
613 /* Return type name for a given CPU model name
614 * Caller is responsible for freeing the returned string.
615 */
616 static char *x86_cpu_type_name(const char *model_name)
617 {
618 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
619 }
620
621 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
622 {
623 ObjectClass *oc;
624 char *typename;
625
626 if (cpu_model == NULL) {
627 return NULL;
628 }
629
630 typename = x86_cpu_type_name(cpu_model);
631 oc = object_class_by_name(typename);
632 g_free(typename);
633 return oc;
634 }
635
636 struct X86CPUDefinition {
637 const char *name;
638 uint32_t level;
639 uint32_t xlevel;
640 uint32_t xlevel2;
641 /* vendor is zero-terminated, 12 character ASCII string */
642 char vendor[CPUID_VENDOR_SZ + 1];
643 int family;
644 int model;
645 int stepping;
646 FeatureWordArray features;
647 char model_id[48];
648 bool cache_info_passthrough;
649 };
650
651 static X86CPUDefinition builtin_x86_defs[] = {
652 {
653 .name = "qemu64",
654 .level = 4,
655 .vendor = CPUID_VENDOR_AMD,
656 .family = 6,
657 .model = 6,
658 .stepping = 3,
659 .features[FEAT_1_EDX] =
660 PPRO_FEATURES |
661 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
662 CPUID_PSE36,
663 .features[FEAT_1_ECX] =
664 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
665 .features[FEAT_8000_0001_EDX] =
666 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
667 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
668 .features[FEAT_8000_0001_ECX] =
669 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
670 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
671 .xlevel = 0x8000000A,
672 },
673 {
674 .name = "phenom",
675 .level = 5,
676 .vendor = CPUID_VENDOR_AMD,
677 .family = 16,
678 .model = 2,
679 .stepping = 3,
680 .features[FEAT_1_EDX] =
681 PPRO_FEATURES |
682 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
683 CPUID_PSE36 | CPUID_VME | CPUID_HT,
684 .features[FEAT_1_ECX] =
685 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
686 CPUID_EXT_POPCNT,
687 .features[FEAT_8000_0001_EDX] =
688 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
689 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
690 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
691 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
692 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
693 CPUID_EXT3_CR8LEG,
694 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
695 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
696 .features[FEAT_8000_0001_ECX] =
697 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
698 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
699 .features[FEAT_SVM] =
700 CPUID_SVM_NPT | CPUID_SVM_LBRV,
701 .xlevel = 0x8000001A,
702 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
703 },
704 {
705 .name = "core2duo",
706 .level = 10,
707 .vendor = CPUID_VENDOR_INTEL,
708 .family = 6,
709 .model = 15,
710 .stepping = 11,
711 .features[FEAT_1_EDX] =
712 PPRO_FEATURES |
713 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
714 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
715 CPUID_HT | CPUID_TM | CPUID_PBE,
716 .features[FEAT_1_ECX] =
717 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
718 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
719 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
720 .features[FEAT_8000_0001_EDX] =
721 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
722 .features[FEAT_8000_0001_ECX] =
723 CPUID_EXT3_LAHF_LM,
724 .xlevel = 0x80000008,
725 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
726 },
727 {
728 .name = "kvm64",
729 .level = 5,
730 .vendor = CPUID_VENDOR_INTEL,
731 .family = 15,
732 .model = 6,
733 .stepping = 1,
734 /* Missing: CPUID_VME, CPUID_HT */
735 .features[FEAT_1_EDX] =
736 PPRO_FEATURES |
737 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
738 CPUID_PSE36,
739 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
740 .features[FEAT_1_ECX] =
741 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
742 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
743 .features[FEAT_8000_0001_EDX] =
744 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
745 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
746 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
747 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
748 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
749 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
750 .features[FEAT_8000_0001_ECX] =
751 0,
752 .xlevel = 0x80000008,
753 .model_id = "Common KVM processor"
754 },
755 {
756 .name = "qemu32",
757 .level = 4,
758 .vendor = CPUID_VENDOR_INTEL,
759 .family = 6,
760 .model = 6,
761 .stepping = 3,
762 .features[FEAT_1_EDX] =
763 PPRO_FEATURES,
764 .features[FEAT_1_ECX] =
765 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
766 .xlevel = 0x80000004,
767 },
768 {
769 .name = "kvm32",
770 .level = 5,
771 .vendor = CPUID_VENDOR_INTEL,
772 .family = 15,
773 .model = 6,
774 .stepping = 1,
775 .features[FEAT_1_EDX] =
776 PPRO_FEATURES |
777 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
778 .features[FEAT_1_ECX] =
779 CPUID_EXT_SSE3,
780 .features[FEAT_8000_0001_EDX] =
781 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
782 .features[FEAT_8000_0001_ECX] =
783 0,
784 .xlevel = 0x80000008,
785 .model_id = "Common 32-bit KVM processor"
786 },
787 {
788 .name = "coreduo",
789 .level = 10,
790 .vendor = CPUID_VENDOR_INTEL,
791 .family = 6,
792 .model = 14,
793 .stepping = 8,
794 .features[FEAT_1_EDX] =
795 PPRO_FEATURES | CPUID_VME |
796 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
797 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
798 .features[FEAT_1_ECX] =
799 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
800 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
801 .features[FEAT_8000_0001_EDX] =
802 CPUID_EXT2_NX,
803 .xlevel = 0x80000008,
804 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
805 },
806 {
807 .name = "486",
808 .level = 1,
809 .vendor = CPUID_VENDOR_INTEL,
810 .family = 4,
811 .model = 8,
812 .stepping = 0,
813 .features[FEAT_1_EDX] =
814 I486_FEATURES,
815 .xlevel = 0,
816 },
817 {
818 .name = "pentium",
819 .level = 1,
820 .vendor = CPUID_VENDOR_INTEL,
821 .family = 5,
822 .model = 4,
823 .stepping = 3,
824 .features[FEAT_1_EDX] =
825 PENTIUM_FEATURES,
826 .xlevel = 0,
827 },
828 {
829 .name = "pentium2",
830 .level = 2,
831 .vendor = CPUID_VENDOR_INTEL,
832 .family = 6,
833 .model = 5,
834 .stepping = 2,
835 .features[FEAT_1_EDX] =
836 PENTIUM2_FEATURES,
837 .xlevel = 0,
838 },
839 {
840 .name = "pentium3",
841 .level = 2,
842 .vendor = CPUID_VENDOR_INTEL,
843 .family = 6,
844 .model = 7,
845 .stepping = 3,
846 .features[FEAT_1_EDX] =
847 PENTIUM3_FEATURES,
848 .xlevel = 0,
849 },
850 {
851 .name = "athlon",
852 .level = 2,
853 .vendor = CPUID_VENDOR_AMD,
854 .family = 6,
855 .model = 2,
856 .stepping = 3,
857 .features[FEAT_1_EDX] =
858 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
859 CPUID_MCA,
860 .features[FEAT_8000_0001_EDX] =
861 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
862 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
863 .xlevel = 0x80000008,
864 },
865 {
866 .name = "n270",
867 /* original is on level 10 */
868 .level = 5,
869 .vendor = CPUID_VENDOR_INTEL,
870 .family = 6,
871 .model = 28,
872 .stepping = 2,
873 .features[FEAT_1_EDX] =
874 PPRO_FEATURES |
875 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
876 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
877 /* Some CPUs got no CPUID_SEP */
878 .features[FEAT_1_ECX] =
879 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
880 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
881 CPUID_EXT_MOVBE,
882 .features[FEAT_8000_0001_EDX] =
883 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
884 CPUID_EXT2_NX,
885 .features[FEAT_8000_0001_ECX] =
886 CPUID_EXT3_LAHF_LM,
887 .xlevel = 0x8000000A,
888 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
889 },
890 {
891 .name = "Conroe",
892 .level = 4,
893 .vendor = CPUID_VENDOR_INTEL,
894 .family = 6,
895 .model = 15,
896 .stepping = 3,
897 .features[FEAT_1_EDX] =
898 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
899 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
900 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
901 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
902 CPUID_DE | CPUID_FP87,
903 .features[FEAT_1_ECX] =
904 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
905 .features[FEAT_8000_0001_EDX] =
906 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
907 .features[FEAT_8000_0001_ECX] =
908 CPUID_EXT3_LAHF_LM,
909 .xlevel = 0x8000000A,
910 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
911 },
912 {
913 .name = "Penryn",
914 .level = 4,
915 .vendor = CPUID_VENDOR_INTEL,
916 .family = 6,
917 .model = 23,
918 .stepping = 3,
919 .features[FEAT_1_EDX] =
920 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
921 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
922 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
923 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
924 CPUID_DE | CPUID_FP87,
925 .features[FEAT_1_ECX] =
926 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
927 CPUID_EXT_SSE3,
928 .features[FEAT_8000_0001_EDX] =
929 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
930 .features[FEAT_8000_0001_ECX] =
931 CPUID_EXT3_LAHF_LM,
932 .xlevel = 0x8000000A,
933 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
934 },
935 {
936 .name = "Nehalem",
937 .level = 4,
938 .vendor = CPUID_VENDOR_INTEL,
939 .family = 6,
940 .model = 26,
941 .stepping = 3,
942 .features[FEAT_1_EDX] =
943 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
944 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
945 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
946 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
947 CPUID_DE | CPUID_FP87,
948 .features[FEAT_1_ECX] =
949 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
950 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
951 .features[FEAT_8000_0001_EDX] =
952 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
953 .features[FEAT_8000_0001_ECX] =
954 CPUID_EXT3_LAHF_LM,
955 .xlevel = 0x8000000A,
956 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
957 },
958 {
959 .name = "Westmere",
960 .level = 11,
961 .vendor = CPUID_VENDOR_INTEL,
962 .family = 6,
963 .model = 44,
964 .stepping = 1,
965 .features[FEAT_1_EDX] =
966 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
967 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
968 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
969 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
970 CPUID_DE | CPUID_FP87,
971 .features[FEAT_1_ECX] =
972 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
973 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
974 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
975 .features[FEAT_8000_0001_EDX] =
976 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
977 .features[FEAT_8000_0001_ECX] =
978 CPUID_EXT3_LAHF_LM,
979 .xlevel = 0x8000000A,
980 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
981 },
982 {
983 .name = "SandyBridge",
984 .level = 0xd,
985 .vendor = CPUID_VENDOR_INTEL,
986 .family = 6,
987 .model = 42,
988 .stepping = 1,
989 .features[FEAT_1_EDX] =
990 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
991 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
992 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
993 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
994 CPUID_DE | CPUID_FP87,
995 .features[FEAT_1_ECX] =
996 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
997 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
998 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
999 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1000 CPUID_EXT_SSE3,
1001 .features[FEAT_8000_0001_EDX] =
1002 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1003 CPUID_EXT2_SYSCALL,
1004 .features[FEAT_8000_0001_ECX] =
1005 CPUID_EXT3_LAHF_LM,
1006 .xlevel = 0x8000000A,
1007 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1008 },
1009 {
1010 .name = "Haswell",
1011 .level = 0xd,
1012 .vendor = CPUID_VENDOR_INTEL,
1013 .family = 6,
1014 .model = 60,
1015 .stepping = 1,
1016 .features[FEAT_1_EDX] =
1017 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1018 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1019 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1020 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1021 CPUID_DE | CPUID_FP87,
1022 .features[FEAT_1_ECX] =
1023 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1024 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1025 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1026 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1027 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1028 CPUID_EXT_PCID,
1029 .features[FEAT_8000_0001_EDX] =
1030 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1031 CPUID_EXT2_SYSCALL,
1032 .features[FEAT_8000_0001_ECX] =
1033 CPUID_EXT3_LAHF_LM,
1034 .features[FEAT_7_0_EBX] =
1035 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1036 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1037 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1038 CPUID_7_0_EBX_RTM,
1039 .xlevel = 0x8000000A,
1040 .model_id = "Intel Core Processor (Haswell)",
1041 },
1042 {
1043 .name = "Broadwell",
1044 .level = 0xd,
1045 .vendor = CPUID_VENDOR_INTEL,
1046 .family = 6,
1047 .model = 61,
1048 .stepping = 2,
1049 .features[FEAT_1_EDX] =
1050 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1051 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1052 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1053 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1054 CPUID_DE | CPUID_FP87,
1055 .features[FEAT_1_ECX] =
1056 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1057 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1058 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1059 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1060 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1061 CPUID_EXT_PCID,
1062 .features[FEAT_8000_0001_EDX] =
1063 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1064 CPUID_EXT2_SYSCALL,
1065 .features[FEAT_8000_0001_ECX] =
1066 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1067 .features[FEAT_7_0_EBX] =
1068 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1069 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1070 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1071 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1072 CPUID_7_0_EBX_SMAP,
1073 .xlevel = 0x8000000A,
1074 .model_id = "Intel Core Processor (Broadwell)",
1075 },
1076 {
1077 .name = "Opteron_G1",
1078 .level = 5,
1079 .vendor = CPUID_VENDOR_AMD,
1080 .family = 15,
1081 .model = 6,
1082 .stepping = 1,
1083 .features[FEAT_1_EDX] =
1084 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1085 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1086 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1087 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1088 CPUID_DE | CPUID_FP87,
1089 .features[FEAT_1_ECX] =
1090 CPUID_EXT_SSE3,
1091 .features[FEAT_8000_0001_EDX] =
1092 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1093 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1094 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1095 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1096 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1097 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1098 .xlevel = 0x80000008,
1099 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1100 },
1101 {
1102 .name = "Opteron_G2",
1103 .level = 5,
1104 .vendor = CPUID_VENDOR_AMD,
1105 .family = 15,
1106 .model = 6,
1107 .stepping = 1,
1108 .features[FEAT_1_EDX] =
1109 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1110 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1111 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1112 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1113 CPUID_DE | CPUID_FP87,
1114 .features[FEAT_1_ECX] =
1115 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1116 .features[FEAT_8000_0001_EDX] =
1117 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1118 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1119 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1120 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1121 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1122 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1123 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1124 .features[FEAT_8000_0001_ECX] =
1125 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1126 .xlevel = 0x80000008,
1127 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1128 },
1129 {
1130 .name = "Opteron_G3",
1131 .level = 5,
1132 .vendor = CPUID_VENDOR_AMD,
1133 .family = 15,
1134 .model = 6,
1135 .stepping = 1,
1136 .features[FEAT_1_EDX] =
1137 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1138 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1139 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1140 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1141 CPUID_DE | CPUID_FP87,
1142 .features[FEAT_1_ECX] =
1143 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1144 CPUID_EXT_SSE3,
1145 .features[FEAT_8000_0001_EDX] =
1146 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1147 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1148 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1149 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1150 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1151 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1152 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1153 .features[FEAT_8000_0001_ECX] =
1154 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1155 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1156 .xlevel = 0x80000008,
1157 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1158 },
1159 {
1160 .name = "Opteron_G4",
1161 .level = 0xd,
1162 .vendor = CPUID_VENDOR_AMD,
1163 .family = 21,
1164 .model = 1,
1165 .stepping = 2,
1166 .features[FEAT_1_EDX] =
1167 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1168 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1169 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1170 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1171 CPUID_DE | CPUID_FP87,
1172 .features[FEAT_1_ECX] =
1173 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1174 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1175 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1176 CPUID_EXT_SSE3,
1177 .features[FEAT_8000_0001_EDX] =
1178 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1179 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1180 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1181 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1182 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1183 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1184 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1185 .features[FEAT_8000_0001_ECX] =
1186 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1187 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1188 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1189 CPUID_EXT3_LAHF_LM,
1190 .xlevel = 0x8000001A,
1191 .model_id = "AMD Opteron 62xx class CPU",
1192 },
1193 {
1194 .name = "Opteron_G5",
1195 .level = 0xd,
1196 .vendor = CPUID_VENDOR_AMD,
1197 .family = 21,
1198 .model = 2,
1199 .stepping = 0,
1200 .features[FEAT_1_EDX] =
1201 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1202 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1203 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1204 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1205 CPUID_DE | CPUID_FP87,
1206 .features[FEAT_1_ECX] =
1207 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1208 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1209 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1210 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1211 .features[FEAT_8000_0001_EDX] =
1212 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1213 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1214 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1215 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1216 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1217 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1218 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1219 .features[FEAT_8000_0001_ECX] =
1220 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1221 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1222 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1223 CPUID_EXT3_LAHF_LM,
1224 .xlevel = 0x8000001A,
1225 .model_id = "AMD Opteron 63xx class CPU",
1226 },
1227 };
1228
1229 /**
1230 * x86_cpu_compat_set_features:
1231 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1232 * @w: Identifies the feature word to be changed.
1233 * @feat_add: Feature bits to be added to feature word
1234 * @feat_remove: Feature bits to be removed from feature word
1235 *
1236 * Change CPU model feature bits for compatibility.
1237 *
1238 * This function may be used by machine-type compatibility functions
1239 * to enable or disable feature bits on specific CPU models.
1240 */
1241 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1242 uint32_t feat_add, uint32_t feat_remove)
1243 {
1244 X86CPUDefinition *def;
1245 int i;
1246 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1247 def = &builtin_x86_defs[i];
1248 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1249 def->features[w] |= feat_add;
1250 def->features[w] &= ~feat_remove;
1251 }
1252 }
1253 }
1254
1255 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1256 bool migratable_only);
1257
1258 #ifdef CONFIG_KVM
1259
1260 static int cpu_x86_fill_model_id(char *str)
1261 {
1262 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1263 int i;
1264
1265 for (i = 0; i < 3; i++) {
1266 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1267 memcpy(str + i * 16 + 0, &eax, 4);
1268 memcpy(str + i * 16 + 4, &ebx, 4);
1269 memcpy(str + i * 16 + 8, &ecx, 4);
1270 memcpy(str + i * 16 + 12, &edx, 4);
1271 }
1272 return 0;
1273 }
1274
1275 static X86CPUDefinition host_cpudef;
1276
1277 static Property host_x86_cpu_properties[] = {
1278 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
1279 DEFINE_PROP_END_OF_LIST()
1280 };
1281
1282 /* class_init for the "host" CPU model
1283 *
1284 * This function may be called before KVM is initialized.
1285 */
1286 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1287 {
1288 DeviceClass *dc = DEVICE_CLASS(oc);
1289 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1290 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1291
1292 xcc->kvm_required = true;
1293
1294 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1295 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1296
1297 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1298 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1299 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1300 host_cpudef.stepping = eax & 0x0F;
1301
1302 cpu_x86_fill_model_id(host_cpudef.model_id);
1303
1304 xcc->cpu_def = &host_cpudef;
1305 host_cpudef.cache_info_passthrough = true;
1306
1307 /* level, xlevel, xlevel2, and the feature words are initialized on
1308 * instance_init, because they require KVM to be initialized.
1309 */
1310
1311 dc->props = host_x86_cpu_properties;
1312 }
1313
1314 static void host_x86_cpu_initfn(Object *obj)
1315 {
1316 X86CPU *cpu = X86_CPU(obj);
1317 CPUX86State *env = &cpu->env;
1318 KVMState *s = kvm_state;
1319
1320 assert(kvm_enabled());
1321
1322 /* We can't fill the features array here because we don't know yet if
1323 * "migratable" is true or false.
1324 */
1325 cpu->host_features = true;
1326
1327 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1328 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1329 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1330
1331 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1332 }
1333
1334 static const TypeInfo host_x86_cpu_type_info = {
1335 .name = X86_CPU_TYPE_NAME("host"),
1336 .parent = TYPE_X86_CPU,
1337 .instance_init = host_x86_cpu_initfn,
1338 .class_init = host_x86_cpu_class_init,
1339 };
1340
1341 #endif
1342
1343 static void report_unavailable_features(FeatureWord w, uint32_t mask)
1344 {
1345 FeatureWordInfo *f = &feature_word_info[w];
1346 int i;
1347
1348 for (i = 0; i < 32; ++i) {
1349 if (1 << i & mask) {
1350 const char *reg = get_register_name_32(f->cpuid_reg);
1351 assert(reg);
1352 fprintf(stderr, "warning: %s doesn't support requested feature: "
1353 "CPUID.%02XH:%s%s%s [bit %d]\n",
1354 kvm_enabled() ? "host" : "TCG",
1355 f->cpuid_eax, reg,
1356 f->feat_names[i] ? "." : "",
1357 f->feat_names[i] ? f->feat_names[i] : "", i);
1358 }
1359 }
1360 }
1361
1362 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1363 const char *name, Error **errp)
1364 {
1365 X86CPU *cpu = X86_CPU(obj);
1366 CPUX86State *env = &cpu->env;
1367 int64_t value;
1368
1369 value = (env->cpuid_version >> 8) & 0xf;
1370 if (value == 0xf) {
1371 value += (env->cpuid_version >> 20) & 0xff;
1372 }
1373 visit_type_int(v, &value, name, errp);
1374 }
1375
1376 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1377 const char *name, Error **errp)
1378 {
1379 X86CPU *cpu = X86_CPU(obj);
1380 CPUX86State *env = &cpu->env;
1381 const int64_t min = 0;
1382 const int64_t max = 0xff + 0xf;
1383 Error *local_err = NULL;
1384 int64_t value;
1385
1386 visit_type_int(v, &value, name, &local_err);
1387 if (local_err) {
1388 error_propagate(errp, local_err);
1389 return;
1390 }
1391 if (value < min || value > max) {
1392 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1393 name ? name : "null", value, min, max);
1394 return;
1395 }
1396
1397 env->cpuid_version &= ~0xff00f00;
1398 if (value > 0x0f) {
1399 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1400 } else {
1401 env->cpuid_version |= value << 8;
1402 }
1403 }
1404
1405 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1406 const char *name, Error **errp)
1407 {
1408 X86CPU *cpu = X86_CPU(obj);
1409 CPUX86State *env = &cpu->env;
1410 int64_t value;
1411
1412 value = (env->cpuid_version >> 4) & 0xf;
1413 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1414 visit_type_int(v, &value, name, errp);
1415 }
1416
1417 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1418 const char *name, Error **errp)
1419 {
1420 X86CPU *cpu = X86_CPU(obj);
1421 CPUX86State *env = &cpu->env;
1422 const int64_t min = 0;
1423 const int64_t max = 0xff;
1424 Error *local_err = NULL;
1425 int64_t value;
1426
1427 visit_type_int(v, &value, name, &local_err);
1428 if (local_err) {
1429 error_propagate(errp, local_err);
1430 return;
1431 }
1432 if (value < min || value > max) {
1433 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1434 name ? name : "null", value, min, max);
1435 return;
1436 }
1437
1438 env->cpuid_version &= ~0xf00f0;
1439 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1440 }
1441
1442 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1443 void *opaque, const char *name,
1444 Error **errp)
1445 {
1446 X86CPU *cpu = X86_CPU(obj);
1447 CPUX86State *env = &cpu->env;
1448 int64_t value;
1449
1450 value = env->cpuid_version & 0xf;
1451 visit_type_int(v, &value, name, errp);
1452 }
1453
1454 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1455 void *opaque, const char *name,
1456 Error **errp)
1457 {
1458 X86CPU *cpu = X86_CPU(obj);
1459 CPUX86State *env = &cpu->env;
1460 const int64_t min = 0;
1461 const int64_t max = 0xf;
1462 Error *local_err = NULL;
1463 int64_t value;
1464
1465 visit_type_int(v, &value, name, &local_err);
1466 if (local_err) {
1467 error_propagate(errp, local_err);
1468 return;
1469 }
1470 if (value < min || value > max) {
1471 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1472 name ? name : "null", value, min, max);
1473 return;
1474 }
1475
1476 env->cpuid_version &= ~0xf;
1477 env->cpuid_version |= value & 0xf;
1478 }
1479
1480 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1481 const char *name, Error **errp)
1482 {
1483 X86CPU *cpu = X86_CPU(obj);
1484
1485 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1486 }
1487
1488 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1489 const char *name, Error **errp)
1490 {
1491 X86CPU *cpu = X86_CPU(obj);
1492
1493 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1494 }
1495
1496 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1497 const char *name, Error **errp)
1498 {
1499 X86CPU *cpu = X86_CPU(obj);
1500
1501 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1502 }
1503
1504 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1505 const char *name, Error **errp)
1506 {
1507 X86CPU *cpu = X86_CPU(obj);
1508
1509 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1510 }
1511
1512 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1513 {
1514 X86CPU *cpu = X86_CPU(obj);
1515 CPUX86State *env = &cpu->env;
1516 char *value;
1517
1518 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1519 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1520 env->cpuid_vendor3);
1521 return value;
1522 }
1523
1524 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1525 Error **errp)
1526 {
1527 X86CPU *cpu = X86_CPU(obj);
1528 CPUX86State *env = &cpu->env;
1529 int i;
1530
1531 if (strlen(value) != CPUID_VENDOR_SZ) {
1532 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1533 "vendor", value);
1534 return;
1535 }
1536
1537 env->cpuid_vendor1 = 0;
1538 env->cpuid_vendor2 = 0;
1539 env->cpuid_vendor3 = 0;
1540 for (i = 0; i < 4; i++) {
1541 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1542 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1543 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1544 }
1545 }
1546
1547 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1548 {
1549 X86CPU *cpu = X86_CPU(obj);
1550 CPUX86State *env = &cpu->env;
1551 char *value;
1552 int i;
1553
1554 value = g_malloc(48 + 1);
1555 for (i = 0; i < 48; i++) {
1556 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1557 }
1558 value[48] = '\0';
1559 return value;
1560 }
1561
1562 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1563 Error **errp)
1564 {
1565 X86CPU *cpu = X86_CPU(obj);
1566 CPUX86State *env = &cpu->env;
1567 int c, len, i;
1568
1569 if (model_id == NULL) {
1570 model_id = "";
1571 }
1572 len = strlen(model_id);
1573 memset(env->cpuid_model, 0, 48);
1574 for (i = 0; i < 48; i++) {
1575 if (i >= len) {
1576 c = '\0';
1577 } else {
1578 c = (uint8_t)model_id[i];
1579 }
1580 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1581 }
1582 }
1583
1584 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1585 const char *name, Error **errp)
1586 {
1587 X86CPU *cpu = X86_CPU(obj);
1588 int64_t value;
1589
1590 value = cpu->env.tsc_khz * 1000;
1591 visit_type_int(v, &value, name, errp);
1592 }
1593
1594 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1595 const char *name, Error **errp)
1596 {
1597 X86CPU *cpu = X86_CPU(obj);
1598 const int64_t min = 0;
1599 const int64_t max = INT64_MAX;
1600 Error *local_err = NULL;
1601 int64_t value;
1602
1603 visit_type_int(v, &value, name, &local_err);
1604 if (local_err) {
1605 error_propagate(errp, local_err);
1606 return;
1607 }
1608 if (value < min || value > max) {
1609 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1610 name ? name : "null", value, min, max);
1611 return;
1612 }
1613
1614 cpu->env.tsc_khz = value / 1000;
1615 }
1616
1617 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1618 const char *name, Error **errp)
1619 {
1620 X86CPU *cpu = X86_CPU(obj);
1621 int64_t value = cpu->env.cpuid_apic_id;
1622
1623 visit_type_int(v, &value, name, errp);
1624 }
1625
1626 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1627 const char *name, Error **errp)
1628 {
1629 X86CPU *cpu = X86_CPU(obj);
1630 DeviceState *dev = DEVICE(obj);
1631 const int64_t min = 0;
1632 const int64_t max = UINT32_MAX;
1633 Error *error = NULL;
1634 int64_t value;
1635
1636 if (dev->realized) {
1637 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1638 "it was realized", name, object_get_typename(obj));
1639 return;
1640 }
1641
1642 visit_type_int(v, &value, name, &error);
1643 if (error) {
1644 error_propagate(errp, error);
1645 return;
1646 }
1647 if (value < min || value > max) {
1648 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1649 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1650 object_get_typename(obj), name, value, min, max);
1651 return;
1652 }
1653
1654 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1655 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1656 return;
1657 }
1658 cpu->env.cpuid_apic_id = value;
1659 }
1660
1661 /* Generic getter for "feature-words" and "filtered-features" properties */
1662 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1663 const char *name, Error **errp)
1664 {
1665 uint32_t *array = (uint32_t *)opaque;
1666 FeatureWord w;
1667 Error *err = NULL;
1668 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1669 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1670 X86CPUFeatureWordInfoList *list = NULL;
1671
1672 for (w = 0; w < FEATURE_WORDS; w++) {
1673 FeatureWordInfo *wi = &feature_word_info[w];
1674 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1675 qwi->cpuid_input_eax = wi->cpuid_eax;
1676 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1677 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1678 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1679 qwi->features = array[w];
1680
1681 /* List will be in reverse order, but order shouldn't matter */
1682 list_entries[w].next = list;
1683 list_entries[w].value = &word_infos[w];
1684 list = &list_entries[w];
1685 }
1686
1687 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1688 error_propagate(errp, err);
1689 }
1690
1691 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1692 const char *name, Error **errp)
1693 {
1694 X86CPU *cpu = X86_CPU(obj);
1695 int64_t value = cpu->hyperv_spinlock_attempts;
1696
1697 visit_type_int(v, &value, name, errp);
1698 }
1699
1700 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1701 const char *name, Error **errp)
1702 {
1703 const int64_t min = 0xFFF;
1704 const int64_t max = UINT_MAX;
1705 X86CPU *cpu = X86_CPU(obj);
1706 Error *err = NULL;
1707 int64_t value;
1708
1709 visit_type_int(v, &value, name, &err);
1710 if (err) {
1711 error_propagate(errp, err);
1712 return;
1713 }
1714
1715 if (value < min || value > max) {
1716 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1717 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1718 object_get_typename(obj), name ? name : "null",
1719 value, min, max);
1720 return;
1721 }
1722 cpu->hyperv_spinlock_attempts = value;
1723 }
1724
1725 static PropertyInfo qdev_prop_spinlocks = {
1726 .name = "int",
1727 .get = x86_get_hv_spinlocks,
1728 .set = x86_set_hv_spinlocks,
1729 };
1730
1731 /* Convert all '_' in a feature string option name to '-', to make feature
1732 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1733 */
1734 static inline void feat2prop(char *s)
1735 {
1736 while ((s = strchr(s, '_'))) {
1737 *s = '-';
1738 }
1739 }
1740
1741 /* Parse "+feature,-feature,feature=foo" CPU feature string
1742 */
1743 static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1744 Error **errp)
1745 {
1746 X86CPU *cpu = X86_CPU(cs);
1747 char *featurestr; /* Single 'key=value" string being parsed */
1748 FeatureWord w;
1749 /* Features to be added */
1750 FeatureWordArray plus_features = { 0 };
1751 /* Features to be removed */
1752 FeatureWordArray minus_features = { 0 };
1753 uint32_t numvalue;
1754 CPUX86State *env = &cpu->env;
1755 Error *local_err = NULL;
1756
1757 featurestr = features ? strtok(features, ",") : NULL;
1758
1759 while (featurestr) {
1760 char *val;
1761 if (featurestr[0] == '+') {
1762 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
1763 } else if (featurestr[0] == '-') {
1764 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
1765 } else if ((val = strchr(featurestr, '='))) {
1766 *val = 0; val++;
1767 feat2prop(featurestr);
1768 if (!strcmp(featurestr, "xlevel")) {
1769 char *err;
1770 char num[32];
1771
1772 numvalue = strtoul(val, &err, 0);
1773 if (!*val || *err) {
1774 error_setg(errp, "bad numerical value %s", val);
1775 return;
1776 }
1777 if (numvalue < 0x80000000) {
1778 error_report("xlevel value shall always be >= 0x80000000"
1779 ", fixup will be removed in future versions");
1780 numvalue += 0x80000000;
1781 }
1782 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1783 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1784 } else if (!strcmp(featurestr, "tsc-freq")) {
1785 int64_t tsc_freq;
1786 char *err;
1787 char num[32];
1788
1789 tsc_freq = strtosz_suffix_unit(val, &err,
1790 STRTOSZ_DEFSUFFIX_B, 1000);
1791 if (tsc_freq < 0 || *err) {
1792 error_setg(errp, "bad numerical value %s", val);
1793 return;
1794 }
1795 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1796 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1797 &local_err);
1798 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1799 char *err;
1800 const int min = 0xFFF;
1801 char num[32];
1802 numvalue = strtoul(val, &err, 0);
1803 if (!*val || *err) {
1804 error_setg(errp, "bad numerical value %s", val);
1805 return;
1806 }
1807 if (numvalue < min) {
1808 error_report("hv-spinlocks value shall always be >= 0x%x"
1809 ", fixup will be removed in future versions",
1810 min);
1811 numvalue = min;
1812 }
1813 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1814 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1815 } else {
1816 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
1817 }
1818 } else {
1819 feat2prop(featurestr);
1820 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
1821 }
1822 if (local_err) {
1823 error_propagate(errp, local_err);
1824 return;
1825 }
1826 featurestr = strtok(NULL, ",");
1827 }
1828
1829 if (cpu->host_features) {
1830 for (w = 0; w < FEATURE_WORDS; w++) {
1831 env->features[w] =
1832 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1833 }
1834 }
1835
1836 for (w = 0; w < FEATURE_WORDS; w++) {
1837 env->features[w] |= plus_features[w];
1838 env->features[w] &= ~minus_features[w];
1839 }
1840 }
1841
1842 /* generate a composite string into buf of all cpuid names in featureset
1843 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1844 * if flags, suppress names undefined in featureset.
1845 */
1846 static void listflags(char *buf, int bufsize, uint32_t fbits,
1847 const char **featureset, uint32_t flags)
1848 {
1849 const char **p = &featureset[31];
1850 char *q, *b, bit;
1851 int nc;
1852
1853 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1854 *buf = '\0';
1855 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1856 if (fbits & 1 << bit && (*p || !flags)) {
1857 if (*p)
1858 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1859 else
1860 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1861 if (bufsize <= nc) {
1862 if (b) {
1863 memcpy(b, "...", sizeof("..."));
1864 }
1865 return;
1866 }
1867 q += nc;
1868 bufsize -= nc;
1869 }
1870 }
1871
1872 /* generate CPU information. */
1873 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1874 {
1875 X86CPUDefinition *def;
1876 char buf[256];
1877 int i;
1878
1879 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1880 def = &builtin_x86_defs[i];
1881 snprintf(buf, sizeof(buf), "%s", def->name);
1882 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1883 }
1884 #ifdef CONFIG_KVM
1885 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1886 "KVM processor with all supported host features "
1887 "(only available in KVM mode)");
1888 #endif
1889
1890 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1891 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1892 FeatureWordInfo *fw = &feature_word_info[i];
1893
1894 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1895 (*cpu_fprintf)(f, " %s\n", buf);
1896 }
1897 }
1898
1899 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1900 {
1901 CpuDefinitionInfoList *cpu_list = NULL;
1902 X86CPUDefinition *def;
1903 int i;
1904
1905 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1906 CpuDefinitionInfoList *entry;
1907 CpuDefinitionInfo *info;
1908
1909 def = &builtin_x86_defs[i];
1910 info = g_malloc0(sizeof(*info));
1911 info->name = g_strdup(def->name);
1912
1913 entry = g_malloc0(sizeof(*entry));
1914 entry->value = info;
1915 entry->next = cpu_list;
1916 cpu_list = entry;
1917 }
1918
1919 return cpu_list;
1920 }
1921
1922 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1923 bool migratable_only)
1924 {
1925 FeatureWordInfo *wi = &feature_word_info[w];
1926 uint32_t r;
1927
1928 if (kvm_enabled()) {
1929 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
1930 wi->cpuid_ecx,
1931 wi->cpuid_reg);
1932 } else if (tcg_enabled()) {
1933 r = wi->tcg_features;
1934 } else {
1935 return ~0;
1936 }
1937 if (migratable_only) {
1938 r &= x86_cpu_get_migratable_flags(w);
1939 }
1940 return r;
1941 }
1942
1943 /*
1944 * Filters CPU feature words based on host availability of each feature.
1945 *
1946 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
1947 */
1948 static int x86_cpu_filter_features(X86CPU *cpu)
1949 {
1950 CPUX86State *env = &cpu->env;
1951 FeatureWord w;
1952 int rv = 0;
1953
1954 for (w = 0; w < FEATURE_WORDS; w++) {
1955 uint32_t host_feat =
1956 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1957 uint32_t requested_features = env->features[w];
1958 env->features[w] &= host_feat;
1959 cpu->filtered_features[w] = requested_features & ~env->features[w];
1960 if (cpu->filtered_features[w]) {
1961 if (cpu->check_cpuid || cpu->enforce_cpuid) {
1962 report_unavailable_features(w, cpu->filtered_features[w]);
1963 }
1964 rv = 1;
1965 }
1966 }
1967
1968 return rv;
1969 }
1970
1971 /* Load data from X86CPUDefinition
1972 */
1973 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
1974 {
1975 CPUX86State *env = &cpu->env;
1976 const char *vendor;
1977 char host_vendor[CPUID_VENDOR_SZ + 1];
1978 FeatureWord w;
1979
1980 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1981 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1982 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1983 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1984 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1985 env->cpuid_xlevel2 = def->xlevel2;
1986 cpu->cache_info_passthrough = def->cache_info_passthrough;
1987 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1988 for (w = 0; w < FEATURE_WORDS; w++) {
1989 env->features[w] = def->features[w];
1990 }
1991
1992 /* Special cases not set in the X86CPUDefinition structs: */
1993 if (kvm_enabled()) {
1994 FeatureWord w;
1995 for (w = 0; w < FEATURE_WORDS; w++) {
1996 env->features[w] |= kvm_default_features[w];
1997 env->features[w] &= ~kvm_default_unset_features[w];
1998 }
1999 }
2000
2001 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
2002
2003 /* sysenter isn't supported in compatibility mode on AMD,
2004 * syscall isn't supported in compatibility mode on Intel.
2005 * Normally we advertise the actual CPU vendor, but you can
2006 * override this using the 'vendor' property if you want to use
2007 * KVM's sysenter/syscall emulation in compatibility mode and
2008 * when doing cross vendor migration
2009 */
2010 vendor = def->vendor;
2011 if (kvm_enabled()) {
2012 uint32_t ebx = 0, ecx = 0, edx = 0;
2013 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2014 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2015 vendor = host_vendor;
2016 }
2017
2018 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2019
2020 }
2021
2022 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
2023 Error **errp)
2024 {
2025 X86CPU *cpu = NULL;
2026 X86CPUClass *xcc;
2027 ObjectClass *oc;
2028 gchar **model_pieces;
2029 char *name, *features;
2030 Error *error = NULL;
2031
2032 model_pieces = g_strsplit(cpu_model, ",", 2);
2033 if (!model_pieces[0]) {
2034 error_setg(&error, "Invalid/empty CPU model name");
2035 goto out;
2036 }
2037 name = model_pieces[0];
2038 features = model_pieces[1];
2039
2040 oc = x86_cpu_class_by_name(name);
2041 if (oc == NULL) {
2042 error_setg(&error, "Unable to find CPU definition: %s", name);
2043 goto out;
2044 }
2045 xcc = X86_CPU_CLASS(oc);
2046
2047 if (xcc->kvm_required && !kvm_enabled()) {
2048 error_setg(&error, "CPU model '%s' requires KVM", name);
2049 goto out;
2050 }
2051
2052 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2053
2054 #ifndef CONFIG_USER_ONLY
2055 if (icc_bridge == NULL) {
2056 error_setg(&error, "Invalid icc-bridge value");
2057 goto out;
2058 }
2059 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
2060 object_unref(OBJECT(cpu));
2061 #endif
2062
2063 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2064 if (error) {
2065 goto out;
2066 }
2067
2068 out:
2069 if (error != NULL) {
2070 error_propagate(errp, error);
2071 if (cpu) {
2072 object_unref(OBJECT(cpu));
2073 cpu = NULL;
2074 }
2075 }
2076 g_strfreev(model_pieces);
2077 return cpu;
2078 }
2079
2080 X86CPU *cpu_x86_init(const char *cpu_model)
2081 {
2082 Error *error = NULL;
2083 X86CPU *cpu;
2084
2085 cpu = cpu_x86_create(cpu_model, NULL, &error);
2086 if (error) {
2087 goto out;
2088 }
2089
2090 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
2091
2092 out:
2093 if (error) {
2094 error_report("%s", error_get_pretty(error));
2095 error_free(error);
2096 if (cpu != NULL) {
2097 object_unref(OBJECT(cpu));
2098 cpu = NULL;
2099 }
2100 }
2101 return cpu;
2102 }
2103
2104 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2105 {
2106 X86CPUDefinition *cpudef = data;
2107 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2108
2109 xcc->cpu_def = cpudef;
2110 }
2111
2112 static void x86_register_cpudef_type(X86CPUDefinition *def)
2113 {
2114 char *typename = x86_cpu_type_name(def->name);
2115 TypeInfo ti = {
2116 .name = typename,
2117 .parent = TYPE_X86_CPU,
2118 .class_init = x86_cpu_cpudef_class_init,
2119 .class_data = def,
2120 };
2121
2122 type_register(&ti);
2123 g_free(typename);
2124 }
2125
2126 #if !defined(CONFIG_USER_ONLY)
2127
2128 void cpu_clear_apic_feature(CPUX86State *env)
2129 {
2130 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2131 }
2132
2133 #endif /* !CONFIG_USER_ONLY */
2134
2135 /* Initialize list of CPU models, filling some non-static fields if necessary
2136 */
2137 void x86_cpudef_setup(void)
2138 {
2139 int i, j;
2140 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2141
2142 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2143 X86CPUDefinition *def = &builtin_x86_defs[i];
2144
2145 /* Look for specific "cpudef" models that */
2146 /* have the QEMU version in .model_id */
2147 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2148 if (strcmp(model_with_versions[j], def->name) == 0) {
2149 pstrcpy(def->model_id, sizeof(def->model_id),
2150 "QEMU Virtual CPU version ");
2151 pstrcat(def->model_id, sizeof(def->model_id),
2152 qemu_get_version());
2153 break;
2154 }
2155 }
2156 }
2157 }
2158
2159 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2160 uint32_t *ecx, uint32_t *edx)
2161 {
2162 *ebx = env->cpuid_vendor1;
2163 *edx = env->cpuid_vendor2;
2164 *ecx = env->cpuid_vendor3;
2165 }
2166
2167 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2168 uint32_t *eax, uint32_t *ebx,
2169 uint32_t *ecx, uint32_t *edx)
2170 {
2171 X86CPU *cpu = x86_env_get_cpu(env);
2172 CPUState *cs = CPU(cpu);
2173
2174 /* test if maximum index reached */
2175 if (index & 0x80000000) {
2176 if (index > env->cpuid_xlevel) {
2177 if (env->cpuid_xlevel2 > 0) {
2178 /* Handle the Centaur's CPUID instruction. */
2179 if (index > env->cpuid_xlevel2) {
2180 index = env->cpuid_xlevel2;
2181 } else if (index < 0xC0000000) {
2182 index = env->cpuid_xlevel;
2183 }
2184 } else {
2185 /* Intel documentation states that invalid EAX input will
2186 * return the same information as EAX=cpuid_level
2187 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2188 */
2189 index = env->cpuid_level;
2190 }
2191 }
2192 } else {
2193 if (index > env->cpuid_level)
2194 index = env->cpuid_level;
2195 }
2196
2197 switch(index) {
2198 case 0:
2199 *eax = env->cpuid_level;
2200 get_cpuid_vendor(env, ebx, ecx, edx);
2201 break;
2202 case 1:
2203 *eax = env->cpuid_version;
2204 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2205 *ecx = env->features[FEAT_1_ECX];
2206 *edx = env->features[FEAT_1_EDX];
2207 if (cs->nr_cores * cs->nr_threads > 1) {
2208 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2209 *edx |= 1 << 28; /* HTT bit */
2210 }
2211 break;
2212 case 2:
2213 /* cache info: needed for Pentium Pro compatibility */
2214 if (cpu->cache_info_passthrough) {
2215 host_cpuid(index, 0, eax, ebx, ecx, edx);
2216 break;
2217 }
2218 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2219 *ebx = 0;
2220 *ecx = 0;
2221 *edx = (L1D_DESCRIPTOR << 16) | \
2222 (L1I_DESCRIPTOR << 8) | \
2223 (L2_DESCRIPTOR);
2224 break;
2225 case 4:
2226 /* cache info: needed for Core compatibility */
2227 if (cpu->cache_info_passthrough) {
2228 host_cpuid(index, count, eax, ebx, ecx, edx);
2229 *eax &= ~0xFC000000;
2230 } else {
2231 *eax = 0;
2232 switch (count) {
2233 case 0: /* L1 dcache info */
2234 *eax |= CPUID_4_TYPE_DCACHE | \
2235 CPUID_4_LEVEL(1) | \
2236 CPUID_4_SELF_INIT_LEVEL;
2237 *ebx = (L1D_LINE_SIZE - 1) | \
2238 ((L1D_PARTITIONS - 1) << 12) | \
2239 ((L1D_ASSOCIATIVITY - 1) << 22);
2240 *ecx = L1D_SETS - 1;
2241 *edx = CPUID_4_NO_INVD_SHARING;
2242 break;
2243 case 1: /* L1 icache info */
2244 *eax |= CPUID_4_TYPE_ICACHE | \
2245 CPUID_4_LEVEL(1) | \
2246 CPUID_4_SELF_INIT_LEVEL;
2247 *ebx = (L1I_LINE_SIZE - 1) | \
2248 ((L1I_PARTITIONS - 1) << 12) | \
2249 ((L1I_ASSOCIATIVITY - 1) << 22);
2250 *ecx = L1I_SETS - 1;
2251 *edx = CPUID_4_NO_INVD_SHARING;
2252 break;
2253 case 2: /* L2 cache info */
2254 *eax |= CPUID_4_TYPE_UNIFIED | \
2255 CPUID_4_LEVEL(2) | \
2256 CPUID_4_SELF_INIT_LEVEL;
2257 if (cs->nr_threads > 1) {
2258 *eax |= (cs->nr_threads - 1) << 14;
2259 }
2260 *ebx = (L2_LINE_SIZE - 1) | \
2261 ((L2_PARTITIONS - 1) << 12) | \
2262 ((L2_ASSOCIATIVITY - 1) << 22);
2263 *ecx = L2_SETS - 1;
2264 *edx = CPUID_4_NO_INVD_SHARING;
2265 break;
2266 default: /* end of info */
2267 *eax = 0;
2268 *ebx = 0;
2269 *ecx = 0;
2270 *edx = 0;
2271 break;
2272 }
2273 }
2274
2275 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2276 if ((*eax & 31) && cs->nr_cores > 1) {
2277 *eax |= (cs->nr_cores - 1) << 26;
2278 }
2279 break;
2280 case 5:
2281 /* mwait info: needed for Core compatibility */
2282 *eax = 0; /* Smallest monitor-line size in bytes */
2283 *ebx = 0; /* Largest monitor-line size in bytes */
2284 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2285 *edx = 0;
2286 break;
2287 case 6:
2288 /* Thermal and Power Leaf */
2289 *eax = 0;
2290 *ebx = 0;
2291 *ecx = 0;
2292 *edx = 0;
2293 break;
2294 case 7:
2295 /* Structured Extended Feature Flags Enumeration Leaf */
2296 if (count == 0) {
2297 *eax = 0; /* Maximum ECX value for sub-leaves */
2298 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2299 *ecx = 0; /* Reserved */
2300 *edx = 0; /* Reserved */
2301 } else {
2302 *eax = 0;
2303 *ebx = 0;
2304 *ecx = 0;
2305 *edx = 0;
2306 }
2307 break;
2308 case 9:
2309 /* Direct Cache Access Information Leaf */
2310 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2311 *ebx = 0;
2312 *ecx = 0;
2313 *edx = 0;
2314 break;
2315 case 0xA:
2316 /* Architectural Performance Monitoring Leaf */
2317 if (kvm_enabled() && cpu->enable_pmu) {
2318 KVMState *s = cs->kvm_state;
2319
2320 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2321 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2322 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2323 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2324 } else {
2325 *eax = 0;
2326 *ebx = 0;
2327 *ecx = 0;
2328 *edx = 0;
2329 }
2330 break;
2331 case 0xD: {
2332 KVMState *s = cs->kvm_state;
2333 uint64_t kvm_mask;
2334 int i;
2335
2336 /* Processor Extended State */
2337 *eax = 0;
2338 *ebx = 0;
2339 *ecx = 0;
2340 *edx = 0;
2341 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2342 break;
2343 }
2344 kvm_mask =
2345 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2346 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2347
2348 if (count == 0) {
2349 *ecx = 0x240;
2350 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2351 const ExtSaveArea *esa = &ext_save_areas[i];
2352 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2353 (kvm_mask & (1 << i)) != 0) {
2354 if (i < 32) {
2355 *eax |= 1 << i;
2356 } else {
2357 *edx |= 1 << (i - 32);
2358 }
2359 *ecx = MAX(*ecx, esa->offset + esa->size);
2360 }
2361 }
2362 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2363 *ebx = *ecx;
2364 } else if (count == 1) {
2365 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2366 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2367 const ExtSaveArea *esa = &ext_save_areas[count];
2368 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2369 (kvm_mask & (1 << count)) != 0) {
2370 *eax = esa->size;
2371 *ebx = esa->offset;
2372 }
2373 }
2374 break;
2375 }
2376 case 0x80000000:
2377 *eax = env->cpuid_xlevel;
2378 *ebx = env->cpuid_vendor1;
2379 *edx = env->cpuid_vendor2;
2380 *ecx = env->cpuid_vendor3;
2381 break;
2382 case 0x80000001:
2383 *eax = env->cpuid_version;
2384 *ebx = 0;
2385 *ecx = env->features[FEAT_8000_0001_ECX];
2386 *edx = env->features[FEAT_8000_0001_EDX];
2387
2388 /* The Linux kernel checks for the CMPLegacy bit and
2389 * discards multiple thread information if it is set.
2390 * So dont set it here for Intel to make Linux guests happy.
2391 */
2392 if (cs->nr_cores * cs->nr_threads > 1) {
2393 uint32_t tebx, tecx, tedx;
2394 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2395 if (tebx != CPUID_VENDOR_INTEL_1 ||
2396 tedx != CPUID_VENDOR_INTEL_2 ||
2397 tecx != CPUID_VENDOR_INTEL_3) {
2398 *ecx |= 1 << 1; /* CmpLegacy bit */
2399 }
2400 }
2401 break;
2402 case 0x80000002:
2403 case 0x80000003:
2404 case 0x80000004:
2405 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2406 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2407 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2408 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2409 break;
2410 case 0x80000005:
2411 /* cache info (L1 cache) */
2412 if (cpu->cache_info_passthrough) {
2413 host_cpuid(index, 0, eax, ebx, ecx, edx);
2414 break;
2415 }
2416 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2417 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2418 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2419 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2420 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2421 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2422 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2423 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2424 break;
2425 case 0x80000006:
2426 /* cache info (L2 cache) */
2427 if (cpu->cache_info_passthrough) {
2428 host_cpuid(index, 0, eax, ebx, ecx, edx);
2429 break;
2430 }
2431 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2432 (L2_DTLB_2M_ENTRIES << 16) | \
2433 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2434 (L2_ITLB_2M_ENTRIES);
2435 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2436 (L2_DTLB_4K_ENTRIES << 16) | \
2437 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2438 (L2_ITLB_4K_ENTRIES);
2439 *ecx = (L2_SIZE_KB_AMD << 16) | \
2440 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2441 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2442 *edx = ((L3_SIZE_KB/512) << 18) | \
2443 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2444 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2445 break;
2446 case 0x80000007:
2447 *eax = 0;
2448 *ebx = 0;
2449 *ecx = 0;
2450 *edx = env->features[FEAT_8000_0007_EDX];
2451 break;
2452 case 0x80000008:
2453 /* virtual & phys address size in low 2 bytes. */
2454 /* XXX: This value must match the one used in the MMU code. */
2455 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2456 /* 64 bit processor */
2457 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2458 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2459 } else {
2460 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2461 *eax = 0x00000024; /* 36 bits physical */
2462 } else {
2463 *eax = 0x00000020; /* 32 bits physical */
2464 }
2465 }
2466 *ebx = 0;
2467 *ecx = 0;
2468 *edx = 0;
2469 if (cs->nr_cores * cs->nr_threads > 1) {
2470 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2471 }
2472 break;
2473 case 0x8000000A:
2474 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2475 *eax = 0x00000001; /* SVM Revision */
2476 *ebx = 0x00000010; /* nr of ASIDs */
2477 *ecx = 0;
2478 *edx = env->features[FEAT_SVM]; /* optional features */
2479 } else {
2480 *eax = 0;
2481 *ebx = 0;
2482 *ecx = 0;
2483 *edx = 0;
2484 }
2485 break;
2486 case 0xC0000000:
2487 *eax = env->cpuid_xlevel2;
2488 *ebx = 0;
2489 *ecx = 0;
2490 *edx = 0;
2491 break;
2492 case 0xC0000001:
2493 /* Support for VIA CPU's CPUID instruction */
2494 *eax = env->cpuid_version;
2495 *ebx = 0;
2496 *ecx = 0;
2497 *edx = env->features[FEAT_C000_0001_EDX];
2498 break;
2499 case 0xC0000002:
2500 case 0xC0000003:
2501 case 0xC0000004:
2502 /* Reserved for the future, and now filled with zero */
2503 *eax = 0;
2504 *ebx = 0;
2505 *ecx = 0;
2506 *edx = 0;
2507 break;
2508 default:
2509 /* reserved values: zero */
2510 *eax = 0;
2511 *ebx = 0;
2512 *ecx = 0;
2513 *edx = 0;
2514 break;
2515 }
2516 }
2517
2518 /* CPUClass::reset() */
2519 static void x86_cpu_reset(CPUState *s)
2520 {
2521 X86CPU *cpu = X86_CPU(s);
2522 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2523 CPUX86State *env = &cpu->env;
2524 int i;
2525
2526 xcc->parent_reset(s);
2527
2528 memset(env, 0, offsetof(CPUX86State, cpuid_level));
2529
2530 tlb_flush(s, 1);
2531
2532 env->old_exception = -1;
2533
2534 /* init to reset state */
2535
2536 #ifdef CONFIG_SOFTMMU
2537 env->hflags |= HF_SOFTMMU_MASK;
2538 #endif
2539 env->hflags2 |= HF2_GIF_MASK;
2540
2541 cpu_x86_update_cr0(env, 0x60000010);
2542 env->a20_mask = ~0x0;
2543 env->smbase = 0x30000;
2544
2545 env->idt.limit = 0xffff;
2546 env->gdt.limit = 0xffff;
2547 env->ldt.limit = 0xffff;
2548 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2549 env->tr.limit = 0xffff;
2550 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2551
2552 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2553 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2554 DESC_R_MASK | DESC_A_MASK);
2555 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2556 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2557 DESC_A_MASK);
2558 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2559 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2560 DESC_A_MASK);
2561 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2562 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2563 DESC_A_MASK);
2564 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2565 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2566 DESC_A_MASK);
2567 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2568 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2569 DESC_A_MASK);
2570
2571 env->eip = 0xfff0;
2572 env->regs[R_EDX] = env->cpuid_version;
2573
2574 env->eflags = 0x2;
2575
2576 /* FPU init */
2577 for (i = 0; i < 8; i++) {
2578 env->fptags[i] = 1;
2579 }
2580 cpu_set_fpuc(env, 0x37f);
2581
2582 env->mxcsr = 0x1f80;
2583 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2584
2585 env->pat = 0x0007040600070406ULL;
2586 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2587
2588 memset(env->dr, 0, sizeof(env->dr));
2589 env->dr[6] = DR6_FIXED_1;
2590 env->dr[7] = DR7_FIXED_1;
2591 cpu_breakpoint_remove_all(s, BP_CPU);
2592 cpu_watchpoint_remove_all(s, BP_CPU);
2593
2594 env->xcr0 = 1;
2595
2596 /*
2597 * SDM 11.11.5 requires:
2598 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2599 * - IA32_MTRR_PHYSMASKn.V = 0
2600 * All other bits are undefined. For simplification, zero it all.
2601 */
2602 env->mtrr_deftype = 0;
2603 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2604 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2605
2606 #if !defined(CONFIG_USER_ONLY)
2607 /* We hard-wire the BSP to the first CPU. */
2608 if (s->cpu_index == 0) {
2609 apic_designate_bsp(cpu->apic_state);
2610 }
2611
2612 s->halted = !cpu_is_bsp(cpu);
2613
2614 if (kvm_enabled()) {
2615 kvm_arch_reset_vcpu(cpu);
2616 }
2617 #endif
2618 }
2619
2620 #ifndef CONFIG_USER_ONLY
2621 bool cpu_is_bsp(X86CPU *cpu)
2622 {
2623 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2624 }
2625
2626 /* TODO: remove me, when reset over QOM tree is implemented */
2627 static void x86_cpu_machine_reset_cb(void *opaque)
2628 {
2629 X86CPU *cpu = opaque;
2630 cpu_reset(CPU(cpu));
2631 }
2632 #endif
2633
2634 static void mce_init(X86CPU *cpu)
2635 {
2636 CPUX86State *cenv = &cpu->env;
2637 unsigned int bank;
2638
2639 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2640 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2641 (CPUID_MCE | CPUID_MCA)) {
2642 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2643 cenv->mcg_ctl = ~(uint64_t)0;
2644 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2645 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2646 }
2647 }
2648 }
2649
2650 #ifndef CONFIG_USER_ONLY
2651 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2652 {
2653 CPUX86State *env = &cpu->env;
2654 DeviceState *dev = DEVICE(cpu);
2655 APICCommonState *apic;
2656 const char *apic_type = "apic";
2657
2658 if (kvm_irqchip_in_kernel()) {
2659 apic_type = "kvm-apic";
2660 } else if (xen_enabled()) {
2661 apic_type = "xen-apic";
2662 }
2663
2664 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2665 if (cpu->apic_state == NULL) {
2666 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2667 return;
2668 }
2669
2670 object_property_add_child(OBJECT(cpu), "apic",
2671 OBJECT(cpu->apic_state), NULL);
2672 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
2673 /* TODO: convert to link<> */
2674 apic = APIC_COMMON(cpu->apic_state);
2675 apic->cpu = cpu;
2676 }
2677
2678 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2679 {
2680 if (cpu->apic_state == NULL) {
2681 return;
2682 }
2683
2684 if (qdev_init(cpu->apic_state)) {
2685 error_setg(errp, "APIC device '%s' could not be initialized",
2686 object_get_typename(OBJECT(cpu->apic_state)));
2687 return;
2688 }
2689 }
2690 #else
2691 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2692 {
2693 }
2694 #endif
2695
2696 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2697 {
2698 CPUState *cs = CPU(dev);
2699 X86CPU *cpu = X86_CPU(dev);
2700 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2701 CPUX86State *env = &cpu->env;
2702 Error *local_err = NULL;
2703
2704 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2705 env->cpuid_level = 7;
2706 }
2707
2708 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2709 * CPUID[1].EDX.
2710 */
2711 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2712 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2713 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2714 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2715 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2716 & CPUID_EXT2_AMD_ALIASES);
2717 }
2718
2719
2720 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2721 error_setg(&local_err,
2722 kvm_enabled() ?
2723 "Host doesn't support requested features" :
2724 "TCG doesn't support requested features");
2725 goto out;
2726 }
2727
2728 #ifndef CONFIG_USER_ONLY
2729 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2730
2731 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2732 x86_cpu_apic_create(cpu, &local_err);
2733 if (local_err != NULL) {
2734 goto out;
2735 }
2736 }
2737 #endif
2738
2739 mce_init(cpu);
2740 qemu_init_vcpu(cs);
2741
2742 x86_cpu_apic_realize(cpu, &local_err);
2743 if (local_err != NULL) {
2744 goto out;
2745 }
2746 cpu_reset(cs);
2747
2748 xcc->parent_realize(dev, &local_err);
2749 out:
2750 if (local_err != NULL) {
2751 error_propagate(errp, local_err);
2752 return;
2753 }
2754 }
2755
2756 /* Enables contiguous-apic-ID mode, for compatibility */
2757 static bool compat_apic_id_mode;
2758
2759 void enable_compat_apic_id_mode(void)
2760 {
2761 compat_apic_id_mode = true;
2762 }
2763
2764 /* Calculates initial APIC ID for a specific CPU index
2765 *
2766 * Currently we need to be able to calculate the APIC ID from the CPU index
2767 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2768 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2769 * all CPUs up to max_cpus.
2770 */
2771 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2772 {
2773 uint32_t correct_id;
2774 static bool warned;
2775
2776 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2777 if (compat_apic_id_mode) {
2778 if (cpu_index != correct_id && !warned) {
2779 error_report("APIC IDs set in compatibility mode, "
2780 "CPU topology won't match the configuration");
2781 warned = true;
2782 }
2783 return cpu_index;
2784 } else {
2785 return correct_id;
2786 }
2787 }
2788
2789 static void x86_cpu_initfn(Object *obj)
2790 {
2791 CPUState *cs = CPU(obj);
2792 X86CPU *cpu = X86_CPU(obj);
2793 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
2794 CPUX86State *env = &cpu->env;
2795 static int inited;
2796
2797 cs->env_ptr = env;
2798 cpu_exec_init(env);
2799
2800 object_property_add(obj, "family", "int",
2801 x86_cpuid_version_get_family,
2802 x86_cpuid_version_set_family, NULL, NULL, NULL);
2803 object_property_add(obj, "model", "int",
2804 x86_cpuid_version_get_model,
2805 x86_cpuid_version_set_model, NULL, NULL, NULL);
2806 object_property_add(obj, "stepping", "int",
2807 x86_cpuid_version_get_stepping,
2808 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2809 object_property_add(obj, "level", "int",
2810 x86_cpuid_get_level,
2811 x86_cpuid_set_level, NULL, NULL, NULL);
2812 object_property_add(obj, "xlevel", "int",
2813 x86_cpuid_get_xlevel,
2814 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2815 object_property_add_str(obj, "vendor",
2816 x86_cpuid_get_vendor,
2817 x86_cpuid_set_vendor, NULL);
2818 object_property_add_str(obj, "model-id",
2819 x86_cpuid_get_model_id,
2820 x86_cpuid_set_model_id, NULL);
2821 object_property_add(obj, "tsc-frequency", "int",
2822 x86_cpuid_get_tsc_freq,
2823 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2824 object_property_add(obj, "apic-id", "int",
2825 x86_cpuid_get_apic_id,
2826 x86_cpuid_set_apic_id, NULL, NULL, NULL);
2827 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2828 x86_cpu_get_feature_words,
2829 NULL, NULL, (void *)env->features, NULL);
2830 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2831 x86_cpu_get_feature_words,
2832 NULL, NULL, (void *)cpu->filtered_features, NULL);
2833
2834 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2835 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2836
2837 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2838
2839 /* init various static tables used in TCG mode */
2840 if (tcg_enabled() && !inited) {
2841 inited = 1;
2842 optimize_flags_init();
2843 }
2844 }
2845
2846 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2847 {
2848 X86CPU *cpu = X86_CPU(cs);
2849 CPUX86State *env = &cpu->env;
2850
2851 return env->cpuid_apic_id;
2852 }
2853
2854 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2855 {
2856 X86CPU *cpu = X86_CPU(cs);
2857
2858 return cpu->env.cr[0] & CR0_PG_MASK;
2859 }
2860
2861 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2862 {
2863 X86CPU *cpu = X86_CPU(cs);
2864
2865 cpu->env.eip = value;
2866 }
2867
2868 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2869 {
2870 X86CPU *cpu = X86_CPU(cs);
2871
2872 cpu->env.eip = tb->pc - tb->cs_base;
2873 }
2874
2875 static bool x86_cpu_has_work(CPUState *cs)
2876 {
2877 X86CPU *cpu = X86_CPU(cs);
2878 CPUX86State *env = &cpu->env;
2879
2880 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2881 CPU_INTERRUPT_POLL)) &&
2882 (env->eflags & IF_MASK)) ||
2883 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2884 CPU_INTERRUPT_INIT |
2885 CPU_INTERRUPT_SIPI |
2886 CPU_INTERRUPT_MCE));
2887 }
2888
2889 static Property x86_cpu_properties[] = {
2890 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2891 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
2892 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
2893 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
2894 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
2895 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2896 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
2897 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
2898 DEFINE_PROP_END_OF_LIST()
2899 };
2900
2901 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2902 {
2903 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2904 CPUClass *cc = CPU_CLASS(oc);
2905 DeviceClass *dc = DEVICE_CLASS(oc);
2906
2907 xcc->parent_realize = dc->realize;
2908 dc->realize = x86_cpu_realizefn;
2909 dc->bus_type = TYPE_ICC_BUS;
2910 dc->props = x86_cpu_properties;
2911
2912 xcc->parent_reset = cc->reset;
2913 cc->reset = x86_cpu_reset;
2914 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2915
2916 cc->class_by_name = x86_cpu_class_by_name;
2917 cc->parse_features = x86_cpu_parse_featurestr;
2918 cc->has_work = x86_cpu_has_work;
2919 cc->do_interrupt = x86_cpu_do_interrupt;
2920 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
2921 cc->dump_state = x86_cpu_dump_state;
2922 cc->set_pc = x86_cpu_set_pc;
2923 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2924 cc->gdb_read_register = x86_cpu_gdb_read_register;
2925 cc->gdb_write_register = x86_cpu_gdb_write_register;
2926 cc->get_arch_id = x86_cpu_get_arch_id;
2927 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2928 #ifdef CONFIG_USER_ONLY
2929 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2930 #else
2931 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2932 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2933 cc->write_elf64_note = x86_cpu_write_elf64_note;
2934 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2935 cc->write_elf32_note = x86_cpu_write_elf32_note;
2936 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2937 cc->vmsd = &vmstate_x86_cpu;
2938 #endif
2939 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2940 #ifndef CONFIG_USER_ONLY
2941 cc->debug_excp_handler = breakpoint_handler;
2942 #endif
2943 cc->cpu_exec_enter = x86_cpu_exec_enter;
2944 cc->cpu_exec_exit = x86_cpu_exec_exit;
2945 }
2946
2947 static const TypeInfo x86_cpu_type_info = {
2948 .name = TYPE_X86_CPU,
2949 .parent = TYPE_CPU,
2950 .instance_size = sizeof(X86CPU),
2951 .instance_init = x86_cpu_initfn,
2952 .abstract = true,
2953 .class_size = sizeof(X86CPUClass),
2954 .class_init = x86_cpu_common_class_init,
2955 };
2956
2957 static void x86_cpu_register_types(void)
2958 {
2959 int i;
2960
2961 type_register_static(&x86_cpu_type_info);
2962 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2963 x86_register_cpudef_type(&builtin_x86_defs[i]);
2964 }
2965 #ifdef CONFIG_KVM
2966 type_register_static(&host_x86_cpu_type_info);
2967 #endif
2968 }
2969
2970 type_init(x86_cpu_register_types)
AR7 emulation for QEMU