target/arm: Handle floating point registers in exception entry
[qemu/ar7.git] / linux-user / aarch64 / target_cpu.h
bloba021c95fa418ff6bd543417c42b59a7f4324e758
1 /*
2 * ARM AArch64 specific CPU ABI and functions for linux-user
4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #ifndef AARCH64_TARGET_CPU_H
20 #define AARCH64_TARGET_CPU_H
22 static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
24 if (newsp) {
25 env->xregs[31] = newsp;
27 env->xregs[0] = 0;
30 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
32 /* Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is
33 * different from AArch32 Linux, which uses TPIDRRO.
35 env->cp15.tpidr_el[0] = newtls;
38 static inline abi_ulong get_sp_from_cpustate(CPUARMState *state)
40 return state->xregs[31];
42 #endif