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cuda: move unknown commands reject out of switch
[qemu/ar7.git] / target-tricore / translate.c
bloba70fdf741e1cd468e4ca8946145f391e36b84410
1 /*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "tcg-op.h"
25 #include "exec/cpu_ldst.h"
26
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
29
30 #include "tricore-opcodes.h"
31 #include "exec/log.h"
32
33 /*
34 * TCG registers
35 */
36 static TCGv cpu_PC;
37 static TCGv cpu_PCXI;
38 static TCGv cpu_PSW;
39 static TCGv cpu_ICR;
40 /* GPR registers */
41 static TCGv cpu_gpr_a[16];
42 static TCGv cpu_gpr_d[16];
43 /* PSW Flag cache */
44 static TCGv cpu_PSW_C;
45 static TCGv cpu_PSW_V;
46 static TCGv cpu_PSW_SV;
47 static TCGv cpu_PSW_AV;
48 static TCGv cpu_PSW_SAV;
49 /* CPU env */
50 static TCGv_ptr cpu_env;
51
52 #include "exec/gen-icount.h"
53
54 static const char *regnames_a[] = {
55 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
56 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
57 "a12" , "a13" , "a14" , "a15",
58 };
59
60 static const char *regnames_d[] = {
61 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
62 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
63 "d12" , "d13" , "d14" , "d15",
64 };
65
66 typedef struct DisasContext {
67 struct TranslationBlock *tb;
68 target_ulong pc, saved_pc, next_pc;
69 uint32_t opcode;
70 int singlestep_enabled;
71 /* Routine used to access memory */
72 int mem_idx;
73 uint32_t hflags, saved_hflags;
74 int bstate;
75 } DisasContext;
76
77 enum {
78
79 BS_NONE = 0,
80 BS_STOP = 1,
81 BS_BRANCH = 2,
82 BS_EXCP = 3,
83 };
84
85 enum {
86 MODE_LL = 0,
87 MODE_LU = 1,
88 MODE_UL = 2,
89 MODE_UU = 3,
90 };
91
92 void tricore_cpu_dump_state(CPUState *cs, FILE *f,
93 fprintf_function cpu_fprintf, int flags)
94 {
95 TriCoreCPU *cpu = TRICORE_CPU(cs);
96 CPUTriCoreState *env = &cpu->env;
97 uint32_t psw;
98 int i;
99
100 psw = psw_read(env);
101
102 cpu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
103 cpu_fprintf(f, " PSW: " TARGET_FMT_lx, psw);
104 cpu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR);
105 cpu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI);
106 cpu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
107 cpu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
108
109 for (i = 0; i < 16; ++i) {
110 if ((i & 3) == 0) {
111 cpu_fprintf(f, "\nGPR A%02d:", i);
112 }
113 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
114 }
115 for (i = 0; i < 16; ++i) {
116 if ((i & 3) == 0) {
117 cpu_fprintf(f, "\nGPR D%02d:", i);
118 }
119 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
120 }
121 cpu_fprintf(f, "\n");
122 }
123
124 /*
125 * Functions to generate micro-ops
126 */
127
128 /* Makros for generating helpers */
129
130 #define gen_helper_1arg(name, arg) do { \
131 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
132 gen_helper_##name(cpu_env, helper_tmp); \
133 tcg_temp_free_i32(helper_tmp); \
134 } while (0)
135
136 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
137 TCGv arg00 = tcg_temp_new(); \
138 TCGv arg01 = tcg_temp_new(); \
139 TCGv arg11 = tcg_temp_new(); \
140 tcg_gen_sari_tl(arg00, arg0, 16); \
141 tcg_gen_ext16s_tl(arg01, arg0); \
142 tcg_gen_ext16s_tl(arg11, arg1); \
143 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
144 tcg_temp_free(arg00); \
145 tcg_temp_free(arg01); \
146 tcg_temp_free(arg11); \
147 } while (0)
148
149 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
150 TCGv arg00 = tcg_temp_new(); \
151 TCGv arg01 = tcg_temp_new(); \
152 TCGv arg10 = tcg_temp_new(); \
153 TCGv arg11 = tcg_temp_new(); \
154 tcg_gen_sari_tl(arg00, arg0, 16); \
155 tcg_gen_ext16s_tl(arg01, arg0); \
156 tcg_gen_sari_tl(arg11, arg1, 16); \
157 tcg_gen_ext16s_tl(arg10, arg1); \
158 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
159 tcg_temp_free(arg00); \
160 tcg_temp_free(arg01); \
161 tcg_temp_free(arg10); \
162 tcg_temp_free(arg11); \
163 } while (0)
164
165 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
166 TCGv arg00 = tcg_temp_new(); \
167 TCGv arg01 = tcg_temp_new(); \
168 TCGv arg10 = tcg_temp_new(); \
169 TCGv arg11 = tcg_temp_new(); \
170 tcg_gen_sari_tl(arg00, arg0, 16); \
171 tcg_gen_ext16s_tl(arg01, arg0); \
172 tcg_gen_sari_tl(arg10, arg1, 16); \
173 tcg_gen_ext16s_tl(arg11, arg1); \
174 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
175 tcg_temp_free(arg00); \
176 tcg_temp_free(arg01); \
177 tcg_temp_free(arg10); \
178 tcg_temp_free(arg11); \
179 } while (0)
180
181 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
182 TCGv arg00 = tcg_temp_new(); \
183 TCGv arg01 = tcg_temp_new(); \
184 TCGv arg11 = tcg_temp_new(); \
185 tcg_gen_sari_tl(arg01, arg0, 16); \
186 tcg_gen_ext16s_tl(arg00, arg0); \
187 tcg_gen_sari_tl(arg11, arg1, 16); \
188 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
189 tcg_temp_free(arg00); \
190 tcg_temp_free(arg01); \
191 tcg_temp_free(arg11); \
192 } while (0)
193
194 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
195 TCGv_i64 ret = tcg_temp_new_i64(); \
196 TCGv_i64 arg1 = tcg_temp_new_i64(); \
197 \
198 tcg_gen_concat_i32_i64(arg1, al1, ah1); \
199 gen_helper_##name(ret, arg1, arg2); \
200 tcg_gen_extr_i64_i32(rl, rh, ret); \
201 \
202 tcg_temp_free_i64(ret); \
203 tcg_temp_free_i64(arg1); \
204 } while (0)
205
206 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \
207 TCGv_i64 ret = tcg_temp_new_i64(); \
208 \
209 gen_helper_##name(ret, cpu_env, arg1, arg2); \
210 tcg_gen_extr_i64_i32(rl, rh, ret); \
211 \
212 tcg_temp_free_i64(ret); \
213 } while (0)
214
215 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
216 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
217 ((offset & 0x0fffff) << 1))
218
219 /* Functions for load/save to/from memory */
220
221 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
222 int16_t con, TCGMemOp mop)
223 {
224 TCGv temp = tcg_temp_new();
225 tcg_gen_addi_tl(temp, r2, con);
226 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
227 tcg_temp_free(temp);
228 }
229
230 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
231 int16_t con, TCGMemOp mop)
232 {
233 TCGv temp = tcg_temp_new();
234 tcg_gen_addi_tl(temp, r2, con);
235 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
236 tcg_temp_free(temp);
237 }
238
239 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
240 {
241 TCGv_i64 temp = tcg_temp_new_i64();
242
243 tcg_gen_concat_i32_i64(temp, rl, rh);
244 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
245
246 tcg_temp_free_i64(temp);
247 }
248
249 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
250 DisasContext *ctx)
251 {
252 TCGv temp = tcg_temp_new();
253 tcg_gen_addi_tl(temp, base, con);
254 gen_st_2regs_64(rh, rl, temp, ctx);
255 tcg_temp_free(temp);
256 }
257
258 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
259 {
260 TCGv_i64 temp = tcg_temp_new_i64();
261
262 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
263 /* write back to two 32 bit regs */
264 tcg_gen_extr_i64_i32(rl, rh, temp);
265
266 tcg_temp_free_i64(temp);
267 }
268
269 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
270 DisasContext *ctx)
271 {
272 TCGv temp = tcg_temp_new();
273 tcg_gen_addi_tl(temp, base, con);
274 gen_ld_2regs_64(rh, rl, temp, ctx);
275 tcg_temp_free(temp);
276 }
277
278 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
279 TCGMemOp mop)
280 {
281 TCGv temp = tcg_temp_new();
282 tcg_gen_addi_tl(temp, r2, off);
283 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
284 tcg_gen_mov_tl(r2, temp);
285 tcg_temp_free(temp);
286 }
287
288 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
289 TCGMemOp mop)
290 {
291 TCGv temp = tcg_temp_new();
292 tcg_gen_addi_tl(temp, r2, off);
293 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
294 tcg_gen_mov_tl(r2, temp);
295 tcg_temp_free(temp);
296 }
297
298 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
299 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
300 {
301 TCGv temp = tcg_temp_new();
302 TCGv temp2 = tcg_temp_new();
303
304 /* temp = (M(EA, word) */
305 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
306 /* temp = temp & ~E[a][63:32]) */
307 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
308 /* temp2 = (E[a][31:0] & E[a][63:32]); */
309 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
310 /* temp = temp | temp2; */
311 tcg_gen_or_tl(temp, temp, temp2);
312 /* M(EA, word) = temp; */
313 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
314
315 tcg_temp_free(temp);
316 tcg_temp_free(temp2);
317 }
318
319 /* tmp = M(EA, word);
320 M(EA, word) = D[a];
321 D[a] = tmp[31:0];*/
322 static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
323 {
324 TCGv temp = tcg_temp_new();
325
326 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
327 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
328 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
329
330 tcg_temp_free(temp);
331 }
332
333 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
334 {
335 TCGv temp = tcg_temp_new();
336 TCGv temp2 = tcg_temp_new();
337 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
338 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp,
339 cpu_gpr_d[reg], temp);
340 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
341 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
342
343 tcg_temp_free(temp);
344 tcg_temp_free(temp2);
345 }
346
347 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
348 {
349 TCGv temp = tcg_temp_new();
350 TCGv temp2 = tcg_temp_new();
351 TCGv temp3 = tcg_temp_new();
352
353 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
354 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]);
355 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]);
356 tcg_gen_or_tl(temp2, temp2, temp3);
357 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
358 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
359
360 tcg_temp_free(temp);
361 tcg_temp_free(temp2);
362 tcg_temp_free(temp3);
363 }
364
365
366 /* We generate loads and store to core special function register (csfr) through
367 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
368 makros R, A and E, which allow read-only, all and endinit protected access.
369 These makros also specify in which ISA version the csfr was introduced. */
370 #define R(ADDRESS, REG, FEATURE) \
371 case ADDRESS: \
372 if (tricore_feature(env, FEATURE)) { \
373 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
374 } \
375 break;
376 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
377 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
378 static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset)
379 {
380 /* since we're caching PSW make this a special case */
381 if (offset == 0xfe04) {
382 gen_helper_psw_read(ret, cpu_env);
383 } else {
384 switch (offset) {
385 #include "csfr.def"
386 }
387 }
388 }
389 #undef R
390 #undef A
391 #undef E
392
393 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
394 since no execption occurs */
395 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
396 case ADDRESS: \
397 if (tricore_feature(env, FEATURE)) { \
398 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
399 } \
400 break;
401 /* Endinit protected registers
402 TODO: Since the endinit bit is in a register of a not yet implemented
403 watchdog device, we handle endinit protected registers like
404 all-access registers for now. */
405 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
406 static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1,
407 int32_t offset)
408 {
409 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
410 /* since we're caching PSW make this a special case */
411 if (offset == 0xfe04) {
412 gen_helper_psw_write(cpu_env, r1);
413 } else {
414 switch (offset) {
415 #include "csfr.def"
416 }
417 }
418 } else {
419 /* generate privilege trap */
420 }
421 }
422
423 /* Functions for arithmetic instructions */
424
425 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
426 {
427 TCGv t0 = tcg_temp_new_i32();
428 TCGv result = tcg_temp_new_i32();
429 /* Addition and set V/SV bits */
430 tcg_gen_add_tl(result, r1, r2);
431 /* calc V bit */
432 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
433 tcg_gen_xor_tl(t0, r1, r2);
434 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
435 /* Calc SV bit */
436 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
437 /* Calc AV/SAV bits */
438 tcg_gen_add_tl(cpu_PSW_AV, result, result);
439 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
440 /* calc SAV */
441 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
442 /* write back result */
443 tcg_gen_mov_tl(ret, result);
444
445 tcg_temp_free(result);
446 tcg_temp_free(t0);
447 }
448
449 static inline void
450 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
451 {
452 TCGv temp = tcg_temp_new();
453 TCGv_i64 t0 = tcg_temp_new_i64();
454 TCGv_i64 t1 = tcg_temp_new_i64();
455 TCGv_i64 result = tcg_temp_new_i64();
456
457 tcg_gen_add_i64(result, r1, r2);
458 /* calc v bit */
459 tcg_gen_xor_i64(t1, result, r1);
460 tcg_gen_xor_i64(t0, r1, r2);
461 tcg_gen_andc_i64(t1, t1, t0);
462 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
463 /* calc SV bit */
464 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
465 /* calc AV/SAV bits */
466 tcg_gen_extrh_i64_i32(temp, result);
467 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
468 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
469 /* calc SAV */
470 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
471 /* write back result */
472 tcg_gen_mov_i64(ret, result);
473
474 tcg_temp_free(temp);
475 tcg_temp_free_i64(result);
476 tcg_temp_free_i64(t0);
477 tcg_temp_free_i64(t1);
478 }
479
480 static inline void
481 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
482 TCGv r3, void(*op1)(TCGv, TCGv, TCGv),
483 void(*op2)(TCGv, TCGv, TCGv))
484 {
485 TCGv temp = tcg_temp_new();
486 TCGv temp2 = tcg_temp_new();
487 TCGv temp3 = tcg_temp_new();
488 TCGv temp4 = tcg_temp_new();
489
490 (*op1)(temp, r1_low, r2);
491 /* calc V0 bit */
492 tcg_gen_xor_tl(temp2, temp, r1_low);
493 tcg_gen_xor_tl(temp3, r1_low, r2);
494 if (op1 == tcg_gen_add_tl) {
495 tcg_gen_andc_tl(temp2, temp2, temp3);
496 } else {
497 tcg_gen_and_tl(temp2, temp2, temp3);
498 }
499
500 (*op2)(temp3, r1_high, r3);
501 /* calc V1 bit */
502 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high);
503 tcg_gen_xor_tl(temp4, r1_high, r3);
504 if (op2 == tcg_gen_add_tl) {
505 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4);
506 } else {
507 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4);
508 }
509 /* combine V0/V1 bits */
510 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2);
511 /* calc sv bit */
512 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
513 /* write result */
514 tcg_gen_mov_tl(ret_low, temp);
515 tcg_gen_mov_tl(ret_high, temp3);
516 /* calc AV bit */
517 tcg_gen_add_tl(temp, ret_low, ret_low);
518 tcg_gen_xor_tl(temp, temp, ret_low);
519 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
520 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high);
521 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
522 /* calc SAV bit */
523 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
524
525 tcg_temp_free(temp);
526 tcg_temp_free(temp2);
527 tcg_temp_free(temp3);
528 tcg_temp_free(temp4);
529 }
530
531 /* ret = r2 + (r1 * r3); */
532 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
533 {
534 TCGv_i64 t1 = tcg_temp_new_i64();
535 TCGv_i64 t2 = tcg_temp_new_i64();
536 TCGv_i64 t3 = tcg_temp_new_i64();
537
538 tcg_gen_ext_i32_i64(t1, r1);
539 tcg_gen_ext_i32_i64(t2, r2);
540 tcg_gen_ext_i32_i64(t3, r3);
541
542 tcg_gen_mul_i64(t1, t1, t3);
543 tcg_gen_add_i64(t1, t2, t1);
544
545 tcg_gen_extrl_i64_i32(ret, t1);
546 /* calc V
547 t1 > 0x7fffffff */
548 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
549 /* t1 < -0x80000000 */
550 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
551 tcg_gen_or_i64(t2, t2, t3);
552 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
553 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
554 /* Calc SV bit */
555 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
556 /* Calc AV/SAV bits */
557 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
558 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
559 /* calc SAV */
560 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
561
562 tcg_temp_free_i64(t1);
563 tcg_temp_free_i64(t2);
564 tcg_temp_free_i64(t3);
565 }
566
567 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
568 {
569 TCGv temp = tcg_const_i32(con);
570 gen_madd32_d(ret, r1, r2, temp);
571 tcg_temp_free(temp);
572 }
573
574 static inline void
575 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
576 TCGv r3)
577 {
578 TCGv t1 = tcg_temp_new();
579 TCGv t2 = tcg_temp_new();
580 TCGv t3 = tcg_temp_new();
581 TCGv t4 = tcg_temp_new();
582
583 tcg_gen_muls2_tl(t1, t2, r1, r3);
584 /* only the add can overflow */
585 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2);
586 /* calc V bit */
587 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
588 tcg_gen_xor_tl(t1, r2_high, t2);
589 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1);
590 /* Calc SV bit */
591 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
592 /* Calc AV/SAV bits */
593 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
594 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
595 /* calc SAV */
596 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
597 /* write back the result */
598 tcg_gen_mov_tl(ret_low, t3);
599 tcg_gen_mov_tl(ret_high, t4);
600
601 tcg_temp_free(t1);
602 tcg_temp_free(t2);
603 tcg_temp_free(t3);
604 tcg_temp_free(t4);
605 }
606
607 static inline void
608 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
609 TCGv r3)
610 {
611 TCGv_i64 t1 = tcg_temp_new_i64();
612 TCGv_i64 t2 = tcg_temp_new_i64();
613 TCGv_i64 t3 = tcg_temp_new_i64();
614
615 tcg_gen_extu_i32_i64(t1, r1);
616 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
617 tcg_gen_extu_i32_i64(t3, r3);
618
619 tcg_gen_mul_i64(t1, t1, t3);
620 tcg_gen_add_i64(t2, t2, t1);
621 /* write back result */
622 tcg_gen_extr_i64_i32(ret_low, ret_high, t2);
623 /* only the add overflows, if t2 < t1
624 calc V bit */
625 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1);
626 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
627 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
628 /* Calc SV bit */
629 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
630 /* Calc AV/SAV bits */
631 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
632 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
633 /* calc SAV */
634 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
635
636 tcg_temp_free_i64(t1);
637 tcg_temp_free_i64(t2);
638 tcg_temp_free_i64(t3);
639 }
640
641 static inline void
642 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
643 int32_t con)
644 {
645 TCGv temp = tcg_const_i32(con);
646 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
647 tcg_temp_free(temp);
648 }
649
650 static inline void
651 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
652 int32_t con)
653 {
654 TCGv temp = tcg_const_i32(con);
655 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
656 tcg_temp_free(temp);
657 }
658
659 static inline void
660 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
661 TCGv r3, uint32_t n, uint32_t mode)
662 {
663 TCGv temp = tcg_const_i32(n);
664 TCGv temp2 = tcg_temp_new();
665 TCGv_i64 temp64 = tcg_temp_new_i64();
666 switch (mode) {
667 case MODE_LL:
668 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
669 break;
670 case MODE_LU:
671 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
672 break;
673 case MODE_UL:
674 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
675 break;
676 case MODE_UU:
677 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
678 break;
679 }
680 tcg_gen_extr_i64_i32(temp, temp2, temp64);
681 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
682 tcg_gen_add_tl, tcg_gen_add_tl);
683 tcg_temp_free(temp);
684 tcg_temp_free(temp2);
685 tcg_temp_free_i64(temp64);
686 }
687
688 static inline void
689 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
690 TCGv r3, uint32_t n, uint32_t mode)
691 {
692 TCGv temp = tcg_const_i32(n);
693 TCGv temp2 = tcg_temp_new();
694 TCGv_i64 temp64 = tcg_temp_new_i64();
695 switch (mode) {
696 case MODE_LL:
697 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
698 break;
699 case MODE_LU:
700 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
701 break;
702 case MODE_UL:
703 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
704 break;
705 case MODE_UU:
706 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
707 break;
708 }
709 tcg_gen_extr_i64_i32(temp, temp2, temp64);
710 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
711 tcg_gen_sub_tl, tcg_gen_add_tl);
712 tcg_temp_free(temp);
713 tcg_temp_free(temp2);
714 tcg_temp_free_i64(temp64);
715 }
716
717 static inline void
718 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
719 TCGv r3, uint32_t n, uint32_t mode)
720 {
721 TCGv temp = tcg_const_i32(n);
722 TCGv_i64 temp64 = tcg_temp_new_i64();
723 TCGv_i64 temp64_2 = tcg_temp_new_i64();
724 TCGv_i64 temp64_3 = tcg_temp_new_i64();
725 switch (mode) {
726 case MODE_LL:
727 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
728 break;
729 case MODE_LU:
730 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
731 break;
732 case MODE_UL:
733 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
734 break;
735 case MODE_UU:
736 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
737 break;
738 }
739 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
740 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
741 tcg_gen_ext32s_i64(temp64, temp64); /* low */
742 tcg_gen_sub_i64(temp64, temp64_2, temp64);
743 tcg_gen_shli_i64(temp64, temp64, 16);
744
745 gen_add64_d(temp64_2, temp64_3, temp64);
746 /* write back result */
747 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
748
749 tcg_temp_free(temp);
750 tcg_temp_free_i64(temp64);
751 tcg_temp_free_i64(temp64_2);
752 tcg_temp_free_i64(temp64_3);
753 }
754
755 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2);
756
757 static inline void
758 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
759 TCGv r3, uint32_t n, uint32_t mode)
760 {
761 TCGv temp = tcg_const_i32(n);
762 TCGv temp2 = tcg_temp_new();
763 TCGv temp3 = tcg_temp_new();
764 TCGv_i64 temp64 = tcg_temp_new_i64();
765
766 switch (mode) {
767 case MODE_LL:
768 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
769 break;
770 case MODE_LU:
771 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
772 break;
773 case MODE_UL:
774 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
775 break;
776 case MODE_UU:
777 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
778 break;
779 }
780 tcg_gen_extr_i64_i32(temp, temp2, temp64);
781 gen_adds(ret_low, r1_low, temp);
782 tcg_gen_mov_tl(temp, cpu_PSW_V);
783 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
784 gen_adds(ret_high, r1_high, temp2);
785 /* combine v bits */
786 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
787 /* combine av bits */
788 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
789
790 tcg_temp_free(temp);
791 tcg_temp_free(temp2);
792 tcg_temp_free(temp3);
793 tcg_temp_free_i64(temp64);
794
795 }
796
797 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2);
798
799 static inline void
800 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
801 TCGv r3, uint32_t n, uint32_t mode)
802 {
803 TCGv temp = tcg_const_i32(n);
804 TCGv temp2 = tcg_temp_new();
805 TCGv temp3 = tcg_temp_new();
806 TCGv_i64 temp64 = tcg_temp_new_i64();
807
808 switch (mode) {
809 case MODE_LL:
810 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
811 break;
812 case MODE_LU:
813 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
814 break;
815 case MODE_UL:
816 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
817 break;
818 case MODE_UU:
819 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
820 break;
821 }
822 tcg_gen_extr_i64_i32(temp, temp2, temp64);
823 gen_subs(ret_low, r1_low, temp);
824 tcg_gen_mov_tl(temp, cpu_PSW_V);
825 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
826 gen_adds(ret_high, r1_high, temp2);
827 /* combine v bits */
828 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
829 /* combine av bits */
830 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
831
832 tcg_temp_free(temp);
833 tcg_temp_free(temp2);
834 tcg_temp_free(temp3);
835 tcg_temp_free_i64(temp64);
836
837 }
838
839 static inline void
840 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
841 TCGv r3, uint32_t n, uint32_t mode)
842 {
843 TCGv temp = tcg_const_i32(n);
844 TCGv_i64 temp64 = tcg_temp_new_i64();
845 TCGv_i64 temp64_2 = tcg_temp_new_i64();
846
847 switch (mode) {
848 case MODE_LL:
849 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
850 break;
851 case MODE_LU:
852 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
853 break;
854 case MODE_UL:
855 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
856 break;
857 case MODE_UU:
858 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
859 break;
860 }
861 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
862 tcg_gen_ext32s_i64(temp64, temp64); /* low */
863 tcg_gen_sub_i64(temp64, temp64_2, temp64);
864 tcg_gen_shli_i64(temp64, temp64, 16);
865 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
866
867 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
868 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
869
870 tcg_temp_free(temp);
871 tcg_temp_free_i64(temp64);
872 tcg_temp_free_i64(temp64_2);
873 }
874
875
876 static inline void
877 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
878 TCGv r3, uint32_t n, uint32_t mode)
879 {
880 TCGv temp = tcg_const_i32(n);
881 TCGv_i64 temp64 = tcg_temp_new_i64();
882 TCGv_i64 temp64_2 = tcg_temp_new_i64();
883 TCGv_i64 temp64_3 = tcg_temp_new_i64();
884 switch (mode) {
885 case MODE_LL:
886 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
887 break;
888 case MODE_LU:
889 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
890 break;
891 case MODE_UL:
892 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
893 break;
894 case MODE_UU:
895 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
896 break;
897 }
898 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
899 gen_add64_d(temp64_3, temp64_2, temp64);
900 /* write back result */
901 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
902
903 tcg_temp_free(temp);
904 tcg_temp_free_i64(temp64);
905 tcg_temp_free_i64(temp64_2);
906 tcg_temp_free_i64(temp64_3);
907 }
908
909 static inline void
910 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
911 TCGv r3, uint32_t n, uint32_t mode)
912 {
913 TCGv temp = tcg_const_i32(n);
914 TCGv_i64 temp64 = tcg_temp_new_i64();
915 TCGv_i64 temp64_2 = tcg_temp_new_i64();
916 switch (mode) {
917 case MODE_LL:
918 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
919 break;
920 case MODE_LU:
921 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
922 break;
923 case MODE_UL:
924 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
925 break;
926 case MODE_UU:
927 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
928 break;
929 }
930 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
931 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
932 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
933
934 tcg_temp_free(temp);
935 tcg_temp_free_i64(temp64);
936 tcg_temp_free_i64(temp64_2);
937 }
938
939 static inline void
940 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
941 uint32_t mode)
942 {
943 TCGv temp = tcg_const_i32(n);
944 TCGv_i64 temp64 = tcg_temp_new_i64();
945 switch (mode) {
946 case MODE_LL:
947 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
948 break;
949 case MODE_LU:
950 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
951 break;
952 case MODE_UL:
953 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
954 break;
955 case MODE_UU:
956 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
957 break;
958 }
959 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
960
961 tcg_temp_free(temp);
962 tcg_temp_free_i64(temp64);
963 }
964
965 static inline void
966 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
967 {
968 TCGv temp = tcg_temp_new();
969 TCGv temp2 = tcg_temp_new();
970
971 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
972 tcg_gen_shli_tl(temp, r1, 16);
973 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
974
975 tcg_temp_free(temp);
976 tcg_temp_free(temp2);
977 }
978
979 static inline void
980 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
981 {
982 TCGv temp = tcg_const_i32(n);
983 TCGv temp2 = tcg_temp_new();
984 TCGv_i64 temp64 = tcg_temp_new_i64();
985 switch (mode) {
986 case MODE_LL:
987 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
988 break;
989 case MODE_LU:
990 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
991 break;
992 case MODE_UL:
993 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
994 break;
995 case MODE_UU:
996 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
997 break;
998 }
999 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1000 tcg_gen_shli_tl(temp, r1, 16);
1001 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2);
1002
1003 tcg_temp_free(temp);
1004 tcg_temp_free(temp2);
1005 tcg_temp_free_i64(temp64);
1006 }
1007
1008
1009 static inline void
1010 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1011 uint32_t n, uint32_t mode)
1012 {
1013 TCGv temp = tcg_const_i32(n);
1014 TCGv_i64 temp64 = tcg_temp_new_i64();
1015 switch (mode) {
1016 case MODE_LL:
1017 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1018 break;
1019 case MODE_LU:
1020 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1021 break;
1022 case MODE_UL:
1023 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1024 break;
1025 case MODE_UU:
1026 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1027 break;
1028 }
1029 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1030
1031 tcg_temp_free(temp);
1032 tcg_temp_free_i64(temp64);
1033 }
1034
1035 static inline void
1036 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1037 {
1038 TCGv temp = tcg_temp_new();
1039 TCGv temp2 = tcg_temp_new();
1040
1041 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1042 tcg_gen_shli_tl(temp, r1, 16);
1043 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
1044
1045 tcg_temp_free(temp);
1046 tcg_temp_free(temp2);
1047 }
1048
1049 static inline void
1050 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1051 {
1052 TCGv temp = tcg_const_i32(n);
1053 TCGv temp2 = tcg_temp_new();
1054 TCGv_i64 temp64 = tcg_temp_new_i64();
1055 switch (mode) {
1056 case MODE_LL:
1057 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1058 break;
1059 case MODE_LU:
1060 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1061 break;
1062 case MODE_UL:
1063 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1064 break;
1065 case MODE_UU:
1066 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1067 break;
1068 }
1069 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1070 tcg_gen_shli_tl(temp, r1, 16);
1071 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2);
1072
1073 tcg_temp_free(temp);
1074 tcg_temp_free(temp2);
1075 tcg_temp_free_i64(temp64);
1076 }
1077
1078 static inline void
1079 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1080 {
1081 TCGv temp = tcg_const_i32(n);
1082 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp);
1083 tcg_temp_free(temp);
1084 }
1085
1086 static inline void
1087 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1088 {
1089 TCGv temp = tcg_const_i32(n);
1090 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1091 tcg_temp_free(temp);
1092 }
1093
1094 static inline void
1095 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1096 uint32_t up_shift, CPUTriCoreState *env)
1097 {
1098 TCGv temp = tcg_temp_new();
1099 TCGv temp2 = tcg_temp_new();
1100 TCGv temp3 = tcg_temp_new();
1101 TCGv_i64 t1 = tcg_temp_new_i64();
1102 TCGv_i64 t2 = tcg_temp_new_i64();
1103 TCGv_i64 t3 = tcg_temp_new_i64();
1104
1105 tcg_gen_ext_i32_i64(t2, arg2);
1106 tcg_gen_ext_i32_i64(t3, arg3);
1107
1108 tcg_gen_mul_i64(t2, t2, t3);
1109 tcg_gen_shli_i64(t2, t2, n);
1110
1111 tcg_gen_ext_i32_i64(t1, arg1);
1112 tcg_gen_sari_i64(t2, t2, up_shift);
1113
1114 tcg_gen_add_i64(t3, t1, t2);
1115 tcg_gen_extrl_i64_i32(temp3, t3);
1116 /* calc v bit */
1117 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1118 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1119 tcg_gen_or_i64(t1, t1, t2);
1120 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1121 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1122 /* We produce an overflow on the host if the mul before was
1123 (0x80000000 * 0x80000000) << 1). If this is the
1124 case, we negate the ovf. */
1125 if (n == 1) {
1126 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1127 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1128 tcg_gen_and_tl(temp, temp, temp2);
1129 tcg_gen_shli_tl(temp, temp, 31);
1130 /* negate v bit, if special condition */
1131 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1132 }
1133 /* Calc SV bit */
1134 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1135 /* Calc AV/SAV bits */
1136 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1137 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1138 /* calc SAV */
1139 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1140 /* write back result */
1141 tcg_gen_mov_tl(ret, temp3);
1142
1143 tcg_temp_free(temp);
1144 tcg_temp_free(temp2);
1145 tcg_temp_free(temp3);
1146 tcg_temp_free_i64(t1);
1147 tcg_temp_free_i64(t2);
1148 tcg_temp_free_i64(t3);
1149 }
1150
1151 static inline void
1152 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1153 {
1154 TCGv temp = tcg_temp_new();
1155 TCGv temp2 = tcg_temp_new();
1156 if (n == 0) {
1157 tcg_gen_mul_tl(temp, arg2, arg3);
1158 } else { /* n is expected to be 1 */
1159 tcg_gen_mul_tl(temp, arg2, arg3);
1160 tcg_gen_shli_tl(temp, temp, 1);
1161 /* catch special case r1 = r2 = 0x8000 */
1162 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1163 tcg_gen_sub_tl(temp, temp, temp2);
1164 }
1165 gen_add_d(ret, arg1, temp);
1166
1167 tcg_temp_free(temp);
1168 tcg_temp_free(temp2);
1169 }
1170
1171 static inline void
1172 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1173 {
1174 TCGv temp = tcg_temp_new();
1175 TCGv temp2 = tcg_temp_new();
1176 if (n == 0) {
1177 tcg_gen_mul_tl(temp, arg2, arg3);
1178 } else { /* n is expected to be 1 */
1179 tcg_gen_mul_tl(temp, arg2, arg3);
1180 tcg_gen_shli_tl(temp, temp, 1);
1181 /* catch special case r1 = r2 = 0x8000 */
1182 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1183 tcg_gen_sub_tl(temp, temp, temp2);
1184 }
1185 gen_adds(ret, arg1, temp);
1186
1187 tcg_temp_free(temp);
1188 tcg_temp_free(temp2);
1189 }
1190
1191 static inline void
1192 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1193 TCGv arg3, uint32_t n)
1194 {
1195 TCGv temp = tcg_temp_new();
1196 TCGv temp2 = tcg_temp_new();
1197 TCGv_i64 t1 = tcg_temp_new_i64();
1198 TCGv_i64 t2 = tcg_temp_new_i64();
1199 TCGv_i64 t3 = tcg_temp_new_i64();
1200
1201 if (n == 0) {
1202 tcg_gen_mul_tl(temp, arg2, arg3);
1203 } else { /* n is expected to be 1 */
1204 tcg_gen_mul_tl(temp, arg2, arg3);
1205 tcg_gen_shli_tl(temp, temp, 1);
1206 /* catch special case r1 = r2 = 0x8000 */
1207 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1208 tcg_gen_sub_tl(temp, temp, temp2);
1209 }
1210 tcg_gen_ext_i32_i64(t2, temp);
1211 tcg_gen_shli_i64(t2, t2, 16);
1212 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1213 gen_add64_d(t3, t1, t2);
1214 /* write back result */
1215 tcg_gen_extr_i64_i32(rl, rh, t3);
1216
1217 tcg_temp_free_i64(t1);
1218 tcg_temp_free_i64(t2);
1219 tcg_temp_free_i64(t3);
1220 tcg_temp_free(temp);
1221 tcg_temp_free(temp2);
1222 }
1223
1224 static inline void
1225 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1226 TCGv arg3, uint32_t n)
1227 {
1228 TCGv temp = tcg_temp_new();
1229 TCGv temp2 = tcg_temp_new();
1230 TCGv_i64 t1 = tcg_temp_new_i64();
1231 TCGv_i64 t2 = tcg_temp_new_i64();
1232
1233 if (n == 0) {
1234 tcg_gen_mul_tl(temp, arg2, arg3);
1235 } else { /* n is expected to be 1 */
1236 tcg_gen_mul_tl(temp, arg2, arg3);
1237 tcg_gen_shli_tl(temp, temp, 1);
1238 /* catch special case r1 = r2 = 0x8000 */
1239 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1240 tcg_gen_sub_tl(temp, temp, temp2);
1241 }
1242 tcg_gen_ext_i32_i64(t2, temp);
1243 tcg_gen_shli_i64(t2, t2, 16);
1244 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1245
1246 gen_helper_add64_ssov(t1, cpu_env, t1, t2);
1247 tcg_gen_extr_i64_i32(rl, rh, t1);
1248
1249 tcg_temp_free(temp);
1250 tcg_temp_free(temp2);
1251 tcg_temp_free_i64(t1);
1252 tcg_temp_free_i64(t2);
1253 }
1254
1255 static inline void
1256 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1257 TCGv arg3, uint32_t n, CPUTriCoreState *env)
1258 {
1259 TCGv_i64 t1 = tcg_temp_new_i64();
1260 TCGv_i64 t2 = tcg_temp_new_i64();
1261 TCGv_i64 t3 = tcg_temp_new_i64();
1262 TCGv_i64 t4 = tcg_temp_new_i64();
1263 TCGv temp, temp2;
1264
1265 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1266 tcg_gen_ext_i32_i64(t2, arg2);
1267 tcg_gen_ext_i32_i64(t3, arg3);
1268
1269 tcg_gen_mul_i64(t2, t2, t3);
1270 if (n != 0) {
1271 tcg_gen_shli_i64(t2, t2, 1);
1272 }
1273 tcg_gen_add_i64(t4, t1, t2);
1274 /* calc v bit */
1275 tcg_gen_xor_i64(t3, t4, t1);
1276 tcg_gen_xor_i64(t2, t1, t2);
1277 tcg_gen_andc_i64(t3, t3, t2);
1278 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
1279 /* We produce an overflow on the host if the mul before was
1280 (0x80000000 * 0x80000000) << 1). If this is the
1281 case, we negate the ovf. */
1282 if (n == 1) {
1283 temp = tcg_temp_new();
1284 temp2 = tcg_temp_new();
1285 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1286 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1287 tcg_gen_and_tl(temp, temp, temp2);
1288 tcg_gen_shli_tl(temp, temp, 31);
1289 /* negate v bit, if special condition */
1290 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1291
1292 tcg_temp_free(temp);
1293 tcg_temp_free(temp2);
1294 }
1295 /* write back result */
1296 tcg_gen_extr_i64_i32(rl, rh, t4);
1297 /* Calc SV bit */
1298 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1299 /* Calc AV/SAV bits */
1300 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1301 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1302 /* calc SAV */
1303 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1304
1305 tcg_temp_free_i64(t1);
1306 tcg_temp_free_i64(t2);
1307 tcg_temp_free_i64(t3);
1308 tcg_temp_free_i64(t4);
1309 }
1310
1311 static inline void
1312 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1313 uint32_t up_shift)
1314 {
1315 TCGv_i64 t1 = tcg_temp_new_i64();
1316 TCGv_i64 t2 = tcg_temp_new_i64();
1317 TCGv_i64 t3 = tcg_temp_new_i64();
1318
1319 tcg_gen_ext_i32_i64(t1, arg1);
1320 tcg_gen_ext_i32_i64(t2, arg2);
1321 tcg_gen_ext_i32_i64(t3, arg3);
1322
1323 tcg_gen_mul_i64(t2, t2, t3);
1324 tcg_gen_sari_i64(t2, t2, up_shift - n);
1325
1326 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2);
1327
1328 tcg_temp_free_i64(t1);
1329 tcg_temp_free_i64(t2);
1330 tcg_temp_free_i64(t3);
1331 }
1332
1333 static inline void
1334 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1335 TCGv arg3, uint32_t n)
1336 {
1337 TCGv_i64 r1 = tcg_temp_new_i64();
1338 TCGv temp = tcg_const_i32(n);
1339
1340 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1341 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
1342 tcg_gen_extr_i64_i32(rl, rh, r1);
1343
1344 tcg_temp_free_i64(r1);
1345 tcg_temp_free(temp);
1346 }
1347 /* ret = r2 - (r1 * r3); */
1348 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
1349 {
1350 TCGv_i64 t1 = tcg_temp_new_i64();
1351 TCGv_i64 t2 = tcg_temp_new_i64();
1352 TCGv_i64 t3 = tcg_temp_new_i64();
1353
1354 tcg_gen_ext_i32_i64(t1, r1);
1355 tcg_gen_ext_i32_i64(t2, r2);
1356 tcg_gen_ext_i32_i64(t3, r3);
1357
1358 tcg_gen_mul_i64(t1, t1, t3);
1359 tcg_gen_sub_i64(t1, t2, t1);
1360
1361 tcg_gen_extrl_i64_i32(ret, t1);
1362 /* calc V
1363 t2 > 0x7fffffff */
1364 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
1365 /* result < -0x80000000 */
1366 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
1367 tcg_gen_or_i64(t2, t2, t3);
1368 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
1369 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1370
1371 /* Calc SV bit */
1372 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1373 /* Calc AV/SAV bits */
1374 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1375 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1376 /* calc SAV */
1377 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1378
1379 tcg_temp_free_i64(t1);
1380 tcg_temp_free_i64(t2);
1381 tcg_temp_free_i64(t3);
1382 }
1383
1384 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1385 {
1386 TCGv temp = tcg_const_i32(con);
1387 gen_msub32_d(ret, r1, r2, temp);
1388 tcg_temp_free(temp);
1389 }
1390
1391 static inline void
1392 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1393 TCGv r3)
1394 {
1395 TCGv t1 = tcg_temp_new();
1396 TCGv t2 = tcg_temp_new();
1397 TCGv t3 = tcg_temp_new();
1398 TCGv t4 = tcg_temp_new();
1399
1400 tcg_gen_muls2_tl(t1, t2, r1, r3);
1401 /* only the sub can overflow */
1402 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2);
1403 /* calc V bit */
1404 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
1405 tcg_gen_xor_tl(t1, r2_high, t2);
1406 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1);
1407 /* Calc SV bit */
1408 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1409 /* Calc AV/SAV bits */
1410 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
1411 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
1412 /* calc SAV */
1413 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1414 /* write back the result */
1415 tcg_gen_mov_tl(ret_low, t3);
1416 tcg_gen_mov_tl(ret_high, t4);
1417
1418 tcg_temp_free(t1);
1419 tcg_temp_free(t2);
1420 tcg_temp_free(t3);
1421 tcg_temp_free(t4);
1422 }
1423
1424 static inline void
1425 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1426 int32_t con)
1427 {
1428 TCGv temp = tcg_const_i32(con);
1429 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1430 tcg_temp_free(temp);
1431 }
1432
1433 static inline void
1434 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1435 TCGv r3)
1436 {
1437 TCGv_i64 t1 = tcg_temp_new_i64();
1438 TCGv_i64 t2 = tcg_temp_new_i64();
1439 TCGv_i64 t3 = tcg_temp_new_i64();
1440
1441 tcg_gen_extu_i32_i64(t1, r1);
1442 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
1443 tcg_gen_extu_i32_i64(t3, r3);
1444
1445 tcg_gen_mul_i64(t1, t1, t3);
1446 tcg_gen_sub_i64(t3, t2, t1);
1447 tcg_gen_extr_i64_i32(ret_low, ret_high, t3);
1448 /* calc V bit, only the sub can overflow, if t1 > t2 */
1449 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2);
1450 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1451 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1452 /* Calc SV bit */
1453 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1454 /* Calc AV/SAV bits */
1455 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1456 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1457 /* calc SAV */
1458 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1459
1460 tcg_temp_free_i64(t1);
1461 tcg_temp_free_i64(t2);
1462 tcg_temp_free_i64(t3);
1463 }
1464
1465 static inline void
1466 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1467 int32_t con)
1468 {
1469 TCGv temp = tcg_const_i32(con);
1470 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1471 tcg_temp_free(temp);
1472 }
1473
1474 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
1475 {
1476 TCGv temp = tcg_const_i32(r2);
1477 gen_add_d(ret, r1, temp);
1478 tcg_temp_free(temp);
1479 }
1480 /* calculate the carry bit too */
1481 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
1482 {
1483 TCGv t0 = tcg_temp_new_i32();
1484 TCGv result = tcg_temp_new_i32();
1485
1486 tcg_gen_movi_tl(t0, 0);
1487 /* Addition and set C/V/SV bits */
1488 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
1489 /* calc V bit */
1490 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1491 tcg_gen_xor_tl(t0, r1, r2);
1492 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1493 /* Calc SV bit */
1494 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1495 /* Calc AV/SAV bits */
1496 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1497 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1498 /* calc SAV */
1499 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1500 /* write back result */
1501 tcg_gen_mov_tl(ret, result);
1502
1503 tcg_temp_free(result);
1504 tcg_temp_free(t0);
1505 }
1506
1507 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
1508 {
1509 TCGv temp = tcg_const_i32(con);
1510 gen_add_CC(ret, r1, temp);
1511 tcg_temp_free(temp);
1512 }
1513
1514 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
1515 {
1516 TCGv carry = tcg_temp_new_i32();
1517 TCGv t0 = tcg_temp_new_i32();
1518 TCGv result = tcg_temp_new_i32();
1519
1520 tcg_gen_movi_tl(t0, 0);
1521 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
1522 /* Addition, carry and set C/V/SV bits */
1523 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
1524 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
1525 /* calc V bit */
1526 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1527 tcg_gen_xor_tl(t0, r1, r2);
1528 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1529 /* Calc SV bit */
1530 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1531 /* Calc AV/SAV bits */
1532 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1533 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1534 /* calc SAV */
1535 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1536 /* write back result */
1537 tcg_gen_mov_tl(ret, result);
1538
1539 tcg_temp_free(result);
1540 tcg_temp_free(t0);
1541 tcg_temp_free(carry);
1542 }
1543
1544 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
1545 {
1546 TCGv temp = tcg_const_i32(con);
1547 gen_addc_CC(ret, r1, temp);
1548 tcg_temp_free(temp);
1549 }
1550
1551 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1552 TCGv r4)
1553 {
1554 TCGv temp = tcg_temp_new();
1555 TCGv temp2 = tcg_temp_new();
1556 TCGv result = tcg_temp_new();
1557 TCGv mask = tcg_temp_new();
1558 TCGv t0 = tcg_const_i32(0);
1559
1560 /* create mask for sticky bits */
1561 tcg_gen_setcond_tl(cond, mask, r4, t0);
1562 tcg_gen_shli_tl(mask, mask, 31);
1563
1564 tcg_gen_add_tl(result, r1, r2);
1565 /* Calc PSW_V */
1566 tcg_gen_xor_tl(temp, result, r1);
1567 tcg_gen_xor_tl(temp2, r1, r2);
1568 tcg_gen_andc_tl(temp, temp, temp2);
1569 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1570 /* Set PSW_SV */
1571 tcg_gen_and_tl(temp, temp, mask);
1572 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1573 /* calc AV bit */
1574 tcg_gen_add_tl(temp, result, result);
1575 tcg_gen_xor_tl(temp, temp, result);
1576 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1577 /* calc SAV bit */
1578 tcg_gen_and_tl(temp, temp, mask);
1579 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1580 /* write back result */
1581 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1582
1583 tcg_temp_free(t0);
1584 tcg_temp_free(temp);
1585 tcg_temp_free(temp2);
1586 tcg_temp_free(result);
1587 tcg_temp_free(mask);
1588 }
1589
1590 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
1591 TCGv r3, TCGv r4)
1592 {
1593 TCGv temp = tcg_const_i32(r2);
1594 gen_cond_add(cond, r1, temp, r3, r4);
1595 tcg_temp_free(temp);
1596 }
1597
1598 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
1599 {
1600 TCGv temp = tcg_temp_new_i32();
1601 TCGv result = tcg_temp_new_i32();
1602
1603 tcg_gen_sub_tl(result, r1, r2);
1604 /* calc V bit */
1605 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1606 tcg_gen_xor_tl(temp, r1, r2);
1607 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1608 /* calc SV bit */
1609 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1610 /* Calc AV bit */
1611 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1612 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1613 /* calc SAV bit */
1614 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1615 /* write back result */
1616 tcg_gen_mov_tl(ret, result);
1617
1618 tcg_temp_free(temp);
1619 tcg_temp_free(result);
1620 }
1621
1622 static inline void
1623 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
1624 {
1625 TCGv temp = tcg_temp_new();
1626 TCGv_i64 t0 = tcg_temp_new_i64();
1627 TCGv_i64 t1 = tcg_temp_new_i64();
1628 TCGv_i64 result = tcg_temp_new_i64();
1629
1630 tcg_gen_sub_i64(result, r1, r2);
1631 /* calc v bit */
1632 tcg_gen_xor_i64(t1, result, r1);
1633 tcg_gen_xor_i64(t0, r1, r2);
1634 tcg_gen_and_i64(t1, t1, t0);
1635 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
1636 /* calc SV bit */
1637 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1638 /* calc AV/SAV bits */
1639 tcg_gen_extrh_i64_i32(temp, result);
1640 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
1641 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
1642 /* calc SAV */
1643 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1644 /* write back result */
1645 tcg_gen_mov_i64(ret, result);
1646
1647 tcg_temp_free(temp);
1648 tcg_temp_free_i64(result);
1649 tcg_temp_free_i64(t0);
1650 tcg_temp_free_i64(t1);
1651 }
1652
1653 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
1654 {
1655 TCGv result = tcg_temp_new();
1656 TCGv temp = tcg_temp_new();
1657
1658 tcg_gen_sub_tl(result, r1, r2);
1659 /* calc C bit */
1660 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2);
1661 /* calc V bit */
1662 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1663 tcg_gen_xor_tl(temp, r1, r2);
1664 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1665 /* calc SV bit */
1666 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1667 /* Calc AV bit */
1668 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1669 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1670 /* calc SAV bit */
1671 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1672 /* write back result */
1673 tcg_gen_mov_tl(ret, result);
1674
1675 tcg_temp_free(result);
1676 tcg_temp_free(temp);
1677 }
1678
1679 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
1680 {
1681 TCGv temp = tcg_temp_new();
1682 tcg_gen_not_tl(temp, r2);
1683 gen_addc_CC(ret, r1, temp);
1684 tcg_temp_free(temp);
1685 }
1686
1687 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1688 TCGv r4)
1689 {
1690 TCGv temp = tcg_temp_new();
1691 TCGv temp2 = tcg_temp_new();
1692 TCGv result = tcg_temp_new();
1693 TCGv mask = tcg_temp_new();
1694 TCGv t0 = tcg_const_i32(0);
1695
1696 /* create mask for sticky bits */
1697 tcg_gen_setcond_tl(cond, mask, r4, t0);
1698 tcg_gen_shli_tl(mask, mask, 31);
1699
1700 tcg_gen_sub_tl(result, r1, r2);
1701 /* Calc PSW_V */
1702 tcg_gen_xor_tl(temp, result, r1);
1703 tcg_gen_xor_tl(temp2, r1, r2);
1704 tcg_gen_and_tl(temp, temp, temp2);
1705 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1706 /* Set PSW_SV */
1707 tcg_gen_and_tl(temp, temp, mask);
1708 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1709 /* calc AV bit */
1710 tcg_gen_add_tl(temp, result, result);
1711 tcg_gen_xor_tl(temp, temp, result);
1712 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1713 /* calc SAV bit */
1714 tcg_gen_and_tl(temp, temp, mask);
1715 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1716 /* write back result */
1717 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1718
1719 tcg_temp_free(t0);
1720 tcg_temp_free(temp);
1721 tcg_temp_free(temp2);
1722 tcg_temp_free(result);
1723 tcg_temp_free(mask);
1724 }
1725
1726 static inline void
1727 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1728 TCGv r3, uint32_t n, uint32_t mode)
1729 {
1730 TCGv temp = tcg_const_i32(n);
1731 TCGv temp2 = tcg_temp_new();
1732 TCGv_i64 temp64 = tcg_temp_new_i64();
1733 switch (mode) {
1734 case MODE_LL:
1735 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1736 break;
1737 case MODE_LU:
1738 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1739 break;
1740 case MODE_UL:
1741 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1742 break;
1743 case MODE_UU:
1744 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1745 break;
1746 }
1747 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1748 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
1749 tcg_gen_sub_tl, tcg_gen_sub_tl);
1750 tcg_temp_free(temp);
1751 tcg_temp_free(temp2);
1752 tcg_temp_free_i64(temp64);
1753 }
1754
1755 static inline void
1756 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1757 TCGv r3, uint32_t n, uint32_t mode)
1758 {
1759 TCGv temp = tcg_const_i32(n);
1760 TCGv temp2 = tcg_temp_new();
1761 TCGv temp3 = tcg_temp_new();
1762 TCGv_i64 temp64 = tcg_temp_new_i64();
1763
1764 switch (mode) {
1765 case MODE_LL:
1766 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1767 break;
1768 case MODE_LU:
1769 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1770 break;
1771 case MODE_UL:
1772 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1773 break;
1774 case MODE_UU:
1775 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1776 break;
1777 }
1778 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1779 gen_subs(ret_low, r1_low, temp);
1780 tcg_gen_mov_tl(temp, cpu_PSW_V);
1781 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
1782 gen_subs(ret_high, r1_high, temp2);
1783 /* combine v bits */
1784 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
1785 /* combine av bits */
1786 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
1787
1788 tcg_temp_free(temp);
1789 tcg_temp_free(temp2);
1790 tcg_temp_free(temp3);
1791 tcg_temp_free_i64(temp64);
1792 }
1793
1794 static inline void
1795 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1796 TCGv r3, uint32_t n, uint32_t mode)
1797 {
1798 TCGv temp = tcg_const_i32(n);
1799 TCGv_i64 temp64 = tcg_temp_new_i64();
1800 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1801 TCGv_i64 temp64_3 = tcg_temp_new_i64();
1802 switch (mode) {
1803 case MODE_LL:
1804 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
1805 break;
1806 case MODE_LU:
1807 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
1808 break;
1809 case MODE_UL:
1810 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
1811 break;
1812 case MODE_UU:
1813 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
1814 break;
1815 }
1816 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1817 gen_sub64_d(temp64_3, temp64_2, temp64);
1818 /* write back result */
1819 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
1820
1821 tcg_temp_free(temp);
1822 tcg_temp_free_i64(temp64);
1823 tcg_temp_free_i64(temp64_2);
1824 tcg_temp_free_i64(temp64_3);
1825 }
1826
1827 static inline void
1828 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1829 TCGv r3, uint32_t n, uint32_t mode)
1830 {
1831 TCGv temp = tcg_const_i32(n);
1832 TCGv_i64 temp64 = tcg_temp_new_i64();
1833 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1834 switch (mode) {
1835 case MODE_LL:
1836 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
1837 break;
1838 case MODE_LU:
1839 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
1840 break;
1841 case MODE_UL:
1842 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
1843 break;
1844 case MODE_UU:
1845 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
1846 break;
1847 }
1848 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1849 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
1850 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1851
1852 tcg_temp_free(temp);
1853 tcg_temp_free_i64(temp64);
1854 tcg_temp_free_i64(temp64_2);
1855 }
1856
1857 static inline void
1858 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
1859 uint32_t mode)
1860 {
1861 TCGv temp = tcg_const_i32(n);
1862 TCGv_i64 temp64 = tcg_temp_new_i64();
1863 switch (mode) {
1864 case MODE_LL:
1865 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1866 break;
1867 case MODE_LU:
1868 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1869 break;
1870 case MODE_UL:
1871 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1872 break;
1873 case MODE_UU:
1874 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1875 break;
1876 }
1877 gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high);
1878
1879 tcg_temp_free(temp);
1880 tcg_temp_free_i64(temp64);
1881 }
1882
1883 static inline void
1884 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1885 {
1886 TCGv temp = tcg_temp_new();
1887 TCGv temp2 = tcg_temp_new();
1888
1889 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1890 tcg_gen_shli_tl(temp, r1, 16);
1891 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode);
1892
1893 tcg_temp_free(temp);
1894 tcg_temp_free(temp2);
1895 }
1896
1897 static inline void
1898 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1899 uint32_t n, uint32_t mode)
1900 {
1901 TCGv temp = tcg_const_i32(n);
1902 TCGv_i64 temp64 = tcg_temp_new_i64();
1903 switch (mode) {
1904 case MODE_LL:
1905 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1906 break;
1907 case MODE_LU:
1908 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1909 break;
1910 case MODE_UL:
1911 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1912 break;
1913 case MODE_UU:
1914 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1915 break;
1916 }
1917 gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1918
1919 tcg_temp_free(temp);
1920 tcg_temp_free_i64(temp64);
1921 }
1922
1923 static inline void
1924 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1925 {
1926 TCGv temp = tcg_temp_new();
1927 TCGv temp2 = tcg_temp_new();
1928
1929 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1930 tcg_gen_shli_tl(temp, r1, 16);
1931 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode);
1932
1933 tcg_temp_free(temp);
1934 tcg_temp_free(temp2);
1935 }
1936
1937 static inline void
1938 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1939 {
1940 TCGv temp = tcg_const_i32(n);
1941 gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp);
1942 tcg_temp_free(temp);
1943 }
1944
1945 static inline void
1946 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1947 {
1948 TCGv temp = tcg_const_i32(n);
1949 gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1950 tcg_temp_free(temp);
1951 }
1952
1953 static inline void
1954 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1955 uint32_t up_shift, CPUTriCoreState *env)
1956 {
1957 TCGv temp = tcg_temp_new();
1958 TCGv temp2 = tcg_temp_new();
1959 TCGv temp3 = tcg_temp_new();
1960 TCGv_i64 t1 = tcg_temp_new_i64();
1961 TCGv_i64 t2 = tcg_temp_new_i64();
1962 TCGv_i64 t3 = tcg_temp_new_i64();
1963 TCGv_i64 t4 = tcg_temp_new_i64();
1964
1965 tcg_gen_ext_i32_i64(t2, arg2);
1966 tcg_gen_ext_i32_i64(t3, arg3);
1967
1968 tcg_gen_mul_i64(t2, t2, t3);
1969
1970 tcg_gen_ext_i32_i64(t1, arg1);
1971 /* if we shift part of the fraction out, we need to round up */
1972 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
1973 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
1974 tcg_gen_sari_i64(t2, t2, up_shift - n);
1975 tcg_gen_add_i64(t2, t2, t4);
1976
1977 tcg_gen_sub_i64(t3, t1, t2);
1978 tcg_gen_extrl_i64_i32(temp3, t3);
1979 /* calc v bit */
1980 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1981 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1982 tcg_gen_or_i64(t1, t1, t2);
1983 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1984 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1985 /* Calc SV bit */
1986 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1987 /* Calc AV/SAV bits */
1988 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1989 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1990 /* calc SAV */
1991 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1992 /* write back result */
1993 tcg_gen_mov_tl(ret, temp3);
1994
1995 tcg_temp_free(temp);
1996 tcg_temp_free(temp2);
1997 tcg_temp_free(temp3);
1998 tcg_temp_free_i64(t1);
1999 tcg_temp_free_i64(t2);
2000 tcg_temp_free_i64(t3);
2001 tcg_temp_free_i64(t4);
2002 }
2003
2004 static inline void
2005 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
2006 {
2007 TCGv temp = tcg_temp_new();
2008 TCGv temp2 = tcg_temp_new();
2009 if (n == 0) {
2010 tcg_gen_mul_tl(temp, arg2, arg3);
2011 } else { /* n is expected to be 1 */
2012 tcg_gen_mul_tl(temp, arg2, arg3);
2013 tcg_gen_shli_tl(temp, temp, 1);
2014 /* catch special case r1 = r2 = 0x8000 */
2015 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2016 tcg_gen_sub_tl(temp, temp, temp2);
2017 }
2018 gen_sub_d(ret, arg1, temp);
2019
2020 tcg_temp_free(temp);
2021 tcg_temp_free(temp2);
2022 }
2023
2024 static inline void
2025 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
2026 {
2027 TCGv temp = tcg_temp_new();
2028 TCGv temp2 = tcg_temp_new();
2029 if (n == 0) {
2030 tcg_gen_mul_tl(temp, arg2, arg3);
2031 } else { /* n is expected to be 1 */
2032 tcg_gen_mul_tl(temp, arg2, arg3);
2033 tcg_gen_shli_tl(temp, temp, 1);
2034 /* catch special case r1 = r2 = 0x8000 */
2035 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2036 tcg_gen_sub_tl(temp, temp, temp2);
2037 }
2038 gen_subs(ret, arg1, temp);
2039
2040 tcg_temp_free(temp);
2041 tcg_temp_free(temp2);
2042 }
2043
2044 static inline void
2045 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2046 TCGv arg3, uint32_t n)
2047 {
2048 TCGv temp = tcg_temp_new();
2049 TCGv temp2 = tcg_temp_new();
2050 TCGv_i64 t1 = tcg_temp_new_i64();
2051 TCGv_i64 t2 = tcg_temp_new_i64();
2052 TCGv_i64 t3 = tcg_temp_new_i64();
2053
2054 if (n == 0) {
2055 tcg_gen_mul_tl(temp, arg2, arg3);
2056 } else { /* n is expected to be 1 */
2057 tcg_gen_mul_tl(temp, arg2, arg3);
2058 tcg_gen_shli_tl(temp, temp, 1);
2059 /* catch special case r1 = r2 = 0x8000 */
2060 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2061 tcg_gen_sub_tl(temp, temp, temp2);
2062 }
2063 tcg_gen_ext_i32_i64(t2, temp);
2064 tcg_gen_shli_i64(t2, t2, 16);
2065 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2066 gen_sub64_d(t3, t1, t2);
2067 /* write back result */
2068 tcg_gen_extr_i64_i32(rl, rh, t3);
2069
2070 tcg_temp_free_i64(t1);
2071 tcg_temp_free_i64(t2);
2072 tcg_temp_free_i64(t3);
2073 tcg_temp_free(temp);
2074 tcg_temp_free(temp2);
2075 }
2076
2077 static inline void
2078 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2079 TCGv arg3, uint32_t n)
2080 {
2081 TCGv temp = tcg_temp_new();
2082 TCGv temp2 = tcg_temp_new();
2083 TCGv_i64 t1 = tcg_temp_new_i64();
2084 TCGv_i64 t2 = tcg_temp_new_i64();
2085
2086 if (n == 0) {
2087 tcg_gen_mul_tl(temp, arg2, arg3);
2088 } else { /* n is expected to be 1 */
2089 tcg_gen_mul_tl(temp, arg2, arg3);
2090 tcg_gen_shli_tl(temp, temp, 1);
2091 /* catch special case r1 = r2 = 0x8000 */
2092 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2093 tcg_gen_sub_tl(temp, temp, temp2);
2094 }
2095 tcg_gen_ext_i32_i64(t2, temp);
2096 tcg_gen_shli_i64(t2, t2, 16);
2097 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2098
2099 gen_helper_sub64_ssov(t1, cpu_env, t1, t2);
2100 tcg_gen_extr_i64_i32(rl, rh, t1);
2101
2102 tcg_temp_free(temp);
2103 tcg_temp_free(temp2);
2104 tcg_temp_free_i64(t1);
2105 tcg_temp_free_i64(t2);
2106 }
2107
2108 static inline void
2109 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2110 TCGv arg3, uint32_t n, CPUTriCoreState *env)
2111 {
2112 TCGv_i64 t1 = tcg_temp_new_i64();
2113 TCGv_i64 t2 = tcg_temp_new_i64();
2114 TCGv_i64 t3 = tcg_temp_new_i64();
2115 TCGv_i64 t4 = tcg_temp_new_i64();
2116 TCGv temp, temp2;
2117
2118 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2119 tcg_gen_ext_i32_i64(t2, arg2);
2120 tcg_gen_ext_i32_i64(t3, arg3);
2121
2122 tcg_gen_mul_i64(t2, t2, t3);
2123 if (n != 0) {
2124 tcg_gen_shli_i64(t2, t2, 1);
2125 }
2126 tcg_gen_sub_i64(t4, t1, t2);
2127 /* calc v bit */
2128 tcg_gen_xor_i64(t3, t4, t1);
2129 tcg_gen_xor_i64(t2, t1, t2);
2130 tcg_gen_and_i64(t3, t3, t2);
2131 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
2132 /* We produce an overflow on the host if the mul before was
2133 (0x80000000 * 0x80000000) << 1). If this is the
2134 case, we negate the ovf. */
2135 if (n == 1) {
2136 temp = tcg_temp_new();
2137 temp2 = tcg_temp_new();
2138 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
2139 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
2140 tcg_gen_and_tl(temp, temp, temp2);
2141 tcg_gen_shli_tl(temp, temp, 31);
2142 /* negate v bit, if special condition */
2143 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
2144
2145 tcg_temp_free(temp);
2146 tcg_temp_free(temp2);
2147 }
2148 /* write back result */
2149 tcg_gen_extr_i64_i32(rl, rh, t4);
2150 /* Calc SV bit */
2151 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2152 /* Calc AV/SAV bits */
2153 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2154 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2155 /* calc SAV */
2156 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2157
2158 tcg_temp_free_i64(t1);
2159 tcg_temp_free_i64(t2);
2160 tcg_temp_free_i64(t3);
2161 tcg_temp_free_i64(t4);
2162 }
2163
2164 static inline void
2165 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
2166 uint32_t up_shift)
2167 {
2168 TCGv_i64 t1 = tcg_temp_new_i64();
2169 TCGv_i64 t2 = tcg_temp_new_i64();
2170 TCGv_i64 t3 = tcg_temp_new_i64();
2171 TCGv_i64 t4 = tcg_temp_new_i64();
2172
2173 tcg_gen_ext_i32_i64(t1, arg1);
2174 tcg_gen_ext_i32_i64(t2, arg2);
2175 tcg_gen_ext_i32_i64(t3, arg3);
2176
2177 tcg_gen_mul_i64(t2, t2, t3);
2178 /* if we shift part of the fraction out, we need to round up */
2179 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
2180 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
2181 tcg_gen_sari_i64(t3, t2, up_shift - n);
2182 tcg_gen_add_i64(t3, t3, t4);
2183
2184 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3);
2185
2186 tcg_temp_free_i64(t1);
2187 tcg_temp_free_i64(t2);
2188 tcg_temp_free_i64(t3);
2189 tcg_temp_free_i64(t4);
2190 }
2191
2192 static inline void
2193 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2194 TCGv arg3, uint32_t n)
2195 {
2196 TCGv_i64 r1 = tcg_temp_new_i64();
2197 TCGv temp = tcg_const_i32(n);
2198
2199 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
2200 gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
2201 tcg_gen_extr_i64_i32(rl, rh, r1);
2202
2203 tcg_temp_free_i64(r1);
2204 tcg_temp_free(temp);
2205 }
2206
2207 static inline void
2208 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2209 TCGv r3, uint32_t n, uint32_t mode)
2210 {
2211 TCGv temp = tcg_const_i32(n);
2212 TCGv temp2 = tcg_temp_new();
2213 TCGv_i64 temp64 = tcg_temp_new_i64();
2214 switch (mode) {
2215 case MODE_LL:
2216 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2217 break;
2218 case MODE_LU:
2219 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2220 break;
2221 case MODE_UL:
2222 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2223 break;
2224 case MODE_UU:
2225 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2226 break;
2227 }
2228 tcg_gen_extr_i64_i32(temp, temp2, temp64);
2229 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
2230 tcg_gen_add_tl, tcg_gen_sub_tl);
2231 tcg_temp_free(temp);
2232 tcg_temp_free(temp2);
2233 tcg_temp_free_i64(temp64);
2234 }
2235
2236 static inline void
2237 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2238 TCGv r3, uint32_t n, uint32_t mode)
2239 {
2240 TCGv temp = tcg_const_i32(n);
2241 TCGv_i64 temp64 = tcg_temp_new_i64();
2242 TCGv_i64 temp64_2 = tcg_temp_new_i64();
2243 TCGv_i64 temp64_3 = tcg_temp_new_i64();
2244 switch (mode) {
2245 case MODE_LL:
2246 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2247 break;
2248 case MODE_LU:
2249 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2250 break;
2251 case MODE_UL:
2252 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2253 break;
2254 case MODE_UU:
2255 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2256 break;
2257 }
2258 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
2259 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2260 tcg_gen_ext32s_i64(temp64, temp64); /* low */
2261 tcg_gen_sub_i64(temp64, temp64_2, temp64);
2262 tcg_gen_shli_i64(temp64, temp64, 16);
2263
2264 gen_sub64_d(temp64_2, temp64_3, temp64);
2265 /* write back result */
2266 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
2267
2268 tcg_temp_free(temp);
2269 tcg_temp_free_i64(temp64);
2270 tcg_temp_free_i64(temp64_2);
2271 tcg_temp_free_i64(temp64_3);
2272 }
2273
2274 static inline void
2275 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2276 {
2277 TCGv temp = tcg_const_i32(n);
2278 TCGv temp2 = tcg_temp_new();
2279 TCGv_i64 temp64 = tcg_temp_new_i64();
2280 switch (mode) {
2281 case MODE_LL:
2282 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2283 break;
2284 case MODE_LU:
2285 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2286 break;
2287 case MODE_UL:
2288 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2289 break;
2290 case MODE_UU:
2291 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2292 break;
2293 }
2294 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2295 tcg_gen_shli_tl(temp, r1, 16);
2296 gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2);
2297
2298 tcg_temp_free(temp);
2299 tcg_temp_free(temp2);
2300 tcg_temp_free_i64(temp64);
2301 }
2302
2303 static inline void
2304 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2305 TCGv r3, uint32_t n, uint32_t mode)
2306 {
2307 TCGv temp = tcg_const_i32(n);
2308 TCGv temp2 = tcg_temp_new();
2309 TCGv temp3 = tcg_temp_new();
2310 TCGv_i64 temp64 = tcg_temp_new_i64();
2311
2312 switch (mode) {
2313 case MODE_LL:
2314 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2315 break;
2316 case MODE_LU:
2317 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2318 break;
2319 case MODE_UL:
2320 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2321 break;
2322 case MODE_UU:
2323 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2324 break;
2325 }
2326 tcg_gen_extr_i64_i32(temp, temp2, temp64);
2327 gen_adds(ret_low, r1_low, temp);
2328 tcg_gen_mov_tl(temp, cpu_PSW_V);
2329 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
2330 gen_subs(ret_high, r1_high, temp2);
2331 /* combine v bits */
2332 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
2333 /* combine av bits */
2334 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
2335
2336 tcg_temp_free(temp);
2337 tcg_temp_free(temp2);
2338 tcg_temp_free(temp3);
2339 tcg_temp_free_i64(temp64);
2340 }
2341
2342 static inline void
2343 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2344 TCGv r3, uint32_t n, uint32_t mode)
2345 {
2346 TCGv temp = tcg_const_i32(n);
2347 TCGv_i64 temp64 = tcg_temp_new_i64();
2348 TCGv_i64 temp64_2 = tcg_temp_new_i64();
2349
2350 switch (mode) {
2351 case MODE_LL:
2352 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2353 break;
2354 case MODE_LU:
2355 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2356 break;
2357 case MODE_UL:
2358 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2359 break;
2360 case MODE_UU:
2361 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2362 break;
2363 }
2364 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2365 tcg_gen_ext32s_i64(temp64, temp64); /* low */
2366 tcg_gen_sub_i64(temp64, temp64_2, temp64);
2367 tcg_gen_shli_i64(temp64, temp64, 16);
2368 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
2369
2370 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
2371 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2372
2373 tcg_temp_free(temp);
2374 tcg_temp_free_i64(temp64);
2375 tcg_temp_free_i64(temp64_2);
2376 }
2377
2378 static inline void
2379 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2380 {
2381 TCGv temp = tcg_const_i32(n);
2382 TCGv temp2 = tcg_temp_new();
2383 TCGv_i64 temp64 = tcg_temp_new_i64();
2384 switch (mode) {
2385 case MODE_LL:
2386 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2387 break;
2388 case MODE_LU:
2389 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2390 break;
2391 case MODE_UL:
2392 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2393 break;
2394 case MODE_UU:
2395 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2396 break;
2397 }
2398 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2399 tcg_gen_shli_tl(temp, r1, 16);
2400 gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2);
2401
2402 tcg_temp_free(temp);
2403 tcg_temp_free(temp2);
2404 tcg_temp_free_i64(temp64);
2405 }
2406
2407 static inline void gen_abs(TCGv ret, TCGv r1)
2408 {
2409 TCGv temp = tcg_temp_new();
2410 TCGv t0 = tcg_const_i32(0);
2411
2412 tcg_gen_neg_tl(temp, r1);
2413 tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp);
2414 /* overflow can only happen, if r1 = 0x80000000 */
2415 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
2416 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2417 /* calc SV bit */
2418 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2419 /* Calc AV bit */
2420 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2421 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2422 /* calc SAV bit */
2423 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2424
2425 tcg_temp_free(temp);
2426 tcg_temp_free(t0);
2427 }
2428
2429 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
2430 {
2431 TCGv temp = tcg_temp_new_i32();
2432 TCGv result = tcg_temp_new_i32();
2433
2434 tcg_gen_sub_tl(result, r1, r2);
2435 tcg_gen_sub_tl(temp, r2, r1);
2436 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
2437
2438 /* calc V bit */
2439 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
2440 tcg_gen_xor_tl(temp, result, r2);
2441 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
2442 tcg_gen_xor_tl(temp, r1, r2);
2443 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
2444 /* calc SV bit */
2445 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2446 /* Calc AV bit */
2447 tcg_gen_add_tl(cpu_PSW_AV, result, result);
2448 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
2449 /* calc SAV bit */
2450 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2451 /* write back result */
2452 tcg_gen_mov_tl(ret, result);
2453
2454 tcg_temp_free(temp);
2455 tcg_temp_free(result);
2456 }
2457
2458 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
2459 {
2460 TCGv temp = tcg_const_i32(con);
2461 gen_absdif(ret, r1, temp);
2462 tcg_temp_free(temp);
2463 }
2464
2465 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
2466 {
2467 TCGv temp = tcg_const_i32(con);
2468 gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
2469 tcg_temp_free(temp);
2470 }
2471
2472 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
2473 {
2474 TCGv high = tcg_temp_new();
2475 TCGv low = tcg_temp_new();
2476
2477 tcg_gen_muls2_tl(low, high, r1, r2);
2478 tcg_gen_mov_tl(ret, low);
2479 /* calc V bit */
2480 tcg_gen_sari_tl(low, low, 31);
2481 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
2482 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2483 /* calc SV bit */
2484 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2485 /* Calc AV bit */
2486 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2487 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2488 /* calc SAV bit */
2489 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2490
2491 tcg_temp_free(high);
2492 tcg_temp_free(low);
2493 }
2494
2495 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
2496 {
2497 TCGv temp = tcg_const_i32(con);
2498 gen_mul_i32s(ret, r1, temp);
2499 tcg_temp_free(temp);
2500 }
2501
2502 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2503 {
2504 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
2505 /* clear V bit */
2506 tcg_gen_movi_tl(cpu_PSW_V, 0);
2507 /* calc SV bit */
2508 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2509 /* Calc AV bit */
2510 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2511 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2512 /* calc SAV bit */
2513 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2514 }
2515
2516 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
2517 int32_t con)
2518 {
2519 TCGv temp = tcg_const_i32(con);
2520 gen_mul_i64s(ret_low, ret_high, r1, temp);
2521 tcg_temp_free(temp);
2522 }
2523
2524 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2525 {
2526 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
2527 /* clear V bit */
2528 tcg_gen_movi_tl(cpu_PSW_V, 0);
2529 /* calc SV bit */
2530 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2531 /* Calc AV bit */
2532 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2533 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2534 /* calc SAV bit */
2535 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2536 }
2537
2538 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
2539 int32_t con)
2540 {
2541 TCGv temp = tcg_const_i32(con);
2542 gen_mul_i64u(ret_low, ret_high, r1, temp);
2543 tcg_temp_free(temp);
2544 }
2545
2546 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
2547 {
2548 TCGv temp = tcg_const_i32(con);
2549 gen_helper_mul_ssov(ret, cpu_env, r1, temp);
2550 tcg_temp_free(temp);
2551 }
2552
2553 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
2554 {
2555 TCGv temp = tcg_const_i32(con);
2556 gen_helper_mul_suov(ret, cpu_env, r1, temp);
2557 tcg_temp_free(temp);
2558 }
2559 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
2560 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2561 {
2562 TCGv temp = tcg_const_i32(con);
2563 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
2564 tcg_temp_free(temp);
2565 }
2566
2567 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2568 {
2569 TCGv temp = tcg_const_i32(con);
2570 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
2571 tcg_temp_free(temp);
2572 }
2573
2574 static void
2575 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
2576 {
2577 TCGv temp = tcg_temp_new();
2578 TCGv_i64 temp_64 = tcg_temp_new_i64();
2579 TCGv_i64 temp2_64 = tcg_temp_new_i64();
2580
2581 if (n == 0) {
2582 if (up_shift == 32) {
2583 tcg_gen_muls2_tl(rh, rl, arg1, arg2);
2584 } else if (up_shift == 16) {
2585 tcg_gen_ext_i32_i64(temp_64, arg1);
2586 tcg_gen_ext_i32_i64(temp2_64, arg2);
2587
2588 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2589 tcg_gen_shri_i64(temp_64, temp_64, up_shift);
2590 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2591 } else {
2592 tcg_gen_muls2_tl(rl, rh, arg1, arg2);
2593 }
2594 /* reset v bit */
2595 tcg_gen_movi_tl(cpu_PSW_V, 0);
2596 } else { /* n is expected to be 1 */
2597 tcg_gen_ext_i32_i64(temp_64, arg1);
2598 tcg_gen_ext_i32_i64(temp2_64, arg2);
2599
2600 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2601
2602 if (up_shift == 0) {
2603 tcg_gen_shli_i64(temp_64, temp_64, 1);
2604 } else {
2605 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1);
2606 }
2607 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2608 /* overflow only occurs if r1 = r2 = 0x8000 */
2609 if (up_shift == 0) {/* result is 64 bit */
2610 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,
2611 0x80000000);
2612 } else { /* result is 32 bit */
2613 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl,
2614 0x80000000);
2615 }
2616 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2617 /* calc sv overflow bit */
2618 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2619 }
2620 /* calc av overflow bit */
2621 if (up_shift == 0) {
2622 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2623 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2624 } else {
2625 tcg_gen_add_tl(cpu_PSW_AV, rl, rl);
2626 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV);
2627 }
2628 /* calc sav overflow bit */
2629 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2630 tcg_temp_free(temp);
2631 tcg_temp_free_i64(temp_64);
2632 tcg_temp_free_i64(temp2_64);
2633 }
2634
2635 static void
2636 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2637 {
2638 TCGv temp = tcg_temp_new();
2639 if (n == 0) {
2640 tcg_gen_mul_tl(ret, arg1, arg2);
2641 } else { /* n is expected to be 1 */
2642 tcg_gen_mul_tl(ret, arg1, arg2);
2643 tcg_gen_shli_tl(ret, ret, 1);
2644 /* catch special case r1 = r2 = 0x8000 */
2645 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000);
2646 tcg_gen_sub_tl(ret, ret, temp);
2647 }
2648 /* reset v bit */
2649 tcg_gen_movi_tl(cpu_PSW_V, 0);
2650 /* calc av overflow bit */
2651 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2652 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2653 /* calc sav overflow bit */
2654 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2655
2656 tcg_temp_free(temp);
2657 }
2658
2659 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2660 {
2661 TCGv temp = tcg_temp_new();
2662 if (n == 0) {
2663 tcg_gen_mul_tl(ret, arg1, arg2);
2664 tcg_gen_addi_tl(ret, ret, 0x8000);
2665 } else {
2666 tcg_gen_mul_tl(ret, arg1, arg2);
2667 tcg_gen_shli_tl(ret, ret, 1);
2668 tcg_gen_addi_tl(ret, ret, 0x8000);
2669 /* catch special case r1 = r2 = 0x8000 */
2670 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000);
2671 tcg_gen_muli_tl(temp, temp, 0x8001);
2672 tcg_gen_sub_tl(ret, ret, temp);
2673 }
2674 /* reset v bit */
2675 tcg_gen_movi_tl(cpu_PSW_V, 0);
2676 /* calc av overflow bit */
2677 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2678 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2679 /* calc sav overflow bit */
2680 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2681 /* cut halfword off */
2682 tcg_gen_andi_tl(ret, ret, 0xffff0000);
2683
2684 tcg_temp_free(temp);
2685 }
2686
2687 static inline void
2688 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2689 TCGv r3)
2690 {
2691 TCGv_i64 temp64 = tcg_temp_new_i64();
2692 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2693 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3);
2694 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2695 tcg_temp_free_i64(temp64);
2696 }
2697
2698 static inline void
2699 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2700 int32_t con)
2701 {
2702 TCGv temp = tcg_const_i32(con);
2703 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2704 tcg_temp_free(temp);
2705 }
2706
2707 static inline void
2708 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2709 TCGv r3)
2710 {
2711 TCGv_i64 temp64 = tcg_temp_new_i64();
2712 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2713 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3);
2714 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2715 tcg_temp_free_i64(temp64);
2716 }
2717
2718 static inline void
2719 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2720 int32_t con)
2721 {
2722 TCGv temp = tcg_const_i32(con);
2723 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2724 tcg_temp_free(temp);
2725 }
2726
2727 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2728 {
2729 TCGv temp = tcg_const_i32(con);
2730 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
2731 tcg_temp_free(temp);
2732 }
2733
2734 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2735 {
2736 TCGv temp = tcg_const_i32(con);
2737 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
2738 tcg_temp_free(temp);
2739 }
2740
2741 static inline void
2742 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2743 TCGv r3)
2744 {
2745 TCGv_i64 temp64 = tcg_temp_new_i64();
2746 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2747 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3);
2748 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2749 tcg_temp_free_i64(temp64);
2750 }
2751
2752 static inline void
2753 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2754 int32_t con)
2755 {
2756 TCGv temp = tcg_const_i32(con);
2757 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2758 tcg_temp_free(temp);
2759 }
2760
2761 static inline void
2762 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2763 TCGv r3)
2764 {
2765 TCGv_i64 temp64 = tcg_temp_new_i64();
2766 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2767 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3);
2768 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2769 tcg_temp_free_i64(temp64);
2770 }
2771
2772 static inline void
2773 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2774 int32_t con)
2775 {
2776 TCGv temp = tcg_const_i32(con);
2777 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2778 tcg_temp_free(temp);
2779 }
2780
2781 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
2782 {
2783 TCGv sat_neg = tcg_const_i32(low);
2784 TCGv temp = tcg_const_i32(up);
2785
2786 /* sat_neg = (arg < low ) ? low : arg; */
2787 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
2788
2789 /* ret = (sat_neg > up ) ? up : sat_neg; */
2790 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
2791
2792 tcg_temp_free(sat_neg);
2793 tcg_temp_free(temp);
2794 }
2795
2796 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
2797 {
2798 TCGv temp = tcg_const_i32(up);
2799 /* sat_neg = (arg > up ) ? up : arg; */
2800 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
2801 tcg_temp_free(temp);
2802 }
2803
2804 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
2805 {
2806 if (shift_count == -32) {
2807 tcg_gen_movi_tl(ret, 0);
2808 } else if (shift_count >= 0) {
2809 tcg_gen_shli_tl(ret, r1, shift_count);
2810 } else {
2811 tcg_gen_shri_tl(ret, r1, -shift_count);
2812 }
2813 }
2814
2815 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
2816 {
2817 TCGv temp_low, temp_high;
2818
2819 if (shiftcount == -16) {
2820 tcg_gen_movi_tl(ret, 0);
2821 } else {
2822 temp_high = tcg_temp_new();
2823 temp_low = tcg_temp_new();
2824
2825 tcg_gen_andi_tl(temp_low, r1, 0xffff);
2826 tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
2827 gen_shi(temp_low, temp_low, shiftcount);
2828 gen_shi(ret, temp_high, shiftcount);
2829 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
2830
2831 tcg_temp_free(temp_low);
2832 tcg_temp_free(temp_high);
2833 }
2834 }
2835
2836 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
2837 {
2838 uint32_t msk, msk_start;
2839 TCGv temp = tcg_temp_new();
2840 TCGv temp2 = tcg_temp_new();
2841 TCGv t_0 = tcg_const_i32(0);
2842
2843 if (shift_count == 0) {
2844 /* Clear PSW.C and PSW.V */
2845 tcg_gen_movi_tl(cpu_PSW_C, 0);
2846 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
2847 tcg_gen_mov_tl(ret, r1);
2848 } else if (shift_count == -32) {
2849 /* set PSW.C */
2850 tcg_gen_mov_tl(cpu_PSW_C, r1);
2851 /* fill ret completly with sign bit */
2852 tcg_gen_sari_tl(ret, r1, 31);
2853 /* clear PSW.V */
2854 tcg_gen_movi_tl(cpu_PSW_V, 0);
2855 } else if (shift_count > 0) {
2856 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
2857 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
2858
2859 /* calc carry */
2860 msk_start = 32 - shift_count;
2861 msk = ((1 << shift_count) - 1) << msk_start;
2862 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2863 /* calc v/sv bits */
2864 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
2865 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
2866 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
2867 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2868 /* calc sv */
2869 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
2870 /* do shift */
2871 tcg_gen_shli_tl(ret, r1, shift_count);
2872
2873 tcg_temp_free(t_max);
2874 tcg_temp_free(t_min);
2875 } else {
2876 /* clear PSW.V */
2877 tcg_gen_movi_tl(cpu_PSW_V, 0);
2878 /* calc carry */
2879 msk = (1 << -shift_count) - 1;
2880 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2881 /* do shift */
2882 tcg_gen_sari_tl(ret, r1, -shift_count);
2883 }
2884 /* calc av overflow bit */
2885 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2886 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2887 /* calc sav overflow bit */
2888 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2889
2890 tcg_temp_free(temp);
2891 tcg_temp_free(temp2);
2892 tcg_temp_free(t_0);
2893 }
2894
2895 static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
2896 {
2897 gen_helper_sha_ssov(ret, cpu_env, r1, r2);
2898 }
2899
2900 static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
2901 {
2902 TCGv temp = tcg_const_i32(con);
2903 gen_shas(ret, r1, temp);
2904 tcg_temp_free(temp);
2905 }
2906
2907 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
2908 {
2909 TCGv low, high;
2910
2911 if (shift_count == 0) {
2912 tcg_gen_mov_tl(ret, r1);
2913 } else if (shift_count > 0) {
2914 low = tcg_temp_new();
2915 high = tcg_temp_new();
2916
2917 tcg_gen_andi_tl(high, r1, 0xffff0000);
2918 tcg_gen_shli_tl(low, r1, shift_count);
2919 tcg_gen_shli_tl(ret, high, shift_count);
2920 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2921
2922 tcg_temp_free(low);
2923 tcg_temp_free(high);
2924 } else {
2925 low = tcg_temp_new();
2926 high = tcg_temp_new();
2927
2928 tcg_gen_ext16s_tl(low, r1);
2929 tcg_gen_sari_tl(low, low, -shift_count);
2930 tcg_gen_sari_tl(ret, r1, -shift_count);
2931 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2932
2933 tcg_temp_free(low);
2934 tcg_temp_free(high);
2935 }
2936
2937 }
2938
2939 /* ret = {ret[30:0], (r1 cond r2)}; */
2940 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
2941 {
2942 TCGv temp = tcg_temp_new();
2943 TCGv temp2 = tcg_temp_new();
2944
2945 tcg_gen_shli_tl(temp, ret, 1);
2946 tcg_gen_setcond_tl(cond, temp2, r1, r2);
2947 tcg_gen_or_tl(ret, temp, temp2);
2948
2949 tcg_temp_free(temp);
2950 tcg_temp_free(temp2);
2951 }
2952
2953 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
2954 {
2955 TCGv temp = tcg_const_i32(con);
2956 gen_sh_cond(cond, ret, r1, temp);
2957 tcg_temp_free(temp);
2958 }
2959
2960 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
2961 {
2962 gen_helper_add_ssov(ret, cpu_env, r1, r2);
2963 }
2964
2965 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
2966 {
2967 TCGv temp = tcg_const_i32(con);
2968 gen_helper_add_ssov(ret, cpu_env, r1, temp);
2969 tcg_temp_free(temp);
2970 }
2971
2972 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
2973 {
2974 TCGv temp = tcg_const_i32(con);
2975 gen_helper_add_suov(ret, cpu_env, r1, temp);
2976 tcg_temp_free(temp);
2977 }
2978
2979 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
2980 {
2981 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
2982 }
2983
2984 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
2985 {
2986 gen_helper_sub_suov(ret, cpu_env, r1, r2);
2987 }
2988
2989 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
2990 int pos1, int pos2,
2991 void(*op1)(TCGv, TCGv, TCGv),
2992 void(*op2)(TCGv, TCGv, TCGv))
2993 {
2994 TCGv temp1, temp2;
2995
2996 temp1 = tcg_temp_new();
2997 temp2 = tcg_temp_new();
2998
2999 tcg_gen_shri_tl(temp2, r2, pos2);
3000 tcg_gen_shri_tl(temp1, r1, pos1);
3001
3002 (*op1)(temp1, temp1, temp2);
3003 (*op2)(temp1 , ret, temp1);
3004
3005 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
3006
3007 tcg_temp_free(temp1);
3008 tcg_temp_free(temp2);
3009 }
3010
3011 /* ret = r1[pos1] op1 r2[pos2]; */
3012 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
3013 int pos1, int pos2,
3014 void(*op1)(TCGv, TCGv, TCGv))
3015 {
3016 TCGv temp1, temp2;
3017
3018 temp1 = tcg_temp_new();
3019 temp2 = tcg_temp_new();
3020
3021 tcg_gen_shri_tl(temp2, r2, pos2);
3022 tcg_gen_shri_tl(temp1, r1, pos1);
3023
3024 (*op1)(ret, temp1, temp2);
3025
3026 tcg_gen_andi_tl(ret, ret, 0x1);
3027
3028 tcg_temp_free(temp1);
3029 tcg_temp_free(temp2);
3030 }
3031
3032 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
3033 void(*op)(TCGv, TCGv, TCGv))
3034 {
3035 TCGv temp = tcg_temp_new();
3036 TCGv temp2 = tcg_temp_new();
3037 /* temp = (arg1 cond arg2 )*/
3038 tcg_gen_setcond_tl(cond, temp, r1, r2);
3039 /* temp2 = ret[0]*/
3040 tcg_gen_andi_tl(temp2, ret, 0x1);
3041 /* temp = temp insn temp2 */
3042 (*op)(temp, temp, temp2);
3043 /* ret = {ret[31:1], temp} */
3044 tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
3045
3046 tcg_temp_free(temp);
3047 tcg_temp_free(temp2);
3048 }
3049
3050 static inline void
3051 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
3052 void(*op)(TCGv, TCGv, TCGv))
3053 {
3054 TCGv temp = tcg_const_i32(con);
3055 gen_accumulating_cond(cond, ret, r1, temp, op);
3056 tcg_temp_free(temp);
3057 }
3058
3059 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
3060 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2)
3061 {
3062 tcg_gen_setcond_tl(cond, ret, r1, r2);
3063 tcg_gen_neg_tl(ret, ret);
3064 }
3065
3066 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
3067 {
3068 TCGv b0 = tcg_temp_new();
3069 TCGv b1 = tcg_temp_new();
3070 TCGv b2 = tcg_temp_new();
3071 TCGv b3 = tcg_temp_new();
3072
3073 /* byte 0 */
3074 tcg_gen_andi_tl(b0, r1, 0xff);
3075 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
3076
3077 /* byte 1 */
3078 tcg_gen_andi_tl(b1, r1, 0xff00);
3079 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
3080
3081 /* byte 2 */
3082 tcg_gen_andi_tl(b2, r1, 0xff0000);
3083 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
3084
3085 /* byte 3 */
3086 tcg_gen_andi_tl(b3, r1, 0xff000000);
3087 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
3088
3089 /* combine them */
3090 tcg_gen_or_tl(ret, b0, b1);
3091 tcg_gen_or_tl(ret, ret, b2);
3092 tcg_gen_or_tl(ret, ret, b3);
3093
3094 tcg_temp_free(b0);
3095 tcg_temp_free(b1);
3096 tcg_temp_free(b2);
3097 tcg_temp_free(b3);
3098 }
3099
3100 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
3101 {
3102 TCGv h0 = tcg_temp_new();
3103 TCGv h1 = tcg_temp_new();
3104
3105 /* halfword 0 */
3106 tcg_gen_andi_tl(h0, r1, 0xffff);
3107 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
3108
3109 /* halfword 1 */
3110 tcg_gen_andi_tl(h1, r1, 0xffff0000);
3111 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
3112
3113 /* combine them */
3114 tcg_gen_or_tl(ret, h0, h1);
3115
3116 tcg_temp_free(h0);
3117 tcg_temp_free(h1);
3118 }
3119 /* mask = ((1 << width) -1) << pos;
3120 ret = (r1 & ~mask) | (r2 << pos) & mask); */
3121 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
3122 {
3123 TCGv mask = tcg_temp_new();
3124 TCGv temp = tcg_temp_new();
3125 TCGv temp2 = tcg_temp_new();
3126
3127 tcg_gen_movi_tl(mask, 1);
3128 tcg_gen_shl_tl(mask, mask, width);
3129 tcg_gen_subi_tl(mask, mask, 1);
3130 tcg_gen_shl_tl(mask, mask, pos);
3131
3132 tcg_gen_shl_tl(temp, r2, pos);
3133 tcg_gen_and_tl(temp, temp, mask);
3134 tcg_gen_andc_tl(temp2, r1, mask);
3135 tcg_gen_or_tl(ret, temp, temp2);
3136
3137 tcg_temp_free(mask);
3138 tcg_temp_free(temp);
3139 tcg_temp_free(temp2);
3140 }
3141
3142 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
3143 {
3144 TCGv_i64 temp = tcg_temp_new_i64();
3145
3146 gen_helper_bsplit(temp, r1);
3147 tcg_gen_extr_i64_i32(rl, rh, temp);
3148
3149 tcg_temp_free_i64(temp);
3150 }
3151
3152 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
3153 {
3154 TCGv_i64 temp = tcg_temp_new_i64();
3155
3156 gen_helper_unpack(temp, r1);
3157 tcg_gen_extr_i64_i32(rl, rh, temp);
3158
3159 tcg_temp_free_i64(temp);
3160 }
3161
3162 static inline void
3163 gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
3164 {
3165 TCGv_i64 ret = tcg_temp_new_i64();
3166
3167 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
3168 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
3169 } else {
3170 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
3171 }
3172 tcg_gen_extr_i64_i32(rl, rh, ret);
3173
3174 tcg_temp_free_i64(ret);
3175 }
3176
3177 static inline void
3178 gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
3179 {
3180 TCGv_i64 ret = tcg_temp_new_i64();
3181
3182 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
3183 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
3184 } else {
3185 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
3186 }
3187 tcg_gen_extr_i64_i32(rl, rh, ret);
3188
3189 tcg_temp_free_i64(ret);
3190 }
3191
3192 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
3193 {
3194 TCGv temp = tcg_temp_new();
3195 /* calc AV bit */
3196 tcg_gen_add_tl(temp, arg_low, arg_low);
3197 tcg_gen_xor_tl(temp, temp, arg_low);
3198 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high);
3199 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high);
3200 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
3201 /* calc SAV bit */
3202 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3203 tcg_gen_movi_tl(cpu_PSW_V, 0);
3204 tcg_temp_free(temp);
3205 }
3206
3207 static void gen_calc_usb_mulr_h(TCGv arg)
3208 {
3209 TCGv temp = tcg_temp_new();
3210 /* calc AV bit */
3211 tcg_gen_add_tl(temp, arg, arg);
3212 tcg_gen_xor_tl(temp, temp, arg);
3213 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16);
3214 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
3215 /* calc SAV bit */
3216 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3217 /* clear V bit */
3218 tcg_gen_movi_tl(cpu_PSW_V, 0);
3219 tcg_temp_free(temp);
3220 }
3221
3222 /* helpers for generating program flow micro-ops */
3223
3224 static inline void gen_save_pc(target_ulong pc)
3225 {
3226 tcg_gen_movi_tl(cpu_PC, pc);
3227 }
3228
3229 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3230 {
3231 TranslationBlock *tb;
3232 tb = ctx->tb;
3233 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3234 likely(!ctx->singlestep_enabled)) {
3235 tcg_gen_goto_tb(n);
3236 gen_save_pc(dest);
3237 tcg_gen_exit_tb((uintptr_t)tb + n);
3238 } else {
3239 gen_save_pc(dest);
3240 if (ctx->singlestep_enabled) {
3241 /* raise exception debug */
3242 }
3243 tcg_gen_exit_tb(0);
3244 }
3245 }
3246
3247 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
3248 TCGv r2, int16_t address)
3249 {
3250 TCGLabel *jumpLabel = gen_new_label();
3251 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
3252
3253 gen_goto_tb(ctx, 1, ctx->next_pc);
3254
3255 gen_set_label(jumpLabel);
3256 gen_goto_tb(ctx, 0, ctx->pc + address * 2);
3257 }
3258
3259 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
3260 int r2, int16_t address)
3261 {
3262 TCGv temp = tcg_const_i32(r2);
3263 gen_branch_cond(ctx, cond, r1, temp, address);
3264 tcg_temp_free(temp);
3265 }
3266
3267 static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
3268 {
3269 TCGLabel *l1 = gen_new_label();
3270
3271 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
3272 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
3273 gen_goto_tb(ctx, 1, ctx->pc + offset);
3274 gen_set_label(l1);
3275 gen_goto_tb(ctx, 0, ctx->next_pc);
3276 }
3277
3278 static void gen_fcall_save_ctx(DisasContext *ctx)
3279 {
3280 TCGv temp = tcg_temp_new();
3281
3282 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4);
3283 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL);
3284 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3285 tcg_gen_mov_tl(cpu_gpr_a[10], temp);
3286
3287 tcg_temp_free(temp);
3288 }
3289
3290 static void gen_fret(DisasContext *ctx)
3291 {
3292 TCGv temp = tcg_temp_new();
3293
3294 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1);
3295 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL);
3296 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4);
3297 tcg_gen_mov_tl(cpu_PC, temp);
3298 tcg_gen_exit_tb(0);
3299 ctx->bstate = BS_BRANCH;
3300
3301 tcg_temp_free(temp);
3302 }
3303
3304 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
3305 int r2 , int32_t constant , int32_t offset)
3306 {
3307 TCGv temp, temp2;
3308 int n;
3309
3310 switch (opc) {
3311 /* SB-format jumps */
3312 case OPC1_16_SB_J:
3313 case OPC1_32_B_J:
3314 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3315 break;
3316 case OPC1_32_B_CALL:
3317 case OPC1_16_SB_CALL:
3318 gen_helper_1arg(call, ctx->next_pc);
3319 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3320 break;
3321 case OPC1_16_SB_JZ:
3322 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
3323 break;
3324 case OPC1_16_SB_JNZ:
3325 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
3326 break;
3327 /* SBC-format jumps */
3328 case OPC1_16_SBC_JEQ:
3329 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
3330 break;
3331 case OPC1_16_SBC_JNE:
3332 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
3333 break;
3334 /* SBRN-format jumps */
3335 case OPC1_16_SBRN_JZ_T:
3336 temp = tcg_temp_new();
3337 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
3338 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3339 tcg_temp_free(temp);
3340 break;
3341 case OPC1_16_SBRN_JNZ_T:
3342 temp = tcg_temp_new();
3343 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
3344 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3345 tcg_temp_free(temp);
3346 break;
3347 /* SBR-format jumps */
3348 case OPC1_16_SBR_JEQ:
3349 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
3350 offset);
3351 break;
3352 case OPC1_16_SBR_JNE:
3353 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
3354 offset);
3355 break;
3356 case OPC1_16_SBR_JNZ:
3357 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
3358 break;
3359 case OPC1_16_SBR_JNZ_A:
3360 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3361 break;
3362 case OPC1_16_SBR_JGEZ:
3363 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
3364 break;
3365 case OPC1_16_SBR_JGTZ:
3366 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
3367 break;
3368 case OPC1_16_SBR_JLEZ:
3369 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
3370 break;
3371 case OPC1_16_SBR_JLTZ:
3372 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
3373 break;
3374 case OPC1_16_SBR_JZ:
3375 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
3376 break;
3377 case OPC1_16_SBR_JZ_A:
3378 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3379 break;
3380 case OPC1_16_SBR_LOOP:
3381 gen_loop(ctx, r1, offset * 2 - 32);
3382 break;
3383 /* SR-format jumps */
3384 case OPC1_16_SR_JI:
3385 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
3386 tcg_gen_exit_tb(0);
3387 break;
3388 case OPC2_32_SYS_RET:
3389 case OPC2_16_SR_RET:
3390 gen_helper_ret(cpu_env);
3391 tcg_gen_exit_tb(0);
3392 break;
3393 /* B-format */
3394 case OPC1_32_B_CALLA:
3395 gen_helper_1arg(call, ctx->next_pc);
3396 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3397 break;
3398 case OPC1_32_B_FCALL:
3399 gen_fcall_save_ctx(ctx);
3400 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3401 break;
3402 case OPC1_32_B_FCALLA:
3403 gen_fcall_save_ctx(ctx);
3404 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3405 break;
3406 case OPC1_32_B_JLA:
3407 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3408 /* fall through */
3409 case OPC1_32_B_JA:
3410 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3411 break;
3412 case OPC1_32_B_JL:
3413 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3414 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3415 break;
3416 /* BOL format */
3417 case OPCM_32_BRC_EQ_NEQ:
3418 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
3419 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
3420 } else {
3421 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
3422 }
3423 break;
3424 case OPCM_32_BRC_GE:
3425 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
3426 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
3427 } else {
3428 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3429 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
3430 offset);
3431 }
3432 break;
3433 case OPCM_32_BRC_JLT:
3434 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
3435 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
3436 } else {
3437 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3438 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
3439 offset);
3440 }
3441 break;
3442 case OPCM_32_BRC_JNE:
3443 temp = tcg_temp_new();
3444 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
3445 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3446 /* subi is unconditional */
3447 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3448 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3449 } else {
3450 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3451 /* addi is unconditional */
3452 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3453 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3454 }
3455 tcg_temp_free(temp);
3456 break;
3457 /* BRN format */
3458 case OPCM_32_BRN_JTT:
3459 n = MASK_OP_BRN_N(ctx->opcode);
3460
3461 temp = tcg_temp_new();
3462 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
3463
3464 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
3465 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3466 } else {
3467 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3468 }
3469 tcg_temp_free(temp);
3470 break;
3471 /* BRR Format */
3472 case OPCM_32_BRR_EQ_NEQ:
3473 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
3474 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
3475 offset);
3476 } else {
3477 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3478 offset);
3479 }
3480 break;
3481 case OPCM_32_BRR_ADDR_EQ_NEQ:
3482 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
3483 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
3484 offset);
3485 } else {
3486 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
3487 offset);
3488 }
3489 break;
3490 case OPCM_32_BRR_GE:
3491 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
3492 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3493 offset);
3494 } else {
3495 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3496 offset);
3497 }
3498 break;
3499 case OPCM_32_BRR_JLT:
3500 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
3501 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
3502 offset);
3503 } else {
3504 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3505 offset);
3506 }
3507 break;
3508 case OPCM_32_BRR_LOOP:
3509 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
3510 gen_loop(ctx, r2, offset * 2);
3511 } else {
3512 /* OPC2_32_BRR_LOOPU */
3513 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3514 }
3515 break;
3516 case OPCM_32_BRR_JNE:
3517 temp = tcg_temp_new();
3518 temp2 = tcg_temp_new();
3519 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
3520 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3521 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3522 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3523 /* subi is unconditional */
3524 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3525 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3526 } else {
3527 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3528 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3529 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3530 /* addi is unconditional */
3531 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3532 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3533 }
3534 tcg_temp_free(temp);
3535 tcg_temp_free(temp2);
3536 break;
3537 case OPCM_32_BRR_JNZ:
3538 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
3539 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3540 } else {
3541 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3542 }
3543 break;
3544 default:
3545 printf("Branch Error at %x\n", ctx->pc);
3546 }
3547 ctx->bstate = BS_BRANCH;
3548 }
3549
3550
3551 /*
3552 * Functions for decoding instructions
3553 */
3554
3555 static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1)
3556 {
3557 int r1;
3558 int32_t const4;
3559 TCGv temp, temp2;
3560
3561 r1 = MASK_OP_SRC_S1D(ctx->opcode);
3562 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
3563
3564 switch (op1) {
3565 case OPC1_16_SRC_ADD:
3566 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3567 break;
3568 case OPC1_16_SRC_ADD_A15:
3569 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
3570 break;
3571 case OPC1_16_SRC_ADD_15A:
3572 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
3573 break;
3574 case OPC1_16_SRC_ADD_A:
3575 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
3576 break;
3577 case OPC1_16_SRC_CADD:
3578 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3579 cpu_gpr_d[15]);
3580 break;
3581 case OPC1_16_SRC_CADDN:
3582 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3583 cpu_gpr_d[15]);
3584 break;
3585 case OPC1_16_SRC_CMOV:
3586 temp = tcg_const_tl(0);
3587 temp2 = tcg_const_tl(const4);
3588 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3589 temp2, cpu_gpr_d[r1]);
3590 tcg_temp_free(temp);
3591 tcg_temp_free(temp2);
3592 break;
3593 case OPC1_16_SRC_CMOVN:
3594 temp = tcg_const_tl(0);
3595 temp2 = tcg_const_tl(const4);
3596 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3597 temp2, cpu_gpr_d[r1]);
3598 tcg_temp_free(temp);
3599 tcg_temp_free(temp2);
3600 break;
3601 case OPC1_16_SRC_EQ:
3602 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3603 const4);
3604 break;
3605 case OPC1_16_SRC_LT:
3606 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3607 const4);
3608 break;
3609 case OPC1_16_SRC_MOV:
3610 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3611 break;
3612 case OPC1_16_SRC_MOV_A:
3613 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
3614 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
3615 break;
3616 case OPC1_16_SRC_MOV_E:
3617 if (tricore_feature(env, TRICORE_FEATURE_16)) {
3618 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3619 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
3620 } /* TODO: else raise illegal opcode trap */
3621 break;
3622 case OPC1_16_SRC_SH:
3623 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3624 break;
3625 case OPC1_16_SRC_SHA:
3626 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3627 break;
3628 }
3629 }
3630
3631 static void decode_srr_opc(DisasContext *ctx, int op1)
3632 {
3633 int r1, r2;
3634 TCGv temp;
3635
3636 r1 = MASK_OP_SRR_S1D(ctx->opcode);
3637 r2 = MASK_OP_SRR_S2(ctx->opcode);
3638
3639 switch (op1) {
3640 case OPC1_16_SRR_ADD:
3641 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3642 break;
3643 case OPC1_16_SRR_ADD_A15:
3644 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3645 break;
3646 case OPC1_16_SRR_ADD_15A:
3647 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3648 break;
3649 case OPC1_16_SRR_ADD_A:
3650 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
3651 break;
3652 case OPC1_16_SRR_ADDS:
3653 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3654 break;
3655 case OPC1_16_SRR_AND:
3656 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3657 break;
3658 case OPC1_16_SRR_CMOV:
3659 temp = tcg_const_tl(0);
3660 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3661 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3662 tcg_temp_free(temp);
3663 break;
3664 case OPC1_16_SRR_CMOVN:
3665 temp = tcg_const_tl(0);
3666 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3667 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3668 tcg_temp_free(temp);
3669 break;
3670 case OPC1_16_SRR_EQ:
3671 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3672 cpu_gpr_d[r2]);
3673 break;
3674 case OPC1_16_SRR_LT:
3675 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3676 cpu_gpr_d[r2]);
3677 break;
3678 case OPC1_16_SRR_MOV:
3679 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
3680 break;
3681 case OPC1_16_SRR_MOV_A:
3682 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
3683 break;
3684 case OPC1_16_SRR_MOV_AA:
3685 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
3686 break;
3687 case OPC1_16_SRR_MOV_D:
3688 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
3689 break;
3690 case OPC1_16_SRR_MUL:
3691 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3692 break;
3693 case OPC1_16_SRR_OR:
3694 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3695 break;
3696 case OPC1_16_SRR_SUB:
3697 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3698 break;
3699 case OPC1_16_SRR_SUB_A15B:
3700 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3701 break;
3702 case OPC1_16_SRR_SUB_15AB:
3703 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3704 break;
3705 case OPC1_16_SRR_SUBS:
3706 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3707 break;
3708 case OPC1_16_SRR_XOR:
3709 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3710 break;
3711 }
3712 }
3713
3714 static void decode_ssr_opc(DisasContext *ctx, int op1)
3715 {
3716 int r1, r2;
3717
3718 r1 = MASK_OP_SSR_S1(ctx->opcode);
3719 r2 = MASK_OP_SSR_S2(ctx->opcode);
3720
3721 switch (op1) {
3722 case OPC1_16_SSR_ST_A:
3723 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3724 break;
3725 case OPC1_16_SSR_ST_A_POSTINC:
3726 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3727 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3728 break;
3729 case OPC1_16_SSR_ST_B:
3730 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3731 break;
3732 case OPC1_16_SSR_ST_B_POSTINC:
3733 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3734 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3735 break;
3736 case OPC1_16_SSR_ST_H:
3737 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3738 break;
3739 case OPC1_16_SSR_ST_H_POSTINC:
3740 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3741 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3742 break;
3743 case OPC1_16_SSR_ST_W:
3744 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3745 break;
3746 case OPC1_16_SSR_ST_W_POSTINC:
3747 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3748 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3749 break;
3750 }
3751 }
3752
3753 static void decode_sc_opc(DisasContext *ctx, int op1)
3754 {
3755 int32_t const16;
3756
3757 const16 = MASK_OP_SC_CONST8(ctx->opcode);
3758
3759 switch (op1) {
3760 case OPC1_16_SC_AND:
3761 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3762 break;
3763 case OPC1_16_SC_BISR:
3764 gen_helper_1arg(bisr, const16 & 0xff);
3765 break;
3766 case OPC1_16_SC_LD_A:
3767 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3768 break;
3769 case OPC1_16_SC_LD_W:
3770 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3771 break;
3772 case OPC1_16_SC_MOV:
3773 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
3774 break;
3775 case OPC1_16_SC_OR:
3776 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3777 break;
3778 case OPC1_16_SC_ST_A:
3779 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3780 break;
3781 case OPC1_16_SC_ST_W:
3782 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3783 break;
3784 case OPC1_16_SC_SUB_A:
3785 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
3786 break;
3787 }
3788 }
3789
3790 static void decode_slr_opc(DisasContext *ctx, int op1)
3791 {
3792 int r1, r2;
3793
3794 r1 = MASK_OP_SLR_D(ctx->opcode);
3795 r2 = MASK_OP_SLR_S2(ctx->opcode);
3796
3797 switch (op1) {
3798 /* SLR-format */
3799 case OPC1_16_SLR_LD_A:
3800 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3801 break;
3802 case OPC1_16_SLR_LD_A_POSTINC:
3803 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3804 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3805 break;
3806 case OPC1_16_SLR_LD_BU:
3807 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3808 break;
3809 case OPC1_16_SLR_LD_BU_POSTINC:
3810 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3811 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3812 break;
3813 case OPC1_16_SLR_LD_H:
3814 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3815 break;
3816 case OPC1_16_SLR_LD_H_POSTINC:
3817 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3818 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3819 break;
3820 case OPC1_16_SLR_LD_W:
3821 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3822 break;
3823 case OPC1_16_SLR_LD_W_POSTINC:
3824 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3825 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3826 break;
3827 }
3828 }
3829
3830 static void decode_sro_opc(DisasContext *ctx, int op1)
3831 {
3832 int r2;
3833 int32_t address;
3834
3835 r2 = MASK_OP_SRO_S2(ctx->opcode);
3836 address = MASK_OP_SRO_OFF4(ctx->opcode);
3837
3838 /* SRO-format */
3839 switch (op1) {
3840 case OPC1_16_SRO_LD_A:
3841 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3842 break;
3843 case OPC1_16_SRO_LD_BU:
3844 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3845 break;
3846 case OPC1_16_SRO_LD_H:
3847 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
3848 break;
3849 case OPC1_16_SRO_LD_W:
3850 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3851 break;
3852 case OPC1_16_SRO_ST_A:
3853 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3854 break;
3855 case OPC1_16_SRO_ST_B:
3856 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3857 break;
3858 case OPC1_16_SRO_ST_H:
3859 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
3860 break;
3861 case OPC1_16_SRO_ST_W:
3862 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3863 break;
3864 }
3865 }
3866
3867 static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx)
3868 {
3869 uint32_t op2;
3870 op2 = MASK_OP_SR_OP2(ctx->opcode);
3871
3872 switch (op2) {
3873 case OPC2_16_SR_NOP:
3874 break;
3875 case OPC2_16_SR_RET:
3876 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
3877 break;
3878 case OPC2_16_SR_RFE:
3879 gen_helper_rfe(cpu_env);
3880 tcg_gen_exit_tb(0);
3881 ctx->bstate = BS_BRANCH;
3882 break;
3883 case OPC2_16_SR_DEBUG:
3884 /* raise EXCP_DEBUG */
3885 break;
3886 case OPC2_16_SR_FRET:
3887 gen_fret(ctx);
3888 }
3889 }
3890
3891 static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx)
3892 {
3893 uint32_t op2;
3894 uint32_t r1;
3895 TCGv temp;
3896
3897 r1 = MASK_OP_SR_S1D(ctx->opcode);
3898 op2 = MASK_OP_SR_OP2(ctx->opcode);
3899
3900 switch (op2) {
3901 case OPC2_16_SR_RSUB:
3902 /* overflow only if r1 = -0x80000000 */
3903 temp = tcg_const_i32(-0x80000000);
3904 /* calc V bit */
3905 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
3906 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
3907 /* calc SV bit */
3908 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
3909 /* sub */
3910 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3911 /* calc av */
3912 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
3913 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
3914 /* calc sav */
3915 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3916 tcg_temp_free(temp);
3917 break;
3918 case OPC2_16_SR_SAT_B:
3919 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
3920 break;
3921 case OPC2_16_SR_SAT_BU:
3922 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
3923 break;
3924 case OPC2_16_SR_SAT_H:
3925 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
3926 break;
3927 case OPC2_16_SR_SAT_HU:
3928 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
3929 break;
3930 }
3931 }
3932
3933 static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
3934 {
3935 int op1;
3936 int r1, r2;
3937 int32_t const16;
3938 int32_t address;
3939 TCGv temp;
3940
3941 op1 = MASK_OP_MAJOR(ctx->opcode);
3942
3943 /* handle ADDSC.A opcode only being 6 bit long */
3944 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
3945 op1 = OPC1_16_SRRS_ADDSC_A;
3946 }
3947
3948 switch (op1) {
3949 case OPC1_16_SRC_ADD:
3950 case OPC1_16_SRC_ADD_A15:
3951 case OPC1_16_SRC_ADD_15A:
3952 case OPC1_16_SRC_ADD_A:
3953 case OPC1_16_SRC_CADD:
3954 case OPC1_16_SRC_CADDN:
3955 case OPC1_16_SRC_CMOV:
3956 case OPC1_16_SRC_CMOVN:
3957 case OPC1_16_SRC_EQ:
3958 case OPC1_16_SRC_LT:
3959 case OPC1_16_SRC_MOV:
3960 case OPC1_16_SRC_MOV_A:
3961 case OPC1_16_SRC_MOV_E:
3962 case OPC1_16_SRC_SH:
3963 case OPC1_16_SRC_SHA:
3964 decode_src_opc(env, ctx, op1);
3965 break;
3966 /* SRR-format */
3967 case OPC1_16_SRR_ADD:
3968 case OPC1_16_SRR_ADD_A15:
3969 case OPC1_16_SRR_ADD_15A:
3970 case OPC1_16_SRR_ADD_A:
3971 case OPC1_16_SRR_ADDS:
3972 case OPC1_16_SRR_AND:
3973 case OPC1_16_SRR_CMOV:
3974 case OPC1_16_SRR_CMOVN:
3975 case OPC1_16_SRR_EQ:
3976 case OPC1_16_SRR_LT:
3977 case OPC1_16_SRR_MOV:
3978 case OPC1_16_SRR_MOV_A:
3979 case OPC1_16_SRR_MOV_AA:
3980 case OPC1_16_SRR_MOV_D:
3981 case OPC1_16_SRR_MUL:
3982 case OPC1_16_SRR_OR:
3983 case OPC1_16_SRR_SUB:
3984 case OPC1_16_SRR_SUB_A15B:
3985 case OPC1_16_SRR_SUB_15AB:
3986 case OPC1_16_SRR_SUBS:
3987 case OPC1_16_SRR_XOR:
3988 decode_srr_opc(ctx, op1);
3989 break;
3990 /* SSR-format */
3991 case OPC1_16_SSR_ST_A:
3992 case OPC1_16_SSR_ST_A_POSTINC:
3993 case OPC1_16_SSR_ST_B:
3994 case OPC1_16_SSR_ST_B_POSTINC:
3995 case OPC1_16_SSR_ST_H:
3996 case OPC1_16_SSR_ST_H_POSTINC:
3997 case OPC1_16_SSR_ST_W:
3998 case OPC1_16_SSR_ST_W_POSTINC:
3999 decode_ssr_opc(ctx, op1);
4000 break;
4001 /* SRRS-format */
4002 case OPC1_16_SRRS_ADDSC_A:
4003 r2 = MASK_OP_SRRS_S2(ctx->opcode);
4004 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
4005 const16 = MASK_OP_SRRS_N(ctx->opcode);
4006 temp = tcg_temp_new();
4007 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
4008 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
4009 tcg_temp_free(temp);
4010 break;
4011 /* SLRO-format */
4012 case OPC1_16_SLRO_LD_A:
4013 r1 = MASK_OP_SLRO_D(ctx->opcode);
4014 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4015 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4016 break;
4017 case OPC1_16_SLRO_LD_BU:
4018 r1 = MASK_OP_SLRO_D(ctx->opcode);
4019 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4020 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
4021 break;
4022 case OPC1_16_SLRO_LD_H:
4023 r1 = MASK_OP_SLRO_D(ctx->opcode);
4024 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4025 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
4026 break;
4027 case OPC1_16_SLRO_LD_W:
4028 r1 = MASK_OP_SLRO_D(ctx->opcode);
4029 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4030 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4031 break;
4032 /* SB-format */
4033 case OPC1_16_SB_CALL:
4034 case OPC1_16_SB_J:
4035 case OPC1_16_SB_JNZ:
4036 case OPC1_16_SB_JZ:
4037 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
4038 gen_compute_branch(ctx, op1, 0, 0, 0, address);
4039 break;
4040 /* SBC-format */
4041 case OPC1_16_SBC_JEQ:
4042 case OPC1_16_SBC_JNE:
4043 address = MASK_OP_SBC_DISP4(ctx->opcode);
4044 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
4045 gen_compute_branch(ctx, op1, 0, 0, const16, address);
4046 break;
4047 /* SBRN-format */
4048 case OPC1_16_SBRN_JNZ_T:
4049 case OPC1_16_SBRN_JZ_T:
4050 address = MASK_OP_SBRN_DISP4(ctx->opcode);
4051 const16 = MASK_OP_SBRN_N(ctx->opcode);
4052 gen_compute_branch(ctx, op1, 0, 0, const16, address);
4053 break;
4054 /* SBR-format */
4055 case OPC1_16_SBR_JEQ:
4056 case OPC1_16_SBR_JGEZ:
4057 case OPC1_16_SBR_JGTZ:
4058 case OPC1_16_SBR_JLEZ:
4059 case OPC1_16_SBR_JLTZ:
4060 case OPC1_16_SBR_JNE:
4061 case OPC1_16_SBR_JNZ:
4062 case OPC1_16_SBR_JNZ_A:
4063 case OPC1_16_SBR_JZ:
4064 case OPC1_16_SBR_JZ_A:
4065 case OPC1_16_SBR_LOOP:
4066 r1 = MASK_OP_SBR_S2(ctx->opcode);
4067 address = MASK_OP_SBR_DISP4(ctx->opcode);
4068 gen_compute_branch(ctx, op1, r1, 0, 0, address);
4069 break;
4070 /* SC-format */
4071 case OPC1_16_SC_AND:
4072 case OPC1_16_SC_BISR:
4073 case OPC1_16_SC_LD_A:
4074 case OPC1_16_SC_LD_W:
4075 case OPC1_16_SC_MOV:
4076 case OPC1_16_SC_OR:
4077 case OPC1_16_SC_ST_A:
4078 case OPC1_16_SC_ST_W:
4079 case OPC1_16_SC_SUB_A:
4080 decode_sc_opc(ctx, op1);
4081 break;
4082 /* SLR-format */
4083 case OPC1_16_SLR_LD_A:
4084 case OPC1_16_SLR_LD_A_POSTINC:
4085 case OPC1_16_SLR_LD_BU:
4086 case OPC1_16_SLR_LD_BU_POSTINC:
4087 case OPC1_16_SLR_LD_H:
4088 case OPC1_16_SLR_LD_H_POSTINC:
4089 case OPC1_16_SLR_LD_W:
4090 case OPC1_16_SLR_LD_W_POSTINC:
4091 decode_slr_opc(ctx, op1);
4092 break;
4093 /* SRO-format */
4094 case OPC1_16_SRO_LD_A:
4095 case OPC1_16_SRO_LD_BU:
4096 case OPC1_16_SRO_LD_H:
4097 case OPC1_16_SRO_LD_W:
4098 case OPC1_16_SRO_ST_A:
4099 case OPC1_16_SRO_ST_B:
4100 case OPC1_16_SRO_ST_H:
4101 case OPC1_16_SRO_ST_W:
4102 decode_sro_opc(ctx, op1);
4103 break;
4104 /* SSRO-format */
4105 case OPC1_16_SSRO_ST_A:
4106 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4107 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4108 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4109 break;
4110 case OPC1_16_SSRO_ST_B:
4111 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4112 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4113 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
4114 break;
4115 case OPC1_16_SSRO_ST_H:
4116 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4117 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4118 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
4119 break;
4120 case OPC1_16_SSRO_ST_W:
4121 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4122 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4123 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4124 break;
4125 /* SR-format */
4126 case OPCM_16_SR_SYSTEM:
4127 decode_sr_system(env, ctx);
4128 break;
4129 case OPCM_16_SR_ACCU:
4130 decode_sr_accu(env, ctx);
4131 break;
4132 case OPC1_16_SR_JI:
4133 r1 = MASK_OP_SR_S1D(ctx->opcode);
4134 gen_compute_branch(ctx, op1, r1, 0, 0, 0);
4135 break;
4136 case OPC1_16_SR_NOT:
4137 r1 = MASK_OP_SR_S1D(ctx->opcode);
4138 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
4139 break;
4140 }
4141 }
4142
4143 /*
4144 * 32 bit instructions
4145 */
4146
4147 /* ABS-format */
4148 static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx)
4149 {
4150 int32_t op2;
4151 int32_t r1;
4152 uint32_t address;
4153 TCGv temp;
4154
4155 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4156 address = MASK_OP_ABS_OFF18(ctx->opcode);
4157 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4158
4159 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4160
4161 switch (op2) {
4162 case OPC2_32_ABS_LD_A:
4163 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
4164 break;
4165 case OPC2_32_ABS_LD_D:
4166 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4167 break;
4168 case OPC2_32_ABS_LD_DA:
4169 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4170 break;
4171 case OPC2_32_ABS_LD_W:
4172 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
4173 break;
4174 }
4175
4176 tcg_temp_free(temp);
4177 }
4178
4179 static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx)
4180 {
4181 int32_t op2;
4182 int32_t r1;
4183 uint32_t address;
4184 TCGv temp;
4185
4186 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4187 address = MASK_OP_ABS_OFF18(ctx->opcode);
4188 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4189
4190 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4191
4192 switch (op2) {
4193 case OPC2_32_ABS_LD_B:
4194 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
4195 break;
4196 case OPC2_32_ABS_LD_BU:
4197 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
4198 break;
4199 case OPC2_32_ABS_LD_H:
4200 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
4201 break;
4202 case OPC2_32_ABS_LD_HU:
4203 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
4204 break;
4205 }
4206
4207 tcg_temp_free(temp);
4208 }
4209
4210 static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx)
4211 {
4212 int32_t op2;
4213 int32_t r1;
4214 uint32_t address;
4215 TCGv temp;
4216
4217 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4218 address = MASK_OP_ABS_OFF18(ctx->opcode);
4219 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4220
4221 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4222
4223 switch (op2) {
4224 case OPC2_32_ABS_LDMST:
4225 gen_ldmst(ctx, r1, temp);
4226 break;
4227 case OPC2_32_ABS_SWAP_W:
4228 gen_swap(ctx, r1, temp);
4229 break;
4230 }
4231
4232 tcg_temp_free(temp);
4233 }
4234
4235 static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx)
4236 {
4237 uint32_t op2;
4238 int32_t off18;
4239
4240 off18 = MASK_OP_ABS_OFF18(ctx->opcode);
4241 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4242
4243 switch (op2) {
4244 case OPC2_32_ABS_LDLCX:
4245 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
4246 break;
4247 case OPC2_32_ABS_LDUCX:
4248 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
4249 break;
4250 case OPC2_32_ABS_STLCX:
4251 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
4252 break;
4253 case OPC2_32_ABS_STUCX:
4254 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
4255 break;
4256 }
4257 }
4258
4259 static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx)
4260 {
4261 int32_t op2;
4262 int32_t r1;
4263 uint32_t address;
4264 TCGv temp;
4265
4266 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4267 address = MASK_OP_ABS_OFF18(ctx->opcode);
4268 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4269
4270 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4271
4272 switch (op2) {
4273 case OPC2_32_ABS_ST_A:
4274 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
4275 break;
4276 case OPC2_32_ABS_ST_D:
4277 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4278 break;
4279 case OPC2_32_ABS_ST_DA:
4280 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4281 break;
4282 case OPC2_32_ABS_ST_W:
4283 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
4284 break;
4285
4286 }
4287 tcg_temp_free(temp);
4288 }
4289
4290 static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx)
4291 {
4292 int32_t op2;
4293 int32_t r1;
4294 uint32_t address;
4295 TCGv temp;
4296
4297 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4298 address = MASK_OP_ABS_OFF18(ctx->opcode);
4299 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4300
4301 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4302
4303 switch (op2) {
4304 case OPC2_32_ABS_ST_B:
4305 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
4306 break;
4307 case OPC2_32_ABS_ST_H:
4308 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
4309 break;
4310 }
4311 tcg_temp_free(temp);
4312 }
4313
4314 /* Bit-format */
4315
4316 static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx)
4317 {
4318 uint32_t op2;
4319 int r1, r2, r3;
4320 int pos1, pos2;
4321
4322 r1 = MASK_OP_BIT_S1(ctx->opcode);
4323 r2 = MASK_OP_BIT_S2(ctx->opcode);
4324 r3 = MASK_OP_BIT_D(ctx->opcode);
4325 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4326 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4327 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4328
4329
4330 switch (op2) {
4331 case OPC2_32_BIT_AND_AND_T:
4332 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4333 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
4334 break;
4335 case OPC2_32_BIT_AND_ANDN_T:
4336 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4337 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
4338 break;
4339 case OPC2_32_BIT_AND_NOR_T:
4340 if (TCG_TARGET_HAS_andc_i32) {
4341 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4342 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
4343 } else {
4344 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4345 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
4346 }
4347 break;
4348 case OPC2_32_BIT_AND_OR_T:
4349 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4350 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
4351 break;
4352 }
4353 }
4354
4355 static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx)
4356 {
4357 uint32_t op2;
4358 int r1, r2, r3;
4359 int pos1, pos2;
4360 r1 = MASK_OP_BIT_S1(ctx->opcode);
4361 r2 = MASK_OP_BIT_S2(ctx->opcode);
4362 r3 = MASK_OP_BIT_D(ctx->opcode);
4363 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4364 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4365 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4366
4367 switch (op2) {
4368 case OPC2_32_BIT_AND_T:
4369 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4370 pos1, pos2, &tcg_gen_and_tl);
4371 break;
4372 case OPC2_32_BIT_ANDN_T:
4373 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4374 pos1, pos2, &tcg_gen_andc_tl);
4375 break;
4376 case OPC2_32_BIT_NOR_T:
4377 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4378 pos1, pos2, &tcg_gen_nor_tl);
4379 break;
4380 case OPC2_32_BIT_OR_T:
4381 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4382 pos1, pos2, &tcg_gen_or_tl);
4383 break;
4384 }
4385 }
4386
4387 static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx)
4388 {
4389 uint32_t op2;
4390 int r1, r2, r3;
4391 int pos1, pos2;
4392 TCGv temp;
4393 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4394 r1 = MASK_OP_BIT_S1(ctx->opcode);
4395 r2 = MASK_OP_BIT_S2(ctx->opcode);
4396 r3 = MASK_OP_BIT_D(ctx->opcode);
4397 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4398 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4399
4400 temp = tcg_temp_new();
4401
4402 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
4403 if (op2 == OPC2_32_BIT_INSN_T) {
4404 tcg_gen_not_tl(temp, temp);
4405 }
4406 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
4407 tcg_temp_free(temp);
4408 }
4409
4410 static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx)
4411 {
4412 uint32_t op2;
4413
4414 int r1, r2, r3;
4415 int pos1, pos2;
4416
4417 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4418 r1 = MASK_OP_BIT_S1(ctx->opcode);
4419 r2 = MASK_OP_BIT_S2(ctx->opcode);
4420 r3 = MASK_OP_BIT_D(ctx->opcode);
4421 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4422 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4423
4424 switch (op2) {
4425 case OPC2_32_BIT_NAND_T:
4426 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4427 pos1, pos2, &tcg_gen_nand_tl);
4428 break;
4429 case OPC2_32_BIT_ORN_T:
4430 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4431 pos1, pos2, &tcg_gen_orc_tl);
4432 break;
4433 case OPC2_32_BIT_XNOR_T:
4434 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4435 pos1, pos2, &tcg_gen_eqv_tl);
4436 break;
4437 case OPC2_32_BIT_XOR_T:
4438 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4439 pos1, pos2, &tcg_gen_xor_tl);
4440 break;
4441 }
4442 }
4443
4444 static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx)
4445 {
4446 uint32_t op2;
4447
4448 int r1, r2, r3;
4449 int pos1, pos2;
4450
4451 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4452 r1 = MASK_OP_BIT_S1(ctx->opcode);
4453 r2 = MASK_OP_BIT_S2(ctx->opcode);
4454 r3 = MASK_OP_BIT_D(ctx->opcode);
4455 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4456 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4457
4458 switch (op2) {
4459 case OPC2_32_BIT_OR_AND_T:
4460 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4461 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
4462 break;
4463 case OPC2_32_BIT_OR_ANDN_T:
4464 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4465 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
4466 break;
4467 case OPC2_32_BIT_OR_NOR_T:
4468 if (TCG_TARGET_HAS_orc_i32) {
4469 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4470 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
4471 } else {
4472 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4473 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
4474 }
4475 break;
4476 case OPC2_32_BIT_OR_OR_T:
4477 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4478 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
4479 break;
4480 }
4481 }
4482
4483 static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx)
4484 {
4485 uint32_t op2;
4486 int r1, r2, r3;
4487 int pos1, pos2;
4488 TCGv temp;
4489
4490 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4491 r1 = MASK_OP_BIT_S1(ctx->opcode);
4492 r2 = MASK_OP_BIT_S2(ctx->opcode);
4493 r3 = MASK_OP_BIT_D(ctx->opcode);
4494 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4495 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4496
4497 temp = tcg_temp_new();
4498
4499 switch (op2) {
4500 case OPC2_32_BIT_SH_AND_T:
4501 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4502 pos1, pos2, &tcg_gen_and_tl);
4503 break;
4504 case OPC2_32_BIT_SH_ANDN_T:
4505 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4506 pos1, pos2, &tcg_gen_andc_tl);
4507 break;
4508 case OPC2_32_BIT_SH_NOR_T:
4509 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4510 pos1, pos2, &tcg_gen_nor_tl);
4511 break;
4512 case OPC2_32_BIT_SH_OR_T:
4513 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4514 pos1, pos2, &tcg_gen_or_tl);
4515 break;
4516 }
4517 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4518 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4519 tcg_temp_free(temp);
4520 }
4521
4522 static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx)
4523 {
4524 uint32_t op2;
4525 int r1, r2, r3;
4526 int pos1, pos2;
4527 TCGv temp;
4528
4529 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4530 r1 = MASK_OP_BIT_S1(ctx->opcode);
4531 r2 = MASK_OP_BIT_S2(ctx->opcode);
4532 r3 = MASK_OP_BIT_D(ctx->opcode);
4533 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4534 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4535
4536 temp = tcg_temp_new();
4537
4538 switch (op2) {
4539 case OPC2_32_BIT_SH_NAND_T:
4540 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
4541 pos1, pos2, &tcg_gen_nand_tl);
4542 break;
4543 case OPC2_32_BIT_SH_ORN_T:
4544 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4545 pos1, pos2, &tcg_gen_orc_tl);
4546 break;
4547 case OPC2_32_BIT_SH_XNOR_T:
4548 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4549 pos1, pos2, &tcg_gen_eqv_tl);
4550 break;
4551 case OPC2_32_BIT_SH_XOR_T:
4552 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4553 pos1, pos2, &tcg_gen_xor_tl);
4554 break;
4555 }
4556 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4557 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4558 tcg_temp_free(temp);
4559 }
4560
4561 /* BO-format */
4562
4563
4564 static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
4565 DisasContext *ctx)
4566 {
4567 uint32_t op2;
4568 uint32_t off10;
4569 int32_t r1, r2;
4570 TCGv temp;
4571
4572 r1 = MASK_OP_BO_S1D(ctx->opcode);
4573 r2 = MASK_OP_BO_S2(ctx->opcode);
4574 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4575 op2 = MASK_OP_BO_OP2(ctx->opcode);
4576
4577 switch (op2) {
4578 case OPC2_32_BO_CACHEA_WI_SHORTOFF:
4579 case OPC2_32_BO_CACHEA_W_SHORTOFF:
4580 case OPC2_32_BO_CACHEA_I_SHORTOFF:
4581 /* instruction to access the cache */
4582 break;
4583 case OPC2_32_BO_CACHEA_WI_POSTINC:
4584 case OPC2_32_BO_CACHEA_W_POSTINC:
4585 case OPC2_32_BO_CACHEA_I_POSTINC:
4586 /* instruction to access the cache, but we still need to handle
4587 the addressing mode */
4588 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4589 break;
4590 case OPC2_32_BO_CACHEA_WI_PREINC:
4591 case OPC2_32_BO_CACHEA_W_PREINC:
4592 case OPC2_32_BO_CACHEA_I_PREINC:
4593 /* instruction to access the cache, but we still need to handle
4594 the addressing mode */
4595 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4596 break;
4597 case OPC2_32_BO_CACHEI_WI_SHORTOFF:
4598 case OPC2_32_BO_CACHEI_W_SHORTOFF:
4599 /* TODO: Raise illegal opcode trap,
4600 if !tricore_feature(TRICORE_FEATURE_131) */
4601 break;
4602 case OPC2_32_BO_CACHEI_W_POSTINC:
4603 case OPC2_32_BO_CACHEI_WI_POSTINC:
4604 if (tricore_feature(env, TRICORE_FEATURE_131)) {
4605 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4606 } /* TODO: else raise illegal opcode trap */
4607 break;
4608 case OPC2_32_BO_CACHEI_W_PREINC:
4609 case OPC2_32_BO_CACHEI_WI_PREINC:
4610 if (tricore_feature(env, TRICORE_FEATURE_131)) {
4611 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4612 } /* TODO: else raise illegal opcode trap */
4613 break;
4614 case OPC2_32_BO_ST_A_SHORTOFF:
4615 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4616 break;
4617 case OPC2_32_BO_ST_A_POSTINC:
4618 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4619 MO_LESL);
4620 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4621 break;
4622 case OPC2_32_BO_ST_A_PREINC:
4623 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4624 break;
4625 case OPC2_32_BO_ST_B_SHORTOFF:
4626 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4627 break;
4628 case OPC2_32_BO_ST_B_POSTINC:
4629 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4630 MO_UB);
4631 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4632 break;
4633 case OPC2_32_BO_ST_B_PREINC:
4634 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4635 break;
4636 case OPC2_32_BO_ST_D_SHORTOFF:
4637 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4638 off10, ctx);
4639 break;
4640 case OPC2_32_BO_ST_D_POSTINC:
4641 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4642 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4643 break;
4644 case OPC2_32_BO_ST_D_PREINC:
4645 temp = tcg_temp_new();
4646 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4647 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4648 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4649 tcg_temp_free(temp);
4650 break;
4651 case OPC2_32_BO_ST_DA_SHORTOFF:
4652 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4653 off10, ctx);
4654 break;
4655 case OPC2_32_BO_ST_DA_POSTINC:
4656 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4657 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4658 break;
4659 case OPC2_32_BO_ST_DA_PREINC:
4660 temp = tcg_temp_new();
4661 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4662 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4663 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4664 tcg_temp_free(temp);
4665 break;
4666 case OPC2_32_BO_ST_H_SHORTOFF:
4667 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4668 break;
4669 case OPC2_32_BO_ST_H_POSTINC:
4670 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4671 MO_LEUW);
4672 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4673 break;
4674 case OPC2_32_BO_ST_H_PREINC:
4675 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4676 break;
4677 case OPC2_32_BO_ST_Q_SHORTOFF:
4678 temp = tcg_temp_new();
4679 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4680 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4681 tcg_temp_free(temp);
4682 break;
4683 case OPC2_32_BO_ST_Q_POSTINC:
4684 temp = tcg_temp_new();
4685 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4686 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
4687 MO_LEUW);
4688 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4689 tcg_temp_free(temp);
4690 break;
4691 case OPC2_32_BO_ST_Q_PREINC:
4692 temp = tcg_temp_new();
4693 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4694 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4695 tcg_temp_free(temp);
4696 break;
4697 case OPC2_32_BO_ST_W_SHORTOFF:
4698 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4699 break;
4700 case OPC2_32_BO_ST_W_POSTINC:
4701 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4702 MO_LEUL);
4703 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4704 break;
4705 case OPC2_32_BO_ST_W_PREINC:
4706 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4707 break;
4708 }
4709 }
4710
4711 static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env,
4712 DisasContext *ctx)
4713 {
4714 uint32_t op2;
4715 uint32_t off10;
4716 int32_t r1, r2;
4717 TCGv temp, temp2, temp3;
4718
4719 r1 = MASK_OP_BO_S1D(ctx->opcode);
4720 r2 = MASK_OP_BO_S2(ctx->opcode);
4721 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4722 op2 = MASK_OP_BO_OP2(ctx->opcode);
4723
4724 temp = tcg_temp_new();
4725 temp2 = tcg_temp_new();
4726 temp3 = tcg_const_i32(off10);
4727
4728 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4729 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4730
4731 switch (op2) {
4732 case OPC2_32_BO_CACHEA_WI_BR:
4733 case OPC2_32_BO_CACHEA_W_BR:
4734 case OPC2_32_BO_CACHEA_I_BR:
4735 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4736 break;
4737 case OPC2_32_BO_CACHEA_WI_CIRC:
4738 case OPC2_32_BO_CACHEA_W_CIRC:
4739 case OPC2_32_BO_CACHEA_I_CIRC:
4740 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4741 break;
4742 case OPC2_32_BO_ST_A_BR:
4743 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4744 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4745 break;
4746 case OPC2_32_BO_ST_A_CIRC:
4747 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4748 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4749 break;
4750 case OPC2_32_BO_ST_B_BR:
4751 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4752 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4753 break;
4754 case OPC2_32_BO_ST_B_CIRC:
4755 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4756 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4757 break;
4758 case OPC2_32_BO_ST_D_BR:
4759 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4760 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4761 break;
4762 case OPC2_32_BO_ST_D_CIRC:
4763 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4764 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4765 tcg_gen_addi_tl(temp, temp, 4);
4766 tcg_gen_rem_tl(temp, temp, temp2);
4767 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4768 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4769 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4770 break;
4771 case OPC2_32_BO_ST_DA_BR:
4772 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4773 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4774 break;
4775 case OPC2_32_BO_ST_DA_CIRC:
4776 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4777 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4778 tcg_gen_addi_tl(temp, temp, 4);
4779 tcg_gen_rem_tl(temp, temp, temp2);
4780 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4781 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4782 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4783 break;
4784 case OPC2_32_BO_ST_H_BR:
4785 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4786 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4787 break;
4788 case OPC2_32_BO_ST_H_CIRC:
4789 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4790 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4791 break;
4792 case OPC2_32_BO_ST_Q_BR:
4793 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4794 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4795 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4796 break;
4797 case OPC2_32_BO_ST_Q_CIRC:
4798 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4799 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4800 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4801 break;
4802 case OPC2_32_BO_ST_W_BR:
4803 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4804 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4805 break;
4806 case OPC2_32_BO_ST_W_CIRC:
4807 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4808 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4809 break;
4810 }
4811 tcg_temp_free(temp);
4812 tcg_temp_free(temp2);
4813 tcg_temp_free(temp3);
4814 }
4815
4816 static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env,
4817 DisasContext *ctx)
4818 {
4819 uint32_t op2;
4820 uint32_t off10;
4821 int32_t r1, r2;
4822 TCGv temp;
4823
4824 r1 = MASK_OP_BO_S1D(ctx->opcode);
4825 r2 = MASK_OP_BO_S2(ctx->opcode);
4826 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4827 op2 = MASK_OP_BO_OP2(ctx->opcode);
4828
4829 switch (op2) {
4830 case OPC2_32_BO_LD_A_SHORTOFF:
4831 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4832 break;
4833 case OPC2_32_BO_LD_A_POSTINC:
4834 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4835 MO_LEUL);
4836 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4837 break;
4838 case OPC2_32_BO_LD_A_PREINC:
4839 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4840 break;
4841 case OPC2_32_BO_LD_B_SHORTOFF:
4842 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4843 break;
4844 case OPC2_32_BO_LD_B_POSTINC:
4845 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4846 MO_SB);
4847 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4848 break;
4849 case OPC2_32_BO_LD_B_PREINC:
4850 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4851 break;
4852 case OPC2_32_BO_LD_BU_SHORTOFF:
4853 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4854 break;
4855 case OPC2_32_BO_LD_BU_POSTINC:
4856 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4857 MO_UB);
4858 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4859 break;
4860 case OPC2_32_BO_LD_BU_PREINC:
4861 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4862 break;
4863 case OPC2_32_BO_LD_D_SHORTOFF:
4864 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4865 off10, ctx);
4866 break;
4867 case OPC2_32_BO_LD_D_POSTINC:
4868 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4869 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4870 break;
4871 case OPC2_32_BO_LD_D_PREINC:
4872 temp = tcg_temp_new();
4873 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4874 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4875 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4876 tcg_temp_free(temp);
4877 break;
4878 case OPC2_32_BO_LD_DA_SHORTOFF:
4879 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4880 off10, ctx);
4881 break;
4882 case OPC2_32_BO_LD_DA_POSTINC:
4883 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4884 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4885 break;
4886 case OPC2_32_BO_LD_DA_PREINC:
4887 temp = tcg_temp_new();
4888 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4889 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4890 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4891 tcg_temp_free(temp);
4892 break;
4893 case OPC2_32_BO_LD_H_SHORTOFF:
4894 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4895 break;
4896 case OPC2_32_BO_LD_H_POSTINC:
4897 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4898 MO_LESW);
4899 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4900 break;
4901 case OPC2_32_BO_LD_H_PREINC:
4902 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4903 break;
4904 case OPC2_32_BO_LD_HU_SHORTOFF:
4905 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4906 break;
4907 case OPC2_32_BO_LD_HU_POSTINC:
4908 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4909 MO_LEUW);
4910 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4911 break;
4912 case OPC2_32_BO_LD_HU_PREINC:
4913 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4914 break;
4915 case OPC2_32_BO_LD_Q_SHORTOFF:
4916 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4917 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4918 break;
4919 case OPC2_32_BO_LD_Q_POSTINC:
4920 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4921 MO_LEUW);
4922 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4923 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4924 break;
4925 case OPC2_32_BO_LD_Q_PREINC:
4926 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4927 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4928 break;
4929 case OPC2_32_BO_LD_W_SHORTOFF:
4930 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4931 break;
4932 case OPC2_32_BO_LD_W_POSTINC:
4933 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4934 MO_LEUL);
4935 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4936 break;
4937 case OPC2_32_BO_LD_W_PREINC:
4938 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4939 break;
4940 }
4941 }
4942
4943 static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env,
4944 DisasContext *ctx)
4945 {
4946 uint32_t op2;
4947 uint32_t off10;
4948 int r1, r2;
4949
4950 TCGv temp, temp2, temp3;
4951
4952 r1 = MASK_OP_BO_S1D(ctx->opcode);
4953 r2 = MASK_OP_BO_S2(ctx->opcode);
4954 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4955 op2 = MASK_OP_BO_OP2(ctx->opcode);
4956
4957 temp = tcg_temp_new();
4958 temp2 = tcg_temp_new();
4959 temp3 = tcg_const_i32(off10);
4960
4961 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4962 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4963
4964
4965 switch (op2) {
4966 case OPC2_32_BO_LD_A_BR:
4967 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4968 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4969 break;
4970 case OPC2_32_BO_LD_A_CIRC:
4971 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4972 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4973 break;
4974 case OPC2_32_BO_LD_B_BR:
4975 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4976 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4977 break;
4978 case OPC2_32_BO_LD_B_CIRC:
4979 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4980 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4981 break;
4982 case OPC2_32_BO_LD_BU_BR:
4983 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4984 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4985 break;
4986 case OPC2_32_BO_LD_BU_CIRC:
4987 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4988 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4989 break;
4990 case OPC2_32_BO_LD_D_BR:
4991 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4992 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4993 break;
4994 case OPC2_32_BO_LD_D_CIRC:
4995 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4996 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4997 tcg_gen_addi_tl(temp, temp, 4);
4998 tcg_gen_rem_tl(temp, temp, temp2);
4999 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
5000 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
5001 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5002 break;
5003 case OPC2_32_BO_LD_DA_BR:
5004 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
5005 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5006 break;
5007 case OPC2_32_BO_LD_DA_CIRC:
5008 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
5009 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
5010 tcg_gen_addi_tl(temp, temp, 4);
5011 tcg_gen_rem_tl(temp, temp, temp2);
5012 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
5013 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
5014 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5015 break;
5016 case OPC2_32_BO_LD_H_BR:
5017 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
5018 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5019 break;
5020 case OPC2_32_BO_LD_H_CIRC:
5021 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
5022 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5023 break;
5024 case OPC2_32_BO_LD_HU_BR:
5025 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5026 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5027 break;
5028 case OPC2_32_BO_LD_HU_CIRC:
5029 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5030 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5031 break;
5032 case OPC2_32_BO_LD_Q_BR:
5033 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5034 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
5035 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5036 break;
5037 case OPC2_32_BO_LD_Q_CIRC:
5038 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5039 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
5040 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5041 break;
5042 case OPC2_32_BO_LD_W_BR:
5043 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
5044 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5045 break;
5046 case OPC2_32_BO_LD_W_CIRC:
5047 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
5048 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5049 break;
5050 }
5051 tcg_temp_free(temp);
5052 tcg_temp_free(temp2);
5053 tcg_temp_free(temp3);
5054 }
5055
5056 static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env,
5057 DisasContext *ctx)
5058 {
5059 uint32_t op2;
5060 uint32_t off10;
5061 int r1, r2;
5062
5063 TCGv temp, temp2;
5064
5065 r1 = MASK_OP_BO_S1D(ctx->opcode);
5066 r2 = MASK_OP_BO_S2(ctx->opcode);
5067 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
5068 op2 = MASK_OP_BO_OP2(ctx->opcode);
5069
5070
5071 temp = tcg_temp_new();
5072 temp2 = tcg_temp_new();
5073
5074 switch (op2) {
5075 case OPC2_32_BO_LDLCX_SHORTOFF:
5076 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5077 gen_helper_ldlcx(cpu_env, temp);
5078 break;
5079 case OPC2_32_BO_LDMST_SHORTOFF:
5080 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5081 gen_ldmst(ctx, r1, temp);
5082 break;
5083 case OPC2_32_BO_LDMST_POSTINC:
5084 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
5085 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5086 break;
5087 case OPC2_32_BO_LDMST_PREINC:
5088 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5089 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
5090 break;
5091 case OPC2_32_BO_LDUCX_SHORTOFF:
5092 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5093 gen_helper_lducx(cpu_env, temp);
5094 break;
5095 case OPC2_32_BO_LEA_SHORTOFF:
5096 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
5097 break;
5098 case OPC2_32_BO_STLCX_SHORTOFF:
5099 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5100 gen_helper_stlcx(cpu_env, temp);
5101 break;
5102 case OPC2_32_BO_STUCX_SHORTOFF:
5103 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5104 gen_helper_stucx(cpu_env, temp);
5105 break;
5106 case OPC2_32_BO_SWAP_W_SHORTOFF:
5107 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5108 gen_swap(ctx, r1, temp);
5109 break;
5110 case OPC2_32_BO_SWAP_W_POSTINC:
5111 gen_swap(ctx, r1, cpu_gpr_a[r2]);
5112 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5113 break;
5114 case OPC2_32_BO_SWAP_W_PREINC:
5115 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5116 gen_swap(ctx, r1, cpu_gpr_a[r2]);
5117 break;
5118 case OPC2_32_BO_CMPSWAP_W_SHORTOFF:
5119 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5120 gen_cmpswap(ctx, r1, temp);
5121 break;
5122 case OPC2_32_BO_CMPSWAP_W_POSTINC:
5123 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
5124 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5125 break;
5126 case OPC2_32_BO_CMPSWAP_W_PREINC:
5127 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5128 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
5129 break;
5130 case OPC2_32_BO_SWAPMSK_W_SHORTOFF:
5131 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5132 gen_swapmsk(ctx, r1, temp);
5133 break;
5134 case OPC2_32_BO_SWAPMSK_W_POSTINC:
5135 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
5136 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5137 break;
5138 case OPC2_32_BO_SWAPMSK_W_PREINC:
5139 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5140 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
5141 break;
5142 }
5143 tcg_temp_free(temp);
5144 tcg_temp_free(temp2);
5145 }
5146
5147 static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env,
5148 DisasContext *ctx)
5149 {
5150 uint32_t op2;
5151 uint32_t off10;
5152 int r1, r2;
5153
5154 TCGv temp, temp2, temp3;
5155
5156 r1 = MASK_OP_BO_S1D(ctx->opcode);
5157 r2 = MASK_OP_BO_S2(ctx->opcode);
5158 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
5159 op2 = MASK_OP_BO_OP2(ctx->opcode);
5160
5161 temp = tcg_temp_new();
5162 temp2 = tcg_temp_new();
5163 temp3 = tcg_const_i32(off10);
5164
5165 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
5166 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
5167
5168 switch (op2) {
5169 case OPC2_32_BO_LDMST_BR:
5170 gen_ldmst(ctx, r1, temp2);
5171 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5172 break;
5173 case OPC2_32_BO_LDMST_CIRC:
5174 gen_ldmst(ctx, r1, temp2);
5175 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5176 break;
5177 case OPC2_32_BO_SWAP_W_BR:
5178 gen_swap(ctx, r1, temp2);
5179 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5180 break;
5181 case OPC2_32_BO_SWAP_W_CIRC:
5182 gen_swap(ctx, r1, temp2);
5183 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5184 break;
5185 case OPC2_32_BO_CMPSWAP_W_BR:
5186 gen_cmpswap(ctx, r1, temp2);
5187 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5188 break;
5189 case OPC2_32_BO_CMPSWAP_W_CIRC:
5190 gen_cmpswap(ctx, r1, temp2);
5191 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5192 break;
5193 case OPC2_32_BO_SWAPMSK_W_BR:
5194 gen_swapmsk(ctx, r1, temp2);
5195 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5196 break;
5197 case OPC2_32_BO_SWAPMSK_W_CIRC:
5198 gen_swapmsk(ctx, r1, temp2);
5199 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5200 break;
5201 }
5202
5203 tcg_temp_free(temp);
5204 tcg_temp_free(temp2);
5205 tcg_temp_free(temp3);
5206 }
5207
5208 static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
5209 {
5210 int r1, r2;
5211 int32_t address;
5212 TCGv temp;
5213
5214 r1 = MASK_OP_BOL_S1D(ctx->opcode);
5215 r2 = MASK_OP_BOL_S2(ctx->opcode);
5216 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
5217
5218 switch (op1) {
5219 case OPC1_32_BOL_LD_A_LONGOFF:
5220 temp = tcg_temp_new();
5221 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
5222 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
5223 tcg_temp_free(temp);
5224 break;
5225 case OPC1_32_BOL_LD_W_LONGOFF:
5226 temp = tcg_temp_new();
5227 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
5228 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
5229 tcg_temp_free(temp);
5230 break;
5231 case OPC1_32_BOL_LEA_LONGOFF:
5232 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
5233 break;
5234 case OPC1_32_BOL_ST_A_LONGOFF:
5235 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5236 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
5237 } else {
5238 /* raise illegal opcode trap */
5239 }
5240 break;
5241 case OPC1_32_BOL_ST_W_LONGOFF:
5242 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
5243 break;
5244 case OPC1_32_BOL_LD_B_LONGOFF:
5245 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5246 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
5247 } else {
5248 /* raise illegal opcode trap */
5249 }
5250 break;
5251 case OPC1_32_BOL_LD_BU_LONGOFF:
5252 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5253 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
5254 } else {
5255 /* raise illegal opcode trap */
5256 }
5257 break;
5258 case OPC1_32_BOL_LD_H_LONGOFF:
5259 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5260 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
5261 } else {
5262 /* raise illegal opcode trap */
5263 }
5264 break;
5265 case OPC1_32_BOL_LD_HU_LONGOFF:
5266 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5267 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
5268 } else {
5269 /* raise illegal opcode trap */
5270 }
5271 break;
5272 case OPC1_32_BOL_ST_B_LONGOFF:
5273 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5274 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
5275 } else {
5276 /* raise illegal opcode trap */
5277 }
5278 break;
5279 case OPC1_32_BOL_ST_H_LONGOFF:
5280 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5281 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
5282 } else {
5283 /* raise illegal opcode trap */
5284 }
5285 break;
5286 }
5287 }
5288
5289 /* RC format */
5290 static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
5291 {
5292 uint32_t op2;
5293 int r1, r2;
5294 int32_t const9;
5295 TCGv temp;
5296
5297 r2 = MASK_OP_RC_D(ctx->opcode);
5298 r1 = MASK_OP_RC_S1(ctx->opcode);
5299 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5300 op2 = MASK_OP_RC_OP2(ctx->opcode);
5301
5302 temp = tcg_temp_new();
5303
5304 switch (op2) {
5305 case OPC2_32_RC_AND:
5306 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5307 break;
5308 case OPC2_32_RC_ANDN:
5309 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
5310 break;
5311 case OPC2_32_RC_NAND:
5312 tcg_gen_movi_tl(temp, const9);
5313 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
5314 break;
5315 case OPC2_32_RC_NOR:
5316 tcg_gen_movi_tl(temp, const9);
5317 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
5318 break;
5319 case OPC2_32_RC_OR:
5320 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5321 break;
5322 case OPC2_32_RC_ORN:
5323 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
5324 break;
5325 case OPC2_32_RC_SH:
5326 const9 = sextract32(const9, 0, 6);
5327 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5328 break;
5329 case OPC2_32_RC_SH_H:
5330 const9 = sextract32(const9, 0, 5);
5331 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5332 break;
5333 case OPC2_32_RC_SHA:
5334 const9 = sextract32(const9, 0, 6);
5335 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5336 break;
5337 case OPC2_32_RC_SHA_H:
5338 const9 = sextract32(const9, 0, 5);
5339 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5340 break;
5341 case OPC2_32_RC_SHAS:
5342 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5343 break;
5344 case OPC2_32_RC_XNOR:
5345 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5346 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]);
5347 break;
5348 case OPC2_32_RC_XOR:
5349 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5350 break;
5351 }
5352 tcg_temp_free(temp);
5353 }
5354
5355 static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx)
5356 {
5357 uint32_t op2;
5358 int r1, r2;
5359 int16_t const9;
5360
5361 TCGv temp;
5362
5363 r2 = MASK_OP_RC_D(ctx->opcode);
5364 r1 = MASK_OP_RC_S1(ctx->opcode);
5365 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5366
5367 op2 = MASK_OP_RC_OP2(ctx->opcode);
5368
5369 temp = tcg_temp_new();
5370
5371 switch (op2) {
5372 case OPC2_32_RC_ABSDIF:
5373 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5374 break;
5375 case OPC2_32_RC_ABSDIFS:
5376 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5377 break;
5378 case OPC2_32_RC_ADD:
5379 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5380 break;
5381 case OPC2_32_RC_ADDC:
5382 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5383 break;
5384 case OPC2_32_RC_ADDS:
5385 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5386 break;
5387 case OPC2_32_RC_ADDS_U:
5388 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5389 break;
5390 case OPC2_32_RC_ADDX:
5391 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5392 break;
5393 case OPC2_32_RC_AND_EQ:
5394 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5395 const9, &tcg_gen_and_tl);
5396 break;
5397 case OPC2_32_RC_AND_GE:
5398 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5399 const9, &tcg_gen_and_tl);
5400 break;
5401 case OPC2_32_RC_AND_GE_U:
5402 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5403 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5404 const9, &tcg_gen_and_tl);
5405 break;
5406 case OPC2_32_RC_AND_LT:
5407 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5408 const9, &tcg_gen_and_tl);
5409 break;
5410 case OPC2_32_RC_AND_LT_U:
5411 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5412 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5413 const9, &tcg_gen_and_tl);
5414 break;
5415 case OPC2_32_RC_AND_NE:
5416 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5417 const9, &tcg_gen_and_tl);
5418 break;
5419 case OPC2_32_RC_EQ:
5420 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5421 break;
5422 case OPC2_32_RC_EQANY_B:
5423 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5424 break;
5425 case OPC2_32_RC_EQANY_H:
5426 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5427 break;
5428 case OPC2_32_RC_GE:
5429 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5430 break;
5431 case OPC2_32_RC_GE_U:
5432 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5433 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5434 break;
5435 case OPC2_32_RC_LT:
5436 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5437 break;
5438 case OPC2_32_RC_LT_U:
5439 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5440 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5441 break;
5442 case OPC2_32_RC_MAX:
5443 tcg_gen_movi_tl(temp, const9);
5444 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5445 cpu_gpr_d[r1], temp);
5446 break;
5447 case OPC2_32_RC_MAX_U:
5448 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5449 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5450 cpu_gpr_d[r1], temp);
5451 break;
5452 case OPC2_32_RC_MIN:
5453 tcg_gen_movi_tl(temp, const9);
5454 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5455 cpu_gpr_d[r1], temp);
5456 break;
5457 case OPC2_32_RC_MIN_U:
5458 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5459 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5460 cpu_gpr_d[r1], temp);
5461 break;
5462 case OPC2_32_RC_NE:
5463 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5464 break;
5465 case OPC2_32_RC_OR_EQ:
5466 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5467 const9, &tcg_gen_or_tl);
5468 break;
5469 case OPC2_32_RC_OR_GE:
5470 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5471 const9, &tcg_gen_or_tl);
5472 break;
5473 case OPC2_32_RC_OR_GE_U:
5474 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5475 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5476 const9, &tcg_gen_or_tl);
5477 break;
5478 case OPC2_32_RC_OR_LT:
5479 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5480 const9, &tcg_gen_or_tl);
5481 break;
5482 case OPC2_32_RC_OR_LT_U:
5483 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5484 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5485 const9, &tcg_gen_or_tl);
5486 break;
5487 case OPC2_32_RC_OR_NE:
5488 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5489 const9, &tcg_gen_or_tl);
5490 break;
5491 case OPC2_32_RC_RSUB:
5492 tcg_gen_movi_tl(temp, const9);
5493 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5494 break;
5495 case OPC2_32_RC_RSUBS:
5496 tcg_gen_movi_tl(temp, const9);
5497 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5498 break;
5499 case OPC2_32_RC_RSUBS_U:
5500 tcg_gen_movi_tl(temp, const9);
5501 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5502 break;
5503 case OPC2_32_RC_SH_EQ:
5504 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5505 break;
5506 case OPC2_32_RC_SH_GE:
5507 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5508 break;
5509 case OPC2_32_RC_SH_GE_U:
5510 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5511 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5512 break;
5513 case OPC2_32_RC_SH_LT:
5514 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5515 break;
5516 case OPC2_32_RC_SH_LT_U:
5517 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5518 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5519 break;
5520 case OPC2_32_RC_SH_NE:
5521 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5522 break;
5523 case OPC2_32_RC_XOR_EQ:
5524 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5525 const9, &tcg_gen_xor_tl);
5526 break;
5527 case OPC2_32_RC_XOR_GE:
5528 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5529 const9, &tcg_gen_xor_tl);
5530 break;
5531 case OPC2_32_RC_XOR_GE_U:
5532 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5533 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5534 const9, &tcg_gen_xor_tl);
5535 break;
5536 case OPC2_32_RC_XOR_LT:
5537 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5538 const9, &tcg_gen_xor_tl);
5539 break;
5540 case OPC2_32_RC_XOR_LT_U:
5541 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5542 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5543 const9, &tcg_gen_xor_tl);
5544 break;
5545 case OPC2_32_RC_XOR_NE:
5546 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5547 const9, &tcg_gen_xor_tl);
5548 break;
5549 }
5550 tcg_temp_free(temp);
5551 }
5552
5553 static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx)
5554 {
5555 uint32_t op2;
5556 uint32_t const9;
5557
5558 op2 = MASK_OP_RC_OP2(ctx->opcode);
5559 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5560
5561 switch (op2) {
5562 case OPC2_32_RC_BISR:
5563 gen_helper_1arg(bisr, const9);
5564 break;
5565 case OPC2_32_RC_SYSCALL:
5566 /* TODO: Add exception generation */
5567 break;
5568 }
5569 }
5570
5571 static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx)
5572 {
5573 uint32_t op2;
5574 int r1, r2;
5575 int16_t const9;
5576
5577 r2 = MASK_OP_RC_D(ctx->opcode);
5578 r1 = MASK_OP_RC_S1(ctx->opcode);
5579 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5580
5581 op2 = MASK_OP_RC_OP2(ctx->opcode);
5582
5583 switch (op2) {
5584 case OPC2_32_RC_MUL_32:
5585 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5586 break;
5587 case OPC2_32_RC_MUL_64:
5588 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5589 break;
5590 case OPC2_32_RC_MULS_32:
5591 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5592 break;
5593 case OPC2_32_RC_MUL_U_64:
5594 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5595 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5596 break;
5597 case OPC2_32_RC_MULS_U_32:
5598 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5599 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5600 break;
5601 }
5602 }
5603
5604 /* RCPW format */
5605 static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx)
5606 {
5607 uint32_t op2;
5608 int r1, r2;
5609 int32_t pos, width, const4;
5610
5611 TCGv temp;
5612
5613 op2 = MASK_OP_RCPW_OP2(ctx->opcode);
5614 r1 = MASK_OP_RCPW_S1(ctx->opcode);
5615 r2 = MASK_OP_RCPW_D(ctx->opcode);
5616 const4 = MASK_OP_RCPW_CONST4(ctx->opcode);
5617 width = MASK_OP_RCPW_WIDTH(ctx->opcode);
5618 pos = MASK_OP_RCPW_POS(ctx->opcode);
5619
5620 switch (op2) {
5621 case OPC2_32_RCPW_IMASK:
5622 /* if pos + width > 31 undefined result */
5623 if (pos + width <= 31) {
5624 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
5625 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
5626 }
5627 break;
5628 case OPC2_32_RCPW_INSERT:
5629 /* if pos + width > 32 undefined result */
5630 if (pos + width <= 32) {
5631 temp = tcg_const_i32(const4);
5632 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
5633 tcg_temp_free(temp);
5634 }
5635 break;
5636 }
5637 }
5638
5639 /* RCRW format */
5640
5641 static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx)
5642 {
5643 uint32_t op2;
5644 int r1, r3, r4;
5645 int32_t width, const4;
5646
5647 TCGv temp, temp2, temp3;
5648
5649 op2 = MASK_OP_RCRW_OP2(ctx->opcode);
5650 r1 = MASK_OP_RCRW_S1(ctx->opcode);
5651 r3 = MASK_OP_RCRW_S3(ctx->opcode);
5652 r4 = MASK_OP_RCRW_D(ctx->opcode);
5653 width = MASK_OP_RCRW_WIDTH(ctx->opcode);
5654 const4 = MASK_OP_RCRW_CONST4(ctx->opcode);
5655
5656 temp = tcg_temp_new();
5657 temp2 = tcg_temp_new();
5658
5659 switch (op2) {
5660 case OPC2_32_RCRW_IMASK:
5661 tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f);
5662 tcg_gen_movi_tl(temp2, (1 << width) - 1);
5663 tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp);
5664 tcg_gen_movi_tl(temp2, const4);
5665 tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp);
5666 break;
5667 case OPC2_32_RCRW_INSERT:
5668 temp3 = tcg_temp_new();
5669
5670 tcg_gen_movi_tl(temp, width);
5671 tcg_gen_movi_tl(temp2, const4);
5672 tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f);
5673 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3);
5674
5675 tcg_temp_free(temp3);
5676 break;
5677 }
5678 tcg_temp_free(temp);
5679 tcg_temp_free(temp2);
5680 }
5681
5682 /* RCR format */
5683
5684 static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
5685 {
5686 uint32_t op2;
5687 int r1, r3, r4;
5688 int32_t const9;
5689
5690 TCGv temp, temp2;
5691
5692 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5693 r1 = MASK_OP_RCR_S1(ctx->opcode);
5694 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5695 r3 = MASK_OP_RCR_S3(ctx->opcode);
5696 r4 = MASK_OP_RCR_D(ctx->opcode);
5697
5698 switch (op2) {
5699 case OPC2_32_RCR_CADD:
5700 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r3],
5701 cpu_gpr_d[r4]);
5702 break;
5703 case OPC2_32_RCR_CADDN:
5704 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r3],
5705 cpu_gpr_d[r4]);
5706 break;
5707 case OPC2_32_RCR_SEL:
5708 temp = tcg_const_i32(0);
5709 temp2 = tcg_const_i32(const9);
5710 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5711 cpu_gpr_d[r1], temp2);
5712 tcg_temp_free(temp);
5713 tcg_temp_free(temp2);
5714 break;
5715 case OPC2_32_RCR_SELN:
5716 temp = tcg_const_i32(0);
5717 temp2 = tcg_const_i32(const9);
5718 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5719 cpu_gpr_d[r1], temp2);
5720 tcg_temp_free(temp);
5721 tcg_temp_free(temp2);
5722 break;
5723 }
5724 }
5725
5726 static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx)
5727 {
5728 uint32_t op2;
5729 int r1, r3, r4;
5730 int32_t const9;
5731
5732
5733 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5734 r1 = MASK_OP_RCR_S1(ctx->opcode);
5735 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5736 r3 = MASK_OP_RCR_S3(ctx->opcode);
5737 r4 = MASK_OP_RCR_D(ctx->opcode);
5738
5739 switch (op2) {
5740 case OPC2_32_RCR_MADD_32:
5741 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5742 break;
5743 case OPC2_32_RCR_MADD_64:
5744 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5745 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5746 break;
5747 case OPC2_32_RCR_MADDS_32:
5748 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5749 break;
5750 case OPC2_32_RCR_MADDS_64:
5751 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5752 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5753 break;
5754 case OPC2_32_RCR_MADD_U_64:
5755 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5756 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5757 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5758 break;
5759 case OPC2_32_RCR_MADDS_U_32:
5760 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5761 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5762 break;
5763 case OPC2_32_RCR_MADDS_U_64:
5764 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5765 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5766 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5767 break;
5768 }
5769 }
5770
5771 static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx)
5772 {
5773 uint32_t op2;
5774 int r1, r3, r4;
5775 int32_t const9;
5776
5777
5778 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5779 r1 = MASK_OP_RCR_S1(ctx->opcode);
5780 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5781 r3 = MASK_OP_RCR_S3(ctx->opcode);
5782 r4 = MASK_OP_RCR_D(ctx->opcode);
5783
5784 switch (op2) {
5785 case OPC2_32_RCR_MSUB_32:
5786 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5787 break;
5788 case OPC2_32_RCR_MSUB_64:
5789 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5790 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5791 break;
5792 case OPC2_32_RCR_MSUBS_32:
5793 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5794 break;
5795 case OPC2_32_RCR_MSUBS_64:
5796 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5797 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5798 break;
5799 case OPC2_32_RCR_MSUB_U_64:
5800 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5801 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5802 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5803 break;
5804 case OPC2_32_RCR_MSUBS_U_32:
5805 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5806 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5807 break;
5808 case OPC2_32_RCR_MSUBS_U_64:
5809 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5810 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5811 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5812 break;
5813 }
5814 }
5815
5816 /* RLC format */
5817
5818 static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx,
5819 uint32_t op1)
5820 {
5821 int32_t const16;
5822 int r1, r2;
5823
5824 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode);
5825 r1 = MASK_OP_RLC_S1(ctx->opcode);
5826 r2 = MASK_OP_RLC_D(ctx->opcode);
5827
5828 switch (op1) {
5829 case OPC1_32_RLC_ADDI:
5830 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16);
5831 break;
5832 case OPC1_32_RLC_ADDIH:
5833 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
5834 break;
5835 case OPC1_32_RLC_ADDIH_A:
5836 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
5837 break;
5838 case OPC1_32_RLC_MFCR:
5839 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5840 gen_mfcr(env, cpu_gpr_d[r2], const16);
5841 break;
5842 case OPC1_32_RLC_MOV:
5843 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5844 break;
5845 case OPC1_32_RLC_MOV_64:
5846 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5847 if ((r2 & 0x1) != 0) {
5848 /* TODO: raise OPD trap */
5849 }
5850 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5851 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
5852 } else {
5853 /* TODO: raise illegal opcode trap */
5854 }
5855 break;
5856 case OPC1_32_RLC_MOV_U:
5857 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5858 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5859 break;
5860 case OPC1_32_RLC_MOV_H:
5861 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16);
5862 break;
5863 case OPC1_32_RLC_MOVH_A:
5864 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16);
5865 break;
5866 case OPC1_32_RLC_MTCR:
5867 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5868 gen_mtcr(env, ctx, cpu_gpr_d[r1], const16);
5869 break;
5870 }
5871 }
5872
5873 /* RR format */
5874 static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
5875 {
5876 uint32_t op2;
5877 int r3, r2, r1;
5878
5879 r3 = MASK_OP_RR_D(ctx->opcode);
5880 r2 = MASK_OP_RR_S2(ctx->opcode);
5881 r1 = MASK_OP_RR_S1(ctx->opcode);
5882 op2 = MASK_OP_RR_OP2(ctx->opcode);
5883
5884 switch (op2) {
5885 case OPC2_32_RR_ABS:
5886 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5887 break;
5888 case OPC2_32_RR_ABS_B:
5889 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5890 break;
5891 case OPC2_32_RR_ABS_H:
5892 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5893 break;
5894 case OPC2_32_RR_ABSDIF:
5895 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5896 break;
5897 case OPC2_32_RR_ABSDIF_B:
5898 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5899 cpu_gpr_d[r2]);
5900 break;
5901 case OPC2_32_RR_ABSDIF_H:
5902 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5903 cpu_gpr_d[r2]);
5904 break;
5905 case OPC2_32_RR_ABSDIFS:
5906 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5907 cpu_gpr_d[r2]);
5908 break;
5909 case OPC2_32_RR_ABSDIFS_H:
5910 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5911 cpu_gpr_d[r2]);
5912 break;
5913 case OPC2_32_RR_ABSS:
5914 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5915 break;
5916 case OPC2_32_RR_ABSS_H:
5917 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5918 break;
5919 case OPC2_32_RR_ADD:
5920 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5921 break;
5922 case OPC2_32_RR_ADD_B:
5923 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5924 break;
5925 case OPC2_32_RR_ADD_H:
5926 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5927 break;
5928 case OPC2_32_RR_ADDC:
5929 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5930 break;
5931 case OPC2_32_RR_ADDS:
5932 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5933 break;
5934 case OPC2_32_RR_ADDS_H:
5935 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5936 cpu_gpr_d[r2]);
5937 break;
5938 case OPC2_32_RR_ADDS_HU:
5939 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5940 cpu_gpr_d[r2]);
5941 break;
5942 case OPC2_32_RR_ADDS_U:
5943 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5944 cpu_gpr_d[r2]);
5945 break;
5946 case OPC2_32_RR_ADDX:
5947 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5948 break;
5949 case OPC2_32_RR_AND_EQ:
5950 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5951 cpu_gpr_d[r2], &tcg_gen_and_tl);
5952 break;
5953 case OPC2_32_RR_AND_GE:
5954 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5955 cpu_gpr_d[r2], &tcg_gen_and_tl);
5956 break;
5957 case OPC2_32_RR_AND_GE_U:
5958 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5959 cpu_gpr_d[r2], &tcg_gen_and_tl);
5960 break;
5961 case OPC2_32_RR_AND_LT:
5962 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5963 cpu_gpr_d[r2], &tcg_gen_and_tl);
5964 break;
5965 case OPC2_32_RR_AND_LT_U:
5966 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5967 cpu_gpr_d[r2], &tcg_gen_and_tl);
5968 break;
5969 case OPC2_32_RR_AND_NE:
5970 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5971 cpu_gpr_d[r2], &tcg_gen_and_tl);
5972 break;
5973 case OPC2_32_RR_EQ:
5974 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5975 cpu_gpr_d[r2]);
5976 break;
5977 case OPC2_32_RR_EQ_B:
5978 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5979 break;
5980 case OPC2_32_RR_EQ_H:
5981 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5982 break;
5983 case OPC2_32_RR_EQ_W:
5984 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5985 break;
5986 case OPC2_32_RR_EQANY_B:
5987 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5988 break;
5989 case OPC2_32_RR_EQANY_H:
5990 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5991 break;
5992 case OPC2_32_RR_GE:
5993 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5994 cpu_gpr_d[r2]);
5995 break;
5996 case OPC2_32_RR_GE_U:
5997 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5998 cpu_gpr_d[r2]);
5999 break;
6000 case OPC2_32_RR_LT:
6001 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6002 cpu_gpr_d[r2]);
6003 break;
6004 case OPC2_32_RR_LT_U:
6005 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6006 cpu_gpr_d[r2]);
6007 break;
6008 case OPC2_32_RR_LT_B:
6009 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6010 break;
6011 case OPC2_32_RR_LT_BU:
6012 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6013 break;
6014 case OPC2_32_RR_LT_H:
6015 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6016 break;
6017 case OPC2_32_RR_LT_HU:
6018 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6019 break;
6020 case OPC2_32_RR_LT_W:
6021 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6022 break;
6023 case OPC2_32_RR_LT_WU:
6024 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6025 break;
6026 case OPC2_32_RR_MAX:
6027 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6028 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6029 break;
6030 case OPC2_32_RR_MAX_U:
6031 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6032 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6033 break;
6034 case OPC2_32_RR_MAX_B:
6035 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6036 break;
6037 case OPC2_32_RR_MAX_BU:
6038 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6039 break;
6040 case OPC2_32_RR_MAX_H:
6041 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6042 break;
6043 case OPC2_32_RR_MAX_HU:
6044 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6045 break;
6046 case OPC2_32_RR_MIN:
6047 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6048 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6049 break;
6050 case OPC2_32_RR_MIN_U:
6051 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6052 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6053 break;
6054 case OPC2_32_RR_MIN_B:
6055 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6056 break;
6057 case OPC2_32_RR_MIN_BU:
6058 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6059 break;
6060 case OPC2_32_RR_MIN_H:
6061 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6062 break;
6063 case OPC2_32_RR_MIN_HU:
6064 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6065 break;
6066 case OPC2_32_RR_MOV:
6067 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
6068 break;
6069 case OPC2_32_RR_NE:
6070 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6071 cpu_gpr_d[r2]);
6072 break;
6073 case OPC2_32_RR_OR_EQ:
6074 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6075 cpu_gpr_d[r2], &tcg_gen_or_tl);
6076 break;
6077 case OPC2_32_RR_OR_GE:
6078 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6079 cpu_gpr_d[r2], &tcg_gen_or_tl);
6080 break;
6081 case OPC2_32_RR_OR_GE_U:
6082 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6083 cpu_gpr_d[r2], &tcg_gen_or_tl);
6084 break;
6085 case OPC2_32_RR_OR_LT:
6086 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6087 cpu_gpr_d[r2], &tcg_gen_or_tl);
6088 break;
6089 case OPC2_32_RR_OR_LT_U:
6090 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6091 cpu_gpr_d[r2], &tcg_gen_or_tl);
6092 break;
6093 case OPC2_32_RR_OR_NE:
6094 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6095 cpu_gpr_d[r2], &tcg_gen_or_tl);
6096 break;
6097 case OPC2_32_RR_SAT_B:
6098 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80);
6099 break;
6100 case OPC2_32_RR_SAT_BU:
6101 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff);
6102 break;
6103 case OPC2_32_RR_SAT_H:
6104 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000);
6105 break;
6106 case OPC2_32_RR_SAT_HU:
6107 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff);
6108 break;
6109 case OPC2_32_RR_SH_EQ:
6110 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6111 cpu_gpr_d[r2]);
6112 break;
6113 case OPC2_32_RR_SH_GE:
6114 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6115 cpu_gpr_d[r2]);
6116 break;
6117 case OPC2_32_RR_SH_GE_U:
6118 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6119 cpu_gpr_d[r2]);
6120 break;
6121 case OPC2_32_RR_SH_LT:
6122 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6123 cpu_gpr_d[r2]);
6124 break;
6125 case OPC2_32_RR_SH_LT_U:
6126 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6127 cpu_gpr_d[r2]);
6128 break;
6129 case OPC2_32_RR_SH_NE:
6130 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6131 cpu_gpr_d[r2]);
6132 break;
6133 case OPC2_32_RR_SUB:
6134 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6135 break;
6136 case OPC2_32_RR_SUB_B:
6137 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6138 break;
6139 case OPC2_32_RR_SUB_H:
6140 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6141 break;
6142 case OPC2_32_RR_SUBC:
6143 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6144 break;
6145 case OPC2_32_RR_SUBS:
6146 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6147 break;
6148 case OPC2_32_RR_SUBS_U:
6149 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6150 break;
6151 case OPC2_32_RR_SUBS_H:
6152 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6153 cpu_gpr_d[r2]);
6154 break;
6155 case OPC2_32_RR_SUBS_HU:
6156 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6157 cpu_gpr_d[r2]);
6158 break;
6159 case OPC2_32_RR_SUBX:
6160 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6161 break;
6162 case OPC2_32_RR_XOR_EQ:
6163 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6164 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6165 break;
6166 case OPC2_32_RR_XOR_GE:
6167 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6168 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6169 break;
6170 case OPC2_32_RR_XOR_GE_U:
6171 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6172 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6173 break;
6174 case OPC2_32_RR_XOR_LT:
6175 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6176 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6177 break;
6178 case OPC2_32_RR_XOR_LT_U:
6179 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6180 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6181 break;
6182 case OPC2_32_RR_XOR_NE:
6183 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6184 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6185 break;
6186 }
6187 }
6188
6189 static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
6190 {
6191 uint32_t op2;
6192 int r3, r2, r1;
6193 TCGv temp;
6194
6195 r3 = MASK_OP_RR_D(ctx->opcode);
6196 r2 = MASK_OP_RR_S2(ctx->opcode);
6197 r1 = MASK_OP_RR_S1(ctx->opcode);
6198
6199 temp = tcg_temp_new();
6200 op2 = MASK_OP_RR_OP2(ctx->opcode);
6201
6202 switch (op2) {
6203 case OPC2_32_RR_AND:
6204 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6205 break;
6206 case OPC2_32_RR_ANDN:
6207 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6208 break;
6209 case OPC2_32_RR_CLO:
6210 gen_helper_clo(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6211 break;
6212 case OPC2_32_RR_CLO_H:
6213 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6214 break;
6215 case OPC2_32_RR_CLS:
6216 gen_helper_cls(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6217 break;
6218 case OPC2_32_RR_CLS_H:
6219 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6220 break;
6221 case OPC2_32_RR_CLZ:
6222 gen_helper_clz(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6223 break;
6224 case OPC2_32_RR_CLZ_H:
6225 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6226 break;
6227 case OPC2_32_RR_NAND:
6228 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6229 break;
6230 case OPC2_32_RR_NOR:
6231 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6232 break;
6233 case OPC2_32_RR_OR:
6234 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6235 break;
6236 case OPC2_32_RR_ORN:
6237 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6238 break;
6239 case OPC2_32_RR_SH:
6240 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6241 break;
6242 case OPC2_32_RR_SH_H:
6243 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6244 break;
6245 case OPC2_32_RR_SHA:
6246 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6247 break;
6248 case OPC2_32_RR_SHA_H:
6249 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6250 break;
6251 case OPC2_32_RR_SHAS:
6252 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6253 break;
6254 case OPC2_32_RR_XNOR:
6255 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6256 break;
6257 case OPC2_32_RR_XOR:
6258 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6259 break;
6260 }
6261 tcg_temp_free(temp);
6262 }
6263
6264 static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx)
6265 {
6266 uint32_t op2, n;
6267 int r1, r2, r3;
6268 TCGv temp;
6269
6270 op2 = MASK_OP_RR_OP2(ctx->opcode);
6271 r3 = MASK_OP_RR_D(ctx->opcode);
6272 r2 = MASK_OP_RR_S2(ctx->opcode);
6273 r1 = MASK_OP_RR_S1(ctx->opcode);
6274 n = MASK_OP_RR_N(ctx->opcode);
6275
6276 switch (op2) {
6277 case OPC2_32_RR_ADD_A:
6278 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6279 break;
6280 case OPC2_32_RR_ADDSC_A:
6281 temp = tcg_temp_new();
6282 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n);
6283 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp);
6284 tcg_temp_free(temp);
6285 break;
6286 case OPC2_32_RR_ADDSC_AT:
6287 temp = tcg_temp_new();
6288 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3);
6289 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp);
6290 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC);
6291 tcg_temp_free(temp);
6292 break;
6293 case OPC2_32_RR_EQ_A:
6294 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1],
6295 cpu_gpr_a[r2]);
6296 break;
6297 case OPC2_32_RR_EQZ:
6298 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6299 break;
6300 case OPC2_32_RR_GE_A:
6301 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6302 cpu_gpr_a[r2]);
6303 break;
6304 case OPC2_32_RR_LT_A:
6305 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6306 cpu_gpr_a[r2]);
6307 break;
6308 case OPC2_32_RR_MOV_A:
6309 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]);
6310 break;
6311 case OPC2_32_RR_MOV_AA:
6312 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]);
6313 break;
6314 case OPC2_32_RR_MOV_D:
6315 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]);
6316 break;
6317 case OPC2_32_RR_NE_A:
6318 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1],
6319 cpu_gpr_a[r2]);
6320 break;
6321 case OPC2_32_RR_NEZ_A:
6322 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6323 break;
6324 case OPC2_32_RR_SUB_A:
6325 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6326 break;
6327 }
6328 }
6329
6330 static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx)
6331 {
6332 uint32_t op2;
6333 int r1;
6334
6335 op2 = MASK_OP_RR_OP2(ctx->opcode);
6336 r1 = MASK_OP_RR_S1(ctx->opcode);
6337
6338 switch (op2) {
6339 case OPC2_32_RR_JI:
6340 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6341 break;
6342 case OPC2_32_RR_JLI:
6343 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
6344 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6345 break;
6346 case OPC2_32_RR_CALLI:
6347 gen_helper_1arg(call, ctx->next_pc);
6348 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6349 break;
6350 case OPC2_32_RR_FCALLI:
6351 gen_fcall_save_ctx(ctx);
6352 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6353 break;
6354 }
6355 tcg_gen_exit_tb(0);
6356 ctx->bstate = BS_BRANCH;
6357 }
6358
6359 static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
6360 {
6361 uint32_t op2;
6362 int r1, r2, r3;
6363
6364 TCGv temp, temp2, temp3;
6365
6366 op2 = MASK_OP_RR_OP2(ctx->opcode);
6367 r3 = MASK_OP_RR_D(ctx->opcode);
6368 r2 = MASK_OP_RR_S2(ctx->opcode);
6369 r1 = MASK_OP_RR_S1(ctx->opcode);
6370
6371 switch (op2) {
6372 case OPC2_32_RR_BMERGE:
6373 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6374 break;
6375 case OPC2_32_RR_BSPLIT:
6376 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6377 break;
6378 case OPC2_32_RR_DVINIT_B:
6379 gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6380 cpu_gpr_d[r2]);
6381 break;
6382 case OPC2_32_RR_DVINIT_BU:
6383 temp = tcg_temp_new();
6384 temp2 = tcg_temp_new();
6385 temp3 = tcg_temp_new();
6386
6387 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
6388 /* reset av */
6389 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6390 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
6391 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6392 tcg_gen_neg_tl(temp, temp3);
6393 /* use cpu_PSW_AV to compare against 0 */
6394 tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
6395 temp, temp3);
6396 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
6397 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
6398 temp2, cpu_gpr_d[r2]);
6399 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6400 } else {
6401 /* overflow = (D[b] == 0) */
6402 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6403 }
6404 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6405 /* sv */
6406 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6407 /* write result */
6408 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
6409 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6410
6411 tcg_temp_free(temp);
6412 tcg_temp_free(temp2);
6413 tcg_temp_free(temp3);
6414 break;
6415 case OPC2_32_RR_DVINIT_H:
6416 gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6417 cpu_gpr_d[r2]);
6418 break;
6419 case OPC2_32_RR_DVINIT_HU:
6420 temp = tcg_temp_new();
6421 temp2 = tcg_temp_new();
6422 temp3 = tcg_temp_new();
6423
6424 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
6425 /* reset av */
6426 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6427 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
6428 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6429 tcg_gen_neg_tl(temp, temp3);
6430 /* use cpu_PSW_AV to compare against 0 */
6431 tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
6432 temp, temp3);
6433 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
6434 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
6435 temp2, cpu_gpr_d[r2]);
6436 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6437 } else {
6438 /* overflow = (D[b] == 0) */
6439 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6440 }
6441 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6442 /* sv */
6443 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6444 /* write result */
6445 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
6446 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6447 tcg_temp_free(temp);
6448 tcg_temp_free(temp2);
6449 tcg_temp_free(temp3);
6450 break;
6451 case OPC2_32_RR_DVINIT:
6452 temp = tcg_temp_new();
6453 temp2 = tcg_temp_new();
6454 /* overflow = ((D[b] == 0) ||
6455 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
6456 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
6457 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000);
6458 tcg_gen_and_tl(temp, temp, temp2);
6459 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0);
6460 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
6461 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6462 /* sv */
6463 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6464 /* reset av */
6465 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6466 /* write result */
6467 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6468 /* sign extend to high reg */
6469 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31);
6470 tcg_temp_free(temp);
6471 tcg_temp_free(temp2);
6472 break;
6473 case OPC2_32_RR_DVINIT_U:
6474 /* overflow = (D[b] == 0) */
6475 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6476 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6477 /* sv */
6478 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6479 /* reset av */
6480 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6481 /* write result */
6482 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6483 /* zero extend to high reg*/
6484 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0);
6485 break;
6486 case OPC2_32_RR_PARITY:
6487 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6488 break;
6489 case OPC2_32_RR_UNPACK:
6490 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6491 break;
6492 case OPC2_32_RR_CRC32:
6493 if (tricore_feature(env, TRICORE_FEATURE_161)) {
6494 gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6495 } /* TODO: else raise illegal opcode trap */
6496 break;
6497 case OPC2_32_RR_DIV:
6498 if (tricore_feature(env, TRICORE_FEATURE_16)) {
6499 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6500 cpu_gpr_d[r2]);
6501 } /* TODO: else raise illegal opcode trap */
6502 break;
6503 case OPC2_32_RR_DIV_U:
6504 if (tricore_feature(env, TRICORE_FEATURE_16)) {
6505 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
6506 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6507 } /* TODO: else raise illegal opcode trap */
6508 break;
6509 }
6510 }
6511
6512 /* RR1 Format */
6513 static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx)
6514 {
6515 uint32_t op2;
6516
6517 int r1, r2, r3;
6518 TCGv n;
6519 TCGv_i64 temp64;
6520
6521 r1 = MASK_OP_RR1_S1(ctx->opcode);
6522 r2 = MASK_OP_RR1_S2(ctx->opcode);
6523 r3 = MASK_OP_RR1_D(ctx->opcode);
6524 n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode));
6525 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6526
6527 switch (op2) {
6528 case OPC2_32_RR1_MUL_H_32_LL:
6529 temp64 = tcg_temp_new_i64();
6530 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6531 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6532 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6533 tcg_temp_free_i64(temp64);
6534 break;
6535 case OPC2_32_RR1_MUL_H_32_LU:
6536 temp64 = tcg_temp_new_i64();
6537 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6538 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6539 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6540 tcg_temp_free_i64(temp64);
6541 break;
6542 case OPC2_32_RR1_MUL_H_32_UL:
6543 temp64 = tcg_temp_new_i64();
6544 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6545 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6546 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6547 tcg_temp_free_i64(temp64);
6548 break;
6549 case OPC2_32_RR1_MUL_H_32_UU:
6550 temp64 = tcg_temp_new_i64();
6551 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6552 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6553 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6554 tcg_temp_free_i64(temp64);
6555 break;
6556 case OPC2_32_RR1_MULM_H_64_LL:
6557 temp64 = tcg_temp_new_i64();
6558 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6559 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6560 /* reset V bit */
6561 tcg_gen_movi_tl(cpu_PSW_V, 0);
6562 /* reset AV bit */
6563 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6564 tcg_temp_free_i64(temp64);
6565 break;
6566 case OPC2_32_RR1_MULM_H_64_LU:
6567 temp64 = tcg_temp_new_i64();
6568 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6569 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6570 /* reset V bit */
6571 tcg_gen_movi_tl(cpu_PSW_V, 0);
6572 /* reset AV bit */
6573 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6574 tcg_temp_free_i64(temp64);
6575 break;
6576 case OPC2_32_RR1_MULM_H_64_UL:
6577 temp64 = tcg_temp_new_i64();
6578 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6579 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6580 /* reset V bit */
6581 tcg_gen_movi_tl(cpu_PSW_V, 0);
6582 /* reset AV bit */
6583 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6584 tcg_temp_free_i64(temp64);
6585 break;
6586 case OPC2_32_RR1_MULM_H_64_UU:
6587 temp64 = tcg_temp_new_i64();
6588 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6589 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6590 /* reset V bit */
6591 tcg_gen_movi_tl(cpu_PSW_V, 0);
6592 /* reset AV bit */
6593 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6594 tcg_temp_free_i64(temp64);
6595
6596 break;
6597 case OPC2_32_RR1_MULR_H_16_LL:
6598 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6599 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6600 break;
6601 case OPC2_32_RR1_MULR_H_16_LU:
6602 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6603 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6604 break;
6605 case OPC2_32_RR1_MULR_H_16_UL:
6606 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6607 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6608 break;
6609 case OPC2_32_RR1_MULR_H_16_UU:
6610 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6611 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6612 break;
6613 }
6614 tcg_temp_free(n);
6615 }
6616
6617 static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx)
6618 {
6619 uint32_t op2;
6620 int r1, r2, r3;
6621 uint32_t n;
6622
6623 TCGv temp, temp2;
6624
6625 r1 = MASK_OP_RR1_S1(ctx->opcode);
6626 r2 = MASK_OP_RR1_S2(ctx->opcode);
6627 r3 = MASK_OP_RR1_D(ctx->opcode);
6628 n = MASK_OP_RR1_N(ctx->opcode);
6629 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6630
6631 temp = tcg_temp_new();
6632 temp2 = tcg_temp_new();
6633
6634 switch (op2) {
6635 case OPC2_32_RR1_MUL_Q_32:
6636 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32);
6637 break;
6638 case OPC2_32_RR1_MUL_Q_64:
6639 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6640 n, 0);
6641 break;
6642 case OPC2_32_RR1_MUL_Q_32_L:
6643 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6644 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6645 break;
6646 case OPC2_32_RR1_MUL_Q_64_L:
6647 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6648 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6649 break;
6650 case OPC2_32_RR1_MUL_Q_32_U:
6651 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6652 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6653 break;
6654 case OPC2_32_RR1_MUL_Q_64_U:
6655 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6656 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6657 break;
6658 case OPC2_32_RR1_MUL_Q_32_LL:
6659 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6660 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6661 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6662 break;
6663 case OPC2_32_RR1_MUL_Q_32_UU:
6664 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6665 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6666 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6667 break;
6668 case OPC2_32_RR1_MULR_Q_32_L:
6669 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6670 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6671 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6672 break;
6673 case OPC2_32_RR1_MULR_Q_32_U:
6674 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6675 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6676 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6677 break;
6678 }
6679 tcg_temp_free(temp);
6680 tcg_temp_free(temp2);
6681 }
6682
6683 /* RR2 format */
6684 static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx)
6685 {
6686 uint32_t op2;
6687 int r1, r2, r3;
6688
6689 op2 = MASK_OP_RR2_OP2(ctx->opcode);
6690 r1 = MASK_OP_RR2_S1(ctx->opcode);
6691 r2 = MASK_OP_RR2_S2(ctx->opcode);
6692 r3 = MASK_OP_RR2_D(ctx->opcode);
6693 switch (op2) {
6694 case OPC2_32_RR2_MUL_32:
6695 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6696 break;
6697 case OPC2_32_RR2_MUL_64:
6698 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6699 cpu_gpr_d[r2]);
6700 break;
6701 case OPC2_32_RR2_MULS_32:
6702 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6703 cpu_gpr_d[r2]);
6704 break;
6705 case OPC2_32_RR2_MUL_U_64:
6706 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6707 cpu_gpr_d[r2]);
6708 break;
6709 case OPC2_32_RR2_MULS_U_32:
6710 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6711 cpu_gpr_d[r2]);
6712 break;
6713 }
6714 }
6715
6716 /* RRPW format */
6717 static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
6718 {
6719 uint32_t op2;
6720 int r1, r2, r3;
6721 int32_t pos, width;
6722
6723 op2 = MASK_OP_RRPW_OP2(ctx->opcode);
6724 r1 = MASK_OP_RRPW_S1(ctx->opcode);
6725 r2 = MASK_OP_RRPW_S2(ctx->opcode);
6726 r3 = MASK_OP_RRPW_D(ctx->opcode);
6727 pos = MASK_OP_RRPW_POS(ctx->opcode);
6728 width = MASK_OP_RRPW_WIDTH(ctx->opcode);
6729
6730 switch (op2) {
6731 case OPC2_32_RRPW_EXTR:
6732 if (pos + width <= 31) {
6733 /* optimize special cases */
6734 if ((pos == 0) && (width == 8)) {
6735 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6736 } else if ((pos == 0) && (width == 16)) {
6737 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6738 } else {
6739 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width);
6740 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width);
6741 }
6742 }
6743 break;
6744 case OPC2_32_RRPW_EXTR_U:
6745 if (width == 0) {
6746 tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
6747 } else {
6748 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
6749 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width));
6750 }
6751 break;
6752 case OPC2_32_RRPW_IMASK:
6753 if (pos + width <= 31) {
6754 tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos);
6755 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
6756 }
6757 break;
6758 case OPC2_32_RRPW_INSERT:
6759 if (pos + width <= 31) {
6760 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
6761 width, pos);
6762 }
6763 break;
6764 }
6765 }
6766
6767 /* RRR format */
6768 static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
6769 {
6770 uint32_t op2;
6771 int r1, r2, r3, r4;
6772 TCGv temp;
6773
6774 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6775 r1 = MASK_OP_RRR_S1(ctx->opcode);
6776 r2 = MASK_OP_RRR_S2(ctx->opcode);
6777 r3 = MASK_OP_RRR_S3(ctx->opcode);
6778 r4 = MASK_OP_RRR_D(ctx->opcode);
6779
6780 switch (op2) {
6781 case OPC2_32_RRR_CADD:
6782 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
6783 cpu_gpr_d[r4], cpu_gpr_d[r3]);
6784 break;
6785 case OPC2_32_RRR_CADDN:
6786 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6787 cpu_gpr_d[r3]);
6788 break;
6789 case OPC2_32_RRR_CSUB:
6790 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6791 cpu_gpr_d[r3]);
6792 break;
6793 case OPC2_32_RRR_CSUBN:
6794 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6795 cpu_gpr_d[r3]);
6796 break;
6797 case OPC2_32_RRR_SEL:
6798 temp = tcg_const_i32(0);
6799 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6800 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6801 tcg_temp_free(temp);
6802 break;
6803 case OPC2_32_RRR_SELN:
6804 temp = tcg_const_i32(0);
6805 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6806 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6807 tcg_temp_free(temp);
6808 break;
6809 }
6810 }
6811
6812 static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx)
6813 {
6814 uint32_t op2;
6815
6816 int r1, r2, r3, r4;
6817
6818 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6819 r1 = MASK_OP_RRR_S1(ctx->opcode);
6820 r2 = MASK_OP_RRR_S2(ctx->opcode);
6821 r3 = MASK_OP_RRR_S3(ctx->opcode);
6822 r4 = MASK_OP_RRR_D(ctx->opcode);
6823
6824 switch (op2) {
6825 case OPC2_32_RRR_DVADJ:
6826 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6827 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6828 break;
6829 case OPC2_32_RRR_DVSTEP:
6830 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6831 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6832 break;
6833 case OPC2_32_RRR_DVSTEP_U:
6834 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6835 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6836 break;
6837 case OPC2_32_RRR_IXMAX:
6838 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6839 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6840 break;
6841 case OPC2_32_RRR_IXMAX_U:
6842 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6843 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6844 break;
6845 case OPC2_32_RRR_IXMIN:
6846 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6847 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6848 break;
6849 case OPC2_32_RRR_IXMIN_U:
6850 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6851 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6852 break;
6853 case OPC2_32_RRR_PACK:
6854 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
6855 cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6856 break;
6857 }
6858 }
6859
6860 /* RRR2 format */
6861 static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx)
6862 {
6863 uint32_t op2;
6864 uint32_t r1, r2, r3, r4;
6865
6866 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
6867 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6868 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6869 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6870 r4 = MASK_OP_RRR2_D(ctx->opcode);
6871 switch (op2) {
6872 case OPC2_32_RRR2_MADD_32:
6873 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6874 cpu_gpr_d[r2]);
6875 break;
6876 case OPC2_32_RRR2_MADD_64:
6877 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6878 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6879 break;
6880 case OPC2_32_RRR2_MADDS_32:
6881 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6882 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6883 break;
6884 case OPC2_32_RRR2_MADDS_64:
6885 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6886 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6887 break;
6888 case OPC2_32_RRR2_MADD_U_64:
6889 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6890 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6891 break;
6892 case OPC2_32_RRR2_MADDS_U_32:
6893 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6894 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6895 break;
6896 case OPC2_32_RRR2_MADDS_U_64:
6897 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6898 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6899 break;
6900 }
6901 }
6902
6903 static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx)
6904 {
6905 uint32_t op2;
6906 uint32_t r1, r2, r3, r4;
6907
6908 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
6909 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6910 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6911 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6912 r4 = MASK_OP_RRR2_D(ctx->opcode);
6913
6914 switch (op2) {
6915 case OPC2_32_RRR2_MSUB_32:
6916 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6917 cpu_gpr_d[r2]);
6918 break;
6919 case OPC2_32_RRR2_MSUB_64:
6920 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6921 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6922 break;
6923 case OPC2_32_RRR2_MSUBS_32:
6924 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6925 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6926 break;
6927 case OPC2_32_RRR2_MSUBS_64:
6928 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6929 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6930 break;
6931 case OPC2_32_RRR2_MSUB_U_64:
6932 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6933 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6934 break;
6935 case OPC2_32_RRR2_MSUBS_U_32:
6936 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6937 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6938 break;
6939 case OPC2_32_RRR2_MSUBS_U_64:
6940 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6941 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6942 break;
6943 }
6944 }
6945
6946 /* RRR1 format */
6947 static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx)
6948 {
6949 uint32_t op2;
6950 uint32_t r1, r2, r3, r4, n;
6951
6952 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
6953 r1 = MASK_OP_RRR1_S1(ctx->opcode);
6954 r2 = MASK_OP_RRR1_S2(ctx->opcode);
6955 r3 = MASK_OP_RRR1_S3(ctx->opcode);
6956 r4 = MASK_OP_RRR1_D(ctx->opcode);
6957 n = MASK_OP_RRR1_N(ctx->opcode);
6958
6959 switch (op2) {
6960 case OPC2_32_RRR1_MADD_H_LL:
6961 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6962 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6963 break;
6964 case OPC2_32_RRR1_MADD_H_LU:
6965 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6966 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6967 break;
6968 case OPC2_32_RRR1_MADD_H_UL:
6969 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6970 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6971 break;
6972 case OPC2_32_RRR1_MADD_H_UU:
6973 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6974 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6975 break;
6976 case OPC2_32_RRR1_MADDS_H_LL:
6977 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6978 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6979 break;
6980 case OPC2_32_RRR1_MADDS_H_LU:
6981 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6982 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6983 break;
6984 case OPC2_32_RRR1_MADDS_H_UL:
6985 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6986 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6987 break;
6988 case OPC2_32_RRR1_MADDS_H_UU:
6989 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6990 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6991 break;
6992 case OPC2_32_RRR1_MADDM_H_LL:
6993 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6994 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6995 break;
6996 case OPC2_32_RRR1_MADDM_H_LU:
6997 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6998 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6999 break;
7000 case OPC2_32_RRR1_MADDM_H_UL:
7001 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7002 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7003 break;
7004 case OPC2_32_RRR1_MADDM_H_UU:
7005 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7006 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7007 break;
7008 case OPC2_32_RRR1_MADDMS_H_LL:
7009 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7010 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7011 break;
7012 case OPC2_32_RRR1_MADDMS_H_LU:
7013 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7014 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7015 break;
7016 case OPC2_32_RRR1_MADDMS_H_UL:
7017 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7018 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7019 break;
7020 case OPC2_32_RRR1_MADDMS_H_UU:
7021 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7022 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7023 break;
7024 case OPC2_32_RRR1_MADDR_H_LL:
7025 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7026 cpu_gpr_d[r2], n, MODE_LL);
7027 break;
7028 case OPC2_32_RRR1_MADDR_H_LU:
7029 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7030 cpu_gpr_d[r2], n, MODE_LU);
7031 break;
7032 case OPC2_32_RRR1_MADDR_H_UL:
7033 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7034 cpu_gpr_d[r2], n, MODE_UL);
7035 break;
7036 case OPC2_32_RRR1_MADDR_H_UU:
7037 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7038 cpu_gpr_d[r2], n, MODE_UU);
7039 break;
7040 case OPC2_32_RRR1_MADDRS_H_LL:
7041 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7042 cpu_gpr_d[r2], n, MODE_LL);
7043 break;
7044 case OPC2_32_RRR1_MADDRS_H_LU:
7045 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7046 cpu_gpr_d[r2], n, MODE_LU);
7047 break;
7048 case OPC2_32_RRR1_MADDRS_H_UL:
7049 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7050 cpu_gpr_d[r2], n, MODE_UL);
7051 break;
7052 case OPC2_32_RRR1_MADDRS_H_UU:
7053 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7054 cpu_gpr_d[r2], n, MODE_UU);
7055 break;
7056 }
7057 }
7058
7059 static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx)
7060 {
7061 uint32_t op2;
7062 uint32_t r1, r2, r3, r4, n;
7063 TCGv temp, temp2;
7064
7065 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7066 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7067 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7068 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7069 r4 = MASK_OP_RRR1_D(ctx->opcode);
7070 n = MASK_OP_RRR1_N(ctx->opcode);
7071
7072 temp = tcg_const_i32(n);
7073 temp2 = tcg_temp_new();
7074
7075 switch (op2) {
7076 case OPC2_32_RRR1_MADD_Q_32:
7077 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7078 cpu_gpr_d[r2], n, 32, env);
7079 break;
7080 case OPC2_32_RRR1_MADD_Q_64:
7081 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7082 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7083 n, env);
7084 break;
7085 case OPC2_32_RRR1_MADD_Q_32_L:
7086 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7087 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7088 temp, n, 16, env);
7089 break;
7090 case OPC2_32_RRR1_MADD_Q_64_L:
7091 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7092 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7093 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7094 n, env);
7095 break;
7096 case OPC2_32_RRR1_MADD_Q_32_U:
7097 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7098 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7099 temp, n, 16, env);
7100 break;
7101 case OPC2_32_RRR1_MADD_Q_64_U:
7102 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7103 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7104 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7105 n, env);
7106 break;
7107 case OPC2_32_RRR1_MADD_Q_32_LL:
7108 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7109 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7110 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7111 break;
7112 case OPC2_32_RRR1_MADD_Q_64_LL:
7113 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7114 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7115 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7116 cpu_gpr_d[r3+1], temp, temp2, n);
7117 break;
7118 case OPC2_32_RRR1_MADD_Q_32_UU:
7119 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7120 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7121 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7122 break;
7123 case OPC2_32_RRR1_MADD_Q_64_UU:
7124 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7125 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7126 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7127 cpu_gpr_d[r3+1], temp, temp2, n);
7128 break;
7129 case OPC2_32_RRR1_MADDS_Q_32:
7130 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7131 cpu_gpr_d[r2], n, 32);
7132 break;
7133 case OPC2_32_RRR1_MADDS_Q_64:
7134 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7135 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7136 n);
7137 break;
7138 case OPC2_32_RRR1_MADDS_Q_32_L:
7139 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7140 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7141 temp, n, 16);
7142 break;
7143 case OPC2_32_RRR1_MADDS_Q_64_L:
7144 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7145 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7146 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7147 n);
7148 break;
7149 case OPC2_32_RRR1_MADDS_Q_32_U:
7150 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7151 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7152 temp, n, 16);
7153 break;
7154 case OPC2_32_RRR1_MADDS_Q_64_U:
7155 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7156 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7157 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7158 n);
7159 break;
7160 case OPC2_32_RRR1_MADDS_Q_32_LL:
7161 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7162 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7163 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7164 break;
7165 case OPC2_32_RRR1_MADDS_Q_64_LL:
7166 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7167 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7168 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7169 cpu_gpr_d[r3+1], temp, temp2, n);
7170 break;
7171 case OPC2_32_RRR1_MADDS_Q_32_UU:
7172 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7173 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7174 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7175 break;
7176 case OPC2_32_RRR1_MADDS_Q_64_UU:
7177 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7178 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7179 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7180 cpu_gpr_d[r3+1], temp, temp2, n);
7181 break;
7182 case OPC2_32_RRR1_MADDR_H_64_UL:
7183 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7184 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7185 break;
7186 case OPC2_32_RRR1_MADDRS_H_64_UL:
7187 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7188 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7189 break;
7190 case OPC2_32_RRR1_MADDR_Q_32_LL:
7191 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7192 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7193 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7194 break;
7195 case OPC2_32_RRR1_MADDR_Q_32_UU:
7196 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7197 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7198 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7199 break;
7200 case OPC2_32_RRR1_MADDRS_Q_32_LL:
7201 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7202 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7203 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7204 break;
7205 case OPC2_32_RRR1_MADDRS_Q_32_UU:
7206 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7207 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7208 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7209 break;
7210 }
7211 tcg_temp_free(temp);
7212 tcg_temp_free(temp2);
7213 }
7214
7215 static void decode_rrr1_maddsu_h(CPUTriCoreState *env, DisasContext *ctx)
7216 {
7217 uint32_t op2;
7218 uint32_t r1, r2, r3, r4, n;
7219
7220 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7221 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7222 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7223 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7224 r4 = MASK_OP_RRR1_D(ctx->opcode);
7225 n = MASK_OP_RRR1_N(ctx->opcode);
7226
7227 switch (op2) {
7228 case OPC2_32_RRR1_MADDSU_H_32_LL:
7229 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7230 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7231 break;
7232 case OPC2_32_RRR1_MADDSU_H_32_LU:
7233 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7234 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7235 break;
7236 case OPC2_32_RRR1_MADDSU_H_32_UL:
7237 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7238 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7239 break;
7240 case OPC2_32_RRR1_MADDSU_H_32_UU:
7241 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7242 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7243 break;
7244 case OPC2_32_RRR1_MADDSUS_H_32_LL:
7245 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7246 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7247 n, MODE_LL);
7248 break;
7249 case OPC2_32_RRR1_MADDSUS_H_32_LU:
7250 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7251 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7252 n, MODE_LU);
7253 break;
7254 case OPC2_32_RRR1_MADDSUS_H_32_UL:
7255 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7256 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7257 n, MODE_UL);
7258 break;
7259 case OPC2_32_RRR1_MADDSUS_H_32_UU:
7260 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7261 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7262 n, MODE_UU);
7263 break;
7264 case OPC2_32_RRR1_MADDSUM_H_64_LL:
7265 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7266 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7267 n, MODE_LL);
7268 break;
7269 case OPC2_32_RRR1_MADDSUM_H_64_LU:
7270 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7271 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7272 n, MODE_LU);
7273 break;
7274 case OPC2_32_RRR1_MADDSUM_H_64_UL:
7275 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7276 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7277 n, MODE_UL);
7278 break;
7279 case OPC2_32_RRR1_MADDSUM_H_64_UU:
7280 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7281 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7282 n, MODE_UU);
7283 break;
7284 case OPC2_32_RRR1_MADDSUMS_H_64_LL:
7285 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7286 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7287 n, MODE_LL);
7288 break;
7289 case OPC2_32_RRR1_MADDSUMS_H_64_LU:
7290 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7291 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7292 n, MODE_LU);
7293 break;
7294 case OPC2_32_RRR1_MADDSUMS_H_64_UL:
7295 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7296 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7297 n, MODE_UL);
7298 break;
7299 case OPC2_32_RRR1_MADDSUMS_H_64_UU:
7300 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7301 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7302 n, MODE_UU);
7303 break;
7304 case OPC2_32_RRR1_MADDSUR_H_16_LL:
7305 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7306 cpu_gpr_d[r2], n, MODE_LL);
7307 break;
7308 case OPC2_32_RRR1_MADDSUR_H_16_LU:
7309 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7310 cpu_gpr_d[r2], n, MODE_LU);
7311 break;
7312 case OPC2_32_RRR1_MADDSUR_H_16_UL:
7313 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7314 cpu_gpr_d[r2], n, MODE_UL);
7315 break;
7316 case OPC2_32_RRR1_MADDSUR_H_16_UU:
7317 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7318 cpu_gpr_d[r2], n, MODE_UU);
7319 break;
7320 case OPC2_32_RRR1_MADDSURS_H_16_LL:
7321 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7322 cpu_gpr_d[r2], n, MODE_LL);
7323 break;
7324 case OPC2_32_RRR1_MADDSURS_H_16_LU:
7325 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7326 cpu_gpr_d[r2], n, MODE_LU);
7327 break;
7328 case OPC2_32_RRR1_MADDSURS_H_16_UL:
7329 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7330 cpu_gpr_d[r2], n, MODE_UL);
7331 break;
7332 case OPC2_32_RRR1_MADDSURS_H_16_UU:
7333 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7334 cpu_gpr_d[r2], n, MODE_UU);
7335 break;
7336 }
7337 }
7338
7339 static void decode_rrr1_msub(CPUTriCoreState *env, DisasContext *ctx)
7340 {
7341 uint32_t op2;
7342 uint32_t r1, r2, r3, r4, n;
7343
7344 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7345 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7346 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7347 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7348 r4 = MASK_OP_RRR1_D(ctx->opcode);
7349 n = MASK_OP_RRR1_N(ctx->opcode);
7350
7351 switch (op2) {
7352 case OPC2_32_RRR1_MSUB_H_LL:
7353 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7354 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7355 break;
7356 case OPC2_32_RRR1_MSUB_H_LU:
7357 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7358 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7359 break;
7360 case OPC2_32_RRR1_MSUB_H_UL:
7361 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7362 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7363 break;
7364 case OPC2_32_RRR1_MSUB_H_UU:
7365 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7366 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7367 break;
7368 case OPC2_32_RRR1_MSUBS_H_LL:
7369 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7370 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7371 break;
7372 case OPC2_32_RRR1_MSUBS_H_LU:
7373 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7374 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7375 break;
7376 case OPC2_32_RRR1_MSUBS_H_UL:
7377 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7378 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7379 break;
7380 case OPC2_32_RRR1_MSUBS_H_UU:
7381 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7382 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7383 break;
7384 case OPC2_32_RRR1_MSUBM_H_LL:
7385 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7386 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7387 break;
7388 case OPC2_32_RRR1_MSUBM_H_LU:
7389 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7390 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7391 break;
7392 case OPC2_32_RRR1_MSUBM_H_UL:
7393 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7394 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7395 break;
7396 case OPC2_32_RRR1_MSUBM_H_UU:
7397 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7398 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7399 break;
7400 case OPC2_32_RRR1_MSUBMS_H_LL:
7401 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7402 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7403 break;
7404 case OPC2_32_RRR1_MSUBMS_H_LU:
7405 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7406 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7407 break;
7408 case OPC2_32_RRR1_MSUBMS_H_UL:
7409 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7410 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7411 break;
7412 case OPC2_32_RRR1_MSUBMS_H_UU:
7413 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7414 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7415 break;
7416 case OPC2_32_RRR1_MSUBR_H_LL:
7417 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7418 cpu_gpr_d[r2], n, MODE_LL);
7419 break;
7420 case OPC2_32_RRR1_MSUBR_H_LU:
7421 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7422 cpu_gpr_d[r2], n, MODE_LU);
7423 break;
7424 case OPC2_32_RRR1_MSUBR_H_UL:
7425 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7426 cpu_gpr_d[r2], n, MODE_UL);
7427 break;
7428 case OPC2_32_RRR1_MSUBR_H_UU:
7429 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7430 cpu_gpr_d[r2], n, MODE_UU);
7431 break;
7432 case OPC2_32_RRR1_MSUBRS_H_LL:
7433 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7434 cpu_gpr_d[r2], n, MODE_LL);
7435 break;
7436 case OPC2_32_RRR1_MSUBRS_H_LU:
7437 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7438 cpu_gpr_d[r2], n, MODE_LU);
7439 break;
7440 case OPC2_32_RRR1_MSUBRS_H_UL:
7441 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7442 cpu_gpr_d[r2], n, MODE_UL);
7443 break;
7444 case OPC2_32_RRR1_MSUBRS_H_UU:
7445 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7446 cpu_gpr_d[r2], n, MODE_UU);
7447 break;
7448 }
7449 }
7450
7451 static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx)
7452 {
7453 uint32_t op2;
7454 uint32_t r1, r2, r3, r4, n;
7455 TCGv temp, temp2;
7456
7457 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7458 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7459 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7460 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7461 r4 = MASK_OP_RRR1_D(ctx->opcode);
7462 n = MASK_OP_RRR1_N(ctx->opcode);
7463
7464 temp = tcg_const_i32(n);
7465 temp2 = tcg_temp_new();
7466
7467 switch (op2) {
7468 case OPC2_32_RRR1_MSUB_Q_32:
7469 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7470 cpu_gpr_d[r2], n, 32, env);
7471 break;
7472 case OPC2_32_RRR1_MSUB_Q_64:
7473 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7474 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7475 n, env);
7476 break;
7477 case OPC2_32_RRR1_MSUB_Q_32_L:
7478 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7479 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7480 temp, n, 16, env);
7481 break;
7482 case OPC2_32_RRR1_MSUB_Q_64_L:
7483 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7484 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7485 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7486 n, env);
7487 break;
7488 case OPC2_32_RRR1_MSUB_Q_32_U:
7489 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7490 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7491 temp, n, 16, env);
7492 break;
7493 case OPC2_32_RRR1_MSUB_Q_64_U:
7494 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7495 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7496 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7497 n, env);
7498 break;
7499 case OPC2_32_RRR1_MSUB_Q_32_LL:
7500 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7501 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7502 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7503 break;
7504 case OPC2_32_RRR1_MSUB_Q_64_LL:
7505 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7506 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7507 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7508 cpu_gpr_d[r3+1], temp, temp2, n);
7509 break;
7510 case OPC2_32_RRR1_MSUB_Q_32_UU:
7511 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7512 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7513 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7514 break;
7515 case OPC2_32_RRR1_MSUB_Q_64_UU:
7516 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7517 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7518 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7519 cpu_gpr_d[r3+1], temp, temp2, n);
7520 break;
7521 case OPC2_32_RRR1_MSUBS_Q_32:
7522 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7523 cpu_gpr_d[r2], n, 32);
7524 break;
7525 case OPC2_32_RRR1_MSUBS_Q_64:
7526 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7527 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7528 n);
7529 break;
7530 case OPC2_32_RRR1_MSUBS_Q_32_L:
7531 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7532 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7533 temp, n, 16);
7534 break;
7535 case OPC2_32_RRR1_MSUBS_Q_64_L:
7536 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7537 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7538 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7539 n);
7540 break;
7541 case OPC2_32_RRR1_MSUBS_Q_32_U:
7542 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7543 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7544 temp, n, 16);
7545 break;
7546 case OPC2_32_RRR1_MSUBS_Q_64_U:
7547 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7548 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7549 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7550 n);
7551 break;
7552 case OPC2_32_RRR1_MSUBS_Q_32_LL:
7553 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7554 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7555 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7556 break;
7557 case OPC2_32_RRR1_MSUBS_Q_64_LL:
7558 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7559 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7560 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7561 cpu_gpr_d[r3+1], temp, temp2, n);
7562 break;
7563 case OPC2_32_RRR1_MSUBS_Q_32_UU:
7564 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7565 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7566 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7567 break;
7568 case OPC2_32_RRR1_MSUBS_Q_64_UU:
7569 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7570 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7571 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7572 cpu_gpr_d[r3+1], temp, temp2, n);
7573 break;
7574 case OPC2_32_RRR1_MSUBR_H_64_UL:
7575 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7576 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7577 break;
7578 case OPC2_32_RRR1_MSUBRS_H_64_UL:
7579 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7580 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7581 break;
7582 case OPC2_32_RRR1_MSUBR_Q_32_LL:
7583 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7584 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7585 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7586 break;
7587 case OPC2_32_RRR1_MSUBR_Q_32_UU:
7588 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7589 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7590 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7591 break;
7592 case OPC2_32_RRR1_MSUBRS_Q_32_LL:
7593 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7594 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7595 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7596 break;
7597 case OPC2_32_RRR1_MSUBRS_Q_32_UU:
7598 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7599 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7600 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7601 break;
7602 }
7603 tcg_temp_free(temp);
7604 tcg_temp_free(temp2);
7605 }
7606
7607 static void decode_rrr1_msubad_h(CPUTriCoreState *env, DisasContext *ctx)
7608 {
7609 uint32_t op2;
7610 uint32_t r1, r2, r3, r4, n;
7611
7612 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7613 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7614 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7615 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7616 r4 = MASK_OP_RRR1_D(ctx->opcode);
7617 n = MASK_OP_RRR1_N(ctx->opcode);
7618
7619 switch (op2) {
7620 case OPC2_32_RRR1_MSUBAD_H_32_LL:
7621 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7622 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7623 break;
7624 case OPC2_32_RRR1_MSUBAD_H_32_LU:
7625 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7626 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7627 break;
7628 case OPC2_32_RRR1_MSUBAD_H_32_UL:
7629 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7630 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7631 break;
7632 case OPC2_32_RRR1_MSUBAD_H_32_UU:
7633 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7634 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7635 break;
7636 case OPC2_32_RRR1_MSUBADS_H_32_LL:
7637 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7638 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7639 n, MODE_LL);
7640 break;
7641 case OPC2_32_RRR1_MSUBADS_H_32_LU:
7642 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7643 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7644 n, MODE_LU);
7645 break;
7646 case OPC2_32_RRR1_MSUBADS_H_32_UL:
7647 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7648 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7649 n, MODE_UL);
7650 break;
7651 case OPC2_32_RRR1_MSUBADS_H_32_UU:
7652 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7653 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7654 n, MODE_UU);
7655 break;
7656 case OPC2_32_RRR1_MSUBADM_H_64_LL:
7657 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7658 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7659 n, MODE_LL);
7660 break;
7661 case OPC2_32_RRR1_MSUBADM_H_64_LU:
7662 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7663 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7664 n, MODE_LU);
7665 break;
7666 case OPC2_32_RRR1_MSUBADM_H_64_UL:
7667 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7668 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7669 n, MODE_UL);
7670 break;
7671 case OPC2_32_RRR1_MSUBADM_H_64_UU:
7672 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7673 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7674 n, MODE_UU);
7675 break;
7676 case OPC2_32_RRR1_MSUBADMS_H_64_LL:
7677 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7678 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7679 n, MODE_LL);
7680 break;
7681 case OPC2_32_RRR1_MSUBADMS_H_64_LU:
7682 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7683 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7684 n, MODE_LU);
7685 break;
7686 case OPC2_32_RRR1_MSUBADMS_H_64_UL:
7687 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7688 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7689 n, MODE_UL);
7690 break;
7691 case OPC2_32_RRR1_MSUBADMS_H_64_UU:
7692 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7693 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7694 n, MODE_UU);
7695 break;
7696 case OPC2_32_RRR1_MSUBADR_H_16_LL:
7697 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7698 cpu_gpr_d[r2], n, MODE_LL);
7699 break;
7700 case OPC2_32_RRR1_MSUBADR_H_16_LU:
7701 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7702 cpu_gpr_d[r2], n, MODE_LU);
7703 break;
7704 case OPC2_32_RRR1_MSUBADR_H_16_UL:
7705 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7706 cpu_gpr_d[r2], n, MODE_UL);
7707 break;
7708 case OPC2_32_RRR1_MSUBADR_H_16_UU:
7709 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7710 cpu_gpr_d[r2], n, MODE_UU);
7711 break;
7712 case OPC2_32_RRR1_MSUBADRS_H_16_LL:
7713 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7714 cpu_gpr_d[r2], n, MODE_LL);
7715 break;
7716 case OPC2_32_RRR1_MSUBADRS_H_16_LU:
7717 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7718 cpu_gpr_d[r2], n, MODE_LU);
7719 break;
7720 case OPC2_32_RRR1_MSUBADRS_H_16_UL:
7721 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7722 cpu_gpr_d[r2], n, MODE_UL);
7723 break;
7724 case OPC2_32_RRR1_MSUBADRS_H_16_UU:
7725 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7726 cpu_gpr_d[r2], n, MODE_UU);
7727 break;
7728 }
7729 }
7730
7731 /* RRRR format */
7732 static void decode_rrrr_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
7733 {
7734 uint32_t op2;
7735 int r1, r2, r3, r4;
7736 TCGv tmp_width, tmp_pos;
7737
7738 r1 = MASK_OP_RRRR_S1(ctx->opcode);
7739 r2 = MASK_OP_RRRR_S2(ctx->opcode);
7740 r3 = MASK_OP_RRRR_S3(ctx->opcode);
7741 r4 = MASK_OP_RRRR_D(ctx->opcode);
7742 op2 = MASK_OP_RRRR_OP2(ctx->opcode);
7743
7744 tmp_pos = tcg_temp_new();
7745 tmp_width = tcg_temp_new();
7746
7747 switch (op2) {
7748 case OPC2_32_RRRR_DEXTR:
7749 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7750 if (r1 == r2) {
7751 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
7752 } else {
7753 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos);
7754 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
7755 tcg_gen_shr_tl(tmp_pos, cpu_gpr_d[r2], tmp_pos);
7756 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, tmp_pos);
7757 }
7758 break;
7759 case OPC2_32_RRRR_EXTR:
7760 case OPC2_32_RRRR_EXTR_U:
7761 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
7762 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7763 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width);
7764 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
7765 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
7766 tcg_gen_subfi_tl(tmp_width, 32, tmp_width);
7767 if (op2 == OPC2_32_RRRR_EXTR) {
7768 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
7769 } else {
7770 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
7771 }
7772 break;
7773 case OPC2_32_RRRR_INSERT:
7774 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
7775 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7776 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width,
7777 tmp_pos);
7778 break;
7779 }
7780 tcg_temp_free(tmp_pos);
7781 tcg_temp_free(tmp_width);
7782 }
7783
7784 /* RRRW format */
7785 static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
7786 {
7787 uint32_t op2;
7788 int r1, r2, r3, r4;
7789 int32_t width;
7790
7791 TCGv temp, temp2;
7792
7793 op2 = MASK_OP_RRRW_OP2(ctx->opcode);
7794 r1 = MASK_OP_RRRW_S1(ctx->opcode);
7795 r2 = MASK_OP_RRRW_S2(ctx->opcode);
7796 r3 = MASK_OP_RRRW_S3(ctx->opcode);
7797 r4 = MASK_OP_RRRW_D(ctx->opcode);
7798 width = MASK_OP_RRRW_WIDTH(ctx->opcode);
7799
7800 temp = tcg_temp_new();
7801
7802 switch (op2) {
7803 case OPC2_32_RRRW_EXTR:
7804 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7805 tcg_gen_addi_tl(temp, temp, width);
7806 tcg_gen_subfi_tl(temp, 32, temp);
7807 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
7808 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width);
7809 break;
7810 case OPC2_32_RRRW_EXTR_U:
7811 if (width == 0) {
7812 tcg_gen_movi_tl(cpu_gpr_d[r4], 0);
7813 } else {
7814 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7815 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
7816 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width));
7817 }
7818 break;
7819 case OPC2_32_RRRW_IMASK:
7820 temp2 = tcg_temp_new();
7821
7822 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7823 tcg_gen_movi_tl(temp2, (1 << width) - 1);
7824 tcg_gen_shl_tl(temp2, temp2, temp);
7825 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp);
7826 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2);
7827
7828 tcg_temp_free(temp2);
7829 break;
7830 case OPC2_32_RRRW_INSERT:
7831 temp2 = tcg_temp_new();
7832
7833 tcg_gen_movi_tl(temp, width);
7834 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f);
7835 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2);
7836
7837 tcg_temp_free(temp2);
7838 break;
7839 }
7840 tcg_temp_free(temp);
7841 }
7842
7843 /* SYS Format*/
7844 static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx)
7845 {
7846 uint32_t op2;
7847 uint32_t r1;
7848 TCGLabel *l1;
7849 TCGv tmp;
7850
7851 op2 = MASK_OP_SYS_OP2(ctx->opcode);
7852 r1 = MASK_OP_SYS_S1D(ctx->opcode);
7853
7854 switch (op2) {
7855 case OPC2_32_SYS_DEBUG:
7856 /* raise EXCP_DEBUG */
7857 break;
7858 case OPC2_32_SYS_DISABLE:
7859 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE);
7860 break;
7861 case OPC2_32_SYS_DSYNC:
7862 break;
7863 case OPC2_32_SYS_ENABLE:
7864 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE);
7865 break;
7866 case OPC2_32_SYS_ISYNC:
7867 break;
7868 case OPC2_32_SYS_NOP:
7869 break;
7870 case OPC2_32_SYS_RET:
7871 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
7872 break;
7873 case OPC2_32_SYS_FRET:
7874 gen_fret(ctx);
7875 break;
7876 case OPC2_32_SYS_RFE:
7877 gen_helper_rfe(cpu_env);
7878 tcg_gen_exit_tb(0);
7879 ctx->bstate = BS_BRANCH;
7880 break;
7881 case OPC2_32_SYS_RFM:
7882 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
7883 tmp = tcg_temp_new();
7884 l1 = gen_new_label();
7885
7886 tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR));
7887 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE);
7888 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1);
7889 gen_helper_rfm(cpu_env);
7890 gen_set_label(l1);
7891 tcg_gen_exit_tb(0);
7892 ctx->bstate = BS_BRANCH;
7893 tcg_temp_free(tmp);
7894 } else {
7895 /* generate privilege trap */
7896 }
7897 break;
7898 case OPC2_32_SYS_RSLCX:
7899 gen_helper_rslcx(cpu_env);
7900 break;
7901 case OPC2_32_SYS_SVLCX:
7902 gen_helper_svlcx(cpu_env);
7903 break;
7904 case OPC2_32_SYS_RESTORE:
7905 if (tricore_feature(env, TRICORE_FEATURE_16)) {
7906 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM ||
7907 (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) {
7908 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
7909 } /* else raise privilege trap */
7910 } /* else raise illegal opcode trap */
7911 break;
7912 case OPC2_32_SYS_TRAPSV:
7913 /* TODO: raise sticky overflow trap */
7914 break;
7915 case OPC2_32_SYS_TRAPV:
7916 /* TODO: raise overflow trap */
7917 break;
7918 }
7919 }
7920
7921 static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
7922 {
7923 int op1;
7924 int32_t r1, r2, r3;
7925 int32_t address, const16;
7926 int8_t b, const4;
7927 int32_t bpos;
7928 TCGv temp, temp2, temp3;
7929
7930 op1 = MASK_OP_MAJOR(ctx->opcode);
7931
7932 /* handle JNZ.T opcode only being 7 bit long */
7933 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) {
7934 op1 = OPCM_32_BRN_JTT;
7935 }
7936
7937 switch (op1) {
7938 /* ABS-format */
7939 case OPCM_32_ABS_LDW:
7940 decode_abs_ldw(env, ctx);
7941 break;
7942 case OPCM_32_ABS_LDB:
7943 decode_abs_ldb(env, ctx);
7944 break;
7945 case OPCM_32_ABS_LDMST_SWAP:
7946 decode_abs_ldst_swap(env, ctx);
7947 break;
7948 case OPCM_32_ABS_LDST_CONTEXT:
7949 decode_abs_ldst_context(env, ctx);
7950 break;
7951 case OPCM_32_ABS_STORE:
7952 decode_abs_store(env, ctx);
7953 break;
7954 case OPCM_32_ABS_STOREB_H:
7955 decode_abs_storeb_h(env, ctx);
7956 break;
7957 case OPC1_32_ABS_STOREQ:
7958 address = MASK_OP_ABS_OFF18(ctx->opcode);
7959 r1 = MASK_OP_ABS_S1D(ctx->opcode);
7960 temp = tcg_const_i32(EA_ABS_FORMAT(address));
7961 temp2 = tcg_temp_new();
7962
7963 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
7964 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
7965
7966 tcg_temp_free(temp2);
7967 tcg_temp_free(temp);
7968 break;
7969 case OPC1_32_ABS_LD_Q:
7970 address = MASK_OP_ABS_OFF18(ctx->opcode);
7971 r1 = MASK_OP_ABS_S1D(ctx->opcode);
7972 temp = tcg_const_i32(EA_ABS_FORMAT(address));
7973
7974 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
7975 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
7976
7977 tcg_temp_free(temp);
7978 break;
7979 case OPC1_32_ABS_LEA:
7980 address = MASK_OP_ABS_OFF18(ctx->opcode);
7981 r1 = MASK_OP_ABS_S1D(ctx->opcode);
7982 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
7983 break;
7984 /* ABSB-format */
7985 case OPC1_32_ABSB_ST_T:
7986 address = MASK_OP_ABS_OFF18(ctx->opcode);
7987 b = MASK_OP_ABSB_B(ctx->opcode);
7988 bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
7989
7990 temp = tcg_const_i32(EA_ABS_FORMAT(address));
7991 temp2 = tcg_temp_new();
7992
7993 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
7994 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
7995 tcg_gen_ori_tl(temp2, temp2, (b << bpos));
7996 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
7997
7998 tcg_temp_free(temp);
7999 tcg_temp_free(temp2);
8000 break;
8001 /* B-format */
8002 case OPC1_32_B_CALL:
8003 case OPC1_32_B_CALLA:
8004 case OPC1_32_B_FCALL:
8005 case OPC1_32_B_FCALLA:
8006 case OPC1_32_B_J:
8007 case OPC1_32_B_JA:
8008 case OPC1_32_B_JL:
8009 case OPC1_32_B_JLA:
8010 address = MASK_OP_B_DISP24_SEXT(ctx->opcode);
8011 gen_compute_branch(ctx, op1, 0, 0, 0, address);
8012 break;
8013 /* Bit-format */
8014 case OPCM_32_BIT_ANDACC:
8015 decode_bit_andacc(env, ctx);
8016 break;
8017 case OPCM_32_BIT_LOGICAL_T1:
8018 decode_bit_logical_t(env, ctx);
8019 break;
8020 case OPCM_32_BIT_INSERT:
8021 decode_bit_insert(env, ctx);
8022 break;
8023 case OPCM_32_BIT_LOGICAL_T2:
8024 decode_bit_logical_t2(env, ctx);
8025 break;
8026 case OPCM_32_BIT_ORAND:
8027 decode_bit_orand(env, ctx);
8028 break;
8029 case OPCM_32_BIT_SH_LOGIC1:
8030 decode_bit_sh_logic1(env, ctx);
8031 break;
8032 case OPCM_32_BIT_SH_LOGIC2:
8033 decode_bit_sh_logic2(env, ctx);
8034 break;
8035 /* BO Format */
8036 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE:
8037 decode_bo_addrmode_post_pre_base(env, ctx);
8038 break;
8039 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR:
8040 decode_bo_addrmode_bitreverse_circular(env, ctx);
8041 break;
8042 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE:
8043 decode_bo_addrmode_ld_post_pre_base(env, ctx);
8044 break;
8045 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR:
8046 decode_bo_addrmode_ld_bitreverse_circular(env, ctx);
8047 break;
8048 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE:
8049 decode_bo_addrmode_stctx_post_pre_base(env, ctx);
8050 break;
8051 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
8052 decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx);
8053 break;
8054 /* BOL-format */
8055 case OPC1_32_BOL_LD_A_LONGOFF:
8056 case OPC1_32_BOL_LD_W_LONGOFF:
8057 case OPC1_32_BOL_LEA_LONGOFF:
8058 case OPC1_32_BOL_ST_W_LONGOFF:
8059 case OPC1_32_BOL_ST_A_LONGOFF:
8060 case OPC1_32_BOL_LD_B_LONGOFF:
8061 case OPC1_32_BOL_LD_BU_LONGOFF:
8062 case OPC1_32_BOL_LD_H_LONGOFF:
8063 case OPC1_32_BOL_LD_HU_LONGOFF:
8064 case OPC1_32_BOL_ST_B_LONGOFF:
8065 case OPC1_32_BOL_ST_H_LONGOFF:
8066 decode_bol_opc(env, ctx, op1);
8067 break;
8068 /* BRC Format */
8069 case OPCM_32_BRC_EQ_NEQ:
8070 case OPCM_32_BRC_GE:
8071 case OPCM_32_BRC_JLT:
8072 case OPCM_32_BRC_JNE:
8073 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode);
8074 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode);
8075 r1 = MASK_OP_BRC_S1(ctx->opcode);
8076 gen_compute_branch(ctx, op1, r1, 0, const4, address);
8077 break;
8078 /* BRN Format */
8079 case OPCM_32_BRN_JTT:
8080 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode);
8081 r1 = MASK_OP_BRN_S1(ctx->opcode);
8082 gen_compute_branch(ctx, op1, r1, 0, 0, address);
8083 break;
8084 /* BRR Format */
8085 case OPCM_32_BRR_EQ_NEQ:
8086 case OPCM_32_BRR_ADDR_EQ_NEQ:
8087 case OPCM_32_BRR_GE:
8088 case OPCM_32_BRR_JLT:
8089 case OPCM_32_BRR_JNE:
8090 case OPCM_32_BRR_JNZ:
8091 case OPCM_32_BRR_LOOP:
8092 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode);
8093 r2 = MASK_OP_BRR_S2(ctx->opcode);
8094 r1 = MASK_OP_BRR_S1(ctx->opcode);
8095 gen_compute_branch(ctx, op1, r1, r2, 0, address);
8096 break;
8097 /* RC Format */
8098 case OPCM_32_RC_LOGICAL_SHIFT:
8099 decode_rc_logical_shift(env, ctx);
8100 break;
8101 case OPCM_32_RC_ACCUMULATOR:
8102 decode_rc_accumulator(env, ctx);
8103 break;
8104 case OPCM_32_RC_SERVICEROUTINE:
8105 decode_rc_serviceroutine(env, ctx);
8106 break;
8107 case OPCM_32_RC_MUL:
8108 decode_rc_mul(env, ctx);
8109 break;
8110 /* RCPW Format */
8111 case OPCM_32_RCPW_MASK_INSERT:
8112 decode_rcpw_insert(env, ctx);
8113 break;
8114 /* RCRR Format */
8115 case OPC1_32_RCRR_INSERT:
8116 r1 = MASK_OP_RCRR_S1(ctx->opcode);
8117 r2 = MASK_OP_RCRR_S3(ctx->opcode);
8118 r3 = MASK_OP_RCRR_D(ctx->opcode);
8119 const16 = MASK_OP_RCRR_CONST4(ctx->opcode);
8120 temp = tcg_const_i32(const16);
8121 temp2 = tcg_temp_new(); /* width*/
8122 temp3 = tcg_temp_new(); /* pos */
8123
8124 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
8125 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
8126
8127 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
8128
8129 tcg_temp_free(temp);
8130 tcg_temp_free(temp2);
8131 tcg_temp_free(temp3);
8132 break;
8133 /* RCRW Format */
8134 case OPCM_32_RCRW_MASK_INSERT:
8135 decode_rcrw_insert(env, ctx);
8136 break;
8137 /* RCR Format */
8138 case OPCM_32_RCR_COND_SELECT:
8139 decode_rcr_cond_select(env, ctx);
8140 break;
8141 case OPCM_32_RCR_MADD:
8142 decode_rcr_madd(env, ctx);
8143 break;
8144 case OPCM_32_RCR_MSUB:
8145 decode_rcr_msub(env, ctx);
8146 break;
8147 /* RLC Format */
8148 case OPC1_32_RLC_ADDI:
8149 case OPC1_32_RLC_ADDIH:
8150 case OPC1_32_RLC_ADDIH_A:
8151 case OPC1_32_RLC_MFCR:
8152 case OPC1_32_RLC_MOV:
8153 case OPC1_32_RLC_MOV_64:
8154 case OPC1_32_RLC_MOV_U:
8155 case OPC1_32_RLC_MOV_H:
8156 case OPC1_32_RLC_MOVH_A:
8157 case OPC1_32_RLC_MTCR:
8158 decode_rlc_opc(env, ctx, op1);
8159 break;
8160 /* RR Format */
8161 case OPCM_32_RR_ACCUMULATOR:
8162 decode_rr_accumulator(env, ctx);
8163 break;
8164 case OPCM_32_RR_LOGICAL_SHIFT:
8165 decode_rr_logical_shift(env, ctx);
8166 break;
8167 case OPCM_32_RR_ADDRESS:
8168 decode_rr_address(env, ctx);
8169 break;
8170 case OPCM_32_RR_IDIRECT:
8171 decode_rr_idirect(env, ctx);
8172 break;
8173 case OPCM_32_RR_DIVIDE:
8174 decode_rr_divide(env, ctx);
8175 break;
8176 /* RR1 Format */
8177 case OPCM_32_RR1_MUL:
8178 decode_rr1_mul(env, ctx);
8179 break;
8180 case OPCM_32_RR1_MULQ:
8181 decode_rr1_mulq(env, ctx);
8182 break;
8183 /* RR2 format */
8184 case OPCM_32_RR2_MUL:
8185 decode_rr2_mul(env, ctx);
8186 break;
8187 /* RRPW format */
8188 case OPCM_32_RRPW_EXTRACT_INSERT:
8189 decode_rrpw_extract_insert(env, ctx);
8190 break;
8191 case OPC1_32_RRPW_DEXTR:
8192 r1 = MASK_OP_RRPW_S1(ctx->opcode);
8193 r2 = MASK_OP_RRPW_S2(ctx->opcode);
8194 r3 = MASK_OP_RRPW_D(ctx->opcode);
8195 const16 = MASK_OP_RRPW_POS(ctx->opcode);
8196 if (r1 == r2) {
8197 tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16);
8198 } else {
8199 temp = tcg_temp_new();
8200 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16);
8201 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16);
8202 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
8203 tcg_temp_free(temp);
8204 }
8205 break;
8206 /* RRR Format */
8207 case OPCM_32_RRR_COND_SELECT:
8208 decode_rrr_cond_select(env, ctx);
8209 break;
8210 case OPCM_32_RRR_DIVIDE:
8211 decode_rrr_divide(env, ctx);
8212 /* RRR2 Format */
8213 case OPCM_32_RRR2_MADD:
8214 decode_rrr2_madd(env, ctx);
8215 break;
8216 case OPCM_32_RRR2_MSUB:
8217 decode_rrr2_msub(env, ctx);
8218 break;
8219 /* RRR1 format */
8220 case OPCM_32_RRR1_MADD:
8221 decode_rrr1_madd(env, ctx);
8222 break;
8223 case OPCM_32_RRR1_MADDQ_H:
8224 decode_rrr1_maddq_h(env, ctx);
8225 break;
8226 case OPCM_32_RRR1_MADDSU_H:
8227 decode_rrr1_maddsu_h(env, ctx);
8228 break;
8229 case OPCM_32_RRR1_MSUB_H:
8230 decode_rrr1_msub(env, ctx);
8231 break;
8232 case OPCM_32_RRR1_MSUB_Q:
8233 decode_rrr1_msubq_h(env, ctx);
8234 break;
8235 case OPCM_32_RRR1_MSUBAD_H:
8236 decode_rrr1_msubad_h(env, ctx);
8237 break;
8238 /* RRRR format */
8239 case OPCM_32_RRRR_EXTRACT_INSERT:
8240 decode_rrrr_extract_insert(env, ctx);
8241 /* RRRW format */
8242 case OPCM_32_RRRW_EXTRACT_INSERT:
8243 decode_rrrw_extract_insert(env, ctx);
8244 break;
8245 /* SYS format */
8246 case OPCM_32_SYS_INTERRUPTS:
8247 decode_sys_interrupts(env, ctx);
8248 break;
8249 case OPC1_32_SYS_RSTV:
8250 tcg_gen_movi_tl(cpu_PSW_V, 0);
8251 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V);
8252 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
8253 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V);
8254 break;
8255 }
8256 }
8257
8258 static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
8259 {
8260 /* 16-Bit Instruction */
8261 if ((ctx->opcode & 0x1) == 0) {
8262 ctx->next_pc = ctx->pc + 2;
8263 decode_16Bit_opc(env, ctx);
8264 /* 32-Bit Instruction */
8265 } else {
8266 ctx->next_pc = ctx->pc + 4;
8267 decode_32Bit_opc(env, ctx);
8268 }
8269 }
8270
8271 void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
8272 {
8273 TriCoreCPU *cpu = tricore_env_get_cpu(env);
8274 CPUState *cs = CPU(cpu);
8275 DisasContext ctx;
8276 target_ulong pc_start;
8277 int num_insns, max_insns;
8278
8279 num_insns = 0;
8280 max_insns = tb->cflags & CF_COUNT_MASK;
8281 if (max_insns == 0) {
8282 max_insns = CF_COUNT_MASK;
8283 }
8284 if (singlestep) {
8285 max_insns = 1;
8286 }
8287 if (max_insns > TCG_MAX_INSNS) {
8288 max_insns = TCG_MAX_INSNS;
8289 }
8290
8291 pc_start = tb->pc;
8292 ctx.pc = pc_start;
8293 ctx.saved_pc = -1;
8294 ctx.tb = tb;
8295 ctx.singlestep_enabled = cs->singlestep_enabled;
8296 ctx.bstate = BS_NONE;
8297 ctx.mem_idx = cpu_mmu_index(env, false);
8298
8299 tcg_clear_temp_count();
8300 gen_tb_start(tb);
8301 while (ctx.bstate == BS_NONE) {
8302 tcg_gen_insn_start(ctx.pc);
8303 num_insns++;
8304
8305 ctx.opcode = cpu_ldl_code(env, ctx.pc);
8306 decode_opc(env, &ctx, 0);
8307
8308 if (num_insns >= max_insns || tcg_op_buf_full()) {
8309 gen_save_pc(ctx.next_pc);
8310 tcg_gen_exit_tb(0);
8311 break;
8312 }
8313 ctx.pc = ctx.next_pc;
8314 }
8315
8316 gen_tb_end(tb, num_insns);
8317 tb->size = ctx.pc - pc_start;
8318 tb->icount = num_insns;
8319
8320 if (tcg_check_temp_count()) {
8321 printf("LEAK at %08x\n", env->PC);
8322 }
8323
8324 #ifdef DEBUG_DISAS
8325 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
8326 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8327 log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);
8328 qemu_log("\n");
8329 }
8330 #endif
8331 }
8332
8333 void
8334 restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb,
8335 target_ulong *data)
8336 {
8337 env->PC = data[0];
8338 }
8339 /*
8340 *
8341 * Initialization
8342 *
8343 */
8344
8345 void cpu_state_reset(CPUTriCoreState *env)
8346 {
8347 /* Reset Regs to Default Value */
8348 env->PSW = 0xb80;
8349 }
8350
8351 static void tricore_tcg_init_csfr(void)
8352 {
8353 cpu_PCXI = tcg_global_mem_new(cpu_env,
8354 offsetof(CPUTriCoreState, PCXI), "PCXI");
8355 cpu_PSW = tcg_global_mem_new(cpu_env,
8356 offsetof(CPUTriCoreState, PSW), "PSW");
8357 cpu_PC = tcg_global_mem_new(cpu_env,
8358 offsetof(CPUTriCoreState, PC), "PC");
8359 cpu_ICR = tcg_global_mem_new(cpu_env,
8360 offsetof(CPUTriCoreState, ICR), "ICR");
8361 }
8362
8363 void tricore_tcg_init(void)
8364 {
8365 int i;
8366 static int inited;
8367 if (inited) {
8368 return;
8369 }
8370 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
8371 /* reg init */
8372 for (i = 0 ; i < 16 ; i++) {
8373 cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
8374 offsetof(CPUTriCoreState, gpr_a[i]),
8375 regnames_a[i]);
8376 }
8377 for (i = 0 ; i < 16 ; i++) {
8378 cpu_gpr_d[i] = tcg_global_mem_new(cpu_env,
8379 offsetof(CPUTriCoreState, gpr_d[i]),
8380 regnames_d[i]);
8381 }
8382 tricore_tcg_init_csfr();
8383 /* init PSW flag cache */
8384 cpu_PSW_C = tcg_global_mem_new(cpu_env,
8385 offsetof(CPUTriCoreState, PSW_USB_C),
8386 "PSW_C");
8387 cpu_PSW_V = tcg_global_mem_new(cpu_env,
8388 offsetof(CPUTriCoreState, PSW_USB_V),
8389 "PSW_V");
8390 cpu_PSW_SV = tcg_global_mem_new(cpu_env,
8391 offsetof(CPUTriCoreState, PSW_USB_SV),
8392 "PSW_SV");
8393 cpu_PSW_AV = tcg_global_mem_new(cpu_env,
8394 offsetof(CPUTriCoreState, PSW_USB_AV),
8395 "PSW_AV");
8396 cpu_PSW_SAV = tcg_global_mem_new(cpu_env,
8397 offsetof(CPUTriCoreState, PSW_USB_SAV),
8398 "PSW_SAV");
8399 }
AR7 emulation for QEMU