target-arm/helper.c

   1 #include "qemu/osdep.h"
   2 #include "cpu.h"
   3 #include "internals.h"
   4 #include "exec/gdbstub.h"
   5 #include "exec/helper-proto.h"
   6 #include "qemu/host-utils.h"
   7 #include "sysemu/arch_init.h"
   8 #include "sysemu/sysemu.h"
   9 #include "qemu/bitops.h"
  10 #include "qemu/crc32c.h"
  11 #include "exec/cpu_ldst.h"
  12 #include "arm_ldst.h"
  13 #include <zlib.h> /* For crc32 */
  14 #include "exec/semihost.h"
  15 #include "sysemu/kvm.h"
  16
  17 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
  18
  19 #ifndef CONFIG_USER_ONLY
  20 static bool get_phys_addr(CPUARMState *env, target_ulong address,
  21                           int access_type, ARMMMUIdx mmu_idx,
  22                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
  23                           target_ulong *page_size, uint32_t *fsr,
  24                           ARMMMUFaultInfo *fi);
  25
  26 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
  27                                int access_type, ARMMMUIdx mmu_idx,
  28                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
  29                                target_ulong *page_size_ptr, uint32_t *fsr,
  30                                ARMMMUFaultInfo *fi);
  31
  32 /* Definitions for the PMCCNTR and PMCR registers */
  33 #define PMCRD   0x8
  34 #define PMCRC   0x4
  35 #define PMCRE   0x1
  36 #endif
  37
  38 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  39 {
  40     int nregs;
  41
  42     /* VFP data registers are always little-endian.  */
  43     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  44     if (reg < nregs) {
  45         stfq_le_p(buf, env->vfp.regs[reg]);
  46         return 8;
  47     }
  48     if (arm_feature(env, ARM_FEATURE_NEON)) {
  49         /* Aliases for Q regs.  */
  50         nregs += 16;
  51         if (reg < nregs) {
  52             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  53             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  54             return 16;
  55         }
  56     }
  57     switch (reg - nregs) {
  58     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  59     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  60     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  61     }
  62     return 0;
  63 }
  64
  65 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  66 {
  67     int nregs;
  68
  69     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  70     if (reg < nregs) {
  71         env->vfp.regs[reg] = ldfq_le_p(buf);
  72         return 8;
  73     }
  74     if (arm_feature(env, ARM_FEATURE_NEON)) {
  75         nregs += 16;
  76         if (reg < nregs) {
  77             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  78             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  79             return 16;
  80         }
  81     }
  82     switch (reg - nregs) {
  83     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  84     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  85     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  86     }
  87     return 0;
  88 }
  89
  90 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  91 {
  92     switch (reg) {
  93     case 0 ... 31:
  94         /* 128 bit FP register */
  95         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  96         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  97         return 16;
  98     case 32:
  99         /* FPSR */
 100         stl_p(buf, vfp_get_fpsr(env));
 101         return 4;
 102     case 33:
 103         /* FPCR */
 104         stl_p(buf, vfp_get_fpcr(env));
 105         return 4;
 106     default:
 107         return 0;
 108     }
 109 }
 110
 111 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 112 {
 113     switch (reg) {
 114     case 0 ... 31:
 115         /* 128 bit FP register */
 116         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 117         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 118         return 16;
 119     case 32:
 120         /* FPSR */
 121         vfp_set_fpsr(env, ldl_p(buf));
 122         return 4;
 123     case 33:
 124         /* FPCR */
 125         vfp_set_fpcr(env, ldl_p(buf));
 126         return 4;
 127     default:
 128         return 0;
 129     }
 130 }
 131
 132 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 133 {
 134     assert(ri->fieldoffset);
 135     if (cpreg_field_is_64bit(ri)) {
 136         return CPREG_FIELD64(env, ri);
 137     } else {
 138         return CPREG_FIELD32(env, ri);
 139     }
 140 }
 141
 142 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 143                       uint64_t value)
 144 {
 145     assert(ri->fieldoffset);
 146     if (cpreg_field_is_64bit(ri)) {
 147         CPREG_FIELD64(env, ri) = value;
 148     } else {
 149         CPREG_FIELD32(env, ri) = value;
 150     }
 151 }
 152
 153 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
 154 {
 155     return (char *)env + ri->fieldoffset;
 156 }
 157
 158 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 159 {
 160     /* Raw read of a coprocessor register (as needed for migration, etc). */
 161     if (ri->type & ARM_CP_CONST) {
 162         return ri->resetvalue;
 163     } else if (ri->raw_readfn) {
 164         return ri->raw_readfn(env, ri);
 165     } else if (ri->readfn) {
 166         return ri->readfn(env, ri);
 167     } else {
 168         return raw_read(env, ri);
 169     }
 170 }
 171
 172 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 173                              uint64_t v)
 174 {
 175     /* Raw write of a coprocessor register (as needed for migration, etc).
 176      * Note that constant registers are treated as write-ignored; the
 177      * caller should check for success by whether a readback gives the
 178      * value written.
 179      */
 180     if (ri->type & ARM_CP_CONST) {
 181         return;
 182     } else if (ri->raw_writefn) {
 183         ri->raw_writefn(env, ri, v);
 184     } else if (ri->writefn) {
 185         ri->writefn(env, ri, v);
 186     } else {
 187         raw_write(env, ri, v);
 188     }
 189 }
 190
 191 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
 192 {
 193    /* Return true if the regdef would cause an assertion if you called
 194     * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
 195     * program bug for it not to have the NO_RAW flag).
 196     * NB that returning false here doesn't necessarily mean that calling
 197     * read/write_raw_cp_reg() is safe, because we can't distinguish "has
 198     * read/write access functions which are safe for raw use" from "has
 199     * read/write access functions which have side effects but has forgotten
 200     * to provide raw access functions".
 201     * The tests here line up with the conditions in read/write_raw_cp_reg()
 202     * and assertions in raw_read()/raw_write().
 203     */
 204     if ((ri->type & ARM_CP_CONST) ||
 205         ri->fieldoffset ||
 206         ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
 207         return false;
 208     }
 209     return true;
 210 }
 211
 212 bool write_cpustate_to_list(ARMCPU *cpu)
 213 {
 214     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 215     int i;
 216     bool ok = true;
 217
 218     for (i = 0; i < cpu->cpreg_array_len; i++) {
 219         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 220         const ARMCPRegInfo *ri;
 221
 222         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 223         if (!ri) {
 224             ok = false;
 225             continue;
 226         }
 227         if (ri->type & ARM_CP_NO_RAW) {
 228             continue;
 229         }
 230         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 231     }
 232     return ok;
 233 }
 234
 235 bool write_list_to_cpustate(ARMCPU *cpu)
 236 {
 237     int i;
 238     bool ok = true;
 239
 240     for (i = 0; i < cpu->cpreg_array_len; i++) {
 241         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 242         uint64_t v = cpu->cpreg_values[i];
 243         const ARMCPRegInfo *ri;
 244
 245         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 246         if (!ri) {
 247             ok = false;
 248             continue;
 249         }
 250         if (ri->type & ARM_CP_NO_RAW) {
 251             continue;
 252         }
 253         /* Write value and confirm it reads back as written
 254          * (to catch read-only registers and partially read-only
 255          * registers where the incoming migration value doesn't match)
 256          */
 257         write_raw_cp_reg(&cpu->env, ri, v);
 258         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 259             ok = false;
 260         }
 261     }
 262     return ok;
 263 }
 264
 265 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 266 {
 267     ARMCPU *cpu = opaque;
 268     uint64_t regidx;
 269     const ARMCPRegInfo *ri;
 270
 271     regidx = *(uint32_t *)key;
 272     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 273
 274     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 275         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 276         /* The value array need not be initialized at this point */
 277         cpu->cpreg_array_len++;
 278     }
 279 }
 280
 281 static void count_cpreg(gpointer key, gpointer opaque)
 282 {
 283     ARMCPU *cpu = opaque;
 284     uint64_t regidx;
 285     const ARMCPRegInfo *ri;
 286
 287     regidx = *(uint32_t *)key;
 288     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 289
 290     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 291         cpu->cpreg_array_len++;
 292     }
 293 }
 294
 295 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 296 {
 297     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 298     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 299
 300     if (aidx > bidx) {
 301         return 1;
 302     }
 303     if (aidx < bidx) {
 304         return -1;
 305     }
 306     return 0;
 307 }
 308
 309 void init_cpreg_list(ARMCPU *cpu)
 310 {
 311     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 312      * Note that we require cpreg_tuples[] to be sorted by key ID.
 313      */
 314     GList *keys;
 315     int arraylen;
 316
 317     keys = g_hash_table_get_keys(cpu->cp_regs);
 318     keys = g_list_sort(keys, cpreg_key_compare);
 319
 320     cpu->cpreg_array_len = 0;
 321
 322     g_list_foreach(keys, count_cpreg, cpu);
 323
 324     arraylen = cpu->cpreg_array_len;
 325     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 326     cpu->cpreg_values = g_new(uint64_t, arraylen);
 327     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 328     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 329     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 330     cpu->cpreg_array_len = 0;
 331
 332     g_list_foreach(keys, add_cpreg_to_list, cpu);
 333
 334     assert(cpu->cpreg_array_len == arraylen);
 335
 336     g_list_free(keys);
 337 }
 338
 339 /*
 340  * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
 341  * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
 342  *
 343  * access_el3_aa32ns: Used to check AArch32 register views.
 344  * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
 345  */
 346 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
 347                                         const ARMCPRegInfo *ri,
 348                                         bool isread)
 349 {
 350     bool secure = arm_is_secure_below_el3(env);
 351
 352     assert(!arm_el_is_aa64(env, 3));
 353     if (secure) {
 354         return CP_ACCESS_TRAP_UNCATEGORIZED;
 355     }
 356     return CP_ACCESS_OK;
 357 }
 358
 359 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
 360                                                 const ARMCPRegInfo *ri,
 361                                                 bool isread)
 362 {
 363     if (!arm_el_is_aa64(env, 3)) {
 364         return access_el3_aa32ns(env, ri, isread);
 365     }
 366     return CP_ACCESS_OK;
 367 }
 368
 369 /* Some secure-only AArch32 registers trap to EL3 if used from
 370  * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
 371  * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
 372  * We assume that the .access field is set to PL1_RW.
 373  */
 374 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
 375                                             const ARMCPRegInfo *ri,
 376                                             bool isread)
 377 {
 378     if (arm_current_el(env) == 3) {
 379         return CP_ACCESS_OK;
 380     }
 381     if (arm_is_secure_below_el3(env)) {
 382         return CP_ACCESS_TRAP_EL3;
 383     }
 384     /* This will be EL1 NS and EL2 NS, which just UNDEF */
 385     return CP_ACCESS_TRAP_UNCATEGORIZED;
 386 }
 387
 388 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 389 {
 390     ARMCPU *cpu = arm_env_get_cpu(env);
 391
 392     raw_write(env, ri, value);
 393     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 394 }
 395
 396 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 397 {
 398     ARMCPU *cpu = arm_env_get_cpu(env);
 399
 400     if (raw_read(env, ri) != value) {
 401         /* Unlike real hardware the qemu TLB uses virtual addresses,
 402          * not modified virtual addresses, so this causes a TLB flush.
 403          */
 404         tlb_flush(CPU(cpu), 1);
 405         raw_write(env, ri, value);
 406     }
 407 }
 408
 409 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 410                              uint64_t value)
 411 {
 412     ARMCPU *cpu = arm_env_get_cpu(env);
 413
 414     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 415         && !extended_addresses_enabled(env)) {
 416         /* For VMSA (when not using the LPAE long descriptor page table
 417          * format) this register includes the ASID, so do a TLB flush.
 418          * For PMSA it is purely a process ID and no action is needed.
 419          */
 420         tlb_flush(CPU(cpu), 1);
 421     }
 422     raw_write(env, ri, value);
 423 }
 424
 425 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 426                           uint64_t value)
 427 {
 428     /* Invalidate all (TLBIALL) */
 429     ARMCPU *cpu = arm_env_get_cpu(env);
 430
 431     tlb_flush(CPU(cpu), 1);
 432 }
 433
 434 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 435                           uint64_t value)
 436 {
 437     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 438     ARMCPU *cpu = arm_env_get_cpu(env);
 439
 440     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 441 }
 442
 443 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 444                            uint64_t value)
 445 {
 446     /* Invalidate by ASID (TLBIASID) */
 447     ARMCPU *cpu = arm_env_get_cpu(env);
 448
 449     tlb_flush(CPU(cpu), value == 0);
 450 }
 451
 452 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 453                            uint64_t value)
 454 {
 455     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 456     ARMCPU *cpu = arm_env_get_cpu(env);
 457
 458     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 459 }
 460
 461 /* IS variants of TLB operations must affect all cores */
 462 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 463                              uint64_t value)
 464 {
 465     CPUState *other_cs;
 466
 467     CPU_FOREACH(other_cs) {
 468         tlb_flush(other_cs, 1);
 469     }
 470 }
 471
 472 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 473                              uint64_t value)
 474 {
 475     CPUState *other_cs;
 476
 477     CPU_FOREACH(other_cs) {
 478         tlb_flush(other_cs, value == 0);
 479     }
 480 }
 481
 482 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 483                              uint64_t value)
 484 {
 485     CPUState *other_cs;
 486
 487     CPU_FOREACH(other_cs) {
 488         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 489     }
 490 }
 491
 492 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 493                              uint64_t value)
 494 {
 495     CPUState *other_cs;
 496
 497     CPU_FOREACH(other_cs) {
 498         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 499     }
 500 }
 501
 502 static const ARMCPRegInfo cp_reginfo[] = {
 503     /* Define the secure and non-secure FCSE identifier CP registers
 504      * separately because there is no secure bank in V8 (no _EL3).  This allows
 505      * the secure register to be properly reset and migrated. There is also no
 506      * v8 EL1 version of the register so the non-secure instance stands alone.
 507      */
 508     { .name = "FCSEIDR(NS)",
 509       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 510       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 511       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
 512       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 513     { .name = "FCSEIDR(S)",
 514       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 515       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 516       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
 517       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 518     /* Define the secure and non-secure context identifier CP registers
 519      * separately because there is no secure bank in V8 (no _EL3).  This allows
 520      * the secure register to be properly reset and migrated.  In the
 521      * non-secure case, the 32-bit register will have reset and migration
 522      * disabled during registration as it is handled by the 64-bit instance.
 523      */
 524     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
 525       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 526       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 527       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
 528       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 529     { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
 530       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 531       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 532       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
 533       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 534     REGINFO_SENTINEL
 535 };
 536
 537 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 538     /* NB: Some of these registers exist in v8 but with more precise
 539      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 540      */
 541     /* MMU Domain access control / MPU write buffer control */
 542     { .name = "DACR",
 543       .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
 544       .access = PL1_RW, .resetvalue = 0,
 545       .writefn = dacr_write, .raw_writefn = raw_write,
 546       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
 547                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
 548     /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
 549      * For v6 and v5, these mappings are overly broad.
 550      */
 551     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
 552       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 553     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
 554       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 555     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
 556       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 557     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
 558       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 559     /* Cache maintenance ops; some of this space may be overridden later. */
 560     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 561       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 562       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 563     REGINFO_SENTINEL
 564 };
 565
 566 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 567     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 568      * over-broad.
 569      */
 570     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 571       .access = PL1_W, .type = ARM_CP_WFI },
 572     REGINFO_SENTINEL
 573 };
 574
 575 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 576     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 577      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 578      */
 579     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 580       .access = PL1_W, .type = ARM_CP_WFI },
 581     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 582      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 583      * OMAPCP will override this space.
 584      */
 585     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 586       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 587       .resetvalue = 0 },
 588     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 589       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 590       .resetvalue = 0 },
 591     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 592     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 593       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
 594       .resetvalue = 0 },
 595     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 596      * implementing it as RAZ means the "debug architecture version" bits
 597      * will read as a reserved value, which should cause Linux to not try
 598      * to use the debug hardware.
 599      */
 600     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 601       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 602     /* MMU TLB control. Note that the wildcarding means we cover not just
 603      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 604      */
 605     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 606       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 607       .type = ARM_CP_NO_RAW },
 608     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 609       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 610       .type = ARM_CP_NO_RAW },
 611     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 612       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 613       .type = ARM_CP_NO_RAW },
 614     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 615       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 616       .type = ARM_CP_NO_RAW },
 617     { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
 618       .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
 619     { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
 620       .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
 621     REGINFO_SENTINEL
 622 };
 623
 624 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 625                         uint64_t value)
 626 {
 627     uint32_t mask = 0;
 628
 629     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 630     if (!arm_feature(env, ARM_FEATURE_V8)) {
 631         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 632          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 633          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 634          */
 635         if (arm_feature(env, ARM_FEATURE_VFP)) {
 636             /* VFP coprocessor: cp10 & cp11 [23:20] */
 637             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 638
 639             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 640                 /* ASEDIS [31] bit is RAO/WI */
 641                 value |= (1 << 31);
 642             }
 643
 644             /* VFPv3 and upwards with NEON implement 32 double precision
 645              * registers (D0-D31).
 646              */
 647             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 648                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 649                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 650                 value |= (1 << 30);
 651             }
 652         }
 653         value &= mask;
 654     }
 655     env->cp15.cpacr_el1 = value;
 656 }
 657
 658 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
 659                                    bool isread)
 660 {
 661     if (arm_feature(env, ARM_FEATURE_V8)) {
 662         /* Check if CPACR accesses are to be trapped to EL2 */
 663         if (arm_current_el(env) == 1 &&
 664             (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
 665             return CP_ACCESS_TRAP_EL2;
 666         /* Check if CPACR accesses are to be trapped to EL3 */
 667         } else if (arm_current_el(env) < 3 &&
 668                    (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 669             return CP_ACCESS_TRAP_EL3;
 670         }
 671     }
 672
 673     return CP_ACCESS_OK;
 674 }
 675
 676 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri,
 677                                   bool isread)
 678 {
 679     /* Check if CPTR accesses are set to trap to EL3 */
 680     if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 681         return CP_ACCESS_TRAP_EL3;
 682     }
 683
 684     return CP_ACCESS_OK;
 685 }
 686
 687 static const ARMCPRegInfo v6_cp_reginfo[] = {
 688     /* prefetch by MVA in v6, NOP in v7 */
 689     { .name = "MVA_prefetch",
 690       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 691       .access = PL1_W, .type = ARM_CP_NOP },
 692     /* We need to break the TB after ISB to execute self-modifying code
 693      * correctly and also to take any pending interrupts immediately.
 694      * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
 695      */
 696     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 697       .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
 698     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 699       .access = PL0_W, .type = ARM_CP_NOP },
 700     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 701       .access = PL0_W, .type = ARM_CP_NOP },
 702     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 703       .access = PL1_RW,
 704       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
 705                              offsetof(CPUARMState, cp15.ifar_ns) },
 706       .resetvalue = 0, },
 707     /* Watchpoint Fault Address Register : should actually only be present
 708      * for 1136, 1176, 11MPCore.
 709      */
 710     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 711       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 712     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 713       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
 714       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
 715       .resetvalue = 0, .writefn = cpacr_write },
 716     REGINFO_SENTINEL
 717 };
 718
 719 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
 720                                    bool isread)
 721 {
 722     /* Performance monitor registers user accessibility is controlled
 723      * by PMUSERENR.
 724      */
 725     if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) {
 726         return CP_ACCESS_TRAP;
 727     }
 728     return CP_ACCESS_OK;
 729 }
 730
 731 #ifndef CONFIG_USER_ONLY
 732
 733 static inline bool arm_ccnt_enabled(CPUARMState *env)
 734 {
 735     /* This does not support checking PMCCFILTR_EL0 register */
 736
 737     if (!(env->cp15.c9_pmcr & PMCRE)) {
 738         return false;
 739     }
 740
 741     return true;
 742 }
 743
 744 void pmccntr_sync(CPUARMState *env)
 745 {
 746     uint64_t temp_ticks;
 747
 748     temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 749                           ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 750
 751     if (env->cp15.c9_pmcr & PMCRD) {
 752         /* Increment once every 64 processor clock cycles */
 753         temp_ticks /= 64;
 754     }
 755
 756     if (arm_ccnt_enabled(env)) {
 757         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 758     }
 759 }
 760
 761 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 762                        uint64_t value)
 763 {
 764     pmccntr_sync(env);
 765
 766     if (value & PMCRC) {
 767         /* The counter has been reset */
 768         env->cp15.c15_ccnt = 0;
 769     }
 770
 771     /* only the DP, X, D and E bits are writable */
 772     env->cp15.c9_pmcr &= ~0x39;
 773     env->cp15.c9_pmcr |= (value & 0x39);
 774
 775     pmccntr_sync(env);
 776 }
 777
 778 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 779 {
 780     uint64_t total_ticks;
 781
 782     if (!arm_ccnt_enabled(env)) {
 783         /* Counter is disabled, do not change value */
 784         return env->cp15.c15_ccnt;
 785     }
 786
 787     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 788                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 789
 790     if (env->cp15.c9_pmcr & PMCRD) {
 791         /* Increment once every 64 processor clock cycles */
 792         total_ticks /= 64;
 793     }
 794     return total_ticks - env->cp15.c15_ccnt;
 795 }
 796
 797 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 798                         uint64_t value)
 799 {
 800     uint64_t total_ticks;
 801
 802     if (!arm_ccnt_enabled(env)) {
 803         /* Counter is disabled, set the absolute value */
 804         env->cp15.c15_ccnt = value;
 805         return;
 806     }
 807
 808     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 809                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 810
 811     if (env->cp15.c9_pmcr & PMCRD) {
 812         /* Increment once every 64 processor clock cycles */
 813         total_ticks /= 64;
 814     }
 815     env->cp15.c15_ccnt = total_ticks - value;
 816 }
 817
 818 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 819                             uint64_t value)
 820 {
 821     uint64_t cur_val = pmccntr_read(env, NULL);
 822
 823     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 824 }
 825
 826 #else /* CONFIG_USER_ONLY */
 827
 828 void pmccntr_sync(CPUARMState *env)
 829 {
 830 }
 831
 832 #endif
 833
 834 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 835                             uint64_t value)
 836 {
 837     pmccntr_sync(env);
 838     env->cp15.pmccfiltr_el0 = value & 0x7E000000;
 839     pmccntr_sync(env);
 840 }
 841
 842 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 843                             uint64_t value)
 844 {
 845     value &= (1 << 31);
 846     env->cp15.c9_pmcnten |= value;
 847 }
 848
 849 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 850                              uint64_t value)
 851 {
 852     value &= (1 << 31);
 853     env->cp15.c9_pmcnten &= ~value;
 854 }
 855
 856 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 857                          uint64_t value)
 858 {
 859     env->cp15.c9_pmovsr &= ~value;
 860 }
 861
 862 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 863                              uint64_t value)
 864 {
 865     env->cp15.c9_pmxevtyper = value & 0xff;
 866 }
 867
 868 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 869                             uint64_t value)
 870 {
 871     env->cp15.c9_pmuserenr = value & 1;
 872 }
 873
 874 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 875                              uint64_t value)
 876 {
 877     /* We have no event counters so only the C bit can be changed */
 878     value &= (1 << 31);
 879     env->cp15.c9_pminten |= value;
 880 }
 881
 882 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 883                              uint64_t value)
 884 {
 885     value &= (1 << 31);
 886     env->cp15.c9_pminten &= ~value;
 887 }
 888
 889 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 890                        uint64_t value)
 891 {
 892     /* Note that even though the AArch64 view of this register has bits
 893      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 894      * architectural requirements for bits which are RES0 only in some
 895      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 896      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 897      */
 898     raw_write(env, ri, value & ~0x1FULL);
 899 }
 900
 901 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 902 {
 903     /* We only mask off bits that are RES0 both for AArch64 and AArch32.
 904      * For bits that vary between AArch32/64, code needs to check the
 905      * current execution mode before directly using the feature bit.
 906      */
 907     uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
 908
 909     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 910         valid_mask &= ~SCR_HCE;
 911
 912         /* On ARMv7, SMD (or SCD as it is called in v7) is only
 913          * supported if EL2 exists. The bit is UNK/SBZP when
 914          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
 915          * when EL2 is unavailable.
 916          * On ARMv8, this bit is always available.
 917          */
 918         if (arm_feature(env, ARM_FEATURE_V7) &&
 919             !arm_feature(env, ARM_FEATURE_V8)) {
 920             valid_mask &= ~SCR_SMD;
 921         }
 922     }
 923
 924     /* Clear all-context RES0 bits.  */
 925     value &= valid_mask;
 926     raw_write(env, ri, value);
 927 }
 928
 929 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 930 {
 931     ARMCPU *cpu = arm_env_get_cpu(env);
 932
 933     /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
 934      * bank
 935      */
 936     uint32_t index = A32_BANKED_REG_GET(env, csselr,
 937                                         ri->secure & ARM_CP_SECSTATE_S);
 938
 939     return cpu->ccsidr[index];
 940 }
 941
 942 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 943                          uint64_t value)
 944 {
 945     raw_write(env, ri, value & 0xf);
 946 }
 947
 948 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 949 {
 950     CPUState *cs = ENV_GET_CPU(env);
 951     uint64_t ret = 0;
 952
 953     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 954         ret |= CPSR_I;
 955     }
 956     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
 957         ret |= CPSR_F;
 958     }
 959     /* External aborts are not possible in QEMU so A bit is always clear */
 960     return ret;
 961 }
 962
 963 static const ARMCPRegInfo v7_cp_reginfo[] = {
 964     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 965     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 966       .access = PL1_W, .type = ARM_CP_NOP },
 967     /* Performance monitors are implementation defined in v7,
 968      * but with an ARM recommended set of registers, which we
 969      * follow (although we don't actually implement any counters)
 970      *
 971      * Performance registers fall into three categories:
 972      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 973      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 974      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 975      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 976      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 977      */
 978     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 979       .access = PL0_RW, .type = ARM_CP_ALIAS,
 980       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 981       .writefn = pmcntenset_write,
 982       .accessfn = pmreg_access,
 983       .raw_writefn = raw_write },
 984     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
 985       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
 986       .access = PL0_RW, .accessfn = pmreg_access,
 987       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
 988       .writefn = pmcntenset_write, .raw_writefn = raw_write },
 989     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 990       .access = PL0_RW,
 991       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 992       .accessfn = pmreg_access,
 993       .writefn = pmcntenclr_write,
 994       .type = ARM_CP_ALIAS },
 995     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
 996       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
 997       .access = PL0_RW, .accessfn = pmreg_access,
 998       .type = ARM_CP_ALIAS,
 999       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
1000       .writefn = pmcntenclr_write },
1001     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
1002       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
1003       .accessfn = pmreg_access,
1004       .writefn = pmovsr_write,
1005       .raw_writefn = raw_write },
1006     /* Unimplemented so WI. */
1007     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
1008       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
1009     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
1010      * We choose to RAZ/WI.
1011      */
1012     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
1013       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1014       .accessfn = pmreg_access },
1015 #ifndef CONFIG_USER_ONLY
1016     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
1017       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
1018       .readfn = pmccntr_read, .writefn = pmccntr_write32,
1019       .accessfn = pmreg_access },
1020     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
1021       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
1022       .access = PL0_RW, .accessfn = pmreg_access,
1023       .type = ARM_CP_IO,
1024       .readfn = pmccntr_read, .writefn = pmccntr_write, },
1025 #endif
1026     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
1027       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
1028       .writefn = pmccfiltr_write,
1029       .access = PL0_RW, .accessfn = pmreg_access,
1030       .type = ARM_CP_IO,
1031       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
1032       .resetvalue = 0, },
1033     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
1034       .access = PL0_RW,
1035       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
1036       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
1037       .raw_writefn = raw_write },
1038     /* Unimplemented, RAZ/WI. */
1039     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
1040       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1041       .accessfn = pmreg_access },
1042     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
1043       .access = PL0_R | PL1_RW,
1044       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1045       .resetvalue = 0,
1046       .writefn = pmuserenr_write, .raw_writefn = raw_write },
1047     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
1048       .access = PL1_RW,
1049       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1050       .resetvalue = 0,
1051       .writefn = pmintenset_write, .raw_writefn = raw_write },
1052     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
1053       .access = PL1_RW, .type = ARM_CP_ALIAS,
1054       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1055       .writefn = pmintenclr_write, },
1056     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
1057       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
1058       .access = PL1_RW, .writefn = vbar_write,
1059       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
1060                              offsetof(CPUARMState, cp15.vbar_ns) },
1061       .resetvalue = 0 },
1062     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
1063       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
1064       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
1065     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
1066       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
1067       .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
1068       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
1069                              offsetof(CPUARMState, cp15.csselr_ns) } },
1070     /* Auxiliary ID register: this actually has an IMPDEF value but for now
1071      * just RAZ for all cores:
1072      */
1073     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1074       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1075       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1076     /* Auxiliary fault status registers: these also are IMPDEF, and we
1077      * choose to RAZ/WI for all cores.
1078      */
1079     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1080       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1081       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1082     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1083       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1084       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1085     /* MAIR can just read-as-written because we don't implement caches
1086      * and so don't need to care about memory attributes.
1087      */
1088     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1089       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1090       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1091       .resetvalue = 0 },
1092     { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
1093       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
1094       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1095       .resetvalue = 0 },
1096     /* For non-long-descriptor page tables these are PRRR and NMRR;
1097      * regardless they still act as reads-as-written for QEMU.
1098      */
1099      /* MAIR0/1 are defined separately from their 64-bit counterpart which
1100       * allows them to assign the correct fieldoffset based on the endianness
1101       * handled in the field definitions.
1102       */
1103     { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1104       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1105       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1106                              offsetof(CPUARMState, cp15.mair0_ns) },
1107       .resetfn = arm_cp_reset_ignore },
1108     { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
1109       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1110       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1111                              offsetof(CPUARMState, cp15.mair1_ns) },
1112       .resetfn = arm_cp_reset_ignore },
1113     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1114       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1115       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1116     /* 32 bit ITLB invalidates */
1117     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1118       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1119     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1120       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1121     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1122       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1123     /* 32 bit DTLB invalidates */
1124     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1125       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1126     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1127       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1128     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1129       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1130     /* 32 bit TLB invalidates */
1131     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1132       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1133     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1134       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1135     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1136       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1137     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1138       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1139     REGINFO_SENTINEL
1140 };
1141
1142 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1143     /* 32 bit TLB invalidates, Inner Shareable */
1144     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1145       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1146     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1147       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1148     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1149       .type = ARM_CP_NO_RAW, .access = PL1_W,
1150       .writefn = tlbiasid_is_write },
1151     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1152       .type = ARM_CP_NO_RAW, .access = PL1_W,
1153       .writefn = tlbimvaa_is_write },
1154     REGINFO_SENTINEL
1155 };
1156
1157 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1158                         uint64_t value)
1159 {
1160     value &= 1;
1161     env->teecr = value;
1162 }
1163
1164 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1165                                     bool isread)
1166 {
1167     if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1168         return CP_ACCESS_TRAP;
1169     }
1170     return CP_ACCESS_OK;
1171 }
1172
1173 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1174     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1175       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1176       .resetvalue = 0,
1177       .writefn = teecr_write },
1178     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1179       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1180       .accessfn = teehbr_access, .resetvalue = 0 },
1181     REGINFO_SENTINEL
1182 };
1183
1184 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1185     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1186       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1187       .access = PL0_RW,
1188       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1189     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1190       .access = PL0_RW,
1191       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1192                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1193       .resetfn = arm_cp_reset_ignore },
1194     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1195       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1196       .access = PL0_R|PL1_W,
1197       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1198       .resetvalue = 0},
1199     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1200       .access = PL0_R|PL1_W,
1201       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1202                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1203       .resetfn = arm_cp_reset_ignore },
1204     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1205       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1206       .access = PL1_RW,
1207       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1208     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1209       .access = PL1_RW,
1210       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1211                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1212       .resetvalue = 0 },
1213     REGINFO_SENTINEL
1214 };
1215
1216 #ifndef CONFIG_USER_ONLY
1217
1218 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
1219                                        bool isread)
1220 {
1221     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1222     if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
1223         return CP_ACCESS_TRAP;
1224     }
1225     return CP_ACCESS_OK;
1226 }
1227
1228 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
1229                                         bool isread)
1230 {
1231     unsigned int cur_el = arm_current_el(env);
1232     bool secure = arm_is_secure(env);
1233
1234     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1235     if (cur_el == 0 &&
1236         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1237         return CP_ACCESS_TRAP;
1238     }
1239
1240     if (arm_feature(env, ARM_FEATURE_EL2) &&
1241         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1242         !extract32(env->cp15.cnthctl_el2, 0, 1)) {
1243         return CP_ACCESS_TRAP_EL2;
1244     }
1245     return CP_ACCESS_OK;
1246 }
1247
1248 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
1249                                       bool isread)
1250 {
1251     unsigned int cur_el = arm_current_el(env);
1252     bool secure = arm_is_secure(env);
1253
1254     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1255      * EL0[PV]TEN is zero.
1256      */
1257     if (cur_el == 0 &&
1258         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1259         return CP_ACCESS_TRAP;
1260     }
1261
1262     if (arm_feature(env, ARM_FEATURE_EL2) &&
1263         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1264         !extract32(env->cp15.cnthctl_el2, 1, 1)) {
1265         return CP_ACCESS_TRAP_EL2;
1266     }
1267     return CP_ACCESS_OK;
1268 }
1269
1270 static CPAccessResult gt_pct_access(CPUARMState *env,
1271                                     const ARMCPRegInfo *ri,
1272                                     bool isread)
1273 {
1274     return gt_counter_access(env, GTIMER_PHYS, isread);
1275 }
1276
1277 static CPAccessResult gt_vct_access(CPUARMState *env,
1278                                     const ARMCPRegInfo *ri,
1279                                     bool isread)
1280 {
1281     return gt_counter_access(env, GTIMER_VIRT, isread);
1282 }
1283
1284 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1285                                        bool isread)
1286 {
1287     return gt_timer_access(env, GTIMER_PHYS, isread);
1288 }
1289
1290 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1291                                        bool isread)
1292 {
1293     return gt_timer_access(env, GTIMER_VIRT, isread);
1294 }
1295
1296 static CPAccessResult gt_stimer_access(CPUARMState *env,
1297                                        const ARMCPRegInfo *ri,
1298                                        bool isread)
1299 {
1300     /* The AArch64 register view of the secure physical timer is
1301      * always accessible from EL3, and configurably accessible from
1302      * Secure EL1.
1303      */
1304     switch (arm_current_el(env)) {
1305     case 1:
1306         if (!arm_is_secure(env)) {
1307             return CP_ACCESS_TRAP;
1308         }
1309         if (!(env->cp15.scr_el3 & SCR_ST)) {
1310             return CP_ACCESS_TRAP_EL3;
1311         }
1312         return CP_ACCESS_OK;
1313     case 0:
1314     case 2:
1315         return CP_ACCESS_TRAP;
1316     case 3:
1317         return CP_ACCESS_OK;
1318     default:
1319         g_assert_not_reached();
1320     }
1321 }
1322
1323 static uint64_t gt_get_countervalue(CPUARMState *env)
1324 {
1325     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1326 }
1327
1328 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1329 {
1330     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1331
1332     if (gt->ctl & 1) {
1333         /* Timer enabled: calculate and set current ISTATUS, irq, and
1334          * reset timer to when ISTATUS next has to change
1335          */
1336         uint64_t offset = timeridx == GTIMER_VIRT ?
1337                                       cpu->env.cp15.cntvoff_el2 : 0;
1338         uint64_t count = gt_get_countervalue(&cpu->env);
1339         /* Note that this must be unsigned 64 bit arithmetic: */
1340         int istatus = count - offset >= gt->cval;
1341         uint64_t nexttick;
1342
1343         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1344         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1345                      (istatus && !(gt->ctl & 2)));
1346         if (istatus) {
1347             /* Next transition is when count rolls back over to zero */
1348             nexttick = UINT64_MAX;
1349         } else {
1350             /* Next transition is when we hit cval */
1351             nexttick = gt->cval + offset;
1352         }
1353         /* Note that the desired next expiry time might be beyond the
1354          * signed-64-bit range of a QEMUTimer -- in this case we just
1355          * set the timer for as far in the future as possible. When the
1356          * timer expires we will reset the timer for any remaining period.
1357          */
1358         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1359             nexttick = INT64_MAX / GTIMER_SCALE;
1360         }
1361         timer_mod(cpu->gt_timer[timeridx], nexttick);
1362     } else {
1363         /* Timer disabled: ISTATUS and timer output always clear */
1364         gt->ctl &= ~4;
1365         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1366         timer_del(cpu->gt_timer[timeridx]);
1367     }
1368 }
1369
1370 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
1371                            int timeridx)
1372 {
1373     ARMCPU *cpu = arm_env_get_cpu(env);
1374
1375     timer_del(cpu->gt_timer[timeridx]);
1376 }
1377
1378 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1379 {
1380     return gt_get_countervalue(env);
1381 }
1382
1383 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1384 {
1385     return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
1386 }
1387
1388 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1389                           int timeridx,
1390                           uint64_t value)
1391 {
1392     env->cp15.c14_timer[timeridx].cval = value;
1393     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1394 }
1395
1396 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
1397                              int timeridx)
1398 {
1399     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1400
1401     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1402                       (gt_get_countervalue(env) - offset));
1403 }
1404
1405 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1406                           int timeridx,
1407                           uint64_t value)
1408 {
1409     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1410
1411     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
1412                                          sextract64(value, 0, 32);
1413     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1414 }
1415
1416 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1417                          int timeridx,
1418                          uint64_t value)
1419 {
1420     ARMCPU *cpu = arm_env_get_cpu(env);
1421     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1422
1423     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1424     if ((oldval ^ value) & 1) {
1425         /* Enable toggled */
1426         gt_recalc_timer(cpu, timeridx);
1427     } else if ((oldval ^ value) & 2) {
1428         /* IMASK toggled: don't need to recalculate,
1429          * just set the interrupt line based on ISTATUS
1430          */
1431         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1432                      (oldval & 4) && !(value & 2));
1433     }
1434 }
1435
1436 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1437 {
1438     gt_timer_reset(env, ri, GTIMER_PHYS);
1439 }
1440
1441 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1442                                uint64_t value)
1443 {
1444     gt_cval_write(env, ri, GTIMER_PHYS, value);
1445 }
1446
1447 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1448 {
1449     return gt_tval_read(env, ri, GTIMER_PHYS);
1450 }
1451
1452 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1453                                uint64_t value)
1454 {
1455     gt_tval_write(env, ri, GTIMER_PHYS, value);
1456 }
1457
1458 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1459                               uint64_t value)
1460 {
1461     gt_ctl_write(env, ri, GTIMER_PHYS, value);
1462 }
1463
1464 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1465 {
1466     gt_timer_reset(env, ri, GTIMER_VIRT);
1467 }
1468
1469 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1470                                uint64_t value)
1471 {
1472     gt_cval_write(env, ri, GTIMER_VIRT, value);
1473 }
1474
1475 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1476 {
1477     return gt_tval_read(env, ri, GTIMER_VIRT);
1478 }
1479
1480 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1481                                uint64_t value)
1482 {
1483     gt_tval_write(env, ri, GTIMER_VIRT, value);
1484 }
1485
1486 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1487                               uint64_t value)
1488 {
1489     gt_ctl_write(env, ri, GTIMER_VIRT, value);
1490 }
1491
1492 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
1493                               uint64_t value)
1494 {
1495     ARMCPU *cpu = arm_env_get_cpu(env);
1496
1497     raw_write(env, ri, value);
1498     gt_recalc_timer(cpu, GTIMER_VIRT);
1499 }
1500
1501 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1502 {
1503     gt_timer_reset(env, ri, GTIMER_HYP);
1504 }
1505
1506 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1507                               uint64_t value)
1508 {
1509     gt_cval_write(env, ri, GTIMER_HYP, value);
1510 }
1511
1512 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1513 {
1514     return gt_tval_read(env, ri, GTIMER_HYP);
1515 }
1516
1517 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1518                               uint64_t value)
1519 {
1520     gt_tval_write(env, ri, GTIMER_HYP, value);
1521 }
1522
1523 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1524                               uint64_t value)
1525 {
1526     gt_ctl_write(env, ri, GTIMER_HYP, value);
1527 }
1528
1529 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1530 {
1531     gt_timer_reset(env, ri, GTIMER_SEC);
1532 }
1533
1534 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1535                               uint64_t value)
1536 {
1537     gt_cval_write(env, ri, GTIMER_SEC, value);
1538 }
1539
1540 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1541 {
1542     return gt_tval_read(env, ri, GTIMER_SEC);
1543 }
1544
1545 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1546                               uint64_t value)
1547 {
1548     gt_tval_write(env, ri, GTIMER_SEC, value);
1549 }
1550
1551 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1552                               uint64_t value)
1553 {
1554     gt_ctl_write(env, ri, GTIMER_SEC, value);
1555 }
1556
1557 void arm_gt_ptimer_cb(void *opaque)
1558 {
1559     ARMCPU *cpu = opaque;
1560
1561     gt_recalc_timer(cpu, GTIMER_PHYS);
1562 }
1563
1564 void arm_gt_vtimer_cb(void *opaque)
1565 {
1566     ARMCPU *cpu = opaque;
1567
1568     gt_recalc_timer(cpu, GTIMER_VIRT);
1569 }
1570
1571 void arm_gt_htimer_cb(void *opaque)
1572 {
1573     ARMCPU *cpu = opaque;
1574
1575     gt_recalc_timer(cpu, GTIMER_HYP);
1576 }
1577
1578 void arm_gt_stimer_cb(void *opaque)
1579 {
1580     ARMCPU *cpu = opaque;
1581
1582     gt_recalc_timer(cpu, GTIMER_SEC);
1583 }
1584
1585 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1586     /* Note that CNTFRQ is purely reads-as-written for the benefit
1587      * of software; writing it doesn't actually change the timer frequency.
1588      * Our reset value matches the fixed frequency we implement the timer at.
1589      */
1590     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1591       .type = ARM_CP_ALIAS,
1592       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1593       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1594     },
1595     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1596       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1597       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1598       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1599       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1600     },
1601     /* overall control: mostly access permissions */
1602     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1603       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1604       .access = PL1_RW,
1605       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1606       .resetvalue = 0,
1607     },
1608     /* per-timer control */
1609     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1610       .secure = ARM_CP_SECSTATE_NS,
1611       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1612       .accessfn = gt_ptimer_access,
1613       .fieldoffset = offsetoflow32(CPUARMState,
1614                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1615       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1616     },
1617     { .name = "CNTP_CTL(S)",
1618       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1619       .secure = ARM_CP_SECSTATE_S,
1620       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1621       .accessfn = gt_ptimer_access,
1622       .fieldoffset = offsetoflow32(CPUARMState,
1623                                    cp15.c14_timer[GTIMER_SEC].ctl),
1624       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1625     },
1626     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1627       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1628       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1629       .accessfn = gt_ptimer_access,
1630       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1631       .resetvalue = 0,
1632       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1633     },
1634     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1635       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1636       .accessfn = gt_vtimer_access,
1637       .fieldoffset = offsetoflow32(CPUARMState,
1638                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1639       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1640     },
1641     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1642       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1643       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1644       .accessfn = gt_vtimer_access,
1645       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1646       .resetvalue = 0,
1647       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1648     },
1649     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1650     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1651       .secure = ARM_CP_SECSTATE_NS,
1652       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1653       .accessfn = gt_ptimer_access,
1654       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1655     },
1656     { .name = "CNTP_TVAL(S)",
1657       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1658       .secure = ARM_CP_SECSTATE_S,
1659       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1660       .accessfn = gt_ptimer_access,
1661       .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
1662     },
1663     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1664       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1665       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1666       .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
1667       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1668     },
1669     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1670       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1671       .accessfn = gt_vtimer_access,
1672       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1673     },
1674     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1675       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1676       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1677       .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
1678       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1679     },
1680     /* The counter itself */
1681     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1682       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1683       .accessfn = gt_pct_access,
1684       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1685     },
1686     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1687       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1688       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1689       .accessfn = gt_pct_access, .readfn = gt_cnt_read,
1690     },
1691     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1692       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1693       .accessfn = gt_vct_access,
1694       .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
1695     },
1696     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1697       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1698       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1699       .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
1700     },
1701     /* Comparison value, indicating when the timer goes off */
1702     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1703       .secure = ARM_CP_SECSTATE_NS,
1704       .access = PL1_RW | PL0_R,
1705       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1706       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1707       .accessfn = gt_ptimer_access,
1708       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1709     },
1710     { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2,
1711       .secure = ARM_CP_SECSTATE_S,
1712       .access = PL1_RW | PL0_R,
1713       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1714       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1715       .accessfn = gt_ptimer_access,
1716       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1717     },
1718     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1719       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1720       .access = PL1_RW | PL0_R,
1721       .type = ARM_CP_IO,
1722       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1723       .resetvalue = 0, .accessfn = gt_ptimer_access,
1724       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1725     },
1726     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1727       .access = PL1_RW | PL0_R,
1728       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1729       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1730       .accessfn = gt_vtimer_access,
1731       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1732     },
1733     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1734       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1735       .access = PL1_RW | PL0_R,
1736       .type = ARM_CP_IO,
1737       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1738       .resetvalue = 0, .accessfn = gt_vtimer_access,
1739       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1740     },
1741     /* Secure timer -- this is actually restricted to only EL3
1742      * and configurably Secure-EL1 via the accessfn.
1743      */
1744     { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
1745       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
1746       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
1747       .accessfn = gt_stimer_access,
1748       .readfn = gt_sec_tval_read,
1749       .writefn = gt_sec_tval_write,
1750       .resetfn = gt_sec_timer_reset,
1751     },
1752     { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
1753       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
1754       .type = ARM_CP_IO, .access = PL1_RW,
1755       .accessfn = gt_stimer_access,
1756       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
1757       .resetvalue = 0,
1758       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1759     },
1760     { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
1761       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
1762       .type = ARM_CP_IO, .access = PL1_RW,
1763       .accessfn = gt_stimer_access,
1764       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1765       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1766     },
1767     REGINFO_SENTINEL
1768 };
1769
1770 #else
1771 /* In user-mode none of the generic timer registers are accessible,
1772  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1773  * so instead just don't register any of them.
1774  */
1775 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1776     REGINFO_SENTINEL
1777 };
1778
1779 #endif
1780
1781 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1782 {
1783     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1784         raw_write(env, ri, value);
1785     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1786         raw_write(env, ri, value & 0xfffff6ff);
1787     } else {
1788         raw_write(env, ri, value & 0xfffff1ff);
1789     }
1790 }
1791
1792 #ifndef CONFIG_USER_ONLY
1793 /* get_phys_addr() isn't present for user-mode-only targets */
1794
1795 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
1796                                  bool isread)
1797 {
1798     if (ri->opc2 & 4) {
1799         /* The ATS12NSO* operations must trap to EL3 if executed in
1800          * Secure EL1 (which can only happen if EL3 is AArch64).
1801          * They are simply UNDEF if executed from NS EL1.
1802          * They function normally from EL2 or EL3.
1803          */
1804         if (arm_current_el(env) == 1) {
1805             if (arm_is_secure_below_el3(env)) {
1806                 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
1807             }
1808             return CP_ACCESS_TRAP_UNCATEGORIZED;
1809         }
1810     }
1811     return CP_ACCESS_OK;
1812 }
1813
1814 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
1815                              int access_type, ARMMMUIdx mmu_idx)
1816 {
1817     hwaddr phys_addr;
1818     target_ulong page_size;
1819     int prot;
1820     uint32_t fsr;
1821     bool ret;
1822     uint64_t par64;
1823     MemTxAttrs attrs = {};
1824     ARMMMUFaultInfo fi = {};
1825
1826     ret = get_phys_addr(env, value, access_type, mmu_idx,
1827                         &phys_addr, &attrs, &prot, &page_size, &fsr, &fi);
1828     if (extended_addresses_enabled(env)) {
1829         /* fsr is a DFSR/IFSR value for the long descriptor
1830          * translation table format, but with WnR always clear.
1831          * Convert it to a 64-bit PAR.
1832          */
1833         par64 = (1 << 11); /* LPAE bit always set */
1834         if (!ret) {
1835             par64 |= phys_addr & ~0xfffULL;
1836             if (!attrs.secure) {
1837                 par64 |= (1 << 9); /* NS */
1838             }
1839             /* We don't set the ATTR or SH fields in the PAR. */
1840         } else {
1841             par64 |= 1; /* F */
1842             par64 |= (fsr & 0x3f) << 1; /* FS */
1843             /* Note that S2WLK and FSTAGE are always zero, because we don't
1844              * implement virtualization and therefore there can't be a stage 2
1845              * fault.
1846              */
1847         }
1848     } else {
1849         /* fsr is a DFSR/IFSR value for the short descriptor
1850          * translation table format (with WnR always clear).
1851          * Convert it to a 32-bit PAR.
1852          */
1853         if (!ret) {
1854             /* We do not set any attribute bits in the PAR */
1855             if (page_size == (1 << 24)
1856                 && arm_feature(env, ARM_FEATURE_V7)) {
1857                 par64 = (phys_addr & 0xff000000) | (1 << 1);
1858             } else {
1859                 par64 = phys_addr & 0xfffff000;
1860             }
1861             if (!attrs.secure) {
1862                 par64 |= (1 << 9); /* NS */
1863             }
1864         } else {
1865             par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
1866                     ((fsr & 0xf) << 1) | 1;
1867         }
1868     }
1869     return par64;
1870 }
1871
1872 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1873 {
1874     int access_type = ri->opc2 & 1;
1875     uint64_t par64;
1876     ARMMMUIdx mmu_idx;
1877     int el = arm_current_el(env);
1878     bool secure = arm_is_secure_below_el3(env);
1879
1880     switch (ri->opc2 & 6) {
1881     case 0:
1882         /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
1883         switch (el) {
1884         case 3:
1885             mmu_idx = ARMMMUIdx_S1E3;
1886             break;
1887         case 2:
1888             mmu_idx = ARMMMUIdx_S1NSE1;
1889             break;
1890         case 1:
1891             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1892             break;
1893         default:
1894             g_assert_not_reached();
1895         }
1896         break;
1897     case 2:
1898         /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
1899         switch (el) {
1900         case 3:
1901             mmu_idx = ARMMMUIdx_S1SE0;
1902             break;
1903         case 2:
1904             mmu_idx = ARMMMUIdx_S1NSE0;
1905             break;
1906         case 1:
1907             mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1908             break;
1909         default:
1910             g_assert_not_reached();
1911         }
1912         break;
1913     case 4:
1914         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
1915         mmu_idx = ARMMMUIdx_S12NSE1;
1916         break;
1917     case 6:
1918         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
1919         mmu_idx = ARMMMUIdx_S12NSE0;
1920         break;
1921     default:
1922         g_assert_not_reached();
1923     }
1924
1925     par64 = do_ats_write(env, value, access_type, mmu_idx);
1926
1927     A32_BANKED_CURRENT_REG_SET(env, par, par64);
1928 }
1929
1930 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
1931                         uint64_t value)
1932 {
1933     int access_type = ri->opc2 & 1;
1934     uint64_t par64;
1935
1936     par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
1937
1938     A32_BANKED_CURRENT_REG_SET(env, par, par64);
1939 }
1940
1941 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
1942                                      bool isread)
1943 {
1944     if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
1945         return CP_ACCESS_TRAP;
1946     }
1947     return CP_ACCESS_OK;
1948 }
1949
1950 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
1951                         uint64_t value)
1952 {
1953     int access_type = ri->opc2 & 1;
1954     ARMMMUIdx mmu_idx;
1955     int secure = arm_is_secure_below_el3(env);
1956
1957     switch (ri->opc2 & 6) {
1958     case 0:
1959         switch (ri->opc1) {
1960         case 0: /* AT S1E1R, AT S1E1W */
1961             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1962             break;
1963         case 4: /* AT S1E2R, AT S1E2W */
1964             mmu_idx = ARMMMUIdx_S1E2;
1965             break;
1966         case 6: /* AT S1E3R, AT S1E3W */
1967             mmu_idx = ARMMMUIdx_S1E3;
1968             break;
1969         default:
1970             g_assert_not_reached();
1971         }
1972         break;
1973     case 2: /* AT S1E0R, AT S1E0W */
1974         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1975         break;
1976     case 4: /* AT S12E1R, AT S12E1W */
1977         mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
1978         break;
1979     case 6: /* AT S12E0R, AT S12E0W */
1980         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
1981         break;
1982     default:
1983         g_assert_not_reached();
1984     }
1985
1986     env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
1987 }
1988 #endif
1989
1990 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1991     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1992       .access = PL1_RW, .resetvalue = 0,
1993       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
1994                              offsetoflow32(CPUARMState, cp15.par_ns) },
1995       .writefn = par_write },
1996 #ifndef CONFIG_USER_ONLY
1997     /* This underdecoding is safe because the reginfo is NO_RAW. */
1998     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1999       .access = PL1_W, .accessfn = ats_access,
2000       .writefn = ats_write, .type = ARM_CP_NO_RAW },
2001 #endif
2002     REGINFO_SENTINEL
2003 };
2004
2005 /* Return basic MPU access permission bits.  */
2006 static uint32_t simple_mpu_ap_bits(uint32_t val)
2007 {
2008     uint32_t ret;
2009     uint32_t mask;
2010     int i;
2011     ret = 0;
2012     mask = 3;
2013     for (i = 0; i < 16; i += 2) {
2014         ret |= (val >> i) & mask;
2015         mask <<= 2;
2016     }
2017     return ret;
2018 }
2019
2020 /* Pad basic MPU access permission bits to extended format.  */
2021 static uint32_t extended_mpu_ap_bits(uint32_t val)
2022 {
2023     uint32_t ret;
2024     uint32_t mask;
2025     int i;
2026     ret = 0;
2027     mask = 3;
2028     for (i = 0; i < 16; i += 2) {
2029         ret |= (val & mask) << i;
2030         mask <<= 2;
2031     }
2032     return ret;
2033 }
2034
2035 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2036                                  uint64_t value)
2037 {
2038     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
2039 }
2040
2041 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2042 {
2043     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
2044 }
2045
2046 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2047                                  uint64_t value)
2048 {
2049     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
2050 }
2051
2052 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2053 {
2054     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
2055 }
2056
2057 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
2058 {
2059     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2060
2061     if (!u32p) {
2062         return 0;
2063     }
2064
2065     u32p += env->cp15.c6_rgnr;
2066     return *u32p;
2067 }
2068
2069 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
2070                          uint64_t value)
2071 {
2072     ARMCPU *cpu = arm_env_get_cpu(env);
2073     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2074
2075     if (!u32p) {
2076         return;
2077     }
2078
2079     u32p += env->cp15.c6_rgnr;
2080     tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
2081     *u32p = value;
2082 }
2083
2084 static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2085 {
2086     ARMCPU *cpu = arm_env_get_cpu(env);
2087     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2088
2089     if (!u32p) {
2090         return;
2091     }
2092
2093     memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
2094 }
2095
2096 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2097                               uint64_t value)
2098 {
2099     ARMCPU *cpu = arm_env_get_cpu(env);
2100     uint32_t nrgs = cpu->pmsav7_dregion;
2101
2102     if (value >= nrgs) {
2103         qemu_log_mask(LOG_GUEST_ERROR,
2104                       "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2105                       " > %" PRIu32 "\n", (uint32_t)value, nrgs);
2106         return;
2107     }
2108
2109     raw_write(env, ri, value);
2110 }
2111
2112 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
2113     { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
2114       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2115       .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
2116       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2117     { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
2118       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2119       .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
2120       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2121     { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
2122       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2123       .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
2124       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2125     { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
2126       .access = PL1_RW,
2127       .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr),
2128       .writefn = pmsav7_rgnr_write },
2129     REGINFO_SENTINEL
2130 };
2131
2132 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
2133     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2134       .access = PL1_RW, .type = ARM_CP_ALIAS,
2135       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2136       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
2137     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2138       .access = PL1_RW, .type = ARM_CP_ALIAS,
2139       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2140       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
2141     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
2142       .access = PL1_RW,
2143       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2144       .resetvalue = 0, },
2145     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
2146       .access = PL1_RW,
2147       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2148       .resetvalue = 0, },
2149     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2150       .access = PL1_RW,
2151       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
2152     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
2153       .access = PL1_RW,
2154       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
2155     /* Protection region base and size registers */
2156     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
2157       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2158       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
2159     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
2160       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2161       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
2162     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
2163       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2164       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
2165     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
2166       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2167       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
2168     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
2169       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2170       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
2171     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
2172       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2173       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
2174     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
2175       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2176       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
2177     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
2178       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2179       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
2180     REGINFO_SENTINEL
2181 };
2182
2183 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
2184                                  uint64_t value)
2185 {
2186     TCR *tcr = raw_ptr(env, ri);
2187     int maskshift = extract32(value, 0, 3);
2188
2189     if (!arm_feature(env, ARM_FEATURE_V8)) {
2190         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
2191             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2192              * using Long-desciptor translation table format */
2193             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
2194         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
2195             /* In an implementation that includes the Security Extensions
2196              * TTBCR has additional fields PD0 [4] and PD1 [5] for
2197              * Short-descriptor translation table format.
2198              */
2199             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
2200         } else {
2201             value &= TTBCR_N;
2202         }
2203     }
2204
2205     /* Update the masks corresponding to the TCR bank being written
2206      * Note that we always calculate mask and base_mask, but
2207      * they are only used for short-descriptor tables (ie if EAE is 0);
2208      * for long-descriptor tables the TCR fields are used differently
2209      * and the mask and base_mask values are meaningless.
2210      */
2211     tcr->raw_tcr = value;
2212     tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
2213     tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
2214 }
2215
2216 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2217                              uint64_t value)
2218 {
2219     ARMCPU *cpu = arm_env_get_cpu(env);
2220
2221     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2222         /* With LPAE the TTBCR could result in a change of ASID
2223          * via the TTBCR.A1 bit, so do a TLB flush.
2224          */
2225         tlb_flush(CPU(cpu), 1);
2226     }
2227     vmsa_ttbcr_raw_write(env, ri, value);
2228 }
2229
2230 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2231 {
2232     TCR *tcr = raw_ptr(env, ri);
2233
2234     /* Reset both the TCR as well as the masks corresponding to the bank of
2235      * the TCR being reset.
2236      */
2237     tcr->raw_tcr = 0;
2238     tcr->mask = 0;
2239     tcr->base_mask = 0xffffc000u;
2240 }
2241
2242 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2243                                uint64_t value)
2244 {
2245     ARMCPU *cpu = arm_env_get_cpu(env);
2246     TCR *tcr = raw_ptr(env, ri);
2247
2248     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2249     tlb_flush(CPU(cpu), 1);
2250     tcr->raw_tcr = value;
2251 }
2252
2253 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2254                             uint64_t value)
2255 {
2256     /* 64 bit accesses to the TTBRs can change the ASID and so we
2257      * must flush the TLB.
2258      */
2259     if (cpreg_field_is_64bit(ri)) {
2260         ARMCPU *cpu = arm_env_get_cpu(env);
2261
2262         tlb_flush(CPU(cpu), 1);
2263     }
2264     raw_write(env, ri, value);
2265 }
2266
2267 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2268                         uint64_t value)
2269 {
2270     ARMCPU *cpu = arm_env_get_cpu(env);
2271     CPUState *cs = CPU(cpu);
2272
2273     /* Accesses to VTTBR may change the VMID so we must flush the TLB.  */
2274     if (raw_read(env, ri) != value) {
2275         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2276                             ARMMMUIdx_S2NS, -1);
2277         raw_write(env, ri, value);
2278     }
2279 }
2280
2281 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
2282     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2283       .access = PL1_RW, .type = ARM_CP_ALIAS,
2284       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
2285                              offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
2286     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2287       .access = PL1_RW, .resetvalue = 0,
2288       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
2289                              offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
2290     { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
2291       .access = PL1_RW, .resetvalue = 0,
2292       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
2293                              offsetof(CPUARMState, cp15.dfar_ns) } },
2294     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
2295       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
2296       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
2297       .resetvalue = 0, },
2298     REGINFO_SENTINEL
2299 };
2300
2301 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
2302     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
2303       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
2304       .access = PL1_RW,
2305       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
2306     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
2307       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
2308       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2309       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2310                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
2311     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
2312       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
2313       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2314       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2315                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
2316     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
2317       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2318       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
2319       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2320       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
2321     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2322       .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
2323       .raw_writefn = vmsa_ttbcr_raw_write,
2324       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
2325                              offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
2326     REGINFO_SENTINEL
2327 };
2328
2329 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
2330                                 uint64_t value)
2331 {
2332     env->cp15.c15_ticonfig = value & 0xe7;
2333     /* The OS_TYPE bit in this register changes the reported CPUID! */
2334     env->cp15.c0_cpuid = (value & (1 << 5)) ?
2335         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
2336 }
2337
2338 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2339                                 uint64_t value)
2340 {
2341     env->cp15.c15_threadid = value & 0xffff;
2342 }
2343
2344 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
2345                            uint64_t value)
2346 {
2347     /* Wait-for-interrupt (deprecated) */
2348     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
2349 }
2350
2351 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
2352                                   uint64_t value)
2353 {
2354     /* On OMAP there are registers indicating the max/min index of dcache lines
2355      * containing a dirty line; cache flush operations have to reset these.
2356      */
2357     env->cp15.c15_i_max = 0x000;
2358     env->cp15.c15_i_min = 0xff0;
2359 }
2360
2361 static const ARMCPRegInfo omap_cp_reginfo[] = {
2362     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
2363       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
2364       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
2365       .resetvalue = 0, },
2366     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2367       .access = PL1_RW, .type = ARM_CP_NOP },
2368     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2369       .access = PL1_RW,
2370       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
2371       .writefn = omap_ticonfig_write },
2372     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
2373       .access = PL1_RW,
2374       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
2375     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
2376       .access = PL1_RW, .resetvalue = 0xff0,
2377       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
2378     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
2379       .access = PL1_RW,
2380       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
2381       .writefn = omap_threadid_write },
2382     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
2383       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2384       .type = ARM_CP_NO_RAW,
2385       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
2386     /* TODO: Peripheral port remap register:
2387      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2388      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2389      * when MMU is off.
2390      */
2391     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
2392       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
2393       .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
2394       .writefn = omap_cachemaint_write },
2395     { .name = "C9", .cp = 15, .crn = 9,
2396       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
2397       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
2398     REGINFO_SENTINEL
2399 };
2400
2401 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2402                               uint64_t value)
2403 {
2404     env->cp15.c15_cpar = value & 0x3fff;
2405 }
2406
2407 static const ARMCPRegInfo xscale_cp_reginfo[] = {
2408     { .name = "XSCALE_CPAR",
2409       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2410       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
2411       .writefn = xscale_cpar_write, },
2412     { .name = "XSCALE_AUXCR",
2413       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
2414       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
2415       .resetvalue = 0, },
2416     /* XScale specific cache-lockdown: since we have no cache we NOP these
2417      * and hope the guest does not really rely on cache behaviour.
2418      */
2419     { .name = "XSCALE_LOCK_ICACHE_LINE",
2420       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2421       .access = PL1_W, .type = ARM_CP_NOP },
2422     { .name = "XSCALE_UNLOCK_ICACHE",
2423       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2424       .access = PL1_W, .type = ARM_CP_NOP },
2425     { .name = "XSCALE_DCACHE_LOCK",
2426       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
2427       .access = PL1_RW, .type = ARM_CP_NOP },
2428     { .name = "XSCALE_UNLOCK_DCACHE",
2429       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
2430       .access = PL1_W, .type = ARM_CP_NOP },
2431     REGINFO_SENTINEL
2432 };
2433
2434 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2435     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2436      * implementation of this implementation-defined space.
2437      * Ideally this should eventually disappear in favour of actually
2438      * implementing the correct behaviour for all cores.
2439      */
2440     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2441       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2442       .access = PL1_RW,
2443       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2444       .resetvalue = 0 },
2445     REGINFO_SENTINEL
2446 };
2447
2448 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2449     /* Cache status: RAZ because we have no cache so it's always clean */
2450     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2451       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2452       .resetvalue = 0 },
2453     REGINFO_SENTINEL
2454 };
2455
2456 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2457     /* We never have a a block transfer operation in progress */
2458     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2459       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2460       .resetvalue = 0 },
2461     /* The cache ops themselves: these all NOP for QEMU */
2462     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2463       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2464     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2465       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2466     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2467       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2468     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2469       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2470     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2471       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2472     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2473       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2474     REGINFO_SENTINEL
2475 };
2476
2477 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2478     /* The cache test-and-clean instructions always return (1 << 30)
2479      * to indicate that there are no dirty cache lines.
2480      */
2481     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2482       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2483       .resetvalue = (1 << 30) },
2484     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2485       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2486       .resetvalue = (1 << 30) },
2487     REGINFO_SENTINEL
2488 };
2489
2490 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2491     /* Ignore ReadBuffer accesses */
2492     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2493       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2494       .access = PL1_RW, .resetvalue = 0,
2495       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2496     REGINFO_SENTINEL
2497 };
2498
2499 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2500 {
2501     ARMCPU *cpu = arm_env_get_cpu(env);
2502     unsigned int cur_el = arm_current_el(env);
2503     bool secure = arm_is_secure(env);
2504
2505     if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2506         return env->cp15.vpidr_el2;
2507     }
2508     return raw_read(env, ri);
2509 }
2510
2511 static uint64_t mpidr_read_val(CPUARMState *env)
2512 {
2513     ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
2514     uint64_t mpidr = cpu->mp_affinity;
2515
2516     if (arm_feature(env, ARM_FEATURE_V7MP)) {
2517         mpidr |= (1U << 31);
2518         /* Cores which are uniprocessor (non-coherent)
2519          * but still implement the MP extensions set
2520          * bit 30. (For instance, Cortex-R5).
2521          */
2522         if (cpu->mp_is_up) {
2523             mpidr |= (1u << 30);
2524         }
2525     }
2526     return mpidr;
2527 }
2528
2529 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2530 {
2531     unsigned int cur_el = arm_current_el(env);
2532     bool secure = arm_is_secure(env);
2533
2534     if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2535         return env->cp15.vmpidr_el2;
2536     }
2537     return mpidr_read_val(env);
2538 }
2539
2540 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2541     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2542       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2543       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2544     REGINFO_SENTINEL
2545 };
2546
2547 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2548     /* NOP AMAIR0/1 */
2549     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2550       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2551       .access = PL1_RW, .type = ARM_CP_CONST,
2552       .resetvalue = 0 },
2553     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2554     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2555       .access = PL1_RW, .type = ARM_CP_CONST,
2556       .resetvalue = 0 },
2557     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2558       .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2559       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2560                              offsetof(CPUARMState, cp15.par_ns)} },
2561     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2562       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2563       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2564                              offsetof(CPUARMState, cp15.ttbr0_ns) },
2565       .writefn = vmsa_ttbr_write, },
2566     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2567       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2568       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2569                              offsetof(CPUARMState, cp15.ttbr1_ns) },
2570       .writefn = vmsa_ttbr_write, },
2571     REGINFO_SENTINEL
2572 };
2573
2574 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2575 {
2576     return vfp_get_fpcr(env);
2577 }
2578
2579 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2580                             uint64_t value)
2581 {
2582     vfp_set_fpcr(env, value);
2583 }
2584
2585 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2586 {
2587     return vfp_get_fpsr(env);
2588 }
2589
2590 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2591                             uint64_t value)
2592 {
2593     vfp_set_fpsr(env, value);
2594 }
2595
2596 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri,
2597                                        bool isread)
2598 {
2599     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2600         return CP_ACCESS_TRAP;
2601     }
2602     return CP_ACCESS_OK;
2603 }
2604
2605 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2606                             uint64_t value)
2607 {
2608     env->daif = value & PSTATE_DAIF;
2609 }
2610
2611 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2612                                           const ARMCPRegInfo *ri,
2613                                           bool isread)
2614 {
2615     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2616      * SCTLR_EL1.UCI is set.
2617      */
2618     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2619         return CP_ACCESS_TRAP;
2620     }
2621     return CP_ACCESS_OK;
2622 }
2623
2624 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2625  * Page D4-1736 (DDI0487A.b)
2626  */
2627
2628 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2629                                     uint64_t value)
2630 {
2631     ARMCPU *cpu = arm_env_get_cpu(env);
2632     CPUState *cs = CPU(cpu);
2633
2634     if (arm_is_secure_below_el3(env)) {
2635         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2636     } else {
2637         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2638     }
2639 }
2640
2641 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2642                                       uint64_t value)
2643 {
2644     bool sec = arm_is_secure_below_el3(env);
2645     CPUState *other_cs;
2646
2647     CPU_FOREACH(other_cs) {
2648         if (sec) {
2649             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2650         } else {
2651             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2652                                 ARMMMUIdx_S12NSE0, -1);
2653         }
2654     }
2655 }
2656
2657 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2658                                   uint64_t value)
2659 {
2660     /* Note that the 'ALL' scope must invalidate both stage 1 and
2661      * stage 2 translations, whereas most other scopes only invalidate
2662      * stage 1 translations.
2663      */
2664     ARMCPU *cpu = arm_env_get_cpu(env);
2665     CPUState *cs = CPU(cpu);
2666
2667     if (arm_is_secure_below_el3(env)) {
2668         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2669     } else {
2670         if (arm_feature(env, ARM_FEATURE_EL2)) {
2671             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2672                                 ARMMMUIdx_S2NS, -1);
2673         } else {
2674             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2675         }
2676     }
2677 }
2678
2679 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2680                                   uint64_t value)
2681 {
2682     ARMCPU *cpu = arm_env_get_cpu(env);
2683     CPUState *cs = CPU(cpu);
2684
2685     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1);
2686 }
2687
2688 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2689                                   uint64_t value)
2690 {
2691     ARMCPU *cpu = arm_env_get_cpu(env);
2692     CPUState *cs = CPU(cpu);
2693
2694     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1);
2695 }
2696
2697 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2698                                     uint64_t value)
2699 {
2700     /* Note that the 'ALL' scope must invalidate both stage 1 and
2701      * stage 2 translations, whereas most other scopes only invalidate
2702      * stage 1 translations.
2703      */
2704     bool sec = arm_is_secure_below_el3(env);
2705     bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
2706     CPUState *other_cs;
2707
2708     CPU_FOREACH(other_cs) {
2709         if (sec) {
2710             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2711         } else if (has_el2) {
2712             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2713                                 ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1);
2714         } else {
2715             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2716                                 ARMMMUIdx_S12NSE0, -1);
2717         }
2718     }
2719 }
2720
2721 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2722                                     uint64_t value)
2723 {
2724     CPUState *other_cs;
2725
2726     CPU_FOREACH(other_cs) {
2727         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1);
2728     }
2729 }
2730
2731 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2732                                     uint64_t value)
2733 {
2734     CPUState *other_cs;
2735
2736     CPU_FOREACH(other_cs) {
2737         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1);
2738     }
2739 }
2740
2741 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2742                                  uint64_t value)
2743 {
2744     /* Invalidate by VA, EL1&0 (AArch64 version).
2745      * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
2746      * since we don't support flush-for-specific-ASID-only or
2747      * flush-last-level-only.
2748      */
2749     ARMCPU *cpu = arm_env_get_cpu(env);
2750     CPUState *cs = CPU(cpu);
2751     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2752
2753     if (arm_is_secure_below_el3(env)) {
2754         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1,
2755                                  ARMMMUIdx_S1SE0, -1);
2756     } else {
2757         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1,
2758                                  ARMMMUIdx_S12NSE0, -1);
2759     }
2760 }
2761
2762 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2763                                  uint64_t value)
2764 {
2765     /* Invalidate by VA, EL2
2766      * Currently handles both VAE2 and VALE2, since we don't support
2767      * flush-last-level-only.
2768      */
2769     ARMCPU *cpu = arm_env_get_cpu(env);
2770     CPUState *cs = CPU(cpu);
2771     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2772
2773     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1);
2774 }
2775
2776 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2777                                  uint64_t value)
2778 {
2779     /* Invalidate by VA, EL3
2780      * Currently handles both VAE3 and VALE3, since we don't support
2781      * flush-last-level-only.
2782      */
2783     ARMCPU *cpu = arm_env_get_cpu(env);
2784     CPUState *cs = CPU(cpu);
2785     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2786
2787     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1);
2788 }
2789
2790 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2791                                    uint64_t value)
2792 {
2793     bool sec = arm_is_secure_below_el3(env);
2794     CPUState *other_cs;
2795     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2796
2797     CPU_FOREACH(other_cs) {
2798         if (sec) {
2799             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1,
2800                                      ARMMMUIdx_S1SE0, -1);
2801         } else {
2802             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1,
2803                                      ARMMMUIdx_S12NSE0, -1);
2804         }
2805     }
2806 }
2807
2808 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2809                                    uint64_t value)
2810 {
2811     CPUState *other_cs;
2812     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2813
2814     CPU_FOREACH(other_cs) {
2815         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
2816     }
2817 }
2818
2819 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2820                                    uint64_t value)
2821 {
2822     CPUState *other_cs;
2823     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2824
2825     CPU_FOREACH(other_cs) {
2826         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1);
2827     }
2828 }
2829
2830 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2831                                     uint64_t value)
2832 {
2833     /* Invalidate by IPA. This has to invalidate any structures that
2834      * contain only stage 2 translation information, but does not need
2835      * to apply to structures that contain combined stage 1 and stage 2
2836      * translation information.
2837      * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
2838      */
2839     ARMCPU *cpu = arm_env_get_cpu(env);
2840     CPUState *cs = CPU(cpu);
2841     uint64_t pageaddr;
2842
2843     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2844         return;
2845     }
2846
2847     pageaddr = sextract64(value << 12, 0, 48);
2848
2849     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);
2850 }
2851
2852 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2853                                       uint64_t value)
2854 {
2855     CPUState *other_cs;
2856     uint64_t pageaddr;
2857
2858     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2859         return;
2860     }
2861
2862     pageaddr = sextract64(value << 12, 0, 48);
2863
2864     CPU_FOREACH(other_cs) {
2865         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);
2866     }
2867 }
2868
2869 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
2870                                       bool isread)
2871 {
2872     /* We don't implement EL2, so the only control on DC ZVA is the
2873      * bit in the SCTLR which can prohibit access for EL0.
2874      */
2875     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
2876         return CP_ACCESS_TRAP;
2877     }
2878     return CP_ACCESS_OK;
2879 }
2880
2881 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
2882 {
2883     ARMCPU *cpu = arm_env_get_cpu(env);
2884     int dzp_bit = 1 << 4;
2885
2886     /* DZP indicates whether DC ZVA access is allowed */
2887     if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) {
2888         dzp_bit = 0;
2889     }
2890     return cpu->dcz_blocksize | dzp_bit;
2891 }
2892
2893 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
2894                                     bool isread)
2895 {
2896     if (!(env->pstate & PSTATE_SP)) {
2897         /* Access to SP_EL0 is undefined if it's being used as
2898          * the stack pointer.
2899          */
2900         return CP_ACCESS_TRAP_UNCATEGORIZED;
2901     }
2902     return CP_ACCESS_OK;
2903 }
2904
2905 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
2906 {
2907     return env->pstate & PSTATE_SP;
2908 }
2909
2910 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
2911 {
2912     update_spsel(env, val);
2913 }
2914
2915 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2916                         uint64_t value)
2917 {
2918     ARMCPU *cpu = arm_env_get_cpu(env);
2919
2920     if (raw_read(env, ri) == value) {
2921         /* Skip the TLB flush if nothing actually changed; Linux likes
2922          * to do a lot of pointless SCTLR writes.
2923          */
2924         return;
2925     }
2926
2927     raw_write(env, ri, value);
2928     /* ??? Lots of these bits are not implemented.  */
2929     /* This may enable/disable the MMU, so do a TLB flush.  */
2930     tlb_flush(CPU(cpu), 1);
2931 }
2932
2933 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
2934                                      bool isread)
2935 {
2936     if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
2937         return CP_ACCESS_TRAP_EL2;
2938     }
2939     if (env->cp15.cptr_el[3] & CPTR_TFP) {
2940         return CP_ACCESS_TRAP_EL3;
2941     }
2942     return CP_ACCESS_OK;
2943 }
2944
2945 static const ARMCPRegInfo v8_cp_reginfo[] = {
2946     /* Minimal set of EL0-visible registers. This will need to be expanded
2947      * significantly for system emulation of AArch64 CPUs.
2948      */
2949     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
2950       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
2951       .access = PL0_RW, .type = ARM_CP_NZCV },
2952     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
2953       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
2954       .type = ARM_CP_NO_RAW,
2955       .access = PL0_RW, .accessfn = aa64_daif_access,
2956       .fieldoffset = offsetof(CPUARMState, daif),
2957       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
2958     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
2959       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
2960       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
2961     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
2962       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
2963       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
2964     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
2965       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
2966       .access = PL0_R, .type = ARM_CP_NO_RAW,
2967       .readfn = aa64_dczid_read },
2968     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
2969       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
2970       .access = PL0_W, .type = ARM_CP_DC_ZVA,
2971 #ifndef CONFIG_USER_ONLY
2972       /* Avoid overhead of an access check that always passes in user-mode */
2973       .accessfn = aa64_zva_access,
2974 #endif
2975     },
2976     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
2977       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
2978       .access = PL1_R, .type = ARM_CP_CURRENTEL },
2979     /* Cache ops: all NOPs since we don't emulate caches */
2980     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
2981       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2982       .access = PL1_W, .type = ARM_CP_NOP },
2983     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
2984       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2985       .access = PL1_W, .type = ARM_CP_NOP },
2986     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
2987       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
2988       .access = PL0_W, .type = ARM_CP_NOP,
2989       .accessfn = aa64_cacheop_access },
2990     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
2991       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2992       .access = PL1_W, .type = ARM_CP_NOP },
2993     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
2994       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2995       .access = PL1_W, .type = ARM_CP_NOP },
2996     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
2997       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
2998       .access = PL0_W, .type = ARM_CP_NOP,
2999       .accessfn = aa64_cacheop_access },
3000     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
3001       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3002       .access = PL1_W, .type = ARM_CP_NOP },
3003     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
3004       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
3005       .access = PL0_W, .type = ARM_CP_NOP,
3006       .accessfn = aa64_cacheop_access },
3007     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
3008       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
3009       .access = PL0_W, .type = ARM_CP_NOP,
3010       .accessfn = aa64_cacheop_access },
3011     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
3012       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3013       .access = PL1_W, .type = ARM_CP_NOP },
3014     /* TLBI operations */
3015     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
3016       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
3017       .access = PL1_W, .type = ARM_CP_NO_RAW,
3018       .writefn = tlbi_aa64_vmalle1is_write },
3019     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
3020       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
3021       .access = PL1_W, .type = ARM_CP_NO_RAW,
3022       .writefn = tlbi_aa64_vae1is_write },
3023     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
3024       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
3025       .access = PL1_W, .type = ARM_CP_NO_RAW,
3026       .writefn = tlbi_aa64_vmalle1is_write },
3027     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
3028       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
3029       .access = PL1_W, .type = ARM_CP_NO_RAW,
3030       .writefn = tlbi_aa64_vae1is_write },
3031     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
3032       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3033       .access = PL1_W, .type = ARM_CP_NO_RAW,
3034       .writefn = tlbi_aa64_vae1is_write },
3035     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
3036       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3037       .access = PL1_W, .type = ARM_CP_NO_RAW,
3038       .writefn = tlbi_aa64_vae1is_write },
3039     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
3040       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
3041       .access = PL1_W, .type = ARM_CP_NO_RAW,
3042       .writefn = tlbi_aa64_vmalle1_write },
3043     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
3044       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
3045       .access = PL1_W, .type = ARM_CP_NO_RAW,
3046       .writefn = tlbi_aa64_vae1_write },
3047     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
3048       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
3049       .access = PL1_W, .type = ARM_CP_NO_RAW,
3050       .writefn = tlbi_aa64_vmalle1_write },
3051     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
3052       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
3053       .access = PL1_W, .type = ARM_CP_NO_RAW,
3054       .writefn = tlbi_aa64_vae1_write },
3055     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
3056       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3057       .access = PL1_W, .type = ARM_CP_NO_RAW,
3058       .writefn = tlbi_aa64_vae1_write },
3059     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
3060       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3061       .access = PL1_W, .type = ARM_CP_NO_RAW,
3062       .writefn = tlbi_aa64_vae1_write },
3063     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
3064       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
3065       .access = PL2_W, .type = ARM_CP_NO_RAW,
3066       .writefn = tlbi_aa64_ipas2e1is_write },
3067     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
3068       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
3069       .access = PL2_W, .type = ARM_CP_NO_RAW,
3070       .writefn = tlbi_aa64_ipas2e1is_write },
3071     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
3072       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
3073       .access = PL2_W, .type = ARM_CP_NO_RAW,
3074       .writefn = tlbi_aa64_alle1is_write },
3075     { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
3076       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
3077       .access = PL2_W, .type = ARM_CP_NO_RAW,
3078       .writefn = tlbi_aa64_alle1is_write },
3079     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
3080       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
3081       .access = PL2_W, .type = ARM_CP_NO_RAW,
3082       .writefn = tlbi_aa64_ipas2e1_write },
3083     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
3084       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
3085       .access = PL2_W, .type = ARM_CP_NO_RAW,
3086       .writefn = tlbi_aa64_ipas2e1_write },
3087     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
3088       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
3089       .access = PL2_W, .type = ARM_CP_NO_RAW,
3090       .writefn = tlbi_aa64_alle1_write },
3091     { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
3092       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
3093       .access = PL2_W, .type = ARM_CP_NO_RAW,
3094       .writefn = tlbi_aa64_alle1is_write },
3095 #ifndef CONFIG_USER_ONLY
3096     /* 64 bit address translation operations */
3097     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
3098       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
3099       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3100     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
3101       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
3102       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3103     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
3104       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
3105       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3106     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
3107       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
3108       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3109     { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
3110       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
3111       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3112     { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
3113       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
3114       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3115     { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
3116       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
3117       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3118     { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
3119       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
3120       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3121     /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3122     { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
3123       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
3124       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3125     { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
3126       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
3127       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3128     { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
3129       .type = ARM_CP_ALIAS,
3130       .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
3131       .access = PL1_RW, .resetvalue = 0,
3132       .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
3133       .writefn = par_write },
3134 #endif
3135     /* TLB invalidate last level of translation table walk */
3136     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3137       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
3138     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3139       .type = ARM_CP_NO_RAW, .access = PL1_W,
3140       .writefn = tlbimvaa_is_write },
3141     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3142       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
3143     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3144       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
3145     /* 32 bit cache operations */
3146     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3147       .type = ARM_CP_NOP, .access = PL1_W },
3148     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
3149       .type = ARM_CP_NOP, .access = PL1_W },
3150     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3151       .type = ARM_CP_NOP, .access = PL1_W },
3152     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
3153       .type = ARM_CP_NOP, .access = PL1_W },
3154     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
3155       .type = ARM_CP_NOP, .access = PL1_W },
3156     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
3157       .type = ARM_CP_NOP, .access = PL1_W },
3158     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3159       .type = ARM_CP_NOP, .access = PL1_W },
3160     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3161       .type = ARM_CP_NOP, .access = PL1_W },
3162     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
3163       .type = ARM_CP_NOP, .access = PL1_W },
3164     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3165       .type = ARM_CP_NOP, .access = PL1_W },
3166     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
3167       .type = ARM_CP_NOP, .access = PL1_W },
3168     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
3169       .type = ARM_CP_NOP, .access = PL1_W },
3170     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3171       .type = ARM_CP_NOP, .access = PL1_W },
3172     /* MMU Domain access control / MPU write buffer control */
3173     { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
3174       .access = PL1_RW, .resetvalue = 0,
3175       .writefn = dacr_write, .raw_writefn = raw_write,
3176       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
3177                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
3178     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
3179       .type = ARM_CP_ALIAS,
3180       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
3181       .access = PL1_RW,
3182       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
3183     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
3184       .type = ARM_CP_ALIAS,
3185       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
3186       .access = PL1_RW,
3187       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
3188     /* We rely on the access checks not allowing the guest to write to the
3189      * state field when SPSel indicates that it's being used as the stack
3190      * pointer.
3191      */
3192     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
3193       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
3194       .access = PL1_RW, .accessfn = sp_el0_access,
3195       .type = ARM_CP_ALIAS,
3196       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
3197     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
3198       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
3199       .access = PL2_RW, .type = ARM_CP_ALIAS,
3200       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
3201     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
3202       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
3203       .type = ARM_CP_NO_RAW,
3204       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
3205     { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
3206       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
3207       .type = ARM_CP_ALIAS,
3208       .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
3209       .access = PL2_RW, .accessfn = fpexc32_access },
3210     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
3211       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
3212       .access = PL2_RW, .resetvalue = 0,
3213       .writefn = dacr_write, .raw_writefn = raw_write,
3214       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
3215     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
3216       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
3217       .access = PL2_RW, .resetvalue = 0,
3218       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
3219     { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
3220       .type = ARM_CP_ALIAS,
3221       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
3222       .access = PL2_RW,
3223       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
3224     { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
3225       .type = ARM_CP_ALIAS,
3226       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
3227       .access = PL2_RW,
3228       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
3229     { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
3230       .type = ARM_CP_ALIAS,
3231       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
3232       .access = PL2_RW,
3233       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
3234     { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
3235       .type = ARM_CP_ALIAS,
3236       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
3237       .access = PL2_RW,
3238       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
3239     REGINFO_SENTINEL
3240 };
3241
3242 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
3243 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
3244     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3245       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3246       .access = PL2_RW,
3247       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3248     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3249       .type = ARM_CP_NO_RAW,
3250       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3251       .access = PL2_RW,
3252       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3253     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3254       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3255       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3256     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3257       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3258       .access = PL2_RW, .type = ARM_CP_CONST,
3259       .resetvalue = 0 },
3260     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3261       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3262       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3263     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3264       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3265       .access = PL2_RW, .type = ARM_CP_CONST,
3266       .resetvalue = 0 },
3267     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3268       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3269       .access = PL2_RW, .type = ARM_CP_CONST,
3270       .resetvalue = 0 },
3271     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3272       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3273       .access = PL2_RW, .type = ARM_CP_CONST,
3274       .resetvalue = 0 },
3275     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3276       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3277       .access = PL2_RW, .type = ARM_CP_CONST,
3278       .resetvalue = 0 },
3279     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3280       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3281       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3282     { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
3283       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3284       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3285       .type = ARM_CP_CONST, .resetvalue = 0 },
3286     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3287       .cp = 15, .opc1 = 6, .crm = 2,
3288       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3289       .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
3290     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3291       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3292       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3293     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3294       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3295       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3296     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3297       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3298       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3299     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3300       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3301       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3302     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3303       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3304       .resetvalue = 0 },
3305     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3306       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3307       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3308     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3309       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3310       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3311     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3312       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3313       .resetvalue = 0 },
3314     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3315       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3316       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3317     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3318       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3319       .resetvalue = 0 },
3320     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3321       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3322       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3323     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3324       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3325       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3326     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3327       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3328       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3329     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
3330       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3331       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3332       .type = ARM_CP_CONST, .resetvalue = 0 },
3333     REGINFO_SENTINEL
3334 };
3335
3336 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3337 {
3338     ARMCPU *cpu = arm_env_get_cpu(env);
3339     uint64_t valid_mask = HCR_MASK;
3340
3341     if (arm_feature(env, ARM_FEATURE_EL3)) {
3342         valid_mask &= ~HCR_HCD;
3343     } else {
3344         valid_mask &= ~HCR_TSC;
3345     }
3346
3347     /* Clear RES0 bits.  */
3348     value &= valid_mask;
3349
3350     /* These bits change the MMU setup:
3351      * HCR_VM enables stage 2 translation
3352      * HCR_PTW forbids certain page-table setups
3353      * HCR_DC Disables stage1 and enables stage2 translation
3354      */
3355     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
3356         tlb_flush(CPU(cpu), 1);
3357     }
3358     raw_write(env, ri, value);
3359 }
3360
3361 static const ARMCPRegInfo el2_cp_reginfo[] = {
3362     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3363       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3364       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
3365       .writefn = hcr_write },
3366     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
3367       .type = ARM_CP_ALIAS,
3368       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
3369       .access = PL2_RW,
3370       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
3371     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
3372       .type = ARM_CP_ALIAS,
3373       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
3374       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
3375     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
3376       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
3377       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
3378     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
3379       .type = ARM_CP_ALIAS,
3380       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
3381       .access = PL2_RW,
3382       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
3383     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3384       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3385       .access = PL2_RW, .writefn = vbar_write,
3386       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
3387       .resetvalue = 0 },
3388     { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
3389       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
3390       .access = PL3_RW, .type = ARM_CP_ALIAS,
3391       .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
3392     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3393       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3394       .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
3395       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
3396     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3397       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3398       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
3399       .resetvalue = 0 },
3400     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3401       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3402       .access = PL2_RW, .type = ARM_CP_ALIAS,
3403       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
3404     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3405       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3406       .access = PL2_RW, .type = ARM_CP_CONST,
3407       .resetvalue = 0 },
3408     /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3409     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3410       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3411       .access = PL2_RW, .type = ARM_CP_CONST,
3412       .resetvalue = 0 },
3413     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3414       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3415       .access = PL2_RW, .type = ARM_CP_CONST,
3416       .resetvalue = 0 },
3417     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3418       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3419       .access = PL2_RW, .type = ARM_CP_CONST,
3420       .resetvalue = 0 },
3421     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3422       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3423       .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
3424       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3425       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
3426     { .name = "VTCR", .state = ARM_CP_STATE_AA32,
3427       .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3428       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3429       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3430     { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
3431       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3432       .access = PL2_RW, .type = ARM_CP_ALIAS,
3433       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3434     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3435       .cp = 15, .opc1 = 6, .crm = 2,
3436       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3437       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3438       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
3439       .writefn = vttbr_write },
3440     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3441       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3442       .access = PL2_RW, .writefn = vttbr_write,
3443       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
3444     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3445       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3446       .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3447       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
3448     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3449       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3450       .access = PL2_RW, .resetvalue = 0,
3451       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
3452     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3453       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3454       .access = PL2_RW, .resetvalue = 0,
3455       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3456     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3457       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3458       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3459     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
3460       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
3461       .type = ARM_CP_NO_RAW, .access = PL2_W,
3462       .writefn = tlbi_aa64_alle2_write },
3463     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
3464       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
3465       .type = ARM_CP_NO_RAW, .access = PL2_W,
3466       .writefn = tlbi_aa64_vae2_write },
3467     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
3468       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
3469       .access = PL2_W, .type = ARM_CP_NO_RAW,
3470       .writefn = tlbi_aa64_vae2_write },
3471     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
3472       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
3473       .access = PL2_W, .type = ARM_CP_NO_RAW,
3474       .writefn = tlbi_aa64_alle2is_write },
3475     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
3476       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
3477       .type = ARM_CP_NO_RAW, .access = PL2_W,
3478       .writefn = tlbi_aa64_vae2is_write },
3479     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
3480       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
3481       .access = PL2_W, .type = ARM_CP_NO_RAW,
3482       .writefn = tlbi_aa64_vae2is_write },
3483 #ifndef CONFIG_USER_ONLY
3484     /* Unlike the other EL2-related AT operations, these must
3485      * UNDEF from EL3 if EL2 is not implemented, which is why we
3486      * define them here rather than with the rest of the AT ops.
3487      */
3488     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
3489       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3490       .access = PL2_W, .accessfn = at_s1e2_access,
3491       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3492     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
3493       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3494       .access = PL2_W, .accessfn = at_s1e2_access,
3495       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3496     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3497      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3498      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3499      * to behave as if SCR.NS was 1.
3500      */
3501     { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3502       .access = PL2_W,
3503       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3504     { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3505       .access = PL2_W,
3506       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3507     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3508       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3509       /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3510        * reset values as IMPDEF. We choose to reset to 3 to comply with
3511        * both ARMv7 and ARMv8.
3512        */
3513       .access = PL2_RW, .resetvalue = 3,
3514       .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
3515     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3516       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3517       .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
3518       .writefn = gt_cntvoff_write,
3519       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3520     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3521       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
3522       .writefn = gt_cntvoff_write,
3523       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3524     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3525       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3526       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3527       .type = ARM_CP_IO, .access = PL2_RW,
3528       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3529     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3530       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3531       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
3532       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3533     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3534       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3535       .type = ARM_CP_IO, .access = PL2_RW,
3536       .resetfn = gt_hyp_timer_reset,
3537       .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
3538     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3539       .type = ARM_CP_IO,
3540       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3541       .access = PL2_RW,
3542       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
3543       .resetvalue = 0,
3544       .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
3545 #endif
3546     /* The only field of MDCR_EL2 that has a defined architectural reset value
3547      * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
3548      * don't impelment any PMU event counters, so using zero as a reset
3549      * value for MDCR_EL2 is okay
3550      */
3551     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3552       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3553       .access = PL2_RW, .resetvalue = 0,
3554       .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
3555     { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
3556       .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3557       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3558       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3559     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
3560       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3561       .access = PL2_RW,
3562       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3563     REGINFO_SENTINEL
3564 };
3565
3566 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
3567                                    bool isread)
3568 {
3569     /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
3570      * At Secure EL1 it traps to EL3.
3571      */
3572     if (arm_current_el(env) == 3) {
3573         return CP_ACCESS_OK;
3574     }
3575     if (arm_is_secure_below_el3(env)) {
3576         return CP_ACCESS_TRAP_EL3;
3577     }
3578     /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
3579     if (isread) {
3580         return CP_ACCESS_OK;
3581     }
3582     return CP_ACCESS_TRAP_UNCATEGORIZED;
3583 }
3584
3585 static const ARMCPRegInfo el3_cp_reginfo[] = {
3586     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
3587       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
3588       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
3589       .resetvalue = 0, .writefn = scr_write },
3590     { .name = "SCR",  .type = ARM_CP_ALIAS,
3591       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
3592       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3593       .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
3594       .writefn = scr_write },
3595     { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
3596       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
3597       .resetvalue = 0,
3598       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
3599     { .name = "SDCR", .type = ARM_CP_ALIAS,
3600       .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
3601       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3602       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
3603     { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
3604       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
3605       .access = PL3_RW, .resetvalue = 0,
3606       .fieldoffset = offsetof(CPUARMState, cp15.sder) },
3607     { .name = "SDER",
3608       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
3609       .access = PL3_RW, .resetvalue = 0,
3610       .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
3611     { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
3612       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3613       .writefn = vbar_write, .resetvalue = 0,
3614       .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
3615     { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
3616       .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */
3617       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
3618       .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3619       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },
3620     { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
3621       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
3622       .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
3623       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
3624     { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
3625       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
3626       .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
3627       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3628       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
3629     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
3630       .type = ARM_CP_ALIAS,
3631       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
3632       .access = PL3_RW,
3633       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
3634     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
3635       .type = ARM_CP_ALIAS,
3636       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
3637       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
3638     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
3639       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
3640       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
3641     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
3642       .type = ARM_CP_ALIAS,
3643       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
3644       .access = PL3_RW,
3645       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
3646     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
3647       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
3648       .access = PL3_RW, .writefn = vbar_write,
3649       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
3650       .resetvalue = 0 },
3651     { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
3652       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
3653       .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
3654       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
3655     { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
3656       .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
3657       .access = PL3_RW, .resetvalue = 0,
3658       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
3659     { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
3660       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
3661       .access = PL3_RW, .type = ARM_CP_CONST,
3662       .resetvalue = 0 },
3663     { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
3664       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
3665       .access = PL3_RW, .type = ARM_CP_CONST,
3666       .resetvalue = 0 },
3667     { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
3668       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
3669       .access = PL3_RW, .type = ARM_CP_CONST,
3670       .resetvalue = 0 },
3671     { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
3672       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
3673       .access = PL3_W, .type = ARM_CP_NO_RAW,
3674       .writefn = tlbi_aa64_alle3is_write },
3675     { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
3676       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
3677       .access = PL3_W, .type = ARM_CP_NO_RAW,
3678       .writefn = tlbi_aa64_vae3is_write },
3679     { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
3680       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
3681       .access = PL3_W, .type = ARM_CP_NO_RAW,
3682       .writefn = tlbi_aa64_vae3is_write },
3683     { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
3684       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
3685       .access = PL3_W, .type = ARM_CP_NO_RAW,
3686       .writefn = tlbi_aa64_alle3_write },
3687     { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
3688       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
3689       .access = PL3_W, .type = ARM_CP_NO_RAW,
3690       .writefn = tlbi_aa64_vae3_write },
3691     { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
3692       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
3693       .access = PL3_W, .type = ARM_CP_NO_RAW,
3694       .writefn = tlbi_aa64_vae3_write },
3695     REGINFO_SENTINEL
3696 };
3697
3698 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
3699                                      bool isread)
3700 {
3701     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
3702      * but the AArch32 CTR has its own reginfo struct)
3703      */
3704     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
3705         return CP_ACCESS_TRAP;
3706     }
3707     return CP_ACCESS_OK;
3708 }
3709
3710 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
3711                         uint64_t value)
3712 {
3713     /* Writes to OSLAR_EL1 may update the OS lock status, which can be
3714      * read via a bit in OSLSR_EL1.
3715      */
3716     int oslock;
3717
3718     if (ri->state == ARM_CP_STATE_AA32) {
3719         oslock = (value == 0xC5ACCE55);
3720     } else {
3721         oslock = value & 1;
3722     }
3723
3724     env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
3725 }
3726
3727 static const ARMCPRegInfo debug_cp_reginfo[] = {
3728     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
3729      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
3730      * unlike DBGDRAR it is never accessible from EL0.
3731      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
3732      * accessor.
3733      */
3734     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
3735       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3736     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
3737       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3738       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3739     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3740       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3741     /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
3742     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
3743       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3744       .access = PL1_RW,
3745       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
3746       .resetvalue = 0 },
3747     /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
3748      * We don't implement the configurable EL0 access.
3749      */
3750     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
3751       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3752       .type = ARM_CP_ALIAS,
3753       .access = PL1_R,
3754       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
3755     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
3756       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
3757       .access = PL1_W, .type = ARM_CP_NO_RAW,
3758       .writefn = oslar_write },
3759     { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
3760       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
3761       .access = PL1_R, .resetvalue = 10,
3762       .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
3763     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
3764     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
3765       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
3766       .access = PL1_RW, .type = ARM_CP_NOP },
3767     /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
3768      * implement vector catch debug events yet.
3769      */
3770     { .name = "DBGVCR",
3771       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3772       .access = PL1_RW, .type = ARM_CP_NOP },
3773     REGINFO_SENTINEL
3774 };
3775
3776 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
3777     /* 64 bit access versions of the (dummy) debug registers */
3778     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
3779       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3780     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
3781       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3782     REGINFO_SENTINEL
3783 };
3784
3785 void hw_watchpoint_update(ARMCPU *cpu, int n)
3786 {
3787     CPUARMState *env = &cpu->env;
3788     vaddr len = 0;
3789     vaddr wvr = env->cp15.dbgwvr[n];
3790     uint64_t wcr = env->cp15.dbgwcr[n];
3791     int mask;
3792     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
3793
3794     if (env->cpu_watchpoint[n]) {
3795         cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
3796         env->cpu_watchpoint[n] = NULL;
3797     }
3798
3799     if (!extract64(wcr, 0, 1)) {
3800         /* E bit clear : watchpoint disabled */
3801         return;
3802     }
3803
3804     switch (extract64(wcr, 3, 2)) {
3805     case 0:
3806         /* LSC 00 is reserved and must behave as if the wp is disabled */
3807         return;
3808     case 1:
3809         flags |= BP_MEM_READ;
3810         break;
3811     case 2:
3812         flags |= BP_MEM_WRITE;
3813         break;
3814     case 3:
3815         flags |= BP_MEM_ACCESS;
3816         break;
3817     }
3818
3819     /* Attempts to use both MASK and BAS fields simultaneously are
3820      * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
3821      * thus generating a watchpoint for every byte in the masked region.
3822      */
3823     mask = extract64(wcr, 24, 4);
3824     if (mask == 1 || mask == 2) {
3825         /* Reserved values of MASK; we must act as if the mask value was
3826          * some non-reserved value, or as if the watchpoint were disabled.
3827          * We choose the latter.
3828          */
3829         return;
3830     } else if (mask) {
3831         /* Watchpoint covers an aligned area up to 2GB in size */
3832         len = 1ULL << mask;
3833         /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
3834          * whether the watchpoint fires when the unmasked bits match; we opt
3835          * to generate the exceptions.
3836          */
3837         wvr &= ~(len - 1);
3838     } else {
3839         /* Watchpoint covers bytes defined by the byte address select bits */
3840         int bas = extract64(wcr, 5, 8);
3841         int basstart;
3842
3843         if (bas == 0) {
3844             /* This must act as if the watchpoint is disabled */
3845             return;
3846         }
3847
3848         if (extract64(wvr, 2, 1)) {
3849             /* Deprecated case of an only 4-aligned address. BAS[7:4] are
3850              * ignored, and BAS[3:0] define which bytes to watch.
3851              */
3852             bas &= 0xf;
3853         }
3854         /* The BAS bits are supposed to be programmed to indicate a contiguous
3855          * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
3856          * we fire for each byte in the word/doubleword addressed by the WVR.
3857          * We choose to ignore any non-zero bits after the first range of 1s.
3858          */
3859         basstart = ctz32(bas);
3860         len = cto32(bas >> basstart);
3861         wvr += basstart;
3862     }
3863
3864     cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
3865                           &env->cpu_watchpoint[n]);
3866 }
3867
3868 void hw_watchpoint_update_all(ARMCPU *cpu)
3869 {
3870     int i;
3871     CPUARMState *env = &cpu->env;
3872
3873     /* Completely clear out existing QEMU watchpoints and our array, to
3874      * avoid possible stale entries following migration load.
3875      */
3876     cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
3877     memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
3878
3879     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
3880         hw_watchpoint_update(cpu, i);
3881     }
3882 }
3883
3884 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3885                          uint64_t value)
3886 {
3887     ARMCPU *cpu = arm_env_get_cpu(env);
3888     int i = ri->crm;
3889
3890     /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
3891      * register reads and behaves as if values written are sign extended.
3892      * Bits [1:0] are RES0.
3893      */
3894     value = sextract64(value, 0, 49) & ~3ULL;
3895
3896     raw_write(env, ri, value);
3897     hw_watchpoint_update(cpu, i);
3898 }
3899
3900 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3901                          uint64_t value)
3902 {
3903     ARMCPU *cpu = arm_env_get_cpu(env);
3904     int i = ri->crm;
3905
3906     raw_write(env, ri, value);
3907     hw_watchpoint_update(cpu, i);
3908 }
3909
3910 void hw_breakpoint_update(ARMCPU *cpu, int n)
3911 {
3912     CPUARMState *env = &cpu->env;
3913     uint64_t bvr = env->cp15.dbgbvr[n];
3914     uint64_t bcr = env->cp15.dbgbcr[n];
3915     vaddr addr;
3916     int bt;
3917     int flags = BP_CPU;
3918
3919     if (env->cpu_breakpoint[n]) {
3920         cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
3921         env->cpu_breakpoint[n] = NULL;
3922     }
3923
3924     if (!extract64(bcr, 0, 1)) {
3925         /* E bit clear : watchpoint disabled */
3926         return;
3927     }
3928
3929     bt = extract64(bcr, 20, 4);
3930
3931     switch (bt) {
3932     case 4: /* unlinked address mismatch (reserved if AArch64) */
3933     case 5: /* linked address mismatch (reserved if AArch64) */
3934         qemu_log_mask(LOG_UNIMP,
3935                       "arm: address mismatch breakpoint types not implemented");
3936         return;
3937     case 0: /* unlinked address match */
3938     case 1: /* linked address match */
3939     {
3940         /* Bits [63:49] are hardwired to the value of bit [48]; that is,
3941          * we behave as if the register was sign extended. Bits [1:0] are
3942          * RES0. The BAS field is used to allow setting breakpoints on 16
3943          * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
3944          * a bp will fire if the addresses covered by the bp and the addresses
3945          * covered by the insn overlap but the insn doesn't start at the
3946          * start of the bp address range. We choose to require the insn and
3947          * the bp to have the same address. The constraints on writing to
3948          * BAS enforced in dbgbcr_write mean we have only four cases:
3949          *  0b0000  => no breakpoint
3950          *  0b0011  => breakpoint on addr
3951          *  0b1100  => breakpoint on addr + 2
3952          *  0b1111  => breakpoint on addr
3953          * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
3954          */
3955         int bas = extract64(bcr, 5, 4);
3956         addr = sextract64(bvr, 0, 49) & ~3ULL;
3957         if (bas == 0) {
3958             return;
3959         }
3960         if (bas == 0xc) {
3961             addr += 2;
3962         }
3963         break;
3964     }
3965     case 2: /* unlinked context ID match */
3966     case 8: /* unlinked VMID match (reserved if no EL2) */
3967     case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
3968         qemu_log_mask(LOG_UNIMP,
3969                       "arm: unlinked context breakpoint types not implemented");
3970         return;
3971     case 9: /* linked VMID match (reserved if no EL2) */
3972     case 11: /* linked context ID and VMID match (reserved if no EL2) */
3973     case 3: /* linked context ID match */
3974     default:
3975         /* We must generate no events for Linked context matches (unless
3976          * they are linked to by some other bp/wp, which is handled in
3977          * updates for the linking bp/wp). We choose to also generate no events
3978          * for reserved values.
3979          */
3980         return;
3981     }
3982
3983     cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
3984 }
3985
3986 void hw_breakpoint_update_all(ARMCPU *cpu)
3987 {
3988     int i;
3989     CPUARMState *env = &cpu->env;
3990
3991     /* Completely clear out existing QEMU breakpoints and our array, to
3992      * avoid possible stale entries following migration load.
3993      */
3994     cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
3995     memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
3996
3997     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
3998         hw_breakpoint_update(cpu, i);
3999     }
4000 }
4001
4002 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4003                          uint64_t value)
4004 {
4005     ARMCPU *cpu = arm_env_get_cpu(env);
4006     int i = ri->crm;
4007
4008     raw_write(env, ri, value);
4009     hw_breakpoint_update(cpu, i);
4010 }
4011
4012 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4013                          uint64_t value)
4014 {
4015     ARMCPU *cpu = arm_env_get_cpu(env);
4016     int i = ri->crm;
4017
4018     /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
4019      * copy of BAS[0].
4020      */
4021     value = deposit64(value, 6, 1, extract64(value, 5, 1));
4022     value = deposit64(value, 8, 1, extract64(value, 7, 1));
4023
4024     raw_write(env, ri, value);
4025     hw_breakpoint_update(cpu, i);
4026 }
4027
4028 static void define_debug_regs(ARMCPU *cpu)
4029 {
4030     /* Define v7 and v8 architectural debug registers.
4031      * These are just dummy implementations for now.
4032      */
4033     int i;
4034     int wrps, brps, ctx_cmps;
4035     ARMCPRegInfo dbgdidr = {
4036         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
4037         .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
4038     };
4039
4040     /* Note that all these register fields hold "number of Xs minus 1". */
4041     brps = extract32(cpu->dbgdidr, 24, 4);
4042     wrps = extract32(cpu->dbgdidr, 28, 4);
4043     ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
4044
4045     assert(ctx_cmps <= brps);
4046
4047     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
4048      * of the debug registers such as number of breakpoints;
4049      * check that if they both exist then they agree.
4050      */
4051     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
4052         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
4053         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
4054         assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
4055     }
4056
4057     define_one_arm_cp_reg(cpu, &dbgdidr);
4058     define_arm_cp_regs(cpu, debug_cp_reginfo);
4059
4060     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
4061         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
4062     }
4063
4064     for (i = 0; i < brps + 1; i++) {
4065         ARMCPRegInfo dbgregs[] = {
4066             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
4067               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
4068               .access = PL1_RW,
4069               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
4070               .writefn = dbgbvr_write, .raw_writefn = raw_write
4071             },
4072             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
4073               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
4074               .access = PL1_RW,
4075               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
4076               .writefn = dbgbcr_write, .raw_writefn = raw_write
4077             },
4078             REGINFO_SENTINEL
4079         };
4080         define_arm_cp_regs(cpu, dbgregs);
4081     }
4082
4083     for (i = 0; i < wrps + 1; i++) {
4084         ARMCPRegInfo dbgregs[] = {
4085             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
4086               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
4087               .access = PL1_RW,
4088               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
4089               .writefn = dbgwvr_write, .raw_writefn = raw_write
4090             },
4091             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
4092               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
4093               .access = PL1_RW,
4094               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
4095               .writefn = dbgwcr_write, .raw_writefn = raw_write
4096             },
4097             REGINFO_SENTINEL
4098         };
4099         define_arm_cp_regs(cpu, dbgregs);
4100     }
4101 }
4102
4103 void register_cp_regs_for_features(ARMCPU *cpu)
4104 {
4105     /* Register all the coprocessor registers based on feature bits */
4106     CPUARMState *env = &cpu->env;
4107     if (arm_feature(env, ARM_FEATURE_M)) {
4108         /* M profile has no coprocessor registers */
4109         return;
4110     }
4111
4112     define_arm_cp_regs(cpu, cp_reginfo);
4113     if (!arm_feature(env, ARM_FEATURE_V8)) {
4114         /* Must go early as it is full of wildcards that may be
4115          * overridden by later definitions.
4116          */
4117         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
4118     }
4119
4120     if (arm_feature(env, ARM_FEATURE_V6)) {
4121         /* The ID registers all have impdef reset values */
4122         ARMCPRegInfo v6_idregs[] = {
4123             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
4124               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
4125               .access = PL1_R, .type = ARM_CP_CONST,
4126               .resetvalue = cpu->id_pfr0 },
4127             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
4128               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
4129               .access = PL1_R, .type = ARM_CP_CONST,
4130               .resetvalue = cpu->id_pfr1 },
4131             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
4132               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
4133               .access = PL1_R, .type = ARM_CP_CONST,
4134               .resetvalue = cpu->id_dfr0 },
4135             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
4136               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
4137               .access = PL1_R, .type = ARM_CP_CONST,
4138               .resetvalue = cpu->id_afr0 },
4139             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
4140               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
4141               .access = PL1_R, .type = ARM_CP_CONST,
4142               .resetvalue = cpu->id_mmfr0 },
4143             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
4144               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
4145               .access = PL1_R, .type = ARM_CP_CONST,
4146               .resetvalue = cpu->id_mmfr1 },
4147             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
4148               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
4149               .access = PL1_R, .type = ARM_CP_CONST,
4150               .resetvalue = cpu->id_mmfr2 },
4151             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
4152               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
4153               .access = PL1_R, .type = ARM_CP_CONST,
4154               .resetvalue = cpu->id_mmfr3 },
4155             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
4156               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
4157               .access = PL1_R, .type = ARM_CP_CONST,
4158               .resetvalue = cpu->id_isar0 },
4159             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
4160               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
4161               .access = PL1_R, .type = ARM_CP_CONST,
4162               .resetvalue = cpu->id_isar1 },
4163             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
4164               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
4165               .access = PL1_R, .type = ARM_CP_CONST,
4166               .resetvalue = cpu->id_isar2 },
4167             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
4168               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
4169               .access = PL1_R, .type = ARM_CP_CONST,
4170               .resetvalue = cpu->id_isar3 },
4171             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
4172               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
4173               .access = PL1_R, .type = ARM_CP_CONST,
4174               .resetvalue = cpu->id_isar4 },
4175             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
4176               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
4177               .access = PL1_R, .type = ARM_CP_CONST,
4178               .resetvalue = cpu->id_isar5 },
4179             /* 6..7 are as yet unallocated and must RAZ */
4180             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
4181               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
4182               .resetvalue = 0 },
4183             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
4184               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
4185               .resetvalue = 0 },
4186             REGINFO_SENTINEL
4187         };
4188         define_arm_cp_regs(cpu, v6_idregs);
4189         define_arm_cp_regs(cpu, v6_cp_reginfo);
4190     } else {
4191         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
4192     }
4193     if (arm_feature(env, ARM_FEATURE_V6K)) {
4194         define_arm_cp_regs(cpu, v6k_cp_reginfo);
4195     }
4196     if (arm_feature(env, ARM_FEATURE_V7MP) &&
4197         !arm_feature(env, ARM_FEATURE_MPU)) {
4198         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
4199     }
4200     if (arm_feature(env, ARM_FEATURE_V7)) {
4201         /* v7 performance monitor control register: same implementor
4202          * field as main ID register, and we implement only the cycle
4203          * count register.
4204          */
4205 #ifndef CONFIG_USER_ONLY
4206         ARMCPRegInfo pmcr = {
4207             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
4208             .access = PL0_RW,
4209             .type = ARM_CP_IO | ARM_CP_ALIAS,
4210             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
4211             .accessfn = pmreg_access, .writefn = pmcr_write,
4212             .raw_writefn = raw_write,
4213         };
4214         ARMCPRegInfo pmcr64 = {
4215             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
4216             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
4217             .access = PL0_RW, .accessfn = pmreg_access,
4218             .type = ARM_CP_IO,
4219             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
4220             .resetvalue = cpu->midr & 0xff000000,
4221             .writefn = pmcr_write, .raw_writefn = raw_write,
4222         };
4223         define_one_arm_cp_reg(cpu, &pmcr);
4224         define_one_arm_cp_reg(cpu, &pmcr64);
4225 #endif
4226         ARMCPRegInfo clidr = {
4227             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
4228             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
4229             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
4230         };
4231         define_one_arm_cp_reg(cpu, &clidr);
4232         define_arm_cp_regs(cpu, v7_cp_reginfo);
4233         define_debug_regs(cpu);
4234     } else {
4235         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
4236     }
4237     if (arm_feature(env, ARM_FEATURE_V8)) {
4238         /* AArch64 ID registers, which all have impdef reset values */
4239         ARMCPRegInfo v8_idregs[] = {
4240             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
4241               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
4242               .access = PL1_R, .type = ARM_CP_CONST,
4243               .resetvalue = cpu->id_aa64pfr0 },
4244             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
4245               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
4246               .access = PL1_R, .type = ARM_CP_CONST,
4247               .resetvalue = cpu->id_aa64pfr1},
4248             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
4249               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
4250               .access = PL1_R, .type = ARM_CP_CONST,
4251               /* We mask out the PMUVer field, because we don't currently
4252                * implement the PMU. Not advertising it prevents the guest
4253                * from trying to use it and getting UNDEFs on registers we
4254                * don't implement.
4255                */
4256               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
4257             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
4258               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
4259               .access = PL1_R, .type = ARM_CP_CONST,
4260               .resetvalue = cpu->id_aa64dfr1 },
4261             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
4262               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
4263               .access = PL1_R, .type = ARM_CP_CONST,
4264               .resetvalue = cpu->id_aa64afr0 },
4265             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
4266               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
4267               .access = PL1_R, .type = ARM_CP_CONST,
4268               .resetvalue = cpu->id_aa64afr1 },
4269             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
4270               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
4271               .access = PL1_R, .type = ARM_CP_CONST,
4272               .resetvalue = cpu->id_aa64isar0 },
4273             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
4274               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
4275               .access = PL1_R, .type = ARM_CP_CONST,
4276               .resetvalue = cpu->id_aa64isar1 },
4277             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
4278               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
4279               .access = PL1_R, .type = ARM_CP_CONST,
4280               .resetvalue = cpu->id_aa64mmfr0 },
4281             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
4282               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
4283               .access = PL1_R, .type = ARM_CP_CONST,
4284               .resetvalue = cpu->id_aa64mmfr1 },
4285             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
4286               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
4287               .access = PL1_R, .type = ARM_CP_CONST,
4288               .resetvalue = cpu->mvfr0 },
4289             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
4290               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
4291               .access = PL1_R, .type = ARM_CP_CONST,
4292               .resetvalue = cpu->mvfr1 },
4293             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
4294               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
4295               .access = PL1_R, .type = ARM_CP_CONST,
4296               .resetvalue = cpu->mvfr2 },
4297             REGINFO_SENTINEL
4298         };
4299         /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4300         if (!arm_feature(env, ARM_FEATURE_EL3) &&
4301             !arm_feature(env, ARM_FEATURE_EL2)) {
4302             ARMCPRegInfo rvbar = {
4303                 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
4304                 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
4305                 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
4306             };
4307             define_one_arm_cp_reg(cpu, &rvbar);
4308         }
4309         define_arm_cp_regs(cpu, v8_idregs);
4310         define_arm_cp_regs(cpu, v8_cp_reginfo);
4311     }
4312     if (arm_feature(env, ARM_FEATURE_EL2)) {
4313         uint64_t vmpidr_def = mpidr_read_val(env);
4314         ARMCPRegInfo vpidr_regs[] = {
4315             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
4316               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4317               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4318               .resetvalue = cpu->midr,
4319               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4320             { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
4321               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4322               .access = PL2_RW, .resetvalue = cpu->midr,
4323               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4324             { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
4325               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4326               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4327               .resetvalue = vmpidr_def,
4328               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4329             { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
4330               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4331               .access = PL2_RW,
4332               .resetvalue = vmpidr_def,
4333               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4334             REGINFO_SENTINEL
4335         };
4336         define_arm_cp_regs(cpu, vpidr_regs);
4337         define_arm_cp_regs(cpu, el2_cp_reginfo);
4338         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4339         if (!arm_feature(env, ARM_FEATURE_EL3)) {
4340             ARMCPRegInfo rvbar = {
4341                 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
4342                 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
4343                 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
4344             };
4345             define_one_arm_cp_reg(cpu, &rvbar);
4346         }
4347     } else {
4348         /* If EL2 is missing but higher ELs are enabled, we need to
4349          * register the no_el2 reginfos.
4350          */
4351         if (arm_feature(env, ARM_FEATURE_EL3)) {
4352             /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4353              * of MIDR_EL1 and MPIDR_EL1.
4354              */
4355             ARMCPRegInfo vpidr_regs[] = {
4356                 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4357                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4358                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4359                   .type = ARM_CP_CONST, .resetvalue = cpu->midr,
4360                   .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4361                 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4362                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4363                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4364                   .type = ARM_CP_NO_RAW,
4365                   .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
4366                 REGINFO_SENTINEL
4367             };
4368             define_arm_cp_regs(cpu, vpidr_regs);
4369             define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
4370         }
4371     }
4372     if (arm_feature(env, ARM_FEATURE_EL3)) {
4373         define_arm_cp_regs(cpu, el3_cp_reginfo);
4374         ARMCPRegInfo rvbar = {
4375             .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
4376             .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
4377             .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar
4378         };
4379         define_one_arm_cp_reg(cpu, &rvbar);
4380     }
4381     /* The behaviour of NSACR is sufficiently various that we don't
4382      * try to describe it in a single reginfo:
4383      *  if EL3 is 64 bit, then trap to EL3 from S EL1,
4384      *     reads as constant 0xc00 from NS EL1 and NS EL2
4385      *  if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
4386      *  if v7 without EL3, register doesn't exist
4387      *  if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
4388      */
4389     if (arm_feature(env, ARM_FEATURE_EL3)) {
4390         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4391             ARMCPRegInfo nsacr = {
4392                 .name = "NSACR", .type = ARM_CP_CONST,
4393                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4394                 .access = PL1_RW, .accessfn = nsacr_access,
4395                 .resetvalue = 0xc00
4396             };
4397             define_one_arm_cp_reg(cpu, &nsacr);
4398         } else {
4399             ARMCPRegInfo nsacr = {
4400                 .name = "NSACR",
4401                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4402                 .access = PL3_RW | PL1_R,
4403                 .resetvalue = 0,
4404                 .fieldoffset = offsetof(CPUARMState, cp15.nsacr)
4405             };
4406             define_one_arm_cp_reg(cpu, &nsacr);
4407         }
4408     } else {
4409         if (arm_feature(env, ARM_FEATURE_V8)) {
4410             ARMCPRegInfo nsacr = {
4411                 .name = "NSACR", .type = ARM_CP_CONST,
4412                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4413                 .access = PL1_R,
4414                 .resetvalue = 0xc00
4415             };
4416             define_one_arm_cp_reg(cpu, &nsacr);
4417         }
4418     }
4419
4420     if (arm_feature(env, ARM_FEATURE_MPU)) {
4421         if (arm_feature(env, ARM_FEATURE_V6)) {
4422             /* PMSAv6 not implemented */
4423             assert(arm_feature(env, ARM_FEATURE_V7));
4424             define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4425             define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
4426         } else {
4427             define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
4428         }
4429     } else {
4430         define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4431         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
4432     }
4433     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
4434         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
4435     }
4436     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
4437         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
4438     }
4439     if (arm_feature(env, ARM_FEATURE_VAPA)) {
4440         define_arm_cp_regs(cpu, vapa_cp_reginfo);
4441     }
4442     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
4443         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
4444     }
4445     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
4446         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
4447     }
4448     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
4449         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
4450     }
4451     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
4452         define_arm_cp_regs(cpu, omap_cp_reginfo);
4453     }
4454     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
4455         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
4456     }
4457     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4458         define_arm_cp_regs(cpu, xscale_cp_reginfo);
4459     }
4460     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
4461         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
4462     }
4463     if (arm_feature(env, ARM_FEATURE_LPAE)) {
4464         define_arm_cp_regs(cpu, lpae_cp_reginfo);
4465     }
4466     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
4467      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
4468      * be read-only (ie write causes UNDEF exception).
4469      */
4470     {
4471         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
4472             /* Pre-v8 MIDR space.
4473              * Note that the MIDR isn't a simple constant register because
4474              * of the TI925 behaviour where writes to another register can
4475              * cause the MIDR value to change.
4476              *
4477              * Unimplemented registers in the c15 0 0 0 space default to
4478              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
4479              * and friends override accordingly.
4480              */
4481             { .name = "MIDR",
4482               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
4483               .access = PL1_R, .resetvalue = cpu->midr,
4484               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
4485               .readfn = midr_read,
4486               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4487               .type = ARM_CP_OVERRIDE },
4488             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
4489             { .name = "DUMMY",
4490               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
4491               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4492             { .name = "DUMMY",
4493               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
4494               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4495             { .name = "DUMMY",
4496               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
4497               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4498             { .name = "DUMMY",
4499               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
4500               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4501             { .name = "DUMMY",
4502               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
4503               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4504             REGINFO_SENTINEL
4505         };
4506         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
4507             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
4508               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
4509               .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
4510               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4511               .readfn = midr_read },
4512             /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
4513             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4514               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4515               .access = PL1_R, .resetvalue = cpu->midr },
4516             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4517               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
4518               .access = PL1_R, .resetvalue = cpu->midr },
4519             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
4520               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
4521               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
4522             REGINFO_SENTINEL
4523         };
4524         ARMCPRegInfo id_cp_reginfo[] = {
4525             /* These are common to v8 and pre-v8 */
4526             { .name = "CTR",
4527               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
4528               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4529             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
4530               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
4531               .access = PL0_R, .accessfn = ctr_el0_access,
4532               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4533             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
4534             { .name = "TCMTR",
4535               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
4536               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4537             REGINFO_SENTINEL
4538         };
4539         /* TLBTR is specific to VMSA */
4540         ARMCPRegInfo id_tlbtr_reginfo = {
4541               .name = "TLBTR",
4542               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
4543               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
4544         };
4545         /* MPUIR is specific to PMSA V6+ */
4546         ARMCPRegInfo id_mpuir_reginfo = {
4547               .name = "MPUIR",
4548               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4549               .access = PL1_R, .type = ARM_CP_CONST,
4550               .resetvalue = cpu->pmsav7_dregion << 8
4551         };
4552         ARMCPRegInfo crn0_wi_reginfo = {
4553             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
4554             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
4555             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
4556         };
4557         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
4558             arm_feature(env, ARM_FEATURE_STRONGARM)) {
4559             ARMCPRegInfo *r;
4560             /* Register the blanket "writes ignored" value first to cover the
4561              * whole space. Then update the specific ID registers to allow write
4562              * access, so that they ignore writes rather than causing them to
4563              * UNDEF.
4564              */
4565             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
4566             for (r = id_pre_v8_midr_cp_reginfo;
4567                  r->type != ARM_CP_SENTINEL; r++) {
4568                 r->access = PL1_RW;
4569             }
4570             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
4571                 r->access = PL1_RW;
4572             }
4573             id_tlbtr_reginfo.access = PL1_RW;
4574             id_tlbtr_reginfo.access = PL1_RW;
4575         }
4576         if (arm_feature(env, ARM_FEATURE_V8)) {
4577             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
4578         } else {
4579             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
4580         }
4581         define_arm_cp_regs(cpu, id_cp_reginfo);
4582         if (!arm_feature(env, ARM_FEATURE_MPU)) {
4583             define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
4584         } else if (arm_feature(env, ARM_FEATURE_V7)) {
4585             define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
4586         }
4587     }
4588
4589     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
4590         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
4591     }
4592
4593     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
4594         ARMCPRegInfo auxcr_reginfo[] = {
4595             { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
4596               .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
4597               .access = PL1_RW, .type = ARM_CP_CONST,
4598               .resetvalue = cpu->reset_auxcr },
4599             { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
4600               .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
4601               .access = PL2_RW, .type = ARM_CP_CONST,
4602               .resetvalue = 0 },
4603             { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
4604               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
4605               .access = PL3_RW, .type = ARM_CP_CONST,
4606               .resetvalue = 0 },
4607             REGINFO_SENTINEL
4608         };
4609         define_arm_cp_regs(cpu, auxcr_reginfo);
4610     }
4611
4612     if (arm_feature(env, ARM_FEATURE_CBAR)) {
4613         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4614             /* 32 bit view is [31:18] 0...0 [43:32]. */
4615             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
4616                 | extract64(cpu->reset_cbar, 32, 12);
4617             ARMCPRegInfo cbar_reginfo[] = {
4618                 { .name = "CBAR",
4619                   .type = ARM_CP_CONST,
4620                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4621                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
4622                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
4623                   .type = ARM_CP_CONST,
4624                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
4625                   .access = PL1_R, .resetvalue = cbar32 },
4626                 REGINFO_SENTINEL
4627             };
4628             /* We don't implement a r/w 64 bit CBAR currently */
4629             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
4630             define_arm_cp_regs(cpu, cbar_reginfo);
4631         } else {
4632             ARMCPRegInfo cbar = {
4633                 .name = "CBAR",
4634                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4635                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
4636                 .fieldoffset = offsetof(CPUARMState,
4637                                         cp15.c15_config_base_address)
4638             };
4639             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
4640                 cbar.access = PL1_R;
4641                 cbar.fieldoffset = 0;
4642                 cbar.type = ARM_CP_CONST;
4643             }
4644             define_one_arm_cp_reg(cpu, &cbar);
4645         }
4646     }
4647
4648     /* Generic registers whose values depend on the implementation */
4649     {
4650         ARMCPRegInfo sctlr = {
4651             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
4652             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
4653             .access = PL1_RW,
4654             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
4655                                    offsetof(CPUARMState, cp15.sctlr_ns) },
4656             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
4657             .raw_writefn = raw_write,
4658         };
4659         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4660             /* Normally we would always end the TB on an SCTLR write, but Linux
4661              * arch/arm/mach-pxa/sleep.S expects two instructions following
4662              * an MMU enable to execute from cache.  Imitate this behaviour.
4663              */
4664             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
4665         }
4666         define_one_arm_cp_reg(cpu, &sctlr);
4667     }
4668 }
4669
4670 ARMCPU *cpu_arm_init(const char *cpu_model)
4671 {
4672     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
4673 }
4674
4675 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
4676 {
4677     CPUState *cs = CPU(cpu);
4678     CPUARMState *env = &cpu->env;
4679
4680     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4681         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
4682                                  aarch64_fpu_gdb_set_reg,
4683                                  34, "aarch64-fpu.xml", 0);
4684     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
4685         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4686                                  51, "arm-neon.xml", 0);
4687     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
4688         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4689                                  35, "arm-vfp3.xml", 0);
4690     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
4691         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4692                                  19, "arm-vfp.xml", 0);
4693     }
4694 }
4695
4696 /* Sort alphabetically by type name, except for "any". */
4697 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
4698 {
4699     ObjectClass *class_a = (ObjectClass *)a;
4700     ObjectClass *class_b = (ObjectClass *)b;
4701     const char *name_a, *name_b;
4702
4703     name_a = object_class_get_name(class_a);
4704     name_b = object_class_get_name(class_b);
4705     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
4706         return 1;
4707     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
4708         return -1;
4709     } else {
4710         return strcmp(name_a, name_b);
4711     }
4712 }
4713
4714 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
4715 {
4716     ObjectClass *oc = data;
4717     CPUListState *s = user_data;
4718     const char *typename;
4719     char *name;
4720
4721     typename = object_class_get_name(oc);
4722     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
4723     (*s->cpu_fprintf)(s->file, "  %s\n",
4724                       name);
4725     g_free(name);
4726 }
4727
4728 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
4729 {
4730     CPUListState s = {
4731         .file = f,
4732         .cpu_fprintf = cpu_fprintf,
4733     };
4734     GSList *list;
4735
4736     list = object_class_get_list(TYPE_ARM_CPU, false);
4737     list = g_slist_sort(list, arm_cpu_list_compare);
4738     (*cpu_fprintf)(f, "Available CPUs:\n");
4739     g_slist_foreach(list, arm_cpu_list_entry, &s);
4740     g_slist_free(list);
4741 #ifdef CONFIG_KVM
4742     /* The 'host' CPU type is dynamically registered only if KVM is
4743      * enabled, so we have to special-case it here:
4744      */
4745     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
4746 #endif
4747 }
4748
4749 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
4750 {
4751     ObjectClass *oc = data;
4752     CpuDefinitionInfoList **cpu_list = user_data;
4753     CpuDefinitionInfoList *entry;
4754     CpuDefinitionInfo *info;
4755     const char *typename;
4756
4757     typename = object_class_get_name(oc);
4758     info = g_malloc0(sizeof(*info));
4759     info->name = g_strndup(typename,
4760                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
4761
4762     entry = g_malloc0(sizeof(*entry));
4763     entry->value = info;
4764     entry->next = *cpu_list;
4765     *cpu_list = entry;
4766 }
4767
4768 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
4769 {
4770     CpuDefinitionInfoList *cpu_list = NULL;
4771     GSList *list;
4772
4773     list = object_class_get_list(TYPE_ARM_CPU, false);
4774     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
4775     g_slist_free(list);
4776
4777     return cpu_list;
4778 }
4779
4780 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
4781                                    void *opaque, int state, int secstate,
4782                                    int crm, int opc1, int opc2)
4783 {
4784     /* Private utility function for define_one_arm_cp_reg_with_opaque():
4785      * add a single reginfo struct to the hash table.
4786      */
4787     uint32_t *key = g_new(uint32_t, 1);
4788     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
4789     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
4790     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
4791
4792     /* Reset the secure state to the specific incoming state.  This is
4793      * necessary as the register may have been defined with both states.
4794      */
4795     r2->secure = secstate;
4796
4797     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
4798         /* Register is banked (using both entries in array).
4799          * Overwriting fieldoffset as the array is only used to define
4800          * banked registers but later only fieldoffset is used.
4801          */
4802         r2->fieldoffset = r->bank_fieldoffsets[ns];
4803     }
4804
4805     if (state == ARM_CP_STATE_AA32) {
4806         if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
4807             /* If the register is banked then we don't need to migrate or
4808              * reset the 32-bit instance in certain cases:
4809              *
4810              * 1) If the register has both 32-bit and 64-bit instances then we
4811              *    can count on the 64-bit instance taking care of the
4812              *    non-secure bank.
4813              * 2) If ARMv8 is enabled then we can count on a 64-bit version
4814              *    taking care of the secure bank.  This requires that separate
4815              *    32 and 64-bit definitions are provided.
4816              */
4817             if ((r->state == ARM_CP_STATE_BOTH && ns) ||
4818                 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
4819                 r2->type |= ARM_CP_ALIAS;
4820             }
4821         } else if ((secstate != r->secure) && !ns) {
4822             /* The register is not banked so we only want to allow migration of
4823              * the non-secure instance.
4824              */
4825             r2->type |= ARM_CP_ALIAS;
4826         }
4827
4828         if (r->state == ARM_CP_STATE_BOTH) {
4829             /* We assume it is a cp15 register if the .cp field is left unset.
4830              */
4831             if (r2->cp == 0) {
4832                 r2->cp = 15;
4833             }
4834
4835 #ifdef HOST_WORDS_BIGENDIAN
4836             if (r2->fieldoffset) {
4837                 r2->fieldoffset += sizeof(uint32_t);
4838             }
4839 #endif
4840         }
4841     }
4842     if (state == ARM_CP_STATE_AA64) {
4843         /* To allow abbreviation of ARMCPRegInfo
4844          * definitions, we treat cp == 0 as equivalent to
4845          * the value for "standard guest-visible sysreg".
4846          * STATE_BOTH definitions are also always "standard
4847          * sysreg" in their AArch64 view (the .cp value may
4848          * be non-zero for the benefit of the AArch32 view).
4849          */
4850         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
4851             r2->cp = CP_REG_ARM64_SYSREG_CP;
4852         }
4853         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
4854                                   r2->opc0, opc1, opc2);
4855     } else {
4856         *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
4857     }
4858     if (opaque) {
4859         r2->opaque = opaque;
4860     }
4861     /* reginfo passed to helpers is correct for the actual access,
4862      * and is never ARM_CP_STATE_BOTH:
4863      */
4864     r2->state = state;
4865     /* Make sure reginfo passed to helpers for wildcarded regs
4866      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
4867      */
4868     r2->crm = crm;
4869     r2->opc1 = opc1;
4870     r2->opc2 = opc2;
4871     /* By convention, for wildcarded registers only the first
4872      * entry is used for migration; the others are marked as
4873      * ALIAS so we don't try to transfer the register
4874      * multiple times. Special registers (ie NOP/WFI) are
4875      * never migratable and not even raw-accessible.
4876      */
4877     if ((r->type & ARM_CP_SPECIAL)) {
4878         r2->type |= ARM_CP_NO_RAW;
4879     }
4880     if (((r->crm == CP_ANY) && crm != 0) ||
4881         ((r->opc1 == CP_ANY) && opc1 != 0) ||
4882         ((r->opc2 == CP_ANY) && opc2 != 0)) {
4883         r2->type |= ARM_CP_ALIAS;
4884     }
4885
4886     /* Check that raw accesses are either forbidden or handled. Note that
4887      * we can't assert this earlier because the setup of fieldoffset for
4888      * banked registers has to be done first.
4889      */
4890     if (!(r2->type & ARM_CP_NO_RAW)) {
4891         assert(!raw_accessors_invalid(r2));
4892     }
4893
4894     /* Overriding of an existing definition must be explicitly
4895      * requested.
4896      */
4897     if (!(r->type & ARM_CP_OVERRIDE)) {
4898         ARMCPRegInfo *oldreg;
4899         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
4900         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
4901             fprintf(stderr, "Register redefined: cp=%d %d bit "
4902                     "crn=%d crm=%d opc1=%d opc2=%d, "
4903                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
4904                     r2->crn, r2->crm, r2->opc1, r2->opc2,
4905                     oldreg->name, r2->name);
4906             g_assert_not_reached();
4907         }
4908     }
4909     g_hash_table_insert(cpu->cp_regs, key, r2);
4910 }
4911
4912
4913 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
4914                                        const ARMCPRegInfo *r, void *opaque)
4915 {
4916     /* Define implementations of coprocessor registers.
4917      * We store these in a hashtable because typically
4918      * there are less than 150 registers in a space which
4919      * is 16*16*16*8*8 = 262144 in size.
4920      * Wildcarding is supported for the crm, opc1 and opc2 fields.
4921      * If a register is defined twice then the second definition is
4922      * used, so this can be used to define some generic registers and
4923      * then override them with implementation specific variations.
4924      * At least one of the original and the second definition should
4925      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
4926      * against accidental use.
4927      *
4928      * The state field defines whether the register is to be
4929      * visible in the AArch32 or AArch64 execution state. If the
4930      * state is set to ARM_CP_STATE_BOTH then we synthesise a
4931      * reginfo structure for the AArch32 view, which sees the lower
4932      * 32 bits of the 64 bit register.
4933      *
4934      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
4935      * be wildcarded. AArch64 registers are always considered to be 64
4936      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
4937      * the register, if any.
4938      */
4939     int crm, opc1, opc2, state;
4940     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
4941     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
4942     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
4943     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
4944     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
4945     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
4946     /* 64 bit registers have only CRm and Opc1 fields */
4947     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
4948     /* op0 only exists in the AArch64 encodings */
4949     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
4950     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
4951     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
4952     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
4953      * encodes a minimum access level for the register. We roll this
4954      * runtime check into our general permission check code, so check
4955      * here that the reginfo's specified permissions are strict enough
4956      * to encompass the generic architectural permission check.
4957      */
4958     if (r->state != ARM_CP_STATE_AA32) {
4959         int mask = 0;
4960         switch (r->opc1) {
4961         case 0: case 1: case 2:
4962             /* min_EL EL1 */
4963             mask = PL1_RW;
4964             break;
4965         case 3:
4966             /* min_EL EL0 */
4967             mask = PL0_RW;
4968             break;
4969         case 4:
4970             /* min_EL EL2 */
4971             mask = PL2_RW;
4972             break;
4973         case 5:
4974             /* unallocated encoding, so not possible */
4975             assert(false);
4976             break;
4977         case 6:
4978             /* min_EL EL3 */
4979             mask = PL3_RW;
4980             break;
4981         case 7:
4982             /* min_EL EL1, secure mode only (we don't check the latter) */
4983             mask = PL1_RW;
4984             break;
4985         default:
4986             /* broken reginfo with out-of-range opc1 */
4987             assert(false);
4988             break;
4989         }
4990         /* assert our permissions are not too lax (stricter is fine) */
4991         assert((r->access & ~mask) == 0);
4992     }
4993
4994     /* Check that the register definition has enough info to handle
4995      * reads and writes if they are permitted.
4996      */
4997     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
4998         if (r->access & PL3_R) {
4999             assert((r->fieldoffset ||
5000                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5001                    r->readfn);
5002         }
5003         if (r->access & PL3_W) {
5004             assert((r->fieldoffset ||
5005                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5006                    r->writefn);
5007         }
5008     }
5009     /* Bad type field probably means missing sentinel at end of reg list */
5010     assert(cptype_valid(r->type));
5011     for (crm = crmmin; crm <= crmmax; crm++) {
5012         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
5013             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
5014                 for (state = ARM_CP_STATE_AA32;
5015                      state <= ARM_CP_STATE_AA64; state++) {
5016                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
5017                         continue;
5018                     }
5019                     if (state == ARM_CP_STATE_AA32) {
5020                         /* Under AArch32 CP registers can be common
5021                          * (same for secure and non-secure world) or banked.
5022                          */
5023                         switch (r->secure) {
5024                         case ARM_CP_SECSTATE_S:
5025                         case ARM_CP_SECSTATE_NS:
5026                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5027                                                    r->secure, crm, opc1, opc2);
5028                             break;
5029                         default:
5030                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5031                                                    ARM_CP_SECSTATE_S,
5032                                                    crm, opc1, opc2);
5033                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5034                                                    ARM_CP_SECSTATE_NS,
5035                                                    crm, opc1, opc2);
5036                             break;
5037                         }
5038                     } else {
5039                         /* AArch64 registers get mapped to non-secure instance
5040                          * of AArch32 */
5041                         add_cpreg_to_hashtable(cpu, r, opaque, state,
5042                                                ARM_CP_SECSTATE_NS,
5043                                                crm, opc1, opc2);
5044                     }
5045                 }
5046             }
5047         }
5048     }
5049 }
5050
5051 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
5052                                     const ARMCPRegInfo *regs, void *opaque)
5053 {
5054     /* Define a whole list of registers */
5055     const ARMCPRegInfo *r;
5056     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
5057         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
5058     }
5059 }
5060
5061 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
5062 {
5063     return g_hash_table_lookup(cpregs, &encoded_cp);
5064 }
5065
5066 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
5067                          uint64_t value)
5068 {
5069     /* Helper coprocessor write function for write-ignore registers */
5070 }
5071
5072 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
5073 {
5074     /* Helper coprocessor write function for read-as-zero registers */
5075     return 0;
5076 }
5077
5078 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
5079 {
5080     /* Helper coprocessor reset function for do-nothing-on-reset registers */
5081 }
5082
5083 static int bad_mode_switch(CPUARMState *env, int mode)
5084 {
5085     /* Return true if it is not valid for us to switch to
5086      * this CPU mode (ie all the UNPREDICTABLE cases in
5087      * the ARM ARM CPSRWriteByInstr pseudocode).
5088      */
5089     switch (mode) {
5090     case ARM_CPU_MODE_USR:
5091     case ARM_CPU_MODE_SYS:
5092     case ARM_CPU_MODE_SVC:
5093     case ARM_CPU_MODE_ABT:
5094     case ARM_CPU_MODE_UND:
5095     case ARM_CPU_MODE_IRQ:
5096     case ARM_CPU_MODE_FIQ:
5097         return 0;
5098     case ARM_CPU_MODE_MON:
5099         return !arm_is_secure(env);
5100     default:
5101         return 1;
5102     }
5103 }
5104
5105 uint32_t cpsr_read(CPUARMState *env)
5106 {
5107     int ZF;
5108     ZF = (env->ZF == 0);
5109     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
5110         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
5111         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
5112         | ((env->condexec_bits & 0xfc) << 8)
5113         | (env->GE << 16) | (env->daif & CPSR_AIF);
5114 }
5115
5116 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
5117 {
5118     uint32_t changed_daif;
5119
5120     if (mask & CPSR_NZCV) {
5121         env->ZF = (~val) & CPSR_Z;
5122         env->NF = val;
5123         env->CF = (val >> 29) & 1;
5124         env->VF = (val << 3) & 0x80000000;
5125     }
5126     if (mask & CPSR_Q)
5127         env->QF = ((val & CPSR_Q) != 0);
5128     if (mask & CPSR_T)
5129         env->thumb = ((val & CPSR_T) != 0);
5130     if (mask & CPSR_IT_0_1) {
5131         env->condexec_bits &= ~3;
5132         env->condexec_bits |= (val >> 25) & 3;
5133     }
5134     if (mask & CPSR_IT_2_7) {
5135         env->condexec_bits &= 3;
5136         env->condexec_bits |= (val >> 8) & 0xfc;
5137     }
5138     if (mask & CPSR_GE) {
5139         env->GE = (val >> 16) & 0xf;
5140     }
5141
5142     /* In a V7 implementation that includes the security extensions but does
5143      * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5144      * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5145      * bits respectively.
5146      *
5147      * In a V8 implementation, it is permitted for privileged software to
5148      * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5149      */
5150     if (!arm_feature(env, ARM_FEATURE_V8) &&
5151         arm_feature(env, ARM_FEATURE_EL3) &&
5152         !arm_feature(env, ARM_FEATURE_EL2) &&
5153         !arm_is_secure(env)) {
5154
5155         changed_daif = (env->daif ^ val) & mask;
5156
5157         if (changed_daif & CPSR_A) {
5158             /* Check to see if we are allowed to change the masking of async
5159              * abort exceptions from a non-secure state.
5160              */
5161             if (!(env->cp15.scr_el3 & SCR_AW)) {
5162                 qemu_log_mask(LOG_GUEST_ERROR,
5163                               "Ignoring attempt to switch CPSR_A flag from "
5164                               "non-secure world with SCR.AW bit clear\n");
5165                 mask &= ~CPSR_A;
5166             }
5167         }
5168
5169         if (changed_daif & CPSR_F) {
5170             /* Check to see if we are allowed to change the masking of FIQ
5171              * exceptions from a non-secure state.
5172              */
5173             if (!(env->cp15.scr_el3 & SCR_FW)) {
5174                 qemu_log_mask(LOG_GUEST_ERROR,
5175                               "Ignoring attempt to switch CPSR_F flag from "
5176                               "non-secure world with SCR.FW bit clear\n");
5177                 mask &= ~CPSR_F;
5178             }
5179
5180             /* Check whether non-maskable FIQ (NMFI) support is enabled.
5181              * If this bit is set software is not allowed to mask
5182              * FIQs, but is allowed to set CPSR_F to 0.
5183              */
5184             if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
5185                 (val & CPSR_F)) {
5186                 qemu_log_mask(LOG_GUEST_ERROR,
5187                               "Ignoring attempt to enable CPSR_F flag "
5188                               "(non-maskable FIQ [NMFI] support enabled)\n");
5189                 mask &= ~CPSR_F;
5190             }
5191         }
5192     }
5193
5194     env->daif &= ~(CPSR_AIF & mask);
5195     env->daif |= val & CPSR_AIF & mask;
5196
5197     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
5198         if (bad_mode_switch(env, val & CPSR_M)) {
5199             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
5200              * We choose to ignore the attempt and leave the CPSR M field
5201              * untouched.
5202              */
5203             mask &= ~CPSR_M;
5204         } else {
5205             switch_mode(env, val & CPSR_M);
5206         }
5207     }
5208     mask &= ~CACHED_CPSR_BITS;
5209     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
5210 }
5211
5212 /* Sign/zero extend */
5213 uint32_t HELPER(sxtb16)(uint32_t x)
5214 {
5215     uint32_t res;
5216     res = (uint16_t)(int8_t)x;
5217     res |= (uint32_t)(int8_t)(x >> 16) << 16;
5218     return res;
5219 }
5220
5221 uint32_t HELPER(uxtb16)(uint32_t x)
5222 {
5223     uint32_t res;
5224     res = (uint16_t)(uint8_t)x;
5225     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
5226     return res;
5227 }
5228
5229 uint32_t HELPER(clz)(uint32_t x)
5230 {
5231     return clz32(x);
5232 }
5233
5234 int32_t HELPER(sdiv)(int32_t num, int32_t den)
5235 {
5236     if (den == 0)
5237       return 0;
5238     if (num == INT_MIN && den == -1)
5239       return INT_MIN;
5240     return num / den;
5241 }
5242
5243 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
5244 {
5245     if (den == 0)
5246       return 0;
5247     return num / den;
5248 }
5249
5250 uint32_t HELPER(rbit)(uint32_t x)
5251 {
5252     return revbit32(x);
5253 }
5254
5255 #if defined(CONFIG_USER_ONLY)
5256
5257 /* These should probably raise undefined insn exceptions.  */
5258 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
5259 {
5260     ARMCPU *cpu = arm_env_get_cpu(env);
5261
5262     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
5263 }
5264
5265 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
5266 {
5267     ARMCPU *cpu = arm_env_get_cpu(env);
5268
5269     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
5270     return 0;
5271 }
5272
5273 void switch_mode(CPUARMState *env, int mode)
5274 {
5275     ARMCPU *cpu = arm_env_get_cpu(env);
5276
5277     if (mode != ARM_CPU_MODE_USR) {
5278         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
5279     }
5280 }
5281
5282 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
5283 {
5284     ARMCPU *cpu = arm_env_get_cpu(env);
5285
5286     cpu_abort(CPU(cpu), "banked r13 write\n");
5287 }
5288
5289 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
5290 {
5291     ARMCPU *cpu = arm_env_get_cpu(env);
5292
5293     cpu_abort(CPU(cpu), "banked r13 read\n");
5294     return 0;
5295 }
5296
5297 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5298                                  uint32_t cur_el, bool secure)
5299 {
5300     return 1;
5301 }
5302
5303 void aarch64_sync_64_to_32(CPUARMState *env)
5304 {
5305     g_assert_not_reached();
5306 }
5307
5308 #else
5309
5310 /* Map CPU modes onto saved register banks.  */
5311 int bank_number(int mode)
5312 {
5313     switch (mode) {
5314     case ARM_CPU_MODE_USR:
5315     case ARM_CPU_MODE_SYS:
5316         return BANK_USRSYS;
5317     case ARM_CPU_MODE_SVC:
5318         return BANK_SVC;
5319     case ARM_CPU_MODE_ABT:
5320         return BANK_ABT;
5321     case ARM_CPU_MODE_UND:
5322         return BANK_UND;
5323     case ARM_CPU_MODE_IRQ:
5324         return BANK_IRQ;
5325     case ARM_CPU_MODE_FIQ:
5326         return BANK_FIQ;
5327     case ARM_CPU_MODE_HYP:
5328         return BANK_HYP;
5329     case ARM_CPU_MODE_MON:
5330         return BANK_MON;
5331     }
5332     g_assert_not_reached();
5333 }
5334
5335 void switch_mode(CPUARMState *env, int mode)
5336 {
5337     int old_mode;
5338     int i;
5339
5340     old_mode = env->uncached_cpsr & CPSR_M;
5341     if (mode == old_mode)
5342         return;
5343
5344     if (old_mode == ARM_CPU_MODE_FIQ) {
5345         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
5346         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
5347     } else if (mode == ARM_CPU_MODE_FIQ) {
5348         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
5349         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
5350     }
5351
5352     i = bank_number(old_mode);
5353     env->banked_r13[i] = env->regs[13];
5354     env->banked_r14[i] = env->regs[14];
5355     env->banked_spsr[i] = env->spsr;
5356
5357     i = bank_number(mode);
5358     env->regs[13] = env->banked_r13[i];
5359     env->regs[14] = env->banked_r14[i];
5360     env->spsr = env->banked_spsr[i];
5361 }
5362
5363 /* Physical Interrupt Target EL Lookup Table
5364  *
5365  * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5366  *
5367  * The below multi-dimensional table is used for looking up the target
5368  * exception level given numerous condition criteria.  Specifically, the
5369  * target EL is based on SCR and HCR routing controls as well as the
5370  * currently executing EL and secure state.
5371  *
5372  *    Dimensions:
5373  *    target_el_table[2][2][2][2][2][4]
5374  *                    |  |  |  |  |  +--- Current EL
5375  *                    |  |  |  |  +------ Non-secure(0)/Secure(1)
5376  *                    |  |  |  +--------- HCR mask override
5377  *                    |  |  +------------ SCR exec state control
5378  *                    |  +--------------- SCR mask override
5379  *                    +------------------ 32-bit(0)/64-bit(1) EL3
5380  *
5381  *    The table values are as such:
5382  *    0-3 = EL0-EL3
5383  *     -1 = Cannot occur
5384  *
5385  * The ARM ARM target EL table includes entries indicating that an "exception
5386  * is not taken".  The two cases where this is applicable are:
5387  *    1) An exception is taken from EL3 but the SCR does not have the exception
5388  *    routed to EL3.
5389  *    2) An exception is taken from EL2 but the HCR does not have the exception
5390  *    routed to EL2.
5391  * In these two cases, the below table contain a target of EL1.  This value is
5392  * returned as it is expected that the consumer of the table data will check
5393  * for "target EL >= current EL" to ensure the exception is not taken.
5394  *
5395  *            SCR     HCR
5396  *         64  EA     AMO                 From
5397  *        BIT IRQ     IMO      Non-secure         Secure
5398  *        EL3 FIQ  RW FMO   EL0 EL1 EL2 EL3   EL0 EL1 EL2 EL3
5399  */
5400 static const int8_t target_el_table[2][2][2][2][2][4] = {
5401     {{{{/* 0   0   0   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5402        {/* 0   0   0   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},
5403       {{/* 0   0   1   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5404        {/* 0   0   1   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},},
5405      {{{/* 0   1   0   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5406        {/* 0   1   0   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},
5407       {{/* 0   1   1   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5408        {/* 0   1   1   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},},},
5409     {{{{/* 1   0   0   0 */{ 1,  1,  2, -1 },{ 1,  1, -1,  1 },},
5410        {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},
5411       {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1, -1,  1 },},
5412        {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},},
5413      {{{/* 1   1   0   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5414        {/* 1   1   0   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},
5415       {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5416        {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},},},
5417 };
5418
5419 /*
5420  * Determine the target EL for physical exceptions
5421  */
5422 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5423                                  uint32_t cur_el, bool secure)
5424 {
5425     CPUARMState *env = cs->env_ptr;
5426     int rw;
5427     int scr;
5428     int hcr;
5429     int target_el;
5430     /* Is the highest EL AArch64? */
5431     int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
5432
5433     if (arm_feature(env, ARM_FEATURE_EL3)) {
5434         rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
5435     } else {
5436         /* Either EL2 is the highest EL (and so the EL2 register width
5437          * is given by is64); or there is no EL2 or EL3, in which case
5438          * the value of 'rw' does not affect the table lookup anyway.
5439          */
5440         rw = is64;
5441     }
5442
5443     switch (excp_idx) {
5444     case EXCP_IRQ:
5445         scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
5446         hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
5447         break;
5448     case EXCP_FIQ:
5449         scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
5450         hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
5451         break;
5452     default:
5453         scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
5454         hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
5455         break;
5456     };
5457
5458     /* If HCR.TGE is set then HCR is treated as being 1 */
5459     hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
5460
5461     /* Perform a table-lookup for the target EL given the current state */
5462     target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
5463
5464     assert(target_el > 0);
5465
5466     return target_el;
5467 }
5468
5469 static void v7m_push(CPUARMState *env, uint32_t val)
5470 {
5471     CPUState *cs = CPU(arm_env_get_cpu(env));
5472
5473     env->regs[13] -= 4;
5474     stl_phys(cs->as, env->regs[13], val);
5475 }
5476
5477 static uint32_t v7m_pop(CPUARMState *env)
5478 {
5479     CPUState *cs = CPU(arm_env_get_cpu(env));
5480     uint32_t val;
5481
5482     val = ldl_phys(cs->as, env->regs[13]);
5483     env->regs[13] += 4;
5484     return val;
5485 }
5486
5487 /* Switch to V7M main or process stack pointer.  */
5488 static void switch_v7m_sp(CPUARMState *env, int process)
5489 {
5490     uint32_t tmp;
5491     if (env->v7m.current_sp != process) {
5492         tmp = env->v7m.other_sp;
5493         env->v7m.other_sp = env->regs[13];
5494         env->regs[13] = tmp;
5495         env->v7m.current_sp = process;
5496     }
5497 }
5498
5499 static void do_v7m_exception_exit(CPUARMState *env)
5500 {
5501     uint32_t type;
5502     uint32_t xpsr;
5503
5504     type = env->regs[15];
5505     if (env->v7m.exception != 0)
5506         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
5507
5508     /* Switch to the target stack.  */
5509     switch_v7m_sp(env, (type & 4) != 0);
5510     /* Pop registers.  */
5511     env->regs[0] = v7m_pop(env);
5512     env->regs[1] = v7m_pop(env);
5513     env->regs[2] = v7m_pop(env);
5514     env->regs[3] = v7m_pop(env);
5515     env->regs[12] = v7m_pop(env);
5516     env->regs[14] = v7m_pop(env);
5517     env->regs[15] = v7m_pop(env);
5518     if (env->regs[15] & 1) {
5519         qemu_log_mask(LOG_GUEST_ERROR,
5520                       "M profile return from interrupt with misaligned "
5521                       "PC is UNPREDICTABLE\n");
5522         /* Actual hardware seems to ignore the lsbit, and there are several
5523          * RTOSes out there which incorrectly assume the r15 in the stack
5524          * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
5525          */
5526         env->regs[15] &= ~1U;
5527     }
5528     xpsr = v7m_pop(env);
5529     xpsr_write(env, xpsr, 0xfffffdff);
5530     /* Undo stack alignment.  */
5531     if (xpsr & 0x200)
5532         env->regs[13] |= 4;
5533     /* ??? The exception return type specifies Thread/Handler mode.  However
5534        this is also implied by the xPSR value. Not sure what to do
5535        if there is a mismatch.  */
5536     /* ??? Likewise for mismatches between the CONTROL register and the stack
5537        pointer.  */
5538 }
5539
5540 void arm_v7m_cpu_do_interrupt(CPUState *cs)
5541 {
5542     ARMCPU *cpu = ARM_CPU(cs);
5543     CPUARMState *env = &cpu->env;
5544     uint32_t xpsr = xpsr_read(env);
5545     uint32_t lr;
5546     uint32_t addr;
5547
5548     arm_log_exception(cs->exception_index);
5549
5550     lr = 0xfffffff1;
5551     if (env->v7m.current_sp)
5552         lr |= 4;
5553     if (env->v7m.exception == 0)
5554         lr |= 8;
5555
5556     /* For exceptions we just mark as pending on the NVIC, and let that
5557        handle it.  */
5558     /* TODO: Need to escalate if the current priority is higher than the
5559        one we're raising.  */
5560     switch (cs->exception_index) {
5561     case EXCP_UDEF:
5562         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
5563         return;
5564     case EXCP_SWI:
5565         /* The PC already points to the next instruction.  */
5566         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
5567         return;
5568     case EXCP_PREFETCH_ABORT:
5569     case EXCP_DATA_ABORT:
5570         /* TODO: if we implemented the MPU registers, this is where we
5571          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
5572          */
5573         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
5574         return;
5575     case EXCP_BKPT:
5576         if (semihosting_enabled()) {
5577             int nr;
5578             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
5579             if (nr == 0xab) {
5580                 env->regs[15] += 2;
5581                 qemu_log_mask(CPU_LOG_INT,
5582                               "...handling as semihosting call 0x%x\n",
5583                               env->regs[0]);
5584                 env->regs[0] = do_arm_semihosting(env);
5585                 return;
5586             }
5587         }
5588         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
5589         return;
5590     case EXCP_IRQ:
5591         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
5592         break;
5593     case EXCP_EXCEPTION_EXIT:
5594         do_v7m_exception_exit(env);
5595         return;
5596     default:
5597         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5598         return; /* Never happens.  Keep compiler happy.  */
5599     }
5600
5601     /* Align stack pointer.  */
5602     /* ??? Should only do this if Configuration Control Register
5603        STACKALIGN bit is set.  */
5604     if (env->regs[13] & 4) {
5605         env->regs[13] -= 4;
5606         xpsr |= 0x200;
5607     }
5608     /* Switch to the handler mode.  */
5609     v7m_push(env, xpsr);
5610     v7m_push(env, env->regs[15]);
5611     v7m_push(env, env->regs[14]);
5612     v7m_push(env, env->regs[12]);
5613     v7m_push(env, env->regs[3]);
5614     v7m_push(env, env->regs[2]);
5615     v7m_push(env, env->regs[1]);
5616     v7m_push(env, env->regs[0]);
5617     switch_v7m_sp(env, 0);
5618     /* Clear IT bits */
5619     env->condexec_bits = 0;
5620     env->regs[14] = lr;
5621     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
5622     env->regs[15] = addr & 0xfffffffe;
5623     env->thumb = addr & 1;
5624 }
5625
5626 /* Function used to synchronize QEMU's AArch64 register set with AArch32
5627  * register set.  This is necessary when switching between AArch32 and AArch64
5628  * execution state.
5629  */
5630 void aarch64_sync_32_to_64(CPUARMState *env)
5631 {
5632     int i;
5633     uint32_t mode = env->uncached_cpsr & CPSR_M;
5634
5635     /* We can blanket copy R[0:7] to X[0:7] */
5636     for (i = 0; i < 8; i++) {
5637         env->xregs[i] = env->regs[i];
5638     }
5639
5640     /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
5641      * Otherwise, they come from the banked user regs.
5642      */
5643     if (mode == ARM_CPU_MODE_FIQ) {
5644         for (i = 8; i < 13; i++) {
5645             env->xregs[i] = env->usr_regs[i - 8];
5646         }
5647     } else {
5648         for (i = 8; i < 13; i++) {
5649             env->xregs[i] = env->regs[i];
5650         }
5651     }
5652
5653     /* Registers x13-x23 are the various mode SP and FP registers. Registers
5654      * r13 and r14 are only copied if we are in that mode, otherwise we copy
5655      * from the mode banked register.
5656      */
5657     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5658         env->xregs[13] = env->regs[13];
5659         env->xregs[14] = env->regs[14];
5660     } else {
5661         env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
5662         /* HYP is an exception in that it is copied from r14 */
5663         if (mode == ARM_CPU_MODE_HYP) {
5664             env->xregs[14] = env->regs[14];
5665         } else {
5666             env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
5667         }
5668     }
5669
5670     if (mode == ARM_CPU_MODE_HYP) {
5671         env->xregs[15] = env->regs[13];
5672     } else {
5673         env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
5674     }
5675
5676     if (mode == ARM_CPU_MODE_IRQ) {
5677         env->xregs[16] = env->regs[14];
5678         env->xregs[17] = env->regs[13];
5679     } else {
5680         env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
5681         env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
5682     }
5683
5684     if (mode == ARM_CPU_MODE_SVC) {
5685         env->xregs[18] = env->regs[14];
5686         env->xregs[19] = env->regs[13];
5687     } else {
5688         env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
5689         env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
5690     }
5691
5692     if (mode == ARM_CPU_MODE_ABT) {
5693         env->xregs[20] = env->regs[14];
5694         env->xregs[21] = env->regs[13];
5695     } else {
5696         env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
5697         env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
5698     }
5699
5700     if (mode == ARM_CPU_MODE_UND) {
5701         env->xregs[22] = env->regs[14];
5702         env->xregs[23] = env->regs[13];
5703     } else {
5704         env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
5705         env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
5706     }
5707
5708     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5709      * mode, then we can copy from r8-r14.  Otherwise, we copy from the
5710      * FIQ bank for r8-r14.
5711      */
5712     if (mode == ARM_CPU_MODE_FIQ) {
5713         for (i = 24; i < 31; i++) {
5714             env->xregs[i] = env->regs[i - 16];   /* X[24:30] <- R[8:14] */
5715         }
5716     } else {
5717         for (i = 24; i < 29; i++) {
5718             env->xregs[i] = env->fiq_regs[i - 24];
5719         }
5720         env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
5721         env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
5722     }
5723
5724     env->pc = env->regs[15];
5725 }
5726
5727 /* Function used to synchronize QEMU's AArch32 register set with AArch64
5728  * register set.  This is necessary when switching between AArch32 and AArch64
5729  * execution state.
5730  */
5731 void aarch64_sync_64_to_32(CPUARMState *env)
5732 {
5733     int i;
5734     uint32_t mode = env->uncached_cpsr & CPSR_M;
5735
5736     /* We can blanket copy X[0:7] to R[0:7] */
5737     for (i = 0; i < 8; i++) {
5738         env->regs[i] = env->xregs[i];
5739     }
5740
5741     /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
5742      * Otherwise, we copy x8-x12 into the banked user regs.
5743      */
5744     if (mode == ARM_CPU_MODE_FIQ) {
5745         for (i = 8; i < 13; i++) {
5746             env->usr_regs[i - 8] = env->xregs[i];
5747         }
5748     } else {
5749         for (i = 8; i < 13; i++) {
5750             env->regs[i] = env->xregs[i];
5751         }
5752     }
5753
5754     /* Registers r13 & r14 depend on the current mode.
5755      * If we are in a given mode, we copy the corresponding x registers to r13
5756      * and r14.  Otherwise, we copy the x register to the banked r13 and r14
5757      * for the mode.
5758      */
5759     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5760         env->regs[13] = env->xregs[13];
5761         env->regs[14] = env->xregs[14];
5762     } else {
5763         env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
5764
5765         /* HYP is an exception in that it does not have its own banked r14 but
5766          * shares the USR r14
5767          */
5768         if (mode == ARM_CPU_MODE_HYP) {
5769             env->regs[14] = env->xregs[14];
5770         } else {
5771             env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
5772         }
5773     }
5774
5775     if (mode == ARM_CPU_MODE_HYP) {
5776         env->regs[13] = env->xregs[15];
5777     } else {
5778         env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
5779     }
5780
5781     if (mode == ARM_CPU_MODE_IRQ) {
5782         env->regs[14] = env->xregs[16];
5783         env->regs[13] = env->xregs[17];
5784     } else {
5785         env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
5786         env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
5787     }
5788
5789     if (mode == ARM_CPU_MODE_SVC) {
5790         env->regs[14] = env->xregs[18];
5791         env->regs[13] = env->xregs[19];
5792     } else {
5793         env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
5794         env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
5795     }
5796
5797     if (mode == ARM_CPU_MODE_ABT) {
5798         env->regs[14] = env->xregs[20];
5799         env->regs[13] = env->xregs[21];
5800     } else {
5801         env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
5802         env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
5803     }
5804
5805     if (mode == ARM_CPU_MODE_UND) {
5806         env->regs[14] = env->xregs[22];
5807         env->regs[13] = env->xregs[23];
5808     } else {
5809         env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
5810         env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
5811     }
5812
5813     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5814      * mode, then we can copy to r8-r14.  Otherwise, we copy to the
5815      * FIQ bank for r8-r14.
5816      */
5817     if (mode == ARM_CPU_MODE_FIQ) {
5818         for (i = 24; i < 31; i++) {
5819             env->regs[i - 16] = env->xregs[i];   /* X[24:30] -> R[8:14] */
5820         }
5821     } else {
5822         for (i = 24; i < 29; i++) {
5823             env->fiq_regs[i - 24] = env->xregs[i];
5824         }
5825         env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
5826         env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
5827     }
5828
5829     env->regs[15] = env->pc;
5830 }
5831
5832 static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
5833 {
5834     ARMCPU *cpu = ARM_CPU(cs);
5835     CPUARMState *env = &cpu->env;
5836     uint32_t addr;
5837     uint32_t mask;
5838     int new_mode;
5839     uint32_t offset;
5840     uint32_t moe;
5841
5842     /* If this is a debug exception we must update the DBGDSCR.MOE bits */
5843     switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
5844     case EC_BREAKPOINT:
5845     case EC_BREAKPOINT_SAME_EL:
5846         moe = 1;
5847         break;
5848     case EC_WATCHPOINT:
5849     case EC_WATCHPOINT_SAME_EL:
5850         moe = 10;
5851         break;
5852     case EC_AA32_BKPT:
5853         moe = 3;
5854         break;
5855     case EC_VECTORCATCH:
5856         moe = 5;
5857         break;
5858     default:
5859         moe = 0;
5860         break;
5861     }
5862
5863     if (moe) {
5864         env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
5865     }
5866
5867     /* TODO: Vectored interrupt controller.  */
5868     switch (cs->exception_index) {
5869     case EXCP_UDEF:
5870         new_mode = ARM_CPU_MODE_UND;
5871         addr = 0x04;
5872         mask = CPSR_I;
5873         if (env->thumb)
5874             offset = 2;
5875         else
5876             offset = 4;
5877         break;
5878     case EXCP_SWI:
5879         new_mode = ARM_CPU_MODE_SVC;
5880         addr = 0x08;
5881         mask = CPSR_I;
5882         /* The PC already points to the next instruction.  */
5883         offset = 0;
5884         break;
5885     case EXCP_BKPT:
5886         env->exception.fsr = 2;
5887         /* Fall through to prefetch abort.  */
5888     case EXCP_PREFETCH_ABORT:
5889         A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
5890         A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
5891         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
5892                       env->exception.fsr, (uint32_t)env->exception.vaddress);
5893         new_mode = ARM_CPU_MODE_ABT;
5894         addr = 0x0c;
5895         mask = CPSR_A | CPSR_I;
5896         offset = 4;
5897         break;
5898     case EXCP_DATA_ABORT:
5899         A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
5900         A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
5901         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
5902                       env->exception.fsr,
5903                       (uint32_t)env->exception.vaddress);
5904         new_mode = ARM_CPU_MODE_ABT;
5905         addr = 0x10;
5906         mask = CPSR_A | CPSR_I;
5907         offset = 8;
5908         break;
5909     case EXCP_IRQ:
5910         new_mode = ARM_CPU_MODE_IRQ;
5911         addr = 0x18;
5912         /* Disable IRQ and imprecise data aborts.  */
5913         mask = CPSR_A | CPSR_I;
5914         offset = 4;
5915         if (env->cp15.scr_el3 & SCR_IRQ) {
5916             /* IRQ routed to monitor mode */
5917             new_mode = ARM_CPU_MODE_MON;
5918             mask |= CPSR_F;
5919         }
5920         break;
5921     case EXCP_FIQ:
5922         new_mode = ARM_CPU_MODE_FIQ;
5923         addr = 0x1c;
5924         /* Disable FIQ, IRQ and imprecise data aborts.  */
5925         mask = CPSR_A | CPSR_I | CPSR_F;
5926         if (env->cp15.scr_el3 & SCR_FIQ) {
5927             /* FIQ routed to monitor mode */
5928             new_mode = ARM_CPU_MODE_MON;
5929         }
5930         offset = 4;
5931         break;
5932     case EXCP_SMC:
5933         new_mode = ARM_CPU_MODE_MON;
5934         addr = 0x08;
5935         mask = CPSR_A | CPSR_I | CPSR_F;
5936         offset = 0;
5937         break;
5938     default:
5939         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5940         return; /* Never happens.  Keep compiler happy.  */
5941     }
5942
5943     if (new_mode == ARM_CPU_MODE_MON) {
5944         addr += env->cp15.mvbar;
5945     } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
5946         /* High vectors. When enabled, base address cannot be remapped. */
5947         addr += 0xffff0000;
5948     } else {
5949         /* ARM v7 architectures provide a vector base address register to remap
5950          * the interrupt vector table.
5951          * This register is only followed in non-monitor mode, and is banked.
5952          * Note: only bits 31:5 are valid.
5953          */
5954         addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
5955     }
5956
5957     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
5958         env->cp15.scr_el3 &= ~SCR_NS;
5959     }
5960
5961     switch_mode (env, new_mode);
5962     /* For exceptions taken to AArch32 we must clear the SS bit in both
5963      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
5964      */
5965     env->uncached_cpsr &= ~PSTATE_SS;
5966     env->spsr = cpsr_read(env);
5967     /* Clear IT bits.  */
5968     env->condexec_bits = 0;
5969     /* Switch to the new mode, and to the correct instruction set.  */
5970     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
5971     env->daif |= mask;
5972     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
5973      * and we should just guard the thumb mode on V4 */
5974     if (arm_feature(env, ARM_FEATURE_V4T)) {
5975         env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
5976     }
5977     env->regs[14] = env->regs[15] + offset;
5978     env->regs[15] = addr;
5979 }
5980
5981 /* Handle exception entry to a target EL which is using AArch64 */
5982 static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
5983 {
5984     ARMCPU *cpu = ARM_CPU(cs);
5985     CPUARMState *env = &cpu->env;
5986     unsigned int new_el = env->exception.target_el;
5987     target_ulong addr = env->cp15.vbar_el[new_el];
5988     unsigned int new_mode = aarch64_pstate_mode(new_el, true);
5989
5990     if (arm_current_el(env) < new_el) {
5991         /* Entry vector offset depends on whether the implemented EL
5992          * immediately lower than the target level is using AArch32 or AArch64
5993          */
5994         bool is_aa64;
5995
5996         switch (new_el) {
5997         case 3:
5998             is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
5999             break;
6000         case 2:
6001             is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0;
6002             break;
6003         case 1:
6004             is_aa64 = is_a64(env);
6005             break;
6006         default:
6007             g_assert_not_reached();
6008         }
6009
6010         if (is_aa64) {
6011             addr += 0x400;
6012         } else {
6013             addr += 0x600;
6014         }
6015     } else if (pstate_read(env) & PSTATE_SP) {
6016         addr += 0x200;
6017     }
6018
6019     switch (cs->exception_index) {
6020     case EXCP_PREFETCH_ABORT:
6021     case EXCP_DATA_ABORT:
6022         env->cp15.far_el[new_el] = env->exception.vaddress;
6023         qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
6024                       env->cp15.far_el[new_el]);
6025         /* fall through */
6026     case EXCP_BKPT:
6027     case EXCP_UDEF:
6028     case EXCP_SWI:
6029     case EXCP_HVC:
6030     case EXCP_HYP_TRAP:
6031     case EXCP_SMC:
6032         env->cp15.esr_el[new_el] = env->exception.syndrome;
6033         break;
6034     case EXCP_IRQ:
6035     case EXCP_VIRQ:
6036         addr += 0x80;
6037         break;
6038     case EXCP_FIQ:
6039     case EXCP_VFIQ:
6040         addr += 0x100;
6041         break;
6042     case EXCP_SEMIHOST:
6043         qemu_log_mask(CPU_LOG_INT,
6044                       "...handling as semihosting call 0x%" PRIx64 "\n",
6045                       env->xregs[0]);
6046         env->xregs[0] = do_arm_semihosting(env);
6047         return;
6048     default:
6049         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
6050     }
6051
6052     if (is_a64(env)) {
6053         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env);
6054         aarch64_save_sp(env, arm_current_el(env));
6055         env->elr_el[new_el] = env->pc;
6056     } else {
6057         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
6058         if (!env->thumb) {
6059             env->cp15.esr_el[new_el] |= 1 << 25;
6060         }
6061         env->elr_el[new_el] = env->regs[15];
6062
6063         aarch64_sync_32_to_64(env);
6064
6065         env->condexec_bits = 0;
6066     }
6067     qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
6068                   env->elr_el[new_el]);
6069
6070     pstate_write(env, PSTATE_DAIF | new_mode);
6071     env->aarch64 = 1;
6072     aarch64_restore_sp(env, new_el);
6073
6074     env->pc = addr;
6075
6076     qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
6077                   new_el, env->pc, pstate_read(env));
6078 }
6079
6080 static inline bool check_for_semihosting(CPUState *cs)
6081 {
6082     /* Check whether this exception is a semihosting call; if so
6083      * then handle it and return true; otherwise return false.
6084      */
6085     ARMCPU *cpu = ARM_CPU(cs);
6086     CPUARMState *env = &cpu->env;
6087
6088     if (is_a64(env)) {
6089         if (cs->exception_index == EXCP_SEMIHOST) {
6090             /* This is always the 64-bit semihosting exception.
6091              * The "is this usermode" and "is semihosting enabled"
6092              * checks have been done at translate time.
6093              */
6094             qemu_log_mask(CPU_LOG_INT,
6095                           "...handling as semihosting call 0x%" PRIx64 "\n",
6096                           env->xregs[0]);
6097             env->xregs[0] = do_arm_semihosting(env);
6098             return true;
6099         }
6100         return false;
6101     } else {
6102         uint32_t imm;
6103
6104         /* Only intercept calls from privileged modes, to provide some
6105          * semblance of security.
6106          */
6107         if (!semihosting_enabled() ||
6108             ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)) {
6109             return false;
6110         }
6111
6112         switch (cs->exception_index) {
6113         case EXCP_SWI:
6114             /* Check for semihosting interrupt.  */
6115             if (env->thumb) {
6116                 imm = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
6117                     & 0xff;
6118                 if (imm == 0xab) {
6119                     break;
6120                 }
6121             } else {
6122                 imm = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
6123                     & 0xffffff;
6124                 if (imm == 0x123456) {
6125                     break;
6126                 }
6127             }
6128             return false;
6129         case EXCP_BKPT:
6130             /* See if this is a semihosting syscall.  */
6131             if (env->thumb) {
6132                 imm = arm_lduw_code(env, env->regs[15], env->bswap_code)
6133                     & 0xff;
6134                 if (imm == 0xab) {
6135                     env->regs[15] += 2;
6136                     break;
6137                 }
6138             }
6139             return false;
6140         default:
6141             return false;
6142         }
6143
6144         qemu_log_mask(CPU_LOG_INT,
6145                       "...handling as semihosting call 0x%x\n",
6146                       env->regs[0]);
6147         env->regs[0] = do_arm_semihosting(env);
6148         return true;
6149     }
6150 }
6151
6152 /* Handle a CPU exception for A and R profile CPUs.
6153  * Do any appropriate logging, handle PSCI calls, and then hand off
6154  * to the AArch64-entry or AArch32-entry function depending on the
6155  * target exception level's register width.
6156  */
6157 void arm_cpu_do_interrupt(CPUState *cs)
6158 {
6159     ARMCPU *cpu = ARM_CPU(cs);
6160     CPUARMState *env = &cpu->env;
6161     unsigned int new_el = env->exception.target_el;
6162
6163     assert(!IS_M(env));
6164
6165     arm_log_exception(cs->exception_index);
6166     qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
6167                   new_el);
6168     if (qemu_loglevel_mask(CPU_LOG_INT)
6169         && !excp_is_internal(cs->exception_index)) {
6170         qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n",
6171                       env->exception.syndrome >> ARM_EL_EC_SHIFT,
6172                       env->exception.syndrome);
6173     }
6174
6175     if (arm_is_psci_call(cpu, cs->exception_index)) {
6176         arm_handle_psci_call(cpu);
6177         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
6178         return;
6179     }
6180
6181     /* Semihosting semantics depend on the register width of the
6182      * code that caused the exception, not the target exception level,
6183      * so must be handled here.
6184      */
6185     if (check_for_semihosting(cs)) {
6186         return;
6187     }
6188
6189     assert(!excp_is_internal(cs->exception_index));
6190     if (arm_el_is_aa64(env, new_el)) {
6191         arm_cpu_do_interrupt_aarch64(cs);
6192     } else {
6193         arm_cpu_do_interrupt_aarch32(cs);
6194     }
6195
6196     if (!kvm_enabled()) {
6197         cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
6198     }
6199 }
6200
6201 /* Return the exception level which controls this address translation regime */
6202 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
6203 {
6204     switch (mmu_idx) {
6205     case ARMMMUIdx_S2NS:
6206     case ARMMMUIdx_S1E2:
6207         return 2;
6208     case ARMMMUIdx_S1E3:
6209         return 3;
6210     case ARMMMUIdx_S1SE0:
6211         return arm_el_is_aa64(env, 3) ? 1 : 3;
6212     case ARMMMUIdx_S1SE1:
6213     case ARMMMUIdx_S1NSE0:
6214     case ARMMMUIdx_S1NSE1:
6215         return 1;
6216     default:
6217         g_assert_not_reached();
6218     }
6219 }
6220
6221 /* Return true if this address translation regime is secure */
6222 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
6223 {
6224     switch (mmu_idx) {
6225     case ARMMMUIdx_S12NSE0:
6226     case ARMMMUIdx_S12NSE1:
6227     case ARMMMUIdx_S1NSE0:
6228     case ARMMMUIdx_S1NSE1:
6229     case ARMMMUIdx_S1E2:
6230     case ARMMMUIdx_S2NS:
6231         return false;
6232     case ARMMMUIdx_S1E3:
6233     case ARMMMUIdx_S1SE0:
6234     case ARMMMUIdx_S1SE1:
6235         return true;
6236     default:
6237         g_assert_not_reached();
6238     }
6239 }
6240
6241 /* Return the SCTLR value which controls this address translation regime */
6242 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
6243 {
6244     return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
6245 }
6246
6247 /* Return true if the specified stage of address translation is disabled */
6248 static inline bool regime_translation_disabled(CPUARMState *env,
6249                                                ARMMMUIdx mmu_idx)
6250 {
6251     if (mmu_idx == ARMMMUIdx_S2NS) {
6252         return (env->cp15.hcr_el2 & HCR_VM) == 0;
6253     }
6254     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
6255 }
6256
6257 /* Return the TCR controlling this translation regime */
6258 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
6259 {
6260     if (mmu_idx == ARMMMUIdx_S2NS) {
6261         return &env->cp15.vtcr_el2;
6262     }
6263     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
6264 }
6265
6266 /* Return the TTBR associated with this translation regime */
6267 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
6268                                    int ttbrn)
6269 {
6270     if (mmu_idx == ARMMMUIdx_S2NS) {
6271         return env->cp15.vttbr_el2;
6272     }
6273     if (ttbrn == 0) {
6274         return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
6275     } else {
6276         return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
6277     }
6278 }
6279
6280 /* Return true if the translation regime is using LPAE format page tables */
6281 static inline bool regime_using_lpae_format(CPUARMState *env,
6282                                             ARMMMUIdx mmu_idx)
6283 {
6284     int el = regime_el(env, mmu_idx);
6285     if (el == 2 || arm_el_is_aa64(env, el)) {
6286         return true;
6287     }
6288     if (arm_feature(env, ARM_FEATURE_LPAE)
6289         && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
6290         return true;
6291     }
6292     return false;
6293 }
6294
6295 /* Returns true if the stage 1 translation regime is using LPAE format page
6296  * tables. Used when raising alignment exceptions, whose FSR changes depending
6297  * on whether the long or short descriptor format is in use. */
6298 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
6299 {
6300     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
6301         mmu_idx += ARMMMUIdx_S1NSE0;
6302     }
6303
6304     return regime_using_lpae_format(env, mmu_idx);
6305 }
6306
6307 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
6308 {
6309     switch (mmu_idx) {
6310     case ARMMMUIdx_S1SE0:
6311     case ARMMMUIdx_S1NSE0:
6312         return true;
6313     default:
6314         return false;
6315     case ARMMMUIdx_S12NSE0:
6316     case ARMMMUIdx_S12NSE1:
6317         g_assert_not_reached();
6318     }
6319 }
6320
6321 /* Translate section/page access permissions to page
6322  * R/W protection flags
6323  *
6324  * @env:         CPUARMState
6325  * @mmu_idx:     MMU index indicating required translation regime
6326  * @ap:          The 3-bit access permissions (AP[2:0])
6327  * @domain_prot: The 2-bit domain access permissions
6328  */
6329 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
6330                                 int ap, int domain_prot)
6331 {
6332     bool is_user = regime_is_user(env, mmu_idx);
6333
6334     if (domain_prot == 3) {
6335         return PAGE_READ | PAGE_WRITE;
6336     }
6337
6338     switch (ap) {
6339     case 0:
6340         if (arm_feature(env, ARM_FEATURE_V7)) {
6341             return 0;
6342         }
6343         switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
6344         case SCTLR_S:
6345             return is_user ? 0 : PAGE_READ;
6346         case SCTLR_R:
6347             return PAGE_READ;
6348         default:
6349             return 0;
6350         }
6351     case 1:
6352         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6353     case 2:
6354         if (is_user) {
6355             return PAGE_READ;
6356         } else {
6357             return PAGE_READ | PAGE_WRITE;
6358         }
6359     case 3:
6360         return PAGE_READ | PAGE_WRITE;
6361     case 4: /* Reserved.  */
6362         return 0;
6363     case 5:
6364         return is_user ? 0 : PAGE_READ;
6365     case 6:
6366         return PAGE_READ;
6367     case 7:
6368         if (!arm_feature(env, ARM_FEATURE_V6K)) {
6369             return 0;
6370         }
6371         return PAGE_READ;
6372     default:
6373         g_assert_not_reached();
6374     }
6375 }
6376
6377 /* Translate section/page access permissions to page
6378  * R/W protection flags.
6379  *
6380  * @ap:      The 2-bit simple AP (AP[2:1])
6381  * @is_user: TRUE if accessing from PL0
6382  */
6383 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
6384 {
6385     switch (ap) {
6386     case 0:
6387         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6388     case 1:
6389         return PAGE_READ | PAGE_WRITE;
6390     case 2:
6391         return is_user ? 0 : PAGE_READ;
6392     case 3:
6393         return PAGE_READ;
6394     default:
6395         g_assert_not_reached();
6396     }
6397 }
6398
6399 static inline int
6400 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
6401 {
6402     return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
6403 }
6404
6405 /* Translate S2 section/page access permissions to protection flags
6406  *
6407  * @env:     CPUARMState
6408  * @s2ap:    The 2-bit stage2 access permissions (S2AP)
6409  * @xn:      XN (execute-never) bit
6410  */
6411 static int get_S2prot(CPUARMState *env, int s2ap, int xn)
6412 {
6413     int prot = 0;
6414
6415     if (s2ap & 1) {
6416         prot |= PAGE_READ;
6417     }
6418     if (s2ap & 2) {
6419         prot |= PAGE_WRITE;
6420     }
6421     if (!xn) {
6422         prot |= PAGE_EXEC;
6423     }
6424     return prot;
6425 }
6426
6427 /* Translate section/page access permissions to protection flags
6428  *
6429  * @env:     CPUARMState
6430  * @mmu_idx: MMU index indicating required translation regime
6431  * @is_aa64: TRUE if AArch64
6432  * @ap:      The 2-bit simple AP (AP[2:1])
6433  * @ns:      NS (non-secure) bit
6434  * @xn:      XN (execute-never) bit
6435  * @pxn:     PXN (privileged execute-never) bit
6436  */
6437 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
6438                       int ap, int ns, int xn, int pxn)
6439 {
6440     bool is_user = regime_is_user(env, mmu_idx);
6441     int prot_rw, user_rw;
6442     bool have_wxn;
6443     int wxn = 0;
6444
6445     assert(mmu_idx != ARMMMUIdx_S2NS);
6446
6447     user_rw = simple_ap_to_rw_prot_is_user(ap, true);
6448     if (is_user) {
6449         prot_rw = user_rw;
6450     } else {
6451         prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
6452     }
6453
6454     if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
6455         return prot_rw;
6456     }
6457
6458     /* TODO have_wxn should be replaced with
6459      *   ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
6460      * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
6461      * compatible processors have EL2, which is required for [U]WXN.
6462      */
6463     have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
6464
6465     if (have_wxn) {
6466         wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
6467     }
6468
6469     if (is_aa64) {
6470         switch (regime_el(env, mmu_idx)) {
6471         case 1:
6472             if (!is_user) {
6473                 xn = pxn || (user_rw & PAGE_WRITE);
6474             }
6475             break;
6476         case 2:
6477         case 3:
6478             break;
6479         }
6480     } else if (arm_feature(env, ARM_FEATURE_V7)) {
6481         switch (regime_el(env, mmu_idx)) {
6482         case 1:
6483         case 3:
6484             if (is_user) {
6485                 xn = xn || !(user_rw & PAGE_READ);
6486             } else {
6487                 int uwxn = 0;
6488                 if (have_wxn) {
6489                     uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
6490                 }
6491                 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
6492                      (uwxn && (user_rw & PAGE_WRITE));
6493             }
6494             break;
6495         case 2:
6496             break;
6497         }
6498     } else {
6499         xn = wxn = 0;
6500     }
6501
6502     if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
6503         return prot_rw;
6504     }
6505     return prot_rw | PAGE_EXEC;
6506 }
6507
6508 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
6509                                      uint32_t *table, uint32_t address)
6510 {
6511     /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
6512     TCR *tcr = regime_tcr(env, mmu_idx);
6513
6514     if (address & tcr->mask) {
6515         if (tcr->raw_tcr & TTBCR_PD1) {
6516             /* Translation table walk disabled for TTBR1 */
6517             return false;
6518         }
6519         *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
6520     } else {
6521         if (tcr->raw_tcr & TTBCR_PD0) {
6522             /* Translation table walk disabled for TTBR0 */
6523             return false;
6524         }
6525         *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
6526     }
6527     *table |= (address >> 18) & 0x3ffc;
6528     return true;
6529 }
6530
6531 /* Translate a S1 pagetable walk through S2 if needed.  */
6532 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
6533                                hwaddr addr, MemTxAttrs txattrs,
6534                                uint32_t *fsr,
6535                                ARMMMUFaultInfo *fi)
6536 {
6537     if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) &&
6538         !regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
6539         target_ulong s2size;
6540         hwaddr s2pa;
6541         int s2prot;
6542         int ret;
6543
6544         ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
6545                                  &txattrs, &s2prot, &s2size, fsr, fi);
6546         if (ret) {
6547             fi->s2addr = addr;
6548             fi->stage2 = true;
6549             fi->s1ptw = true;
6550             return ~0;
6551         }
6552         addr = s2pa;
6553     }
6554     return addr;
6555 }
6556
6557 /* All loads done in the course of a page table walk go through here.
6558  * TODO: rather than ignoring errors from physical memory reads (which
6559  * are external aborts in ARM terminology) we should propagate this
6560  * error out so that we can turn it into a Data Abort if this walk
6561  * was being done for a CPU load/store or an address translation instruction
6562  * (but not if it was for a debug access).
6563  */
6564 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6565                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6566                             ARMMMUFaultInfo *fi)
6567 {
6568     ARMCPU *cpu = ARM_CPU(cs);
6569     CPUARMState *env = &cpu->env;
6570     MemTxAttrs attrs = {};
6571     AddressSpace *as;
6572
6573     attrs.secure = is_secure;
6574     as = arm_addressspace(cs, attrs);
6575     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6576     if (fi->s1ptw) {
6577         return 0;
6578     }
6579     return address_space_ldl(as, addr, attrs, NULL);
6580 }
6581
6582 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6583                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6584                             ARMMMUFaultInfo *fi)
6585 {
6586     ARMCPU *cpu = ARM_CPU(cs);
6587     CPUARMState *env = &cpu->env;
6588     MemTxAttrs attrs = {};
6589     AddressSpace *as;
6590
6591     attrs.secure = is_secure;
6592     as = arm_addressspace(cs, attrs);
6593     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6594     if (fi->s1ptw) {
6595         return 0;
6596     }
6597     return address_space_ldq(as, addr, attrs, NULL);
6598 }
6599
6600 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
6601                              int access_type, ARMMMUIdx mmu_idx,
6602                              hwaddr *phys_ptr, int *prot,
6603                              target_ulong *page_size, uint32_t *fsr,
6604                              ARMMMUFaultInfo *fi)
6605 {
6606     CPUState *cs = CPU(arm_env_get_cpu(env));
6607     int code;
6608     uint32_t table;
6609     uint32_t desc;
6610     int type;
6611     int ap;
6612     int domain = 0;
6613     int domain_prot;
6614     hwaddr phys_addr;
6615     uint32_t dacr;
6616
6617     /* Pagetable walk.  */
6618     /* Lookup l1 descriptor.  */
6619     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6620         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6621         code = 5;
6622         goto do_fault;
6623     }
6624     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6625                        mmu_idx, fsr, fi);
6626     type = (desc & 3);
6627     domain = (desc >> 5) & 0x0f;
6628     if (regime_el(env, mmu_idx) == 1) {
6629         dacr = env->cp15.dacr_ns;
6630     } else {
6631         dacr = env->cp15.dacr_s;
6632     }
6633     domain_prot = (dacr >> (domain * 2)) & 3;
6634     if (type == 0) {
6635         /* Section translation fault.  */
6636         code = 5;
6637         goto do_fault;
6638     }
6639     if (domain_prot == 0 || domain_prot == 2) {
6640         if (type == 2)
6641             code = 9; /* Section domain fault.  */
6642         else
6643             code = 11; /* Page domain fault.  */
6644         goto do_fault;
6645     }
6646     if (type == 2) {
6647         /* 1Mb section.  */
6648         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6649         ap = (desc >> 10) & 3;
6650         code = 13;
6651         *page_size = 1024 * 1024;
6652     } else {
6653         /* Lookup l2 entry.  */
6654         if (type == 1) {
6655             /* Coarse pagetable.  */
6656             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6657         } else {
6658             /* Fine pagetable.  */
6659             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
6660         }
6661         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6662                            mmu_idx, fsr, fi);
6663         switch (desc & 3) {
6664         case 0: /* Page translation fault.  */
6665             code = 7;
6666             goto do_fault;
6667         case 1: /* 64k page.  */
6668             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6669             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
6670             *page_size = 0x10000;
6671             break;
6672         case 2: /* 4k page.  */
6673             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6674             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
6675             *page_size = 0x1000;
6676             break;
6677         case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
6678             if (type == 1) {
6679                 /* ARMv6/XScale extended small page format */
6680                 if (arm_feature(env, ARM_FEATURE_XSCALE)
6681                     || arm_feature(env, ARM_FEATURE_V6)) {
6682                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6683                     *page_size = 0x1000;
6684                 } else {
6685                     /* UNPREDICTABLE in ARMv5; we choose to take a
6686                      * page translation fault.
6687                      */
6688                     code = 7;
6689                     goto do_fault;
6690                 }
6691             } else {
6692                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
6693                 *page_size = 0x400;
6694             }
6695             ap = (desc >> 4) & 3;
6696             break;
6697         default:
6698             /* Never happens, but compiler isn't smart enough to tell.  */
6699             abort();
6700         }
6701         code = 15;
6702     }
6703     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6704     *prot |= *prot ? PAGE_EXEC : 0;
6705     if (!(*prot & (1 << access_type))) {
6706         /* Access permission fault.  */
6707         goto do_fault;
6708     }
6709     *phys_ptr = phys_addr;
6710     return false;
6711 do_fault:
6712     *fsr = code | (domain << 4);
6713     return true;
6714 }
6715
6716 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
6717                              int access_type, ARMMMUIdx mmu_idx,
6718                              hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
6719                              target_ulong *page_size, uint32_t *fsr,
6720                              ARMMMUFaultInfo *fi)
6721 {
6722     CPUState *cs = CPU(arm_env_get_cpu(env));
6723     int code;
6724     uint32_t table;
6725     uint32_t desc;
6726     uint32_t xn;
6727     uint32_t pxn = 0;
6728     int type;
6729     int ap;
6730     int domain = 0;
6731     int domain_prot;
6732     hwaddr phys_addr;
6733     uint32_t dacr;
6734     bool ns;
6735
6736     /* Pagetable walk.  */
6737     /* Lookup l1 descriptor.  */
6738     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6739         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6740         code = 5;
6741         goto do_fault;
6742     }
6743     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6744                        mmu_idx, fsr, fi);
6745     type = (desc & 3);
6746     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
6747         /* Section translation fault, or attempt to use the encoding
6748          * which is Reserved on implementations without PXN.
6749          */
6750         code = 5;
6751         goto do_fault;
6752     }
6753     if ((type == 1) || !(desc & (1 << 18))) {
6754         /* Page or Section.  */
6755         domain = (desc >> 5) & 0x0f;
6756     }
6757     if (regime_el(env, mmu_idx) == 1) {
6758         dacr = env->cp15.dacr_ns;
6759     } else {
6760         dacr = env->cp15.dacr_s;
6761     }
6762     domain_prot = (dacr >> (domain * 2)) & 3;
6763     if (domain_prot == 0 || domain_prot == 2) {
6764         if (type != 1) {
6765             code = 9; /* Section domain fault.  */
6766         } else {
6767             code = 11; /* Page domain fault.  */
6768         }
6769         goto do_fault;
6770     }
6771     if (type != 1) {
6772         if (desc & (1 << 18)) {
6773             /* Supersection.  */
6774             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
6775             phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
6776             phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
6777             *page_size = 0x1000000;
6778         } else {
6779             /* Section.  */
6780             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6781             *page_size = 0x100000;
6782         }
6783         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
6784         xn = desc & (1 << 4);
6785         pxn = desc & 1;
6786         code = 13;
6787         ns = extract32(desc, 19, 1);
6788     } else {
6789         if (arm_feature(env, ARM_FEATURE_PXN)) {
6790             pxn = (desc >> 2) & 1;
6791         }
6792         ns = extract32(desc, 3, 1);
6793         /* Lookup l2 entry.  */
6794         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6795         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6796                            mmu_idx, fsr, fi);
6797         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
6798         switch (desc & 3) {
6799         case 0: /* Page translation fault.  */
6800             code = 7;
6801             goto do_fault;
6802         case 1: /* 64k page.  */
6803             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6804             xn = desc & (1 << 15);
6805             *page_size = 0x10000;
6806             break;
6807         case 2: case 3: /* 4k page.  */
6808             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6809             xn = desc & 1;
6810             *page_size = 0x1000;
6811             break;
6812         default:
6813             /* Never happens, but compiler isn't smart enough to tell.  */
6814             abort();
6815         }
6816         code = 15;
6817     }
6818     if (domain_prot == 3) {
6819         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
6820     } else {
6821         if (pxn && !regime_is_user(env, mmu_idx)) {
6822             xn = 1;
6823         }
6824         if (xn && access_type == 2)
6825             goto do_fault;
6826
6827         if (arm_feature(env, ARM_FEATURE_V6K) &&
6828                 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
6829             /* The simplified model uses AP[0] as an access control bit.  */
6830             if ((ap & 1) == 0) {
6831                 /* Access flag fault.  */
6832                 code = (code == 15) ? 6 : 3;
6833                 goto do_fault;
6834             }
6835             *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
6836         } else {
6837             *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6838         }
6839         if (*prot && !xn) {
6840             *prot |= PAGE_EXEC;
6841         }
6842         if (!(*prot & (1 << access_type))) {
6843             /* Access permission fault.  */
6844             goto do_fault;
6845         }
6846     }
6847     if (ns) {
6848         /* The NS bit will (as required by the architecture) have no effect if
6849          * the CPU doesn't support TZ or this is a non-secure translation
6850          * regime, because the attribute will already be non-secure.
6851          */
6852         attrs->secure = false;
6853     }
6854     *phys_ptr = phys_addr;
6855     return false;
6856 do_fault:
6857     *fsr = code | (domain << 4);
6858     return true;
6859 }
6860
6861 /* Fault type for long-descriptor MMU fault reporting; this corresponds
6862  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
6863  */
6864 typedef enum {
6865     translation_fault = 1,
6866     access_fault = 2,
6867     permission_fault = 3,
6868 } MMUFaultType;
6869
6870 /*
6871  * check_s2_mmu_setup
6872  * @cpu:        ARMCPU
6873  * @is_aa64:    True if the translation regime is in AArch64 state
6874  * @startlevel: Suggested starting level
6875  * @inputsize:  Bitsize of IPAs
6876  * @stride:     Page-table stride (See the ARM ARM)
6877  *
6878  * Returns true if the suggested S2 translation parameters are OK and
6879  * false otherwise.
6880  */
6881 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
6882                                int inputsize, int stride)
6883 {
6884     const int grainsize = stride + 3;
6885     int startsizecheck;
6886
6887     /* Negative levels are never allowed.  */
6888     if (level < 0) {
6889         return false;
6890     }
6891
6892     startsizecheck = inputsize - ((3 - level) * stride + grainsize);
6893     if (startsizecheck < 1 || startsizecheck > stride + 4) {
6894         return false;
6895     }
6896
6897     if (is_aa64) {
6898         CPUARMState *env = &cpu->env;
6899         unsigned int pamax = arm_pamax(cpu);
6900
6901         switch (stride) {
6902         case 13: /* 64KB Pages.  */
6903             if (level == 0 || (level == 1 && pamax <= 42)) {
6904                 return false;
6905             }
6906             break;
6907         case 11: /* 16KB Pages.  */
6908             if (level == 0 || (level == 1 && pamax <= 40)) {
6909                 return false;
6910             }
6911             break;
6912         case 9: /* 4KB Pages.  */
6913             if (level == 0 && pamax <= 42) {
6914                 return false;
6915             }
6916             break;
6917         default:
6918             g_assert_not_reached();
6919         }
6920
6921         /* Inputsize checks.  */
6922         if (inputsize > pamax &&
6923             (arm_el_is_aa64(env, 1) || inputsize > 40)) {
6924             /* This is CONSTRAINED UNPREDICTABLE and we choose to fault.  */
6925             return false;
6926         }
6927     } else {
6928         /* AArch32 only supports 4KB pages. Assert on that.  */
6929         assert(stride == 9);
6930
6931         if (level == 0) {
6932             return false;
6933         }
6934     }
6935     return true;
6936 }
6937
6938 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
6939                                int access_type, ARMMMUIdx mmu_idx,
6940                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
6941                                target_ulong *page_size_ptr, uint32_t *fsr,
6942                                ARMMMUFaultInfo *fi)
6943 {
6944     ARMCPU *cpu = arm_env_get_cpu(env);
6945     CPUState *cs = CPU(cpu);
6946     /* Read an LPAE long-descriptor translation table. */
6947     MMUFaultType fault_type = translation_fault;
6948     uint32_t level = 1;
6949     uint32_t epd = 0;
6950     int32_t t0sz, t1sz;
6951     uint32_t tg;
6952     uint64_t ttbr;
6953     int ttbr_select;
6954     hwaddr descaddr, descmask;
6955     uint32_t tableattrs;
6956     target_ulong page_size;
6957     uint32_t attrs;
6958     int32_t stride = 9;
6959     int32_t va_size = 32;
6960     int inputsize;
6961     int32_t tbi = 0;
6962     TCR *tcr = regime_tcr(env, mmu_idx);
6963     int ap, ns, xn, pxn;
6964     uint32_t el = regime_el(env, mmu_idx);
6965     bool ttbr1_valid = true;
6966     uint64_t descaddrmask;
6967
6968     /* TODO:
6969      * This code does not handle the different format TCR for VTCR_EL2.
6970      * This code also does not support shareability levels.
6971      * Attribute and permission bit handling should also be checked when adding
6972      * support for those page table walks.
6973      */
6974     if (arm_el_is_aa64(env, el)) {
6975         va_size = 64;
6976         if (el > 1) {
6977             if (mmu_idx != ARMMMUIdx_S2NS) {
6978                 tbi = extract64(tcr->raw_tcr, 20, 1);
6979             }
6980         } else {
6981             if (extract64(address, 55, 1)) {
6982                 tbi = extract64(tcr->raw_tcr, 38, 1);
6983             } else {
6984                 tbi = extract64(tcr->raw_tcr, 37, 1);
6985             }
6986         }
6987         tbi *= 8;
6988
6989         /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
6990          * invalid.
6991          */
6992         if (el > 1) {
6993             ttbr1_valid = false;
6994         }
6995     } else {
6996         /* There is no TTBR1 for EL2 */
6997         if (el == 2) {
6998             ttbr1_valid = false;
6999         }
7000     }
7001
7002     /* Determine whether this address is in the region controlled by
7003      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
7004      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
7005      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
7006      */
7007     if (va_size == 64) {
7008         /* AArch64 translation.  */
7009         t0sz = extract32(tcr->raw_tcr, 0, 6);
7010         t0sz = MIN(t0sz, 39);
7011         t0sz = MAX(t0sz, 16);
7012     } else if (mmu_idx != ARMMMUIdx_S2NS) {
7013         /* AArch32 stage 1 translation.  */
7014         t0sz = extract32(tcr->raw_tcr, 0, 3);
7015     } else {
7016         /* AArch32 stage 2 translation.  */
7017         bool sext = extract32(tcr->raw_tcr, 4, 1);
7018         bool sign = extract32(tcr->raw_tcr, 3, 1);
7019         t0sz = sextract32(tcr->raw_tcr, 0, 4);
7020
7021         /* If the sign-extend bit is not the same as t0sz[3], the result
7022          * is unpredictable. Flag this as a guest error.  */
7023         if (sign != sext) {
7024             qemu_log_mask(LOG_GUEST_ERROR,
7025                           "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n");
7026         }
7027     }
7028     t1sz = extract32(tcr->raw_tcr, 16, 6);
7029     if (va_size == 64) {
7030         t1sz = MIN(t1sz, 39);
7031         t1sz = MAX(t1sz, 16);
7032     }
7033     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
7034         /* there is a ttbr0 region and we are in it (high bits all zero) */
7035         ttbr_select = 0;
7036     } else if (ttbr1_valid && t1sz &&
7037                !extract64(~address, va_size - t1sz, t1sz - tbi)) {
7038         /* there is a ttbr1 region and we are in it (high bits all one) */
7039         ttbr_select = 1;
7040     } else if (!t0sz) {
7041         /* ttbr0 region is "everything not in the ttbr1 region" */
7042         ttbr_select = 0;
7043     } else if (!t1sz && ttbr1_valid) {
7044         /* ttbr1 region is "everything not in the ttbr0 region" */
7045         ttbr_select = 1;
7046     } else {
7047         /* in the gap between the two regions, this is a Translation fault */
7048         fault_type = translation_fault;
7049         goto do_fault;
7050     }
7051
7052     /* Note that QEMU ignores shareability and cacheability attributes,
7053      * so we don't need to do anything with the SH, ORGN, IRGN fields
7054      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
7055      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
7056      * implement any ASID-like capability so we can ignore it (instead
7057      * we will always flush the TLB any time the ASID is changed).
7058      */
7059     if (ttbr_select == 0) {
7060         ttbr = regime_ttbr(env, mmu_idx, 0);
7061         if (el < 2) {
7062             epd = extract32(tcr->raw_tcr, 7, 1);
7063         }
7064         inputsize = va_size - t0sz;
7065
7066         tg = extract32(tcr->raw_tcr, 14, 2);
7067         if (tg == 1) { /* 64KB pages */
7068             stride = 13;
7069         }
7070         if (tg == 2) { /* 16KB pages */
7071             stride = 11;
7072         }
7073     } else {
7074         /* We should only be here if TTBR1 is valid */
7075         assert(ttbr1_valid);
7076
7077         ttbr = regime_ttbr(env, mmu_idx, 1);
7078         epd = extract32(tcr->raw_tcr, 23, 1);
7079         inputsize = va_size - t1sz;
7080
7081         tg = extract32(tcr->raw_tcr, 30, 2);
7082         if (tg == 3)  { /* 64KB pages */
7083             stride = 13;
7084         }
7085         if (tg == 1) { /* 16KB pages */
7086             stride = 11;
7087         }
7088     }
7089
7090     /* Here we should have set up all the parameters for the translation:
7091      * va_size, inputsize, ttbr, epd, stride, tbi
7092      */
7093
7094     if (epd) {
7095         /* Translation table walk disabled => Translation fault on TLB miss
7096          * Note: This is always 0 on 64-bit EL2 and EL3.
7097          */
7098         goto do_fault;
7099     }
7100
7101     if (mmu_idx != ARMMMUIdx_S2NS) {
7102         /* The starting level depends on the virtual address size (which can
7103          * be up to 48 bits) and the translation granule size. It indicates
7104          * the number of strides (stride bits at a time) needed to
7105          * consume the bits of the input address. In the pseudocode this is:
7106          *  level = 4 - RoundUp((inputsize - grainsize) / stride)
7107          * where their 'inputsize' is our 'inputsize', 'grainsize' is
7108          * our 'stride + 3' and 'stride' is our 'stride'.
7109          * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
7110          * = 4 - (inputsize - stride - 3 + stride - 1) / stride
7111          * = 4 - (inputsize - 4) / stride;
7112          */
7113         level = 4 - (inputsize - 4) / stride;
7114     } else {
7115         /* For stage 2 translations the starting level is specified by the
7116          * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
7117          */
7118         int startlevel = extract32(tcr->raw_tcr, 6, 2);
7119         bool ok;
7120
7121         if (va_size == 32 || stride == 9) {
7122             /* AArch32 or 4KB pages */
7123             level = 2 - startlevel;
7124         } else {
7125             /* 16KB or 64KB pages */
7126             level = 3 - startlevel;
7127         }
7128
7129         /* Check that the starting level is valid. */
7130         ok = check_s2_mmu_setup(cpu, va_size == 64, level, inputsize, stride);
7131         if (!ok) {
7132             /* AArch64 reports these as level 0 faults.
7133              * AArch32 reports these as level 1 faults.
7134              */
7135             level = va_size == 64 ? 0 : 1;
7136             fault_type = translation_fault;
7137             goto do_fault;
7138         }
7139     }
7140
7141     /* Clear the vaddr bits which aren't part of the within-region address,
7142      * so that we don't have to special case things when calculating the
7143      * first descriptor address.
7144      */
7145     if (va_size != inputsize) {
7146         address &= (1ULL << inputsize) - 1;
7147     }
7148
7149     descmask = (1ULL << (stride + 3)) - 1;
7150
7151     /* Now we can extract the actual base address from the TTBR */
7152     descaddr = extract64(ttbr, 0, 48);
7153     descaddr &= ~((1ULL << (inputsize - (stride * (4 - level)))) - 1);
7154
7155     /* The address field in the descriptor goes up to bit 39 for ARMv7
7156      * but up to bit 47 for ARMv8.
7157      */
7158     if (arm_feature(env, ARM_FEATURE_V8)) {
7159         descaddrmask = 0xfffffffff000ULL;
7160     } else {
7161         descaddrmask = 0xfffffff000ULL;
7162     }
7163
7164     /* Secure accesses start with the page table in secure memory and
7165      * can be downgraded to non-secure at any step. Non-secure accesses
7166      * remain non-secure. We implement this by just ORing in the NSTable/NS
7167      * bits at each step.
7168      */
7169     tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
7170     for (;;) {
7171         uint64_t descriptor;
7172         bool nstable;
7173
7174         descaddr |= (address >> (stride * (4 - level))) & descmask;
7175         descaddr &= ~7ULL;
7176         nstable = extract32(tableattrs, 4, 1);
7177         descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi);
7178         if (fi->s1ptw) {
7179             goto do_fault;
7180         }
7181
7182         if (!(descriptor & 1) ||
7183             (!(descriptor & 2) && (level == 3))) {
7184             /* Invalid, or the Reserved level 3 encoding */
7185             goto do_fault;
7186         }
7187         descaddr = descriptor & descaddrmask;
7188
7189         if ((descriptor & 2) && (level < 3)) {
7190             /* Table entry. The top five bits are attributes which  may
7191              * propagate down through lower levels of the table (and
7192              * which are all arranged so that 0 means "no effect", so
7193              * we can gather them up by ORing in the bits at each level).
7194              */
7195             tableattrs |= extract64(descriptor, 59, 5);
7196             level++;
7197             continue;
7198         }
7199         /* Block entry at level 1 or 2, or page entry at level 3.
7200          * These are basically the same thing, although the number
7201          * of bits we pull in from the vaddr varies.
7202          */
7203         page_size = (1ULL << ((stride * (4 - level)) + 3));
7204         descaddr |= (address & (page_size - 1));
7205         /* Extract attributes from the descriptor */
7206         attrs = extract64(descriptor, 2, 10)
7207             | (extract64(descriptor, 52, 12) << 10);
7208
7209         if (mmu_idx == ARMMMUIdx_S2NS) {
7210             /* Stage 2 table descriptors do not include any attribute fields */
7211             break;
7212         }
7213         /* Merge in attributes from table descriptors */
7214         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
7215         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
7216         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
7217          * means "force PL1 access only", which means forcing AP[1] to 0.
7218          */
7219         if (extract32(tableattrs, 2, 1)) {
7220             attrs &= ~(1 << 4);
7221         }
7222         attrs |= nstable << 3; /* NS */
7223         break;
7224     }
7225     /* Here descaddr is the final physical address, and attributes
7226      * are all in attrs.
7227      */
7228     fault_type = access_fault;
7229     if ((attrs & (1 << 8)) == 0) {
7230         /* Access flag */
7231         goto do_fault;
7232     }
7233
7234     ap = extract32(attrs, 4, 2);
7235     xn = extract32(attrs, 12, 1);
7236
7237     if (mmu_idx == ARMMMUIdx_S2NS) {
7238         ns = true;
7239         *prot = get_S2prot(env, ap, xn);
7240     } else {
7241         ns = extract32(attrs, 3, 1);
7242         pxn = extract32(attrs, 11, 1);
7243         *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
7244     }
7245
7246     fault_type = permission_fault;
7247     if (!(*prot & (1 << access_type))) {
7248         goto do_fault;
7249     }
7250
7251     if (ns) {
7252         /* The NS bit will (as required by the architecture) have no effect if
7253          * the CPU doesn't support TZ or this is a non-secure translation
7254          * regime, because the attribute will already be non-secure.
7255          */
7256         txattrs->secure = false;
7257     }
7258     *phys_ptr = descaddr;
7259     *page_size_ptr = page_size;
7260     return false;
7261
7262 do_fault:
7263     /* Long-descriptor format IFSR/DFSR value */
7264     *fsr = (1 << 9) | (fault_type << 2) | level;
7265     /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2.  */
7266     fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS);
7267     return true;
7268 }
7269
7270 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
7271                                                 ARMMMUIdx mmu_idx,
7272                                                 int32_t address, int *prot)
7273 {
7274     *prot = PAGE_READ | PAGE_WRITE;
7275     switch (address) {
7276     case 0xF0000000 ... 0xFFFFFFFF:
7277         if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
7278             *prot |= PAGE_EXEC;
7279         }
7280         break;
7281     case 0x00000000 ... 0x7FFFFFFF:
7282         *prot |= PAGE_EXEC;
7283         break;
7284     }
7285
7286 }
7287
7288 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
7289                                  int access_type, ARMMMUIdx mmu_idx,
7290                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7291 {
7292     ARMCPU *cpu = arm_env_get_cpu(env);
7293     int n;
7294     bool is_user = regime_is_user(env, mmu_idx);
7295
7296     *phys_ptr = address;
7297     *prot = 0;
7298
7299     if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
7300         get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7301     } else { /* MPU enabled */
7302         for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
7303             /* region search */
7304             uint32_t base = env->pmsav7.drbar[n];
7305             uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
7306             uint32_t rmask;
7307             bool srdis = false;
7308
7309             if (!(env->pmsav7.drsr[n] & 0x1)) {
7310                 continue;
7311             }
7312
7313             if (!rsize) {
7314                 qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
7315                 continue;
7316             }
7317             rsize++;
7318             rmask = (1ull << rsize) - 1;
7319
7320             if (base & rmask) {
7321                 qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
7322                               "to DRSR region size, mask = %" PRIx32,
7323                               base, rmask);
7324                 continue;
7325             }
7326
7327             if (address < base || address > base + rmask) {
7328                 continue;
7329             }
7330
7331             /* Region matched */
7332
7333             if (rsize >= 8) { /* no subregions for regions < 256 bytes */
7334                 int i, snd;
7335                 uint32_t srdis_mask;
7336
7337                 rsize -= 3; /* sub region size (power of 2) */
7338                 snd = ((address - base) >> rsize) & 0x7;
7339                 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
7340
7341                 srdis_mask = srdis ? 0x3 : 0x0;
7342                 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
7343                     /* This will check in groups of 2, 4 and then 8, whether
7344                      * the subregion bits are consistent. rsize is incremented
7345                      * back up to give the region size, considering consistent
7346                      * adjacent subregions as one region. Stop testing if rsize
7347                      * is already big enough for an entire QEMU page.
7348                      */
7349                     int snd_rounded = snd & ~(i - 1);
7350                     uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
7351                                                      snd_rounded + 8, i);
7352                     if (srdis_mask ^ srdis_multi) {
7353                         break;
7354                     }
7355                     srdis_mask = (srdis_mask << i) | srdis_mask;
7356                     rsize++;
7357                 }
7358             }
7359             if (rsize < TARGET_PAGE_BITS) {
7360                 qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
7361                               "alignment of %" PRIu32 " bits. Minimum is %d\n",
7362                               rsize, TARGET_PAGE_BITS);
7363                 continue;
7364             }
7365             if (srdis) {
7366                 continue;
7367             }
7368             break;
7369         }
7370
7371         if (n == -1) { /* no hits */
7372             if (cpu->pmsav7_dregion &&
7373                 (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
7374                 /* background fault */
7375                 *fsr = 0;
7376                 return true;
7377             }
7378             get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7379         } else { /* a MPU hit! */
7380             uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
7381
7382             if (is_user) { /* User mode AP bit decoding */
7383                 switch (ap) {
7384                 case 0:
7385                 case 1:
7386                 case 5:
7387                     break; /* no access */
7388                 case 3:
7389                     *prot |= PAGE_WRITE;
7390                     /* fall through */
7391                 case 2:
7392                 case 6:
7393                     *prot |= PAGE_READ | PAGE_EXEC;
7394                     break;
7395                 default:
7396                     qemu_log_mask(LOG_GUEST_ERROR,
7397                                   "Bad value for AP bits in DRACR %"
7398                                   PRIx32 "\n", ap);
7399                 }
7400             } else { /* Priv. mode AP bits decoding */
7401                 switch (ap) {
7402                 case 0:
7403                     break; /* no access */
7404                 case 1:
7405                 case 2:
7406                 case 3:
7407                     *prot |= PAGE_WRITE;
7408                     /* fall through */
7409                 case 5:
7410                 case 6:
7411                     *prot |= PAGE_READ | PAGE_EXEC;
7412                     break;
7413                 default:
7414                     qemu_log_mask(LOG_GUEST_ERROR,
7415                                   "Bad value for AP bits in DRACR %"
7416                                   PRIx32 "\n", ap);
7417                 }
7418             }
7419
7420             /* execute never */
7421             if (env->pmsav7.dracr[n] & (1 << 12)) {
7422                 *prot &= ~PAGE_EXEC;
7423             }
7424         }
7425     }
7426
7427     *fsr = 0x00d; /* Permission fault */
7428     return !(*prot & (1 << access_type));
7429 }
7430
7431 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
7432                                  int access_type, ARMMMUIdx mmu_idx,
7433                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7434 {
7435     int n;
7436     uint32_t mask;
7437     uint32_t base;
7438     bool is_user = regime_is_user(env, mmu_idx);
7439
7440     *phys_ptr = address;
7441     for (n = 7; n >= 0; n--) {
7442         base = env->cp15.c6_region[n];
7443         if ((base & 1) == 0) {
7444             continue;
7445         }
7446         mask = 1 << ((base >> 1) & 0x1f);
7447         /* Keep this shift separate from the above to avoid an
7448            (undefined) << 32.  */
7449         mask = (mask << 1) - 1;
7450         if (((base ^ address) & ~mask) == 0) {
7451             break;
7452         }
7453     }
7454     if (n < 0) {
7455         *fsr = 2;
7456         return true;
7457     }
7458
7459     if (access_type == 2) {
7460         mask = env->cp15.pmsav5_insn_ap;
7461     } else {
7462         mask = env->cp15.pmsav5_data_ap;
7463     }
7464     mask = (mask >> (n * 4)) & 0xf;
7465     switch (mask) {
7466     case 0:
7467         *fsr = 1;
7468         return true;
7469     case 1:
7470         if (is_user) {
7471             *fsr = 1;
7472             return true;
7473         }
7474         *prot = PAGE_READ | PAGE_WRITE;
7475         break;
7476     case 2:
7477         *prot = PAGE_READ;
7478         if (!is_user) {
7479             *prot |= PAGE_WRITE;
7480         }
7481         break;
7482     case 3:
7483         *prot = PAGE_READ | PAGE_WRITE;
7484         break;
7485     case 5:
7486         if (is_user) {
7487             *fsr = 1;
7488             return true;
7489         }
7490         *prot = PAGE_READ;
7491         break;
7492     case 6:
7493         *prot = PAGE_READ;
7494         break;
7495     default:
7496         /* Bad permission.  */
7497         *fsr = 1;
7498         return true;
7499     }
7500     *prot |= PAGE_EXEC;
7501     return false;
7502 }
7503
7504 /* get_phys_addr - get the physical address for this virtual address
7505  *
7506  * Find the physical address corresponding to the given virtual address,
7507  * by doing a translation table walk on MMU based systems or using the
7508  * MPU state on MPU based systems.
7509  *
7510  * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
7511  * prot and page_size may not be filled in, and the populated fsr value provides
7512  * information on why the translation aborted, in the format of a
7513  * DFSR/IFSR fault register, with the following caveats:
7514  *  * we honour the short vs long DFSR format differences.
7515  *  * the WnR bit is never set (the caller must do this).
7516  *  * for PSMAv5 based systems we don't bother to return a full FSR format
7517  *    value.
7518  *
7519  * @env: CPUARMState
7520  * @address: virtual address to get physical address for
7521  * @access_type: 0 for read, 1 for write, 2 for execute
7522  * @mmu_idx: MMU index indicating required translation regime
7523  * @phys_ptr: set to the physical address corresponding to the virtual address
7524  * @attrs: set to the memory transaction attributes to use
7525  * @prot: set to the permissions for the page containing phys_ptr
7526  * @page_size: set to the size of the page containing phys_ptr
7527  * @fsr: set to the DFSR/IFSR value on failure
7528  */
7529 static bool get_phys_addr(CPUARMState *env, target_ulong address,
7530                           int access_type, ARMMMUIdx mmu_idx,
7531                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
7532                           target_ulong *page_size, uint32_t *fsr,
7533                           ARMMMUFaultInfo *fi)
7534 {
7535     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
7536         /* Call ourselves recursively to do the stage 1 and then stage 2
7537          * translations.
7538          */
7539         if (arm_feature(env, ARM_FEATURE_EL2)) {
7540             hwaddr ipa;
7541             int s2_prot;
7542             int ret;
7543
7544             ret = get_phys_addr(env, address, access_type,
7545                                 mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs,
7546                                 prot, page_size, fsr, fi);
7547
7548             /* If S1 fails or S2 is disabled, return early.  */
7549             if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
7550                 *phys_ptr = ipa;
7551                 return ret;
7552             }
7553
7554             /* S1 is done. Now do S2 translation.  */
7555             ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS,
7556                                      phys_ptr, attrs, &s2_prot,
7557                                      page_size, fsr, fi);
7558             fi->s2addr = ipa;
7559             /* Combine the S1 and S2 perms.  */
7560             *prot &= s2_prot;
7561             return ret;
7562         } else {
7563             /*
7564              * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
7565              */
7566             mmu_idx += ARMMMUIdx_S1NSE0;
7567         }
7568     }
7569
7570     /* The page table entries may downgrade secure to non-secure, but
7571      * cannot upgrade an non-secure translation regime's attributes
7572      * to secure.
7573      */
7574     attrs->secure = regime_is_secure(env, mmu_idx);
7575     attrs->user = regime_is_user(env, mmu_idx);
7576
7577     /* Fast Context Switch Extension. This doesn't exist at all in v8.
7578      * In v7 and earlier it affects all stage 1 translations.
7579      */
7580     if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
7581         && !arm_feature(env, ARM_FEATURE_V8)) {
7582         if (regime_el(env, mmu_idx) == 3) {
7583             address += env->cp15.fcseidr_s;
7584         } else {
7585             address += env->cp15.fcseidr_ns;
7586         }
7587     }
7588
7589     /* pmsav7 has special handling for when MPU is disabled so call it before
7590      * the common MMU/MPU disabled check below.
7591      */
7592     if (arm_feature(env, ARM_FEATURE_MPU) &&
7593         arm_feature(env, ARM_FEATURE_V7)) {
7594         *page_size = TARGET_PAGE_SIZE;
7595         return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
7596                                     phys_ptr, prot, fsr);
7597     }
7598
7599     if (regime_translation_disabled(env, mmu_idx)) {
7600         /* MMU/MPU disabled.  */
7601         *phys_ptr = address;
7602         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7603         *page_size = TARGET_PAGE_SIZE;
7604         return 0;
7605     }
7606
7607     if (arm_feature(env, ARM_FEATURE_MPU)) {
7608         /* Pre-v7 MPU */
7609         *page_size = TARGET_PAGE_SIZE;
7610         return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
7611                                     phys_ptr, prot, fsr);
7612     }
7613
7614     if (regime_using_lpae_format(env, mmu_idx)) {
7615         return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
7616                                   attrs, prot, page_size, fsr, fi);
7617     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
7618         return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
7619                                 attrs, prot, page_size, fsr, fi);
7620     } else {
7621         return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
7622                                 prot, page_size, fsr, fi);
7623     }
7624 }
7625
7626 /* Walk the page table and (if the mapping exists) add the page
7627  * to the TLB. Return false on success, or true on failure. Populate
7628  * fsr with ARM DFSR/IFSR fault register format value on failure.
7629  */
7630 bool arm_tlb_fill(CPUState *cs, vaddr address,
7631                   int access_type, int mmu_idx, uint32_t *fsr,
7632                   ARMMMUFaultInfo *fi)
7633 {
7634     ARMCPU *cpu = ARM_CPU(cs);
7635     CPUARMState *env = &cpu->env;
7636     hwaddr phys_addr;
7637     target_ulong page_size;
7638     int prot;
7639     int ret;
7640     MemTxAttrs attrs = {};
7641
7642     ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
7643                         &attrs, &prot, &page_size, fsr, fi);
7644     if (!ret) {
7645         /* Map a single [sub]page.  */
7646         phys_addr &= TARGET_PAGE_MASK;
7647         address &= TARGET_PAGE_MASK;
7648         tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
7649                                 prot, mmu_idx, page_size);
7650         return 0;
7651     }
7652
7653     return ret;
7654 }
7655
7656 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
7657                                          MemTxAttrs *attrs)
7658 {
7659     ARMCPU *cpu = ARM_CPU(cs);
7660     CPUARMState *env = &cpu->env;
7661     hwaddr phys_addr;
7662     target_ulong page_size;
7663     int prot;
7664     bool ret;
7665     uint32_t fsr;
7666     ARMMMUFaultInfo fi = {};
7667
7668     *attrs = (MemTxAttrs) {};
7669
7670     ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr,
7671                         attrs, &prot, &page_size, &fsr, &fi);
7672
7673     if (ret) {
7674         return -1;
7675     }
7676     return phys_addr;
7677 }
7678
7679 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
7680 {
7681     if ((env->uncached_cpsr & CPSR_M) == mode) {
7682         env->regs[13] = val;
7683     } else {
7684         env->banked_r13[bank_number(mode)] = val;
7685     }
7686 }
7687
7688 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
7689 {
7690     if ((env->uncached_cpsr & CPSR_M) == mode) {
7691         return env->regs[13];
7692     } else {
7693         return env->banked_r13[bank_number(mode)];
7694     }
7695 }
7696
7697 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
7698 {
7699     ARMCPU *cpu = arm_env_get_cpu(env);
7700
7701     switch (reg) {
7702     case 0: /* APSR */
7703         return xpsr_read(env) & 0xf8000000;
7704     case 1: /* IAPSR */
7705         return xpsr_read(env) & 0xf80001ff;
7706     case 2: /* EAPSR */
7707         return xpsr_read(env) & 0xff00fc00;
7708     case 3: /* xPSR */
7709         return xpsr_read(env) & 0xff00fdff;
7710     case 5: /* IPSR */
7711         return xpsr_read(env) & 0x000001ff;
7712     case 6: /* EPSR */
7713         return xpsr_read(env) & 0x0700fc00;
7714     case 7: /* IEPSR */
7715         return xpsr_read(env) & 0x0700edff;
7716     case 8: /* MSP */
7717         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
7718     case 9: /* PSP */
7719         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
7720     case 16: /* PRIMASK */
7721         return (env->daif & PSTATE_I) != 0;
7722     case 17: /* BASEPRI */
7723     case 18: /* BASEPRI_MAX */
7724         return env->v7m.basepri;
7725     case 19: /* FAULTMASK */
7726         return (env->daif & PSTATE_F) != 0;
7727     case 20: /* CONTROL */
7728         return env->v7m.control;
7729     default:
7730         /* ??? For debugging only.  */
7731         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
7732         return 0;
7733     }
7734 }
7735
7736 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
7737 {
7738     ARMCPU *cpu = arm_env_get_cpu(env);
7739
7740     switch (reg) {
7741     case 0: /* APSR */
7742         xpsr_write(env, val, 0xf8000000);
7743         break;
7744     case 1: /* IAPSR */
7745         xpsr_write(env, val, 0xf8000000);
7746         break;
7747     case 2: /* EAPSR */
7748         xpsr_write(env, val, 0xfe00fc00);
7749         break;
7750     case 3: /* xPSR */
7751         xpsr_write(env, val, 0xfe00fc00);
7752         break;
7753     case 5: /* IPSR */
7754         /* IPSR bits are readonly.  */
7755         break;
7756     case 6: /* EPSR */
7757         xpsr_write(env, val, 0x0600fc00);
7758         break;
7759     case 7: /* IEPSR */
7760         xpsr_write(env, val, 0x0600fc00);
7761         break;
7762     case 8: /* MSP */
7763         if (env->v7m.current_sp)
7764             env->v7m.other_sp = val;
7765         else
7766             env->regs[13] = val;
7767         break;
7768     case 9: /* PSP */
7769         if (env->v7m.current_sp)
7770             env->regs[13] = val;
7771         else
7772             env->v7m.other_sp = val;
7773         break;
7774     case 16: /* PRIMASK */
7775         if (val & 1) {
7776             env->daif |= PSTATE_I;
7777         } else {
7778             env->daif &= ~PSTATE_I;
7779         }
7780         break;
7781     case 17: /* BASEPRI */
7782         env->v7m.basepri = val & 0xff;
7783         break;
7784     case 18: /* BASEPRI_MAX */
7785         val &= 0xff;
7786         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
7787             env->v7m.basepri = val;
7788         break;
7789     case 19: /* FAULTMASK */
7790         if (val & 1) {
7791             env->daif |= PSTATE_F;
7792         } else {
7793             env->daif &= ~PSTATE_F;
7794         }
7795         break;
7796     case 20: /* CONTROL */
7797         env->v7m.control = val & 3;
7798         switch_v7m_sp(env, (val & 2) != 0);
7799         break;
7800     default:
7801         /* ??? For debugging only.  */
7802         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
7803         return;
7804     }
7805 }
7806
7807 #endif
7808
7809 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
7810 {
7811     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
7812      * Note that we do not implement the (architecturally mandated)
7813      * alignment fault for attempts to use this on Device memory
7814      * (which matches the usual QEMU behaviour of not implementing either
7815      * alignment faults or any memory attribute handling).
7816      */
7817
7818     ARMCPU *cpu = arm_env_get_cpu(env);
7819     uint64_t blocklen = 4 << cpu->dcz_blocksize;
7820     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
7821
7822 #ifndef CONFIG_USER_ONLY
7823     {
7824         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
7825          * the block size so we might have to do more than one TLB lookup.
7826          * We know that in fact for any v8 CPU the page size is at least 4K
7827          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
7828          * 1K as an artefact of legacy v5 subpage support being present in the
7829          * same QEMU executable.
7830          */
7831         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
7832         void *hostaddr[maxidx];
7833         int try, i;
7834         unsigned mmu_idx = cpu_mmu_index(env, false);
7835         TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
7836
7837         for (try = 0; try < 2; try++) {
7838
7839             for (i = 0; i < maxidx; i++) {
7840                 hostaddr[i] = tlb_vaddr_to_host(env,
7841                                                 vaddr + TARGET_PAGE_SIZE * i,
7842                                                 1, mmu_idx);
7843                 if (!hostaddr[i]) {
7844                     break;
7845                 }
7846             }
7847             if (i == maxidx) {
7848                 /* If it's all in the TLB it's fair game for just writing to;
7849                  * we know we don't need to update dirty status, etc.
7850                  */
7851                 for (i = 0; i < maxidx - 1; i++) {
7852                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
7853                 }
7854                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
7855                 return;
7856             }
7857             /* OK, try a store and see if we can populate the tlb. This
7858              * might cause an exception if the memory isn't writable,
7859              * in which case we will longjmp out of here. We must for
7860              * this purpose use the actual register value passed to us
7861              * so that we get the fault address right.
7862              */
7863             helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA());
7864             /* Now we can populate the other TLB entries, if any */
7865             for (i = 0; i < maxidx; i++) {
7866                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
7867                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
7868                     helper_ret_stb_mmu(env, va, 0, oi, GETRA());
7869                 }
7870             }
7871         }
7872
7873         /* Slow path (probably attempt to do this to an I/O device or
7874          * similar, or clearing of a block of code we have translations
7875          * cached for). Just do a series of byte writes as the architecture
7876          * demands. It's not worth trying to use a cpu_physical_memory_map(),
7877          * memset(), unmap() sequence here because:
7878          *  + we'd need to account for the blocksize being larger than a page
7879          *  + the direct-RAM access case is almost always going to be dealt
7880          *    with in the fastpath code above, so there's no speed benefit
7881          *  + we would have to deal with the map returning NULL because the
7882          *    bounce buffer was in use
7883          */
7884         for (i = 0; i < blocklen; i++) {
7885             helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA());
7886         }
7887     }
7888 #else
7889     memset(g2h(vaddr), 0, blocklen);
7890 #endif
7891 }
7892
7893 /* Note that signed overflow is undefined in C.  The following routines are
7894    careful to use unsigned types where modulo arithmetic is required.
7895    Failure to do so _will_ break on newer gcc.  */
7896
7897 /* Signed saturating arithmetic.  */
7898
7899 /* Perform 16-bit signed saturating addition.  */
7900 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
7901 {
7902     uint16_t res;
7903
7904     res = a + b;
7905     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
7906         if (a & 0x8000)
7907             res = 0x8000;
7908         else
7909             res = 0x7fff;
7910     }
7911     return res;
7912 }
7913
7914 /* Perform 8-bit signed saturating addition.  */
7915 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
7916 {
7917     uint8_t res;
7918
7919     res = a + b;
7920     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
7921         if (a & 0x80)
7922             res = 0x80;
7923         else
7924             res = 0x7f;
7925     }
7926     return res;
7927 }
7928
7929 /* Perform 16-bit signed saturating subtraction.  */
7930 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
7931 {
7932     uint16_t res;
7933
7934     res = a - b;
7935     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
7936         if (a & 0x8000)
7937             res = 0x8000;
7938         else
7939             res = 0x7fff;
7940     }
7941     return res;
7942 }
7943
7944 /* Perform 8-bit signed saturating subtraction.  */
7945 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
7946 {
7947     uint8_t res;
7948
7949     res = a - b;
7950     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
7951         if (a & 0x80)
7952             res = 0x80;
7953         else
7954             res = 0x7f;
7955     }
7956     return res;
7957 }
7958
7959 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
7960 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
7961 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
7962 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
7963 #define PFX q
7964
7965 #include "op_addsub.h"
7966
7967 /* Unsigned saturating arithmetic.  */
7968 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
7969 {
7970     uint16_t res;
7971     res = a + b;
7972     if (res < a)
7973         res = 0xffff;
7974     return res;
7975 }
7976
7977 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
7978 {
7979     if (a > b)
7980         return a - b;
7981     else
7982         return 0;
7983 }
7984
7985 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
7986 {
7987     uint8_t res;
7988     res = a + b;
7989     if (res < a)
7990         res = 0xff;
7991     return res;
7992 }
7993
7994 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
7995 {
7996     if (a > b)
7997         return a - b;
7998     else
7999         return 0;
8000 }
8001
8002 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
8003 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
8004 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
8005 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
8006 #define PFX uq
8007
8008 #include "op_addsub.h"
8009
8010 /* Signed modulo arithmetic.  */
8011 #define SARITH16(a, b, n, op) do { \
8012     int32_t sum; \
8013     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
8014     RESULT(sum, n, 16); \
8015     if (sum >= 0) \
8016         ge |= 3 << (n * 2); \
8017     } while(0)
8018
8019 #define SARITH8(a, b, n, op) do { \
8020     int32_t sum; \
8021     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
8022     RESULT(sum, n, 8); \
8023     if (sum >= 0) \
8024         ge |= 1 << n; \
8025     } while(0)
8026
8027
8028 #define ADD16(a, b, n) SARITH16(a, b, n, +)
8029 #define SUB16(a, b, n) SARITH16(a, b, n, -)
8030 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
8031 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
8032 #define PFX s
8033 #define ARITH_GE
8034
8035 #include "op_addsub.h"
8036
8037 /* Unsigned modulo arithmetic.  */
8038 #define ADD16(a, b, n) do { \
8039     uint32_t sum; \
8040     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
8041     RESULT(sum, n, 16); \
8042     if ((sum >> 16) == 1) \
8043         ge |= 3 << (n * 2); \
8044     } while(0)
8045
8046 #define ADD8(a, b, n) do { \
8047     uint32_t sum; \
8048     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
8049     RESULT(sum, n, 8); \
8050     if ((sum >> 8) == 1) \
8051         ge |= 1 << n; \
8052     } while(0)
8053
8054 #define SUB16(a, b, n) do { \
8055     uint32_t sum; \
8056     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
8057     RESULT(sum, n, 16); \
8058     if ((sum >> 16) == 0) \
8059         ge |= 3 << (n * 2); \
8060     } while(0)
8061
8062 #define SUB8(a, b, n) do { \
8063     uint32_t sum; \
8064     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
8065     RESULT(sum, n, 8); \
8066     if ((sum >> 8) == 0) \
8067         ge |= 1 << n; \
8068     } while(0)
8069
8070 #define PFX u
8071 #define ARITH_GE
8072
8073 #include "op_addsub.h"
8074
8075 /* Halved signed arithmetic.  */
8076 #define ADD16(a, b, n) \
8077   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
8078 #define SUB16(a, b, n) \
8079   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
8080 #define ADD8(a, b, n) \
8081   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
8082 #define SUB8(a, b, n) \
8083   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
8084 #define PFX sh
8085
8086 #include "op_addsub.h"
8087
8088 /* Halved unsigned arithmetic.  */
8089 #define ADD16(a, b, n) \
8090   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
8091 #define SUB16(a, b, n) \
8092   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
8093 #define ADD8(a, b, n) \
8094   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
8095 #define SUB8(a, b, n) \
8096   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
8097 #define PFX uh
8098
8099 #include "op_addsub.h"
8100
8101 static inline uint8_t do_usad(uint8_t a, uint8_t b)
8102 {
8103     if (a > b)
8104         return a - b;
8105     else
8106         return b - a;
8107 }
8108
8109 /* Unsigned sum of absolute byte differences.  */
8110 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
8111 {
8112     uint32_t sum;
8113     sum = do_usad(a, b);
8114     sum += do_usad(a >> 8, b >> 8);
8115     sum += do_usad(a >> 16, b >>16);
8116     sum += do_usad(a >> 24, b >> 24);
8117     return sum;
8118 }
8119
8120 /* For ARMv6 SEL instruction.  */
8121 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
8122 {
8123     uint32_t mask;
8124
8125     mask = 0;
8126     if (flags & 1)
8127         mask |= 0xff;
8128     if (flags & 2)
8129         mask |= 0xff00;
8130     if (flags & 4)
8131         mask |= 0xff0000;
8132     if (flags & 8)
8133         mask |= 0xff000000;
8134     return (a & mask) | (b & ~mask);
8135 }
8136
8137 /* VFP support.  We follow the convention used for VFP instructions:
8138    Single precision routines have a "s" suffix, double precision a
8139    "d" suffix.  */
8140
8141 /* Convert host exception flags to vfp form.  */
8142 static inline int vfp_exceptbits_from_host(int host_bits)
8143 {
8144     int target_bits = 0;
8145
8146     if (host_bits & float_flag_invalid)
8147         target_bits |= 1;
8148     if (host_bits & float_flag_divbyzero)
8149         target_bits |= 2;
8150     if (host_bits & float_flag_overflow)
8151         target_bits |= 4;
8152     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
8153         target_bits |= 8;
8154     if (host_bits & float_flag_inexact)
8155         target_bits |= 0x10;
8156     if (host_bits & float_flag_input_denormal)
8157         target_bits |= 0x80;
8158     return target_bits;
8159 }
8160
8161 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
8162 {
8163     int i;
8164     uint32_t fpscr;
8165
8166     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
8167             | (env->vfp.vec_len << 16)
8168             | (env->vfp.vec_stride << 20);
8169     i = get_float_exception_flags(&env->vfp.fp_status);
8170     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
8171     fpscr |= vfp_exceptbits_from_host(i);
8172     return fpscr;
8173 }
8174
8175 uint32_t vfp_get_fpscr(CPUARMState *env)
8176 {
8177     return HELPER(vfp_get_fpscr)(env);
8178 }
8179
8180 /* Convert vfp exception flags to target form.  */
8181 static inline int vfp_exceptbits_to_host(int target_bits)
8182 {
8183     int host_bits = 0;
8184
8185     if (target_bits & 1)
8186         host_bits |= float_flag_invalid;
8187     if (target_bits & 2)
8188         host_bits |= float_flag_divbyzero;
8189     if (target_bits & 4)
8190         host_bits |= float_flag_overflow;
8191     if (target_bits & 8)
8192         host_bits |= float_flag_underflow;
8193     if (target_bits & 0x10)
8194         host_bits |= float_flag_inexact;
8195     if (target_bits & 0x80)
8196         host_bits |= float_flag_input_denormal;
8197     return host_bits;
8198 }
8199
8200 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
8201 {
8202     int i;
8203     uint32_t changed;
8204
8205     changed = env->vfp.xregs[ARM_VFP_FPSCR];
8206     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
8207     env->vfp.vec_len = (val >> 16) & 7;
8208     env->vfp.vec_stride = (val >> 20) & 3;
8209
8210     changed ^= val;
8211     if (changed & (3 << 22)) {
8212         i = (val >> 22) & 3;
8213         switch (i) {
8214         case FPROUNDING_TIEEVEN:
8215             i = float_round_nearest_even;
8216             break;
8217         case FPROUNDING_POSINF:
8218             i = float_round_up;
8219             break;
8220         case FPROUNDING_NEGINF:
8221             i = float_round_down;
8222             break;
8223         case FPROUNDING_ZERO:
8224             i = float_round_to_zero;
8225             break;
8226         }
8227         set_float_rounding_mode(i, &env->vfp.fp_status);
8228     }
8229     if (changed & (1 << 24)) {
8230         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8231         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8232     }
8233     if (changed & (1 << 25))
8234         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
8235
8236     i = vfp_exceptbits_to_host(val);
8237     set_float_exception_flags(i, &env->vfp.fp_status);
8238     set_float_exception_flags(0, &env->vfp.standard_fp_status);
8239 }
8240
8241 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
8242 {
8243     HELPER(vfp_set_fpscr)(env, val);
8244 }
8245
8246 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
8247
8248 #define VFP_BINOP(name) \
8249 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
8250 { \
8251     float_status *fpst = fpstp; \
8252     return float32_ ## name(a, b, fpst); \
8253 } \
8254 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
8255 { \
8256     float_status *fpst = fpstp; \
8257     return float64_ ## name(a, b, fpst); \
8258 }
8259 VFP_BINOP(add)
8260 VFP_BINOP(sub)
8261 VFP_BINOP(mul)
8262 VFP_BINOP(div)
8263 VFP_BINOP(min)
8264 VFP_BINOP(max)
8265 VFP_BINOP(minnum)
8266 VFP_BINOP(maxnum)
8267 #undef VFP_BINOP
8268
8269 float32 VFP_HELPER(neg, s)(float32 a)
8270 {
8271     return float32_chs(a);
8272 }
8273
8274 float64 VFP_HELPER(neg, d)(float64 a)
8275 {
8276     return float64_chs(a);
8277 }
8278
8279 float32 VFP_HELPER(abs, s)(float32 a)
8280 {
8281     return float32_abs(a);
8282 }
8283
8284 float64 VFP_HELPER(abs, d)(float64 a)
8285 {
8286     return float64_abs(a);
8287 }
8288
8289 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
8290 {
8291     return float32_sqrt(a, &env->vfp.fp_status);
8292 }
8293
8294 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
8295 {
8296     return float64_sqrt(a, &env->vfp.fp_status);
8297 }
8298
8299 /* XXX: check quiet/signaling case */
8300 #define DO_VFP_cmp(p, type) \
8301 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
8302 { \
8303     uint32_t flags; \
8304     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
8305     case 0: flags = 0x6; break; \
8306     case -1: flags = 0x8; break; \
8307     case 1: flags = 0x2; break; \
8308     default: case 2: flags = 0x3; break; \
8309     } \
8310     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8311         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8312 } \
8313 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
8314 { \
8315     uint32_t flags; \
8316     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
8317     case 0: flags = 0x6; break; \
8318     case -1: flags = 0x8; break; \
8319     case 1: flags = 0x2; break; \
8320     default: case 2: flags = 0x3; break; \
8321     } \
8322     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8323         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8324 }
8325 DO_VFP_cmp(s, float32)
8326 DO_VFP_cmp(d, float64)
8327 #undef DO_VFP_cmp
8328
8329 /* Integer to float and float to integer conversions */
8330
8331 #define CONV_ITOF(name, fsz, sign) \
8332     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
8333 { \
8334     float_status *fpst = fpstp; \
8335     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
8336 }
8337
8338 #define CONV_FTOI(name, fsz, sign, round) \
8339 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
8340 { \
8341     float_status *fpst = fpstp; \
8342     if (float##fsz##_is_any_nan(x)) { \
8343         float_raise(float_flag_invalid, fpst); \
8344         return 0; \
8345     } \
8346     return float##fsz##_to_##sign##int32##round(x, fpst); \
8347 }
8348
8349 #define FLOAT_CONVS(name, p, fsz, sign) \
8350 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
8351 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
8352 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
8353
8354 FLOAT_CONVS(si, s, 32, )
8355 FLOAT_CONVS(si, d, 64, )
8356 FLOAT_CONVS(ui, s, 32, u)
8357 FLOAT_CONVS(ui, d, 64, u)
8358
8359 #undef CONV_ITOF
8360 #undef CONV_FTOI
8361 #undef FLOAT_CONVS
8362
8363 /* floating point conversion */
8364 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
8365 {
8366     float64 r = float32_to_float64(x, &env->vfp.fp_status);
8367     /* ARM requires that S<->D conversion of any kind of NaN generates
8368      * a quiet NaN by forcing the most significant frac bit to 1.
8369      */
8370     return float64_maybe_silence_nan(r);
8371 }
8372
8373 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
8374 {
8375     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
8376     /* ARM requires that S<->D conversion of any kind of NaN generates
8377      * a quiet NaN by forcing the most significant frac bit to 1.
8378      */
8379     return float32_maybe_silence_nan(r);
8380 }
8381
8382 /* VFP3 fixed point conversion.  */
8383 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8384 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
8385                                      void *fpstp) \
8386 { \
8387     float_status *fpst = fpstp; \
8388     float##fsz tmp; \
8389     tmp = itype##_to_##float##fsz(x, fpst); \
8390     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
8391 }
8392
8393 /* Notice that we want only input-denormal exception flags from the
8394  * scalbn operation: the other possible flags (overflow+inexact if
8395  * we overflow to infinity, output-denormal) aren't correct for the
8396  * complete scale-and-convert operation.
8397  */
8398 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
8399 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
8400                                              uint32_t shift, \
8401                                              void *fpstp) \
8402 { \
8403     float_status *fpst = fpstp; \
8404     int old_exc_flags = get_float_exception_flags(fpst); \
8405     float##fsz tmp; \
8406     if (float##fsz##_is_any_nan(x)) { \
8407         float_raise(float_flag_invalid, fpst); \
8408         return 0; \
8409     } \
8410     tmp = float##fsz##_scalbn(x, shift, fpst); \
8411     old_exc_flags |= get_float_exception_flags(fpst) \
8412         & float_flag_input_denormal; \
8413     set_float_exception_flags(old_exc_flags, fpst); \
8414     return float##fsz##_to_##itype##round(tmp, fpst); \
8415 }
8416
8417 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
8418 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8419 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
8420 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8421
8422 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
8423 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8424 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8425
8426 VFP_CONV_FIX(sh, d, 64, 64, int16)
8427 VFP_CONV_FIX(sl, d, 64, 64, int32)
8428 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
8429 VFP_CONV_FIX(uh, d, 64, 64, uint16)
8430 VFP_CONV_FIX(ul, d, 64, 64, uint32)
8431 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
8432 VFP_CONV_FIX(sh, s, 32, 32, int16)
8433 VFP_CONV_FIX(sl, s, 32, 32, int32)
8434 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
8435 VFP_CONV_FIX(uh, s, 32, 32, uint16)
8436 VFP_CONV_FIX(ul, s, 32, 32, uint32)
8437 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
8438 #undef VFP_CONV_FIX
8439 #undef VFP_CONV_FIX_FLOAT
8440 #undef VFP_CONV_FLOAT_FIX_ROUND
8441
8442 /* Set the current fp rounding mode and return the old one.
8443  * The argument is a softfloat float_round_ value.
8444  */
8445 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
8446 {
8447     float_status *fp_status = &env->vfp.fp_status;
8448
8449     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8450     set_float_rounding_mode(rmode, fp_status);
8451
8452     return prev_rmode;
8453 }
8454
8455 /* Set the current fp rounding mode in the standard fp status and return
8456  * the old one. This is for NEON instructions that need to change the
8457  * rounding mode but wish to use the standard FPSCR values for everything
8458  * else. Always set the rounding mode back to the correct value after
8459  * modifying it.
8460  * The argument is a softfloat float_round_ value.
8461  */
8462 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
8463 {
8464     float_status *fp_status = &env->vfp.standard_fp_status;
8465
8466     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8467     set_float_rounding_mode(rmode, fp_status);
8468
8469     return prev_rmode;
8470 }
8471
8472 /* Half precision conversions.  */
8473 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
8474 {
8475     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8476     float32 r = float16_to_float32(make_float16(a), ieee, s);
8477     if (ieee) {
8478         return float32_maybe_silence_nan(r);
8479     }
8480     return r;
8481 }
8482
8483 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
8484 {
8485     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8486     float16 r = float32_to_float16(a, ieee, s);
8487     if (ieee) {
8488         r = float16_maybe_silence_nan(r);
8489     }
8490     return float16_val(r);
8491 }
8492
8493 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8494 {
8495     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
8496 }
8497
8498 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8499 {
8500     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
8501 }
8502
8503 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8504 {
8505     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
8506 }
8507
8508 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8509 {
8510     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
8511 }
8512
8513 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
8514 {
8515     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8516     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
8517     if (ieee) {
8518         return float64_maybe_silence_nan(r);
8519     }
8520     return r;
8521 }
8522
8523 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
8524 {
8525     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8526     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
8527     if (ieee) {
8528         r = float16_maybe_silence_nan(r);
8529     }
8530     return float16_val(r);
8531 }
8532
8533 #define float32_two make_float32(0x40000000)
8534 #define float32_three make_float32(0x40400000)
8535 #define float32_one_point_five make_float32(0x3fc00000)
8536
8537 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
8538 {
8539     float_status *s = &env->vfp.standard_fp_status;
8540     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8541         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8542         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8543             float_raise(float_flag_input_denormal, s);
8544         }
8545         return float32_two;
8546     }
8547     return float32_sub(float32_two, float32_mul(a, b, s), s);
8548 }
8549
8550 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
8551 {
8552     float_status *s = &env->vfp.standard_fp_status;
8553     float32 product;
8554     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8555         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8556         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8557             float_raise(float_flag_input_denormal, s);
8558         }
8559         return float32_one_point_five;
8560     }
8561     product = float32_mul(a, b, s);
8562     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
8563 }
8564
8565 /* NEON helpers.  */
8566
8567 /* Constants 256 and 512 are used in some helpers; we avoid relying on
8568  * int->float conversions at run-time.  */
8569 #define float64_256 make_float64(0x4070000000000000LL)
8570 #define float64_512 make_float64(0x4080000000000000LL)
8571 #define float32_maxnorm make_float32(0x7f7fffff)
8572 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
8573
8574 /* Reciprocal functions
8575  *
8576  * The algorithm that must be used to calculate the estimate
8577  * is specified by the ARM ARM, see FPRecipEstimate()
8578  */
8579
8580 static float64 recip_estimate(float64 a, float_status *real_fp_status)
8581 {
8582     /* These calculations mustn't set any fp exception flags,
8583      * so we use a local copy of the fp_status.
8584      */
8585     float_status dummy_status = *real_fp_status;
8586     float_status *s = &dummy_status;
8587     /* q = (int)(a * 512.0) */
8588     float64 q = float64_mul(float64_512, a, s);
8589     int64_t q_int = float64_to_int64_round_to_zero(q, s);
8590
8591     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
8592     q = int64_to_float64(q_int, s);
8593     q = float64_add(q, float64_half, s);
8594     q = float64_div(q, float64_512, s);
8595     q = float64_div(float64_one, q, s);
8596
8597     /* s = (int)(256.0 * r + 0.5) */
8598     q = float64_mul(q, float64_256, s);
8599     q = float64_add(q, float64_half, s);
8600     q_int = float64_to_int64_round_to_zero(q, s);
8601
8602     /* return (double)s / 256.0 */
8603     return float64_div(int64_to_float64(q_int, s), float64_256, s);
8604 }
8605
8606 /* Common wrapper to call recip_estimate */
8607 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
8608 {
8609     uint64_t val64 = float64_val(num);
8610     uint64_t frac = extract64(val64, 0, 52);
8611     int64_t exp = extract64(val64, 52, 11);
8612     uint64_t sbit;
8613     float64 scaled, estimate;
8614
8615     /* Generate the scaled number for the estimate function */
8616     if (exp == 0) {
8617         if (extract64(frac, 51, 1) == 0) {
8618             exp = -1;
8619             frac = extract64(frac, 0, 50) << 2;
8620         } else {
8621             frac = extract64(frac, 0, 51) << 1;
8622         }
8623     }
8624
8625     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
8626     scaled = make_float64((0x3feULL << 52)
8627                           | extract64(frac, 44, 8) << 44);
8628
8629     estimate = recip_estimate(scaled, fpst);
8630
8631     /* Build new result */
8632     val64 = float64_val(estimate);
8633     sbit = 0x8000000000000000ULL & val64;
8634     exp = off - exp;
8635     frac = extract64(val64, 0, 52);
8636
8637     if (exp == 0) {
8638         frac = 1ULL << 51 | extract64(frac, 1, 51);
8639     } else if (exp == -1) {
8640         frac = 1ULL << 50 | extract64(frac, 2, 50);
8641         exp = 0;
8642     }
8643
8644     return make_float64(sbit | (exp << 52) | frac);
8645 }
8646
8647 static bool round_to_inf(float_status *fpst, bool sign_bit)
8648 {
8649     switch (fpst->float_rounding_mode) {
8650     case float_round_nearest_even: /* Round to Nearest */
8651         return true;
8652     case float_round_up: /* Round to +Inf */
8653         return !sign_bit;
8654     case float_round_down: /* Round to -Inf */
8655         return sign_bit;
8656     case float_round_to_zero: /* Round to Zero */
8657         return false;
8658     }
8659
8660     g_assert_not_reached();
8661 }
8662
8663 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
8664 {
8665     float_status *fpst = fpstp;
8666     float32 f32 = float32_squash_input_denormal(input, fpst);
8667     uint32_t f32_val = float32_val(f32);
8668     uint32_t f32_sbit = 0x80000000ULL & f32_val;
8669     int32_t f32_exp = extract32(f32_val, 23, 8);
8670     uint32_t f32_frac = extract32(f32_val, 0, 23);
8671     float64 f64, r64;
8672     uint64_t r64_val;
8673     int64_t r64_exp;
8674     uint64_t r64_frac;
8675
8676     if (float32_is_any_nan(f32)) {
8677         float32 nan = f32;
8678         if (float32_is_signaling_nan(f32)) {
8679             float_raise(float_flag_invalid, fpst);
8680             nan = float32_maybe_silence_nan(f32);
8681         }
8682         if (fpst->default_nan_mode) {
8683             nan =  float32_default_nan;
8684         }
8685         return nan;
8686     } else if (float32_is_infinity(f32)) {
8687         return float32_set_sign(float32_zero, float32_is_neg(f32));
8688     } else if (float32_is_zero(f32)) {
8689         float_raise(float_flag_divbyzero, fpst);
8690         return float32_set_sign(float32_infinity, float32_is_neg(f32));
8691     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
8692         /* Abs(value) < 2.0^-128 */
8693         float_raise(float_flag_overflow | float_flag_inexact, fpst);
8694         if (round_to_inf(fpst, f32_sbit)) {
8695             return float32_set_sign(float32_infinity, float32_is_neg(f32));
8696         } else {
8697             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
8698         }
8699     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
8700         float_raise(float_flag_underflow, fpst);
8701         return float32_set_sign(float32_zero, float32_is_neg(f32));
8702     }
8703
8704
8705     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
8706     r64 = call_recip_estimate(f64, 253, fpst);
8707     r64_val = float64_val(r64);
8708     r64_exp = extract64(r64_val, 52, 11);
8709     r64_frac = extract64(r64_val, 0, 52);
8710
8711     /* result = sign : result_exp<7:0> : fraction<51:29>; */
8712     return make_float32(f32_sbit |
8713                         (r64_exp & 0xff) << 23 |
8714                         extract64(r64_frac, 29, 24));
8715 }
8716
8717 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
8718 {
8719     float_status *fpst = fpstp;
8720     float64 f64 = float64_squash_input_denormal(input, fpst);
8721     uint64_t f64_val = float64_val(f64);
8722     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
8723     int64_t f64_exp = extract64(f64_val, 52, 11);
8724     float64 r64;
8725     uint64_t r64_val;
8726     int64_t r64_exp;
8727     uint64_t r64_frac;
8728
8729     /* Deal with any special cases */
8730     if (float64_is_any_nan(f64)) {
8731         float64 nan = f64;
8732         if (float64_is_signaling_nan(f64)) {
8733             float_raise(float_flag_invalid, fpst);
8734             nan = float64_maybe_silence_nan(f64);
8735         }
8736         if (fpst->default_nan_mode) {
8737             nan =  float64_default_nan;
8738         }
8739         return nan;
8740     } else if (float64_is_infinity(f64)) {
8741         return float64_set_sign(float64_zero, float64_is_neg(f64));
8742     } else if (float64_is_zero(f64)) {
8743         float_raise(float_flag_divbyzero, fpst);
8744         return float64_set_sign(float64_infinity, float64_is_neg(f64));
8745     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
8746         /* Abs(value) < 2.0^-1024 */
8747         float_raise(float_flag_overflow | float_flag_inexact, fpst);
8748         if (round_to_inf(fpst, f64_sbit)) {
8749             return float64_set_sign(float64_infinity, float64_is_neg(f64));
8750         } else {
8751             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
8752         }
8753     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
8754         float_raise(float_flag_underflow, fpst);
8755         return float64_set_sign(float64_zero, float64_is_neg(f64));
8756     }
8757
8758     r64 = call_recip_estimate(f64, 2045, fpst);
8759     r64_val = float64_val(r64);
8760     r64_exp = extract64(r64_val, 52, 11);
8761     r64_frac = extract64(r64_val, 0, 52);
8762
8763     /* result = sign : result_exp<10:0> : fraction<51:0> */
8764     return make_float64(f64_sbit |
8765                         ((r64_exp & 0x7ff) << 52) |
8766                         r64_frac);
8767 }
8768
8769 /* The algorithm that must be used to calculate the estimate
8770  * is specified by the ARM ARM.
8771  */
8772 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
8773 {
8774     /* These calculations mustn't set any fp exception flags,
8775      * so we use a local copy of the fp_status.
8776      */
8777     float_status dummy_status = *real_fp_status;
8778     float_status *s = &dummy_status;
8779     float64 q;
8780     int64_t q_int;
8781
8782     if (float64_lt(a, float64_half, s)) {
8783         /* range 0.25 <= a < 0.5 */
8784
8785         /* a in units of 1/512 rounded down */
8786         /* q0 = (int)(a * 512.0);  */
8787         q = float64_mul(float64_512, a, s);
8788         q_int = float64_to_int64_round_to_zero(q, s);
8789
8790         /* reciprocal root r */
8791         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
8792         q = int64_to_float64(q_int, s);
8793         q = float64_add(q, float64_half, s);
8794         q = float64_div(q, float64_512, s);
8795         q = float64_sqrt(q, s);
8796         q = float64_div(float64_one, q, s);
8797     } else {
8798         /* range 0.5 <= a < 1.0 */
8799
8800         /* a in units of 1/256 rounded down */
8801         /* q1 = (int)(a * 256.0); */
8802         q = float64_mul(float64_256, a, s);
8803         int64_t q_int = float64_to_int64_round_to_zero(q, s);
8804
8805         /* reciprocal root r */
8806         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
8807         q = int64_to_float64(q_int, s);
8808         q = float64_add(q, float64_half, s);
8809         q = float64_div(q, float64_256, s);
8810         q = float64_sqrt(q, s);
8811         q = float64_div(float64_one, q, s);
8812     }
8813     /* r in units of 1/256 rounded to nearest */
8814     /* s = (int)(256.0 * r + 0.5); */
8815
8816     q = float64_mul(q, float64_256,s );
8817     q = float64_add(q, float64_half, s);
8818     q_int = float64_to_int64_round_to_zero(q, s);
8819
8820     /* return (double)s / 256.0;*/
8821     return float64_div(int64_to_float64(q_int, s), float64_256, s);
8822 }
8823
8824 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
8825 {
8826     float_status *s = fpstp;
8827     float32 f32 = float32_squash_input_denormal(input, s);
8828     uint32_t val = float32_val(f32);
8829     uint32_t f32_sbit = 0x80000000 & val;
8830     int32_t f32_exp = extract32(val, 23, 8);
8831     uint32_t f32_frac = extract32(val, 0, 23);
8832     uint64_t f64_frac;
8833     uint64_t val64;
8834     int result_exp;
8835     float64 f64;
8836
8837     if (float32_is_any_nan(f32)) {
8838         float32 nan = f32;
8839         if (float32_is_signaling_nan(f32)) {
8840             float_raise(float_flag_invalid, s);
8841             nan = float32_maybe_silence_nan(f32);
8842         }
8843         if (s->default_nan_mode) {
8844             nan =  float32_default_nan;
8845         }
8846         return nan;
8847     } else if (float32_is_zero(f32)) {
8848         float_raise(float_flag_divbyzero, s);
8849         return float32_set_sign(float32_infinity, float32_is_neg(f32));
8850     } else if (float32_is_neg(f32)) {
8851         float_raise(float_flag_invalid, s);
8852         return float32_default_nan;
8853     } else if (float32_is_infinity(f32)) {
8854         return float32_zero;
8855     }
8856
8857     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8858      * preserving the parity of the exponent.  */
8859
8860     f64_frac = ((uint64_t) f32_frac) << 29;
8861     if (f32_exp == 0) {
8862         while (extract64(f64_frac, 51, 1) == 0) {
8863             f64_frac = f64_frac << 1;
8864             f32_exp = f32_exp-1;
8865         }
8866         f64_frac = extract64(f64_frac, 0, 51) << 1;
8867     }
8868
8869     if (extract64(f32_exp, 0, 1) == 0) {
8870         f64 = make_float64(((uint64_t) f32_sbit) << 32
8871                            | (0x3feULL << 52)
8872                            | f64_frac);
8873     } else {
8874         f64 = make_float64(((uint64_t) f32_sbit) << 32
8875                            | (0x3fdULL << 52)
8876                            | f64_frac);
8877     }
8878
8879     result_exp = (380 - f32_exp) / 2;
8880
8881     f64 = recip_sqrt_estimate(f64, s);
8882
8883     val64 = float64_val(f64);
8884
8885     val = ((result_exp & 0xff) << 23)
8886         | ((val64 >> 29)  & 0x7fffff);
8887     return make_float32(val);
8888 }
8889
8890 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
8891 {
8892     float_status *s = fpstp;
8893     float64 f64 = float64_squash_input_denormal(input, s);
8894     uint64_t val = float64_val(f64);
8895     uint64_t f64_sbit = 0x8000000000000000ULL & val;
8896     int64_t f64_exp = extract64(val, 52, 11);
8897     uint64_t f64_frac = extract64(val, 0, 52);
8898     int64_t result_exp;
8899     uint64_t result_frac;
8900
8901     if (float64_is_any_nan(f64)) {
8902         float64 nan = f64;
8903         if (float64_is_signaling_nan(f64)) {
8904             float_raise(float_flag_invalid, s);
8905             nan = float64_maybe_silence_nan(f64);
8906         }
8907         if (s->default_nan_mode) {
8908             nan =  float64_default_nan;
8909         }
8910         return nan;
8911     } else if (float64_is_zero(f64)) {
8912         float_raise(float_flag_divbyzero, s);
8913         return float64_set_sign(float64_infinity, float64_is_neg(f64));
8914     } else if (float64_is_neg(f64)) {
8915         float_raise(float_flag_invalid, s);
8916         return float64_default_nan;
8917     } else if (float64_is_infinity(f64)) {
8918         return float64_zero;
8919     }
8920
8921     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8922      * preserving the parity of the exponent.  */
8923
8924     if (f64_exp == 0) {
8925         while (extract64(f64_frac, 51, 1) == 0) {
8926             f64_frac = f64_frac << 1;
8927             f64_exp = f64_exp - 1;
8928         }
8929         f64_frac = extract64(f64_frac, 0, 51) << 1;
8930     }
8931
8932     if (extract64(f64_exp, 0, 1) == 0) {
8933         f64 = make_float64(f64_sbit
8934                            | (0x3feULL << 52)
8935                            | f64_frac);
8936     } else {
8937         f64 = make_float64(f64_sbit
8938                            | (0x3fdULL << 52)
8939                            | f64_frac);
8940     }
8941
8942     result_exp = (3068 - f64_exp) / 2;
8943
8944     f64 = recip_sqrt_estimate(f64, s);
8945
8946     result_frac = extract64(float64_val(f64), 0, 52);
8947
8948     return make_float64(f64_sbit |
8949                         ((result_exp & 0x7ff) << 52) |
8950                         result_frac);
8951 }
8952
8953 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
8954 {
8955     float_status *s = fpstp;
8956     float64 f64;
8957
8958     if ((a & 0x80000000) == 0) {
8959         return 0xffffffff;
8960     }
8961
8962     f64 = make_float64((0x3feULL << 52)
8963                        | ((int64_t)(a & 0x7fffffff) << 21));
8964
8965     f64 = recip_estimate(f64, s);
8966
8967     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
8968 }
8969
8970 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
8971 {
8972     float_status *fpst = fpstp;
8973     float64 f64;
8974
8975     if ((a & 0xc0000000) == 0) {
8976         return 0xffffffff;
8977     }
8978
8979     if (a & 0x80000000) {
8980         f64 = make_float64((0x3feULL << 52)
8981                            | ((uint64_t)(a & 0x7fffffff) << 21));
8982     } else { /* bits 31-30 == '01' */
8983         f64 = make_float64((0x3fdULL << 52)
8984                            | ((uint64_t)(a & 0x3fffffff) << 22));
8985     }
8986
8987     f64 = recip_sqrt_estimate(f64, fpst);
8988
8989     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
8990 }
8991
8992 /* VFPv4 fused multiply-accumulate */
8993 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
8994 {
8995     float_status *fpst = fpstp;
8996     return float32_muladd(a, b, c, 0, fpst);
8997 }
8998
8999 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
9000 {
9001     float_status *fpst = fpstp;
9002     return float64_muladd(a, b, c, 0, fpst);
9003 }
9004
9005 /* ARMv8 round to integral */
9006 float32 HELPER(rints_exact)(float32 x, void *fp_status)
9007 {
9008     return float32_round_to_int(x, fp_status);
9009 }
9010
9011 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
9012 {
9013     return float64_round_to_int(x, fp_status);
9014 }
9015
9016 float32 HELPER(rints)(float32 x, void *fp_status)
9017 {
9018     int old_flags = get_float_exception_flags(fp_status), new_flags;
9019     float32 ret;
9020
9021     ret = float32_round_to_int(x, fp_status);
9022
9023     /* Suppress any inexact exceptions the conversion produced */
9024     if (!(old_flags & float_flag_inexact)) {
9025         new_flags = get_float_exception_flags(fp_status);
9026         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
9027     }
9028
9029     return ret;
9030 }
9031
9032 float64 HELPER(rintd)(float64 x, void *fp_status)
9033 {
9034     int old_flags = get_float_exception_flags(fp_status), new_flags;
9035     float64 ret;
9036
9037     ret = float64_round_to_int(x, fp_status);
9038
9039     new_flags = get_float_exception_flags(fp_status);
9040
9041     /* Suppress any inexact exceptions the conversion produced */
9042     if (!(old_flags & float_flag_inexact)) {
9043         new_flags = get_float_exception_flags(fp_status);
9044         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
9045     }
9046
9047     return ret;
9048 }
9049
9050 /* Convert ARM rounding mode to softfloat */
9051 int arm_rmode_to_sf(int rmode)
9052 {
9053     switch (rmode) {
9054     case FPROUNDING_TIEAWAY:
9055         rmode = float_round_ties_away;
9056         break;
9057     case FPROUNDING_ODD:
9058         /* FIXME: add support for TIEAWAY and ODD */
9059         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
9060                       rmode);
9061     case FPROUNDING_TIEEVEN:
9062     default:
9063         rmode = float_round_nearest_even;
9064         break;
9065     case FPROUNDING_POSINF:
9066         rmode = float_round_up;
9067         break;
9068     case FPROUNDING_NEGINF:
9069         rmode = float_round_down;
9070         break;
9071     case FPROUNDING_ZERO:
9072         rmode = float_round_to_zero;
9073         break;
9074     }
9075     return rmode;
9076 }
9077
9078 /* CRC helpers.
9079  * The upper bytes of val (above the number specified by 'bytes') must have
9080  * been zeroed out by the caller.
9081  */
9082 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
9083 {
9084     uint8_t buf[4];
9085
9086     stl_le_p(buf, val);
9087
9088     /* zlib crc32 converts the accumulator and output to one's complement.  */
9089     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
9090 }
9091
9092 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
9093 {
9094     uint8_t buf[4];
9095
9096     stl_le_p(buf, val);
9097
9098     /* Linux crc32c converts the output to one's complement.  */
9099     return crc32c(acc, buf, bytes) ^ 0xffffffff;
9100 }