target/ppc/helper_regs.c

   1 /*
   2  *  PowerPC emulation special registers manipulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "qemu/main-loop.h"
  23 #include "exec/exec-all.h"
  24 #include "sysemu/kvm.h"
  25 #include "helper_regs.h"
  26
  27 /* Swap temporary saved registers with GPRs */
  28 void hreg_swap_gpr_tgpr(CPUPPCState *env)
  29 {
  30     target_ulong tmp;
  31
  32     tmp = env->gpr[0];
  33     env->gpr[0] = env->tgpr[0];
  34     env->tgpr[0] = tmp;
  35     tmp = env->gpr[1];
  36     env->gpr[1] = env->tgpr[1];
  37     env->tgpr[1] = tmp;
  38     tmp = env->gpr[2];
  39     env->gpr[2] = env->tgpr[2];
  40     env->tgpr[2] = tmp;
  41     tmp = env->gpr[3];
  42     env->gpr[3] = env->tgpr[3];
  43     env->tgpr[3] = tmp;
  44 }
  45
  46 void hreg_compute_mem_idx(CPUPPCState *env)
  47 {
  48     /*
  49      * This is our encoding for server processors. The architecture
  50      * specifies that there is no such thing as userspace with
  51      * translation off, however it appears that MacOS does it and some
  52      * 32-bit CPUs support it. Weird...
  53      *
  54      *   0 = Guest User space virtual mode
  55      *   1 = Guest Kernel space virtual mode
  56      *   2 = Guest User space real mode
  57      *   3 = Guest Kernel space real mode
  58      *   4 = HV User space virtual mode
  59      *   5 = HV Kernel space virtual mode
  60      *   6 = HV User space real mode
  61      *   7 = HV Kernel space real mode
  62      *
  63      * For BookE, we need 8 MMU modes as follow:
  64      *
  65      *  0 = AS 0 HV User space
  66      *  1 = AS 0 HV Kernel space
  67      *  2 = AS 1 HV User space
  68      *  3 = AS 1 HV Kernel space
  69      *  4 = AS 0 Guest User space
  70      *  5 = AS 0 Guest Kernel space
  71      *  6 = AS 1 Guest User space
  72      *  7 = AS 1 Guest Kernel space
  73      */
  74     if (env->mmu_model & POWERPC_MMU_BOOKE) {
  75         env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
  76         env->immu_idx += msr_is ? 2 : 0;
  77         env->dmmu_idx += msr_ds ? 2 : 0;
  78         env->immu_idx += msr_gs ? 4 : 0;
  79         env->dmmu_idx += msr_gs ? 4 : 0;
  80     } else {
  81         env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
  82         env->immu_idx += msr_ir ? 0 : 2;
  83         env->dmmu_idx += msr_dr ? 0 : 2;
  84         env->immu_idx += msr_hv ? 4 : 0;
  85         env->dmmu_idx += msr_hv ? 4 : 0;
  86     }
  87 }
  88
  89 void hreg_compute_hflags(CPUPPCState *env)
  90 {
  91     target_ulong msr = env->msr;
  92     uint32_t ppc_flags = env->flags;
  93     uint32_t hflags = 0;
  94     uint32_t msr_mask;
  95
  96     /* Some bits come straight across from MSR. */
  97     QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE);
  98     QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR);
  99     QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR);
 100     QEMU_BUILD_BUG_ON(MSR_IR != HFLAGS_IR);
 101     QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP);
 102     msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) |
 103                 (1 << MSR_DR) | (1 << MSR_IR) | (1 << MSR_FP));
 104
 105     if (ppc_flags & POWERPC_FLAG_HID0_LE) {
 106         /*
 107          * Note that MSR_LE is not set in env->msr_mask for this cpu,
 108          * and so will never be set in msr.
 109          */
 110         uint32_t le = extract32(env->spr[SPR_HID0], 3, 1);
 111         hflags |= le << MSR_LE;
 112     }
 113
 114     if (ppc_flags & POWERPC_FLAG_DE) {
 115         target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
 116         if (dbcr0 & DBCR0_ICMP) {
 117             hflags |= 1 << HFLAGS_SE;
 118         }
 119         if (dbcr0 & DBCR0_BRT) {
 120             hflags |= 1 << HFLAGS_BE;
 121         }
 122     } else {
 123         if (ppc_flags & POWERPC_FLAG_BE) {
 124             QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE);
 125             msr_mask |= 1 << MSR_BE;
 126         }
 127         if (ppc_flags & POWERPC_FLAG_SE) {
 128             QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE);
 129             msr_mask |= 1 << MSR_SE;
 130         }
 131     }
 132
 133     if (msr_is_64bit(env, msr)) {
 134         hflags |= 1 << HFLAGS_64;
 135     }
 136     if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) {
 137         hflags |= 1 << HFLAGS_SPE;
 138     }
 139     if (ppc_flags & POWERPC_FLAG_VRE) {
 140         QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR);
 141         msr_mask |= 1 << MSR_VR;
 142     }
 143     if (ppc_flags & POWERPC_FLAG_VSX) {
 144         QEMU_BUILD_BUG_ON(MSR_VSX != HFLAGS_VSX);
 145         msr_mask |= 1 << MSR_VSX;
 146     }
 147     if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) {
 148         hflags |= 1 << HFLAGS_TM;
 149     }
 150     if (env->spr[SPR_LPCR] & LPCR_GTSE) {
 151         hflags |= 1 << HFLAGS_GTSE;
 152     }
 153
 154 #ifndef CONFIG_USER_ONLY
 155     if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
 156         hflags |= 1 << HFLAGS_HV;
 157     }
 158 #endif
 159
 160     env->hflags = hflags | (msr & msr_mask);
 161     hreg_compute_mem_idx(env);
 162 }
 163
 164 void cpu_interrupt_exittb(CPUState *cs)
 165 {
 166     if (!kvm_enabled()) {
 167         return;
 168     }
 169
 170     if (!qemu_mutex_iothread_locked()) {
 171         qemu_mutex_lock_iothread();
 172         cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
 173         qemu_mutex_unlock_iothread();
 174     } else {
 175         cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
 176     }
 177 }
 178
 179 int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
 180 {
 181     int excp;
 182 #if !defined(CONFIG_USER_ONLY)
 183     CPUState *cs = env_cpu(env);
 184 #endif
 185
 186     excp = 0;
 187     value &= env->msr_mask;
 188 #if !defined(CONFIG_USER_ONLY)
 189     /* Neither mtmsr nor guest state can alter HV */
 190     if (!alter_hv || !(env->msr & MSR_HVB)) {
 191         value &= ~MSR_HVB;
 192         value |= env->msr & MSR_HVB;
 193     }
 194     if (((value >> MSR_IR) & 1) != msr_ir ||
 195         ((value >> MSR_DR) & 1) != msr_dr) {
 196         cpu_interrupt_exittb(cs);
 197     }
 198     if ((env->mmu_model & POWERPC_MMU_BOOKE) &&
 199         ((value >> MSR_GS) & 1) != msr_gs) {
 200         cpu_interrupt_exittb(cs);
 201     }
 202     if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
 203                  ((value ^ env->msr) & (1 << MSR_TGPR)))) {
 204         /* Swap temporary saved registers with GPRs */
 205         hreg_swap_gpr_tgpr(env);
 206     }
 207     if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
 208         /* Change the exception prefix on PowerPC 601 */
 209         env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
 210     }
 211     /*
 212      * If PR=1 then EE, IR and DR must be 1
 213      *
 214      * Note: We only enforce this on 64-bit server processors.
 215      * It appears that:
 216      * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
 217      *   exploits it.
 218      * - 64-bit embedded implementations do not need any operation to be
 219      *   performed when PR is set.
 220      */
 221     if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) {
 222         value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
 223     }
 224 #endif
 225     env->msr = value;
 226     hreg_compute_hflags(env);
 227 #if !defined(CONFIG_USER_ONLY)
 228     if (unlikely(msr_pow == 1)) {
 229         if (!env->pending_interrupts && (*env->check_pow)(env)) {
 230             cs->halted = 1;
 231             excp = EXCP_HALTED;
 232         }
 233     }
 234 #endif
 235
 236     return excp;
 237 }
 238
 239 #ifndef CONFIG_USER_ONLY
 240 void check_tlb_flush(CPUPPCState *env, bool global)
 241 {
 242     CPUState *cs = env_cpu(env);
 243
 244     /* Handle global flushes first */
 245     if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
 246         env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
 247         env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
 248         tlb_flush_all_cpus_synced(cs);
 249         return;
 250     }
 251
 252     /* Then handle local ones */
 253     if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {
 254         env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
 255         tlb_flush(cs);
 256     }
 257 }
 258 #endif