target/riscv/cpu.h

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef RISCV_CPU_H
  21 #define RISCV_CPU_H
  22
  23 #include "hw/core/cpu.h"
  24 #include "hw/registerfields.h"
  25 #include "exec/cpu-defs.h"
  26 #include "fpu/softfloat-types.h"
  27 #include "qom/object.h"
  28
  29 #define TCG_GUEST_DEFAULT_MO 0
  30
  31 #define TYPE_RISCV_CPU "riscv-cpu"
  32
  33 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
  34 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
  35 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
  36
  37 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
  38 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
  39 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
  40 #define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
  41 #define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
  42 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
  43 #define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
  44 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
  45 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
  46 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
  47
  48 #if defined(TARGET_RISCV32)
  49 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
  50 #elif defined(TARGET_RISCV64)
  51 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
  52 #endif
  53
  54 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
  55 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
  56
  57 #if defined(TARGET_RISCV32)
  58 #define RVXLEN RV32
  59 #elif defined(TARGET_RISCV64)
  60 #define RVXLEN RV64
  61 #endif
  62
  63 #define RV(x) ((target_ulong)1 << (x - 'A'))
  64
  65 #define RVI RV('I')
  66 #define RVE RV('E') /* E and I are mutually exclusive */
  67 #define RVM RV('M')
  68 #define RVA RV('A')
  69 #define RVF RV('F')
  70 #define RVD RV('D')
  71 #define RVV RV('V')
  72 #define RVC RV('C')
  73 #define RVS RV('S')
  74 #define RVU RV('U')
  75 #define RVH RV('H')
  76
  77 /* S extension denotes that Supervisor mode exists, however it is possible
  78    to have a core that support S mode but does not have an MMU and there
  79    is currently no bit in misa to indicate whether an MMU exists or not
  80    so a cpu features bitfield is required, likewise for optional PMP support */
  81 enum {
  82     RISCV_FEATURE_MMU,
  83     RISCV_FEATURE_PMP,
  84     RISCV_FEATURE_MISA
  85 };
  86
  87 #define PRIV_VERSION_1_10_0 0x00011000
  88 #define PRIV_VERSION_1_11_0 0x00011100
  89
  90 #define VEXT_VERSION_0_07_1 0x00000701
  91
  92 enum {
  93     TRANSLATE_SUCCESS,
  94     TRANSLATE_FAIL,
  95     TRANSLATE_PMP_FAIL,
  96     TRANSLATE_G_STAGE_FAIL
  97 };
  98
  99 #define MMU_USER_IDX 3
 100
 101 #define MAX_RISCV_PMPS (16)
 102
 103 typedef struct CPURISCVState CPURISCVState;
 104
 105 #include "pmp.h"
 106
 107 #define RV_VLEN_MAX 256
 108
 109 FIELD(VTYPE, VLMUL, 0, 2)
 110 FIELD(VTYPE, VSEW, 2, 3)
 111 FIELD(VTYPE, VEDIV, 5, 2)
 112 FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
 113 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
 114
 115 struct CPURISCVState {
 116     target_ulong gpr[32];
 117     uint64_t fpr[32]; /* assume both F and D extensions */
 118
 119     /* vector coprocessor state. */
 120     uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
 121     target_ulong vxrm;
 122     target_ulong vxsat;
 123     target_ulong vl;
 124     target_ulong vstart;
 125     target_ulong vtype;
 126
 127     target_ulong pc;
 128     target_ulong load_res;
 129     target_ulong load_val;
 130
 131     target_ulong frm;
 132
 133     target_ulong badaddr;
 134     target_ulong guest_phys_fault_addr;
 135
 136     target_ulong priv_ver;
 137     target_ulong vext_ver;
 138     target_ulong misa;
 139     target_ulong misa_mask;
 140
 141     uint32_t features;
 142
 143 #ifdef CONFIG_USER_ONLY
 144     uint32_t elf_flags;
 145 #endif
 146
 147 #ifndef CONFIG_USER_ONLY
 148     target_ulong priv;
 149     /* This contains QEMU specific information about the virt state. */
 150     target_ulong virt;
 151     target_ulong resetvec;
 152
 153     target_ulong mhartid;
 154     /*
 155      * For RV32 this is 32-bit mstatus and 32-bit mstatush.
 156      * For RV64 this is a 64-bit mstatus.
 157      */
 158     uint64_t mstatus;
 159
 160     target_ulong mip;
 161
 162     uint32_t miclaim;
 163
 164     target_ulong mie;
 165     target_ulong mideleg;
 166
 167     target_ulong satp;   /* since: priv-1.10.0 */
 168     target_ulong stval;
 169     target_ulong medeleg;
 170
 171     target_ulong stvec;
 172     target_ulong sepc;
 173     target_ulong scause;
 174
 175     target_ulong mtvec;
 176     target_ulong mepc;
 177     target_ulong mcause;
 178     target_ulong mtval;  /* since: priv-1.10.0 */
 179
 180     /* Hypervisor CSRs */
 181     target_ulong hstatus;
 182     target_ulong hedeleg;
 183     target_ulong hideleg;
 184     target_ulong hcounteren;
 185     target_ulong htval;
 186     target_ulong htinst;
 187     target_ulong hgatp;
 188     uint64_t htimedelta;
 189
 190     /* Virtual CSRs */
 191     /*
 192      * For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
 193      * For RV64 this is a 64-bit vsstatus.
 194      */
 195     uint64_t vsstatus;
 196     target_ulong vstvec;
 197     target_ulong vsscratch;
 198     target_ulong vsepc;
 199     target_ulong vscause;
 200     target_ulong vstval;
 201     target_ulong vsatp;
 202
 203     target_ulong mtval2;
 204     target_ulong mtinst;
 205
 206     /* HS Backup CSRs */
 207     target_ulong stvec_hs;
 208     target_ulong sscratch_hs;
 209     target_ulong sepc_hs;
 210     target_ulong scause_hs;
 211     target_ulong stval_hs;
 212     target_ulong satp_hs;
 213     uint64_t mstatus_hs;
 214
 215     /* Signals whether the current exception occurred with two-stage address
 216        translation active. */
 217     bool two_stage_lookup;
 218
 219     target_ulong scounteren;
 220     target_ulong mcounteren;
 221
 222     target_ulong sscratch;
 223     target_ulong mscratch;
 224
 225     /* temporary htif regs */
 226     uint64_t mfromhost;
 227     uint64_t mtohost;
 228     uint64_t timecmp;
 229
 230     /* physical memory protection */
 231     pmp_table_t pmp_state;
 232
 233     /* machine specific rdtime callback */
 234     uint64_t (*rdtime_fn)(uint32_t);
 235     uint32_t rdtime_fn_arg;
 236
 237     /* True if in debugger mode.  */
 238     bool debugger;
 239 #endif
 240
 241     float_status fp_status;
 242
 243     /* Fields from here on are preserved across CPU reset. */
 244     QEMUTimer *timer; /* Internal timer */
 245 };
 246
 247 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
 248                     RISCV_CPU)
 249
 250 /**
 251  * RISCVCPUClass:
 252  * @parent_realize: The parent class' realize handler.
 253  * @parent_reset: The parent class' reset handler.
 254  *
 255  * A RISCV CPU model.
 256  */
 257 struct RISCVCPUClass {
 258     /*< private >*/
 259     CPUClass parent_class;
 260     /*< public >*/
 261     DeviceRealize parent_realize;
 262     DeviceReset parent_reset;
 263 };
 264
 265 /**
 266  * RISCVCPU:
 267  * @env: #CPURISCVState
 268  *
 269  * A RISCV CPU.
 270  */
 271 struct RISCVCPU {
 272     /*< private >*/
 273     CPUState parent_obj;
 274     /*< public >*/
 275     CPUNegativeOffsetState neg;
 276     CPURISCVState env;
 277
 278     char *dyn_csr_xml;
 279
 280     /* Configuration Settings */
 281     struct {
 282         bool ext_i;
 283         bool ext_e;
 284         bool ext_g;
 285         bool ext_m;
 286         bool ext_a;
 287         bool ext_f;
 288         bool ext_d;
 289         bool ext_c;
 290         bool ext_s;
 291         bool ext_u;
 292         bool ext_h;
 293         bool ext_v;
 294         bool ext_counters;
 295         bool ext_ifencei;
 296         bool ext_icsr;
 297
 298         char *priv_spec;
 299         char *user_spec;
 300         char *vext_spec;
 301         uint16_t vlen;
 302         uint16_t elen;
 303         bool mmu;
 304         bool pmp;
 305         uint64_t resetvec;
 306     } cfg;
 307 };
 308
 309 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 310 {
 311     return (env->misa & ext) != 0;
 312 }
 313
 314 static inline bool riscv_feature(CPURISCVState *env, int feature)
 315 {
 316     return env->features & (1ULL << feature);
 317 }
 318
 319 #include "cpu_user.h"
 320 #include "cpu_bits.h"
 321
 322 extern const char * const riscv_int_regnames[];
 323 extern const char * const riscv_fpr_regnames[];
 324 extern const char * const riscv_excp_names[];
 325 extern const char * const riscv_intr_names[];
 326
 327 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
 328 void riscv_cpu_do_interrupt(CPUState *cpu);
 329 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
 330                                int cpuid, void *opaque);
 331 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
 332                                int cpuid, void *opaque);
 333 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 334 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 335 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 336 bool riscv_cpu_fp_enabled(CPURISCVState *env);
 337 bool riscv_cpu_virt_enabled(CPURISCVState *env);
 338 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
 339 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
 340 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
 341 bool riscv_cpu_two_stage_lookup(int mmu_idx);
 342 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 343 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 344 void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 345                                     MMUAccessType access_type, int mmu_idx,
 346                                     uintptr_t retaddr);
 347 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 348                         MMUAccessType access_type, int mmu_idx,
 349                         bool probe, uintptr_t retaddr);
 350 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 351                                      vaddr addr, unsigned size,
 352                                      MMUAccessType access_type,
 353                                      int mmu_idx, MemTxAttrs attrs,
 354                                      MemTxResult response, uintptr_t retaddr);
 355 char *riscv_isa_string(RISCVCPU *cpu);
 356 void riscv_cpu_list(void);
 357
 358 #define cpu_signal_handler riscv_cpu_signal_handler
 359 #define cpu_list riscv_cpu_list
 360 #define cpu_mmu_index riscv_cpu_mmu_index
 361
 362 #ifndef CONFIG_USER_ONLY
 363 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
 364 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
 365 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
 366 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
 367 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
 368                              uint32_t arg);
 369 #endif
 370 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
 371
 372 void riscv_translate_init(void);
 373 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
 374 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
 375                                          uint32_t exception, uintptr_t pc);
 376
 377 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 378 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 379
 380 #define TB_FLAGS_MMU_MASK   7
 381 #define TB_FLAGS_PRIV_MMU_MASK                3
 382 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2)
 383 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
 384
 385 typedef CPURISCVState CPUArchState;
 386 typedef RISCVCPU ArchCPU;
 387 #include "exec/cpu-all.h"
 388
 389 FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
 390 FIELD(TB_FLAGS, LMUL, 3, 2)
 391 FIELD(TB_FLAGS, SEW, 5, 3)
 392 FIELD(TB_FLAGS, VILL, 8, 1)
 393 /* Is a Hypervisor instruction load/store allowed? */
 394 FIELD(TB_FLAGS, HLSX, 9, 1)
 395
 396 bool riscv_cpu_is_32bit(CPURISCVState *env);
 397
 398 /*
 399  * A simplification for VLMAX
 400  * = (1 << LMUL) * VLEN / (8 * (1 << SEW))
 401  * = (VLEN << LMUL) / (8 << SEW)
 402  * = (VLEN << LMUL) >> (SEW + 3)
 403  * = VLEN >> (SEW + 3 - LMUL)
 404  */
 405 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
 406 {
 407     uint8_t sew, lmul;
 408
 409     sew = FIELD_EX64(vtype, VTYPE, VSEW);
 410     lmul = FIELD_EX64(vtype, VTYPE, VLMUL);
 411     return cpu->cfg.vlen >> (sew + 3 - lmul);
 412 }
 413
 414 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 415                                         target_ulong *cs_base, uint32_t *pflags)
 416 {
 417     uint32_t flags = 0;
 418
 419     *pc = env->pc;
 420     *cs_base = 0;
 421
 422     if (riscv_has_ext(env, RVV)) {
 423         uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
 424         bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
 425         flags = FIELD_DP32(flags, TB_FLAGS, VILL,
 426                     FIELD_EX64(env->vtype, VTYPE, VILL));
 427         flags = FIELD_DP32(flags, TB_FLAGS, SEW,
 428                     FIELD_EX64(env->vtype, VTYPE, VSEW));
 429         flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
 430                     FIELD_EX64(env->vtype, VTYPE, VLMUL));
 431         flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
 432     } else {
 433         flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
 434     }
 435
 436 #ifdef CONFIG_USER_ONLY
 437     flags |= TB_FLAGS_MSTATUS_FS;
 438 #else
 439     flags |= cpu_mmu_index(env, 0);
 440     if (riscv_cpu_fp_enabled(env)) {
 441         flags |= env->mstatus & MSTATUS_FS;
 442     }
 443
 444     if (riscv_has_ext(env, RVH)) {
 445         if (env->priv == PRV_M ||
 446             (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 447             (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
 448                 get_field(env->hstatus, HSTATUS_HU))) {
 449             flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
 450         }
 451     }
 452 #endif
 453
 454     *pflags = flags;
 455 }
 456
 457 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 458                 target_ulong new_value, target_ulong write_mask);
 459 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
 460                       target_ulong new_value, target_ulong write_mask);
 461
 462 static inline void riscv_csr_write(CPURISCVState *env, int csrno,
 463                                    target_ulong val)
 464 {
 465     riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
 466 }
 467
 468 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
 469 {
 470     target_ulong val = 0;
 471     riscv_csrrw(env, csrno, &val, 0, 0);
 472     return val;
 473 }
 474
 475 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
 476                                                  int csrno);
 477 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
 478     target_ulong *ret_value);
 479 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
 480     target_ulong new_value);
 481 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
 482     target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
 483
 484 typedef struct {
 485     const char *name;
 486     riscv_csr_predicate_fn predicate;
 487     riscv_csr_read_fn read;
 488     riscv_csr_write_fn write;
 489     riscv_csr_op_fn op;
 490 } riscv_csr_operations;
 491
 492 /* CSR function table constants */
 493 enum {
 494     CSR_TABLE_SIZE = 0x1000
 495 };
 496
 497 /* CSR function table */
 498 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 499
 500 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
 501 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 502
 503 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 504
 505 #endif /* RISCV_CPU_H */