target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22 #ifndef CPU_S390X_H
  23 #define CPU_S390X_H
  24
  25 #include "config.h"
  26 #include "qemu-common.h"
  27
  28 #define TARGET_LONG_BITS 64
  29
  30 #define ELF_MACHINE     EM_S390
  31 #define ELF_MACHINE_UNAME "S390X"
  32
  33 #define CPUArchState struct CPUS390XState
  34
  35 #include "exec/cpu-defs.h"
  36 #define TARGET_PAGE_BITS 12
  37
  38 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  39 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  40
  41 #include "exec/cpu-all.h"
  42
  43 #include "fpu/softfloat.h"
  44
  45 #define NB_MMU_MODES 3
  46
  47 #define MMU_MODE0_SUFFIX _primary
  48 #define MMU_MODE1_SUFFIX _secondary
  49 #define MMU_MODE2_SUFFIX _home
  50
  51 #define MMU_USER_IDX 0
  52
  53 #define MAX_EXT_QUEUE 16
  54 #define MAX_IO_QUEUE 16
  55 #define MAX_MCHK_QUEUE 16
  56
  57 #define PSW_MCHK_MASK 0x0004000000000000
  58 #define PSW_IO_MASK 0x0200000000000000
  59
  60 typedef struct PSW {
  61     uint64_t mask;
  62     uint64_t addr;
  63 } PSW;
  64
  65 typedef struct ExtQueue {
  66     uint32_t code;
  67     uint32_t param;
  68     uint32_t param64;
  69 } ExtQueue;
  70
  71 typedef struct IOIntQueue {
  72     uint16_t id;
  73     uint16_t nr;
  74     uint32_t parm;
  75     uint32_t word;
  76 } IOIntQueue;
  77
  78 typedef struct MchkQueue {
  79     uint16_t type;
  80 } MchkQueue;
  81
  82 typedef struct CPUS390XState {
  83     uint64_t regs[16];     /* GP registers */
  84     /*
  85      * The floating point registers are part of the vector registers.
  86      * vregs[0][0] -> vregs[15][0] are 16 floating point registers
  87      */
  88     CPU_DoubleU vregs[32][2];  /* vector registers */
  89     uint32_t aregs[16];    /* access registers */
  90
  91     uint32_t fpc;          /* floating-point control register */
  92     uint32_t cc_op;
  93
  94     float_status fpu_status; /* passed to softfloat lib */
  95
  96     /* The low part of a 128-bit return, or remainder of a divide.  */
  97     uint64_t retxl;
  98
  99     PSW psw;
 100
 101     uint64_t cc_src;
 102     uint64_t cc_dst;
 103     uint64_t cc_vr;
 104
 105     uint64_t __excp_addr;
 106     uint64_t psa;
 107
 108     uint32_t int_pgm_code;
 109     uint32_t int_pgm_ilen;
 110
 111     uint32_t int_svc_code;
 112     uint32_t int_svc_ilen;
 113
 114     uint64_t cregs[16]; /* control registers */
 115
 116     ExtQueue ext_queue[MAX_EXT_QUEUE];
 117     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 118     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 119
 120     int pending_int;
 121     int ext_index;
 122     int io_index[8];
 123     int mchk_index;
 124
 125     uint64_t ckc;
 126     uint64_t cputm;
 127     uint32_t todpr;
 128
 129     uint64_t pfault_token;
 130     uint64_t pfault_compare;
 131     uint64_t pfault_select;
 132
 133     uint64_t gbea;
 134     uint64_t pp;
 135
 136     CPU_COMMON
 137
 138     /* reset does memset(0) up to here */
 139
 140     uint32_t cpu_num;
 141     uint32_t machine_type;
 142
 143     uint8_t *storage_keys;
 144
 145     uint64_t tod_offset;
 146     uint64_t tod_basetime;
 147     QEMUTimer *tod_timer;
 148
 149     QEMUTimer *cpu_timer;
 150
 151     /*
 152      * The cpu state represents the logical state of a cpu. In contrast to other
 153      * architectures, there is a difference between a halt and a stop on s390.
 154      * If all cpus are either stopped (including check stop) or in the disabled
 155      * wait state, the vm can be shut down.
 156      */
 157 #define CPU_STATE_UNINITIALIZED        0x00
 158 #define CPU_STATE_STOPPED              0x01
 159 #define CPU_STATE_CHECK_STOP           0x02
 160 #define CPU_STATE_OPERATING            0x03
 161 #define CPU_STATE_LOAD                 0x04
 162     uint8_t cpu_state;
 163
 164     /* currently processed sigp order */
 165     uint8_t sigp_order;
 166
 167 } CPUS390XState;
 168
 169 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
 170 {
 171     return &cs->vregs[nr][0];
 172 }
 173
 174 #include "cpu-qom.h"
 175 #include <sysemu/kvm.h>
 176
 177 /* distinguish between 24 bit and 31 bit addressing */
 178 #define HIGH_ORDER_BIT 0x80000000
 179
 180 /* Interrupt Codes */
 181 /* Program Interrupts */
 182 #define PGM_OPERATION                   0x0001
 183 #define PGM_PRIVILEGED                  0x0002
 184 #define PGM_EXECUTE                     0x0003
 185 #define PGM_PROTECTION                  0x0004
 186 #define PGM_ADDRESSING                  0x0005
 187 #define PGM_SPECIFICATION               0x0006
 188 #define PGM_DATA                        0x0007
 189 #define PGM_FIXPT_OVERFLOW              0x0008
 190 #define PGM_FIXPT_DIVIDE                0x0009
 191 #define PGM_DEC_OVERFLOW                0x000a
 192 #define PGM_DEC_DIVIDE                  0x000b
 193 #define PGM_HFP_EXP_OVERFLOW            0x000c
 194 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 195 #define PGM_HFP_SIGNIFICANCE            0x000e
 196 #define PGM_HFP_DIVIDE                  0x000f
 197 #define PGM_SEGMENT_TRANS               0x0010
 198 #define PGM_PAGE_TRANS                  0x0011
 199 #define PGM_TRANS_SPEC                  0x0012
 200 #define PGM_SPECIAL_OP                  0x0013
 201 #define PGM_OPERAND                     0x0015
 202 #define PGM_TRACE_TABLE                 0x0016
 203 #define PGM_SPACE_SWITCH                0x001c
 204 #define PGM_HFP_SQRT                    0x001d
 205 #define PGM_PC_TRANS_SPEC               0x001f
 206 #define PGM_AFX_TRANS                   0x0020
 207 #define PGM_ASX_TRANS                   0x0021
 208 #define PGM_LX_TRANS                    0x0022
 209 #define PGM_EX_TRANS                    0x0023
 210 #define PGM_PRIM_AUTH                   0x0024
 211 #define PGM_SEC_AUTH                    0x0025
 212 #define PGM_ALET_SPEC                   0x0028
 213 #define PGM_ALEN_SPEC                   0x0029
 214 #define PGM_ALE_SEQ                     0x002a
 215 #define PGM_ASTE_VALID                  0x002b
 216 #define PGM_ASTE_SEQ                    0x002c
 217 #define PGM_EXT_AUTH                    0x002d
 218 #define PGM_STACK_FULL                  0x0030
 219 #define PGM_STACK_EMPTY                 0x0031
 220 #define PGM_STACK_SPEC                  0x0032
 221 #define PGM_STACK_TYPE                  0x0033
 222 #define PGM_STACK_OP                    0x0034
 223 #define PGM_ASCE_TYPE                   0x0038
 224 #define PGM_REG_FIRST_TRANS             0x0039
 225 #define PGM_REG_SEC_TRANS               0x003a
 226 #define PGM_REG_THIRD_TRANS             0x003b
 227 #define PGM_MONITOR                     0x0040
 228 #define PGM_PER                         0x0080
 229 #define PGM_CRYPTO                      0x0119
 230
 231 /* External Interrupts */
 232 #define EXT_INTERRUPT_KEY               0x0040
 233 #define EXT_CLOCK_COMP                  0x1004
 234 #define EXT_CPU_TIMER                   0x1005
 235 #define EXT_MALFUNCTION                 0x1200
 236 #define EXT_EMERGENCY                   0x1201
 237 #define EXT_EXTERNAL_CALL               0x1202
 238 #define EXT_ETR                         0x1406
 239 #define EXT_SERVICE                     0x2401
 240 #define EXT_VIRTIO                      0x2603
 241
 242 /* PSW defines */
 243 #undef PSW_MASK_PER
 244 #undef PSW_MASK_DAT
 245 #undef PSW_MASK_IO
 246 #undef PSW_MASK_EXT
 247 #undef PSW_MASK_KEY
 248 #undef PSW_SHIFT_KEY
 249 #undef PSW_MASK_MCHECK
 250 #undef PSW_MASK_WAIT
 251 #undef PSW_MASK_PSTATE
 252 #undef PSW_MASK_ASC
 253 #undef PSW_MASK_CC
 254 #undef PSW_MASK_PM
 255 #undef PSW_MASK_64
 256 #undef PSW_MASK_32
 257 #undef PSW_MASK_ESA_ADDR
 258
 259 #define PSW_MASK_PER            0x4000000000000000ULL
 260 #define PSW_MASK_DAT            0x0400000000000000ULL
 261 #define PSW_MASK_IO             0x0200000000000000ULL
 262 #define PSW_MASK_EXT            0x0100000000000000ULL
 263 #define PSW_MASK_KEY            0x00F0000000000000ULL
 264 #define PSW_SHIFT_KEY           56
 265 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 266 #define PSW_MASK_WAIT           0x0002000000000000ULL
 267 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 268 #define PSW_MASK_ASC            0x0000C00000000000ULL
 269 #define PSW_MASK_CC             0x0000300000000000ULL
 270 #define PSW_MASK_PM             0x00000F0000000000ULL
 271 #define PSW_MASK_64             0x0000000100000000ULL
 272 #define PSW_MASK_32             0x0000000080000000ULL
 273 #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 274
 275 #undef PSW_ASC_PRIMARY
 276 #undef PSW_ASC_ACCREG
 277 #undef PSW_ASC_SECONDARY
 278 #undef PSW_ASC_HOME
 279
 280 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 281 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 282 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 283 #define PSW_ASC_HOME            0x0000C00000000000ULL
 284
 285 /* tb flags */
 286
 287 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 288 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 289 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 290 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 291 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 292 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 293 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 294 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 295 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 296 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 297 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 298 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 299 #define FLAG_MASK_32            0x00001000
 300
 301 /* Control register 0 bits */
 302 #define CR0_LOWPROT             0x0000000010000000ULL
 303 #define CR0_EDAT                0x0000000000800000ULL
 304
 305 /* MMU */
 306 #define MMU_PRIMARY_IDX         0
 307 #define MMU_SECONDARY_IDX       1
 308 #define MMU_HOME_IDX            2
 309
 310 static inline int cpu_mmu_index (CPUS390XState *env)
 311 {
 312     switch (env->psw.mask & PSW_MASK_ASC) {
 313     case PSW_ASC_PRIMARY:
 314         return MMU_PRIMARY_IDX;
 315     case PSW_ASC_SECONDARY:
 316         return MMU_SECONDARY_IDX;
 317     case PSW_ASC_HOME:
 318         return MMU_HOME_IDX;
 319     case PSW_ASC_ACCREG:
 320         /* Fallthrough: access register mode is not yet supported */
 321     default:
 322         abort();
 323     }
 324 }
 325
 326 static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
 327 {
 328     switch (mmu_idx) {
 329     case MMU_PRIMARY_IDX:
 330         return PSW_ASC_PRIMARY;
 331     case MMU_SECONDARY_IDX:
 332         return PSW_ASC_SECONDARY;
 333     case MMU_HOME_IDX:
 334         return PSW_ASC_HOME;
 335     default:
 336         abort();
 337     }
 338 }
 339
 340 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 341                                         target_ulong *cs_base, int *flags)
 342 {
 343     *pc = env->psw.addr;
 344     *cs_base = 0;
 345     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 346              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 347 }
 348
 349 /* While the PoO talks about ILC (a number between 1-3) what is actually
 350    stored in LowCore is shifted left one bit (an even between 2-6).  As
 351    this is the actual length of the insn and therefore more useful, that
 352    is what we want to pass around and manipulate.  To make sure that we
 353    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 354 static inline int get_ilen(uint8_t opc)
 355 {
 356     switch (opc >> 6) {
 357     case 0:
 358         return 2;
 359     case 1:
 360     case 2:
 361         return 4;
 362     default:
 363         return 6;
 364     }
 365 }
 366
 367 #ifndef CONFIG_USER_ONLY
 368 /* In several cases of runtime exceptions, we havn't recorded the true
 369    instruction length.  Use these codes when raising exceptions in order
 370    to re-compute the length by examining the insn in memory.  */
 371 #define ILEN_LATER       0x20
 372 #define ILEN_LATER_INC   0x21
 373 void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
 374 #endif
 375
 376 S390CPU *cpu_s390x_init(const char *cpu_model);
 377 void s390x_translate_init(void);
 378 int cpu_s390x_exec(CPUS390XState *s);
 379
 380 /* you can call this signal handler from your SIGBUS and SIGSEGV
 381    signal handlers to inform the virtual CPU of exceptions. non zero
 382    is returned if the signal was handled by the virtual CPU.  */
 383 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 384                            void *puc);
 385 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 386                               int mmu_idx);
 387
 388 #include "ioinst.h"
 389
 390
 391 #ifndef CONFIG_USER_ONLY
 392 void do_restart_interrupt(CPUS390XState *env);
 393
 394 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
 395                                        uint8_t *ar)
 396 {
 397     hwaddr addr = 0;
 398     uint8_t reg;
 399
 400     reg = ipb >> 28;
 401     if (reg > 0) {
 402         addr = env->regs[reg];
 403     }
 404     addr += (ipb >> 16) & 0xfff;
 405     if (ar) {
 406         *ar = reg;
 407     }
 408
 409     return addr;
 410 }
 411
 412 /* Base/displacement are at the same locations. */
 413 #define decode_basedisp_rs decode_basedisp_s
 414
 415 /* helper functions for run_on_cpu() */
 416 static inline void s390_do_cpu_reset(void *arg)
 417 {
 418     CPUState *cs = arg;
 419     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 420
 421     scc->cpu_reset(cs);
 422 }
 423 static inline void s390_do_cpu_full_reset(void *arg)
 424 {
 425     CPUState *cs = arg;
 426
 427     cpu_reset(cs);
 428 }
 429
 430 void s390x_tod_timer(void *opaque);
 431 void s390x_cpu_timer(void *opaque);
 432
 433 int s390_virtio_hypercall(CPUS390XState *env);
 434 void s390_virtio_irq(int config_change, uint64_t token);
 435
 436 #ifdef CONFIG_KVM
 437 void kvm_s390_virtio_irq(int config_change, uint64_t token);
 438 void kvm_s390_service_interrupt(uint32_t parm);
 439 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
 440 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
 441 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
 442 void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
 443 int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
 444                     int len, bool is_write);
 445 int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
 446 int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
 447 #else
 448 static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
 449 {
 450 }
 451 static inline void kvm_s390_service_interrupt(uint32_t parm)
 452 {
 453 }
 454 static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 455 {
 456     return -ENOSYS;
 457 }
 458 static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 459 {
 460     return -ENOSYS;
 461 }
 462 static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
 463                                   void *hostbuf, int len, bool is_write)
 464 {
 465     return -ENOSYS;
 466 }
 467 static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
 468                                              uint64_t te_code)
 469 {
 470 }
 471 #endif
 472
 473 static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 474 {
 475     if (kvm_enabled()) {
 476         return kvm_s390_get_clock(tod_high, tod_low);
 477     }
 478     /* Fixme TCG */
 479     *tod_high = 0;
 480     *tod_low = 0;
 481     return 0;
 482 }
 483
 484 static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 485 {
 486     if (kvm_enabled()) {
 487         return kvm_s390_set_clock(tod_high, tod_low);
 488     }
 489     /* Fixme TCG */
 490     return 0;
 491 }
 492
 493 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 494 unsigned int s390_cpu_halt(S390CPU *cpu);
 495 void s390_cpu_unhalt(S390CPU *cpu);
 496 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
 497 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
 498 {
 499     return cpu->env.cpu_state;
 500 }
 501
 502 void gtod_save(QEMUFile *f, void *opaque);
 503 int gtod_load(QEMUFile *f, void *opaque, int version_id);
 504
 505 /* service interrupts are floating therefore we must not pass an cpustate */
 506 void s390_sclp_extint(uint32_t parm);
 507
 508 /* from s390-virtio-bus */
 509 extern const hwaddr virtio_size;
 510
 511 #else
 512 static inline unsigned int s390_cpu_halt(S390CPU *cpu)
 513 {
 514     return 0;
 515 }
 516
 517 static inline void s390_cpu_unhalt(S390CPU *cpu)
 518 {
 519 }
 520
 521 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 522 {
 523     return 0;
 524 }
 525 #endif
 526 void cpu_lock(void);
 527 void cpu_unlock(void);
 528
 529 typedef struct SubchDev SubchDev;
 530
 531 #ifndef CONFIG_USER_ONLY
 532 extern void io_subsystem_reset(void);
 533 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 534                          uint16_t schid);
 535 bool css_subch_visible(SubchDev *sch);
 536 void css_conditional_io_interrupt(SubchDev *sch);
 537 int css_do_stsch(SubchDev *sch, SCHIB *schib);
 538 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
 539 int css_do_msch(SubchDev *sch, const SCHIB *schib);
 540 int css_do_xsch(SubchDev *sch);
 541 int css_do_csch(SubchDev *sch);
 542 int css_do_hsch(SubchDev *sch);
 543 int css_do_ssch(SubchDev *sch, ORB *orb);
 544 int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
 545 void css_do_tsch_update_subch(SubchDev *sch);
 546 int css_do_stcrw(CRW *crw);
 547 void css_undo_stcrw(CRW *crw);
 548 int css_do_tpi(IOIntCode *int_code, int lowcore);
 549 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
 550                          int rfmt, void *buf);
 551 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
 552 int css_enable_mcsse(void);
 553 int css_enable_mss(void);
 554 int css_do_rsch(SubchDev *sch);
 555 int css_do_rchp(uint8_t cssid, uint8_t chpid);
 556 bool css_present(uint8_t cssid);
 557 #endif
 558
 559 #define cpu_init(model) CPU(cpu_s390x_init(model))
 560 #define cpu_exec cpu_s390x_exec
 561 #define cpu_gen_code cpu_s390x_gen_code
 562 #define cpu_signal_handler cpu_s390x_signal_handler
 563
 564 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 565 #define cpu_list s390_cpu_list
 566
 567 #include "exec/exec-all.h"
 568
 569 #define EXCP_EXT 1 /* external interrupt */
 570 #define EXCP_SVC 2 /* supervisor call (syscall) */
 571 #define EXCP_PGM 3 /* program interruption */
 572 #define EXCP_IO  7 /* I/O interrupt */
 573 #define EXCP_MCHK 8 /* machine check */
 574
 575 #define INTERRUPT_EXT        (1 << 0)
 576 #define INTERRUPT_TOD        (1 << 1)
 577 #define INTERRUPT_CPUTIMER   (1 << 2)
 578 #define INTERRUPT_IO         (1 << 3)
 579 #define INTERRUPT_MCHK       (1 << 4)
 580
 581 /* Program Status Word.  */
 582 #define S390_PSWM_REGNUM 0
 583 #define S390_PSWA_REGNUM 1
 584 /* General Purpose Registers.  */
 585 #define S390_R0_REGNUM 2
 586 #define S390_R1_REGNUM 3
 587 #define S390_R2_REGNUM 4
 588 #define S390_R3_REGNUM 5
 589 #define S390_R4_REGNUM 6
 590 #define S390_R5_REGNUM 7
 591 #define S390_R6_REGNUM 8
 592 #define S390_R7_REGNUM 9
 593 #define S390_R8_REGNUM 10
 594 #define S390_R9_REGNUM 11
 595 #define S390_R10_REGNUM 12
 596 #define S390_R11_REGNUM 13
 597 #define S390_R12_REGNUM 14
 598 #define S390_R13_REGNUM 15
 599 #define S390_R14_REGNUM 16
 600 #define S390_R15_REGNUM 17
 601 /* Total Core Registers. */
 602 #define S390_NUM_CORE_REGS 18
 603
 604 /* CC optimization */
 605
 606 enum cc_op {
 607     CC_OP_CONST0 = 0,           /* CC is 0 */
 608     CC_OP_CONST1,               /* CC is 1 */
 609     CC_OP_CONST2,               /* CC is 2 */
 610     CC_OP_CONST3,               /* CC is 3 */
 611
 612     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 613     CC_OP_STATIC,               /* CC value is env->cc_op */
 614
 615     CC_OP_NZ,                   /* env->cc_dst != 0 */
 616     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 617     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 618     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 619     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 620     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 621     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 622
 623     CC_OP_ADD_64,               /* overflow on add (64bit) */
 624     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 625     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 626     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 627     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 628     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 629     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 630     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 631
 632     CC_OP_ADD_32,               /* overflow on add (32bit) */
 633     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 634     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 635     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 636     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 637     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 638     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 639     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 640
 641     CC_OP_COMP_32,              /* complement */
 642     CC_OP_COMP_64,              /* complement */
 643
 644     CC_OP_TM_32,                /* test under mask (32bit) */
 645     CC_OP_TM_64,                /* test under mask (64bit) */
 646
 647     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 648     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 649     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 650
 651     CC_OP_ICM,                  /* insert characters under mask */
 652     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 653     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 654     CC_OP_FLOGR,                /* find leftmost one */
 655     CC_OP_MAX
 656 };
 657
 658 static const char *cc_names[] = {
 659     [CC_OP_CONST0]    = "CC_OP_CONST0",
 660     [CC_OP_CONST1]    = "CC_OP_CONST1",
 661     [CC_OP_CONST2]    = "CC_OP_CONST2",
 662     [CC_OP_CONST3]    = "CC_OP_CONST3",
 663     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 664     [CC_OP_STATIC]    = "CC_OP_STATIC",
 665     [CC_OP_NZ]        = "CC_OP_NZ",
 666     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 667     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 668     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 669     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 670     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 671     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 672     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 673     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 674     [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 675     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 676     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 677     [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 678     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 679     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 680     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 681     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 682     [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 683     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 684     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 685     [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 686     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 687     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 688     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 689     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 690     [CC_OP_TM_32]     = "CC_OP_TM_32",
 691     [CC_OP_TM_64]     = "CC_OP_TM_64",
 692     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 693     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 694     [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 695     [CC_OP_ICM]       = "CC_OP_ICM",
 696     [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 697     [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 698     [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 699 };
 700
 701 static inline const char *cc_name(int cc_op)
 702 {
 703     return cc_names[cc_op];
 704 }
 705
 706 static inline void setcc(S390CPU *cpu, uint64_t cc)
 707 {
 708     CPUS390XState *env = &cpu->env;
 709
 710     env->psw.mask &= ~(3ull << 44);
 711     env->psw.mask |= (cc & 3) << 44;
 712 }
 713
 714 typedef struct LowCore
 715 {
 716     /* prefix area: defined by architecture */
 717     uint32_t        ccw1[2];                  /* 0x000 */
 718     uint32_t        ccw2[4];                  /* 0x008 */
 719     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 720     uint32_t        ext_params;               /* 0x080 */
 721     uint16_t        cpu_addr;                 /* 0x084 */
 722     uint16_t        ext_int_code;             /* 0x086 */
 723     uint16_t        svc_ilen;                 /* 0x088 */
 724     uint16_t        svc_code;                 /* 0x08a */
 725     uint16_t        pgm_ilen;                 /* 0x08c */
 726     uint16_t        pgm_code;                 /* 0x08e */
 727     uint32_t        data_exc_code;            /* 0x090 */
 728     uint16_t        mon_class_num;            /* 0x094 */
 729     uint16_t        per_perc_atmid;           /* 0x096 */
 730     uint64_t        per_address;              /* 0x098 */
 731     uint8_t         exc_access_id;            /* 0x0a0 */
 732     uint8_t         per_access_id;            /* 0x0a1 */
 733     uint8_t         op_access_id;             /* 0x0a2 */
 734     uint8_t         ar_access_id;             /* 0x0a3 */
 735     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 736     uint64_t        trans_exc_code;           /* 0x0a8 */
 737     uint64_t        monitor_code;             /* 0x0b0 */
 738     uint16_t        subchannel_id;            /* 0x0b8 */
 739     uint16_t        subchannel_nr;            /* 0x0ba */
 740     uint32_t        io_int_parm;              /* 0x0bc */
 741     uint32_t        io_int_word;              /* 0x0c0 */
 742     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 743     uint32_t        stfl_fac_list;            /* 0x0c8 */
 744     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 745     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 746     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 747     uint32_t        external_damage_code;     /* 0x0f4 */
 748     uint64_t        failing_storage_address;  /* 0x0f8 */
 749     uint8_t         pad6[0x120-0x100];        /* 0x100 */
 750     PSW             restart_old_psw;          /* 0x120 */
 751     PSW             external_old_psw;         /* 0x130 */
 752     PSW             svc_old_psw;              /* 0x140 */
 753     PSW             program_old_psw;          /* 0x150 */
 754     PSW             mcck_old_psw;             /* 0x160 */
 755     PSW             io_old_psw;               /* 0x170 */
 756     uint8_t         pad7[0x1a0-0x180];        /* 0x180 */
 757     PSW             restart_new_psw;          /* 0x1a0 */
 758     PSW             external_new_psw;         /* 0x1b0 */
 759     PSW             svc_new_psw;              /* 0x1c0 */
 760     PSW             program_new_psw;          /* 0x1d0 */
 761     PSW             mcck_new_psw;             /* 0x1e0 */
 762     PSW             io_new_psw;               /* 0x1f0 */
 763     PSW             return_psw;               /* 0x200 */
 764     uint8_t         irb[64];                  /* 0x210 */
 765     uint64_t        sync_enter_timer;         /* 0x250 */
 766     uint64_t        async_enter_timer;        /* 0x258 */
 767     uint64_t        exit_timer;               /* 0x260 */
 768     uint64_t        last_update_timer;        /* 0x268 */
 769     uint64_t        user_timer;               /* 0x270 */
 770     uint64_t        system_timer;             /* 0x278 */
 771     uint64_t        last_update_clock;        /* 0x280 */
 772     uint64_t        steal_clock;              /* 0x288 */
 773     PSW             return_mcck_psw;          /* 0x290 */
 774     uint8_t         pad8[0xc00-0x2a0];        /* 0x2a0 */
 775     /* System info area */
 776     uint64_t        save_area[16];            /* 0xc00 */
 777     uint8_t         pad9[0xd40-0xc80];        /* 0xc80 */
 778     uint64_t        kernel_stack;             /* 0xd40 */
 779     uint64_t        thread_info;              /* 0xd48 */
 780     uint64_t        async_stack;              /* 0xd50 */
 781     uint64_t        kernel_asce;              /* 0xd58 */
 782     uint64_t        user_asce;                /* 0xd60 */
 783     uint64_t        panic_stack;              /* 0xd68 */
 784     uint64_t        user_exec_asce;           /* 0xd70 */
 785     uint8_t         pad10[0xdc0-0xd78];       /* 0xd78 */
 786
 787     /* SMP info area: defined by DJB */
 788     uint64_t        clock_comparator;         /* 0xdc0 */
 789     uint64_t        ext_call_fast;            /* 0xdc8 */
 790     uint64_t        percpu_offset;            /* 0xdd0 */
 791     uint64_t        current_task;             /* 0xdd8 */
 792     uint32_t        softirq_pending;          /* 0xde0 */
 793     uint32_t        pad_0x0de4;               /* 0xde4 */
 794     uint64_t        int_clock;                /* 0xde8 */
 795     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 796
 797     /* 0xe00 is used as indicator for dump tools */
 798     /* whether the kernel died with panic() or not */
 799     uint32_t        panic_magic;              /* 0xe00 */
 800
 801     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 802
 803     /* 64 bit extparam used for pfault, diag 250 etc  */
 804     uint64_t        ext_params2;               /* 0x11B8 */
 805
 806     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 807
 808     /* System info area */
 809
 810     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 811     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 812     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 813     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 814     uint32_t        prefixreg_save_area;       /* 0x1318 */
 815     uint32_t        fpt_creg_save_area;        /* 0x131c */
 816     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 817     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 818     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 819     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 820     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 821     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 822     uint64_t        cregs_save_area[16];       /* 0x1380 */
 823
 824     /* align to the top of the prefix area */
 825
 826     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 827 } QEMU_PACKED LowCore;
 828
 829 /* STSI */
 830 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 831 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 832 #define STSI_LEVEL_1            0x0000000010000000ULL
 833 #define STSI_LEVEL_2            0x0000000020000000ULL
 834 #define STSI_LEVEL_3            0x0000000030000000ULL
 835 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 836 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 837 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 838 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 839
 840 /* Basic Machine Configuration */
 841 struct sysib_111 {
 842     uint32_t res1[8];
 843     uint8_t  manuf[16];
 844     uint8_t  type[4];
 845     uint8_t  res2[12];
 846     uint8_t  model[16];
 847     uint8_t  sequence[16];
 848     uint8_t  plant[4];
 849     uint8_t  res3[156];
 850 };
 851
 852 /* Basic Machine CPU */
 853 struct sysib_121 {
 854     uint32_t res1[80];
 855     uint8_t  sequence[16];
 856     uint8_t  plant[4];
 857     uint8_t  res2[2];
 858     uint16_t cpu_addr;
 859     uint8_t  res3[152];
 860 };
 861
 862 /* Basic Machine CPUs */
 863 struct sysib_122 {
 864     uint8_t res1[32];
 865     uint32_t capability;
 866     uint16_t total_cpus;
 867     uint16_t active_cpus;
 868     uint16_t standby_cpus;
 869     uint16_t reserved_cpus;
 870     uint16_t adjustments[2026];
 871 };
 872
 873 /* LPAR CPU */
 874 struct sysib_221 {
 875     uint32_t res1[80];
 876     uint8_t  sequence[16];
 877     uint8_t  plant[4];
 878     uint16_t cpu_id;
 879     uint16_t cpu_addr;
 880     uint8_t  res3[152];
 881 };
 882
 883 /* LPAR CPUs */
 884 struct sysib_222 {
 885     uint32_t res1[32];
 886     uint16_t lpar_num;
 887     uint8_t  res2;
 888     uint8_t  lcpuc;
 889     uint16_t total_cpus;
 890     uint16_t conf_cpus;
 891     uint16_t standby_cpus;
 892     uint16_t reserved_cpus;
 893     uint8_t  name[8];
 894     uint32_t caf;
 895     uint8_t  res3[16];
 896     uint16_t dedicated_cpus;
 897     uint16_t shared_cpus;
 898     uint8_t  res4[180];
 899 };
 900
 901 /* VM CPUs */
 902 struct sysib_322 {
 903     uint8_t  res1[31];
 904     uint8_t  count;
 905     struct {
 906         uint8_t  res2[4];
 907         uint16_t total_cpus;
 908         uint16_t conf_cpus;
 909         uint16_t standby_cpus;
 910         uint16_t reserved_cpus;
 911         uint8_t  name[8];
 912         uint32_t caf;
 913         uint8_t  cpi[16];
 914         uint8_t res5[3];
 915         uint8_t ext_name_encoding;
 916         uint32_t res3;
 917         uint8_t uuid[16];
 918     } vm[8];
 919     uint8_t res4[1504];
 920     uint8_t ext_names[8][256];
 921 };
 922
 923 /* MMU defines */
 924 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 925 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 926 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 927 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 928 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 929 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 930 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 931 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 932 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 933 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 934 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 935 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 936
 937 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 938 #define _REGION_ENTRY_RO        0x200     /* region/segment protection bit    */
 939 #define _REGION_ENTRY_TF        0xc0      /* region/segment table offset      */
 940 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 941 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 942 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 943 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 944 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 945 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 946
 947 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 948 #define _SEGMENT_ENTRY_FC       0x400     /* format control                   */
 949 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 950 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 951
 952 #define _PAGE_RO        0x200            /* HW read-only bit  */
 953 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 954 #define _PAGE_RES0      0x800            /* bit must be zero  */
 955
 956 #define SK_C                    (0x1 << 1)
 957 #define SK_R                    (0x1 << 2)
 958 #define SK_F                    (0x1 << 3)
 959 #define SK_ACC_MASK             (0xf << 4)
 960
 961 /* SIGP order codes */
 962 #define SIGP_SENSE             0x01
 963 #define SIGP_EXTERNAL_CALL     0x02
 964 #define SIGP_EMERGENCY         0x03
 965 #define SIGP_START             0x04
 966 #define SIGP_STOP              0x05
 967 #define SIGP_RESTART           0x06
 968 #define SIGP_STOP_STORE_STATUS 0x09
 969 #define SIGP_INITIAL_CPU_RESET 0x0b
 970 #define SIGP_CPU_RESET         0x0c
 971 #define SIGP_SET_PREFIX        0x0d
 972 #define SIGP_STORE_STATUS_ADDR 0x0e
 973 #define SIGP_SET_ARCH          0x12
 974 #define SIGP_STORE_ADTL_STATUS 0x17
 975
 976 /* SIGP condition codes */
 977 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
 978 #define SIGP_CC_STATUS_STORED       1
 979 #define SIGP_CC_BUSY                2
 980 #define SIGP_CC_NOT_OPERATIONAL     3
 981
 982 /* SIGP status bits */
 983 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 984 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 985 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 986 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 987 #define SIGP_STAT_STOPPED           0x00000040UL
 988 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 989 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 990 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 991 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 992 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 993
 994 /* SIGP SET ARCHITECTURE modes */
 995 #define SIGP_MODE_ESA_S390 0
 996 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
 997 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
 998
 999 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
1000 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
1001                   target_ulong *raddr, int *flags, bool exc);
1002 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
1003 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
1004                  uint64_t vr);
1005
1006 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
1007                          int len, bool is_write);
1008
1009 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len)    \
1010         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
1011 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len)       \
1012         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
1013 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len)   \
1014         s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
1015
1016 /* The value of the TOD clock for 1.1.1970. */
1017 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
1018
1019 /* Converts ns to s390's clock format */
1020 static inline uint64_t time2tod(uint64_t ns) {
1021     return (ns << 9) / 125;
1022 }
1023
1024 /* Converts s390's clock format to ns */
1025 static inline uint64_t tod2time(uint64_t t) {
1026     return (t * 125) >> 9;
1027 }
1028
1029 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
1030                                   uint64_t param64)
1031 {
1032     CPUS390XState *env = &cpu->env;
1033
1034     if (env->ext_index == MAX_EXT_QUEUE - 1) {
1035         /* ugh - can't queue anymore. Let's drop. */
1036         return;
1037     }
1038
1039     env->ext_index++;
1040     assert(env->ext_index < MAX_EXT_QUEUE);
1041
1042     env->ext_queue[env->ext_index].code = code;
1043     env->ext_queue[env->ext_index].param = param;
1044     env->ext_queue[env->ext_index].param64 = param64;
1045
1046     env->pending_int |= INTERRUPT_EXT;
1047     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1048 }
1049
1050 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
1051                                  uint16_t subchannel_number,
1052                                  uint32_t io_int_parm, uint32_t io_int_word)
1053 {
1054     CPUS390XState *env = &cpu->env;
1055     int isc = IO_INT_WORD_ISC(io_int_word);
1056
1057     if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1058         /* ugh - can't queue anymore. Let's drop. */
1059         return;
1060     }
1061
1062     env->io_index[isc]++;
1063     assert(env->io_index[isc] < MAX_IO_QUEUE);
1064
1065     env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1066     env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1067     env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1068     env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1069
1070     env->pending_int |= INTERRUPT_IO;
1071     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1072 }
1073
1074 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1075 {
1076     CPUS390XState *env = &cpu->env;
1077
1078     if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1079         /* ugh - can't queue anymore. Let's drop. */
1080         return;
1081     }
1082
1083     env->mchk_index++;
1084     assert(env->mchk_index < MAX_MCHK_QUEUE);
1085
1086     env->mchk_queue[env->mchk_index].type = 1;
1087
1088     env->pending_int |= INTERRUPT_MCHK;
1089     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1090 }
1091
1092 /* from s390-virtio-ccw */
1093 #define MEM_SECTION_SIZE             0x10000000UL
1094 #define MAX_AVAIL_SLOTS              32
1095
1096 /* fpu_helper.c */
1097 uint32_t set_cc_nz_f32(float32 v);
1098 uint32_t set_cc_nz_f64(float64 v);
1099 uint32_t set_cc_nz_f128(float128 v);
1100
1101 /* misc_helper.c */
1102 #ifndef CONFIG_USER_ONLY
1103 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1104 #endif
1105 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1106 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1107                                      uintptr_t retaddr);
1108
1109 #ifdef CONFIG_KVM
1110 void kvm_s390_io_interrupt(uint16_t subchannel_id,
1111                            uint16_t subchannel_nr, uint32_t io_int_parm,
1112                            uint32_t io_int_word);
1113 void kvm_s390_crw_mchk(void);
1114 void kvm_s390_enable_css_support(S390CPU *cpu);
1115 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1116                                     int vq, bool assign);
1117 int kvm_s390_cpu_restart(S390CPU *cpu);
1118 int kvm_s390_get_memslot_count(KVMState *s);
1119 void kvm_s390_clear_cmma_callback(void *opaque);
1120 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1121 void kvm_s390_reset_vcpu(S390CPU *cpu);
1122 int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1123 void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1124 int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1125 #else
1126 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1127                                         uint16_t subchannel_nr,
1128                                         uint32_t io_int_parm,
1129                                         uint32_t io_int_word)
1130 {
1131 }
1132 static inline void kvm_s390_crw_mchk(void)
1133 {
1134 }
1135 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1136 {
1137 }
1138 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1139                                                   uint32_t sch, int vq,
1140                                                   bool assign)
1141 {
1142     return -ENOSYS;
1143 }
1144 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1145 {
1146     return -ENOSYS;
1147 }
1148 static inline void kvm_s390_clear_cmma_callback(void *opaque)
1149 {
1150 }
1151 static inline int kvm_s390_get_memslot_count(KVMState *s)
1152 {
1153   return MAX_AVAIL_SLOTS;
1154 }
1155 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1156 {
1157     return -ENOSYS;
1158 }
1159 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1160 {
1161 }
1162 static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1163                                          uint64_t *hw_limit)
1164 {
1165     return 0;
1166 }
1167 static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1168 {
1169 }
1170 static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1171 {
1172     return 0;
1173 }
1174 #endif
1175
1176 static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1177 {
1178     if (kvm_enabled()) {
1179         return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1180     }
1181     return 0;
1182 }
1183
1184 static inline void cmma_reset(S390CPU *cpu)
1185 {
1186     if (kvm_enabled()) {
1187         CPUState *cs = CPU(cpu);
1188         kvm_s390_clear_cmma_callback(cs->kvm_state);
1189     }
1190 }
1191
1192 static inline int s390_cpu_restart(S390CPU *cpu)
1193 {
1194     if (kvm_enabled()) {
1195         return kvm_s390_cpu_restart(cpu);
1196     }
1197     return -ENOSYS;
1198 }
1199
1200 static inline int s390_get_memslot_count(KVMState *s)
1201 {
1202     if (kvm_enabled()) {
1203         return kvm_s390_get_memslot_count(s);
1204     } else {
1205         return MAX_AVAIL_SLOTS;
1206     }
1207 }
1208
1209 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1210                        uint32_t io_int_parm, uint32_t io_int_word);
1211 void s390_crw_mchk(void);
1212
1213 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1214                                               uint32_t sch_id, int vq,
1215                                               bool assign)
1216 {
1217     if (kvm_enabled()) {
1218         return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1219     } else {
1220         return -ENOSYS;
1221     }
1222 }
1223
1224 #ifdef CONFIG_KVM
1225 static inline bool vregs_needed(void *opaque)
1226 {
1227     if (kvm_enabled()) {
1228         return kvm_check_extension(kvm_state, KVM_CAP_S390_VECTOR_REGISTERS);
1229     }
1230     return 0;
1231 }
1232 #else
1233 static inline bool vregs_needed(void *opaque)
1234 {
1235     return 0;
1236 }
1237 #endif
1238 #endif