2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
26 #include "hw/mips/cpudevs.h"
27 #include "qapi/qapi-commands-target.h"
39 #if !defined(CONFIG_USER_ONLY)
41 /* no MMU emulation */
42 int no_mmu_map_address (CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
43 target_ulong address
, int rw
, int access_type
)
46 *prot
= PAGE_READ
| PAGE_WRITE
;
50 /* fixed mapping MMU emulation */
51 int fixed_mmu_map_address (CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
52 target_ulong address
, int rw
, int access_type
)
54 if (address
<= (int32_t)0x7FFFFFFFUL
) {
55 if (!(env
->CP0_Status
& (1 << CP0St_ERL
)))
56 *physical
= address
+ 0x40000000UL
;
59 } else if (address
<= (int32_t)0xBFFFFFFFUL
)
60 *physical
= address
& 0x1FFFFFFF;
64 *prot
= PAGE_READ
| PAGE_WRITE
;
68 /* MIPS32/MIPS64 R4000-style MMU emulation */
69 int r4k_map_address (CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
70 target_ulong address
, int rw
, int access_type
)
72 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
75 for (i
= 0; i
< env
->tlb
->tlb_in_use
; i
++) {
76 r4k_tlb_t
*tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
77 /* 1k pages are not supported. */
78 target_ulong mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
79 target_ulong tag
= address
& ~mask
;
80 target_ulong VPN
= tlb
->VPN
& ~mask
;
81 #if defined(TARGET_MIPS64)
85 /* Check ASID, virtual page number & size */
86 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
&& !tlb
->EHINV
) {
88 int n
= !!(address
& mask
& ~(mask
>> 1));
89 /* Check access rights */
90 if (!(n
? tlb
->V1
: tlb
->V0
)) {
91 return TLBRET_INVALID
;
93 if (rw
== MMU_INST_FETCH
&& (n
? tlb
->XI1
: tlb
->XI0
)) {
96 if (rw
== MMU_DATA_LOAD
&& (n
? tlb
->RI1
: tlb
->RI0
)) {
99 if (rw
!= MMU_DATA_STORE
|| (n
? tlb
->D1
: tlb
->D0
)) {
100 *physical
= tlb
->PFN
[n
] | (address
& (mask
>> 1));
102 if (n
? tlb
->D1
: tlb
->D0
)
109 return TLBRET_NOMATCH
;
112 static int is_seg_am_mapped(unsigned int am
, bool eu
, int mmu_idx
)
115 * Interpret access control mode and mmu_idx.
118 * UK 0 0 1 1 0 0 - - 0
119 * MK 1 0 1 1 0 1 - - !eu
120 * MSK 2 0 0 1 0 1 1 - !eu
121 * MUSK 3 0 0 0 0 1 1 1 !eu
122 * MUSUK 4 0 0 0 0 0 1 1 0
123 * USK 5 0 0 1 0 0 0 - 0
124 * - 6 - - - - - - - -
125 * UUSK 7 0 0 0 0 0 0 0 0
131 /* If EU is set, always unmapped */
137 /* Never AdE, TLB mapped if AM={1,2,3} */
138 adetlb_mask
= 0x70000000;
142 /* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
143 adetlb_mask
= 0xc0380000;
147 /* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
148 adetlb_mask
= 0xe4180000;
151 /* does this AM cause AdE in current execution mode */
152 if ((adetlb_mask
<< am
) < 0) {
153 return TLBRET_BADADDR
;
158 /* is this AM mapped in current execution mode */
159 return ((adetlb_mask
<< am
) < 0);
162 return TLBRET_BADADDR
;
166 static int get_seg_physical_address(CPUMIPSState
*env
, hwaddr
*physical
,
167 int *prot
, target_ulong real_address
,
168 int rw
, int access_type
, int mmu_idx
,
169 unsigned int am
, bool eu
,
170 target_ulong segmask
,
171 hwaddr physical_base
)
173 int mapped
= is_seg_am_mapped(am
, eu
, mmu_idx
);
176 /* is_seg_am_mapped can report TLBRET_BADADDR */
179 /* The segment is TLB mapped */
180 return env
->tlb
->map_address(env
, physical
, prot
, real_address
, rw
,
183 /* The segment is unmapped */
184 *physical
= physical_base
| (real_address
& segmask
);
185 *prot
= PAGE_READ
| PAGE_WRITE
;
190 static int get_segctl_physical_address(CPUMIPSState
*env
, hwaddr
*physical
,
191 int *prot
, target_ulong real_address
,
192 int rw
, int access_type
, int mmu_idx
,
193 uint16_t segctl
, target_ulong segmask
)
195 unsigned int am
= (segctl
& CP0SC_AM_MASK
) >> CP0SC_AM
;
196 bool eu
= (segctl
>> CP0SC_EU
) & 1;
197 hwaddr pa
= ((hwaddr
)segctl
& CP0SC_PA_MASK
) << 20;
199 return get_seg_physical_address(env
, physical
, prot
, real_address
, rw
,
200 access_type
, mmu_idx
, am
, eu
, segmask
,
201 pa
& ~(hwaddr
)segmask
);
204 static int get_physical_address (CPUMIPSState
*env
, hwaddr
*physical
,
205 int *prot
, target_ulong real_address
,
206 int rw
, int access_type
, int mmu_idx
)
208 /* User mode can only access useg/xuseg */
209 #if defined(TARGET_MIPS64)
210 int user_mode
= mmu_idx
== MIPS_HFLAG_UM
;
211 int supervisor_mode
= mmu_idx
== MIPS_HFLAG_SM
;
212 int kernel_mode
= !user_mode
&& !supervisor_mode
;
213 int UX
= (env
->CP0_Status
& (1 << CP0St_UX
)) != 0;
214 int SX
= (env
->CP0_Status
& (1 << CP0St_SX
)) != 0;
215 int KX
= (env
->CP0_Status
& (1 << CP0St_KX
)) != 0;
217 int ret
= TLBRET_MATCH
;
218 /* effective address (modified for KVM T&E kernel segments) */
219 target_ulong address
= real_address
;
221 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
222 #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
223 #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
224 #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
225 #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
227 #define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
228 #define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
230 if (mips_um_ksegs_enabled()) {
231 /* KVM T&E adds guest kernel segments in useg */
232 if (real_address
>= KVM_KSEG0_BASE
) {
233 if (real_address
< KVM_KSEG2_BASE
) {
235 address
+= KSEG0_BASE
- KVM_KSEG0_BASE
;
236 } else if (real_address
<= USEG_LIMIT
) {
238 address
+= KSEG2_BASE
- KVM_KSEG2_BASE
;
243 if (address
<= USEG_LIMIT
) {
247 if (address
>= 0x40000000UL
) {
248 segctl
= env
->CP0_SegCtl2
;
250 segctl
= env
->CP0_SegCtl2
>> 16;
252 ret
= get_segctl_physical_address(env
, physical
, prot
, real_address
, rw
,
253 access_type
, mmu_idx
, segctl
,
255 #if defined(TARGET_MIPS64)
256 } else if (address
< 0x4000000000000000ULL
) {
258 if (UX
&& address
<= (0x3FFFFFFFFFFFFFFFULL
& env
->SEGMask
)) {
259 ret
= env
->tlb
->map_address(env
, physical
, prot
, real_address
, rw
, access_type
);
261 ret
= TLBRET_BADADDR
;
263 } else if (address
< 0x8000000000000000ULL
) {
265 if ((supervisor_mode
|| kernel_mode
) &&
266 SX
&& address
<= (0x7FFFFFFFFFFFFFFFULL
& env
->SEGMask
)) {
267 ret
= env
->tlb
->map_address(env
, physical
, prot
, real_address
, rw
, access_type
);
269 ret
= TLBRET_BADADDR
;
271 } else if (address
< 0xC000000000000000ULL
) {
273 if ((address
& 0x07FFFFFFFFFFFFFFULL
) <= env
->PAMask
) {
274 /* KX/SX/UX bit to check for each xkphys EVA access mode */
275 static const uint8_t am_ksux
[8] = {
276 [CP0SC_AM_UK
] = (1u << CP0St_KX
),
277 [CP0SC_AM_MK
] = (1u << CP0St_KX
),
278 [CP0SC_AM_MSK
] = (1u << CP0St_SX
),
279 [CP0SC_AM_MUSK
] = (1u << CP0St_UX
),
280 [CP0SC_AM_MUSUK
] = (1u << CP0St_UX
),
281 [CP0SC_AM_USK
] = (1u << CP0St_SX
),
282 [6] = (1u << CP0St_KX
),
283 [CP0SC_AM_UUSK
] = (1u << CP0St_UX
),
285 unsigned int am
= CP0SC_AM_UK
;
286 unsigned int xr
= (env
->CP0_SegCtl2
& CP0SC2_XR_MASK
) >> CP0SC2_XR
;
288 if (xr
& (1 << ((address
>> 59) & 0x7))) {
289 am
= (env
->CP0_SegCtl1
& CP0SC1_XAM_MASK
) >> CP0SC1_XAM
;
291 /* Does CP0_Status.KX/SX/UX permit the access mode (am) */
292 if (env
->CP0_Status
& am_ksux
[am
]) {
293 ret
= get_seg_physical_address(env
, physical
, prot
,
294 real_address
, rw
, access_type
,
295 mmu_idx
, am
, false, env
->PAMask
,
298 ret
= TLBRET_BADADDR
;
301 ret
= TLBRET_BADADDR
;
303 } else if (address
< 0xFFFFFFFF80000000ULL
) {
305 if (kernel_mode
&& KX
&&
306 address
<= (0xFFFFFFFF7FFFFFFFULL
& env
->SEGMask
)) {
307 ret
= env
->tlb
->map_address(env
, physical
, prot
, real_address
, rw
, access_type
);
309 ret
= TLBRET_BADADDR
;
312 } else if (address
< KSEG1_BASE
) {
314 ret
= get_segctl_physical_address(env
, physical
, prot
, real_address
, rw
,
315 access_type
, mmu_idx
,
316 env
->CP0_SegCtl1
>> 16, 0x1FFFFFFF);
317 } else if (address
< KSEG2_BASE
) {
319 ret
= get_segctl_physical_address(env
, physical
, prot
, real_address
, rw
,
320 access_type
, mmu_idx
,
321 env
->CP0_SegCtl1
, 0x1FFFFFFF);
322 } else if (address
< KSEG3_BASE
) {
324 ret
= get_segctl_physical_address(env
, physical
, prot
, real_address
, rw
,
325 access_type
, mmu_idx
,
326 env
->CP0_SegCtl0
>> 16, 0x1FFFFFFF);
329 /* XXX: debug segment is not emulated */
330 ret
= get_segctl_physical_address(env
, physical
, prot
, real_address
, rw
,
331 access_type
, mmu_idx
,
332 env
->CP0_SegCtl0
, 0x1FFFFFFF);
337 void cpu_mips_tlb_flush(CPUMIPSState
*env
)
339 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
341 /* Flush qemu's TLB and discard all shadowed entries. */
343 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
346 /* Called for updates to CP0_Status. */
347 void sync_c0_status(CPUMIPSState
*env
, CPUMIPSState
*cpu
, int tc
)
349 int32_t tcstatus
, *tcst
;
350 uint32_t v
= cpu
->CP0_Status
;
351 uint32_t cu
, mx
, asid
, ksu
;
352 uint32_t mask
= ((1 << CP0TCSt_TCU3
)
353 | (1 << CP0TCSt_TCU2
)
354 | (1 << CP0TCSt_TCU1
)
355 | (1 << CP0TCSt_TCU0
)
357 | (3 << CP0TCSt_TKSU
)
358 | (0xff << CP0TCSt_TASID
));
360 cu
= (v
>> CP0St_CU0
) & 0xf;
361 mx
= (v
>> CP0St_MX
) & 0x1;
362 ksu
= (v
>> CP0St_KSU
) & 0x3;
363 asid
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
365 tcstatus
= cu
<< CP0TCSt_TCU0
;
366 tcstatus
|= mx
<< CP0TCSt_TMX
;
367 tcstatus
|= ksu
<< CP0TCSt_TKSU
;
370 if (tc
== cpu
->current_tc
) {
371 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
373 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
381 void cpu_mips_store_status(CPUMIPSState
*env
, target_ulong val
)
383 uint32_t mask
= env
->CP0_Status_rw_bitmask
;
384 target_ulong old
= env
->CP0_Status
;
386 if (env
->insn_flags
& ISA_MIPS32R6
) {
387 bool has_supervisor
= extract32(mask
, CP0St_KSU
, 2) == 0x3;
388 #if defined(TARGET_MIPS64)
389 uint32_t ksux
= (1 << CP0St_KX
) & val
;
390 ksux
|= (ksux
>> 1) & val
; /* KX = 0 forces SX to be 0 */
391 ksux
|= (ksux
>> 1) & val
; /* SX = 0 forces UX to be 0 */
392 val
= (val
& ~(7 << CP0St_UX
)) | ksux
;
394 if (has_supervisor
&& extract32(val
, CP0St_KSU
, 2) == 0x3) {
395 mask
&= ~(3 << CP0St_KSU
);
397 mask
&= ~(((1 << CP0St_SR
) | (1 << CP0St_NMI
)) & val
);
400 env
->CP0_Status
= (old
& ~mask
) | (val
& mask
);
401 #if defined(TARGET_MIPS64)
402 if ((env
->CP0_Status
^ old
) & (old
& (7 << CP0St_UX
))) {
403 /* Access to at least one of the 64-bit segments has been disabled */
404 tlb_flush(CPU(mips_env_get_cpu(env
)));
407 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
408 sync_c0_status(env
, env
, env
->current_tc
);
414 void cpu_mips_store_cause(CPUMIPSState
*env
, target_ulong val
)
416 uint32_t mask
= 0x00C00300;
417 uint32_t old
= env
->CP0_Cause
;
420 if (env
->insn_flags
& ISA_MIPS32R2
) {
421 mask
|= 1 << CP0Ca_DC
;
423 if (env
->insn_flags
& ISA_MIPS32R6
) {
424 mask
&= ~((1 << CP0Ca_WP
) & val
);
427 env
->CP0_Cause
= (env
->CP0_Cause
& ~mask
) | (val
& mask
);
429 if ((old
^ env
->CP0_Cause
) & (1 << CP0Ca_DC
)) {
430 if (env
->CP0_Cause
& (1 << CP0Ca_DC
)) {
431 cpu_mips_stop_count(env
);
433 cpu_mips_start_count(env
);
437 /* Set/reset software interrupts */
438 for (i
= 0 ; i
< 2 ; i
++) {
439 if ((old
^ env
->CP0_Cause
) & (1 << (CP0Ca_IP
+ i
))) {
440 cpu_mips_soft_irq(env
, i
, env
->CP0_Cause
& (1 << (CP0Ca_IP
+ i
)));
446 static void raise_mmu_exception(CPUMIPSState
*env
, target_ulong address
,
447 int rw
, int tlb_error
)
449 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
450 int exception
= 0, error_code
= 0;
452 if (rw
== MMU_INST_FETCH
) {
453 error_code
|= EXCP_INST_NOTAVAIL
;
459 /* Reference to kernel address from user mode or supervisor mode */
460 /* Reference to supervisor address from user mode */
461 if (rw
== MMU_DATA_STORE
) {
462 exception
= EXCP_AdES
;
464 exception
= EXCP_AdEL
;
468 /* No TLB match for a mapped address */
469 if (rw
== MMU_DATA_STORE
) {
470 exception
= EXCP_TLBS
;
472 exception
= EXCP_TLBL
;
474 error_code
|= EXCP_TLB_NOMATCH
;
477 /* TLB match with no valid bit */
478 if (rw
== MMU_DATA_STORE
) {
479 exception
= EXCP_TLBS
;
481 exception
= EXCP_TLBL
;
485 /* TLB match but 'D' bit is cleared */
486 exception
= EXCP_LTLBL
;
489 /* Execute-Inhibit Exception */
490 if (env
->CP0_PageGrain
& (1 << CP0PG_IEC
)) {
491 exception
= EXCP_TLBXI
;
493 exception
= EXCP_TLBL
;
497 /* Read-Inhibit Exception */
498 if (env
->CP0_PageGrain
& (1 << CP0PG_IEC
)) {
499 exception
= EXCP_TLBRI
;
501 exception
= EXCP_TLBL
;
505 /* Raise exception */
506 if (!(env
->hflags
& MIPS_HFLAG_DM
)) {
507 env
->CP0_BadVAddr
= address
;
509 env
->CP0_Context
= (env
->CP0_Context
& ~0x007fffff) |
510 ((address
>> 9) & 0x007ffff0);
511 env
->CP0_EntryHi
= (env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
) |
512 (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) |
513 (address
& (TARGET_PAGE_MASK
<< 1));
514 #if defined(TARGET_MIPS64)
515 env
->CP0_EntryHi
&= env
->SEGMask
;
517 /* PTEBase */ (env
->CP0_XContext
& ((~0ULL) << (env
->SEGBITS
- 7))) |
518 /* R */ (extract64(address
, 62, 2) << (env
->SEGBITS
- 9)) |
519 /* BadVPN2 */ (extract64(address
, 13, env
->SEGBITS
- 13) << 4);
521 cs
->exception_index
= exception
;
522 env
->error_code
= error_code
;
525 #if !defined(CONFIG_USER_ONLY)
526 hwaddr
mips_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
528 MIPSCPU
*cpu
= MIPS_CPU(cs
);
529 CPUMIPSState
*env
= &cpu
->env
;
533 if (get_physical_address(env
, &phys_addr
, &prot
, addr
, 0, ACCESS_INT
,
534 cpu_mmu_index(env
, false)) != 0) {
541 #if !defined(CONFIG_USER_ONLY)
542 #if !defined(TARGET_MIPS64)
545 * Perform hardware page table walk
547 * Memory accesses are performed using the KERNEL privilege level.
548 * Synchronous exceptions detected on memory accesses cause a silent exit
549 * from page table walking, resulting in a TLB or XTLB Refill exception.
551 * Implementations are not required to support page table walk memory
552 * accesses from mapped memory regions. When an unsupported access is
553 * attempted, a silent exit is taken, resulting in a TLB or XTLB Refill
556 * Note that if an exception is caused by AddressTranslation or LoadMemory
557 * functions, the exception is not taken, a silent exit is taken,
558 * resulting in a TLB or XTLB Refill exception.
561 static bool get_pte(CPUMIPSState
*env
, uint64_t vaddr
, int entry_size
,
564 if ((vaddr
& ((entry_size
>> 3) - 1)) != 0) {
567 if (entry_size
== 64) {
568 *pte
= cpu_ldq_code(env
, vaddr
);
570 *pte
= cpu_ldl_code(env
, vaddr
);
575 static uint64_t get_tlb_entry_layout(CPUMIPSState
*env
, uint64_t entry
,
576 int entry_size
, int ptei
)
578 uint64_t result
= entry
;
580 if (ptei
> entry_size
) {
583 result
>>= (ptei
- 2);
586 result
|= rixi
<< CP0EnLo_XI
;
590 static int walk_directory(CPUMIPSState
*env
, uint64_t *vaddr
,
591 int directory_index
, bool *huge_page
, bool *hgpg_directory_hit
,
592 uint64_t *pw_entrylo0
, uint64_t *pw_entrylo1
)
594 int dph
= (env
->CP0_PWCtl
>> CP0PC_DPH
) & 0x1;
595 int psn
= (env
->CP0_PWCtl
>> CP0PC_PSN
) & 0x3F;
596 int hugepg
= (env
->CP0_PWCtl
>> CP0PC_HUGEPG
) & 0x1;
597 int pf_ptew
= (env
->CP0_PWField
>> CP0PF_PTEW
) & 0x3F;
598 int ptew
= (env
->CP0_PWSize
>> CP0PS_PTEW
) & 0x3F;
599 int native_shift
= (((env
->CP0_PWSize
>> CP0PS_PS
) & 1) == 0) ? 2 : 3;
600 int directory_shift
= (ptew
> 1) ? -1 :
601 (hugepg
&& (ptew
== 1)) ? native_shift
+ 1 : native_shift
;
602 int leaf_shift
= (ptew
> 1) ? -1 :
603 (ptew
== 1) ? native_shift
+ 1 : native_shift
;
604 uint32_t direntry_size
= 1 << (directory_shift
+ 3);
605 uint32_t leafentry_size
= 1 << (leaf_shift
+ 3);
612 if (get_physical_address(env
, &paddr
, &prot
, *vaddr
, MMU_DATA_LOAD
,
613 ACCESS_INT
, cpu_mmu_index(env
, false)) !=
615 /* wrong base address */
618 if (!get_pte(env
, *vaddr
, direntry_size
, &entry
)) {
622 if ((entry
& (1 << psn
)) && hugepg
) {
624 *hgpg_directory_hit
= true;
625 entry
= get_tlb_entry_layout(env
, entry
, leafentry_size
, pf_ptew
);
626 w
= directory_index
- 1;
627 if (directory_index
& 0x1) {
628 /* Generate adjacent page from same PTE for odd TLB page */
630 *pw_entrylo0
= entry
& ~lsb
; /* even page */
631 *pw_entrylo1
= entry
| lsb
; /* odd page */
633 int oddpagebit
= 1 << leaf_shift
;
634 uint64_t vaddr2
= *vaddr
^ oddpagebit
;
635 if (*vaddr
& oddpagebit
) {
636 *pw_entrylo1
= entry
;
638 *pw_entrylo0
= entry
;
640 if (get_physical_address(env
, &paddr
, &prot
, vaddr2
, MMU_DATA_LOAD
,
641 ACCESS_INT
, cpu_mmu_index(env
, false)) !=
645 if (!get_pte(env
, vaddr2
, leafentry_size
, &entry
)) {
648 entry
= get_tlb_entry_layout(env
, entry
, leafentry_size
, pf_ptew
);
649 if (*vaddr
& oddpagebit
) {
650 *pw_entrylo0
= entry
;
652 *pw_entrylo1
= entry
;
664 static bool page_table_walk_refill(CPUMIPSState
*env
, vaddr address
, int rw
,
667 int gdw
= (env
->CP0_PWSize
>> CP0PS_GDW
) & 0x3F;
668 int udw
= (env
->CP0_PWSize
>> CP0PS_UDW
) & 0x3F;
669 int mdw
= (env
->CP0_PWSize
>> CP0PS_MDW
) & 0x3F;
670 int ptw
= (env
->CP0_PWSize
>> CP0PS_PTW
) & 0x3F;
671 int ptew
= (env
->CP0_PWSize
>> CP0PS_PTEW
) & 0x3F;
674 bool huge_page
= false;
675 bool hgpg_bdhit
= false;
676 bool hgpg_gdhit
= false;
677 bool hgpg_udhit
= false;
678 bool hgpg_mdhit
= false;
680 int32_t pw_pagemask
= 0;
681 target_ulong pw_entryhi
= 0;
682 uint64_t pw_entrylo0
= 0;
683 uint64_t pw_entrylo1
= 0;
685 /* Native pointer size */
686 /*For the 32-bit architectures, this bit is fixed to 0.*/
687 int native_shift
= (((env
->CP0_PWSize
>> CP0PS_PS
) & 1) == 0) ? 2 : 3;
689 /* Indices from PWField */
690 int pf_gdw
= (env
->CP0_PWField
>> CP0PF_GDW
) & 0x3F;
691 int pf_udw
= (env
->CP0_PWField
>> CP0PF_UDW
) & 0x3F;
692 int pf_mdw
= (env
->CP0_PWField
>> CP0PF_MDW
) & 0x3F;
693 int pf_ptw
= (env
->CP0_PWField
>> CP0PF_PTW
) & 0x3F;
694 int pf_ptew
= (env
->CP0_PWField
>> CP0PF_PTEW
) & 0x3F;
696 /* Indices computed from faulting address */
697 int gindex
= (address
>> pf_gdw
) & ((1 << gdw
) - 1);
698 int uindex
= (address
>> pf_udw
) & ((1 << udw
) - 1);
699 int mindex
= (address
>> pf_mdw
) & ((1 << mdw
) - 1);
700 int ptindex
= (address
>> pf_ptw
) & ((1 << ptw
) - 1);
702 /* Other HTW configs */
703 int hugepg
= (env
->CP0_PWCtl
>> CP0PC_HUGEPG
) & 0x1;
705 /* HTW Shift values (depend on entry size) */
706 int directory_shift
= (ptew
> 1) ? -1 :
707 (hugepg
&& (ptew
== 1)) ? native_shift
+ 1 : native_shift
;
708 int leaf_shift
= (ptew
> 1) ? -1 :
709 (ptew
== 1) ? native_shift
+ 1 : native_shift
;
711 /* Offsets into tables */
712 int goffset
= gindex
<< directory_shift
;
713 int uoffset
= uindex
<< directory_shift
;
714 int moffset
= mindex
<< directory_shift
;
715 int ptoffset0
= (ptindex
>> 1) << (leaf_shift
+ 1);
716 int ptoffset1
= ptoffset0
| (1 << (leaf_shift
));
718 uint32_t leafentry_size
= 1 << (leaf_shift
+ 3);
720 /* Starting address - Page Table Base */
721 uint64_t vaddr
= env
->CP0_PWBase
;
728 if (!(env
->CP0_Config3
& (1 << CP0C3_PW
))) {
729 /* walker is unimplemented */
732 if (!(env
->CP0_PWCtl
& (1 << CP0PC_PWEN
))) {
733 /* walker is disabled */
736 if (!(gdw
> 0 || udw
> 0 || mdw
> 0)) {
737 /* no structure to walk */
740 if ((directory_shift
== -1) || (leaf_shift
== -1)) {
744 /* Global Directory */
747 switch (walk_directory(env
, &vaddr
, pf_gdw
, &huge_page
, &hgpg_gdhit
,
748 &pw_entrylo0
, &pw_entrylo1
))
760 /* Upper directory */
763 switch (walk_directory(env
, &vaddr
, pf_udw
, &huge_page
, &hgpg_udhit
,
764 &pw_entrylo0
, &pw_entrylo1
))
776 /* Middle directory */
779 switch (walk_directory(env
, &vaddr
, pf_mdw
, &huge_page
, &hgpg_mdhit
,
780 &pw_entrylo0
, &pw_entrylo1
))
792 /* Leaf Level Page Table - First half of PTE pair */
794 if (get_physical_address(env
, &paddr
, &prot
, vaddr
, MMU_DATA_LOAD
,
795 ACCESS_INT
, cpu_mmu_index(env
, false)) !=
799 if (!get_pte(env
, vaddr
, leafentry_size
, &dir_entry
)) {
802 dir_entry
= get_tlb_entry_layout(env
, dir_entry
, leafentry_size
, pf_ptew
);
803 pw_entrylo0
= dir_entry
;
805 /* Leaf Level Page Table - Second half of PTE pair */
807 if (get_physical_address(env
, &paddr
, &prot
, vaddr
, MMU_DATA_LOAD
,
808 ACCESS_INT
, cpu_mmu_index(env
, false)) !=
812 if (!get_pte(env
, vaddr
, leafentry_size
, &dir_entry
)) {
815 dir_entry
= get_tlb_entry_layout(env
, dir_entry
, leafentry_size
, pf_ptew
);
816 pw_entrylo1
= dir_entry
;
820 m
= (1 << pf_ptw
) - 1;
823 switch (hgpg_bdhit
<< 3 | hgpg_gdhit
<< 2 | hgpg_udhit
<< 1 |
827 m
= (1 << pf_gdw
) - 1;
833 m
= (1 << pf_udw
) - 1;
839 m
= (1 << pf_mdw
) - 1;
846 pw_pagemask
= m
>> 12;
847 update_pagemask(env
, pw_pagemask
<< 13, &pw_pagemask
);
848 pw_entryhi
= (address
& ~0x1fff) | (env
->CP0_EntryHi
& 0xFF);
850 target_ulong tmp_entryhi
= env
->CP0_EntryHi
;
851 int32_t tmp_pagemask
= env
->CP0_PageMask
;
852 uint64_t tmp_entrylo0
= env
->CP0_EntryLo0
;
853 uint64_t tmp_entrylo1
= env
->CP0_EntryLo1
;
855 env
->CP0_EntryHi
= pw_entryhi
;
856 env
->CP0_PageMask
= pw_pagemask
;
857 env
->CP0_EntryLo0
= pw_entrylo0
;
858 env
->CP0_EntryLo1
= pw_entrylo1
;
861 * The hardware page walker inserts a page into the TLB in a manner
862 * identical to a TLBWR instruction as executed by the software refill
865 r4k_helper_tlbwr(env
);
867 env
->CP0_EntryHi
= tmp_entryhi
;
868 env
->CP0_PageMask
= tmp_pagemask
;
869 env
->CP0_EntryLo0
= tmp_entrylo0
;
870 env
->CP0_EntryLo1
= tmp_entrylo1
;
877 int mips_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int size
, int rw
,
880 MIPSCPU
*cpu
= MIPS_CPU(cs
);
881 CPUMIPSState
*env
= &cpu
->env
;
882 #if !defined(CONFIG_USER_ONLY)
890 log_cpu_state(cs
, 0);
892 qemu_log_mask(CPU_LOG_MMU
,
893 "%s pc " TARGET_FMT_lx
" ad %" VADDR_PRIx
" rw %d mmu_idx %d\n",
894 __func__
, env
->active_tc
.PC
, address
, rw
, mmu_idx
);
897 #if !defined(CONFIG_USER_ONLY)
898 /* XXX: put correct access by using cpu_restore_state() correctly */
899 access_type
= ACCESS_INT
;
900 ret
= get_physical_address(env
, &physical
, &prot
,
901 address
, rw
, access_type
, mmu_idx
);
904 qemu_log_mask(CPU_LOG_MMU
,
905 "%s address=%" VADDR_PRIx
" physical " TARGET_FMT_plx
906 " prot %d\n", __func__
, address
, physical
, prot
);
909 qemu_log_mask(CPU_LOG_MMU
,
910 "%s address=%" VADDR_PRIx
" ret %d\n", __func__
, address
,
914 if (ret
== TLBRET_MATCH
) {
915 tlb_set_page(cs
, address
& TARGET_PAGE_MASK
,
916 physical
& TARGET_PAGE_MASK
, prot
| PAGE_EXEC
,
917 mmu_idx
, TARGET_PAGE_SIZE
);
922 #if !defined(CONFIG_USER_ONLY)
923 #if !defined(TARGET_MIPS64)
924 if ((ret
== TLBRET_NOMATCH
) && (env
->tlb
->nb_tlb
> 1)) {
926 * Memory reads during hardware page table walking are performed
927 * as if they were kernel-mode load instructions.
929 int mode
= (env
->hflags
& MIPS_HFLAG_KSU
);
931 env
->hflags
&= ~MIPS_HFLAG_KSU
;
932 ret_walker
= page_table_walk_refill(env
, address
, rw
, mmu_idx
);
935 ret
= get_physical_address(env
, &physical
, &prot
,
936 address
, rw
, access_type
, mmu_idx
);
937 if (ret
== TLBRET_MATCH
) {
938 tlb_set_page(cs
, address
& TARGET_PAGE_MASK
,
939 physical
& TARGET_PAGE_MASK
, prot
| PAGE_EXEC
,
940 mmu_idx
, TARGET_PAGE_SIZE
);
948 raise_mmu_exception(env
, address
, rw
, ret
);
955 #if !defined(CONFIG_USER_ONLY)
956 hwaddr
cpu_mips_translate_address(CPUMIPSState
*env
, target_ulong address
, int rw
)
964 access_type
= ACCESS_INT
;
965 ret
= get_physical_address(env
, &physical
, &prot
, address
, rw
, access_type
,
966 cpu_mmu_index(env
, false));
967 if (ret
!= TLBRET_MATCH
) {
968 raise_mmu_exception(env
, address
, rw
, ret
);
975 static const char * const excp_names
[EXCP_LAST
+ 1] = {
976 [EXCP_RESET
] = "reset",
977 [EXCP_SRESET
] = "soft reset",
978 [EXCP_DSS
] = "debug single step",
979 [EXCP_DINT
] = "debug interrupt",
980 [EXCP_NMI
] = "non-maskable interrupt",
981 [EXCP_MCHECK
] = "machine check",
982 [EXCP_EXT_INTERRUPT
] = "interrupt",
983 [EXCP_DFWATCH
] = "deferred watchpoint",
984 [EXCP_DIB
] = "debug instruction breakpoint",
985 [EXCP_IWATCH
] = "instruction fetch watchpoint",
986 [EXCP_AdEL
] = "address error load",
987 [EXCP_AdES
] = "address error store",
988 [EXCP_TLBF
] = "TLB refill",
989 [EXCP_IBE
] = "instruction bus error",
990 [EXCP_DBp
] = "debug breakpoint",
991 [EXCP_SYSCALL
] = "syscall",
992 [EXCP_BREAK
] = "break",
993 [EXCP_CpU
] = "coprocessor unusable",
994 [EXCP_RI
] = "reserved instruction",
995 [EXCP_OVERFLOW
] = "arithmetic overflow",
996 [EXCP_TRAP
] = "trap",
997 [EXCP_FPE
] = "floating point",
998 [EXCP_DDBS
] = "debug data break store",
999 [EXCP_DWATCH
] = "data watchpoint",
1000 [EXCP_LTLBL
] = "TLB modify",
1001 [EXCP_TLBL
] = "TLB load",
1002 [EXCP_TLBS
] = "TLB store",
1003 [EXCP_DBE
] = "data bus error",
1004 [EXCP_DDBL
] = "debug data break load",
1005 [EXCP_THREAD
] = "thread",
1006 [EXCP_MDMX
] = "MDMX",
1007 [EXCP_C2E
] = "precise coprocessor 2",
1008 [EXCP_CACHE
] = "cache error",
1009 [EXCP_TLBXI
] = "TLB execute-inhibit",
1010 [EXCP_TLBRI
] = "TLB read-inhibit",
1011 [EXCP_MSADIS
] = "MSA disabled",
1012 [EXCP_MSAFPE
] = "MSA floating point",
1016 target_ulong
exception_resume_pc (CPUMIPSState
*env
)
1018 target_ulong bad_pc
;
1019 target_ulong isa_mode
;
1021 isa_mode
= !!(env
->hflags
& MIPS_HFLAG_M16
);
1022 bad_pc
= env
->active_tc
.PC
| isa_mode
;
1023 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
1024 /* If the exception was raised from a delay slot, come back to
1026 bad_pc
-= (env
->hflags
& MIPS_HFLAG_B16
? 2 : 4);
1032 #if !defined(CONFIG_USER_ONLY)
1033 static void set_hflags_for_handler (CPUMIPSState
*env
)
1035 /* Exception handlers are entered in 32-bit mode. */
1036 env
->hflags
&= ~(MIPS_HFLAG_M16
);
1037 /* ...except that microMIPS lets you choose. */
1038 if (env
->insn_flags
& ASE_MICROMIPS
) {
1039 env
->hflags
|= (!!(env
->CP0_Config3
1040 & (1 << CP0C3_ISA_ON_EXC
))
1041 << MIPS_HFLAG_M16_SHIFT
);
1045 static inline void set_badinstr_registers(CPUMIPSState
*env
)
1047 if (env
->insn_flags
& ISA_NANOMIPS32
) {
1048 if (env
->CP0_Config3
& (1 << CP0C3_BI
)) {
1049 uint32_t instr
= (cpu_lduw_code(env
, env
->active_tc
.PC
)) << 16;
1050 if ((instr
& 0x10000000) == 0) {
1051 instr
|= cpu_lduw_code(env
, env
->active_tc
.PC
+ 2);
1053 env
->CP0_BadInstr
= instr
;
1055 if ((instr
& 0xFC000000) == 0x60000000) {
1056 instr
= cpu_lduw_code(env
, env
->active_tc
.PC
+ 4) << 16;
1057 env
->CP0_BadInstrX
= instr
;
1063 if (env
->hflags
& MIPS_HFLAG_M16
) {
1064 /* TODO: add BadInstr support for microMIPS */
1067 if (env
->CP0_Config3
& (1 << CP0C3_BI
)) {
1068 env
->CP0_BadInstr
= cpu_ldl_code(env
, env
->active_tc
.PC
);
1070 if ((env
->CP0_Config3
& (1 << CP0C3_BP
)) &&
1071 (env
->hflags
& MIPS_HFLAG_BMASK
)) {
1072 env
->CP0_BadInstrP
= cpu_ldl_code(env
, env
->active_tc
.PC
- 4);
1077 void mips_cpu_do_interrupt(CPUState
*cs
)
1079 #if !defined(CONFIG_USER_ONLY)
1080 MIPSCPU
*cpu
= MIPS_CPU(cs
);
1081 CPUMIPSState
*env
= &cpu
->env
;
1082 bool update_badinstr
= 0;
1083 target_ulong offset
;
1087 if (qemu_loglevel_mask(CPU_LOG_INT
)
1088 && cs
->exception_index
!= EXCP_EXT_INTERRUPT
) {
1089 if (cs
->exception_index
< 0 || cs
->exception_index
> EXCP_LAST
) {
1092 name
= excp_names
[cs
->exception_index
];
1095 qemu_log("%s enter: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
1097 __func__
, env
->active_tc
.PC
, env
->CP0_EPC
, name
);
1099 if (cs
->exception_index
== EXCP_EXT_INTERRUPT
&&
1100 (env
->hflags
& MIPS_HFLAG_DM
)) {
1101 cs
->exception_index
= EXCP_DINT
;
1104 switch (cs
->exception_index
) {
1106 env
->CP0_Debug
|= 1 << CP0DB_DSS
;
1107 /* Debug single step cannot be raised inside a delay slot and
1108 resume will always occur on the next instruction
1109 (but we assume the pc has always been updated during
1110 code translation). */
1111 env
->CP0_DEPC
= env
->active_tc
.PC
| !!(env
->hflags
& MIPS_HFLAG_M16
);
1112 goto enter_debug_mode
;
1114 env
->CP0_Debug
|= 1 << CP0DB_DINT
;
1117 env
->CP0_Debug
|= 1 << CP0DB_DIB
;
1120 env
->CP0_Debug
|= 1 << CP0DB_DBp
;
1121 /* Setup DExcCode - SDBBP instruction */
1122 env
->CP0_Debug
= (env
->CP0_Debug
& ~(0x1fULL
<< CP0DB_DEC
)) | 9 << CP0DB_DEC
;
1125 env
->CP0_Debug
|= 1 << CP0DB_DDBS
;
1128 env
->CP0_Debug
|= 1 << CP0DB_DDBL
;
1130 env
->CP0_DEPC
= exception_resume_pc(env
);
1131 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
1133 if (env
->insn_flags
& ISA_MIPS3
) {
1134 env
->hflags
|= MIPS_HFLAG_64
;
1135 if (!(env
->insn_flags
& ISA_MIPS64R6
) ||
1136 env
->CP0_Status
& (1 << CP0St_KX
)) {
1137 env
->hflags
&= ~MIPS_HFLAG_AWRAP
;
1140 env
->hflags
|= MIPS_HFLAG_DM
| MIPS_HFLAG_CP0
;
1141 env
->hflags
&= ~(MIPS_HFLAG_KSU
);
1142 /* EJTAG probe trap enable is not implemented... */
1143 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)))
1144 env
->CP0_Cause
&= ~(1U << CP0Ca_BD
);
1145 env
->active_tc
.PC
= env
->exception_base
+ 0x480;
1146 set_hflags_for_handler(env
);
1149 cpu_reset(CPU(cpu
));
1152 env
->CP0_Status
|= (1 << CP0St_SR
);
1153 memset(env
->CP0_WatchLo
, 0, sizeof(env
->CP0_WatchLo
));
1156 env
->CP0_Status
|= (1 << CP0St_NMI
);
1158 env
->CP0_ErrorEPC
= exception_resume_pc(env
);
1159 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
1160 env
->CP0_Status
|= (1 << CP0St_ERL
) | (1 << CP0St_BEV
);
1161 if (env
->insn_flags
& ISA_MIPS3
) {
1162 env
->hflags
|= MIPS_HFLAG_64
;
1163 if (!(env
->insn_flags
& ISA_MIPS64R6
) ||
1164 env
->CP0_Status
& (1 << CP0St_KX
)) {
1165 env
->hflags
&= ~MIPS_HFLAG_AWRAP
;
1168 env
->hflags
|= MIPS_HFLAG_CP0
;
1169 env
->hflags
&= ~(MIPS_HFLAG_KSU
);
1170 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)))
1171 env
->CP0_Cause
&= ~(1U << CP0Ca_BD
);
1172 env
->active_tc
.PC
= env
->exception_base
;
1173 set_hflags_for_handler(env
);
1175 case EXCP_EXT_INTERRUPT
:
1177 if (env
->CP0_Cause
& (1 << CP0Ca_IV
)) {
1178 uint32_t spacing
= (env
->CP0_IntCtl
>> CP0IntCtl_VS
) & 0x1f;
1180 if ((env
->CP0_Status
& (1 << CP0St_BEV
)) || spacing
== 0) {
1183 uint32_t vector
= 0;
1184 uint32_t pending
= (env
->CP0_Cause
& CP0Ca_IP_mask
) >> CP0Ca_IP
;
1186 if (env
->CP0_Config3
& (1 << CP0C3_VEIC
)) {
1187 /* For VEIC mode, the external interrupt controller feeds
1188 * the vector through the CP0Cause IP lines. */
1191 /* Vectored Interrupts
1192 * Mask with Status.IM7-IM0 to get enabled interrupts. */
1193 pending
&= (env
->CP0_Status
>> CP0St_IM
) & 0xff;
1194 /* Find the highest-priority interrupt. */
1195 while (pending
>>= 1) {
1199 offset
= 0x200 + (vector
* (spacing
<< 5));
1205 update_badinstr
= !(env
->error_code
& EXCP_INST_NOTAVAIL
);
1209 update_badinstr
= !(env
->error_code
& EXCP_INST_NOTAVAIL
);
1210 if ((env
->error_code
& EXCP_TLB_NOMATCH
) &&
1211 !(env
->CP0_Status
& (1 << CP0St_EXL
))) {
1212 #if defined(TARGET_MIPS64)
1213 int R
= env
->CP0_BadVAddr
>> 62;
1214 int UX
= (env
->CP0_Status
& (1 << CP0St_UX
)) != 0;
1215 int KX
= (env
->CP0_Status
& (1 << CP0St_KX
)) != 0;
1217 if ((R
!= 0 || UX
) && (R
!= 3 || KX
) &&
1218 (!(env
->insn_flags
& (INSN_LOONGSON2E
| INSN_LOONGSON2F
)))) {
1223 #if defined(TARGET_MIPS64)
1230 update_badinstr
= 1;
1231 if ((env
->error_code
& EXCP_TLB_NOMATCH
) &&
1232 !(env
->CP0_Status
& (1 << CP0St_EXL
))) {
1233 #if defined(TARGET_MIPS64)
1234 int R
= env
->CP0_BadVAddr
>> 62;
1235 int UX
= (env
->CP0_Status
& (1 << CP0St_UX
)) != 0;
1236 int KX
= (env
->CP0_Status
& (1 << CP0St_KX
)) != 0;
1238 if ((R
!= 0 || UX
) && (R
!= 3 || KX
) &&
1239 (!(env
->insn_flags
& (INSN_LOONGSON2E
| INSN_LOONGSON2F
)))) {
1244 #if defined(TARGET_MIPS64)
1251 update_badinstr
= !(env
->error_code
& EXCP_INST_NOTAVAIL
);
1255 update_badinstr
= 1;
1265 update_badinstr
= 1;
1269 update_badinstr
= 1;
1273 update_badinstr
= 1;
1277 update_badinstr
= 1;
1278 env
->CP0_Cause
= (env
->CP0_Cause
& ~(0x3 << CP0Ca_CE
)) |
1279 (env
->error_code
<< CP0Ca_CE
);
1283 update_badinstr
= 1;
1287 update_badinstr
= 1;
1291 update_badinstr
= 1;
1295 update_badinstr
= 1;
1302 update_badinstr
= 1;
1309 update_badinstr
= 1;
1316 /* XXX: TODO: manage deferred watch exceptions */
1331 if (!(env
->CP0_Status
& (1 << CP0St_EXL
))) {
1332 env
->CP0_EPC
= exception_resume_pc(env
);
1333 if (update_badinstr
) {
1334 set_badinstr_registers(env
);
1336 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
1337 env
->CP0_Cause
|= (1U << CP0Ca_BD
);
1339 env
->CP0_Cause
&= ~(1U << CP0Ca_BD
);
1341 env
->CP0_Status
|= (1 << CP0St_EXL
);
1342 if (env
->insn_flags
& ISA_MIPS3
) {
1343 env
->hflags
|= MIPS_HFLAG_64
;
1344 if (!(env
->insn_flags
& ISA_MIPS64R6
) ||
1345 env
->CP0_Status
& (1 << CP0St_KX
)) {
1346 env
->hflags
&= ~MIPS_HFLAG_AWRAP
;
1349 env
->hflags
|= MIPS_HFLAG_CP0
;
1350 env
->hflags
&= ~(MIPS_HFLAG_KSU
);
1352 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
1353 if (env
->CP0_Status
& (1 << CP0St_BEV
)) {
1354 env
->active_tc
.PC
= env
->exception_base
+ 0x200;
1355 } else if (cause
== 30 && !(env
->CP0_Config3
& (1 << CP0C3_SC
) &&
1356 env
->CP0_Config5
& (1 << CP0C5_CV
))) {
1357 /* Force KSeg1 for cache errors */
1358 env
->active_tc
.PC
= KSEG1_BASE
| (env
->CP0_EBase
& 0x1FFFF000);
1360 env
->active_tc
.PC
= env
->CP0_EBase
& ~0xfff;
1363 env
->active_tc
.PC
+= offset
;
1364 set_hflags_for_handler(env
);
1365 env
->CP0_Cause
= (env
->CP0_Cause
& ~(0x1f << CP0Ca_EC
)) | (cause
<< CP0Ca_EC
);
1370 if (qemu_loglevel_mask(CPU_LOG_INT
)
1371 && cs
->exception_index
!= EXCP_EXT_INTERRUPT
) {
1372 qemu_log("%s: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
" cause %d\n"
1373 " S %08x C %08x A " TARGET_FMT_lx
" D " TARGET_FMT_lx
"\n",
1374 __func__
, env
->active_tc
.PC
, env
->CP0_EPC
, cause
,
1375 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_BadVAddr
,
1379 cs
->exception_index
= EXCP_NONE
;
1382 bool mips_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
1384 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
1385 MIPSCPU
*cpu
= MIPS_CPU(cs
);
1386 CPUMIPSState
*env
= &cpu
->env
;
1388 if (cpu_mips_hw_interrupts_enabled(env
) &&
1389 cpu_mips_hw_interrupts_pending(env
)) {
1391 cs
->exception_index
= EXCP_EXT_INTERRUPT
;
1392 env
->error_code
= 0;
1393 mips_cpu_do_interrupt(cs
);
1400 #if !defined(CONFIG_USER_ONLY)
1401 void r4k_invalidate_tlb (CPUMIPSState
*env
, int idx
, int use_extra
)
1403 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1408 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
1411 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1412 /* The qemu TLB is flushed when the ASID changes, so no need to
1413 flush these entries again. */
1414 if (tlb
->G
== 0 && tlb
->ASID
!= ASID
) {
1418 if (use_extra
&& env
->tlb
->tlb_in_use
< MIPS_TLB_MAX
) {
1419 /* For tlbwr, we can shadow the discarded entry into
1420 a new (fake) TLB entry, as long as the guest can not
1421 tell that it's there. */
1422 env
->tlb
->mmu
.r4k
.tlb
[env
->tlb
->tlb_in_use
] = *tlb
;
1423 env
->tlb
->tlb_in_use
++;
1427 /* 1k pages are not supported. */
1428 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
1431 addr
= tlb
->VPN
& ~mask
;
1432 #if defined(TARGET_MIPS64)
1433 if (addr
>= (0xFFFFFFFF80000000ULL
& env
->SEGMask
)) {
1434 addr
|= 0x3FFFFF0000000000ULL
;
1437 end
= addr
| (mask
>> 1);
1438 while (addr
< end
) {
1439 tlb_flush_page(cs
, addr
);
1440 addr
+= TARGET_PAGE_SIZE
;
1445 addr
= (tlb
->VPN
& ~mask
) | ((mask
>> 1) + 1);
1446 #if defined(TARGET_MIPS64)
1447 if (addr
>= (0xFFFFFFFF80000000ULL
& env
->SEGMask
)) {
1448 addr
|= 0x3FFFFF0000000000ULL
;
1452 while (addr
- 1 < end
) {
1453 tlb_flush_page(cs
, addr
);
1454 addr
+= TARGET_PAGE_SIZE
;
1460 void QEMU_NORETURN
do_raise_exception_err(CPUMIPSState
*env
,
1465 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
1467 qemu_log_mask(CPU_LOG_INT
, "%s: %d %d\n",
1468 __func__
, exception
, error_code
);
1469 cs
->exception_index
= exception
;
1470 env
->error_code
= error_code
;
1472 cpu_loop_exit_restore(cs
, pc
);
1475 static void mips_cpu_add_definition(gpointer data
, gpointer user_data
)
1477 ObjectClass
*oc
= data
;
1478 CpuDefinitionInfoList
**cpu_list
= user_data
;
1479 CpuDefinitionInfoList
*entry
;
1480 CpuDefinitionInfo
*info
;
1481 const char *typename
;
1483 typename
= object_class_get_name(oc
);
1484 info
= g_malloc0(sizeof(*info
));
1485 info
->name
= g_strndup(typename
,
1486 strlen(typename
) - strlen("-" TYPE_MIPS_CPU
));
1487 info
->q_typename
= g_strdup(typename
);
1489 entry
= g_malloc0(sizeof(*entry
));
1490 entry
->value
= info
;
1491 entry
->next
= *cpu_list
;
1495 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
1497 CpuDefinitionInfoList
*cpu_list
= NULL
;
1500 list
= object_class_get_list(TYPE_MIPS_CPU
, false);
1501 g_slist_foreach(list
, mips_cpu_add_definition
, &cpu_list
);