4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
29 #include "translate.h"
30 #include "internals.h"
31 #include "qemu/host-utils.h"
33 #include "exec/gen-icount.h"
35 #include "exec/helper-proto.h"
36 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
40 static TCGv_i64 cpu_X
[32];
41 static TCGv_i64 cpu_pc
;
42 static TCGv_i32 cpu_NF
, cpu_ZF
, cpu_CF
, cpu_VF
;
44 /* Load/store exclusive handling */
45 static TCGv_i64 cpu_exclusive_addr
;
46 static TCGv_i64 cpu_exclusive_val
;
47 static TCGv_i64 cpu_exclusive_high
;
48 #ifdef CONFIG_USER_ONLY
49 static TCGv_i64 cpu_exclusive_test
;
50 static TCGv_i32 cpu_exclusive_info
;
53 static const char *regnames
[] = {
54 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
55 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
56 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
57 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
61 A64_SHIFT_TYPE_LSL
= 0,
62 A64_SHIFT_TYPE_LSR
= 1,
63 A64_SHIFT_TYPE_ASR
= 2,
64 A64_SHIFT_TYPE_ROR
= 3
67 /* Table based decoder typedefs - used when the relevant bits for decode
68 * are too awkwardly scattered across the instruction (eg SIMD).
70 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
72 typedef struct AArch64DecodeTable
{
75 AArch64DecodeFn
*disas_fn
;
78 /* Function prototype for gen_ functions for calling Neon helpers */
79 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
80 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
81 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
82 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
83 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
84 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
85 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
86 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
87 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
88 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
89 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
90 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
91 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
93 /* initialize TCG globals. */
94 void a64_translate_init(void)
98 cpu_pc
= tcg_global_mem_new_i64(TCG_AREG0
,
99 offsetof(CPUARMState
, pc
),
101 for (i
= 0; i
< 32; i
++) {
102 cpu_X
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
103 offsetof(CPUARMState
, xregs
[i
]),
107 cpu_NF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, NF
), "NF");
108 cpu_ZF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, ZF
), "ZF");
109 cpu_CF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, CF
), "CF");
110 cpu_VF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, VF
), "VF");
112 cpu_exclusive_addr
= tcg_global_mem_new_i64(TCG_AREG0
,
113 offsetof(CPUARMState
, exclusive_addr
), "exclusive_addr");
114 cpu_exclusive_val
= tcg_global_mem_new_i64(TCG_AREG0
,
115 offsetof(CPUARMState
, exclusive_val
), "exclusive_val");
116 cpu_exclusive_high
= tcg_global_mem_new_i64(TCG_AREG0
,
117 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
118 #ifdef CONFIG_USER_ONLY
119 cpu_exclusive_test
= tcg_global_mem_new_i64(TCG_AREG0
,
120 offsetof(CPUARMState
, exclusive_test
), "exclusive_test");
121 cpu_exclusive_info
= tcg_global_mem_new_i32(TCG_AREG0
,
122 offsetof(CPUARMState
, exclusive_info
), "exclusive_info");
126 static inline ARMMMUIdx
get_a64_user_mem_index(DisasContext
*s
)
128 /* Return the mmu_idx to use for A64 "unprivileged load/store" insns:
129 * if EL1, access as if EL0; otherwise access at current EL
131 switch (s
->mmu_idx
) {
132 case ARMMMUIdx_S12NSE1
:
133 return ARMMMUIdx_S12NSE0
;
134 case ARMMMUIdx_S1SE1
:
135 return ARMMMUIdx_S1SE0
;
137 g_assert_not_reached();
143 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
144 fprintf_function cpu_fprintf
, int flags
)
146 ARMCPU
*cpu
= ARM_CPU(cs
);
147 CPUARMState
*env
= &cpu
->env
;
148 uint32_t psr
= pstate_read(env
);
151 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
152 env
->pc
, env
->xregs
[31]);
153 for (i
= 0; i
< 31; i
++) {
154 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
156 cpu_fprintf(f
, "\n");
161 cpu_fprintf(f
, "PSTATE=%08x (flags %c%c%c%c)\n",
163 psr
& PSTATE_N
? 'N' : '-',
164 psr
& PSTATE_Z
? 'Z' : '-',
165 psr
& PSTATE_C
? 'C' : '-',
166 psr
& PSTATE_V
? 'V' : '-');
167 cpu_fprintf(f
, "\n");
169 if (flags
& CPU_DUMP_FPU
) {
171 for (i
= 0; i
< numvfpregs
; i
+= 2) {
172 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
173 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
174 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
176 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
177 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
178 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
181 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
182 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
186 void gen_a64_set_pc_im(uint64_t val
)
188 tcg_gen_movi_i64(cpu_pc
, val
);
191 static void gen_exception_internal(int excp
)
193 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
195 assert(excp_is_internal(excp
));
196 gen_helper_exception_internal(cpu_env
, tcg_excp
);
197 tcg_temp_free_i32(tcg_excp
);
200 static void gen_exception(int excp
, uint32_t syndrome
)
202 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
203 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
205 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
, tcg_syn
);
206 tcg_temp_free_i32(tcg_syn
);
207 tcg_temp_free_i32(tcg_excp
);
210 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
212 gen_a64_set_pc_im(s
->pc
- offset
);
213 gen_exception_internal(excp
);
214 s
->is_jmp
= DISAS_EXC
;
217 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
220 gen_a64_set_pc_im(s
->pc
- offset
);
221 gen_exception(excp
, syndrome
);
222 s
->is_jmp
= DISAS_EXC
;
225 static void gen_ss_advance(DisasContext
*s
)
227 /* If the singlestep state is Active-not-pending, advance to
232 gen_helper_clear_pstate_ss(cpu_env
);
236 static void gen_step_complete_exception(DisasContext
*s
)
238 /* We just completed step of an insn. Move from Active-not-pending
239 * to Active-pending, and then also take the swstep exception.
240 * This corresponds to making the (IMPDEF) choice to prioritize
241 * swstep exceptions over asynchronous exceptions taken to an exception
242 * level where debug is disabled. This choice has the advantage that
243 * we do not need to maintain internal state corresponding to the
244 * ISV/EX syndrome bits between completion of the step and generation
245 * of the exception, and our syndrome information is always correct.
248 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
));
249 s
->is_jmp
= DISAS_EXC
;
252 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
254 /* No direct tb linking with singlestep (either QEMU's or the ARM
255 * debug architecture kind) or deterministic io
257 if (s
->singlestep_enabled
|| s
->ss_active
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
261 /* Only link tbs from inside the same guest page */
262 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
269 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
271 TranslationBlock
*tb
;
274 if (use_goto_tb(s
, n
, dest
)) {
276 gen_a64_set_pc_im(dest
);
277 tcg_gen_exit_tb((intptr_t)tb
+ n
);
278 s
->is_jmp
= DISAS_TB_JUMP
;
280 gen_a64_set_pc_im(dest
);
282 gen_step_complete_exception(s
);
283 } else if (s
->singlestep_enabled
) {
284 gen_exception_internal(EXCP_DEBUG
);
287 s
->is_jmp
= DISAS_TB_JUMP
;
292 static void unallocated_encoding(DisasContext
*s
)
294 /* Unallocated and reserved encodings are uncategorized */
295 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized());
298 #define unsupported_encoding(s, insn) \
300 qemu_log_mask(LOG_UNIMP, \
301 "%s:%d: unsupported instruction encoding 0x%08x " \
302 "at pc=%016" PRIx64 "\n", \
303 __FILE__, __LINE__, insn, s->pc - 4); \
304 unallocated_encoding(s); \
307 static void init_tmp_a64_array(DisasContext
*s
)
309 #ifdef CONFIG_DEBUG_TCG
311 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
312 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
315 s
->tmp_a64_count
= 0;
318 static void free_tmp_a64(DisasContext
*s
)
321 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
322 tcg_temp_free_i64(s
->tmp_a64
[i
]);
324 init_tmp_a64_array(s
);
327 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
329 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
330 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
333 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
335 TCGv_i64 t
= new_tmp_a64(s
);
336 tcg_gen_movi_i64(t
, 0);
341 * Register access functions
343 * These functions are used for directly accessing a register in where
344 * changes to the final register value are likely to be made. If you
345 * need to use a register for temporary calculation (e.g. index type
346 * operations) use the read_* form.
348 * B1.2.1 Register mappings
350 * In instruction register encoding 31 can refer to ZR (zero register) or
351 * the SP (stack pointer) depending on context. In QEMU's case we map SP
352 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
353 * This is the point of the _sp forms.
355 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
358 return new_tmp_a64_zero(s
);
364 /* register access for when 31 == SP */
365 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
370 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
371 * representing the register contents. This TCGv is an auto-freed
372 * temporary so it need not be explicitly freed, and may be modified.
374 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
376 TCGv_i64 v
= new_tmp_a64(s
);
379 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
381 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
384 tcg_gen_movi_i64(v
, 0);
389 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
391 TCGv_i64 v
= new_tmp_a64(s
);
393 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
395 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
400 /* We should have at some point before trying to access an FP register
401 * done the necessary access check, so assert that
402 * (a) we did the check and
403 * (b) we didn't then just plough ahead anyway if it failed.
404 * Print the instruction pattern in the abort message so we can figure
405 * out what we need to fix if a user encounters this problem in the wild.
407 static inline void assert_fp_access_checked(DisasContext
*s
)
409 #ifdef CONFIG_DEBUG_TCG
410 if (unlikely(!s
->fp_access_checked
|| !s
->cpacr_fpen
)) {
411 fprintf(stderr
, "target-arm: FP access check missing for "
412 "instruction 0x%08x\n", s
->insn
);
418 /* Return the offset into CPUARMState of an element of specified
419 * size, 'element' places in from the least significant end of
420 * the FP/vector register Qn.
422 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
423 int element
, TCGMemOp size
)
425 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
426 #ifdef HOST_WORDS_BIGENDIAN
427 /* This is complicated slightly because vfp.regs[2n] is
428 * still the low half and vfp.regs[2n+1] the high half
429 * of the 128 bit vector, even on big endian systems.
430 * Calculate the offset assuming a fully bigendian 128 bits,
431 * then XOR to account for the order of the two 64 bit halves.
433 offs
+= (16 - ((element
+ 1) * (1 << size
)));
436 offs
+= element
* (1 << size
);
438 assert_fp_access_checked(s
);
442 /* Return the offset into CPUARMState of a slice (from
443 * the least significant end) of FP register Qn (ie
445 * (Note that this is not the same mapping as for A32; see cpu.h)
447 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
449 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
450 #ifdef HOST_WORDS_BIGENDIAN
451 offs
+= (8 - (1 << size
));
453 assert_fp_access_checked(s
);
457 /* Offset of the high half of the 128 bit vector Qn */
458 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
460 assert_fp_access_checked(s
);
461 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
464 /* Convenience accessors for reading and writing single and double
465 * FP registers. Writing clears the upper parts of the associated
466 * 128 bit vector register, as required by the architecture.
467 * Note that unlike the GP register accessors, the values returned
468 * by the read functions must be manually freed.
470 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
472 TCGv_i64 v
= tcg_temp_new_i64();
474 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
478 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
480 TCGv_i32 v
= tcg_temp_new_i32();
482 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
486 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
488 TCGv_i64 tcg_zero
= tcg_const_i64(0);
490 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
491 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
492 tcg_temp_free_i64(tcg_zero
);
495 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
497 TCGv_i64 tmp
= tcg_temp_new_i64();
499 tcg_gen_extu_i32_i64(tmp
, v
);
500 write_fp_dreg(s
, reg
, tmp
);
501 tcg_temp_free_i64(tmp
);
504 static TCGv_ptr
get_fpstatus_ptr(void)
506 TCGv_ptr statusptr
= tcg_temp_new_ptr();
509 /* In A64 all instructions (both FP and Neon) use the FPCR;
510 * there is no equivalent of the A32 Neon "standard FPSCR value"
511 * and all operations use vfp.fp_status.
513 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
514 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
518 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
519 * than the 32 bit equivalent.
521 static inline void gen_set_NZ64(TCGv_i64 result
)
523 TCGv_i64 flag
= tcg_temp_new_i64();
525 tcg_gen_setcondi_i64(TCG_COND_NE
, flag
, result
, 0);
526 tcg_gen_trunc_i64_i32(cpu_ZF
, flag
);
527 tcg_gen_shri_i64(flag
, result
, 32);
528 tcg_gen_trunc_i64_i32(cpu_NF
, flag
);
529 tcg_temp_free_i64(flag
);
532 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
533 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
536 gen_set_NZ64(result
);
538 tcg_gen_trunc_i64_i32(cpu_ZF
, result
);
539 tcg_gen_trunc_i64_i32(cpu_NF
, result
);
541 tcg_gen_movi_i32(cpu_CF
, 0);
542 tcg_gen_movi_i32(cpu_VF
, 0);
545 /* dest = T0 + T1; compute C, N, V and Z flags */
546 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
549 TCGv_i64 result
, flag
, tmp
;
550 result
= tcg_temp_new_i64();
551 flag
= tcg_temp_new_i64();
552 tmp
= tcg_temp_new_i64();
554 tcg_gen_movi_i64(tmp
, 0);
555 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
557 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
559 gen_set_NZ64(result
);
561 tcg_gen_xor_i64(flag
, result
, t0
);
562 tcg_gen_xor_i64(tmp
, t0
, t1
);
563 tcg_gen_andc_i64(flag
, flag
, tmp
);
564 tcg_temp_free_i64(tmp
);
565 tcg_gen_shri_i64(flag
, flag
, 32);
566 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
568 tcg_gen_mov_i64(dest
, result
);
569 tcg_temp_free_i64(result
);
570 tcg_temp_free_i64(flag
);
572 /* 32 bit arithmetic */
573 TCGv_i32 t0_32
= tcg_temp_new_i32();
574 TCGv_i32 t1_32
= tcg_temp_new_i32();
575 TCGv_i32 tmp
= tcg_temp_new_i32();
577 tcg_gen_movi_i32(tmp
, 0);
578 tcg_gen_trunc_i64_i32(t0_32
, t0
);
579 tcg_gen_trunc_i64_i32(t1_32
, t1
);
580 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
581 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
582 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
583 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
584 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
585 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
587 tcg_temp_free_i32(tmp
);
588 tcg_temp_free_i32(t0_32
);
589 tcg_temp_free_i32(t1_32
);
593 /* dest = T0 - T1; compute C, N, V and Z flags */
594 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
597 /* 64 bit arithmetic */
598 TCGv_i64 result
, flag
, tmp
;
600 result
= tcg_temp_new_i64();
601 flag
= tcg_temp_new_i64();
602 tcg_gen_sub_i64(result
, t0
, t1
);
604 gen_set_NZ64(result
);
606 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
607 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
609 tcg_gen_xor_i64(flag
, result
, t0
);
610 tmp
= tcg_temp_new_i64();
611 tcg_gen_xor_i64(tmp
, t0
, t1
);
612 tcg_gen_and_i64(flag
, flag
, tmp
);
613 tcg_temp_free_i64(tmp
);
614 tcg_gen_shri_i64(flag
, flag
, 32);
615 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
616 tcg_gen_mov_i64(dest
, result
);
617 tcg_temp_free_i64(flag
);
618 tcg_temp_free_i64(result
);
620 /* 32 bit arithmetic */
621 TCGv_i32 t0_32
= tcg_temp_new_i32();
622 TCGv_i32 t1_32
= tcg_temp_new_i32();
625 tcg_gen_trunc_i64_i32(t0_32
, t0
);
626 tcg_gen_trunc_i64_i32(t1_32
, t1
);
627 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
628 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
629 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
630 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
631 tmp
= tcg_temp_new_i32();
632 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
633 tcg_temp_free_i32(t0_32
);
634 tcg_temp_free_i32(t1_32
);
635 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
636 tcg_temp_free_i32(tmp
);
637 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
641 /* dest = T0 + T1 + CF; do not compute flags. */
642 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
644 TCGv_i64 flag
= tcg_temp_new_i64();
645 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
646 tcg_gen_add_i64(dest
, t0
, t1
);
647 tcg_gen_add_i64(dest
, dest
, flag
);
648 tcg_temp_free_i64(flag
);
651 tcg_gen_ext32u_i64(dest
, dest
);
655 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
656 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
659 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
660 result
= tcg_temp_new_i64();
661 cf_64
= tcg_temp_new_i64();
662 vf_64
= tcg_temp_new_i64();
663 tmp
= tcg_const_i64(0);
665 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
666 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
667 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
668 tcg_gen_trunc_i64_i32(cpu_CF
, cf_64
);
669 gen_set_NZ64(result
);
671 tcg_gen_xor_i64(vf_64
, result
, t0
);
672 tcg_gen_xor_i64(tmp
, t0
, t1
);
673 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
674 tcg_gen_shri_i64(vf_64
, vf_64
, 32);
675 tcg_gen_trunc_i64_i32(cpu_VF
, vf_64
);
677 tcg_gen_mov_i64(dest
, result
);
679 tcg_temp_free_i64(tmp
);
680 tcg_temp_free_i64(vf_64
);
681 tcg_temp_free_i64(cf_64
);
682 tcg_temp_free_i64(result
);
684 TCGv_i32 t0_32
, t1_32
, tmp
;
685 t0_32
= tcg_temp_new_i32();
686 t1_32
= tcg_temp_new_i32();
687 tmp
= tcg_const_i32(0);
689 tcg_gen_trunc_i64_i32(t0_32
, t0
);
690 tcg_gen_trunc_i64_i32(t1_32
, t1
);
691 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
692 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
694 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
695 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
696 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
697 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
698 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
700 tcg_temp_free_i32(tmp
);
701 tcg_temp_free_i32(t1_32
);
702 tcg_temp_free_i32(t0_32
);
707 * Load/Store generators
711 * Store from GPR register to memory.
713 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
714 TCGv_i64 tcg_addr
, int size
, int memidx
)
717 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, MO_TE
+ size
);
720 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
721 TCGv_i64 tcg_addr
, int size
)
723 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
));
727 * Load from memory to GPR register
729 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
730 int size
, bool is_signed
, bool extend
, int memidx
)
732 TCGMemOp memop
= MO_TE
+ size
;
740 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
742 if (extend
&& is_signed
) {
744 tcg_gen_ext32u_i64(dest
, dest
);
748 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
749 int size
, bool is_signed
, bool extend
)
751 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
756 * Store from FP register to memory
758 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
760 /* This writes the bottom N bits of a 128 bit wide vector to memory */
761 TCGv_i64 tmp
= tcg_temp_new_i64();
762 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
764 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TE
+ size
);
766 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
767 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
768 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
769 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
770 tcg_gen_qemu_st_i64(tmp
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
771 tcg_temp_free_i64(tcg_hiaddr
);
774 tcg_temp_free_i64(tmp
);
778 * Load from memory to FP register
780 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
782 /* This always zero-extends and writes to a full 128 bit wide vector */
783 TCGv_i64 tmplo
= tcg_temp_new_i64();
787 TCGMemOp memop
= MO_TE
+ size
;
788 tmphi
= tcg_const_i64(0);
789 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
792 tmphi
= tcg_temp_new_i64();
793 tcg_hiaddr
= tcg_temp_new_i64();
795 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
796 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
797 tcg_gen_qemu_ld_i64(tmphi
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
798 tcg_temp_free_i64(tcg_hiaddr
);
801 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
802 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
804 tcg_temp_free_i64(tmplo
);
805 tcg_temp_free_i64(tmphi
);
809 * Vector load/store helpers.
811 * The principal difference between this and a FP load is that we don't
812 * zero extend as we are filling a partial chunk of the vector register.
813 * These functions don't support 128 bit loads/stores, which would be
814 * normal load/store operations.
816 * The _i32 versions are useful when operating on 32 bit quantities
817 * (eg for floating point single or using Neon helper functions).
820 /* Get value of an element within a vector register */
821 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
822 int element
, TCGMemOp memop
)
824 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
827 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
830 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
833 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
836 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
839 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
842 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
846 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
849 g_assert_not_reached();
853 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
854 int element
, TCGMemOp memop
)
856 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
859 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
862 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
865 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
868 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
872 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
875 g_assert_not_reached();
879 /* Set value of an element within a vector register */
880 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
881 int element
, TCGMemOp memop
)
883 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
886 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
889 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
892 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
895 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
898 g_assert_not_reached();
902 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
903 int destidx
, int element
, TCGMemOp memop
)
905 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
908 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
911 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
914 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
917 g_assert_not_reached();
921 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
922 * vector ops all need to do this).
924 static void clear_vec_high(DisasContext
*s
, int rd
)
926 TCGv_i64 tcg_zero
= tcg_const_i64(0);
928 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
929 tcg_temp_free_i64(tcg_zero
);
932 /* Store from vector register to memory */
933 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
934 TCGv_i64 tcg_addr
, int size
)
936 TCGMemOp memop
= MO_TE
+ size
;
937 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
939 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
940 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
942 tcg_temp_free_i64(tcg_tmp
);
945 /* Load from memory to vector register */
946 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
947 TCGv_i64 tcg_addr
, int size
)
949 TCGMemOp memop
= MO_TE
+ size
;
950 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
952 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
953 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
955 tcg_temp_free_i64(tcg_tmp
);
958 /* Check that FP/Neon access is enabled. If it is, return
959 * true. If not, emit code to generate an appropriate exception,
960 * and return false; the caller should not emit any code for
961 * the instruction. Note that this check must happen after all
962 * unallocated-encoding checks (otherwise the syndrome information
963 * for the resulting exception will be incorrect).
965 static inline bool fp_access_check(DisasContext
*s
)
967 assert(!s
->fp_access_checked
);
968 s
->fp_access_checked
= true;
974 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false));
979 * This utility function is for doing register extension with an
980 * optional shift. You will likely want to pass a temporary for the
981 * destination register. See DecodeRegExtend() in the ARM ARM.
983 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
984 int option
, unsigned int shift
)
986 int extsize
= extract32(option
, 0, 2);
987 bool is_signed
= extract32(option
, 2, 1);
992 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
995 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
998 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1001 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1007 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1010 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1013 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1016 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1022 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1026 static inline void gen_check_sp_alignment(DisasContext
*s
)
1028 /* The AArch64 architecture mandates that (if enabled via PSTATE
1029 * or SCTLR bits) there is a check that SP is 16-aligned on every
1030 * SP-relative load or store (with an exception generated if it is not).
1031 * In line with general QEMU practice regarding misaligned accesses,
1032 * we omit these checks for the sake of guest program performance.
1033 * This function is provided as a hook so we can more easily add these
1034 * checks in future (possibly as a "favour catching guest program bugs
1035 * over speed" user selectable option).
1040 * This provides a simple table based table lookup decoder. It is
1041 * intended to be used when the relevant bits for decode are too
1042 * awkwardly placed and switch/if based logic would be confusing and
1043 * deeply nested. Since it's a linear search through the table, tables
1044 * should be kept small.
1046 * It returns the first handler where insn & mask == pattern, or
1047 * NULL if there is no match.
1048 * The table is terminated by an empty mask (i.e. 0)
1050 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1053 const AArch64DecodeTable
*tptr
= table
;
1055 while (tptr
->mask
) {
1056 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1057 return tptr
->disas_fn
;
1065 * the instruction disassembly implemented here matches
1066 * the instruction encoding classifications in chapter 3 (C3)
1067 * of the ARM Architecture Reference Manual (DDI0487A_a)
1070 /* C3.2.7 Unconditional branch (immediate)
1072 * +----+-----------+-------------------------------------+
1073 * | op | 0 0 1 0 1 | imm26 |
1074 * +----+-----------+-------------------------------------+
1076 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1078 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1080 if (insn
& (1 << 31)) {
1081 /* C5.6.26 BL Branch with link */
1082 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1085 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1086 gen_goto_tb(s
, 0, addr
);
1089 /* C3.2.1 Compare & branch (immediate)
1090 * 31 30 25 24 23 5 4 0
1091 * +----+-------------+----+---------------------+--------+
1092 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1093 * +----+-------------+----+---------------------+--------+
1095 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1097 unsigned int sf
, op
, rt
;
1102 sf
= extract32(insn
, 31, 1);
1103 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1104 rt
= extract32(insn
, 0, 5);
1105 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1107 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1108 label_match
= gen_new_label();
1110 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1111 tcg_cmp
, 0, label_match
);
1113 gen_goto_tb(s
, 0, s
->pc
);
1114 gen_set_label(label_match
);
1115 gen_goto_tb(s
, 1, addr
);
1118 /* C3.2.5 Test & branch (immediate)
1119 * 31 30 25 24 23 19 18 5 4 0
1120 * +----+-------------+----+-------+-------------+------+
1121 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1122 * +----+-------------+----+-------+-------------+------+
1124 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1126 unsigned int bit_pos
, op
, rt
;
1131 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1132 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1133 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1134 rt
= extract32(insn
, 0, 5);
1136 tcg_cmp
= tcg_temp_new_i64();
1137 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1138 label_match
= gen_new_label();
1139 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1140 tcg_cmp
, 0, label_match
);
1141 tcg_temp_free_i64(tcg_cmp
);
1142 gen_goto_tb(s
, 0, s
->pc
);
1143 gen_set_label(label_match
);
1144 gen_goto_tb(s
, 1, addr
);
1147 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1148 * 31 25 24 23 5 4 3 0
1149 * +---------------+----+---------------------+----+------+
1150 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1151 * +---------------+----+---------------------+----+------+
1153 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1158 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1159 unallocated_encoding(s
);
1162 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1163 cond
= extract32(insn
, 0, 4);
1166 /* genuinely conditional branches */
1167 int label_match
= gen_new_label();
1168 arm_gen_test_cc(cond
, label_match
);
1169 gen_goto_tb(s
, 0, s
->pc
);
1170 gen_set_label(label_match
);
1171 gen_goto_tb(s
, 1, addr
);
1173 /* 0xe and 0xf are both "always" conditions */
1174 gen_goto_tb(s
, 0, addr
);
1179 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1180 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1182 unsigned int selector
= crm
<< 3 | op2
;
1185 unallocated_encoding(s
);
1193 s
->is_jmp
= DISAS_WFI
;
1197 s
->is_jmp
= DISAS_WFE
;
1201 /* we treat all as NOP at least for now */
1204 /* default specified as NOP equivalent */
1209 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1211 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1214 /* CLREX, DSB, DMB, ISB */
1215 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1216 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1219 unallocated_encoding(s
);
1230 /* We don't emulate caches so barriers are no-ops */
1233 unallocated_encoding(s
);
1238 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1239 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1240 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1242 int op
= op1
<< 3 | op2
;
1244 case 0x05: /* SPSel */
1245 if (s
->current_el
== 0) {
1246 unallocated_encoding(s
);
1250 case 0x1e: /* DAIFSet */
1251 case 0x1f: /* DAIFClear */
1253 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1254 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1255 gen_a64_set_pc_im(s
->pc
- 4);
1256 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1257 tcg_temp_free_i32(tcg_imm
);
1258 tcg_temp_free_i32(tcg_op
);
1259 s
->is_jmp
= DISAS_UPDATE
;
1263 unallocated_encoding(s
);
1268 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1270 TCGv_i32 tmp
= tcg_temp_new_i32();
1271 TCGv_i32 nzcv
= tcg_temp_new_i32();
1273 /* build bit 31, N */
1274 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1 << 31));
1275 /* build bit 30, Z */
1276 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1277 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1278 /* build bit 29, C */
1279 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1280 /* build bit 28, V */
1281 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1282 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1283 /* generate result */
1284 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1286 tcg_temp_free_i32(nzcv
);
1287 tcg_temp_free_i32(tmp
);
1290 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1293 TCGv_i32 nzcv
= tcg_temp_new_i32();
1295 /* take NZCV from R[t] */
1296 tcg_gen_trunc_i64_i32(nzcv
, tcg_rt
);
1299 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1 << 31));
1301 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1302 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1304 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1305 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1307 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1308 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1309 tcg_temp_free_i32(nzcv
);
1312 /* C5.6.129 MRS - move from system register
1313 * C5.6.131 MSR (register) - move to system register
1316 * These are all essentially the same insn in 'read' and 'write'
1317 * versions, with varying op0 fields.
1319 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1320 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1321 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1323 const ARMCPRegInfo
*ri
;
1326 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1327 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1328 crn
, crm
, op0
, op1
, op2
));
1331 /* Unknown register; this might be a guest error or a QEMU
1332 * unimplemented feature.
1334 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1335 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1336 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1337 unallocated_encoding(s
);
1341 /* Check access permissions */
1342 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1343 unallocated_encoding(s
);
1348 /* Emit code to perform further access permissions checks at
1349 * runtime; this may result in an exception.
1355 gen_a64_set_pc_im(s
->pc
- 4);
1356 tmpptr
= tcg_const_ptr(ri
);
1357 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1358 tcg_syn
= tcg_const_i32(syndrome
);
1359 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
);
1360 tcg_temp_free_ptr(tmpptr
);
1361 tcg_temp_free_i32(tcg_syn
);
1364 /* Handle special cases first */
1365 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1369 tcg_rt
= cpu_reg(s
, rt
);
1371 gen_get_nzcv(tcg_rt
);
1373 gen_set_nzcv(tcg_rt
);
1376 case ARM_CP_CURRENTEL
:
1377 /* Reads as current EL value from pstate, which is
1378 * guaranteed to be constant by the tb flags.
1380 tcg_rt
= cpu_reg(s
, rt
);
1381 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1384 /* Writes clear the aligned block of memory which rt points into. */
1385 tcg_rt
= cpu_reg(s
, rt
);
1386 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1392 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1396 tcg_rt
= cpu_reg(s
, rt
);
1399 if (ri
->type
& ARM_CP_CONST
) {
1400 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1401 } else if (ri
->readfn
) {
1403 tmpptr
= tcg_const_ptr(ri
);
1404 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1405 tcg_temp_free_ptr(tmpptr
);
1407 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1410 if (ri
->type
& ARM_CP_CONST
) {
1411 /* If not forbidden by access permissions, treat as WI */
1413 } else if (ri
->writefn
) {
1415 tmpptr
= tcg_const_ptr(ri
);
1416 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1417 tcg_temp_free_ptr(tmpptr
);
1419 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1423 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1424 /* I/O operations must end the TB here (whether read or write) */
1426 s
->is_jmp
= DISAS_UPDATE
;
1427 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1428 /* We default to ending the TB on a coprocessor register write,
1429 * but allow this to be suppressed by the register definition
1430 * (usually only necessary to work around guest bugs).
1432 s
->is_jmp
= DISAS_UPDATE
;
1437 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1438 * +---------------------+---+-----+-----+-------+-------+-----+------+
1439 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1440 * +---------------------+---+-----+-----+-------+-------+-----+------+
1442 static void disas_system(DisasContext
*s
, uint32_t insn
)
1444 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1445 l
= extract32(insn
, 21, 1);
1446 op0
= extract32(insn
, 19, 2);
1447 op1
= extract32(insn
, 16, 3);
1448 crn
= extract32(insn
, 12, 4);
1449 crm
= extract32(insn
, 8, 4);
1450 op2
= extract32(insn
, 5, 3);
1451 rt
= extract32(insn
, 0, 5);
1454 if (l
|| rt
!= 31) {
1455 unallocated_encoding(s
);
1459 case 2: /* C5.6.68 HINT */
1460 handle_hint(s
, insn
, op1
, op2
, crm
);
1462 case 3: /* CLREX, DSB, DMB, ISB */
1463 handle_sync(s
, insn
, op1
, op2
, crm
);
1465 case 4: /* C5.6.130 MSR (immediate) */
1466 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1469 unallocated_encoding(s
);
1474 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1477 /* C3.2.3 Exception generation
1479 * 31 24 23 21 20 5 4 2 1 0
1480 * +-----------------+-----+------------------------+-----+----+
1481 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1482 * +-----------------------+------------------------+----------+
1484 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1486 int opc
= extract32(insn
, 21, 3);
1487 int op2_ll
= extract32(insn
, 0, 5);
1488 int imm16
= extract32(insn
, 5, 16);
1493 /* For SVC, HVC and SMC we advance the single-step state
1494 * machine before taking the exception. This is architecturally
1495 * mandated, to ensure that single-stepping a system call
1496 * instruction works properly.
1501 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
));
1504 if (s
->current_el
== 0) {
1505 unallocated_encoding(s
);
1508 /* The pre HVC helper handles cases when HVC gets trapped
1509 * as an undefined insn by runtime configuration.
1511 gen_a64_set_pc_im(s
->pc
- 4);
1512 gen_helper_pre_hvc(cpu_env
);
1514 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
));
1517 if (s
->current_el
== 0) {
1518 unallocated_encoding(s
);
1521 gen_a64_set_pc_im(s
->pc
- 4);
1522 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1523 gen_helper_pre_smc(cpu_env
, tmp
);
1524 tcg_temp_free_i32(tmp
);
1526 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
));
1529 unallocated_encoding(s
);
1535 unallocated_encoding(s
);
1539 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
));
1543 unallocated_encoding(s
);
1547 unsupported_encoding(s
, insn
);
1550 if (op2_ll
< 1 || op2_ll
> 3) {
1551 unallocated_encoding(s
);
1554 /* DCPS1, DCPS2, DCPS3 */
1555 unsupported_encoding(s
, insn
);
1558 unallocated_encoding(s
);
1563 /* C3.2.7 Unconditional branch (register)
1564 * 31 25 24 21 20 16 15 10 9 5 4 0
1565 * +---------------+-------+-------+-------+------+-------+
1566 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1567 * +---------------+-------+-------+-------+------+-------+
1569 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1571 unsigned int opc
, op2
, op3
, rn
, op4
;
1573 opc
= extract32(insn
, 21, 4);
1574 op2
= extract32(insn
, 16, 5);
1575 op3
= extract32(insn
, 10, 6);
1576 rn
= extract32(insn
, 5, 5);
1577 op4
= extract32(insn
, 0, 5);
1579 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1580 unallocated_encoding(s
);
1587 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1590 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1591 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1594 if (s
->current_el
== 0) {
1595 unallocated_encoding(s
);
1598 gen_helper_exception_return(cpu_env
);
1599 s
->is_jmp
= DISAS_JUMP
;
1603 unallocated_encoding(s
);
1605 unsupported_encoding(s
, insn
);
1609 unallocated_encoding(s
);
1613 s
->is_jmp
= DISAS_JUMP
;
1616 /* C3.2 Branches, exception generating and system instructions */
1617 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1619 switch (extract32(insn
, 25, 7)) {
1620 case 0x0a: case 0x0b:
1621 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1622 disas_uncond_b_imm(s
, insn
);
1624 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1625 disas_comp_b_imm(s
, insn
);
1627 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1628 disas_test_b_imm(s
, insn
);
1630 case 0x2a: /* Conditional branch (immediate) */
1631 disas_cond_b_imm(s
, insn
);
1633 case 0x6a: /* Exception generation / System */
1634 if (insn
& (1 << 24)) {
1635 disas_system(s
, insn
);
1640 case 0x6b: /* Unconditional branch (register) */
1641 disas_uncond_b_reg(s
, insn
);
1644 unallocated_encoding(s
);
1650 * Load/Store exclusive instructions are implemented by remembering
1651 * the value/address loaded, and seeing if these are the same
1652 * when the store is performed. This is not actually the architecturally
1653 * mandated semantics, but it works for typical guest code sequences
1654 * and avoids having to monitor regular stores.
1656 * In system emulation mode only one CPU will be running at once, so
1657 * this sequence is effectively atomic. In user emulation mode we
1658 * throw an exception and handle the atomic operation elsewhere.
1660 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1661 TCGv_i64 addr
, int size
, bool is_pair
)
1663 TCGv_i64 tmp
= tcg_temp_new_i64();
1664 TCGMemOp memop
= MO_TE
+ size
;
1666 g_assert(size
<= 3);
1667 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1670 TCGv_i64 addr2
= tcg_temp_new_i64();
1671 TCGv_i64 hitmp
= tcg_temp_new_i64();
1673 g_assert(size
>= 2);
1674 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1675 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1676 tcg_temp_free_i64(addr2
);
1677 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1678 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1679 tcg_temp_free_i64(hitmp
);
1682 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1683 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1685 tcg_temp_free_i64(tmp
);
1686 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1689 #ifdef CONFIG_USER_ONLY
1690 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1691 TCGv_i64 addr
, int size
, int is_pair
)
1693 tcg_gen_mov_i64(cpu_exclusive_test
, addr
);
1694 tcg_gen_movi_i32(cpu_exclusive_info
,
1695 size
| is_pair
<< 2 | (rd
<< 4) | (rt
<< 9) | (rt2
<< 14));
1696 gen_exception_internal_insn(s
, 4, EXCP_STREX
);
1699 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1700 TCGv_i64 inaddr
, int size
, int is_pair
)
1702 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1703 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1706 * [addr + datasize] = {Rt2};
1712 * env->exclusive_addr = -1;
1714 int fail_label
= gen_new_label();
1715 int done_label
= gen_new_label();
1716 TCGv_i64 addr
= tcg_temp_local_new_i64();
1719 /* Copy input into a local temp so it is not trashed when the
1720 * basic block ends at the branch insn.
1722 tcg_gen_mov_i64(addr
, inaddr
);
1723 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1725 tmp
= tcg_temp_new_i64();
1726 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), MO_TE
+ size
);
1727 tcg_gen_brcond_i64(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
1728 tcg_temp_free_i64(tmp
);
1731 TCGv_i64 addrhi
= tcg_temp_new_i64();
1732 TCGv_i64 tmphi
= tcg_temp_new_i64();
1734 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1735 tcg_gen_qemu_ld_i64(tmphi
, addrhi
, get_mem_index(s
), MO_TE
+ size
);
1736 tcg_gen_brcond_i64(TCG_COND_NE
, tmphi
, cpu_exclusive_high
, fail_label
);
1738 tcg_temp_free_i64(tmphi
);
1739 tcg_temp_free_i64(addrhi
);
1742 /* We seem to still have the exclusive monitor, so do the store */
1743 tcg_gen_qemu_st_i64(cpu_reg(s
, rt
), addr
, get_mem_index(s
), MO_TE
+ size
);
1745 TCGv_i64 addrhi
= tcg_temp_new_i64();
1747 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1748 tcg_gen_qemu_st_i64(cpu_reg(s
, rt2
), addrhi
,
1749 get_mem_index(s
), MO_TE
+ size
);
1750 tcg_temp_free_i64(addrhi
);
1753 tcg_temp_free_i64(addr
);
1755 tcg_gen_movi_i64(cpu_reg(s
, rd
), 0);
1756 tcg_gen_br(done_label
);
1757 gen_set_label(fail_label
);
1758 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1759 gen_set_label(done_label
);
1760 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1765 /* C3.3.6 Load/store exclusive
1767 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1768 * +-----+-------------+----+---+----+------+----+-------+------+------+
1769 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1770 * +-----+-------------+----+---+----+------+----+-------+------+------+
1772 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1773 * L: 0 -> store, 1 -> load
1774 * o2: 0 -> exclusive, 1 -> not
1775 * o1: 0 -> single register, 1 -> register pair
1776 * o0: 1 -> load-acquire/store-release, 0 -> not
1778 * o0 == 0 AND o2 == 1 is un-allocated
1779 * o1 == 1 is un-allocated except for 32 and 64 bit sizes
1781 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1783 int rt
= extract32(insn
, 0, 5);
1784 int rn
= extract32(insn
, 5, 5);
1785 int rt2
= extract32(insn
, 10, 5);
1786 int is_lasr
= extract32(insn
, 15, 1);
1787 int rs
= extract32(insn
, 16, 5);
1788 int is_pair
= extract32(insn
, 21, 1);
1789 int is_store
= !extract32(insn
, 22, 1);
1790 int is_excl
= !extract32(insn
, 23, 1);
1791 int size
= extract32(insn
, 30, 2);
1794 if ((!is_excl
&& !is_lasr
) ||
1795 (is_pair
&& size
< 2)) {
1796 unallocated_encoding(s
);
1801 gen_check_sp_alignment(s
);
1803 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1805 /* Note that since TCG is single threaded load-acquire/store-release
1806 * semantics require no extra if (is_lasr) { ... } handling.
1812 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1814 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1817 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1819 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1821 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false);
1824 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt
);
1825 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1827 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1829 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, false, false);
1836 * C3.3.5 Load register (literal)
1838 * 31 30 29 27 26 25 24 23 5 4 0
1839 * +-----+-------+---+-----+-------------------+-------+
1840 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1841 * +-----+-------+---+-----+-------------------+-------+
1843 * V: 1 -> vector (simd/fp)
1844 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1845 * 10-> 32 bit signed, 11 -> prefetch
1846 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1848 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
1850 int rt
= extract32(insn
, 0, 5);
1851 int64_t imm
= sextract32(insn
, 5, 19) << 2;
1852 bool is_vector
= extract32(insn
, 26, 1);
1853 int opc
= extract32(insn
, 30, 2);
1854 bool is_signed
= false;
1856 TCGv_i64 tcg_rt
, tcg_addr
;
1860 unallocated_encoding(s
);
1864 if (!fp_access_check(s
)) {
1869 /* PRFM (literal) : prefetch */
1872 size
= 2 + extract32(opc
, 0, 1);
1873 is_signed
= extract32(opc
, 1, 1);
1876 tcg_rt
= cpu_reg(s
, rt
);
1878 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
1880 do_fp_ld(s
, rt
, tcg_addr
, size
);
1882 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1884 tcg_temp_free_i64(tcg_addr
);
1888 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1889 * C5.6.81 LDP (Load Pair - non vector)
1890 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1891 * C5.6.176 STNP (Store Pair - non-temporal hint)
1892 * C5.6.177 STP (Store Pair - non vector)
1893 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1894 * C6.3.165 LDP (Load Pair of SIMD&FP)
1895 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1896 * C6.3.284 STP (Store Pair of SIMD&FP)
1898 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1899 * +-----+-------+---+---+-------+---+-----------------------------+
1900 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1901 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1903 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1905 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1906 * V: 0 -> GPR, 1 -> Vector
1907 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1908 * 10 -> signed offset, 11 -> pre-index
1909 * L: 0 -> Store 1 -> Load
1911 * Rt, Rt2 = GPR or SIMD registers to be stored
1912 * Rn = general purpose register containing address
1913 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1915 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
1917 int rt
= extract32(insn
, 0, 5);
1918 int rn
= extract32(insn
, 5, 5);
1919 int rt2
= extract32(insn
, 10, 5);
1920 int64_t offset
= sextract32(insn
, 15, 7);
1921 int index
= extract32(insn
, 23, 2);
1922 bool is_vector
= extract32(insn
, 26, 1);
1923 bool is_load
= extract32(insn
, 22, 1);
1924 int opc
= extract32(insn
, 30, 2);
1926 bool is_signed
= false;
1927 bool postindex
= false;
1930 TCGv_i64 tcg_addr
; /* calculated address */
1934 unallocated_encoding(s
);
1941 size
= 2 + extract32(opc
, 1, 1);
1942 is_signed
= extract32(opc
, 0, 1);
1943 if (!is_load
&& is_signed
) {
1944 unallocated_encoding(s
);
1950 case 1: /* post-index */
1955 /* signed offset with "non-temporal" hint. Since we don't emulate
1956 * caches we don't care about hints to the cache system about
1957 * data access patterns, and handle this identically to plain
1961 /* There is no non-temporal-hint version of LDPSW */
1962 unallocated_encoding(s
);
1967 case 2: /* signed offset, rn not updated */
1970 case 3: /* pre-index */
1976 if (is_vector
&& !fp_access_check(s
)) {
1983 gen_check_sp_alignment(s
);
1986 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1989 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
1994 do_fp_ld(s
, rt
, tcg_addr
, size
);
1996 do_fp_st(s
, rt
, tcg_addr
, size
);
1999 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2001 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
2003 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2006 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2009 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2011 do_fp_st(s
, rt2
, tcg_addr
, size
);
2014 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2016 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false);
2018 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
2024 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2026 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2028 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2033 * C3.3.8 Load/store (immediate post-indexed)
2034 * C3.3.9 Load/store (immediate pre-indexed)
2035 * C3.3.12 Load/store (unscaled immediate)
2037 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2038 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2039 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2040 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2042 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2044 * V = 0 -> non-vector
2045 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2046 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2048 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
)
2050 int rt
= extract32(insn
, 0, 5);
2051 int rn
= extract32(insn
, 5, 5);
2052 int imm9
= sextract32(insn
, 12, 9);
2053 int opc
= extract32(insn
, 22, 2);
2054 int size
= extract32(insn
, 30, 2);
2055 int idx
= extract32(insn
, 10, 2);
2056 bool is_signed
= false;
2057 bool is_store
= false;
2058 bool is_extended
= false;
2059 bool is_unpriv
= (idx
== 2);
2060 bool is_vector
= extract32(insn
, 26, 1);
2067 size
|= (opc
& 2) << 1;
2068 if (size
> 4 || is_unpriv
) {
2069 unallocated_encoding(s
);
2072 is_store
= ((opc
& 1) == 0);
2073 if (!fp_access_check(s
)) {
2077 if (size
== 3 && opc
== 2) {
2078 /* PRFM - prefetch */
2080 unallocated_encoding(s
);
2085 if (opc
== 3 && size
> 1) {
2086 unallocated_encoding(s
);
2089 is_store
= (opc
== 0);
2090 is_signed
= opc
& (1<<1);
2091 is_extended
= (size
< 3) && (opc
& 1);
2111 gen_check_sp_alignment(s
);
2113 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2116 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2121 do_fp_st(s
, rt
, tcg_addr
, size
);
2123 do_fp_ld(s
, rt
, tcg_addr
, size
);
2126 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2127 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2130 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
);
2132 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2133 is_signed
, is_extended
, memidx
);
2138 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2140 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2142 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2147 * C3.3.10 Load/store (register offset)
2149 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2150 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2151 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2152 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2155 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2156 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2158 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2159 * opc<0>: 0 -> store, 1 -> load
2160 * V: 1 -> vector/simd
2161 * opt: extend encoding (see DecodeRegExtend)
2162 * S: if S=1 then scale (essentially index by sizeof(size))
2163 * Rt: register to transfer into/out of
2164 * Rn: address register or SP for base
2165 * Rm: offset register or ZR for offset
2167 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
)
2169 int rt
= extract32(insn
, 0, 5);
2170 int rn
= extract32(insn
, 5, 5);
2171 int shift
= extract32(insn
, 12, 1);
2172 int rm
= extract32(insn
, 16, 5);
2173 int opc
= extract32(insn
, 22, 2);
2174 int opt
= extract32(insn
, 13, 3);
2175 int size
= extract32(insn
, 30, 2);
2176 bool is_signed
= false;
2177 bool is_store
= false;
2178 bool is_extended
= false;
2179 bool is_vector
= extract32(insn
, 26, 1);
2184 if (extract32(opt
, 1, 1) == 0) {
2185 unallocated_encoding(s
);
2190 size
|= (opc
& 2) << 1;
2192 unallocated_encoding(s
);
2195 is_store
= !extract32(opc
, 0, 1);
2196 if (!fp_access_check(s
)) {
2200 if (size
== 3 && opc
== 2) {
2201 /* PRFM - prefetch */
2204 if (opc
== 3 && size
> 1) {
2205 unallocated_encoding(s
);
2208 is_store
= (opc
== 0);
2209 is_signed
= extract32(opc
, 1, 1);
2210 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2214 gen_check_sp_alignment(s
);
2216 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2218 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2219 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2221 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2225 do_fp_st(s
, rt
, tcg_addr
, size
);
2227 do_fp_ld(s
, rt
, tcg_addr
, size
);
2230 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2232 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2234 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2240 * C3.3.13 Load/store (unsigned immediate)
2242 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2243 * +----+-------+---+-----+-----+------------+-------+------+
2244 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2245 * +----+-------+---+-----+-----+------------+-------+------+
2248 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2249 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2251 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2252 * opc<0>: 0 -> store, 1 -> load
2253 * Rn: base address register (inc SP)
2254 * Rt: target register
2256 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
)
2258 int rt
= extract32(insn
, 0, 5);
2259 int rn
= extract32(insn
, 5, 5);
2260 unsigned int imm12
= extract32(insn
, 10, 12);
2261 bool is_vector
= extract32(insn
, 26, 1);
2262 int size
= extract32(insn
, 30, 2);
2263 int opc
= extract32(insn
, 22, 2);
2264 unsigned int offset
;
2269 bool is_signed
= false;
2270 bool is_extended
= false;
2273 size
|= (opc
& 2) << 1;
2275 unallocated_encoding(s
);
2278 is_store
= !extract32(opc
, 0, 1);
2279 if (!fp_access_check(s
)) {
2283 if (size
== 3 && opc
== 2) {
2284 /* PRFM - prefetch */
2287 if (opc
== 3 && size
> 1) {
2288 unallocated_encoding(s
);
2291 is_store
= (opc
== 0);
2292 is_signed
= extract32(opc
, 1, 1);
2293 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2297 gen_check_sp_alignment(s
);
2299 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2300 offset
= imm12
<< size
;
2301 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2305 do_fp_st(s
, rt
, tcg_addr
, size
);
2307 do_fp_ld(s
, rt
, tcg_addr
, size
);
2310 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2312 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2314 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2319 /* Load/store register (all forms) */
2320 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2322 switch (extract32(insn
, 24, 2)) {
2324 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2325 disas_ldst_reg_roffset(s
, insn
);
2327 /* Load/store register (unscaled immediate)
2328 * Load/store immediate pre/post-indexed
2329 * Load/store register unprivileged
2331 disas_ldst_reg_imm9(s
, insn
);
2335 disas_ldst_reg_unsigned_imm(s
, insn
);
2338 unallocated_encoding(s
);
2343 /* C3.3.1 AdvSIMD load/store multiple structures
2345 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2346 * +---+---+---------------+---+-------------+--------+------+------+------+
2347 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2348 * +---+---+---------------+---+-------------+--------+------+------+------+
2350 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2352 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2353 * +---+---+---------------+---+---+---------+--------+------+------+------+
2354 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2355 * +---+---+---------------+---+---+---------+--------+------+------+------+
2357 * Rt: first (or only) SIMD&FP register to be transferred
2358 * Rn: base address or SP
2359 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2361 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2363 int rt
= extract32(insn
, 0, 5);
2364 int rn
= extract32(insn
, 5, 5);
2365 int size
= extract32(insn
, 10, 2);
2366 int opcode
= extract32(insn
, 12, 4);
2367 bool is_store
= !extract32(insn
, 22, 1);
2368 bool is_postidx
= extract32(insn
, 23, 1);
2369 bool is_q
= extract32(insn
, 30, 1);
2370 TCGv_i64 tcg_addr
, tcg_rn
;
2372 int ebytes
= 1 << size
;
2373 int elements
= (is_q
? 128 : 64) / (8 << size
);
2374 int rpt
; /* num iterations */
2375 int selem
; /* structure elements */
2378 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2379 unallocated_encoding(s
);
2383 /* From the shared decode logic */
2414 unallocated_encoding(s
);
2418 if (size
== 3 && !is_q
&& selem
!= 1) {
2420 unallocated_encoding(s
);
2424 if (!fp_access_check(s
)) {
2429 gen_check_sp_alignment(s
);
2432 tcg_rn
= cpu_reg_sp(s
, rn
);
2433 tcg_addr
= tcg_temp_new_i64();
2434 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2436 for (r
= 0; r
< rpt
; r
++) {
2438 for (e
= 0; e
< elements
; e
++) {
2439 int tt
= (rt
+ r
) % 32;
2441 for (xs
= 0; xs
< selem
; xs
++) {
2443 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2445 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2447 /* For non-quad operations, setting a slice of the low
2448 * 64 bits of the register clears the high 64 bits (in
2449 * the ARM ARM pseudocode this is implicit in the fact
2450 * that 'rval' is a 64 bit wide variable). We optimize
2451 * by noticing that we only need to do this the first
2452 * time we touch a register.
2454 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2455 clear_vec_high(s
, tt
);
2458 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2465 int rm
= extract32(insn
, 16, 5);
2467 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2469 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2472 tcg_temp_free_i64(tcg_addr
);
2475 /* C3.3.3 AdvSIMD load/store single structure
2477 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2478 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2479 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2480 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2482 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2484 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2485 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2486 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2487 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2489 * Rt: first (or only) SIMD&FP register to be transferred
2490 * Rn: base address or SP
2491 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2492 * index = encoded in Q:S:size dependent on size
2494 * lane_size = encoded in R, opc
2495 * transfer width = encoded in opc, S, size
2497 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2499 int rt
= extract32(insn
, 0, 5);
2500 int rn
= extract32(insn
, 5, 5);
2501 int size
= extract32(insn
, 10, 2);
2502 int S
= extract32(insn
, 12, 1);
2503 int opc
= extract32(insn
, 13, 3);
2504 int R
= extract32(insn
, 21, 1);
2505 int is_load
= extract32(insn
, 22, 1);
2506 int is_postidx
= extract32(insn
, 23, 1);
2507 int is_q
= extract32(insn
, 30, 1);
2509 int scale
= extract32(opc
, 1, 2);
2510 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2511 bool replicate
= false;
2512 int index
= is_q
<< 3 | S
<< 2 | size
;
2514 TCGv_i64 tcg_addr
, tcg_rn
;
2518 if (!is_load
|| S
) {
2519 unallocated_encoding(s
);
2528 if (extract32(size
, 0, 1)) {
2529 unallocated_encoding(s
);
2535 if (extract32(size
, 1, 1)) {
2536 unallocated_encoding(s
);
2539 if (!extract32(size
, 0, 1)) {
2543 unallocated_encoding(s
);
2551 g_assert_not_reached();
2554 if (!fp_access_check(s
)) {
2558 ebytes
= 1 << scale
;
2561 gen_check_sp_alignment(s
);
2564 tcg_rn
= cpu_reg_sp(s
, rn
);
2565 tcg_addr
= tcg_temp_new_i64();
2566 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2568 for (xs
= 0; xs
< selem
; xs
++) {
2570 /* Load and replicate to all elements */
2572 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2574 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2575 get_mem_index(s
), MO_TE
+ scale
);
2578 mulconst
= 0x0101010101010101ULL
;
2581 mulconst
= 0x0001000100010001ULL
;
2584 mulconst
= 0x0000000100000001ULL
;
2590 g_assert_not_reached();
2593 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2595 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2597 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2599 clear_vec_high(s
, rt
);
2601 tcg_temp_free_i64(tcg_tmp
);
2603 /* Load/store one element per register */
2605 do_vec_ld(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2607 do_vec_st(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2610 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2615 int rm
= extract32(insn
, 16, 5);
2617 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2619 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2622 tcg_temp_free_i64(tcg_addr
);
2625 /* C3.3 Loads and stores */
2626 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2628 switch (extract32(insn
, 24, 6)) {
2629 case 0x08: /* Load/store exclusive */
2630 disas_ldst_excl(s
, insn
);
2632 case 0x18: case 0x1c: /* Load register (literal) */
2633 disas_ld_lit(s
, insn
);
2635 case 0x28: case 0x29:
2636 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2637 disas_ldst_pair(s
, insn
);
2639 case 0x38: case 0x39:
2640 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2641 disas_ldst_reg(s
, insn
);
2643 case 0x0c: /* AdvSIMD load/store multiple structures */
2644 disas_ldst_multiple_struct(s
, insn
);
2646 case 0x0d: /* AdvSIMD load/store single structure */
2647 disas_ldst_single_struct(s
, insn
);
2650 unallocated_encoding(s
);
2655 /* C3.4.6 PC-rel. addressing
2656 * 31 30 29 28 24 23 5 4 0
2657 * +----+-------+-----------+-------------------+------+
2658 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2659 * +----+-------+-----------+-------------------+------+
2661 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2663 unsigned int page
, rd
;
2667 page
= extract32(insn
, 31, 1);
2668 /* SignExtend(immhi:immlo) -> offset */
2669 offset
= ((int64_t)sextract32(insn
, 5, 19) << 2) | extract32(insn
, 29, 2);
2670 rd
= extract32(insn
, 0, 5);
2674 /* ADRP (page based) */
2679 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2683 * C3.4.1 Add/subtract (immediate)
2685 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2686 * +--+--+--+-----------+-----+-------------+-----+-----+
2687 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2688 * +--+--+--+-----------+-----+-------------+-----+-----+
2690 * sf: 0 -> 32bit, 1 -> 64bit
2691 * op: 0 -> add , 1 -> sub
2693 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2695 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2697 int rd
= extract32(insn
, 0, 5);
2698 int rn
= extract32(insn
, 5, 5);
2699 uint64_t imm
= extract32(insn
, 10, 12);
2700 int shift
= extract32(insn
, 22, 2);
2701 bool setflags
= extract32(insn
, 29, 1);
2702 bool sub_op
= extract32(insn
, 30, 1);
2703 bool is_64bit
= extract32(insn
, 31, 1);
2705 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2706 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2707 TCGv_i64 tcg_result
;
2716 unallocated_encoding(s
);
2720 tcg_result
= tcg_temp_new_i64();
2723 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2725 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2728 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2730 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2732 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2734 tcg_temp_free_i64(tcg_imm
);
2738 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2740 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2743 tcg_temp_free_i64(tcg_result
);
2746 /* The input should be a value in the bottom e bits (with higher
2747 * bits zero); returns that value replicated into every element
2748 * of size e in a 64 bit integer.
2750 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2760 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2761 static inline uint64_t bitmask64(unsigned int length
)
2763 assert(length
> 0 && length
<= 64);
2764 return ~0ULL >> (64 - length
);
2767 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2768 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2769 * value (ie should cause a guest UNDEF exception), and true if they are
2770 * valid, in which case the decoded bit pattern is written to result.
2772 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
2773 unsigned int imms
, unsigned int immr
)
2776 unsigned e
, levels
, s
, r
;
2779 assert(immn
< 2 && imms
< 64 && immr
< 64);
2781 /* The bit patterns we create here are 64 bit patterns which
2782 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2783 * 64 bits each. Each element contains the same value: a run
2784 * of between 1 and e-1 non-zero bits, rotated within the
2785 * element by between 0 and e-1 bits.
2787 * The element size and run length are encoded into immn (1 bit)
2788 * and imms (6 bits) as follows:
2789 * 64 bit elements: immn = 1, imms = <length of run - 1>
2790 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2791 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2792 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2793 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2794 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2795 * Notice that immn = 0, imms = 11111x is the only combination
2796 * not covered by one of the above options; this is reserved.
2797 * Further, <length of run - 1> all-ones is a reserved pattern.
2799 * In all cases the rotation is by immr % e (and immr is 6 bits).
2802 /* First determine the element size */
2803 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
2805 /* This is the immn == 0, imms == 0x11111x case */
2815 /* <length of run - 1> mustn't be all-ones. */
2819 /* Create the value of one element: s+1 set bits rotated
2820 * by r within the element (which is e bits wide)...
2822 mask
= bitmask64(s
+ 1);
2823 mask
= (mask
>> r
) | (mask
<< (e
- r
));
2824 /* ...then replicate the element over the whole 64 bit value */
2825 mask
= bitfield_replicate(mask
, e
);
2830 /* C3.4.4 Logical (immediate)
2831 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2832 * +----+-----+-------------+---+------+------+------+------+
2833 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2834 * +----+-----+-------------+---+------+------+------+------+
2836 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
2838 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
2839 TCGv_i64 tcg_rd
, tcg_rn
;
2841 bool is_and
= false;
2843 sf
= extract32(insn
, 31, 1);
2844 opc
= extract32(insn
, 29, 2);
2845 is_n
= extract32(insn
, 22, 1);
2846 immr
= extract32(insn
, 16, 6);
2847 imms
= extract32(insn
, 10, 6);
2848 rn
= extract32(insn
, 5, 5);
2849 rd
= extract32(insn
, 0, 5);
2852 unallocated_encoding(s
);
2856 if (opc
== 0x3) { /* ANDS */
2857 tcg_rd
= cpu_reg(s
, rd
);
2859 tcg_rd
= cpu_reg_sp(s
, rd
);
2861 tcg_rn
= cpu_reg(s
, rn
);
2863 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
2864 /* some immediate field values are reserved */
2865 unallocated_encoding(s
);
2870 wmask
&= 0xffffffff;
2874 case 0x3: /* ANDS */
2876 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
2880 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
2883 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
2886 assert(FALSE
); /* must handle all above */
2890 if (!sf
&& !is_and
) {
2891 /* zero extend final result; we know we can skip this for AND
2892 * since the immediate had the high 32 bits clear.
2894 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2897 if (opc
== 3) { /* ANDS */
2898 gen_logic_CC(sf
, tcg_rd
);
2903 * C3.4.5 Move wide (immediate)
2905 * 31 30 29 28 23 22 21 20 5 4 0
2906 * +--+-----+-------------+-----+----------------+------+
2907 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2908 * +--+-----+-------------+-----+----------------+------+
2910 * sf: 0 -> 32 bit, 1 -> 64 bit
2911 * opc: 00 -> N, 10 -> Z, 11 -> K
2912 * hw: shift/16 (0,16, and sf only 32, 48)
2914 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
2916 int rd
= extract32(insn
, 0, 5);
2917 uint64_t imm
= extract32(insn
, 5, 16);
2918 int sf
= extract32(insn
, 31, 1);
2919 int opc
= extract32(insn
, 29, 2);
2920 int pos
= extract32(insn
, 21, 2) << 4;
2921 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2924 if (!sf
&& (pos
>= 32)) {
2925 unallocated_encoding(s
);
2939 tcg_gen_movi_i64(tcg_rd
, imm
);
2942 tcg_imm
= tcg_const_i64(imm
);
2943 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
2944 tcg_temp_free_i64(tcg_imm
);
2946 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2950 unallocated_encoding(s
);
2956 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2957 * +----+-----+-------------+---+------+------+------+------+
2958 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2959 * +----+-----+-------------+---+------+------+------+------+
2961 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
2963 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
2964 TCGv_i64 tcg_rd
, tcg_tmp
;
2966 sf
= extract32(insn
, 31, 1);
2967 opc
= extract32(insn
, 29, 2);
2968 n
= extract32(insn
, 22, 1);
2969 ri
= extract32(insn
, 16, 6);
2970 si
= extract32(insn
, 10, 6);
2971 rn
= extract32(insn
, 5, 5);
2972 rd
= extract32(insn
, 0, 5);
2973 bitsize
= sf
? 64 : 32;
2975 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
2976 unallocated_encoding(s
);
2980 tcg_rd
= cpu_reg(s
, rd
);
2981 tcg_tmp
= read_cpu_reg(s
, rn
, sf
);
2983 /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
2985 if (opc
!= 1) { /* SBFM or UBFM */
2986 tcg_gen_movi_i64(tcg_rd
, 0);
2989 /* do the bit move operation */
2991 /* Wd<s-r:0> = Wn<s:r> */
2992 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
2994 len
= (si
- ri
) + 1;
2996 /* Wd<32+s-r,32-r> = Wn<s:0> */
3001 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3003 if (opc
== 0) { /* SBFM - sign extend the destination field */
3004 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
3005 tcg_gen_sari_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
3008 if (!sf
) { /* zero extend final result */
3009 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3014 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3015 * +----+------+-------------+---+----+------+--------+------+------+
3016 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3017 * +----+------+-------------+---+----+------+--------+------+------+
3019 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3021 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3023 sf
= extract32(insn
, 31, 1);
3024 n
= extract32(insn
, 22, 1);
3025 rm
= extract32(insn
, 16, 5);
3026 imm
= extract32(insn
, 10, 6);
3027 rn
= extract32(insn
, 5, 5);
3028 rd
= extract32(insn
, 0, 5);
3029 op21
= extract32(insn
, 29, 2);
3030 op0
= extract32(insn
, 21, 1);
3031 bitsize
= sf
? 64 : 32;
3033 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3034 unallocated_encoding(s
);
3036 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3038 tcg_rd
= cpu_reg(s
, rd
);
3041 /* OPTME: we can special case rm==rn as a rotate */
3042 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3043 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3044 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3045 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3046 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3048 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3051 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3052 * so an extract from bit 0 is a special case.
3055 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3057 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3064 /* C3.4 Data processing - immediate */
3065 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3067 switch (extract32(insn
, 23, 6)) {
3068 case 0x20: case 0x21: /* PC-rel. addressing */
3069 disas_pc_rel_adr(s
, insn
);
3071 case 0x22: case 0x23: /* Add/subtract (immediate) */
3072 disas_add_sub_imm(s
, insn
);
3074 case 0x24: /* Logical (immediate) */
3075 disas_logic_imm(s
, insn
);
3077 case 0x25: /* Move wide (immediate) */
3078 disas_movw_imm(s
, insn
);
3080 case 0x26: /* Bitfield */
3081 disas_bitfield(s
, insn
);
3083 case 0x27: /* Extract */
3084 disas_extract(s
, insn
);
3087 unallocated_encoding(s
);
3092 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3093 * Note that it is the caller's responsibility to ensure that the
3094 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3095 * mandated semantics for out of range shifts.
3097 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3098 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3100 switch (shift_type
) {
3101 case A64_SHIFT_TYPE_LSL
:
3102 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3104 case A64_SHIFT_TYPE_LSR
:
3105 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3107 case A64_SHIFT_TYPE_ASR
:
3109 tcg_gen_ext32s_i64(dst
, src
);
3111 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3113 case A64_SHIFT_TYPE_ROR
:
3115 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3118 t0
= tcg_temp_new_i32();
3119 t1
= tcg_temp_new_i32();
3120 tcg_gen_trunc_i64_i32(t0
, src
);
3121 tcg_gen_trunc_i64_i32(t1
, shift_amount
);
3122 tcg_gen_rotr_i32(t0
, t0
, t1
);
3123 tcg_gen_extu_i32_i64(dst
, t0
);
3124 tcg_temp_free_i32(t0
);
3125 tcg_temp_free_i32(t1
);
3129 assert(FALSE
); /* all shift types should be handled */
3133 if (!sf
) { /* zero extend final result */
3134 tcg_gen_ext32u_i64(dst
, dst
);
3138 /* Shift a TCGv src by immediate, put result in dst.
3139 * The shift amount must be in range (this should always be true as the
3140 * relevant instructions will UNDEF on bad shift immediates).
3142 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3143 enum a64_shift_type shift_type
, unsigned int shift_i
)
3145 assert(shift_i
< (sf
? 64 : 32));
3148 tcg_gen_mov_i64(dst
, src
);
3150 TCGv_i64 shift_const
;
3152 shift_const
= tcg_const_i64(shift_i
);
3153 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3154 tcg_temp_free_i64(shift_const
);
3158 /* C3.5.10 Logical (shifted register)
3159 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3160 * +----+-----+-----------+-------+---+------+--------+------+------+
3161 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3162 * +----+-----+-----------+-------+---+------+--------+------+------+
3164 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3166 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3167 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3169 sf
= extract32(insn
, 31, 1);
3170 opc
= extract32(insn
, 29, 2);
3171 shift_type
= extract32(insn
, 22, 2);
3172 invert
= extract32(insn
, 21, 1);
3173 rm
= extract32(insn
, 16, 5);
3174 shift_amount
= extract32(insn
, 10, 6);
3175 rn
= extract32(insn
, 5, 5);
3176 rd
= extract32(insn
, 0, 5);
3178 if (!sf
&& (shift_amount
& (1 << 5))) {
3179 unallocated_encoding(s
);
3183 tcg_rd
= cpu_reg(s
, rd
);
3185 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3186 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3187 * register-register MOV and MVN, so it is worth special casing.
3189 tcg_rm
= cpu_reg(s
, rm
);
3191 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3193 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3197 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3199 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3205 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3208 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3211 tcg_rn
= cpu_reg(s
, rn
);
3213 switch (opc
| (invert
<< 2)) {
3216 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3219 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3222 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3226 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3229 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3232 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3240 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3244 gen_logic_CC(sf
, tcg_rd
);
3249 * C3.5.1 Add/subtract (extended register)
3251 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3252 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3253 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3254 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3256 * sf: 0 -> 32bit, 1 -> 64bit
3257 * op: 0 -> add , 1 -> sub
3260 * option: extension type (see DecodeRegExtend)
3261 * imm3: optional shift to Rm
3263 * Rd = Rn + LSL(extend(Rm), amount)
3265 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3267 int rd
= extract32(insn
, 0, 5);
3268 int rn
= extract32(insn
, 5, 5);
3269 int imm3
= extract32(insn
, 10, 3);
3270 int option
= extract32(insn
, 13, 3);
3271 int rm
= extract32(insn
, 16, 5);
3272 bool setflags
= extract32(insn
, 29, 1);
3273 bool sub_op
= extract32(insn
, 30, 1);
3274 bool sf
= extract32(insn
, 31, 1);
3276 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3278 TCGv_i64 tcg_result
;
3281 unallocated_encoding(s
);
3285 /* non-flag setting ops may use SP */
3287 tcg_rd
= cpu_reg_sp(s
, rd
);
3289 tcg_rd
= cpu_reg(s
, rd
);
3291 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3293 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3294 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3296 tcg_result
= tcg_temp_new_i64();
3300 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3302 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3306 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3308 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3313 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3315 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3318 tcg_temp_free_i64(tcg_result
);
3322 * C3.5.2 Add/subtract (shifted register)
3324 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3325 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3326 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3327 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3329 * sf: 0 -> 32bit, 1 -> 64bit
3330 * op: 0 -> add , 1 -> sub
3332 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3333 * imm6: Shift amount to apply to Rm before the add/sub
3335 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3337 int rd
= extract32(insn
, 0, 5);
3338 int rn
= extract32(insn
, 5, 5);
3339 int imm6
= extract32(insn
, 10, 6);
3340 int rm
= extract32(insn
, 16, 5);
3341 int shift_type
= extract32(insn
, 22, 2);
3342 bool setflags
= extract32(insn
, 29, 1);
3343 bool sub_op
= extract32(insn
, 30, 1);
3344 bool sf
= extract32(insn
, 31, 1);
3346 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3347 TCGv_i64 tcg_rn
, tcg_rm
;
3348 TCGv_i64 tcg_result
;
3350 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3351 unallocated_encoding(s
);
3355 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3356 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3358 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3360 tcg_result
= tcg_temp_new_i64();
3364 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3366 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3370 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3372 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3377 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3379 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3382 tcg_temp_free_i64(tcg_result
);
3385 /* C3.5.9 Data-processing (3 source)
3387 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3388 +--+------+-----------+------+------+----+------+------+------+
3389 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3390 +--+------+-----------+------+------+----+------+------+------+
3393 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3395 int rd
= extract32(insn
, 0, 5);
3396 int rn
= extract32(insn
, 5, 5);
3397 int ra
= extract32(insn
, 10, 5);
3398 int rm
= extract32(insn
, 16, 5);
3399 int op_id
= (extract32(insn
, 29, 3) << 4) |
3400 (extract32(insn
, 21, 3) << 1) |
3401 extract32(insn
, 15, 1);
3402 bool sf
= extract32(insn
, 31, 1);
3403 bool is_sub
= extract32(op_id
, 0, 1);
3404 bool is_high
= extract32(op_id
, 2, 1);
3405 bool is_signed
= false;
3410 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3412 case 0x42: /* SMADDL */
3413 case 0x43: /* SMSUBL */
3414 case 0x44: /* SMULH */
3417 case 0x0: /* MADD (32bit) */
3418 case 0x1: /* MSUB (32bit) */
3419 case 0x40: /* MADD (64bit) */
3420 case 0x41: /* MSUB (64bit) */
3421 case 0x4a: /* UMADDL */
3422 case 0x4b: /* UMSUBL */
3423 case 0x4c: /* UMULH */
3426 unallocated_encoding(s
);
3431 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3432 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3433 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3434 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3437 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3439 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3442 tcg_temp_free_i64(low_bits
);
3446 tcg_op1
= tcg_temp_new_i64();
3447 tcg_op2
= tcg_temp_new_i64();
3448 tcg_tmp
= tcg_temp_new_i64();
3451 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3452 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3455 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3456 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3458 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3459 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3463 if (ra
== 31 && !is_sub
) {
3464 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3465 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3467 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3469 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3471 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3476 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3479 tcg_temp_free_i64(tcg_op1
);
3480 tcg_temp_free_i64(tcg_op2
);
3481 tcg_temp_free_i64(tcg_tmp
);
3484 /* C3.5.3 - Add/subtract (with carry)
3485 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3486 * +--+--+--+------------------------+------+---------+------+-----+
3487 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3488 * +--+--+--+------------------------+------+---------+------+-----+
3492 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3494 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3495 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3497 if (extract32(insn
, 10, 6) != 0) {
3498 unallocated_encoding(s
);
3502 sf
= extract32(insn
, 31, 1);
3503 op
= extract32(insn
, 30, 1);
3504 setflags
= extract32(insn
, 29, 1);
3505 rm
= extract32(insn
, 16, 5);
3506 rn
= extract32(insn
, 5, 5);
3507 rd
= extract32(insn
, 0, 5);
3509 tcg_rd
= cpu_reg(s
, rd
);
3510 tcg_rn
= cpu_reg(s
, rn
);
3513 tcg_y
= new_tmp_a64(s
);
3514 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3516 tcg_y
= cpu_reg(s
, rm
);
3520 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3522 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3526 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3527 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3528 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3529 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3530 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3533 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3535 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3536 int label_continue
= -1;
3537 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3539 if (!extract32(insn
, 29, 1)) {
3540 unallocated_encoding(s
);
3543 if (insn
& (1 << 10 | 1 << 4)) {
3544 unallocated_encoding(s
);
3547 sf
= extract32(insn
, 31, 1);
3548 op
= extract32(insn
, 30, 1);
3549 is_imm
= extract32(insn
, 11, 1);
3550 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3551 cond
= extract32(insn
, 12, 4);
3552 rn
= extract32(insn
, 5, 5);
3553 nzcv
= extract32(insn
, 0, 4);
3555 if (cond
< 0x0e) { /* not always */
3556 int label_match
= gen_new_label();
3557 label_continue
= gen_new_label();
3558 arm_gen_test_cc(cond
, label_match
);
3560 tcg_tmp
= tcg_temp_new_i64();
3561 tcg_gen_movi_i64(tcg_tmp
, nzcv
<< 28);
3562 gen_set_nzcv(tcg_tmp
);
3563 tcg_temp_free_i64(tcg_tmp
);
3564 tcg_gen_br(label_continue
);
3565 gen_set_label(label_match
);
3567 /* match, or condition is always */
3569 tcg_y
= new_tmp_a64(s
);
3570 tcg_gen_movi_i64(tcg_y
, y
);
3572 tcg_y
= cpu_reg(s
, y
);
3574 tcg_rn
= cpu_reg(s
, rn
);
3576 tcg_tmp
= tcg_temp_new_i64();
3578 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3580 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3582 tcg_temp_free_i64(tcg_tmp
);
3584 if (cond
< 0x0e) { /* continue */
3585 gen_set_label(label_continue
);
3589 /* C3.5.6 Conditional select
3590 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3591 * +----+----+---+-----------------+------+------+-----+------+------+
3592 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3593 * +----+----+---+-----------------+------+------+-----+------+------+
3595 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3597 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3598 TCGv_i64 tcg_rd
, tcg_src
;
3600 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3601 /* S == 1 or op2<1> == 1 */
3602 unallocated_encoding(s
);
3605 sf
= extract32(insn
, 31, 1);
3606 else_inv
= extract32(insn
, 30, 1);
3607 rm
= extract32(insn
, 16, 5);
3608 cond
= extract32(insn
, 12, 4);
3609 else_inc
= extract32(insn
, 10, 1);
3610 rn
= extract32(insn
, 5, 5);
3611 rd
= extract32(insn
, 0, 5);
3614 /* silly no-op write; until we use movcond we must special-case
3615 * this to avoid a dead temporary across basic blocks.
3620 tcg_rd
= cpu_reg(s
, rd
);
3622 if (cond
>= 0x0e) { /* condition "always" */
3623 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3624 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3626 /* OPTME: we could use movcond here, at the cost of duplicating
3627 * a lot of the arm_gen_test_cc() logic.
3629 int label_match
= gen_new_label();
3630 int label_continue
= gen_new_label();
3632 arm_gen_test_cc(cond
, label_match
);
3634 tcg_src
= cpu_reg(s
, rm
);
3636 if (else_inv
&& else_inc
) {
3637 tcg_gen_neg_i64(tcg_rd
, tcg_src
);
3638 } else if (else_inv
) {
3639 tcg_gen_not_i64(tcg_rd
, tcg_src
);
3640 } else if (else_inc
) {
3641 tcg_gen_addi_i64(tcg_rd
, tcg_src
, 1);
3643 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3646 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3648 tcg_gen_br(label_continue
);
3650 gen_set_label(label_match
);
3651 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3652 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3654 gen_set_label(label_continue
);
3658 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3659 unsigned int rn
, unsigned int rd
)
3661 TCGv_i64 tcg_rd
, tcg_rn
;
3662 tcg_rd
= cpu_reg(s
, rd
);
3663 tcg_rn
= cpu_reg(s
, rn
);
3666 gen_helper_clz64(tcg_rd
, tcg_rn
);
3668 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3669 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3670 gen_helper_clz(tcg_tmp32
, tcg_tmp32
);
3671 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3672 tcg_temp_free_i32(tcg_tmp32
);
3676 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3677 unsigned int rn
, unsigned int rd
)
3679 TCGv_i64 tcg_rd
, tcg_rn
;
3680 tcg_rd
= cpu_reg(s
, rd
);
3681 tcg_rn
= cpu_reg(s
, rn
);
3684 gen_helper_cls64(tcg_rd
, tcg_rn
);
3686 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3687 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3688 gen_helper_cls32(tcg_tmp32
, tcg_tmp32
);
3689 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3690 tcg_temp_free_i32(tcg_tmp32
);
3694 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3695 unsigned int rn
, unsigned int rd
)
3697 TCGv_i64 tcg_rd
, tcg_rn
;
3698 tcg_rd
= cpu_reg(s
, rd
);
3699 tcg_rn
= cpu_reg(s
, rn
);
3702 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3704 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3705 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3706 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3707 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3708 tcg_temp_free_i32(tcg_tmp32
);
3712 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3713 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
3714 unsigned int rn
, unsigned int rd
)
3717 unallocated_encoding(s
);
3720 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
3723 /* C5.6.149 REV with sf==0, opcode==2
3724 * C5.6.151 REV32 (sf==1, opcode==2)
3726 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
3727 unsigned int rn
, unsigned int rd
)
3729 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3732 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3733 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3735 /* bswap32_i64 requires zero high word */
3736 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
3737 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
3738 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3739 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
3740 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
3742 tcg_temp_free_i64(tcg_tmp
);
3744 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
3745 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
3749 /* C5.6.150 REV16 (opcode==1) */
3750 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
3751 unsigned int rn
, unsigned int rd
)
3753 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3754 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3755 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3757 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
3758 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
3760 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
3761 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3762 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3763 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
3766 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3767 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3768 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3769 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
3771 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
3772 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3773 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
3776 tcg_temp_free_i64(tcg_tmp
);
3779 /* C3.5.7 Data-processing (1 source)
3780 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3781 * +----+---+---+-----------------+---------+--------+------+------+
3782 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
3783 * +----+---+---+-----------------+---------+--------+------+------+
3785 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
3787 unsigned int sf
, opcode
, rn
, rd
;
3789 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
3790 unallocated_encoding(s
);
3794 sf
= extract32(insn
, 31, 1);
3795 opcode
= extract32(insn
, 10, 6);
3796 rn
= extract32(insn
, 5, 5);
3797 rd
= extract32(insn
, 0, 5);
3801 handle_rbit(s
, sf
, rn
, rd
);
3804 handle_rev16(s
, sf
, rn
, rd
);
3807 handle_rev32(s
, sf
, rn
, rd
);
3810 handle_rev64(s
, sf
, rn
, rd
);
3813 handle_clz(s
, sf
, rn
, rd
);
3816 handle_cls(s
, sf
, rn
, rd
);
3821 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
3822 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3824 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
3825 tcg_rd
= cpu_reg(s
, rd
);
3827 if (!sf
&& is_signed
) {
3828 tcg_n
= new_tmp_a64(s
);
3829 tcg_m
= new_tmp_a64(s
);
3830 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
3831 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
3833 tcg_n
= read_cpu_reg(s
, rn
, sf
);
3834 tcg_m
= read_cpu_reg(s
, rm
, sf
);
3838 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
3840 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
3843 if (!sf
) { /* zero extend final result */
3844 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3848 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
3849 static void handle_shift_reg(DisasContext
*s
,
3850 enum a64_shift_type shift_type
, unsigned int sf
,
3851 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3853 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
3854 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3855 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3857 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
3858 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
3859 tcg_temp_free_i64(tcg_shift
);
3862 /* CRC32[BHWX], CRC32C[BHWX] */
3863 static void handle_crc32(DisasContext
*s
,
3864 unsigned int sf
, unsigned int sz
, bool crc32c
,
3865 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3867 TCGv_i64 tcg_acc
, tcg_val
;
3870 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
3871 || (sf
== 1 && sz
!= 3)
3872 || (sf
== 0 && sz
== 3)) {
3873 unallocated_encoding(s
);
3878 tcg_val
= cpu_reg(s
, rm
);
3892 g_assert_not_reached();
3894 tcg_val
= new_tmp_a64(s
);
3895 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
3898 tcg_acc
= cpu_reg(s
, rn
);
3899 tcg_bytes
= tcg_const_i32(1 << sz
);
3902 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
3904 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
3907 tcg_temp_free_i32(tcg_bytes
);
3910 /* C3.5.8 Data-processing (2 source)
3911 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3912 * +----+---+---+-----------------+------+--------+------+------+
3913 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
3914 * +----+---+---+-----------------+------+--------+------+------+
3916 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
3918 unsigned int sf
, rm
, opcode
, rn
, rd
;
3919 sf
= extract32(insn
, 31, 1);
3920 rm
= extract32(insn
, 16, 5);
3921 opcode
= extract32(insn
, 10, 6);
3922 rn
= extract32(insn
, 5, 5);
3923 rd
= extract32(insn
, 0, 5);
3925 if (extract32(insn
, 29, 1)) {
3926 unallocated_encoding(s
);
3932 handle_div(s
, false, sf
, rm
, rn
, rd
);
3935 handle_div(s
, true, sf
, rm
, rn
, rd
);
3938 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
3941 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
3944 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
3947 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
3956 case 23: /* CRC32 */
3958 int sz
= extract32(opcode
, 0, 2);
3959 bool crc32c
= extract32(opcode
, 2, 1);
3960 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
3964 unallocated_encoding(s
);
3969 /* C3.5 Data processing - register */
3970 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
3972 switch (extract32(insn
, 24, 5)) {
3973 case 0x0a: /* Logical (shifted register) */
3974 disas_logic_reg(s
, insn
);
3976 case 0x0b: /* Add/subtract */
3977 if (insn
& (1 << 21)) { /* (extended register) */
3978 disas_add_sub_ext_reg(s
, insn
);
3980 disas_add_sub_reg(s
, insn
);
3983 case 0x1b: /* Data-processing (3 source) */
3984 disas_data_proc_3src(s
, insn
);
3987 switch (extract32(insn
, 21, 3)) {
3988 case 0x0: /* Add/subtract (with carry) */
3989 disas_adc_sbc(s
, insn
);
3991 case 0x2: /* Conditional compare */
3992 disas_cc(s
, insn
); /* both imm and reg forms */
3994 case 0x4: /* Conditional select */
3995 disas_cond_select(s
, insn
);
3997 case 0x6: /* Data-processing */
3998 if (insn
& (1 << 30)) { /* (1 source) */
3999 disas_data_proc_1src(s
, insn
);
4000 } else { /* (2 source) */
4001 disas_data_proc_2src(s
, insn
);
4005 unallocated_encoding(s
);
4010 unallocated_encoding(s
);
4015 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
4016 unsigned int rn
, unsigned int rm
,
4017 bool cmp_with_zero
, bool signal_all_nans
)
4019 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4020 TCGv_ptr fpst
= get_fpstatus_ptr();
4023 TCGv_i64 tcg_vn
, tcg_vm
;
4025 tcg_vn
= read_fp_dreg(s
, rn
);
4026 if (cmp_with_zero
) {
4027 tcg_vm
= tcg_const_i64(0);
4029 tcg_vm
= read_fp_dreg(s
, rm
);
4031 if (signal_all_nans
) {
4032 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4034 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4036 tcg_temp_free_i64(tcg_vn
);
4037 tcg_temp_free_i64(tcg_vm
);
4039 TCGv_i32 tcg_vn
, tcg_vm
;
4041 tcg_vn
= read_fp_sreg(s
, rn
);
4042 if (cmp_with_zero
) {
4043 tcg_vm
= tcg_const_i32(0);
4045 tcg_vm
= read_fp_sreg(s
, rm
);
4047 if (signal_all_nans
) {
4048 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4050 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4052 tcg_temp_free_i32(tcg_vn
);
4053 tcg_temp_free_i32(tcg_vm
);
4056 tcg_temp_free_ptr(fpst
);
4058 gen_set_nzcv(tcg_flags
);
4060 tcg_temp_free_i64(tcg_flags
);
4063 /* C3.6.22 Floating point compare
4064 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4065 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4066 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4067 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4069 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4071 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4073 mos
= extract32(insn
, 29, 3);
4074 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4075 rm
= extract32(insn
, 16, 5);
4076 op
= extract32(insn
, 14, 2);
4077 rn
= extract32(insn
, 5, 5);
4078 opc
= extract32(insn
, 3, 2);
4079 op2r
= extract32(insn
, 0, 3);
4081 if (mos
|| op
|| op2r
|| type
> 1) {
4082 unallocated_encoding(s
);
4086 if (!fp_access_check(s
)) {
4090 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4093 /* C3.6.23 Floating point conditional compare
4094 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4095 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4096 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4097 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4099 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4101 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4103 int label_continue
= -1;
4105 mos
= extract32(insn
, 29, 3);
4106 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4107 rm
= extract32(insn
, 16, 5);
4108 cond
= extract32(insn
, 12, 4);
4109 rn
= extract32(insn
, 5, 5);
4110 op
= extract32(insn
, 4, 1);
4111 nzcv
= extract32(insn
, 0, 4);
4113 if (mos
|| type
> 1) {
4114 unallocated_encoding(s
);
4118 if (!fp_access_check(s
)) {
4122 if (cond
< 0x0e) { /* not always */
4123 int label_match
= gen_new_label();
4124 label_continue
= gen_new_label();
4125 arm_gen_test_cc(cond
, label_match
);
4127 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4128 gen_set_nzcv(tcg_flags
);
4129 tcg_temp_free_i64(tcg_flags
);
4130 tcg_gen_br(label_continue
);
4131 gen_set_label(label_match
);
4134 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4137 gen_set_label(label_continue
);
4141 /* copy src FP register to dst FP register; type specifies single or double */
4142 static void gen_mov_fp2fp(DisasContext
*s
, int type
, int dst
, int src
)
4145 TCGv_i64 v
= read_fp_dreg(s
, src
);
4146 write_fp_dreg(s
, dst
, v
);
4147 tcg_temp_free_i64(v
);
4149 TCGv_i32 v
= read_fp_sreg(s
, src
);
4150 write_fp_sreg(s
, dst
, v
);
4151 tcg_temp_free_i32(v
);
4155 /* C3.6.24 Floating point conditional select
4156 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4157 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4158 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4159 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4161 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4163 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4164 int label_continue
= -1;
4166 mos
= extract32(insn
, 29, 3);
4167 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4168 rm
= extract32(insn
, 16, 5);
4169 cond
= extract32(insn
, 12, 4);
4170 rn
= extract32(insn
, 5, 5);
4171 rd
= extract32(insn
, 0, 5);
4173 if (mos
|| type
> 1) {
4174 unallocated_encoding(s
);
4178 if (!fp_access_check(s
)) {
4182 if (cond
< 0x0e) { /* not always */
4183 int label_match
= gen_new_label();
4184 label_continue
= gen_new_label();
4185 arm_gen_test_cc(cond
, label_match
);
4187 gen_mov_fp2fp(s
, type
, rd
, rm
);
4188 tcg_gen_br(label_continue
);
4189 gen_set_label(label_match
);
4192 gen_mov_fp2fp(s
, type
, rd
, rn
);
4194 if (cond
< 0x0e) { /* continue */
4195 gen_set_label(label_continue
);
4199 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4200 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4206 fpst
= get_fpstatus_ptr();
4207 tcg_op
= read_fp_sreg(s
, rn
);
4208 tcg_res
= tcg_temp_new_i32();
4211 case 0x0: /* FMOV */
4212 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4214 case 0x1: /* FABS */
4215 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4217 case 0x2: /* FNEG */
4218 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4220 case 0x3: /* FSQRT */
4221 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4223 case 0x8: /* FRINTN */
4224 case 0x9: /* FRINTP */
4225 case 0xa: /* FRINTM */
4226 case 0xb: /* FRINTZ */
4227 case 0xc: /* FRINTA */
4229 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4231 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4232 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4234 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4235 tcg_temp_free_i32(tcg_rmode
);
4238 case 0xe: /* FRINTX */
4239 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4241 case 0xf: /* FRINTI */
4242 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4248 write_fp_sreg(s
, rd
, tcg_res
);
4250 tcg_temp_free_ptr(fpst
);
4251 tcg_temp_free_i32(tcg_op
);
4252 tcg_temp_free_i32(tcg_res
);
4255 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4256 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4262 fpst
= get_fpstatus_ptr();
4263 tcg_op
= read_fp_dreg(s
, rn
);
4264 tcg_res
= tcg_temp_new_i64();
4267 case 0x0: /* FMOV */
4268 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4270 case 0x1: /* FABS */
4271 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4273 case 0x2: /* FNEG */
4274 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4276 case 0x3: /* FSQRT */
4277 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4279 case 0x8: /* FRINTN */
4280 case 0x9: /* FRINTP */
4281 case 0xa: /* FRINTM */
4282 case 0xb: /* FRINTZ */
4283 case 0xc: /* FRINTA */
4285 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4287 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4288 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4290 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4291 tcg_temp_free_i32(tcg_rmode
);
4294 case 0xe: /* FRINTX */
4295 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4297 case 0xf: /* FRINTI */
4298 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4304 write_fp_dreg(s
, rd
, tcg_res
);
4306 tcg_temp_free_ptr(fpst
);
4307 tcg_temp_free_i64(tcg_op
);
4308 tcg_temp_free_i64(tcg_res
);
4311 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4312 int rd
, int rn
, int dtype
, int ntype
)
4317 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4319 /* Single to double */
4320 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4321 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4322 write_fp_dreg(s
, rd
, tcg_rd
);
4323 tcg_temp_free_i64(tcg_rd
);
4325 /* Single to half */
4326 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4327 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4328 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4329 write_fp_sreg(s
, rd
, tcg_rd
);
4330 tcg_temp_free_i32(tcg_rd
);
4332 tcg_temp_free_i32(tcg_rn
);
4337 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4338 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4340 /* Double to single */
4341 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4343 /* Double to half */
4344 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4345 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4347 write_fp_sreg(s
, rd
, tcg_rd
);
4348 tcg_temp_free_i32(tcg_rd
);
4349 tcg_temp_free_i64(tcg_rn
);
4354 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4355 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4357 /* Half to single */
4358 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4359 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4360 write_fp_sreg(s
, rd
, tcg_rd
);
4361 tcg_temp_free_i32(tcg_rd
);
4363 /* Half to double */
4364 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4365 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4366 write_fp_dreg(s
, rd
, tcg_rd
);
4367 tcg_temp_free_i64(tcg_rd
);
4369 tcg_temp_free_i32(tcg_rn
);
4377 /* C3.6.25 Floating point data-processing (1 source)
4378 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4379 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4380 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4381 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4383 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4385 int type
= extract32(insn
, 22, 2);
4386 int opcode
= extract32(insn
, 15, 6);
4387 int rn
= extract32(insn
, 5, 5);
4388 int rd
= extract32(insn
, 0, 5);
4391 case 0x4: case 0x5: case 0x7:
4393 /* FCVT between half, single and double precision */
4394 int dtype
= extract32(opcode
, 0, 2);
4395 if (type
== 2 || dtype
== type
) {
4396 unallocated_encoding(s
);
4399 if (!fp_access_check(s
)) {
4403 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4409 /* 32-to-32 and 64-to-64 ops */
4412 if (!fp_access_check(s
)) {
4416 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4419 if (!fp_access_check(s
)) {
4423 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4426 unallocated_encoding(s
);
4430 unallocated_encoding(s
);
4435 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4436 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4437 int rd
, int rn
, int rm
)
4444 tcg_res
= tcg_temp_new_i32();
4445 fpst
= get_fpstatus_ptr();
4446 tcg_op1
= read_fp_sreg(s
, rn
);
4447 tcg_op2
= read_fp_sreg(s
, rm
);
4450 case 0x0: /* FMUL */
4451 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4453 case 0x1: /* FDIV */
4454 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4456 case 0x2: /* FADD */
4457 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4459 case 0x3: /* FSUB */
4460 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4462 case 0x4: /* FMAX */
4463 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4465 case 0x5: /* FMIN */
4466 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4468 case 0x6: /* FMAXNM */
4469 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4471 case 0x7: /* FMINNM */
4472 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4474 case 0x8: /* FNMUL */
4475 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4476 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4480 write_fp_sreg(s
, rd
, tcg_res
);
4482 tcg_temp_free_ptr(fpst
);
4483 tcg_temp_free_i32(tcg_op1
);
4484 tcg_temp_free_i32(tcg_op2
);
4485 tcg_temp_free_i32(tcg_res
);
4488 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4489 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4490 int rd
, int rn
, int rm
)
4497 tcg_res
= tcg_temp_new_i64();
4498 fpst
= get_fpstatus_ptr();
4499 tcg_op1
= read_fp_dreg(s
, rn
);
4500 tcg_op2
= read_fp_dreg(s
, rm
);
4503 case 0x0: /* FMUL */
4504 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4506 case 0x1: /* FDIV */
4507 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4509 case 0x2: /* FADD */
4510 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4512 case 0x3: /* FSUB */
4513 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4515 case 0x4: /* FMAX */
4516 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4518 case 0x5: /* FMIN */
4519 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4521 case 0x6: /* FMAXNM */
4522 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4524 case 0x7: /* FMINNM */
4525 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4527 case 0x8: /* FNMUL */
4528 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4529 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4533 write_fp_dreg(s
, rd
, tcg_res
);
4535 tcg_temp_free_ptr(fpst
);
4536 tcg_temp_free_i64(tcg_op1
);
4537 tcg_temp_free_i64(tcg_op2
);
4538 tcg_temp_free_i64(tcg_res
);
4541 /* C3.6.26 Floating point data-processing (2 source)
4542 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4543 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4544 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4545 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4547 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4549 int type
= extract32(insn
, 22, 2);
4550 int rd
= extract32(insn
, 0, 5);
4551 int rn
= extract32(insn
, 5, 5);
4552 int rm
= extract32(insn
, 16, 5);
4553 int opcode
= extract32(insn
, 12, 4);
4556 unallocated_encoding(s
);
4562 if (!fp_access_check(s
)) {
4565 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4568 if (!fp_access_check(s
)) {
4571 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4574 unallocated_encoding(s
);
4578 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4579 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4580 int rd
, int rn
, int rm
, int ra
)
4582 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4583 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4584 TCGv_ptr fpst
= get_fpstatus_ptr();
4586 tcg_op1
= read_fp_sreg(s
, rn
);
4587 tcg_op2
= read_fp_sreg(s
, rm
);
4588 tcg_op3
= read_fp_sreg(s
, ra
);
4590 /* These are fused multiply-add, and must be done as one
4591 * floating point operation with no rounding between the
4592 * multiplication and addition steps.
4593 * NB that doing the negations here as separate steps is
4594 * correct : an input NaN should come out with its sign bit
4595 * flipped if it is a negated-input.
4598 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4602 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4605 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4607 write_fp_sreg(s
, rd
, tcg_res
);
4609 tcg_temp_free_ptr(fpst
);
4610 tcg_temp_free_i32(tcg_op1
);
4611 tcg_temp_free_i32(tcg_op2
);
4612 tcg_temp_free_i32(tcg_op3
);
4613 tcg_temp_free_i32(tcg_res
);
4616 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4617 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4618 int rd
, int rn
, int rm
, int ra
)
4620 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4621 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4622 TCGv_ptr fpst
= get_fpstatus_ptr();
4624 tcg_op1
= read_fp_dreg(s
, rn
);
4625 tcg_op2
= read_fp_dreg(s
, rm
);
4626 tcg_op3
= read_fp_dreg(s
, ra
);
4628 /* These are fused multiply-add, and must be done as one
4629 * floating point operation with no rounding between the
4630 * multiplication and addition steps.
4631 * NB that doing the negations here as separate steps is
4632 * correct : an input NaN should come out with its sign bit
4633 * flipped if it is a negated-input.
4636 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4640 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4643 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4645 write_fp_dreg(s
, rd
, tcg_res
);
4647 tcg_temp_free_ptr(fpst
);
4648 tcg_temp_free_i64(tcg_op1
);
4649 tcg_temp_free_i64(tcg_op2
);
4650 tcg_temp_free_i64(tcg_op3
);
4651 tcg_temp_free_i64(tcg_res
);
4654 /* C3.6.27 Floating point data-processing (3 source)
4655 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4656 * +---+---+---+-----------+------+----+------+----+------+------+------+
4657 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4658 * +---+---+---+-----------+------+----+------+----+------+------+------+
4660 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4662 int type
= extract32(insn
, 22, 2);
4663 int rd
= extract32(insn
, 0, 5);
4664 int rn
= extract32(insn
, 5, 5);
4665 int ra
= extract32(insn
, 10, 5);
4666 int rm
= extract32(insn
, 16, 5);
4667 bool o0
= extract32(insn
, 15, 1);
4668 bool o1
= extract32(insn
, 21, 1);
4672 if (!fp_access_check(s
)) {
4675 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4678 if (!fp_access_check(s
)) {
4681 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4684 unallocated_encoding(s
);
4688 /* C3.6.28 Floating point immediate
4689 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4690 * +---+---+---+-----------+------+---+------------+-------+------+------+
4691 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4692 * +---+---+---+-----------+------+---+------------+-------+------+------+
4694 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4696 int rd
= extract32(insn
, 0, 5);
4697 int imm8
= extract32(insn
, 13, 8);
4698 int is_double
= extract32(insn
, 22, 2);
4702 if (is_double
> 1) {
4703 unallocated_encoding(s
);
4707 if (!fp_access_check(s
)) {
4711 /* The imm8 encodes the sign bit, enough bits to represent
4712 * an exponent in the range 01....1xx to 10....0xx,
4713 * and the most significant 4 bits of the mantissa; see
4714 * VFPExpandImm() in the v8 ARM ARM.
4717 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4718 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4719 extract32(imm8
, 0, 6);
4722 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4723 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
4724 (extract32(imm8
, 0, 6) << 3);
4728 tcg_res
= tcg_const_i64(imm
);
4729 write_fp_dreg(s
, rd
, tcg_res
);
4730 tcg_temp_free_i64(tcg_res
);
4733 /* Handle floating point <=> fixed point conversions. Note that we can
4734 * also deal with fp <=> integer conversions as a special case (scale == 64)
4735 * OPTME: consider handling that special case specially or at least skipping
4736 * the call to scalbn in the helpers for zero shifts.
4738 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
4739 bool itof
, int rmode
, int scale
, int sf
, int type
)
4741 bool is_signed
= !(opcode
& 1);
4742 bool is_double
= type
;
4743 TCGv_ptr tcg_fpstatus
;
4746 tcg_fpstatus
= get_fpstatus_ptr();
4748 tcg_shift
= tcg_const_i32(64 - scale
);
4751 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
4753 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
4756 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
4758 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
4761 tcg_int
= tcg_extend
;
4765 TCGv_i64 tcg_double
= tcg_temp_new_i64();
4767 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
4768 tcg_shift
, tcg_fpstatus
);
4770 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
4771 tcg_shift
, tcg_fpstatus
);
4773 write_fp_dreg(s
, rd
, tcg_double
);
4774 tcg_temp_free_i64(tcg_double
);
4776 TCGv_i32 tcg_single
= tcg_temp_new_i32();
4778 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
4779 tcg_shift
, tcg_fpstatus
);
4781 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
4782 tcg_shift
, tcg_fpstatus
);
4784 write_fp_sreg(s
, rd
, tcg_single
);
4785 tcg_temp_free_i32(tcg_single
);
4788 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
4791 if (extract32(opcode
, 2, 1)) {
4792 /* There are too many rounding modes to all fit into rmode,
4793 * so FCVTA[US] is a special case.
4795 rmode
= FPROUNDING_TIEAWAY
;
4798 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
4800 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4803 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
4806 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
4807 tcg_shift
, tcg_fpstatus
);
4809 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
4810 tcg_shift
, tcg_fpstatus
);
4814 gen_helper_vfp_tould(tcg_int
, tcg_double
,
4815 tcg_shift
, tcg_fpstatus
);
4817 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
4818 tcg_shift
, tcg_fpstatus
);
4821 tcg_temp_free_i64(tcg_double
);
4823 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
4826 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
4827 tcg_shift
, tcg_fpstatus
);
4829 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
4830 tcg_shift
, tcg_fpstatus
);
4833 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
4835 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
4836 tcg_shift
, tcg_fpstatus
);
4838 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
4839 tcg_shift
, tcg_fpstatus
);
4841 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
4842 tcg_temp_free_i32(tcg_dest
);
4844 tcg_temp_free_i32(tcg_single
);
4847 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4848 tcg_temp_free_i32(tcg_rmode
);
4851 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
4855 tcg_temp_free_ptr(tcg_fpstatus
);
4856 tcg_temp_free_i32(tcg_shift
);
4859 /* C3.6.29 Floating point <-> fixed point conversions
4860 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4861 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4862 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
4863 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4865 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
4867 int rd
= extract32(insn
, 0, 5);
4868 int rn
= extract32(insn
, 5, 5);
4869 int scale
= extract32(insn
, 10, 6);
4870 int opcode
= extract32(insn
, 16, 3);
4871 int rmode
= extract32(insn
, 19, 2);
4872 int type
= extract32(insn
, 22, 2);
4873 bool sbit
= extract32(insn
, 29, 1);
4874 bool sf
= extract32(insn
, 31, 1);
4877 if (sbit
|| (type
> 1)
4878 || (!sf
&& scale
< 32)) {
4879 unallocated_encoding(s
);
4883 switch ((rmode
<< 3) | opcode
) {
4884 case 0x2: /* SCVTF */
4885 case 0x3: /* UCVTF */
4888 case 0x18: /* FCVTZS */
4889 case 0x19: /* FCVTZU */
4893 unallocated_encoding(s
);
4897 if (!fp_access_check(s
)) {
4901 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
4904 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
4906 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
4907 * without conversion.
4911 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4917 TCGv_i64 tmp
= tcg_temp_new_i64();
4918 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
4919 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
4920 tcg_gen_movi_i64(tmp
, 0);
4921 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4922 tcg_temp_free_i64(tmp
);
4928 TCGv_i64 tmp
= tcg_const_i64(0);
4929 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
4930 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4931 tcg_temp_free_i64(tmp
);
4935 /* 64 bit to top half. */
4936 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4940 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4945 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
4949 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
4952 /* 64 bits from top half */
4953 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
4959 /* C3.6.30 Floating point <-> integer conversions
4960 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4961 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4962 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
4963 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4965 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
4967 int rd
= extract32(insn
, 0, 5);
4968 int rn
= extract32(insn
, 5, 5);
4969 int opcode
= extract32(insn
, 16, 3);
4970 int rmode
= extract32(insn
, 19, 2);
4971 int type
= extract32(insn
, 22, 2);
4972 bool sbit
= extract32(insn
, 29, 1);
4973 bool sf
= extract32(insn
, 31, 1);
4976 unallocated_encoding(s
);
4982 bool itof
= opcode
& 1;
4985 unallocated_encoding(s
);
4989 switch (sf
<< 3 | type
<< 1 | rmode
) {
4990 case 0x0: /* 32 bit */
4991 case 0xa: /* 64 bit */
4992 case 0xd: /* 64 bit to top half of quad */
4995 /* all other sf/type/rmode combinations are invalid */
4996 unallocated_encoding(s
);
5000 if (!fp_access_check(s
)) {
5003 handle_fmov(s
, rd
, rn
, type
, itof
);
5005 /* actual FP conversions */
5006 bool itof
= extract32(opcode
, 1, 1);
5008 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
5009 unallocated_encoding(s
);
5013 if (!fp_access_check(s
)) {
5016 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
5020 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5021 * 31 30 29 28 25 24 0
5022 * +---+---+---+---------+-----------------------------+
5023 * | | 0 | | 1 1 1 1 | |
5024 * +---+---+---+---------+-----------------------------+
5026 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
5028 if (extract32(insn
, 24, 1)) {
5029 /* Floating point data-processing (3 source) */
5030 disas_fp_3src(s
, insn
);
5031 } else if (extract32(insn
, 21, 1) == 0) {
5032 /* Floating point to fixed point conversions */
5033 disas_fp_fixed_conv(s
, insn
);
5035 switch (extract32(insn
, 10, 2)) {
5037 /* Floating point conditional compare */
5038 disas_fp_ccomp(s
, insn
);
5041 /* Floating point data-processing (2 source) */
5042 disas_fp_2src(s
, insn
);
5045 /* Floating point conditional select */
5046 disas_fp_csel(s
, insn
);
5049 switch (ctz32(extract32(insn
, 12, 4))) {
5050 case 0: /* [15:12] == xxx1 */
5051 /* Floating point immediate */
5052 disas_fp_imm(s
, insn
);
5054 case 1: /* [15:12] == xx10 */
5055 /* Floating point compare */
5056 disas_fp_compare(s
, insn
);
5058 case 2: /* [15:12] == x100 */
5059 /* Floating point data-processing (1 source) */
5060 disas_fp_1src(s
, insn
);
5062 case 3: /* [15:12] == 1000 */
5063 unallocated_encoding(s
);
5065 default: /* [15:12] == 0000 */
5066 /* Floating point <-> integer conversions */
5067 disas_fp_int_conv(s
, insn
);
5075 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5078 /* Extract 64 bits from the middle of two concatenated 64 bit
5079 * vector register slices left:right. The extracted bits start
5080 * at 'pos' bits into the right (least significant) side.
5081 * We return the result in tcg_right, and guarantee not to
5084 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5085 assert(pos
> 0 && pos
< 64);
5087 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5088 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5089 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5091 tcg_temp_free_i64(tcg_tmp
);
5095 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5096 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5097 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5098 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5100 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5102 int is_q
= extract32(insn
, 30, 1);
5103 int op2
= extract32(insn
, 22, 2);
5104 int imm4
= extract32(insn
, 11, 4);
5105 int rm
= extract32(insn
, 16, 5);
5106 int rn
= extract32(insn
, 5, 5);
5107 int rd
= extract32(insn
, 0, 5);
5108 int pos
= imm4
<< 3;
5109 TCGv_i64 tcg_resl
, tcg_resh
;
5111 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5112 unallocated_encoding(s
);
5116 if (!fp_access_check(s
)) {
5120 tcg_resh
= tcg_temp_new_i64();
5121 tcg_resl
= tcg_temp_new_i64();
5123 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5124 * either extracting 128 bits from a 128:128 concatenation, or
5125 * extracting 64 bits from a 64:64 concatenation.
5128 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5130 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5131 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5133 tcg_gen_movi_i64(tcg_resh
, 0);
5140 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5141 EltPosns
*elt
= eltposns
;
5148 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5150 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5153 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5154 tcg_hh
= tcg_temp_new_i64();
5155 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5156 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5157 tcg_temp_free_i64(tcg_hh
);
5161 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5162 tcg_temp_free_i64(tcg_resl
);
5163 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5164 tcg_temp_free_i64(tcg_resh
);
5168 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5169 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5170 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5171 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5173 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5175 int op2
= extract32(insn
, 22, 2);
5176 int is_q
= extract32(insn
, 30, 1);
5177 int rm
= extract32(insn
, 16, 5);
5178 int rn
= extract32(insn
, 5, 5);
5179 int rd
= extract32(insn
, 0, 5);
5180 int is_tblx
= extract32(insn
, 12, 1);
5181 int len
= extract32(insn
, 13, 2);
5182 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5183 TCGv_i32 tcg_regno
, tcg_numregs
;
5186 unallocated_encoding(s
);
5190 if (!fp_access_check(s
)) {
5194 /* This does a table lookup: for every byte element in the input
5195 * we index into a table formed from up to four vector registers,
5196 * and then the output is the result of the lookups. Our helper
5197 * function does the lookup operation for a single 64 bit part of
5200 tcg_resl
= tcg_temp_new_i64();
5201 tcg_resh
= tcg_temp_new_i64();
5204 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5206 tcg_gen_movi_i64(tcg_resl
, 0);
5208 if (is_tblx
&& is_q
) {
5209 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5211 tcg_gen_movi_i64(tcg_resh
, 0);
5214 tcg_idx
= tcg_temp_new_i64();
5215 tcg_regno
= tcg_const_i32(rn
);
5216 tcg_numregs
= tcg_const_i32(len
+ 1);
5217 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5218 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5219 tcg_regno
, tcg_numregs
);
5221 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5222 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5223 tcg_regno
, tcg_numregs
);
5225 tcg_temp_free_i64(tcg_idx
);
5226 tcg_temp_free_i32(tcg_regno
);
5227 tcg_temp_free_i32(tcg_numregs
);
5229 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5230 tcg_temp_free_i64(tcg_resl
);
5231 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5232 tcg_temp_free_i64(tcg_resh
);
5235 /* C3.6.3 ZIP/UZP/TRN
5236 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5237 * +---+---+-------------+------+---+------+---+------------------+------+
5238 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5239 * +---+---+-------------+------+---+------+---+------------------+------+
5241 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5243 int rd
= extract32(insn
, 0, 5);
5244 int rn
= extract32(insn
, 5, 5);
5245 int rm
= extract32(insn
, 16, 5);
5246 int size
= extract32(insn
, 22, 2);
5247 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5248 * bit 2 indicates 1 vs 2 variant of the insn.
5250 int opcode
= extract32(insn
, 12, 2);
5251 bool part
= extract32(insn
, 14, 1);
5252 bool is_q
= extract32(insn
, 30, 1);
5253 int esize
= 8 << size
;
5255 int datasize
= is_q
? 128 : 64;
5256 int elements
= datasize
/ esize
;
5257 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5259 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5260 unallocated_encoding(s
);
5264 if (!fp_access_check(s
)) {
5268 tcg_resl
= tcg_const_i64(0);
5269 tcg_resh
= tcg_const_i64(0);
5270 tcg_res
= tcg_temp_new_i64();
5272 for (i
= 0; i
< elements
; i
++) {
5274 case 1: /* UZP1/2 */
5276 int midpoint
= elements
/ 2;
5278 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5280 read_vec_element(s
, tcg_res
, rm
,
5281 2 * (i
- midpoint
) + part
, size
);
5285 case 2: /* TRN1/2 */
5287 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5289 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5292 case 3: /* ZIP1/2 */
5294 int base
= part
* elements
/ 2;
5296 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5298 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5303 g_assert_not_reached();
5308 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5309 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5311 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5312 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5316 tcg_temp_free_i64(tcg_res
);
5318 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5319 tcg_temp_free_i64(tcg_resl
);
5320 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5321 tcg_temp_free_i64(tcg_resh
);
5324 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5325 int opc
, bool is_min
, TCGv_ptr fpst
)
5327 /* Helper function for disas_simd_across_lanes: do a single precision
5328 * min/max operation on the specified two inputs,
5329 * and return the result in tcg_elt1.
5333 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5335 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5340 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5342 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5347 /* C3.6.4 AdvSIMD across lanes
5348 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5349 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5350 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5351 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5353 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5355 int rd
= extract32(insn
, 0, 5);
5356 int rn
= extract32(insn
, 5, 5);
5357 int size
= extract32(insn
, 22, 2);
5358 int opcode
= extract32(insn
, 12, 5);
5359 bool is_q
= extract32(insn
, 30, 1);
5360 bool is_u
= extract32(insn
, 29, 1);
5362 bool is_min
= false;
5366 TCGv_i64 tcg_res
, tcg_elt
;
5369 case 0x1b: /* ADDV */
5371 unallocated_encoding(s
);
5375 case 0x3: /* SADDLV, UADDLV */
5376 case 0xa: /* SMAXV, UMAXV */
5377 case 0x1a: /* SMINV, UMINV */
5378 if (size
== 3 || (size
== 2 && !is_q
)) {
5379 unallocated_encoding(s
);
5383 case 0xc: /* FMAXNMV, FMINNMV */
5384 case 0xf: /* FMAXV, FMINV */
5385 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5386 unallocated_encoding(s
);
5389 /* Bit 1 of size field encodes min vs max, and actual size is always
5390 * 32 bits: adjust the size variable so following code can rely on it
5392 is_min
= extract32(size
, 1, 1);
5397 unallocated_encoding(s
);
5401 if (!fp_access_check(s
)) {
5406 elements
= (is_q
? 128 : 64) / esize
;
5408 tcg_res
= tcg_temp_new_i64();
5409 tcg_elt
= tcg_temp_new_i64();
5411 /* These instructions operate across all lanes of a vector
5412 * to produce a single result. We can guarantee that a 64
5413 * bit intermediate is sufficient:
5414 * + for [US]ADDLV the maximum element size is 32 bits, and
5415 * the result type is 64 bits
5416 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5417 * same as the element size, which is 32 bits at most
5418 * For the integer operations we can choose to work at 64
5419 * or 32 bits and truncate at the end; for simplicity
5420 * we use 64 bits always. The floating point
5421 * ops do require 32 bit intermediates, though.
5424 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5426 for (i
= 1; i
< elements
; i
++) {
5427 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5430 case 0x03: /* SADDLV / UADDLV */
5431 case 0x1b: /* ADDV */
5432 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5434 case 0x0a: /* SMAXV / UMAXV */
5435 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5437 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5439 case 0x1a: /* SMINV / UMINV */
5440 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5442 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5446 g_assert_not_reached();
5451 /* Floating point ops which work on 32 bit (single) intermediates.
5452 * Note that correct NaN propagation requires that we do these
5453 * operations in exactly the order specified by the pseudocode.
5455 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5456 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5457 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5458 TCGv_ptr fpst
= get_fpstatus_ptr();
5460 assert(esize
== 32);
5461 assert(elements
== 4);
5463 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5464 tcg_gen_trunc_i64_i32(tcg_elt1
, tcg_elt
);
5465 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5466 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5468 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5470 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5471 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5472 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5473 tcg_gen_trunc_i64_i32(tcg_elt3
, tcg_elt
);
5475 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5477 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5479 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5480 tcg_temp_free_i32(tcg_elt1
);
5481 tcg_temp_free_i32(tcg_elt2
);
5482 tcg_temp_free_i32(tcg_elt3
);
5483 tcg_temp_free_ptr(fpst
);
5486 tcg_temp_free_i64(tcg_elt
);
5488 /* Now truncate the result to the width required for the final output */
5489 if (opcode
== 0x03) {
5490 /* SADDLV, UADDLV: result is 2*esize */
5496 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5499 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5502 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5507 g_assert_not_reached();
5510 write_fp_dreg(s
, rd
, tcg_res
);
5511 tcg_temp_free_i64(tcg_res
);
5514 /* C6.3.31 DUP (Element, Vector)
5516 * 31 30 29 21 20 16 15 10 9 5 4 0
5517 * +---+---+-------------------+--------+-------------+------+------+
5518 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5519 * +---+---+-------------------+--------+-------------+------+------+
5521 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5523 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5526 int size
= ctz32(imm5
);
5527 int esize
= 8 << size
;
5528 int elements
= (is_q
? 128 : 64) / esize
;
5532 if (size
> 3 || (size
== 3 && !is_q
)) {
5533 unallocated_encoding(s
);
5537 if (!fp_access_check(s
)) {
5541 index
= imm5
>> (size
+ 1);
5543 tmp
= tcg_temp_new_i64();
5544 read_vec_element(s
, tmp
, rn
, index
, size
);
5546 for (i
= 0; i
< elements
; i
++) {
5547 write_vec_element(s
, tmp
, rd
, i
, size
);
5551 clear_vec_high(s
, rd
);
5554 tcg_temp_free_i64(tmp
);
5557 /* C6.3.31 DUP (element, scalar)
5558 * 31 21 20 16 15 10 9 5 4 0
5559 * +-----------------------+--------+-------------+------+------+
5560 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5561 * +-----------------------+--------+-------------+------+------+
5563 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5566 int size
= ctz32(imm5
);
5571 unallocated_encoding(s
);
5575 if (!fp_access_check(s
)) {
5579 index
= imm5
>> (size
+ 1);
5581 /* This instruction just extracts the specified element and
5582 * zero-extends it into the bottom of the destination register.
5584 tmp
= tcg_temp_new_i64();
5585 read_vec_element(s
, tmp
, rn
, index
, size
);
5586 write_fp_dreg(s
, rd
, tmp
);
5587 tcg_temp_free_i64(tmp
);
5590 /* C6.3.32 DUP (General)
5592 * 31 30 29 21 20 16 15 10 9 5 4 0
5593 * +---+---+-------------------+--------+-------------+------+------+
5594 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5595 * +---+---+-------------------+--------+-------------+------+------+
5597 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5599 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5602 int size
= ctz32(imm5
);
5603 int esize
= 8 << size
;
5604 int elements
= (is_q
? 128 : 64)/esize
;
5607 if (size
> 3 || ((size
== 3) && !is_q
)) {
5608 unallocated_encoding(s
);
5612 if (!fp_access_check(s
)) {
5616 for (i
= 0; i
< elements
; i
++) {
5617 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5620 clear_vec_high(s
, rd
);
5624 /* C6.3.150 INS (Element)
5626 * 31 21 20 16 15 14 11 10 9 5 4 0
5627 * +-----------------------+--------+------------+---+------+------+
5628 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5629 * +-----------------------+--------+------------+---+------+------+
5631 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5632 * index: encoded in imm5<4:size+1>
5634 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5637 int size
= ctz32(imm5
);
5638 int src_index
, dst_index
;
5642 unallocated_encoding(s
);
5646 if (!fp_access_check(s
)) {
5650 dst_index
= extract32(imm5
, 1+size
, 5);
5651 src_index
= extract32(imm4
, size
, 4);
5653 tmp
= tcg_temp_new_i64();
5655 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5656 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5658 tcg_temp_free_i64(tmp
);
5662 /* C6.3.151 INS (General)
5664 * 31 21 20 16 15 10 9 5 4 0
5665 * +-----------------------+--------+-------------+------+------+
5666 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5667 * +-----------------------+--------+-------------+------+------+
5669 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5670 * index: encoded in imm5<4:size+1>
5672 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5674 int size
= ctz32(imm5
);
5678 unallocated_encoding(s
);
5682 if (!fp_access_check(s
)) {
5686 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5687 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5691 * C6.3.321 UMOV (General)
5692 * C6.3.237 SMOV (General)
5694 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5695 * +---+---+-------------------+--------+-------------+------+------+
5696 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5697 * +---+---+-------------------+--------+-------------+------+------+
5699 * U: unsigned when set
5700 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5702 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5703 int rn
, int rd
, int imm5
)
5705 int size
= ctz32(imm5
);
5709 /* Check for UnallocatedEncodings */
5711 if (size
> 2 || (size
== 2 && !is_q
)) {
5712 unallocated_encoding(s
);
5717 || (size
< 3 && is_q
)
5718 || (size
== 3 && !is_q
)) {
5719 unallocated_encoding(s
);
5724 if (!fp_access_check(s
)) {
5728 element
= extract32(imm5
, 1+size
, 4);
5730 tcg_rd
= cpu_reg(s
, rd
);
5731 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
5732 if (is_signed
&& !is_q
) {
5733 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5737 /* C3.6.5 AdvSIMD copy
5738 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5739 * +---+---+----+-----------------+------+---+------+---+------+------+
5740 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5741 * +---+---+----+-----------------+------+---+------+---+------+------+
5743 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
5745 int rd
= extract32(insn
, 0, 5);
5746 int rn
= extract32(insn
, 5, 5);
5747 int imm4
= extract32(insn
, 11, 4);
5748 int op
= extract32(insn
, 29, 1);
5749 int is_q
= extract32(insn
, 30, 1);
5750 int imm5
= extract32(insn
, 16, 5);
5755 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
5757 unallocated_encoding(s
);
5762 /* DUP (element - vector) */
5763 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
5767 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
5772 handle_simd_insg(s
, rd
, rn
, imm5
);
5774 unallocated_encoding(s
);
5779 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
5780 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
5783 unallocated_encoding(s
);
5789 /* C3.6.6 AdvSIMD modified immediate
5790 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
5791 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5792 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
5793 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5795 * There are a number of operations that can be carried out here:
5796 * MOVI - move (shifted) imm into register
5797 * MVNI - move inverted (shifted) imm into register
5798 * ORR - bitwise OR of (shifted) imm with register
5799 * BIC - bitwise clear of (shifted) imm with register
5801 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
5803 int rd
= extract32(insn
, 0, 5);
5804 int cmode
= extract32(insn
, 12, 4);
5805 int cmode_3_1
= extract32(cmode
, 1, 3);
5806 int cmode_0
= extract32(cmode
, 0, 1);
5807 int o2
= extract32(insn
, 11, 1);
5808 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
5809 bool is_neg
= extract32(insn
, 29, 1);
5810 bool is_q
= extract32(insn
, 30, 1);
5812 TCGv_i64 tcg_rd
, tcg_imm
;
5815 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
5816 unallocated_encoding(s
);
5820 if (!fp_access_check(s
)) {
5824 /* See AdvSIMDExpandImm() in ARM ARM */
5825 switch (cmode_3_1
) {
5826 case 0: /* Replicate(Zeros(24):imm8, 2) */
5827 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
5828 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
5829 case 3: /* Replicate(imm8:Zeros(24), 2) */
5831 int shift
= cmode_3_1
* 8;
5832 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
5835 case 4: /* Replicate(Zeros(8):imm8, 4) */
5836 case 5: /* Replicate(imm8:Zeros(8), 4) */
5838 int shift
= (cmode_3_1
& 0x1) * 8;
5839 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
5844 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
5845 imm
= (abcdefgh
<< 16) | 0xffff;
5847 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
5848 imm
= (abcdefgh
<< 8) | 0xff;
5850 imm
= bitfield_replicate(imm
, 32);
5853 if (!cmode_0
&& !is_neg
) {
5854 imm
= bitfield_replicate(abcdefgh
, 8);
5855 } else if (!cmode_0
&& is_neg
) {
5858 for (i
= 0; i
< 8; i
++) {
5859 if ((abcdefgh
) & (1 << i
)) {
5860 imm
|= 0xffULL
<< (i
* 8);
5863 } else if (cmode_0
) {
5865 imm
= (abcdefgh
& 0x3f) << 48;
5866 if (abcdefgh
& 0x80) {
5867 imm
|= 0x8000000000000000ULL
;
5869 if (abcdefgh
& 0x40) {
5870 imm
|= 0x3fc0000000000000ULL
;
5872 imm
|= 0x4000000000000000ULL
;
5875 imm
= (abcdefgh
& 0x3f) << 19;
5876 if (abcdefgh
& 0x80) {
5879 if (abcdefgh
& 0x40) {
5890 if (cmode_3_1
!= 7 && is_neg
) {
5894 tcg_imm
= tcg_const_i64(imm
);
5895 tcg_rd
= new_tmp_a64(s
);
5897 for (i
= 0; i
< 2; i
++) {
5898 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
5900 if (i
== 1 && !is_q
) {
5901 /* non-quad ops clear high half of vector */
5902 tcg_gen_movi_i64(tcg_rd
, 0);
5903 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
5904 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
5907 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5910 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5914 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
5916 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
5919 tcg_temp_free_i64(tcg_imm
);
5922 /* C3.6.7 AdvSIMD scalar copy
5923 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5924 * +-----+----+-----------------+------+---+------+---+------+------+
5925 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5926 * +-----+----+-----------------+------+---+------+---+------+------+
5928 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
5930 int rd
= extract32(insn
, 0, 5);
5931 int rn
= extract32(insn
, 5, 5);
5932 int imm4
= extract32(insn
, 11, 4);
5933 int imm5
= extract32(insn
, 16, 5);
5934 int op
= extract32(insn
, 29, 1);
5936 if (op
!= 0 || imm4
!= 0) {
5937 unallocated_encoding(s
);
5941 /* DUP (element, scalar) */
5942 handle_simd_dupes(s
, rd
, rn
, imm5
);
5945 /* C3.6.8 AdvSIMD scalar pairwise
5946 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5947 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5948 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5949 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5951 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
5953 int u
= extract32(insn
, 29, 1);
5954 int size
= extract32(insn
, 22, 2);
5955 int opcode
= extract32(insn
, 12, 5);
5956 int rn
= extract32(insn
, 5, 5);
5957 int rd
= extract32(insn
, 0, 5);
5960 /* For some ops (the FP ones), size[1] is part of the encoding.
5961 * For ADDP strictly it is not but size[1] is always 1 for valid
5964 opcode
|= (extract32(size
, 1, 1) << 5);
5967 case 0x3b: /* ADDP */
5968 if (u
|| size
!= 3) {
5969 unallocated_encoding(s
);
5972 if (!fp_access_check(s
)) {
5976 TCGV_UNUSED_PTR(fpst
);
5978 case 0xc: /* FMAXNMP */
5979 case 0xd: /* FADDP */
5980 case 0xf: /* FMAXP */
5981 case 0x2c: /* FMINNMP */
5982 case 0x2f: /* FMINP */
5983 /* FP op, size[0] is 32 or 64 bit */
5985 unallocated_encoding(s
);
5988 if (!fp_access_check(s
)) {
5992 size
= extract32(size
, 0, 1) ? 3 : 2;
5993 fpst
= get_fpstatus_ptr();
5996 unallocated_encoding(s
);
6001 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6002 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6003 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6005 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
6006 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
6009 case 0x3b: /* ADDP */
6010 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
6012 case 0xc: /* FMAXNMP */
6013 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6015 case 0xd: /* FADDP */
6016 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6018 case 0xf: /* FMAXP */
6019 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6021 case 0x2c: /* FMINNMP */
6022 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6024 case 0x2f: /* FMINP */
6025 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6028 g_assert_not_reached();
6031 write_fp_dreg(s
, rd
, tcg_res
);
6033 tcg_temp_free_i64(tcg_op1
);
6034 tcg_temp_free_i64(tcg_op2
);
6035 tcg_temp_free_i64(tcg_res
);
6037 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6038 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6039 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6041 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6042 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6045 case 0xc: /* FMAXNMP */
6046 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6048 case 0xd: /* FADDP */
6049 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6051 case 0xf: /* FMAXP */
6052 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6054 case 0x2c: /* FMINNMP */
6055 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6057 case 0x2f: /* FMINP */
6058 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6061 g_assert_not_reached();
6064 write_fp_sreg(s
, rd
, tcg_res
);
6066 tcg_temp_free_i32(tcg_op1
);
6067 tcg_temp_free_i32(tcg_op2
);
6068 tcg_temp_free_i32(tcg_res
);
6071 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
6072 tcg_temp_free_ptr(fpst
);
6077 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6079 * This code is handles the common shifting code and is used by both
6080 * the vector and scalar code.
6082 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6083 TCGv_i64 tcg_rnd
, bool accumulate
,
6084 bool is_u
, int size
, int shift
)
6086 bool extended_result
= false;
6087 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
6089 TCGv_i64 tcg_src_hi
;
6091 if (round
&& size
== 3) {
6092 extended_result
= true;
6093 ext_lshift
= 64 - shift
;
6094 tcg_src_hi
= tcg_temp_new_i64();
6095 } else if (shift
== 64) {
6096 if (!accumulate
&& is_u
) {
6097 /* result is zero */
6098 tcg_gen_movi_i64(tcg_res
, 0);
6103 /* Deal with the rounding step */
6105 if (extended_result
) {
6106 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6108 /* take care of sign extending tcg_res */
6109 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6110 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6111 tcg_src
, tcg_src_hi
,
6114 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6118 tcg_temp_free_i64(tcg_zero
);
6120 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6124 /* Now do the shift right */
6125 if (round
&& extended_result
) {
6126 /* extended case, >64 bit precision required */
6127 if (ext_lshift
== 0) {
6128 /* special case, only high bits matter */
6129 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6131 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6132 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6133 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6138 /* essentially shifting in 64 zeros */
6139 tcg_gen_movi_i64(tcg_src
, 0);
6141 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6145 /* effectively extending the sign-bit */
6146 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6148 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6154 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6156 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6159 if (extended_result
) {
6160 tcg_temp_free_i64(tcg_src_hi
);
6164 /* Common SHL/SLI - Shift left with an optional insert */
6165 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6166 bool insert
, int shift
)
6168 if (insert
) { /* SLI */
6169 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6171 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6175 /* SRI: shift right with insert */
6176 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6177 int size
, int shift
)
6179 int esize
= 8 << size
;
6181 /* shift count same as element size is valid but does nothing;
6182 * special case to avoid potential shift by 64.
6184 if (shift
!= esize
) {
6185 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6186 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6190 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6191 static void handle_scalar_simd_shri(DisasContext
*s
,
6192 bool is_u
, int immh
, int immb
,
6193 int opcode
, int rn
, int rd
)
6196 int immhb
= immh
<< 3 | immb
;
6197 int shift
= 2 * (8 << size
) - immhb
;
6198 bool accumulate
= false;
6200 bool insert
= false;
6205 if (!extract32(immh
, 3, 1)) {
6206 unallocated_encoding(s
);
6210 if (!fp_access_check(s
)) {
6215 case 0x02: /* SSRA / USRA (accumulate) */
6218 case 0x04: /* SRSHR / URSHR (rounding) */
6221 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6222 accumulate
= round
= true;
6224 case 0x08: /* SRI */
6230 uint64_t round_const
= 1ULL << (shift
- 1);
6231 tcg_round
= tcg_const_i64(round_const
);
6233 TCGV_UNUSED_I64(tcg_round
);
6236 tcg_rn
= read_fp_dreg(s
, rn
);
6237 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6240 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6242 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6243 accumulate
, is_u
, size
, shift
);
6246 write_fp_dreg(s
, rd
, tcg_rd
);
6248 tcg_temp_free_i64(tcg_rn
);
6249 tcg_temp_free_i64(tcg_rd
);
6251 tcg_temp_free_i64(tcg_round
);
6255 /* SHL/SLI - Scalar shift left */
6256 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6257 int immh
, int immb
, int opcode
,
6260 int size
= 32 - clz32(immh
) - 1;
6261 int immhb
= immh
<< 3 | immb
;
6262 int shift
= immhb
- (8 << size
);
6263 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6264 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6266 if (!extract32(immh
, 3, 1)) {
6267 unallocated_encoding(s
);
6271 if (!fp_access_check(s
)) {
6275 tcg_rn
= read_fp_dreg(s
, rn
);
6276 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6278 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6280 write_fp_dreg(s
, rd
, tcg_rd
);
6282 tcg_temp_free_i64(tcg_rn
);
6283 tcg_temp_free_i64(tcg_rd
);
6286 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6287 * (signed/unsigned) narrowing */
6288 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6289 bool is_u_shift
, bool is_u_narrow
,
6290 int immh
, int immb
, int opcode
,
6293 int immhb
= immh
<< 3 | immb
;
6294 int size
= 32 - clz32(immh
) - 1;
6295 int esize
= 8 << size
;
6296 int shift
= (2 * esize
) - immhb
;
6297 int elements
= is_scalar
? 1 : (64 / esize
);
6298 bool round
= extract32(opcode
, 0, 1);
6299 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6300 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6301 TCGv_i32 tcg_rd_narrowed
;
6304 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6305 { gen_helper_neon_narrow_sat_s8
,
6306 gen_helper_neon_unarrow_sat8
},
6307 { gen_helper_neon_narrow_sat_s16
,
6308 gen_helper_neon_unarrow_sat16
},
6309 { gen_helper_neon_narrow_sat_s32
,
6310 gen_helper_neon_unarrow_sat32
},
6313 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6314 gen_helper_neon_narrow_sat_u8
,
6315 gen_helper_neon_narrow_sat_u16
,
6316 gen_helper_neon_narrow_sat_u32
,
6319 NeonGenNarrowEnvFn
*narrowfn
;
6325 if (extract32(immh
, 3, 1)) {
6326 unallocated_encoding(s
);
6330 if (!fp_access_check(s
)) {
6335 narrowfn
= unsigned_narrow_fns
[size
];
6337 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6340 tcg_rn
= tcg_temp_new_i64();
6341 tcg_rd
= tcg_temp_new_i64();
6342 tcg_rd_narrowed
= tcg_temp_new_i32();
6343 tcg_final
= tcg_const_i64(0);
6346 uint64_t round_const
= 1ULL << (shift
- 1);
6347 tcg_round
= tcg_const_i64(round_const
);
6349 TCGV_UNUSED_I64(tcg_round
);
6352 for (i
= 0; i
< elements
; i
++) {
6353 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6354 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6355 false, is_u_shift
, size
+1, shift
);
6356 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6357 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6358 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6362 clear_vec_high(s
, rd
);
6363 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6365 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6369 tcg_temp_free_i64(tcg_round
);
6371 tcg_temp_free_i64(tcg_rn
);
6372 tcg_temp_free_i64(tcg_rd
);
6373 tcg_temp_free_i32(tcg_rd_narrowed
);
6374 tcg_temp_free_i64(tcg_final
);
6378 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6379 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6380 bool src_unsigned
, bool dst_unsigned
,
6381 int immh
, int immb
, int rn
, int rd
)
6383 int immhb
= immh
<< 3 | immb
;
6384 int size
= 32 - clz32(immh
) - 1;
6385 int shift
= immhb
- (8 << size
);
6389 assert(!(scalar
&& is_q
));
6392 if (!is_q
&& extract32(immh
, 3, 1)) {
6393 unallocated_encoding(s
);
6397 /* Since we use the variable-shift helpers we must
6398 * replicate the shift count into each element of
6399 * the tcg_shift value.
6403 shift
|= shift
<< 8;
6406 shift
|= shift
<< 16;
6412 g_assert_not_reached();
6416 if (!fp_access_check(s
)) {
6421 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6422 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6423 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6424 { NULL
, gen_helper_neon_qshl_u64
},
6426 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6427 int maxpass
= is_q
? 2 : 1;
6429 for (pass
= 0; pass
< maxpass
; pass
++) {
6430 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6432 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6433 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6434 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6436 tcg_temp_free_i64(tcg_op
);
6438 tcg_temp_free_i64(tcg_shift
);
6441 clear_vec_high(s
, rd
);
6444 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6445 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6447 { gen_helper_neon_qshl_s8
,
6448 gen_helper_neon_qshl_s16
,
6449 gen_helper_neon_qshl_s32
},
6450 { gen_helper_neon_qshlu_s8
,
6451 gen_helper_neon_qshlu_s16
,
6452 gen_helper_neon_qshlu_s32
}
6454 { NULL
, NULL
, NULL
},
6455 { gen_helper_neon_qshl_u8
,
6456 gen_helper_neon_qshl_u16
,
6457 gen_helper_neon_qshl_u32
}
6460 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6461 TCGMemOp memop
= scalar
? size
: MO_32
;
6462 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6464 for (pass
= 0; pass
< maxpass
; pass
++) {
6465 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6467 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6468 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6472 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6475 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6480 g_assert_not_reached();
6482 write_fp_sreg(s
, rd
, tcg_op
);
6484 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6487 tcg_temp_free_i32(tcg_op
);
6489 tcg_temp_free_i32(tcg_shift
);
6491 if (!is_q
&& !scalar
) {
6492 clear_vec_high(s
, rd
);
6497 /* Common vector code for handling integer to FP conversion */
6498 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6499 int elements
, int is_signed
,
6500 int fracbits
, int size
)
6502 bool is_double
= size
== 3 ? true : false;
6503 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6504 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6505 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6506 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6509 for (pass
= 0; pass
< elements
; pass
++) {
6510 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6513 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6515 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6516 tcg_shift
, tcg_fpst
);
6518 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6519 tcg_shift
, tcg_fpst
);
6521 if (elements
== 1) {
6522 write_fp_dreg(s
, rd
, tcg_double
);
6524 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6526 tcg_temp_free_i64(tcg_double
);
6528 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6530 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6531 tcg_shift
, tcg_fpst
);
6533 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6534 tcg_shift
, tcg_fpst
);
6536 if (elements
== 1) {
6537 write_fp_sreg(s
, rd
, tcg_single
);
6539 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6541 tcg_temp_free_i32(tcg_single
);
6545 if (!is_double
&& elements
== 2) {
6546 clear_vec_high(s
, rd
);
6549 tcg_temp_free_i64(tcg_int
);
6550 tcg_temp_free_ptr(tcg_fpst
);
6551 tcg_temp_free_i32(tcg_shift
);
6554 /* UCVTF/SCVTF - Integer to FP conversion */
6555 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6556 bool is_q
, bool is_u
,
6557 int immh
, int immb
, int opcode
,
6560 bool is_double
= extract32(immh
, 3, 1);
6561 int size
= is_double
? MO_64
: MO_32
;
6563 int immhb
= immh
<< 3 | immb
;
6564 int fracbits
= (is_double
? 128 : 64) - immhb
;
6566 if (!extract32(immh
, 2, 2)) {
6567 unallocated_encoding(s
);
6574 elements
= is_double
? 2 : is_q
? 4 : 2;
6575 if (is_double
&& !is_q
) {
6576 unallocated_encoding(s
);
6581 if (!fp_access_check(s
)) {
6585 /* immh == 0 would be a failure of the decode logic */
6588 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6591 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6592 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6593 bool is_q
, bool is_u
,
6594 int immh
, int immb
, int rn
, int rd
)
6596 bool is_double
= extract32(immh
, 3, 1);
6597 int immhb
= immh
<< 3 | immb
;
6598 int fracbits
= (is_double
? 128 : 64) - immhb
;
6600 TCGv_ptr tcg_fpstatus
;
6601 TCGv_i32 tcg_rmode
, tcg_shift
;
6603 if (!extract32(immh
, 2, 2)) {
6604 unallocated_encoding(s
);
6608 if (!is_scalar
&& !is_q
&& is_double
) {
6609 unallocated_encoding(s
);
6613 if (!fp_access_check(s
)) {
6617 assert(!(is_scalar
&& is_q
));
6619 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6620 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6621 tcg_fpstatus
= get_fpstatus_ptr();
6622 tcg_shift
= tcg_const_i32(fracbits
);
6625 int maxpass
= is_scalar
? 1 : 2;
6627 for (pass
= 0; pass
< maxpass
; pass
++) {
6628 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6630 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6632 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6634 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6636 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6637 tcg_temp_free_i64(tcg_op
);
6640 clear_vec_high(s
, rd
);
6643 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6644 for (pass
= 0; pass
< maxpass
; pass
++) {
6645 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6647 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6649 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6651 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6654 write_fp_sreg(s
, rd
, tcg_op
);
6656 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6658 tcg_temp_free_i32(tcg_op
);
6660 if (!is_q
&& !is_scalar
) {
6661 clear_vec_high(s
, rd
);
6665 tcg_temp_free_ptr(tcg_fpstatus
);
6666 tcg_temp_free_i32(tcg_shift
);
6667 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6668 tcg_temp_free_i32(tcg_rmode
);
6671 /* C3.6.9 AdvSIMD scalar shift by immediate
6672 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6673 * +-----+---+-------------+------+------+--------+---+------+------+
6674 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6675 * +-----+---+-------------+------+------+--------+---+------+------+
6677 * This is the scalar version so it works on a fixed sized registers
6679 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6681 int rd
= extract32(insn
, 0, 5);
6682 int rn
= extract32(insn
, 5, 5);
6683 int opcode
= extract32(insn
, 11, 5);
6684 int immb
= extract32(insn
, 16, 3);
6685 int immh
= extract32(insn
, 19, 4);
6686 bool is_u
= extract32(insn
, 29, 1);
6689 unallocated_encoding(s
);
6694 case 0x08: /* SRI */
6696 unallocated_encoding(s
);
6700 case 0x00: /* SSHR / USHR */
6701 case 0x02: /* SSRA / USRA */
6702 case 0x04: /* SRSHR / URSHR */
6703 case 0x06: /* SRSRA / URSRA */
6704 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6706 case 0x0a: /* SHL / SLI */
6707 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6709 case 0x1c: /* SCVTF, UCVTF */
6710 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6713 case 0x10: /* SQSHRUN, SQSHRUN2 */
6714 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6716 unallocated_encoding(s
);
6719 handle_vec_simd_sqshrn(s
, true, false, false, true,
6720 immh
, immb
, opcode
, rn
, rd
);
6722 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6723 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6724 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
6725 immh
, immb
, opcode
, rn
, rd
);
6727 case 0xc: /* SQSHLU */
6729 unallocated_encoding(s
);
6732 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
6734 case 0xe: /* SQSHL, UQSHL */
6735 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
6737 case 0x1f: /* FCVTZS, FCVTZU */
6738 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
6741 unallocated_encoding(s
);
6746 /* C3.6.10 AdvSIMD scalar three different
6747 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6748 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6749 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
6750 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6752 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
6754 bool is_u
= extract32(insn
, 29, 1);
6755 int size
= extract32(insn
, 22, 2);
6756 int opcode
= extract32(insn
, 12, 4);
6757 int rm
= extract32(insn
, 16, 5);
6758 int rn
= extract32(insn
, 5, 5);
6759 int rd
= extract32(insn
, 0, 5);
6762 unallocated_encoding(s
);
6767 case 0x9: /* SQDMLAL, SQDMLAL2 */
6768 case 0xb: /* SQDMLSL, SQDMLSL2 */
6769 case 0xd: /* SQDMULL, SQDMULL2 */
6770 if (size
== 0 || size
== 3) {
6771 unallocated_encoding(s
);
6776 unallocated_encoding(s
);
6780 if (!fp_access_check(s
)) {
6785 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6786 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6787 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6789 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
6790 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
6792 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
6793 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6796 case 0xd: /* SQDMULL, SQDMULL2 */
6798 case 0xb: /* SQDMLSL, SQDMLSL2 */
6799 tcg_gen_neg_i64(tcg_res
, tcg_res
);
6801 case 0x9: /* SQDMLAL, SQDMLAL2 */
6802 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
6803 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
6807 g_assert_not_reached();
6810 write_fp_dreg(s
, rd
, tcg_res
);
6812 tcg_temp_free_i64(tcg_op1
);
6813 tcg_temp_free_i64(tcg_op2
);
6814 tcg_temp_free_i64(tcg_res
);
6816 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6817 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6818 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6820 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
6821 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
6823 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
6824 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6827 case 0xd: /* SQDMULL, SQDMULL2 */
6829 case 0xb: /* SQDMLSL, SQDMLSL2 */
6830 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
6832 case 0x9: /* SQDMLAL, SQDMLAL2 */
6834 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
6835 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
6836 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
6838 tcg_temp_free_i64(tcg_op3
);
6842 g_assert_not_reached();
6845 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6846 write_fp_dreg(s
, rd
, tcg_res
);
6848 tcg_temp_free_i32(tcg_op1
);
6849 tcg_temp_free_i32(tcg_op2
);
6850 tcg_temp_free_i64(tcg_res
);
6854 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
6855 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
6857 /* Handle 64x64->64 opcodes which are shared between the scalar
6858 * and vector 3-same groups. We cover every opcode where size == 3
6859 * is valid in either the three-reg-same (integer, not pairwise)
6860 * or scalar-three-reg-same groups. (Some opcodes are not yet
6866 case 0x1: /* SQADD */
6868 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6870 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6873 case 0x5: /* SQSUB */
6875 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6877 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6880 case 0x6: /* CMGT, CMHI */
6881 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
6882 * We implement this using setcond (test) and then negating.
6884 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
6886 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
6887 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6889 case 0x7: /* CMGE, CMHS */
6890 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
6892 case 0x11: /* CMTST, CMEQ */
6897 /* CMTST : test is "if (X & Y != 0)". */
6898 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6899 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
6900 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6902 case 0x8: /* SSHL, USHL */
6904 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6906 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6909 case 0x9: /* SQSHL, UQSHL */
6911 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6913 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6916 case 0xa: /* SRSHL, URSHL */
6918 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6920 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6923 case 0xb: /* SQRSHL, UQRSHL */
6925 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6927 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6930 case 0x10: /* ADD, SUB */
6932 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6934 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6938 g_assert_not_reached();
6942 /* Handle the 3-same-operands float operations; shared by the scalar
6943 * and vector encodings. The caller must filter out any encodings
6944 * not allocated for the encoding it is dealing with.
6946 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
6947 int fpopcode
, int rd
, int rn
, int rm
)
6950 TCGv_ptr fpst
= get_fpstatus_ptr();
6952 for (pass
= 0; pass
< elements
; pass
++) {
6955 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6956 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6957 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6959 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
6960 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
6963 case 0x39: /* FMLS */
6964 /* As usual for ARM, separate negation for fused multiply-add */
6965 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6967 case 0x19: /* FMLA */
6968 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6969 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
6972 case 0x18: /* FMAXNM */
6973 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6975 case 0x1a: /* FADD */
6976 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6978 case 0x1b: /* FMULX */
6979 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6981 case 0x1c: /* FCMEQ */
6982 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6984 case 0x1e: /* FMAX */
6985 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6987 case 0x1f: /* FRECPS */
6988 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6990 case 0x38: /* FMINNM */
6991 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6993 case 0x3a: /* FSUB */
6994 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6996 case 0x3e: /* FMIN */
6997 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6999 case 0x3f: /* FRSQRTS */
7000 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7002 case 0x5b: /* FMUL */
7003 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7005 case 0x5c: /* FCMGE */
7006 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7008 case 0x5d: /* FACGE */
7009 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7011 case 0x5f: /* FDIV */
7012 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7014 case 0x7a: /* FABD */
7015 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7016 gen_helper_vfp_absd(tcg_res
, tcg_res
);
7018 case 0x7c: /* FCMGT */
7019 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7021 case 0x7d: /* FACGT */
7022 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7025 g_assert_not_reached();
7028 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7030 tcg_temp_free_i64(tcg_res
);
7031 tcg_temp_free_i64(tcg_op1
);
7032 tcg_temp_free_i64(tcg_op2
);
7035 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7036 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7037 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7039 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7040 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7043 case 0x39: /* FMLS */
7044 /* As usual for ARM, separate negation for fused multiply-add */
7045 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7047 case 0x19: /* FMLA */
7048 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7049 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7052 case 0x1a: /* FADD */
7053 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7055 case 0x1b: /* FMULX */
7056 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7058 case 0x1c: /* FCMEQ */
7059 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7061 case 0x1e: /* FMAX */
7062 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7064 case 0x1f: /* FRECPS */
7065 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7067 case 0x18: /* FMAXNM */
7068 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7070 case 0x38: /* FMINNM */
7071 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7073 case 0x3a: /* FSUB */
7074 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7076 case 0x3e: /* FMIN */
7077 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7079 case 0x3f: /* FRSQRTS */
7080 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7082 case 0x5b: /* FMUL */
7083 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7085 case 0x5c: /* FCMGE */
7086 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7088 case 0x5d: /* FACGE */
7089 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7091 case 0x5f: /* FDIV */
7092 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7094 case 0x7a: /* FABD */
7095 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7096 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7098 case 0x7c: /* FCMGT */
7099 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7101 case 0x7d: /* FACGT */
7102 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7105 g_assert_not_reached();
7108 if (elements
== 1) {
7109 /* scalar single so clear high part */
7110 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7112 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7113 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7114 tcg_temp_free_i64(tcg_tmp
);
7116 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7119 tcg_temp_free_i32(tcg_res
);
7120 tcg_temp_free_i32(tcg_op1
);
7121 tcg_temp_free_i32(tcg_op2
);
7125 tcg_temp_free_ptr(fpst
);
7127 if ((elements
<< size
) < 4) {
7128 /* scalar, or non-quad vector op */
7129 clear_vec_high(s
, rd
);
7133 /* C3.6.11 AdvSIMD scalar three same
7134 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7135 * +-----+---+-----------+------+---+------+--------+---+------+------+
7136 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7137 * +-----+---+-----------+------+---+------+--------+---+------+------+
7139 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7141 int rd
= extract32(insn
, 0, 5);
7142 int rn
= extract32(insn
, 5, 5);
7143 int opcode
= extract32(insn
, 11, 5);
7144 int rm
= extract32(insn
, 16, 5);
7145 int size
= extract32(insn
, 22, 2);
7146 bool u
= extract32(insn
, 29, 1);
7149 if (opcode
>= 0x18) {
7150 /* Floating point: U, size[1] and opcode indicate operation */
7151 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7153 case 0x1b: /* FMULX */
7154 case 0x1f: /* FRECPS */
7155 case 0x3f: /* FRSQRTS */
7156 case 0x5d: /* FACGE */
7157 case 0x7d: /* FACGT */
7158 case 0x1c: /* FCMEQ */
7159 case 0x5c: /* FCMGE */
7160 case 0x7c: /* FCMGT */
7161 case 0x7a: /* FABD */
7164 unallocated_encoding(s
);
7168 if (!fp_access_check(s
)) {
7172 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7177 case 0x1: /* SQADD, UQADD */
7178 case 0x5: /* SQSUB, UQSUB */
7179 case 0x9: /* SQSHL, UQSHL */
7180 case 0xb: /* SQRSHL, UQRSHL */
7182 case 0x8: /* SSHL, USHL */
7183 case 0xa: /* SRSHL, URSHL */
7184 case 0x6: /* CMGT, CMHI */
7185 case 0x7: /* CMGE, CMHS */
7186 case 0x11: /* CMTST, CMEQ */
7187 case 0x10: /* ADD, SUB (vector) */
7189 unallocated_encoding(s
);
7193 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7194 if (size
!= 1 && size
!= 2) {
7195 unallocated_encoding(s
);
7200 unallocated_encoding(s
);
7204 if (!fp_access_check(s
)) {
7208 tcg_rd
= tcg_temp_new_i64();
7211 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7212 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7214 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7215 tcg_temp_free_i64(tcg_rn
);
7216 tcg_temp_free_i64(tcg_rm
);
7218 /* Do a single operation on the lowest element in the vector.
7219 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7220 * no side effects for all these operations.
7221 * OPTME: special-purpose helpers would avoid doing some
7222 * unnecessary work in the helper for the 8 and 16 bit cases.
7224 NeonGenTwoOpEnvFn
*genenvfn
;
7225 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7226 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7227 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7229 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7230 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7233 case 0x1: /* SQADD, UQADD */
7235 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7236 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7237 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7238 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7240 genenvfn
= fns
[size
][u
];
7243 case 0x5: /* SQSUB, UQSUB */
7245 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7246 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7247 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7248 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7250 genenvfn
= fns
[size
][u
];
7253 case 0x9: /* SQSHL, UQSHL */
7255 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7256 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7257 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7258 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7260 genenvfn
= fns
[size
][u
];
7263 case 0xb: /* SQRSHL, UQRSHL */
7265 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7266 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7267 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7268 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7270 genenvfn
= fns
[size
][u
];
7273 case 0x16: /* SQDMULH, SQRDMULH */
7275 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7276 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7277 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7279 assert(size
== 1 || size
== 2);
7280 genenvfn
= fns
[size
- 1][u
];
7284 g_assert_not_reached();
7287 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7288 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7289 tcg_temp_free_i32(tcg_rd32
);
7290 tcg_temp_free_i32(tcg_rn
);
7291 tcg_temp_free_i32(tcg_rm
);
7294 write_fp_dreg(s
, rd
, tcg_rd
);
7296 tcg_temp_free_i64(tcg_rd
);
7299 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7300 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7301 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7303 /* Handle 64->64 opcodes which are shared between the scalar and
7304 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7305 * is valid in either group and also the double-precision fp ops.
7306 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7312 case 0x4: /* CLS, CLZ */
7314 gen_helper_clz64(tcg_rd
, tcg_rn
);
7316 gen_helper_cls64(tcg_rd
, tcg_rn
);
7320 /* This opcode is shared with CNT and RBIT but we have earlier
7321 * enforced that size == 3 if and only if this is the NOT insn.
7323 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7325 case 0x7: /* SQABS, SQNEG */
7327 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7329 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7332 case 0xa: /* CMLT */
7333 /* 64 bit integer comparison against zero, result is
7334 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7339 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7340 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7342 case 0x8: /* CMGT, CMGE */
7343 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7345 case 0x9: /* CMEQ, CMLE */
7346 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7348 case 0xb: /* ABS, NEG */
7350 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7352 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7353 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7354 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7356 tcg_temp_free_i64(tcg_zero
);
7359 case 0x2f: /* FABS */
7360 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7362 case 0x6f: /* FNEG */
7363 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7365 case 0x7f: /* FSQRT */
7366 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7368 case 0x1a: /* FCVTNS */
7369 case 0x1b: /* FCVTMS */
7370 case 0x1c: /* FCVTAS */
7371 case 0x3a: /* FCVTPS */
7372 case 0x3b: /* FCVTZS */
7374 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7375 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7376 tcg_temp_free_i32(tcg_shift
);
7379 case 0x5a: /* FCVTNU */
7380 case 0x5b: /* FCVTMU */
7381 case 0x5c: /* FCVTAU */
7382 case 0x7a: /* FCVTPU */
7383 case 0x7b: /* FCVTZU */
7385 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7386 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7387 tcg_temp_free_i32(tcg_shift
);
7390 case 0x18: /* FRINTN */
7391 case 0x19: /* FRINTM */
7392 case 0x38: /* FRINTP */
7393 case 0x39: /* FRINTZ */
7394 case 0x58: /* FRINTA */
7395 case 0x79: /* FRINTI */
7396 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7398 case 0x59: /* FRINTX */
7399 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7402 g_assert_not_reached();
7406 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7407 bool is_scalar
, bool is_u
, bool is_q
,
7408 int size
, int rn
, int rd
)
7410 bool is_double
= (size
== 3);
7413 if (!fp_access_check(s
)) {
7417 fpst
= get_fpstatus_ptr();
7420 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7421 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7422 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7423 NeonGenTwoDoubleOPFn
*genfn
;
7428 case 0x2e: /* FCMLT (zero) */
7431 case 0x2c: /* FCMGT (zero) */
7432 genfn
= gen_helper_neon_cgt_f64
;
7434 case 0x2d: /* FCMEQ (zero) */
7435 genfn
= gen_helper_neon_ceq_f64
;
7437 case 0x6d: /* FCMLE (zero) */
7440 case 0x6c: /* FCMGE (zero) */
7441 genfn
= gen_helper_neon_cge_f64
;
7444 g_assert_not_reached();
7447 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7448 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7450 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7452 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7454 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7457 clear_vec_high(s
, rd
);
7460 tcg_temp_free_i64(tcg_res
);
7461 tcg_temp_free_i64(tcg_zero
);
7462 tcg_temp_free_i64(tcg_op
);
7464 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7465 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7466 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7467 NeonGenTwoSingleOPFn
*genfn
;
7469 int pass
, maxpasses
;
7472 case 0x2e: /* FCMLT (zero) */
7475 case 0x2c: /* FCMGT (zero) */
7476 genfn
= gen_helper_neon_cgt_f32
;
7478 case 0x2d: /* FCMEQ (zero) */
7479 genfn
= gen_helper_neon_ceq_f32
;
7481 case 0x6d: /* FCMLE (zero) */
7484 case 0x6c: /* FCMGE (zero) */
7485 genfn
= gen_helper_neon_cge_f32
;
7488 g_assert_not_reached();
7494 maxpasses
= is_q
? 4 : 2;
7497 for (pass
= 0; pass
< maxpasses
; pass
++) {
7498 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7500 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7502 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7505 write_fp_sreg(s
, rd
, tcg_res
);
7507 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7510 tcg_temp_free_i32(tcg_res
);
7511 tcg_temp_free_i32(tcg_zero
);
7512 tcg_temp_free_i32(tcg_op
);
7513 if (!is_q
&& !is_scalar
) {
7514 clear_vec_high(s
, rd
);
7518 tcg_temp_free_ptr(fpst
);
7521 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7522 bool is_scalar
, bool is_u
, bool is_q
,
7523 int size
, int rn
, int rd
)
7525 bool is_double
= (size
== 3);
7526 TCGv_ptr fpst
= get_fpstatus_ptr();
7529 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7530 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7533 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7534 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7536 case 0x3d: /* FRECPE */
7537 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7539 case 0x3f: /* FRECPX */
7540 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7542 case 0x7d: /* FRSQRTE */
7543 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7546 g_assert_not_reached();
7548 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7551 clear_vec_high(s
, rd
);
7554 tcg_temp_free_i64(tcg_res
);
7555 tcg_temp_free_i64(tcg_op
);
7557 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7558 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7559 int pass
, maxpasses
;
7564 maxpasses
= is_q
? 4 : 2;
7567 for (pass
= 0; pass
< maxpasses
; pass
++) {
7568 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7571 case 0x3c: /* URECPE */
7572 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7574 case 0x3d: /* FRECPE */
7575 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7577 case 0x3f: /* FRECPX */
7578 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7580 case 0x7d: /* FRSQRTE */
7581 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7584 g_assert_not_reached();
7588 write_fp_sreg(s
, rd
, tcg_res
);
7590 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7593 tcg_temp_free_i32(tcg_res
);
7594 tcg_temp_free_i32(tcg_op
);
7595 if (!is_q
&& !is_scalar
) {
7596 clear_vec_high(s
, rd
);
7599 tcg_temp_free_ptr(fpst
);
7602 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7603 int opcode
, bool u
, bool is_q
,
7604 int size
, int rn
, int rd
)
7606 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7607 * in the source becomes a size element in the destination).
7610 TCGv_i32 tcg_res
[2];
7611 int destelt
= is_q
? 2 : 0;
7612 int passes
= scalar
? 1 : 2;
7615 tcg_res
[1] = tcg_const_i32(0);
7618 for (pass
= 0; pass
< passes
; pass
++) {
7619 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7620 NeonGenNarrowFn
*genfn
= NULL
;
7621 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7624 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7626 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7628 tcg_res
[pass
] = tcg_temp_new_i32();
7631 case 0x12: /* XTN, SQXTUN */
7633 static NeonGenNarrowFn
* const xtnfns
[3] = {
7634 gen_helper_neon_narrow_u8
,
7635 gen_helper_neon_narrow_u16
,
7636 tcg_gen_trunc_i64_i32
,
7638 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7639 gen_helper_neon_unarrow_sat8
,
7640 gen_helper_neon_unarrow_sat16
,
7641 gen_helper_neon_unarrow_sat32
,
7644 genenvfn
= sqxtunfns
[size
];
7646 genfn
= xtnfns
[size
];
7650 case 0x14: /* SQXTN, UQXTN */
7652 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7653 { gen_helper_neon_narrow_sat_s8
,
7654 gen_helper_neon_narrow_sat_u8
},
7655 { gen_helper_neon_narrow_sat_s16
,
7656 gen_helper_neon_narrow_sat_u16
},
7657 { gen_helper_neon_narrow_sat_s32
,
7658 gen_helper_neon_narrow_sat_u32
},
7660 genenvfn
= fns
[size
][u
];
7663 case 0x16: /* FCVTN, FCVTN2 */
7664 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7666 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7668 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7669 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7670 tcg_gen_trunc_i64_i32(tcg_lo
, tcg_op
);
7671 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7672 tcg_gen_shri_i64(tcg_op
, tcg_op
, 32);
7673 tcg_gen_trunc_i64_i32(tcg_hi
, tcg_op
);
7674 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7675 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7676 tcg_temp_free_i32(tcg_lo
);
7677 tcg_temp_free_i32(tcg_hi
);
7680 case 0x56: /* FCVTXN, FCVTXN2 */
7681 /* 64 bit to 32 bit float conversion
7682 * with von Neumann rounding (round to odd)
7685 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7688 g_assert_not_reached();
7692 genfn(tcg_res
[pass
], tcg_op
);
7693 } else if (genenvfn
) {
7694 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7697 tcg_temp_free_i64(tcg_op
);
7700 for (pass
= 0; pass
< 2; pass
++) {
7701 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7702 tcg_temp_free_i32(tcg_res
[pass
]);
7705 clear_vec_high(s
, rd
);
7709 /* Remaining saturating accumulating ops */
7710 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
7711 bool is_q
, int size
, int rn
, int rd
)
7713 bool is_double
= (size
== 3);
7716 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
7717 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7720 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7721 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
7722 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7724 if (is_u
) { /* USQADD */
7725 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7726 } else { /* SUQADD */
7727 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7729 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7732 clear_vec_high(s
, rd
);
7735 tcg_temp_free_i64(tcg_rd
);
7736 tcg_temp_free_i64(tcg_rn
);
7738 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7739 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7740 int pass
, maxpasses
;
7745 maxpasses
= is_q
? 4 : 2;
7748 for (pass
= 0; pass
< maxpasses
; pass
++) {
7750 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
7751 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
7753 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
7754 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7757 if (is_u
) { /* USQADD */
7760 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7763 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7766 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7769 g_assert_not_reached();
7771 } else { /* SUQADD */
7774 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7777 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7780 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7783 g_assert_not_reached();
7788 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7789 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
7790 tcg_temp_free_i64(tcg_zero
);
7792 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7796 clear_vec_high(s
, rd
);
7799 tcg_temp_free_i32(tcg_rd
);
7800 tcg_temp_free_i32(tcg_rn
);
7804 /* C3.6.12 AdvSIMD scalar two reg misc
7805 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7806 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7807 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
7808 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7810 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
7812 int rd
= extract32(insn
, 0, 5);
7813 int rn
= extract32(insn
, 5, 5);
7814 int opcode
= extract32(insn
, 12, 5);
7815 int size
= extract32(insn
, 22, 2);
7816 bool u
= extract32(insn
, 29, 1);
7817 bool is_fcvt
= false;
7820 TCGv_ptr tcg_fpstatus
;
7823 case 0x3: /* USQADD / SUQADD*/
7824 if (!fp_access_check(s
)) {
7827 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
7829 case 0x7: /* SQABS / SQNEG */
7831 case 0xa: /* CMLT */
7833 unallocated_encoding(s
);
7837 case 0x8: /* CMGT, CMGE */
7838 case 0x9: /* CMEQ, CMLE */
7839 case 0xb: /* ABS, NEG */
7841 unallocated_encoding(s
);
7845 case 0x12: /* SQXTUN */
7847 unallocated_encoding(s
);
7851 case 0x14: /* SQXTN, UQXTN */
7853 unallocated_encoding(s
);
7856 if (!fp_access_check(s
)) {
7859 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
7864 /* Floating point: U, size[1] and opcode indicate operation;
7865 * size[0] indicates single or double precision.
7867 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
7868 size
= extract32(size
, 0, 1) ? 3 : 2;
7870 case 0x2c: /* FCMGT (zero) */
7871 case 0x2d: /* FCMEQ (zero) */
7872 case 0x2e: /* FCMLT (zero) */
7873 case 0x6c: /* FCMGE (zero) */
7874 case 0x6d: /* FCMLE (zero) */
7875 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
7877 case 0x1d: /* SCVTF */
7878 case 0x5d: /* UCVTF */
7880 bool is_signed
= (opcode
== 0x1d);
7881 if (!fp_access_check(s
)) {
7884 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
7887 case 0x3d: /* FRECPE */
7888 case 0x3f: /* FRECPX */
7889 case 0x7d: /* FRSQRTE */
7890 if (!fp_access_check(s
)) {
7893 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
7895 case 0x1a: /* FCVTNS */
7896 case 0x1b: /* FCVTMS */
7897 case 0x3a: /* FCVTPS */
7898 case 0x3b: /* FCVTZS */
7899 case 0x5a: /* FCVTNU */
7900 case 0x5b: /* FCVTMU */
7901 case 0x7a: /* FCVTPU */
7902 case 0x7b: /* FCVTZU */
7904 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
7906 case 0x1c: /* FCVTAS */
7907 case 0x5c: /* FCVTAU */
7908 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
7910 rmode
= FPROUNDING_TIEAWAY
;
7912 case 0x56: /* FCVTXN, FCVTXN2 */
7914 unallocated_encoding(s
);
7917 if (!fp_access_check(s
)) {
7920 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
7923 unallocated_encoding(s
);
7928 unallocated_encoding(s
);
7932 if (!fp_access_check(s
)) {
7937 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7938 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7939 tcg_fpstatus
= get_fpstatus_ptr();
7941 TCGV_UNUSED_I32(tcg_rmode
);
7942 TCGV_UNUSED_PTR(tcg_fpstatus
);
7946 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7947 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7949 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
7950 write_fp_dreg(s
, rd
, tcg_rd
);
7951 tcg_temp_free_i64(tcg_rd
);
7952 tcg_temp_free_i64(tcg_rn
);
7954 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7955 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7957 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7960 case 0x7: /* SQABS, SQNEG */
7962 NeonGenOneOpEnvFn
*genfn
;
7963 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
7964 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
7965 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
7966 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
7968 genfn
= fns
[size
][u
];
7969 genfn(tcg_rd
, cpu_env
, tcg_rn
);
7972 case 0x1a: /* FCVTNS */
7973 case 0x1b: /* FCVTMS */
7974 case 0x1c: /* FCVTAS */
7975 case 0x3a: /* FCVTPS */
7976 case 0x3b: /* FCVTZS */
7978 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7979 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7980 tcg_temp_free_i32(tcg_shift
);
7983 case 0x5a: /* FCVTNU */
7984 case 0x5b: /* FCVTMU */
7985 case 0x5c: /* FCVTAU */
7986 case 0x7a: /* FCVTPU */
7987 case 0x7b: /* FCVTZU */
7989 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7990 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7991 tcg_temp_free_i32(tcg_shift
);
7995 g_assert_not_reached();
7998 write_fp_sreg(s
, rd
, tcg_rd
);
7999 tcg_temp_free_i32(tcg_rd
);
8000 tcg_temp_free_i32(tcg_rn
);
8004 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8005 tcg_temp_free_i32(tcg_rmode
);
8006 tcg_temp_free_ptr(tcg_fpstatus
);
8010 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8011 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
8012 int immh
, int immb
, int opcode
, int rn
, int rd
)
8014 int size
= 32 - clz32(immh
) - 1;
8015 int immhb
= immh
<< 3 | immb
;
8016 int shift
= 2 * (8 << size
) - immhb
;
8017 bool accumulate
= false;
8019 bool insert
= false;
8020 int dsize
= is_q
? 128 : 64;
8021 int esize
= 8 << size
;
8022 int elements
= dsize
/esize
;
8023 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
8024 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8025 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8029 if (extract32(immh
, 3, 1) && !is_q
) {
8030 unallocated_encoding(s
);
8034 if (size
> 3 && !is_q
) {
8035 unallocated_encoding(s
);
8039 if (!fp_access_check(s
)) {
8044 case 0x02: /* SSRA / USRA (accumulate) */
8047 case 0x04: /* SRSHR / URSHR (rounding) */
8050 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8051 accumulate
= round
= true;
8053 case 0x08: /* SRI */
8059 uint64_t round_const
= 1ULL << (shift
- 1);
8060 tcg_round
= tcg_const_i64(round_const
);
8062 TCGV_UNUSED_I64(tcg_round
);
8065 for (i
= 0; i
< elements
; i
++) {
8066 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8067 if (accumulate
|| insert
) {
8068 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8072 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8074 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8075 accumulate
, is_u
, size
, shift
);
8078 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8082 clear_vec_high(s
, rd
);
8086 tcg_temp_free_i64(tcg_round
);
8090 /* SHL/SLI - Vector shift left */
8091 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8092 int immh
, int immb
, int opcode
, int rn
, int rd
)
8094 int size
= 32 - clz32(immh
) - 1;
8095 int immhb
= immh
<< 3 | immb
;
8096 int shift
= immhb
- (8 << size
);
8097 int dsize
= is_q
? 128 : 64;
8098 int esize
= 8 << size
;
8099 int elements
= dsize
/esize
;
8100 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8101 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8104 if (extract32(immh
, 3, 1) && !is_q
) {
8105 unallocated_encoding(s
);
8109 if (size
> 3 && !is_q
) {
8110 unallocated_encoding(s
);
8114 if (!fp_access_check(s
)) {
8118 for (i
= 0; i
< elements
; i
++) {
8119 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8121 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8124 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8126 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8130 clear_vec_high(s
, rd
);
8134 /* USHLL/SHLL - Vector shift left with widening */
8135 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8136 int immh
, int immb
, int opcode
, int rn
, int rd
)
8138 int size
= 32 - clz32(immh
) - 1;
8139 int immhb
= immh
<< 3 | immb
;
8140 int shift
= immhb
- (8 << size
);
8142 int esize
= 8 << size
;
8143 int elements
= dsize
/esize
;
8144 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8145 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8149 unallocated_encoding(s
);
8153 if (!fp_access_check(s
)) {
8157 /* For the LL variants the store is larger than the load,
8158 * so if rd == rn we would overwrite parts of our input.
8159 * So load everything right now and use shifts in the main loop.
8161 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8163 for (i
= 0; i
< elements
; i
++) {
8164 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8165 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8166 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8167 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8171 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8172 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8173 int immh
, int immb
, int opcode
, int rn
, int rd
)
8175 int immhb
= immh
<< 3 | immb
;
8176 int size
= 32 - clz32(immh
) - 1;
8178 int esize
= 8 << size
;
8179 int elements
= dsize
/esize
;
8180 int shift
= (2 * esize
) - immhb
;
8181 bool round
= extract32(opcode
, 0, 1);
8182 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8186 if (extract32(immh
, 3, 1)) {
8187 unallocated_encoding(s
);
8191 if (!fp_access_check(s
)) {
8195 tcg_rn
= tcg_temp_new_i64();
8196 tcg_rd
= tcg_temp_new_i64();
8197 tcg_final
= tcg_temp_new_i64();
8198 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8201 uint64_t round_const
= 1ULL << (shift
- 1);
8202 tcg_round
= tcg_const_i64(round_const
);
8204 TCGV_UNUSED_I64(tcg_round
);
8207 for (i
= 0; i
< elements
; i
++) {
8208 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8209 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8210 false, true, size
+1, shift
);
8212 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8216 clear_vec_high(s
, rd
);
8217 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8219 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8223 tcg_temp_free_i64(tcg_round
);
8225 tcg_temp_free_i64(tcg_rn
);
8226 tcg_temp_free_i64(tcg_rd
);
8227 tcg_temp_free_i64(tcg_final
);
8232 /* C3.6.14 AdvSIMD shift by immediate
8233 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8234 * +---+---+---+-------------+------+------+--------+---+------+------+
8235 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8236 * +---+---+---+-------------+------+------+--------+---+------+------+
8238 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8240 int rd
= extract32(insn
, 0, 5);
8241 int rn
= extract32(insn
, 5, 5);
8242 int opcode
= extract32(insn
, 11, 5);
8243 int immb
= extract32(insn
, 16, 3);
8244 int immh
= extract32(insn
, 19, 4);
8245 bool is_u
= extract32(insn
, 29, 1);
8246 bool is_q
= extract32(insn
, 30, 1);
8249 case 0x08: /* SRI */
8251 unallocated_encoding(s
);
8255 case 0x00: /* SSHR / USHR */
8256 case 0x02: /* SSRA / USRA (accumulate) */
8257 case 0x04: /* SRSHR / URSHR (rounding) */
8258 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8259 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8261 case 0x0a: /* SHL / SLI */
8262 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8264 case 0x10: /* SHRN */
8265 case 0x11: /* RSHRN / SQRSHRUN */
8267 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8270 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8273 case 0x12: /* SQSHRN / UQSHRN */
8274 case 0x13: /* SQRSHRN / UQRSHRN */
8275 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8278 case 0x14: /* SSHLL / USHLL */
8279 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8281 case 0x1c: /* SCVTF / UCVTF */
8282 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8285 case 0xc: /* SQSHLU */
8287 unallocated_encoding(s
);
8290 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8292 case 0xe: /* SQSHL, UQSHL */
8293 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8295 case 0x1f: /* FCVTZS/ FCVTZU */
8296 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8299 unallocated_encoding(s
);
8304 /* Generate code to do a "long" addition or subtraction, ie one done in
8305 * TCGv_i64 on vector lanes twice the width specified by size.
8307 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8308 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8310 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8311 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8312 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8313 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8315 NeonGenTwo64OpFn
*genfn
;
8318 genfn
= fns
[size
][is_sub
];
8319 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8322 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8323 int opcode
, int rd
, int rn
, int rm
)
8325 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8326 TCGv_i64 tcg_res
[2];
8329 tcg_res
[0] = tcg_temp_new_i64();
8330 tcg_res
[1] = tcg_temp_new_i64();
8332 /* Does this op do an adding accumulate, a subtracting accumulate,
8333 * or no accumulate at all?
8351 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8352 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8355 /* size == 2 means two 32x32->64 operations; this is worth special
8356 * casing because we can generally handle it inline.
8359 for (pass
= 0; pass
< 2; pass
++) {
8360 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8361 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8362 TCGv_i64 tcg_passres
;
8363 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8365 int elt
= pass
+ is_q
* 2;
8367 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8368 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8371 tcg_passres
= tcg_res
[pass
];
8373 tcg_passres
= tcg_temp_new_i64();
8377 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8378 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8380 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8381 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8383 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8384 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8386 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8387 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8389 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8390 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8391 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8393 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8394 tcg_temp_free_i64(tcg_tmp1
);
8395 tcg_temp_free_i64(tcg_tmp2
);
8398 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8399 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8400 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8401 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8403 case 9: /* SQDMLAL, SQDMLAL2 */
8404 case 11: /* SQDMLSL, SQDMLSL2 */
8405 case 13: /* SQDMULL, SQDMULL2 */
8406 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8407 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8408 tcg_passres
, tcg_passres
);
8411 g_assert_not_reached();
8414 if (opcode
== 9 || opcode
== 11) {
8415 /* saturating accumulate ops */
8417 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8419 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8420 tcg_res
[pass
], tcg_passres
);
8421 } else if (accop
> 0) {
8422 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8423 } else if (accop
< 0) {
8424 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8428 tcg_temp_free_i64(tcg_passres
);
8431 tcg_temp_free_i64(tcg_op1
);
8432 tcg_temp_free_i64(tcg_op2
);
8435 /* size 0 or 1, generally helper functions */
8436 for (pass
= 0; pass
< 2; pass
++) {
8437 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8438 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8439 TCGv_i64 tcg_passres
;
8440 int elt
= pass
+ is_q
* 2;
8442 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8443 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8446 tcg_passres
= tcg_res
[pass
];
8448 tcg_passres
= tcg_temp_new_i64();
8452 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8453 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8455 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8456 static NeonGenWidenFn
* const widenfns
[2][2] = {
8457 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8458 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8460 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8462 widenfn(tcg_op2_64
, tcg_op2
);
8463 widenfn(tcg_passres
, tcg_op1
);
8464 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8465 tcg_passres
, tcg_op2_64
);
8466 tcg_temp_free_i64(tcg_op2_64
);
8469 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8470 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8473 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8475 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8479 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8481 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8485 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8486 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8487 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8490 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8492 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8496 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8498 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8502 case 9: /* SQDMLAL, SQDMLAL2 */
8503 case 11: /* SQDMLSL, SQDMLSL2 */
8504 case 13: /* SQDMULL, SQDMULL2 */
8506 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8507 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8508 tcg_passres
, tcg_passres
);
8510 case 14: /* PMULL */
8512 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8515 g_assert_not_reached();
8517 tcg_temp_free_i32(tcg_op1
);
8518 tcg_temp_free_i32(tcg_op2
);
8521 if (opcode
== 9 || opcode
== 11) {
8522 /* saturating accumulate ops */
8524 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8526 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8530 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8531 tcg_res
[pass
], tcg_passres
);
8533 tcg_temp_free_i64(tcg_passres
);
8538 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8539 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8540 tcg_temp_free_i64(tcg_res
[0]);
8541 tcg_temp_free_i64(tcg_res
[1]);
8544 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8545 int opcode
, int rd
, int rn
, int rm
)
8547 TCGv_i64 tcg_res
[2];
8548 int part
= is_q
? 2 : 0;
8551 for (pass
= 0; pass
< 2; pass
++) {
8552 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8553 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8554 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8555 static NeonGenWidenFn
* const widenfns
[3][2] = {
8556 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8557 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8558 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8560 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8562 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8563 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8564 widenfn(tcg_op2_wide
, tcg_op2
);
8565 tcg_temp_free_i32(tcg_op2
);
8566 tcg_res
[pass
] = tcg_temp_new_i64();
8567 gen_neon_addl(size
, (opcode
== 3),
8568 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8569 tcg_temp_free_i64(tcg_op1
);
8570 tcg_temp_free_i64(tcg_op2_wide
);
8573 for (pass
= 0; pass
< 2; pass
++) {
8574 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8575 tcg_temp_free_i64(tcg_res
[pass
]);
8579 static void do_narrow_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8581 tcg_gen_shri_i64(in
, in
, 32);
8582 tcg_gen_trunc_i64_i32(res
, in
);
8585 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8587 tcg_gen_addi_i64(in
, in
, 1U << 31);
8588 do_narrow_high_u32(res
, in
);
8591 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8592 int opcode
, int rd
, int rn
, int rm
)
8594 TCGv_i32 tcg_res
[2];
8595 int part
= is_q
? 2 : 0;
8598 for (pass
= 0; pass
< 2; pass
++) {
8599 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8600 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8601 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8602 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8603 { gen_helper_neon_narrow_high_u8
,
8604 gen_helper_neon_narrow_round_high_u8
},
8605 { gen_helper_neon_narrow_high_u16
,
8606 gen_helper_neon_narrow_round_high_u16
},
8607 { do_narrow_high_u32
, do_narrow_round_high_u32
},
8609 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8611 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8612 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8614 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8616 tcg_temp_free_i64(tcg_op1
);
8617 tcg_temp_free_i64(tcg_op2
);
8619 tcg_res
[pass
] = tcg_temp_new_i32();
8620 gennarrow(tcg_res
[pass
], tcg_wideres
);
8621 tcg_temp_free_i64(tcg_wideres
);
8624 for (pass
= 0; pass
< 2; pass
++) {
8625 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8626 tcg_temp_free_i32(tcg_res
[pass
]);
8629 clear_vec_high(s
, rd
);
8633 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8635 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8636 * is the only three-reg-diff instruction which produces a
8637 * 128-bit wide result from a single operation. However since
8638 * it's possible to calculate the two halves more or less
8639 * separately we just use two helper calls.
8641 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8642 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8643 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8645 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8646 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8647 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8648 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8649 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8650 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8652 tcg_temp_free_i64(tcg_op1
);
8653 tcg_temp_free_i64(tcg_op2
);
8654 tcg_temp_free_i64(tcg_res
);
8657 /* C3.6.15 AdvSIMD three different
8658 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8659 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8660 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8661 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8663 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8665 /* Instructions in this group fall into three basic classes
8666 * (in each case with the operation working on each element in
8667 * the input vectors):
8668 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8670 * (2) wide 64 x 128 -> 128
8671 * (3) narrowing 128 x 128 -> 64
8672 * Here we do initial decode, catch unallocated cases and
8673 * dispatch to separate functions for each class.
8675 int is_q
= extract32(insn
, 30, 1);
8676 int is_u
= extract32(insn
, 29, 1);
8677 int size
= extract32(insn
, 22, 2);
8678 int opcode
= extract32(insn
, 12, 4);
8679 int rm
= extract32(insn
, 16, 5);
8680 int rn
= extract32(insn
, 5, 5);
8681 int rd
= extract32(insn
, 0, 5);
8684 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8685 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8686 /* 64 x 128 -> 128 */
8688 unallocated_encoding(s
);
8691 if (!fp_access_check(s
)) {
8694 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8696 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8697 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8698 /* 128 x 128 -> 64 */
8700 unallocated_encoding(s
);
8703 if (!fp_access_check(s
)) {
8706 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8708 case 14: /* PMULL, PMULL2 */
8709 if (is_u
|| size
== 1 || size
== 2) {
8710 unallocated_encoding(s
);
8714 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
8715 unallocated_encoding(s
);
8718 if (!fp_access_check(s
)) {
8721 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8725 case 9: /* SQDMLAL, SQDMLAL2 */
8726 case 11: /* SQDMLSL, SQDMLSL2 */
8727 case 13: /* SQDMULL, SQDMULL2 */
8728 if (is_u
|| size
== 0) {
8729 unallocated_encoding(s
);
8733 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8734 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8735 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8736 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8737 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8738 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8739 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
8740 /* 64 x 64 -> 128 */
8742 unallocated_encoding(s
);
8746 if (!fp_access_check(s
)) {
8750 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8753 /* opcode 15 not allocated */
8754 unallocated_encoding(s
);
8759 /* Logic op (opcode == 3) subgroup of C3.6.16. */
8760 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
8762 int rd
= extract32(insn
, 0, 5);
8763 int rn
= extract32(insn
, 5, 5);
8764 int rm
= extract32(insn
, 16, 5);
8765 int size
= extract32(insn
, 22, 2);
8766 bool is_u
= extract32(insn
, 29, 1);
8767 bool is_q
= extract32(insn
, 30, 1);
8768 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
8771 if (!fp_access_check(s
)) {
8775 tcg_op1
= tcg_temp_new_i64();
8776 tcg_op2
= tcg_temp_new_i64();
8777 tcg_res
[0] = tcg_temp_new_i64();
8778 tcg_res
[1] = tcg_temp_new_i64();
8780 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
8781 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8782 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8787 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8790 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8793 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8796 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8801 /* B* ops need res loaded to operate on */
8802 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8807 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8809 case 1: /* BSL bitwise select */
8810 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8811 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8812 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
8814 case 2: /* BIT, bitwise insert if true */
8815 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8816 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8817 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8819 case 3: /* BIF, bitwise insert if false */
8820 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8821 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8822 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8828 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8830 tcg_gen_movi_i64(tcg_res
[1], 0);
8832 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8834 tcg_temp_free_i64(tcg_op1
);
8835 tcg_temp_free_i64(tcg_op2
);
8836 tcg_temp_free_i64(tcg_res
[0]);
8837 tcg_temp_free_i64(tcg_res
[1]);
8840 /* Helper functions for 32 bit comparisons */
8841 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8843 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
8846 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8848 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
8851 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8853 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
8856 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8858 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
8861 /* Pairwise op subgroup of C3.6.16.
8863 * This is called directly or via the handle_3same_float for float pairwise
8864 * operations where the opcode and size are calculated differently.
8866 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
8867 int size
, int rn
, int rm
, int rd
)
8872 /* Floating point operations need fpst */
8873 if (opcode
>= 0x58) {
8874 fpst
= get_fpstatus_ptr();
8876 TCGV_UNUSED_PTR(fpst
);
8879 if (!fp_access_check(s
)) {
8883 /* These operations work on the concatenated rm:rn, with each pair of
8884 * adjacent elements being operated on to produce an element in the result.
8887 TCGv_i64 tcg_res
[2];
8889 for (pass
= 0; pass
< 2; pass
++) {
8890 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8891 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8892 int passreg
= (pass
== 0) ? rn
: rm
;
8894 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
8895 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
8896 tcg_res
[pass
] = tcg_temp_new_i64();
8899 case 0x17: /* ADDP */
8900 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8902 case 0x58: /* FMAXNMP */
8903 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8905 case 0x5a: /* FADDP */
8906 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8908 case 0x5e: /* FMAXP */
8909 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8911 case 0x78: /* FMINNMP */
8912 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8914 case 0x7e: /* FMINP */
8915 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8918 g_assert_not_reached();
8921 tcg_temp_free_i64(tcg_op1
);
8922 tcg_temp_free_i64(tcg_op2
);
8925 for (pass
= 0; pass
< 2; pass
++) {
8926 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8927 tcg_temp_free_i64(tcg_res
[pass
]);
8930 int maxpass
= is_q
? 4 : 2;
8931 TCGv_i32 tcg_res
[4];
8933 for (pass
= 0; pass
< maxpass
; pass
++) {
8934 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8935 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8936 NeonGenTwoOpFn
*genfn
= NULL
;
8937 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
8938 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
8940 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
8941 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
8942 tcg_res
[pass
] = tcg_temp_new_i32();
8945 case 0x17: /* ADDP */
8947 static NeonGenTwoOpFn
* const fns
[3] = {
8948 gen_helper_neon_padd_u8
,
8949 gen_helper_neon_padd_u16
,
8955 case 0x14: /* SMAXP, UMAXP */
8957 static NeonGenTwoOpFn
* const fns
[3][2] = {
8958 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
8959 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
8960 { gen_max_s32
, gen_max_u32
},
8962 genfn
= fns
[size
][u
];
8965 case 0x15: /* SMINP, UMINP */
8967 static NeonGenTwoOpFn
* const fns
[3][2] = {
8968 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
8969 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
8970 { gen_min_s32
, gen_min_u32
},
8972 genfn
= fns
[size
][u
];
8975 /* The FP operations are all on single floats (32 bit) */
8976 case 0x58: /* FMAXNMP */
8977 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8979 case 0x5a: /* FADDP */
8980 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8982 case 0x5e: /* FMAXP */
8983 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8985 case 0x78: /* FMINNMP */
8986 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8988 case 0x7e: /* FMINP */
8989 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8992 g_assert_not_reached();
8995 /* FP ops called directly, otherwise call now */
8997 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9000 tcg_temp_free_i32(tcg_op1
);
9001 tcg_temp_free_i32(tcg_op2
);
9004 for (pass
= 0; pass
< maxpass
; pass
++) {
9005 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9006 tcg_temp_free_i32(tcg_res
[pass
]);
9009 clear_vec_high(s
, rd
);
9013 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
9014 tcg_temp_free_ptr(fpst
);
9018 /* Floating point op subgroup of C3.6.16. */
9019 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
9021 /* For floating point ops, the U, size[1] and opcode bits
9022 * together indicate the operation. size[0] indicates single
9025 int fpopcode
= extract32(insn
, 11, 5)
9026 | (extract32(insn
, 23, 1) << 5)
9027 | (extract32(insn
, 29, 1) << 6);
9028 int is_q
= extract32(insn
, 30, 1);
9029 int size
= extract32(insn
, 22, 1);
9030 int rm
= extract32(insn
, 16, 5);
9031 int rn
= extract32(insn
, 5, 5);
9032 int rd
= extract32(insn
, 0, 5);
9034 int datasize
= is_q
? 128 : 64;
9035 int esize
= 32 << size
;
9036 int elements
= datasize
/ esize
;
9038 if (size
== 1 && !is_q
) {
9039 unallocated_encoding(s
);
9044 case 0x58: /* FMAXNMP */
9045 case 0x5a: /* FADDP */
9046 case 0x5e: /* FMAXP */
9047 case 0x78: /* FMINNMP */
9048 case 0x7e: /* FMINP */
9049 if (size
&& !is_q
) {
9050 unallocated_encoding(s
);
9053 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9056 case 0x1b: /* FMULX */
9057 case 0x1f: /* FRECPS */
9058 case 0x3f: /* FRSQRTS */
9059 case 0x5d: /* FACGE */
9060 case 0x7d: /* FACGT */
9061 case 0x19: /* FMLA */
9062 case 0x39: /* FMLS */
9063 case 0x18: /* FMAXNM */
9064 case 0x1a: /* FADD */
9065 case 0x1c: /* FCMEQ */
9066 case 0x1e: /* FMAX */
9067 case 0x38: /* FMINNM */
9068 case 0x3a: /* FSUB */
9069 case 0x3e: /* FMIN */
9070 case 0x5b: /* FMUL */
9071 case 0x5c: /* FCMGE */
9072 case 0x5f: /* FDIV */
9073 case 0x7a: /* FABD */
9074 case 0x7c: /* FCMGT */
9075 if (!fp_access_check(s
)) {
9079 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9082 unallocated_encoding(s
);
9087 /* Integer op subgroup of C3.6.16. */
9088 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9090 int is_q
= extract32(insn
, 30, 1);
9091 int u
= extract32(insn
, 29, 1);
9092 int size
= extract32(insn
, 22, 2);
9093 int opcode
= extract32(insn
, 11, 5);
9094 int rm
= extract32(insn
, 16, 5);
9095 int rn
= extract32(insn
, 5, 5);
9096 int rd
= extract32(insn
, 0, 5);
9100 case 0x13: /* MUL, PMUL */
9101 if (u
&& size
!= 0) {
9102 unallocated_encoding(s
);
9106 case 0x0: /* SHADD, UHADD */
9107 case 0x2: /* SRHADD, URHADD */
9108 case 0x4: /* SHSUB, UHSUB */
9109 case 0xc: /* SMAX, UMAX */
9110 case 0xd: /* SMIN, UMIN */
9111 case 0xe: /* SABD, UABD */
9112 case 0xf: /* SABA, UABA */
9113 case 0x12: /* MLA, MLS */
9115 unallocated_encoding(s
);
9119 case 0x16: /* SQDMULH, SQRDMULH */
9120 if (size
== 0 || size
== 3) {
9121 unallocated_encoding(s
);
9126 if (size
== 3 && !is_q
) {
9127 unallocated_encoding(s
);
9133 if (!fp_access_check(s
)) {
9139 for (pass
= 0; pass
< 2; pass
++) {
9140 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9141 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9142 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9144 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9145 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9147 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9149 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9151 tcg_temp_free_i64(tcg_res
);
9152 tcg_temp_free_i64(tcg_op1
);
9153 tcg_temp_free_i64(tcg_op2
);
9156 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9157 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9158 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9159 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9160 NeonGenTwoOpFn
*genfn
= NULL
;
9161 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9163 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9164 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9167 case 0x0: /* SHADD, UHADD */
9169 static NeonGenTwoOpFn
* const fns
[3][2] = {
9170 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9171 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9172 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9174 genfn
= fns
[size
][u
];
9177 case 0x1: /* SQADD, UQADD */
9179 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9180 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9181 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9182 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9184 genenvfn
= fns
[size
][u
];
9187 case 0x2: /* SRHADD, URHADD */
9189 static NeonGenTwoOpFn
* const fns
[3][2] = {
9190 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9191 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9192 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9194 genfn
= fns
[size
][u
];
9197 case 0x4: /* SHSUB, UHSUB */
9199 static NeonGenTwoOpFn
* const fns
[3][2] = {
9200 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9201 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9202 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9204 genfn
= fns
[size
][u
];
9207 case 0x5: /* SQSUB, UQSUB */
9209 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9210 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9211 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9212 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9214 genenvfn
= fns
[size
][u
];
9217 case 0x6: /* CMGT, CMHI */
9219 static NeonGenTwoOpFn
* const fns
[3][2] = {
9220 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9221 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9222 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9224 genfn
= fns
[size
][u
];
9227 case 0x7: /* CMGE, CMHS */
9229 static NeonGenTwoOpFn
* const fns
[3][2] = {
9230 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9231 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9232 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9234 genfn
= fns
[size
][u
];
9237 case 0x8: /* SSHL, USHL */
9239 static NeonGenTwoOpFn
* const fns
[3][2] = {
9240 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9241 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9242 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9244 genfn
= fns
[size
][u
];
9247 case 0x9: /* SQSHL, UQSHL */
9249 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9250 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9251 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9252 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9254 genenvfn
= fns
[size
][u
];
9257 case 0xa: /* SRSHL, URSHL */
9259 static NeonGenTwoOpFn
* const fns
[3][2] = {
9260 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9261 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9262 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9264 genfn
= fns
[size
][u
];
9267 case 0xb: /* SQRSHL, UQRSHL */
9269 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9270 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9271 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9272 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9274 genenvfn
= fns
[size
][u
];
9277 case 0xc: /* SMAX, UMAX */
9279 static NeonGenTwoOpFn
* const fns
[3][2] = {
9280 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9281 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9282 { gen_max_s32
, gen_max_u32
},
9284 genfn
= fns
[size
][u
];
9288 case 0xd: /* SMIN, UMIN */
9290 static NeonGenTwoOpFn
* const fns
[3][2] = {
9291 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9292 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9293 { gen_min_s32
, gen_min_u32
},
9295 genfn
= fns
[size
][u
];
9298 case 0xe: /* SABD, UABD */
9299 case 0xf: /* SABA, UABA */
9301 static NeonGenTwoOpFn
* const fns
[3][2] = {
9302 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9303 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9304 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9306 genfn
= fns
[size
][u
];
9309 case 0x10: /* ADD, SUB */
9311 static NeonGenTwoOpFn
* const fns
[3][2] = {
9312 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9313 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9314 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9316 genfn
= fns
[size
][u
];
9319 case 0x11: /* CMTST, CMEQ */
9321 static NeonGenTwoOpFn
* const fns
[3][2] = {
9322 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9323 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9324 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9326 genfn
= fns
[size
][u
];
9329 case 0x13: /* MUL, PMUL */
9333 genfn
= gen_helper_neon_mul_p8
;
9336 /* fall through : MUL */
9337 case 0x12: /* MLA, MLS */
9339 static NeonGenTwoOpFn
* const fns
[3] = {
9340 gen_helper_neon_mul_u8
,
9341 gen_helper_neon_mul_u16
,
9347 case 0x16: /* SQDMULH, SQRDMULH */
9349 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9350 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9351 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9353 assert(size
== 1 || size
== 2);
9354 genenvfn
= fns
[size
- 1][u
];
9358 g_assert_not_reached();
9362 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9364 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9367 if (opcode
== 0xf || opcode
== 0x12) {
9368 /* SABA, UABA, MLA, MLS: accumulating ops */
9369 static NeonGenTwoOpFn
* const fns
[3][2] = {
9370 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9371 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9372 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9374 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9376 genfn
= fns
[size
][is_sub
];
9377 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9378 genfn(tcg_res
, tcg_op1
, tcg_res
);
9381 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9383 tcg_temp_free_i32(tcg_res
);
9384 tcg_temp_free_i32(tcg_op1
);
9385 tcg_temp_free_i32(tcg_op2
);
9390 clear_vec_high(s
, rd
);
9394 /* C3.6.16 AdvSIMD three same
9395 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9396 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9397 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9398 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9400 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9402 int opcode
= extract32(insn
, 11, 5);
9405 case 0x3: /* logic ops */
9406 disas_simd_3same_logic(s
, insn
);
9408 case 0x17: /* ADDP */
9409 case 0x14: /* SMAXP, UMAXP */
9410 case 0x15: /* SMINP, UMINP */
9412 /* Pairwise operations */
9413 int is_q
= extract32(insn
, 30, 1);
9414 int u
= extract32(insn
, 29, 1);
9415 int size
= extract32(insn
, 22, 2);
9416 int rm
= extract32(insn
, 16, 5);
9417 int rn
= extract32(insn
, 5, 5);
9418 int rd
= extract32(insn
, 0, 5);
9419 if (opcode
== 0x17) {
9420 if (u
|| (size
== 3 && !is_q
)) {
9421 unallocated_encoding(s
);
9426 unallocated_encoding(s
);
9430 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9434 /* floating point ops, sz[1] and U are part of opcode */
9435 disas_simd_3same_float(s
, insn
);
9438 disas_simd_3same_int(s
, insn
);
9443 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9444 int size
, int rn
, int rd
)
9446 /* Handle 2-reg-misc ops which are widening (so each size element
9447 * in the source becomes a 2*size element in the destination.
9448 * The only instruction like this is FCVTL.
9453 /* 32 -> 64 bit fp conversion */
9454 TCGv_i64 tcg_res
[2];
9455 int srcelt
= is_q
? 2 : 0;
9457 for (pass
= 0; pass
< 2; pass
++) {
9458 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9459 tcg_res
[pass
] = tcg_temp_new_i64();
9461 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9462 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9463 tcg_temp_free_i32(tcg_op
);
9465 for (pass
= 0; pass
< 2; pass
++) {
9466 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9467 tcg_temp_free_i64(tcg_res
[pass
]);
9470 /* 16 -> 32 bit fp conversion */
9471 int srcelt
= is_q
? 4 : 0;
9472 TCGv_i32 tcg_res
[4];
9474 for (pass
= 0; pass
< 4; pass
++) {
9475 tcg_res
[pass
] = tcg_temp_new_i32();
9477 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9478 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9481 for (pass
= 0; pass
< 4; pass
++) {
9482 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9483 tcg_temp_free_i32(tcg_res
[pass
]);
9488 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9489 bool is_q
, int size
, int rn
, int rd
)
9491 int op
= (opcode
<< 1) | u
;
9492 int opsz
= op
+ size
;
9493 int grp_size
= 3 - opsz
;
9494 int dsize
= is_q
? 128 : 64;
9498 unallocated_encoding(s
);
9502 if (!fp_access_check(s
)) {
9507 /* Special case bytes, use bswap op on each group of elements */
9508 int groups
= dsize
/ (8 << grp_size
);
9510 for (i
= 0; i
< groups
; i
++) {
9511 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9513 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9516 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9519 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9522 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9525 g_assert_not_reached();
9527 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9528 tcg_temp_free_i64(tcg_tmp
);
9531 clear_vec_high(s
, rd
);
9534 int revmask
= (1 << grp_size
) - 1;
9535 int esize
= 8 << size
;
9536 int elements
= dsize
/ esize
;
9537 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9538 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9539 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9541 for (i
= 0; i
< elements
; i
++) {
9542 int e_rev
= (i
& 0xf) ^ revmask
;
9543 int off
= e_rev
* esize
;
9544 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9546 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9547 tcg_rn
, off
- 64, esize
);
9549 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9552 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9553 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9555 tcg_temp_free_i64(tcg_rd_hi
);
9556 tcg_temp_free_i64(tcg_rd
);
9557 tcg_temp_free_i64(tcg_rn
);
9561 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9562 bool is_q
, int size
, int rn
, int rd
)
9564 /* Implement the pairwise operations from 2-misc:
9565 * SADDLP, UADDLP, SADALP, UADALP.
9566 * These all add pairs of elements in the input to produce a
9567 * double-width result element in the output (possibly accumulating).
9569 bool accum
= (opcode
== 0x6);
9570 int maxpass
= is_q
? 2 : 1;
9572 TCGv_i64 tcg_res
[2];
9575 /* 32 + 32 -> 64 op */
9576 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9578 for (pass
= 0; pass
< maxpass
; pass
++) {
9579 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9580 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9582 tcg_res
[pass
] = tcg_temp_new_i64();
9584 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9585 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9586 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9588 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9589 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9592 tcg_temp_free_i64(tcg_op1
);
9593 tcg_temp_free_i64(tcg_op2
);
9596 for (pass
= 0; pass
< maxpass
; pass
++) {
9597 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9598 NeonGenOneOpFn
*genfn
;
9599 static NeonGenOneOpFn
* const fns
[2][2] = {
9600 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9601 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9604 genfn
= fns
[size
][u
];
9606 tcg_res
[pass
] = tcg_temp_new_i64();
9608 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9609 genfn(tcg_res
[pass
], tcg_op
);
9612 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9614 gen_helper_neon_addl_u16(tcg_res
[pass
],
9615 tcg_res
[pass
], tcg_op
);
9617 gen_helper_neon_addl_u32(tcg_res
[pass
],
9618 tcg_res
[pass
], tcg_op
);
9621 tcg_temp_free_i64(tcg_op
);
9625 tcg_res
[1] = tcg_const_i64(0);
9627 for (pass
= 0; pass
< 2; pass
++) {
9628 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9629 tcg_temp_free_i64(tcg_res
[pass
]);
9633 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9635 /* Implement SHLL and SHLL2 */
9637 int part
= is_q
? 2 : 0;
9638 TCGv_i64 tcg_res
[2];
9640 for (pass
= 0; pass
< 2; pass
++) {
9641 static NeonGenWidenFn
* const widenfns
[3] = {
9642 gen_helper_neon_widen_u8
,
9643 gen_helper_neon_widen_u16
,
9644 tcg_gen_extu_i32_i64
,
9646 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9647 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9649 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9650 tcg_res
[pass
] = tcg_temp_new_i64();
9651 widenfn(tcg_res
[pass
], tcg_op
);
9652 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9654 tcg_temp_free_i32(tcg_op
);
9657 for (pass
= 0; pass
< 2; pass
++) {
9658 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9659 tcg_temp_free_i64(tcg_res
[pass
]);
9663 /* C3.6.17 AdvSIMD two reg misc
9664 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9665 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9666 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9667 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9669 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9671 int size
= extract32(insn
, 22, 2);
9672 int opcode
= extract32(insn
, 12, 5);
9673 bool u
= extract32(insn
, 29, 1);
9674 bool is_q
= extract32(insn
, 30, 1);
9675 int rn
= extract32(insn
, 5, 5);
9676 int rd
= extract32(insn
, 0, 5);
9677 bool need_fpstatus
= false;
9678 bool need_rmode
= false;
9681 TCGv_ptr tcg_fpstatus
;
9684 case 0x0: /* REV64, REV32 */
9685 case 0x1: /* REV16 */
9686 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9688 case 0x5: /* CNT, NOT, RBIT */
9689 if (u
&& size
== 0) {
9690 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9693 } else if (u
&& size
== 1) {
9696 } else if (!u
&& size
== 0) {
9700 unallocated_encoding(s
);
9702 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9703 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9705 unallocated_encoding(s
);
9708 if (!fp_access_check(s
)) {
9712 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9714 case 0x4: /* CLS, CLZ */
9716 unallocated_encoding(s
);
9720 case 0x2: /* SADDLP, UADDLP */
9721 case 0x6: /* SADALP, UADALP */
9723 unallocated_encoding(s
);
9726 if (!fp_access_check(s
)) {
9729 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9731 case 0x13: /* SHLL, SHLL2 */
9732 if (u
== 0 || size
== 3) {
9733 unallocated_encoding(s
);
9736 if (!fp_access_check(s
)) {
9739 handle_shll(s
, is_q
, size
, rn
, rd
);
9741 case 0xa: /* CMLT */
9743 unallocated_encoding(s
);
9747 case 0x8: /* CMGT, CMGE */
9748 case 0x9: /* CMEQ, CMLE */
9749 case 0xb: /* ABS, NEG */
9750 if (size
== 3 && !is_q
) {
9751 unallocated_encoding(s
);
9755 case 0x3: /* SUQADD, USQADD */
9756 if (size
== 3 && !is_q
) {
9757 unallocated_encoding(s
);
9760 if (!fp_access_check(s
)) {
9763 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
9765 case 0x7: /* SQABS, SQNEG */
9766 if (size
== 3 && !is_q
) {
9767 unallocated_encoding(s
);
9775 /* Floating point: U, size[1] and opcode indicate operation;
9776 * size[0] indicates single or double precision.
9778 int is_double
= extract32(size
, 0, 1);
9779 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9780 size
= is_double
? 3 : 2;
9782 case 0x2f: /* FABS */
9783 case 0x6f: /* FNEG */
9784 if (size
== 3 && !is_q
) {
9785 unallocated_encoding(s
);
9789 case 0x1d: /* SCVTF */
9790 case 0x5d: /* UCVTF */
9792 bool is_signed
= (opcode
== 0x1d) ? true : false;
9793 int elements
= is_double
? 2 : is_q
? 4 : 2;
9794 if (is_double
&& !is_q
) {
9795 unallocated_encoding(s
);
9798 if (!fp_access_check(s
)) {
9801 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
9804 case 0x2c: /* FCMGT (zero) */
9805 case 0x2d: /* FCMEQ (zero) */
9806 case 0x2e: /* FCMLT (zero) */
9807 case 0x6c: /* FCMGE (zero) */
9808 case 0x6d: /* FCMLE (zero) */
9809 if (size
== 3 && !is_q
) {
9810 unallocated_encoding(s
);
9813 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9815 case 0x7f: /* FSQRT */
9816 if (size
== 3 && !is_q
) {
9817 unallocated_encoding(s
);
9821 case 0x1a: /* FCVTNS */
9822 case 0x1b: /* FCVTMS */
9823 case 0x3a: /* FCVTPS */
9824 case 0x3b: /* FCVTZS */
9825 case 0x5a: /* FCVTNU */
9826 case 0x5b: /* FCVTMU */
9827 case 0x7a: /* FCVTPU */
9828 case 0x7b: /* FCVTZU */
9829 need_fpstatus
= true;
9831 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9832 if (size
== 3 && !is_q
) {
9833 unallocated_encoding(s
);
9837 case 0x5c: /* FCVTAU */
9838 case 0x1c: /* FCVTAS */
9839 need_fpstatus
= true;
9841 rmode
= FPROUNDING_TIEAWAY
;
9842 if (size
== 3 && !is_q
) {
9843 unallocated_encoding(s
);
9847 case 0x3c: /* URECPE */
9849 unallocated_encoding(s
);
9853 case 0x3d: /* FRECPE */
9854 case 0x7d: /* FRSQRTE */
9855 if (size
== 3 && !is_q
) {
9856 unallocated_encoding(s
);
9859 if (!fp_access_check(s
)) {
9862 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9864 case 0x56: /* FCVTXN, FCVTXN2 */
9866 unallocated_encoding(s
);
9870 case 0x16: /* FCVTN, FCVTN2 */
9871 /* handle_2misc_narrow does a 2*size -> size operation, but these
9872 * instructions encode the source size rather than dest size.
9874 if (!fp_access_check(s
)) {
9877 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
9879 case 0x17: /* FCVTL, FCVTL2 */
9880 if (!fp_access_check(s
)) {
9883 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
9885 case 0x18: /* FRINTN */
9886 case 0x19: /* FRINTM */
9887 case 0x38: /* FRINTP */
9888 case 0x39: /* FRINTZ */
9890 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9892 case 0x59: /* FRINTX */
9893 case 0x79: /* FRINTI */
9894 need_fpstatus
= true;
9895 if (size
== 3 && !is_q
) {
9896 unallocated_encoding(s
);
9900 case 0x58: /* FRINTA */
9902 rmode
= FPROUNDING_TIEAWAY
;
9903 need_fpstatus
= true;
9904 if (size
== 3 && !is_q
) {
9905 unallocated_encoding(s
);
9909 case 0x7c: /* URSQRTE */
9911 unallocated_encoding(s
);
9914 need_fpstatus
= true;
9917 unallocated_encoding(s
);
9923 unallocated_encoding(s
);
9927 if (!fp_access_check(s
)) {
9931 if (need_fpstatus
) {
9932 tcg_fpstatus
= get_fpstatus_ptr();
9934 TCGV_UNUSED_PTR(tcg_fpstatus
);
9937 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9938 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
9940 TCGV_UNUSED_I32(tcg_rmode
);
9944 /* All 64-bit element operations can be shared with scalar 2misc */
9947 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9948 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9949 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9951 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9953 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
9954 tcg_rmode
, tcg_fpstatus
);
9956 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9958 tcg_temp_free_i64(tcg_res
);
9959 tcg_temp_free_i64(tcg_op
);
9964 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9965 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9966 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9969 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9972 /* Special cases for 32 bit elements */
9974 case 0xa: /* CMLT */
9975 /* 32 bit integer comparison against zero, result is
9976 * test ? (2^32 - 1) : 0. We implement via setcond(test)
9981 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
9982 tcg_gen_neg_i32(tcg_res
, tcg_res
);
9984 case 0x8: /* CMGT, CMGE */
9985 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9987 case 0x9: /* CMEQ, CMLE */
9988 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9992 gen_helper_clz32(tcg_res
, tcg_op
);
9994 gen_helper_cls32(tcg_res
, tcg_op
);
9997 case 0x7: /* SQABS, SQNEG */
9999 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
10001 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
10004 case 0xb: /* ABS, NEG */
10006 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10008 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10009 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10010 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
10011 tcg_zero
, tcg_op
, tcg_res
);
10012 tcg_temp_free_i32(tcg_zero
);
10015 case 0x2f: /* FABS */
10016 gen_helper_vfp_abss(tcg_res
, tcg_op
);
10018 case 0x6f: /* FNEG */
10019 gen_helper_vfp_negs(tcg_res
, tcg_op
);
10021 case 0x7f: /* FSQRT */
10022 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
10024 case 0x1a: /* FCVTNS */
10025 case 0x1b: /* FCVTMS */
10026 case 0x1c: /* FCVTAS */
10027 case 0x3a: /* FCVTPS */
10028 case 0x3b: /* FCVTZS */
10030 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10031 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
10032 tcg_shift
, tcg_fpstatus
);
10033 tcg_temp_free_i32(tcg_shift
);
10036 case 0x5a: /* FCVTNU */
10037 case 0x5b: /* FCVTMU */
10038 case 0x5c: /* FCVTAU */
10039 case 0x7a: /* FCVTPU */
10040 case 0x7b: /* FCVTZU */
10042 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10043 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10044 tcg_shift
, tcg_fpstatus
);
10045 tcg_temp_free_i32(tcg_shift
);
10048 case 0x18: /* FRINTN */
10049 case 0x19: /* FRINTM */
10050 case 0x38: /* FRINTP */
10051 case 0x39: /* FRINTZ */
10052 case 0x58: /* FRINTA */
10053 case 0x79: /* FRINTI */
10054 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10056 case 0x59: /* FRINTX */
10057 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10059 case 0x7c: /* URSQRTE */
10060 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10063 g_assert_not_reached();
10066 /* Use helpers for 8 and 16 bit elements */
10068 case 0x5: /* CNT, RBIT */
10069 /* For these two insns size is part of the opcode specifier
10070 * (handled earlier); they always operate on byte elements.
10073 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10075 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10078 case 0x7: /* SQABS, SQNEG */
10080 NeonGenOneOpEnvFn
*genfn
;
10081 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10082 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10083 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10085 genfn
= fns
[size
][u
];
10086 genfn(tcg_res
, cpu_env
, tcg_op
);
10089 case 0x8: /* CMGT, CMGE */
10090 case 0x9: /* CMEQ, CMLE */
10091 case 0xa: /* CMLT */
10093 static NeonGenTwoOpFn
* const fns
[3][2] = {
10094 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10095 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10096 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10098 NeonGenTwoOpFn
*genfn
;
10101 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10103 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10104 comp
= (opcode
- 0x8) * 2 + u
;
10105 /* ...but LE, LT are implemented as reverse GE, GT */
10106 reverse
= (comp
> 2);
10110 genfn
= fns
[comp
][size
];
10112 genfn(tcg_res
, tcg_zero
, tcg_op
);
10114 genfn(tcg_res
, tcg_op
, tcg_zero
);
10116 tcg_temp_free_i32(tcg_zero
);
10119 case 0xb: /* ABS, NEG */
10121 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10123 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10125 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10127 tcg_temp_free_i32(tcg_zero
);
10130 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10132 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10136 case 0x4: /* CLS, CLZ */
10139 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10141 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10145 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10147 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10152 g_assert_not_reached();
10156 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10158 tcg_temp_free_i32(tcg_res
);
10159 tcg_temp_free_i32(tcg_op
);
10163 clear_vec_high(s
, rd
);
10167 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10168 tcg_temp_free_i32(tcg_rmode
);
10170 if (need_fpstatus
) {
10171 tcg_temp_free_ptr(tcg_fpstatus
);
10175 /* C3.6.13 AdvSIMD scalar x indexed element
10176 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10177 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10178 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10179 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10180 * C3.6.18 AdvSIMD vector x indexed element
10181 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10182 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10183 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10184 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10186 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10188 /* This encoding has two kinds of instruction:
10189 * normal, where we perform elt x idxelt => elt for each
10190 * element in the vector
10191 * long, where we perform elt x idxelt and generate a result of
10192 * double the width of the input element
10193 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10195 bool is_scalar
= extract32(insn
, 28, 1);
10196 bool is_q
= extract32(insn
, 30, 1);
10197 bool u
= extract32(insn
, 29, 1);
10198 int size
= extract32(insn
, 22, 2);
10199 int l
= extract32(insn
, 21, 1);
10200 int m
= extract32(insn
, 20, 1);
10201 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10202 int rm
= extract32(insn
, 16, 4);
10203 int opcode
= extract32(insn
, 12, 4);
10204 int h
= extract32(insn
, 11, 1);
10205 int rn
= extract32(insn
, 5, 5);
10206 int rd
= extract32(insn
, 0, 5);
10207 bool is_long
= false;
10208 bool is_fp
= false;
10213 case 0x0: /* MLA */
10214 case 0x4: /* MLS */
10215 if (!u
|| is_scalar
) {
10216 unallocated_encoding(s
);
10220 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10221 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10222 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10224 unallocated_encoding(s
);
10229 case 0x3: /* SQDMLAL, SQDMLAL2 */
10230 case 0x7: /* SQDMLSL, SQDMLSL2 */
10231 case 0xb: /* SQDMULL, SQDMULL2 */
10234 case 0xc: /* SQDMULH */
10235 case 0xd: /* SQRDMULH */
10237 unallocated_encoding(s
);
10241 case 0x8: /* MUL */
10242 if (u
|| is_scalar
) {
10243 unallocated_encoding(s
);
10247 case 0x1: /* FMLA */
10248 case 0x5: /* FMLS */
10250 unallocated_encoding(s
);
10254 case 0x9: /* FMUL, FMULX */
10255 if (!extract32(size
, 1, 1)) {
10256 unallocated_encoding(s
);
10262 unallocated_encoding(s
);
10267 /* low bit of size indicates single/double */
10268 size
= extract32(size
, 0, 1) ? 3 : 2;
10270 index
= h
<< 1 | l
;
10273 unallocated_encoding(s
);
10282 index
= h
<< 2 | l
<< 1 | m
;
10285 index
= h
<< 1 | l
;
10289 unallocated_encoding(s
);
10294 if (!fp_access_check(s
)) {
10299 fpst
= get_fpstatus_ptr();
10301 TCGV_UNUSED_PTR(fpst
);
10305 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10308 assert(is_fp
&& is_q
&& !is_long
);
10310 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10312 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10313 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10314 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10316 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10319 case 0x5: /* FMLS */
10320 /* As usual for ARM, separate negation for fused multiply-add */
10321 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10323 case 0x1: /* FMLA */
10324 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10325 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10327 case 0x9: /* FMUL, FMULX */
10329 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10331 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10335 g_assert_not_reached();
10338 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10339 tcg_temp_free_i64(tcg_op
);
10340 tcg_temp_free_i64(tcg_res
);
10344 clear_vec_high(s
, rd
);
10347 tcg_temp_free_i64(tcg_idx
);
10348 } else if (!is_long
) {
10349 /* 32 bit floating point, or 16 or 32 bit integer.
10350 * For the 16 bit scalar case we use the usual Neon helpers and
10351 * rely on the fact that 0 op 0 == 0 with no side effects.
10353 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10354 int pass
, maxpasses
;
10359 maxpasses
= is_q
? 4 : 2;
10362 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10364 if (size
== 1 && !is_scalar
) {
10365 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10366 * the index into both halves of the 32 bit tcg_idx and then use
10367 * the usual Neon helpers.
10369 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10372 for (pass
= 0; pass
< maxpasses
; pass
++) {
10373 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10374 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10376 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10379 case 0x0: /* MLA */
10380 case 0x4: /* MLS */
10381 case 0x8: /* MUL */
10383 static NeonGenTwoOpFn
* const fns
[2][2] = {
10384 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10385 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10387 NeonGenTwoOpFn
*genfn
;
10388 bool is_sub
= opcode
== 0x4;
10391 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10393 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10395 if (opcode
== 0x8) {
10398 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10399 genfn
= fns
[size
- 1][is_sub
];
10400 genfn(tcg_res
, tcg_op
, tcg_res
);
10403 case 0x5: /* FMLS */
10404 /* As usual for ARM, separate negation for fused multiply-add */
10405 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10407 case 0x1: /* FMLA */
10408 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10409 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10411 case 0x9: /* FMUL, FMULX */
10413 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10415 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10418 case 0xc: /* SQDMULH */
10420 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10423 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10427 case 0xd: /* SQRDMULH */
10429 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10432 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10437 g_assert_not_reached();
10441 write_fp_sreg(s
, rd
, tcg_res
);
10443 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10446 tcg_temp_free_i32(tcg_op
);
10447 tcg_temp_free_i32(tcg_res
);
10450 tcg_temp_free_i32(tcg_idx
);
10453 clear_vec_high(s
, rd
);
10456 /* long ops: 16x16->32 or 32x32->64 */
10457 TCGv_i64 tcg_res
[2];
10459 bool satop
= extract32(opcode
, 0, 1);
10460 TCGMemOp memop
= MO_32
;
10467 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10469 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10471 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10472 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10473 TCGv_i64 tcg_passres
;
10479 passelt
= pass
+ (is_q
* 2);
10482 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10484 tcg_res
[pass
] = tcg_temp_new_i64();
10486 if (opcode
== 0xa || opcode
== 0xb) {
10487 /* Non-accumulating ops */
10488 tcg_passres
= tcg_res
[pass
];
10490 tcg_passres
= tcg_temp_new_i64();
10493 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10494 tcg_temp_free_i64(tcg_op
);
10497 /* saturating, doubling */
10498 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10499 tcg_passres
, tcg_passres
);
10502 if (opcode
== 0xa || opcode
== 0xb) {
10506 /* Accumulating op: handle accumulate step */
10507 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10510 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10511 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10513 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10514 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10516 case 0x7: /* SQDMLSL, SQDMLSL2 */
10517 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10519 case 0x3: /* SQDMLAL, SQDMLAL2 */
10520 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10525 g_assert_not_reached();
10527 tcg_temp_free_i64(tcg_passres
);
10529 tcg_temp_free_i64(tcg_idx
);
10532 clear_vec_high(s
, rd
);
10535 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10538 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10541 /* The simplest way to handle the 16x16 indexed ops is to
10542 * duplicate the index into both halves of the 32 bit tcg_idx
10543 * and then use the usual Neon helpers.
10545 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10548 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10549 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10550 TCGv_i64 tcg_passres
;
10553 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10555 read_vec_element_i32(s
, tcg_op
, rn
,
10556 pass
+ (is_q
* 2), MO_32
);
10559 tcg_res
[pass
] = tcg_temp_new_i64();
10561 if (opcode
== 0xa || opcode
== 0xb) {
10562 /* Non-accumulating ops */
10563 tcg_passres
= tcg_res
[pass
];
10565 tcg_passres
= tcg_temp_new_i64();
10568 if (memop
& MO_SIGN
) {
10569 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10571 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10574 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10575 tcg_passres
, tcg_passres
);
10577 tcg_temp_free_i32(tcg_op
);
10579 if (opcode
== 0xa || opcode
== 0xb) {
10583 /* Accumulating op: handle accumulate step */
10584 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10587 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10588 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10591 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10592 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10595 case 0x7: /* SQDMLSL, SQDMLSL2 */
10596 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10598 case 0x3: /* SQDMLAL, SQDMLAL2 */
10599 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10604 g_assert_not_reached();
10606 tcg_temp_free_i64(tcg_passres
);
10608 tcg_temp_free_i32(tcg_idx
);
10611 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10616 tcg_res
[1] = tcg_const_i64(0);
10619 for (pass
= 0; pass
< 2; pass
++) {
10620 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10621 tcg_temp_free_i64(tcg_res
[pass
]);
10625 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10626 tcg_temp_free_ptr(fpst
);
10630 /* C3.6.19 Crypto AES
10631 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10632 * +-----------------+------+-----------+--------+-----+------+------+
10633 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10634 * +-----------------+------+-----------+--------+-----+------+------+
10636 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10638 int size
= extract32(insn
, 22, 2);
10639 int opcode
= extract32(insn
, 12, 5);
10640 int rn
= extract32(insn
, 5, 5);
10641 int rd
= extract32(insn
, 0, 5);
10643 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10644 CryptoThreeOpEnvFn
*genfn
;
10646 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10648 unallocated_encoding(s
);
10653 case 0x4: /* AESE */
10655 genfn
= gen_helper_crypto_aese
;
10657 case 0x6: /* AESMC */
10659 genfn
= gen_helper_crypto_aesmc
;
10661 case 0x5: /* AESD */
10663 genfn
= gen_helper_crypto_aese
;
10665 case 0x7: /* AESIMC */
10667 genfn
= gen_helper_crypto_aesmc
;
10670 unallocated_encoding(s
);
10674 /* Note that we convert the Vx register indexes into the
10675 * index within the vfp.regs[] array, so we can share the
10676 * helper with the AArch32 instructions.
10678 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10679 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10680 tcg_decrypt
= tcg_const_i32(decrypt
);
10682 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10684 tcg_temp_free_i32(tcg_rd_regno
);
10685 tcg_temp_free_i32(tcg_rn_regno
);
10686 tcg_temp_free_i32(tcg_decrypt
);
10689 /* C3.6.20 Crypto three-reg SHA
10690 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10691 * +-----------------+------+---+------+---+--------+-----+------+------+
10692 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10693 * +-----------------+------+---+------+---+--------+-----+------+------+
10695 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10697 int size
= extract32(insn
, 22, 2);
10698 int opcode
= extract32(insn
, 12, 3);
10699 int rm
= extract32(insn
, 16, 5);
10700 int rn
= extract32(insn
, 5, 5);
10701 int rd
= extract32(insn
, 0, 5);
10702 CryptoThreeOpEnvFn
*genfn
;
10703 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
10704 int feature
= ARM_FEATURE_V8_SHA256
;
10707 unallocated_encoding(s
);
10712 case 0: /* SHA1C */
10713 case 1: /* SHA1P */
10714 case 2: /* SHA1M */
10715 case 3: /* SHA1SU0 */
10717 feature
= ARM_FEATURE_V8_SHA1
;
10719 case 4: /* SHA256H */
10720 genfn
= gen_helper_crypto_sha256h
;
10722 case 5: /* SHA256H2 */
10723 genfn
= gen_helper_crypto_sha256h2
;
10725 case 6: /* SHA256SU1 */
10726 genfn
= gen_helper_crypto_sha256su1
;
10729 unallocated_encoding(s
);
10733 if (!arm_dc_feature(s
, feature
)) {
10734 unallocated_encoding(s
);
10738 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10739 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10740 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
10743 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
10745 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
10747 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
10748 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
10749 tcg_temp_free_i32(tcg_opcode
);
10752 tcg_temp_free_i32(tcg_rd_regno
);
10753 tcg_temp_free_i32(tcg_rn_regno
);
10754 tcg_temp_free_i32(tcg_rm_regno
);
10757 /* C3.6.21 Crypto two-reg SHA
10758 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10759 * +-----------------+------+-----------+--------+-----+------+------+
10760 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10761 * +-----------------+------+-----------+--------+-----+------+------+
10763 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
10765 int size
= extract32(insn
, 22, 2);
10766 int opcode
= extract32(insn
, 12, 5);
10767 int rn
= extract32(insn
, 5, 5);
10768 int rd
= extract32(insn
, 0, 5);
10769 CryptoTwoOpEnvFn
*genfn
;
10771 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
10774 unallocated_encoding(s
);
10779 case 0: /* SHA1H */
10780 feature
= ARM_FEATURE_V8_SHA1
;
10781 genfn
= gen_helper_crypto_sha1h
;
10783 case 1: /* SHA1SU1 */
10784 feature
= ARM_FEATURE_V8_SHA1
;
10785 genfn
= gen_helper_crypto_sha1su1
;
10787 case 2: /* SHA256SU0 */
10788 feature
= ARM_FEATURE_V8_SHA256
;
10789 genfn
= gen_helper_crypto_sha256su0
;
10792 unallocated_encoding(s
);
10796 if (!arm_dc_feature(s
, feature
)) {
10797 unallocated_encoding(s
);
10801 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10802 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10804 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
10806 tcg_temp_free_i32(tcg_rd_regno
);
10807 tcg_temp_free_i32(tcg_rn_regno
);
10810 /* C3.6 Data processing - SIMD, inc Crypto
10812 * As the decode gets a little complex we are using a table based
10813 * approach for this part of the decode.
10815 static const AArch64DecodeTable data_proc_simd
[] = {
10816 /* pattern , mask , fn */
10817 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
10818 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
10819 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
10820 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
10821 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
10822 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
10823 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
10824 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
10825 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
10826 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
10827 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
10828 { 0x2e000000, 0xbf208400, disas_simd_ext
},
10829 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
10830 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
10831 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
10832 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
10833 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
10834 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
10835 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
10836 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
10837 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
10838 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
10839 { 0x00000000, 0x00000000, NULL
}
10842 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
10844 /* Note that this is called with all non-FP cases from
10845 * table C3-6 so it must UNDEF for entries not specifically
10846 * allocated to instructions in that table.
10848 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
10852 unallocated_encoding(s
);
10856 /* C3.6 Data processing - SIMD and floating point */
10857 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
10859 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
10860 disas_data_proc_fp(s
, insn
);
10862 /* SIMD, including crypto */
10863 disas_data_proc_simd(s
, insn
);
10867 /* C3.1 A64 instruction index by encoding */
10868 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
10872 insn
= arm_ldl_code(env
, s
->pc
, s
->bswap_code
);
10876 s
->fp_access_checked
= false;
10878 switch (extract32(insn
, 25, 4)) {
10879 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
10880 unallocated_encoding(s
);
10882 case 0x8: case 0x9: /* Data processing - immediate */
10883 disas_data_proc_imm(s
, insn
);
10885 case 0xa: case 0xb: /* Branch, exception generation and system insns */
10886 disas_b_exc_sys(s
, insn
);
10891 case 0xe: /* Loads and stores */
10892 disas_ldst(s
, insn
);
10895 case 0xd: /* Data processing - register */
10896 disas_data_proc_reg(s
, insn
);
10899 case 0xf: /* Data processing - SIMD and floating point */
10900 disas_data_proc_simd_fp(s
, insn
);
10903 assert(FALSE
); /* all 15 cases should be handled above */
10907 /* if we allocated any temporaries, free them here */
10911 void gen_intermediate_code_internal_a64(ARMCPU
*cpu
,
10912 TranslationBlock
*tb
,
10915 CPUState
*cs
= CPU(cpu
);
10916 CPUARMState
*env
= &cpu
->env
;
10917 DisasContext dc1
, *dc
= &dc1
;
10919 uint16_t *gen_opc_end
;
10921 target_ulong pc_start
;
10922 target_ulong next_page_start
;
10930 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
10932 dc
->is_jmp
= DISAS_NEXT
;
10934 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
10939 dc
->bswap_code
= 0;
10940 dc
->condexec_mask
= 0;
10941 dc
->condexec_cond
= 0;
10942 dc
->mmu_idx
= ARM_TBFLAG_MMUIDX(tb
->flags
);
10943 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
10944 #if !defined(CONFIG_USER_ONLY)
10945 dc
->user
= (dc
->current_el
== 0);
10947 dc
->cpacr_fpen
= ARM_TBFLAG_AA64_FPEN(tb
->flags
);
10949 dc
->vec_stride
= 0;
10950 dc
->cp_regs
= cpu
->cp_regs
;
10951 dc
->features
= env
->features
;
10953 /* Single step state. The code-generation logic here is:
10955 * generate code with no special handling for single-stepping (except
10956 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
10957 * this happens anyway because those changes are all system register or
10959 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
10960 * emit code for one insn
10961 * emit code to clear PSTATE.SS
10962 * emit code to generate software step exception for completed step
10963 * end TB (as usual for having generated an exception)
10964 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
10965 * emit code to generate a software step exception
10968 dc
->ss_active
= ARM_TBFLAG_AA64_SS_ACTIVE(tb
->flags
);
10969 dc
->pstate_ss
= ARM_TBFLAG_AA64_PSTATE_SS(tb
->flags
);
10970 dc
->is_ldex
= false;
10971 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
10973 init_tmp_a64_array(dc
);
10975 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
10978 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
10979 if (max_insns
== 0) {
10980 max_insns
= CF_COUNT_MASK
;
10985 tcg_clear_temp_count();
10988 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
10989 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
10990 if (bp
->pc
== dc
->pc
) {
10991 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
10992 /* Advance PC so that clearing the breakpoint will
10993 invalidate this TB. */
10995 goto done_generating
;
11001 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
11005 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
11008 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
11009 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
11010 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
11013 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
11017 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
11018 tcg_gen_debug_insn_start(dc
->pc
);
11021 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11022 /* Singlestep state is Active-pending.
11023 * If we're in this state at the start of a TB then either
11024 * a) we just took an exception to an EL which is being debugged
11025 * and this is the first insn in the exception handler
11026 * b) debug exceptions were masked and we just unmasked them
11027 * without changing EL (eg by clearing PSTATE.D)
11028 * In either case we're going to take a swstep exception in the
11029 * "did not step an insn" case, and so the syndrome ISV and EX
11030 * bits should be zero.
11032 assert(num_insns
== 0);
11033 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0));
11034 dc
->is_jmp
= DISAS_EXC
;
11038 disas_a64_insn(env
, dc
);
11040 if (tcg_check_temp_count()) {
11041 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
11045 /* Translation stops when a conditional branch is encountered.
11046 * Otherwise the subsequent code could get translated several times.
11047 * Also stop translation when a page boundary is reached. This
11048 * ensures prefetch aborts occur at the right place.
11051 } while (!dc
->is_jmp
&& tcg_ctx
.gen_opc_ptr
< gen_opc_end
&&
11052 !cs
->singlestep_enabled
&&
11055 dc
->pc
< next_page_start
&&
11056 num_insns
< max_insns
);
11058 if (tb
->cflags
& CF_LAST_IO
) {
11062 if (unlikely(cs
->singlestep_enabled
|| dc
->ss_active
)
11063 && dc
->is_jmp
!= DISAS_EXC
) {
11064 /* Note that this means single stepping WFI doesn't halt the CPU.
11065 * For conditional branch insns this is harmless unreachable code as
11066 * gen_goto_tb() has already handled emitting the debug exception
11067 * (and thus a tb-jump is not possible when singlestepping).
11069 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
11070 if (dc
->is_jmp
!= DISAS_JUMP
) {
11071 gen_a64_set_pc_im(dc
->pc
);
11073 if (cs
->singlestep_enabled
) {
11074 gen_exception_internal(EXCP_DEBUG
);
11076 gen_step_complete_exception(dc
);
11079 switch (dc
->is_jmp
) {
11081 gen_goto_tb(dc
, 1, dc
->pc
);
11085 gen_a64_set_pc_im(dc
->pc
);
11088 /* indicate that the hash table must be used to find the next TB */
11089 tcg_gen_exit_tb(0);
11091 case DISAS_TB_JUMP
:
11096 gen_a64_set_pc_im(dc
->pc
);
11097 gen_helper_wfe(cpu_env
);
11100 /* This is a special case because we don't want to just halt the CPU
11101 * if trying to debug across a WFI.
11103 gen_a64_set_pc_im(dc
->pc
);
11104 gen_helper_wfi(cpu_env
);
11110 gen_tb_end(tb
, num_insns
);
11111 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
11114 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
11115 qemu_log("----------------\n");
11116 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11117 log_target_disas(env
, pc_start
, dc
->pc
- pc_start
,
11118 4 | (dc
->bswap_code
<< 1));
11123 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
11126 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
11129 tb
->size
= dc
->pc
- pc_start
;
11130 tb
->icount
= num_insns
;