target-ppc/mmu-hash64.c

   1 /*
   2  *  PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *  Copyright (c) 2013 David Gibson, IBM Corporation
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "sysemu/kvm.h"
  23 #include "kvm_ppc.h"
  24 #include "mmu-hash64.h"
  25
  26 //#define DEBUG_SLB
  27
  28 #ifdef DEBUG_SLB
  29 #  define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
  30 #else
  31 #  define LOG_SLB(...) do { } while (0)
  32 #endif
  33
  34 /*
  35  * Used to indicate whether we have allocated htab in the
  36  * host kernel
  37  */
  38 bool kvmppc_kern_htab;
  39 /*
  40  * SLB handling
  41  */
  42
  43 static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
  44 {
  45     uint64_t esid_256M, esid_1T;
  46     int n;
  47
  48     LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
  49
  50     esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
  51     esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
  52
  53     for (n = 0; n < env->slb_nr; n++) {
  54         ppc_slb_t *slb = &env->slb[n];
  55
  56         LOG_SLB("%s: slot %d %016" PRIx64 " %016"
  57                     PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
  58         /* We check for 1T matches on all MMUs here - if the MMU
  59          * doesn't have 1T segment support, we will have prevented 1T
  60          * entries from being inserted in the slbmte code. */
  61         if (((slb->esid == esid_256M) &&
  62              ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
  63             || ((slb->esid == esid_1T) &&
  64                 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
  65             return slb;
  66         }
  67     }
  68
  69     return NULL;
  70 }
  71
  72 void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
  73 {
  74     int i;
  75     uint64_t slbe, slbv;
  76
  77     cpu_synchronize_state(CPU(ppc_env_get_cpu(env)));
  78
  79     cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
  80     for (i = 0; i < env->slb_nr; i++) {
  81         slbe = env->slb[i].esid;
  82         slbv = env->slb[i].vsid;
  83         if (slbe == 0 && slbv == 0) {
  84             continue;
  85         }
  86         cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
  87                     i, slbe, slbv);
  88     }
  89 }
  90
  91 void helper_slbia(CPUPPCState *env)
  92 {
  93     PowerPCCPU *cpu = ppc_env_get_cpu(env);
  94     int n, do_invalidate;
  95
  96     do_invalidate = 0;
  97     /* XXX: Warning: slbia never invalidates the first segment */
  98     for (n = 1; n < env->slb_nr; n++) {
  99         ppc_slb_t *slb = &env->slb[n];
 100
 101         if (slb->esid & SLB_ESID_V) {
 102             slb->esid &= ~SLB_ESID_V;
 103             /* XXX: given the fact that segment size is 256 MB or 1TB,
 104              *      and we still don't have a tlb_flush_mask(env, n, mask)
 105              *      in QEMU, we just invalidate all TLBs
 106              */
 107             do_invalidate = 1;
 108         }
 109     }
 110     if (do_invalidate) {
 111         tlb_flush(CPU(cpu), 1);
 112     }
 113 }
 114
 115 void helper_slbie(CPUPPCState *env, target_ulong addr)
 116 {
 117     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 118     ppc_slb_t *slb;
 119
 120     slb = slb_lookup(env, addr);
 121     if (!slb) {
 122         return;
 123     }
 124
 125     if (slb->esid & SLB_ESID_V) {
 126         slb->esid &= ~SLB_ESID_V;
 127
 128         /* XXX: given the fact that segment size is 256 MB or 1TB,
 129          *      and we still don't have a tlb_flush_mask(env, n, mask)
 130          *      in QEMU, we just invalidate all TLBs
 131          */
 132         tlb_flush(CPU(cpu), 1);
 133     }
 134 }
 135
 136 int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
 137 {
 138     int slot = rb & 0xfff;
 139     ppc_slb_t *slb = &env->slb[slot];
 140
 141     if (rb & (0x1000 - env->slb_nr)) {
 142         return -1; /* Reserved bits set or slot too high */
 143     }
 144     if (rs & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
 145         return -1; /* Bad segment size */
 146     }
 147     if ((rs & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
 148         return -1; /* 1T segment on MMU that doesn't support it */
 149     }
 150
 151     /* Mask out the slot number as we store the entry */
 152     slb->esid = rb & (SLB_ESID_ESID | SLB_ESID_V);
 153     slb->vsid = rs;
 154
 155     LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
 156             " %016" PRIx64 "\n", __func__, slot, rb, rs,
 157             slb->esid, slb->vsid);
 158
 159     return 0;
 160 }
 161
 162 static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
 163                              target_ulong *rt)
 164 {
 165     int slot = rb & 0xfff;
 166     ppc_slb_t *slb = &env->slb[slot];
 167
 168     if (slot >= env->slb_nr) {
 169         return -1;
 170     }
 171
 172     *rt = slb->esid;
 173     return 0;
 174 }
 175
 176 static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
 177                              target_ulong *rt)
 178 {
 179     int slot = rb & 0xfff;
 180     ppc_slb_t *slb = &env->slb[slot];
 181
 182     if (slot >= env->slb_nr) {
 183         return -1;
 184     }
 185
 186     *rt = slb->vsid;
 187     return 0;
 188 }
 189
 190 void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
 191 {
 192     if (ppc_store_slb(env, rb, rs) < 0) {
 193         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 194                                    POWERPC_EXCP_INVAL);
 195     }
 196 }
 197
 198 target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
 199 {
 200     target_ulong rt = 0;
 201
 202     if (ppc_load_slb_esid(env, rb, &rt) < 0) {
 203         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 204                                    POWERPC_EXCP_INVAL);
 205     }
 206     return rt;
 207 }
 208
 209 target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
 210 {
 211     target_ulong rt = 0;
 212
 213     if (ppc_load_slb_vsid(env, rb, &rt) < 0) {
 214         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 215                                    POWERPC_EXCP_INVAL);
 216     }
 217     return rt;
 218 }
 219
 220 /*
 221  * 64-bit hash table MMU handling
 222  */
 223
 224 static int ppc_hash64_pte_prot(CPUPPCState *env,
 225                                ppc_slb_t *slb, ppc_hash_pte64_t pte)
 226 {
 227     unsigned pp, key;
 228     /* Some pp bit combinations have undefined behaviour, so default
 229      * to no access in those cases */
 230     int prot = 0;
 231
 232     key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
 233              : (slb->vsid & SLB_VSID_KS));
 234     pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
 235
 236     if (key == 0) {
 237         switch (pp) {
 238         case 0x0:
 239         case 0x1:
 240         case 0x2:
 241             prot = PAGE_READ | PAGE_WRITE;
 242             break;
 243
 244         case 0x3:
 245         case 0x6:
 246             prot = PAGE_READ;
 247             break;
 248         }
 249     } else {
 250         switch (pp) {
 251         case 0x0:
 252         case 0x6:
 253             prot = 0;
 254             break;
 255
 256         case 0x1:
 257         case 0x3:
 258             prot = PAGE_READ;
 259             break;
 260
 261         case 0x2:
 262             prot = PAGE_READ | PAGE_WRITE;
 263             break;
 264         }
 265     }
 266
 267     /* No execute if either noexec or guarded bits set */
 268     if (!(pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G)
 269         || (slb->vsid & SLB_VSID_N)) {
 270         prot |= PAGE_EXEC;
 271     }
 272
 273     return prot;
 274 }
 275
 276 static int ppc_hash64_amr_prot(CPUPPCState *env, ppc_hash_pte64_t pte)
 277 {
 278     int key, amrbits;
 279     int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 280
 281
 282     /* Only recent MMUs implement Virtual Page Class Key Protection */
 283     if (!(env->mmu_model & POWERPC_MMU_AMR)) {
 284         return prot;
 285     }
 286
 287     key = HPTE64_R_KEY(pte.pte1);
 288     amrbits = (env->spr[SPR_AMR] >> 2*(31 - key)) & 0x3;
 289
 290     /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
 291     /*         env->spr[SPR_AMR]); */
 292
 293     /*
 294      * A store is permitted if the AMR bit is 0. Remove write
 295      * protection if it is set.
 296      */
 297     if (amrbits & 0x2) {
 298         prot &= ~PAGE_WRITE;
 299     }
 300     /*
 301      * A load is permitted if the AMR bit is 0. Remove read
 302      * protection if it is set.
 303      */
 304     if (amrbits & 0x1) {
 305         prot &= ~PAGE_READ;
 306     }
 307
 308     return prot;
 309 }
 310
 311 uint64_t ppc_hash64_start_access(PowerPCCPU *cpu, target_ulong pte_index)
 312 {
 313     uint64_t token = 0;
 314     hwaddr pte_offset;
 315
 316     pte_offset = pte_index * HASH_PTE_SIZE_64;
 317     if (kvmppc_kern_htab) {
 318         /*
 319          * HTAB is controlled by KVM. Fetch the PTEG into a new buffer.
 320          */
 321         token = kvmppc_hash64_read_pteg(cpu, pte_index);
 322         if (token) {
 323             return token;
 324         }
 325         /*
 326          * pteg read failed, even though we have allocated htab via
 327          * kvmppc_reset_htab.
 328          */
 329         return 0;
 330     }
 331     /*
 332      * HTAB is controlled by QEMU. Just point to the internally
 333      * accessible PTEG.
 334      */
 335     if (cpu->env.external_htab) {
 336         token = (uint64_t)(uintptr_t) cpu->env.external_htab + pte_offset;
 337     } else if (cpu->env.htab_base) {
 338         token = cpu->env.htab_base + pte_offset;
 339     }
 340     return token;
 341 }
 342
 343 void ppc_hash64_stop_access(uint64_t token)
 344 {
 345     if (kvmppc_kern_htab) {
 346         kvmppc_hash64_free_pteg(token);
 347     }
 348 }
 349
 350 static hwaddr ppc_hash64_pteg_search(CPUPPCState *env, hwaddr hash,
 351                                      bool secondary, target_ulong ptem,
 352                                      ppc_hash_pte64_t *pte)
 353 {
 354     int i;
 355     uint64_t token;
 356     target_ulong pte0, pte1;
 357     target_ulong pte_index;
 358
 359     pte_index = (hash & env->htab_mask) * HPTES_PER_GROUP;
 360     token = ppc_hash64_start_access(ppc_env_get_cpu(env), pte_index);
 361     if (!token) {
 362         return -1;
 363     }
 364     for (i = 0; i < HPTES_PER_GROUP; i++) {
 365         pte0 = ppc_hash64_load_hpte0(env, token, i);
 366         pte1 = ppc_hash64_load_hpte1(env, token, i);
 367
 368         if ((pte0 & HPTE64_V_VALID)
 369             && (secondary == !!(pte0 & HPTE64_V_SECONDARY))
 370             && HPTE64_V_COMPARE(pte0, ptem)) {
 371             pte->pte0 = pte0;
 372             pte->pte1 = pte1;
 373             ppc_hash64_stop_access(token);
 374             return (pte_index + i) * HASH_PTE_SIZE_64;
 375         }
 376     }
 377     ppc_hash64_stop_access(token);
 378     /*
 379      * We didn't find a valid entry.
 380      */
 381     return -1;
 382 }
 383
 384 static uint64_t ppc_hash64_page_shift(ppc_slb_t *slb)
 385 {
 386     uint64_t epnshift;
 387
 388     /* Page size according to the SLB, which we use to generate the
 389      * EPN for hash table lookup..  When we implement more recent MMU
 390      * extensions this might be different from the actual page size
 391      * encoded in the PTE */
 392     if ((slb->vsid & SLB_VSID_LLP_MASK) == SLB_VSID_4K) {
 393         epnshift = TARGET_PAGE_BITS;
 394     } else if ((slb->vsid & SLB_VSID_LLP_MASK) == SLB_VSID_64K) {
 395         epnshift = TARGET_PAGE_BITS_64K;
 396     } else {
 397         epnshift = TARGET_PAGE_BITS_16M;
 398     }
 399     return epnshift;
 400 }
 401
 402 static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
 403                                      ppc_slb_t *slb, target_ulong eaddr,
 404                                      ppc_hash_pte64_t *pte)
 405 {
 406     hwaddr pte_offset;
 407     hwaddr hash;
 408     uint64_t vsid, epnshift, epnmask, epn, ptem;
 409
 410     epnshift = ppc_hash64_page_shift(slb);
 411     epnmask = ~((1ULL << epnshift) - 1);
 412
 413     if (slb->vsid & SLB_VSID_B) {
 414         /* 1TB segment */
 415         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
 416         epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;
 417         hash = vsid ^ (vsid << 25) ^ (epn >> epnshift);
 418     } else {
 419         /* 256M segment */
 420         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
 421         epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
 422         hash = vsid ^ (epn >> epnshift);
 423     }
 424     ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
 425
 426     /* Page address translation */
 427     qemu_log_mask(CPU_LOG_MMU,
 428             "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
 429             " hash " TARGET_FMT_plx "\n",
 430             env->htab_base, env->htab_mask, hash);
 431
 432     /* Primary PTEG lookup */
 433     qemu_log_mask(CPU_LOG_MMU,
 434             "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 435             " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
 436             " hash=" TARGET_FMT_plx "\n",
 437             env->htab_base, env->htab_mask, vsid, ptem,  hash);
 438     pte_offset = ppc_hash64_pteg_search(env, hash, 0, ptem, pte);
 439
 440     if (pte_offset == -1) {
 441         /* Secondary PTEG lookup */
 442         qemu_log_mask(CPU_LOG_MMU,
 443                 "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 444                 " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
 445                 " hash=" TARGET_FMT_plx "\n", env->htab_base,
 446                 env->htab_mask, vsid, ptem, ~hash);
 447
 448         pte_offset = ppc_hash64_pteg_search(env, ~hash, 1, ptem, pte);
 449     }
 450
 451     return pte_offset;
 452 }
 453
 454 static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte,
 455                                    target_ulong eaddr)
 456 {
 457     hwaddr mask;
 458     int target_page_bits;
 459     hwaddr rpn = pte.pte1 & HPTE64_R_RPN;
 460     /*
 461      * We support 4K, 64K and 16M now
 462      */
 463     target_page_bits = ppc_hash64_page_shift(slb);
 464     mask = (1ULL << target_page_bits) - 1;
 465     return (rpn & ~mask) | (eaddr & mask);
 466 }
 467
 468 int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
 469                                 int rwx, int mmu_idx)
 470 {
 471     CPUState *cs = CPU(cpu);
 472     CPUPPCState *env = &cpu->env;
 473     ppc_slb_t *slb;
 474     hwaddr pte_offset;
 475     ppc_hash_pte64_t pte;
 476     int pp_prot, amr_prot, prot;
 477     uint64_t new_pte1;
 478     const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
 479     hwaddr raddr;
 480
 481     assert((rwx == 0) || (rwx == 1) || (rwx == 2));
 482
 483     /* 1. Handle real mode accesses */
 484     if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
 485         /* Translation is off */
 486         /* In real mode the top 4 effective address bits are ignored */
 487         raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
 488         tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
 489                      PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
 490                      TARGET_PAGE_SIZE);
 491         return 0;
 492     }
 493
 494     /* 2. Translation is on, so look up the SLB */
 495     slb = slb_lookup(env, eaddr);
 496
 497     if (!slb) {
 498         if (rwx == 2) {
 499             cs->exception_index = POWERPC_EXCP_ISEG;
 500             env->error_code = 0;
 501         } else {
 502             cs->exception_index = POWERPC_EXCP_DSEG;
 503             env->error_code = 0;
 504             env->spr[SPR_DAR] = eaddr;
 505         }
 506         return 1;
 507     }
 508
 509     /* 3. Check for segment level no-execute violation */
 510     if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
 511         cs->exception_index = POWERPC_EXCP_ISI;
 512         env->error_code = 0x10000000;
 513         return 1;
 514     }
 515
 516     /* 4. Locate the PTE in the hash table */
 517     pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte);
 518     if (pte_offset == -1) {
 519         if (rwx == 2) {
 520             cs->exception_index = POWERPC_EXCP_ISI;
 521             env->error_code = 0x40000000;
 522         } else {
 523             cs->exception_index = POWERPC_EXCP_DSI;
 524             env->error_code = 0;
 525             env->spr[SPR_DAR] = eaddr;
 526             if (rwx == 1) {
 527                 env->spr[SPR_DSISR] = 0x42000000;
 528             } else {
 529                 env->spr[SPR_DSISR] = 0x40000000;
 530             }
 531         }
 532         return 1;
 533     }
 534     qemu_log_mask(CPU_LOG_MMU,
 535                 "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
 536
 537     /* 5. Check access permissions */
 538
 539     pp_prot = ppc_hash64_pte_prot(env, slb, pte);
 540     amr_prot = ppc_hash64_amr_prot(env, pte);
 541     prot = pp_prot & amr_prot;
 542
 543     if ((need_prot[rwx] & ~prot) != 0) {
 544         /* Access right violation */
 545         qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
 546         if (rwx == 2) {
 547             cs->exception_index = POWERPC_EXCP_ISI;
 548             env->error_code = 0x08000000;
 549         } else {
 550             target_ulong dsisr = 0;
 551
 552             cs->exception_index = POWERPC_EXCP_DSI;
 553             env->error_code = 0;
 554             env->spr[SPR_DAR] = eaddr;
 555             if (need_prot[rwx] & ~pp_prot) {
 556                 dsisr |= 0x08000000;
 557             }
 558             if (rwx == 1) {
 559                 dsisr |= 0x02000000;
 560             }
 561             if (need_prot[rwx] & ~amr_prot) {
 562                 dsisr |= 0x00200000;
 563             }
 564             env->spr[SPR_DSISR] = dsisr;
 565         }
 566         return 1;
 567     }
 568
 569     qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
 570
 571     /* 6. Update PTE referenced and changed bits if necessary */
 572
 573     new_pte1 = pte.pte1 | HPTE64_R_R; /* set referenced bit */
 574     if (rwx == 1) {
 575         new_pte1 |= HPTE64_R_C; /* set changed (dirty) bit */
 576     } else {
 577         /* Treat the page as read-only for now, so that a later write
 578          * will pass through this function again to set the C bit */
 579         prot &= ~PAGE_WRITE;
 580     }
 581
 582     if (new_pte1 != pte.pte1) {
 583         ppc_hash64_store_hpte(env, pte_offset / HASH_PTE_SIZE_64,
 584                               pte.pte0, new_pte1);
 585     }
 586
 587     /* 7. Determine the real address from the PTE */
 588
 589     raddr = ppc_hash64_pte_raddr(slb, pte, eaddr);
 590
 591     tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
 592                  prot, mmu_idx, TARGET_PAGE_SIZE);
 593
 594     return 0;
 595 }
 596
 597 hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
 598 {
 599     ppc_slb_t *slb;
 600     hwaddr pte_offset;
 601     ppc_hash_pte64_t pte;
 602
 603     if (msr_dr == 0) {
 604         /* In real mode the top 4 effective address bits are ignored */
 605         return addr & 0x0FFFFFFFFFFFFFFFULL;
 606     }
 607
 608     slb = slb_lookup(env, addr);
 609     if (!slb) {
 610         return -1;
 611     }
 612
 613     pte_offset = ppc_hash64_htab_lookup(env, slb, addr, &pte);
 614     if (pte_offset == -1) {
 615         return -1;
 616     }
 617
 618     return ppc_hash64_pte_raddr(slb, pte, addr) & TARGET_PAGE_MASK;
 619 }
 620
 621 void ppc_hash64_store_hpte(CPUPPCState *env,
 622                            target_ulong pte_index,
 623                            target_ulong pte0, target_ulong pte1)
 624 {
 625     CPUState *cs = CPU(ppc_env_get_cpu(env));
 626
 627     if (kvmppc_kern_htab) {
 628         kvmppc_hash64_write_pte(env, pte_index, pte0, pte1);
 629         return;
 630     }
 631
 632     pte_index *= HASH_PTE_SIZE_64;
 633     if (env->external_htab) {
 634         stq_p(env->external_htab + pte_index, pte0);
 635         stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64/2, pte1);
 636     } else {
 637         stq_phys(cs->as, env->htab_base + pte_index, pte0);
 638         stq_phys(cs->as, env->htab_base + pte_index + HASH_PTE_SIZE_64/2, pte1);
 639     }
 640 }