hw/vmware_vga.c

   1 /*
   2  * QEMU VMware-SVGA "chipset".
   3  *
   4  * Copyright (c) 2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "loader.h"
  26 #include "console.h"
  27 #include "pci.h"
  28
  29 #undef VERBOSE
  30 #define HW_RECT_ACCEL
  31 #define HW_FILL_ACCEL
  32 #define HW_MOUSE_ACCEL
  33
  34 # include "vga_int.h"
  35
  36 struct vmsvga_state_s {
  37     VGACommonState vga;
  38
  39     int width;
  40     int height;
  41     int invalidated;
  42     int depth;
  43     int bypp;
  44     int enable;
  45     int config;
  46     struct {
  47         int id;
  48         int x;
  49         int y;
  50         int on;
  51     } cursor;
  52
  53     int index;
  54     int scratch_size;
  55     uint32_t *scratch;
  56     int new_width;
  57     int new_height;
  58     uint32_t guest;
  59     uint32_t svgaid;
  60     uint32_t wred;
  61     uint32_t wgreen;
  62     uint32_t wblue;
  63     int syncing;
  64     int fb_size;
  65
  66     MemoryRegion fifo_ram;
  67     uint8_t *fifo_ptr;
  68     unsigned int fifo_size;
  69
  70     union {
  71         uint32_t *fifo;
  72         struct QEMU_PACKED {
  73             uint32_t min;
  74             uint32_t max;
  75             uint32_t next_cmd;
  76             uint32_t stop;
  77             /* Add registers here when adding capabilities.  */
  78             uint32_t fifo[0];
  79         } *cmd;
  80     };
  81
  82 #define REDRAW_FIFO_LEN  512
  83     struct vmsvga_rect_s {
  84         int x, y, w, h;
  85     } redraw_fifo[REDRAW_FIFO_LEN];
  86     int redraw_fifo_first, redraw_fifo_last;
  87 };
  88
  89 struct pci_vmsvga_state_s {
  90     PCIDevice card;
  91     struct vmsvga_state_s chip;
  92     MemoryRegion io_bar;
  93 };
  94
  95 #define SVGA_MAGIC              0x900000UL
  96 #define SVGA_MAKE_ID(ver)       (SVGA_MAGIC << 8 | (ver))
  97 #define SVGA_ID_0               SVGA_MAKE_ID(0)
  98 #define SVGA_ID_1               SVGA_MAKE_ID(1)
  99 #define SVGA_ID_2               SVGA_MAKE_ID(2)
 100
 101 #define SVGA_LEGACY_BASE_PORT   0x4560
 102 #define SVGA_INDEX_PORT         0x0
 103 #define SVGA_VALUE_PORT         0x1
 104 #define SVGA_BIOS_PORT          0x2
 105
 106 #define SVGA_VERSION_2
 107
 108 #ifdef SVGA_VERSION_2
 109 # define SVGA_ID                SVGA_ID_2
 110 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 111 # define SVGA_IO_MUL            1
 112 # define SVGA_FIFO_SIZE         0x10000
 113 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA2
 114 #else
 115 # define SVGA_ID                SVGA_ID_1
 116 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 117 # define SVGA_IO_MUL            4
 118 # define SVGA_FIFO_SIZE         0x10000
 119 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA
 120 #endif
 121
 122 enum {
 123     /* ID 0, 1 and 2 registers */
 124     SVGA_REG_ID = 0,
 125     SVGA_REG_ENABLE = 1,
 126     SVGA_REG_WIDTH = 2,
 127     SVGA_REG_HEIGHT = 3,
 128     SVGA_REG_MAX_WIDTH = 4,
 129     SVGA_REG_MAX_HEIGHT = 5,
 130     SVGA_REG_DEPTH = 6,
 131     SVGA_REG_BITS_PER_PIXEL = 7,        /* Current bpp in the guest */
 132     SVGA_REG_PSEUDOCOLOR = 8,
 133     SVGA_REG_RED_MASK = 9,
 134     SVGA_REG_GREEN_MASK = 10,
 135     SVGA_REG_BLUE_MASK = 11,
 136     SVGA_REG_BYTES_PER_LINE = 12,
 137     SVGA_REG_FB_START = 13,
 138     SVGA_REG_FB_OFFSET = 14,
 139     SVGA_REG_VRAM_SIZE = 15,
 140     SVGA_REG_FB_SIZE = 16,
 141
 142     /* ID 1 and 2 registers */
 143     SVGA_REG_CAPABILITIES = 17,
 144     SVGA_REG_MEM_START = 18,            /* Memory for command FIFO */
 145     SVGA_REG_MEM_SIZE = 19,
 146     SVGA_REG_CONFIG_DONE = 20,          /* Set when memory area configured */
 147     SVGA_REG_SYNC = 21,                 /* Write to force synchronization */
 148     SVGA_REG_BUSY = 22,                 /* Read to check if sync is done */
 149     SVGA_REG_GUEST_ID = 23,             /* Set guest OS identifier */
 150     SVGA_REG_CURSOR_ID = 24,            /* ID of cursor */
 151     SVGA_REG_CURSOR_X = 25,             /* Set cursor X position */
 152     SVGA_REG_CURSOR_Y = 26,             /* Set cursor Y position */
 153     SVGA_REG_CURSOR_ON = 27,            /* Turn cursor on/off */
 154     SVGA_REG_HOST_BITS_PER_PIXEL = 28,  /* Current bpp in the host */
 155     SVGA_REG_SCRATCH_SIZE = 29,         /* Number of scratch registers */
 156     SVGA_REG_MEM_REGS = 30,             /* Number of FIFO registers */
 157     SVGA_REG_NUM_DISPLAYS = 31,         /* Number of guest displays */
 158     SVGA_REG_PITCHLOCK = 32,            /* Fixed pitch for all modes */
 159
 160     SVGA_PALETTE_BASE = 1024,           /* Base of SVGA color map */
 161     SVGA_PALETTE_END  = SVGA_PALETTE_BASE + 767,
 162     SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
 163 };
 164
 165 #define SVGA_CAP_NONE                   0
 166 #define SVGA_CAP_RECT_FILL              (1 << 0)
 167 #define SVGA_CAP_RECT_COPY              (1 << 1)
 168 #define SVGA_CAP_RECT_PAT_FILL          (1 << 2)
 169 #define SVGA_CAP_LEGACY_OFFSCREEN       (1 << 3)
 170 #define SVGA_CAP_RASTER_OP              (1 << 4)
 171 #define SVGA_CAP_CURSOR                 (1 << 5)
 172 #define SVGA_CAP_CURSOR_BYPASS          (1 << 6)
 173 #define SVGA_CAP_CURSOR_BYPASS_2        (1 << 7)
 174 #define SVGA_CAP_8BIT_EMULATION         (1 << 8)
 175 #define SVGA_CAP_ALPHA_CURSOR           (1 << 9)
 176 #define SVGA_CAP_GLYPH                  (1 << 10)
 177 #define SVGA_CAP_GLYPH_CLIPPING         (1 << 11)
 178 #define SVGA_CAP_OFFSCREEN_1            (1 << 12)
 179 #define SVGA_CAP_ALPHA_BLEND            (1 << 13)
 180 #define SVGA_CAP_3D                     (1 << 14)
 181 #define SVGA_CAP_EXTENDED_FIFO          (1 << 15)
 182 #define SVGA_CAP_MULTIMON               (1 << 16)
 183 #define SVGA_CAP_PITCHLOCK              (1 << 17)
 184
 185 /*
 186  * FIFO offsets (seen as an array of 32-bit words)
 187  */
 188 enum {
 189     /*
 190      * The original defined FIFO offsets
 191      */
 192     SVGA_FIFO_MIN = 0,
 193     SVGA_FIFO_MAX,      /* The distance from MIN to MAX must be at least 10K */
 194     SVGA_FIFO_NEXT_CMD,
 195     SVGA_FIFO_STOP,
 196
 197     /*
 198      * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
 199      */
 200     SVGA_FIFO_CAPABILITIES = 4,
 201     SVGA_FIFO_FLAGS,
 202     SVGA_FIFO_FENCE,
 203     SVGA_FIFO_3D_HWVERSION,
 204     SVGA_FIFO_PITCHLOCK,
 205 };
 206
 207 #define SVGA_FIFO_CAP_NONE              0
 208 #define SVGA_FIFO_CAP_FENCE             (1 << 0)
 209 #define SVGA_FIFO_CAP_ACCELFRONT        (1 << 1)
 210 #define SVGA_FIFO_CAP_PITCHLOCK         (1 << 2)
 211
 212 #define SVGA_FIFO_FLAG_NONE             0
 213 #define SVGA_FIFO_FLAG_ACCELFRONT       (1 << 0)
 214
 215 /* These values can probably be changed arbitrarily.  */
 216 #define SVGA_SCRATCH_SIZE               0x8000
 217 #define SVGA_MAX_WIDTH                  2360
 218 #define SVGA_MAX_HEIGHT                 1770
 219
 220 #ifdef VERBOSE
 221 # define GUEST_OS_BASE          0x5001
 222 static const char *vmsvga_guest_id[] = {
 223     [0x00] = "Dos",
 224     [0x01] = "Windows 3.1",
 225     [0x02] = "Windows 95",
 226     [0x03] = "Windows 98",
 227     [0x04] = "Windows ME",
 228     [0x05] = "Windows NT",
 229     [0x06] = "Windows 2000",
 230     [0x07] = "Linux",
 231     [0x08] = "OS/2",
 232     [0x09] = "an unknown OS",
 233     [0x0a] = "BSD",
 234     [0x0b] = "Whistler",
 235     [0x0c] = "an unknown OS",
 236     [0x0d] = "an unknown OS",
 237     [0x0e] = "an unknown OS",
 238     [0x0f] = "an unknown OS",
 239     [0x10] = "an unknown OS",
 240     [0x11] = "an unknown OS",
 241     [0x12] = "an unknown OS",
 242     [0x13] = "an unknown OS",
 243     [0x14] = "an unknown OS",
 244     [0x15] = "Windows 2003",
 245 };
 246 #endif
 247
 248 enum {
 249     SVGA_CMD_INVALID_CMD = 0,
 250     SVGA_CMD_UPDATE = 1,
 251     SVGA_CMD_RECT_FILL = 2,
 252     SVGA_CMD_RECT_COPY = 3,
 253     SVGA_CMD_DEFINE_BITMAP = 4,
 254     SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
 255     SVGA_CMD_DEFINE_PIXMAP = 6,
 256     SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
 257     SVGA_CMD_RECT_BITMAP_FILL = 8,
 258     SVGA_CMD_RECT_PIXMAP_FILL = 9,
 259     SVGA_CMD_RECT_BITMAP_COPY = 10,
 260     SVGA_CMD_RECT_PIXMAP_COPY = 11,
 261     SVGA_CMD_FREE_OBJECT = 12,
 262     SVGA_CMD_RECT_ROP_FILL = 13,
 263     SVGA_CMD_RECT_ROP_COPY = 14,
 264     SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
 265     SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
 266     SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
 267     SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
 268     SVGA_CMD_DEFINE_CURSOR = 19,
 269     SVGA_CMD_DISPLAY_CURSOR = 20,
 270     SVGA_CMD_MOVE_CURSOR = 21,
 271     SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
 272     SVGA_CMD_DRAW_GLYPH = 23,
 273     SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
 274     SVGA_CMD_UPDATE_VERBOSE = 25,
 275     SVGA_CMD_SURFACE_FILL = 26,
 276     SVGA_CMD_SURFACE_COPY = 27,
 277     SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
 278     SVGA_CMD_FRONT_ROP_FILL = 29,
 279     SVGA_CMD_FENCE = 30,
 280 };
 281
 282 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
 283 enum {
 284     SVGA_CURSOR_ON_HIDE = 0,
 285     SVGA_CURSOR_ON_SHOW = 1,
 286     SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
 287     SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
 288 };
 289
 290 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
 291                 int x, int y, int w, int h)
 292 {
 293     int line;
 294     int bypl;
 295     int width;
 296     int start;
 297     uint8_t *src;
 298     uint8_t *dst;
 299
 300     if (x + w > s->width) {
 301         fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
 302                 __func__, x, w);
 303         x = MIN(x, s->width);
 304         w = s->width - x;
 305     }
 306
 307     if (y + h > s->height) {
 308         fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
 309                 __func__, y, h);
 310         y = MIN(y, s->height);
 311         h = s->height - y;
 312     }
 313
 314     bypl = s->bypp * s->width;
 315     width = s->bypp * w;
 316     start = s->bypp * x + bypl * y;
 317     src = s->vga.vram_ptr + start;
 318     dst = ds_get_data(s->vga.ds) + start;
 319
 320     for (line = h; line > 0; line--, src += bypl, dst += bypl) {
 321         memcpy(dst, src, width);
 322     }
 323     dpy_gfx_update(s->vga.ds, x, y, w, h);
 324 }
 325
 326 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
 327 {
 328     memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr,
 329            s->bypp * s->width * s->height);
 330     dpy_gfx_update(s->vga.ds, 0, 0, s->width, s->height);
 331 }
 332
 333 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
 334                 int x, int y, int w, int h)
 335 {
 336     struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++];
 337
 338     s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
 339     rect->x = x;
 340     rect->y = y;
 341     rect->w = w;
 342     rect->h = h;
 343 }
 344
 345 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
 346 {
 347     struct vmsvga_rect_s *rect;
 348
 349     if (s->invalidated) {
 350         s->redraw_fifo_first = s->redraw_fifo_last;
 351         return;
 352     }
 353     /* Overlapping region updates can be optimised out here - if someone
 354      * knows a smart algorithm to do that, please share.  */
 355     while (s->redraw_fifo_first != s->redraw_fifo_last) {
 356         rect = &s->redraw_fifo[s->redraw_fifo_first++];
 357         s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
 358         vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
 359     }
 360 }
 361
 362 #ifdef HW_RECT_ACCEL
 363 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
 364                 int x0, int y0, int x1, int y1, int w, int h)
 365 {
 366     uint8_t *vram = s->vga.vram_ptr;
 367     int bypl = s->bypp * s->width;
 368     int width = s->bypp * w;
 369     int line = h;
 370     uint8_t *ptr[2];
 371
 372     if (y1 > y0) {
 373         ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
 374         ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
 375         for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) {
 376             memmove(ptr[1], ptr[0], width);
 377         }
 378     } else {
 379         ptr[0] = vram + s->bypp * x0 + bypl * y0;
 380         ptr[1] = vram + s->bypp * x1 + bypl * y1;
 381         for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) {
 382             memmove(ptr[1], ptr[0], width);
 383         }
 384     }
 385
 386     vmsvga_update_rect_delayed(s, x1, y1, w, h);
 387 }
 388 #endif
 389
 390 #ifdef HW_FILL_ACCEL
 391 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
 392                 uint32_t c, int x, int y, int w, int h)
 393 {
 394     uint8_t *vram = s->vga.vram_ptr;
 395     int bypp = s->bypp;
 396     int bypl = bypp * s->width;
 397     int width = bypp * w;
 398     int line = h;
 399     int column;
 400     uint8_t *fst = vram + bypp * x + bypl * y;
 401     uint8_t *dst;
 402     uint8_t *src;
 403     uint8_t col[4];
 404
 405     col[0] = c;
 406     col[1] = c >> 8;
 407     col[2] = c >> 16;
 408     col[3] = c >> 24;
 409
 410     if (line--) {
 411         dst = fst;
 412         src = col;
 413         for (column = width; column > 0; column--) {
 414             *(dst++) = *(src++);
 415             if (src - col == bypp) {
 416                 src = col;
 417             }
 418         }
 419         dst = fst;
 420         for (; line > 0; line--) {
 421             dst += bypl;
 422             memcpy(dst, fst, width);
 423         }
 424     }
 425
 426     vmsvga_update_rect_delayed(s, x, y, w, h);
 427 }
 428 #endif
 429
 430 struct vmsvga_cursor_definition_s {
 431     int width;
 432     int height;
 433     int id;
 434     int bpp;
 435     int hot_x;
 436     int hot_y;
 437     uint32_t mask[1024];
 438     uint32_t image[4096];
 439 };
 440
 441 #define SVGA_BITMAP_SIZE(w, h)          ((((w) + 31) >> 5) * (h))
 442 #define SVGA_PIXMAP_SIZE(w, h, bpp)     (((((w) * (bpp)) + 31) >> 5) * (h))
 443
 444 #ifdef HW_MOUSE_ACCEL
 445 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
 446                 struct vmsvga_cursor_definition_s *c)
 447 {
 448     QEMUCursor *qc;
 449     int i, pixels;
 450
 451     qc = cursor_alloc(c->width, c->height);
 452     qc->hot_x = c->hot_x;
 453     qc->hot_y = c->hot_y;
 454     switch (c->bpp) {
 455     case 1:
 456         cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image,
 457                         1, (void *)c->mask);
 458 #ifdef DEBUG
 459         cursor_print_ascii_art(qc, "vmware/mono");
 460 #endif
 461         break;
 462     case 32:
 463         /* fill alpha channel from mask, set color to zero */
 464         cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask,
 465                         1, (void *)c->mask);
 466         /* add in rgb values */
 467         pixels = c->width * c->height;
 468         for (i = 0; i < pixels; i++) {
 469             qc->data[i] |= c->image[i] & 0xffffff;
 470         }
 471 #ifdef DEBUG
 472         cursor_print_ascii_art(qc, "vmware/32bit");
 473 #endif
 474         break;
 475     default:
 476         fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
 477                 __func__, c->bpp);
 478         cursor_put(qc);
 479         qc = cursor_builtin_left_ptr();
 480     }
 481
 482     dpy_cursor_define(s->vga.ds, qc);
 483     cursor_put(qc);
 484 }
 485 #endif
 486
 487 #define CMD(f)  le32_to_cpu(s->cmd->f)
 488
 489 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
 490 {
 491     int num;
 492
 493     if (!s->config || !s->enable) {
 494         return 0;
 495     }
 496     num = CMD(next_cmd) - CMD(stop);
 497     if (num < 0) {
 498         num += CMD(max) - CMD(min);
 499     }
 500     return num >> 2;
 501 }
 502
 503 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
 504 {
 505     uint32_t cmd = s->fifo[CMD(stop) >> 2];
 506
 507     s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
 508     if (CMD(stop) >= CMD(max)) {
 509         s->cmd->stop = s->cmd->min;
 510     }
 511     return cmd;
 512 }
 513
 514 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
 515 {
 516     return le32_to_cpu(vmsvga_fifo_read_raw(s));
 517 }
 518
 519 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
 520 {
 521     uint32_t cmd, colour;
 522     int args, len;
 523     int x, y, dx, dy, width, height;
 524     struct vmsvga_cursor_definition_s cursor;
 525     uint32_t cmd_start;
 526
 527     len = vmsvga_fifo_length(s);
 528     while (len > 0) {
 529         /* May need to go back to the start of the command if incomplete */
 530         cmd_start = s->cmd->stop;
 531
 532         switch (cmd = vmsvga_fifo_read(s)) {
 533         case SVGA_CMD_UPDATE:
 534         case SVGA_CMD_UPDATE_VERBOSE:
 535             len -= 5;
 536             if (len < 0) {
 537                 goto rewind;
 538             }
 539
 540             x = vmsvga_fifo_read(s);
 541             y = vmsvga_fifo_read(s);
 542             width = vmsvga_fifo_read(s);
 543             height = vmsvga_fifo_read(s);
 544             vmsvga_update_rect_delayed(s, x, y, width, height);
 545             break;
 546
 547         case SVGA_CMD_RECT_FILL:
 548             len -= 6;
 549             if (len < 0) {
 550                 goto rewind;
 551             }
 552
 553             colour = vmsvga_fifo_read(s);
 554             x = vmsvga_fifo_read(s);
 555             y = vmsvga_fifo_read(s);
 556             width = vmsvga_fifo_read(s);
 557             height = vmsvga_fifo_read(s);
 558 #ifdef HW_FILL_ACCEL
 559             vmsvga_fill_rect(s, colour, x, y, width, height);
 560             break;
 561 #else
 562             args = 0;
 563             goto badcmd;
 564 #endif
 565
 566         case SVGA_CMD_RECT_COPY:
 567             len -= 7;
 568             if (len < 0) {
 569                 goto rewind;
 570             }
 571
 572             x = vmsvga_fifo_read(s);
 573             y = vmsvga_fifo_read(s);
 574             dx = vmsvga_fifo_read(s);
 575             dy = vmsvga_fifo_read(s);
 576             width = vmsvga_fifo_read(s);
 577             height = vmsvga_fifo_read(s);
 578 #ifdef HW_RECT_ACCEL
 579             vmsvga_copy_rect(s, x, y, dx, dy, width, height);
 580             break;
 581 #else
 582             args = 0;
 583             goto badcmd;
 584 #endif
 585
 586         case SVGA_CMD_DEFINE_CURSOR:
 587             len -= 8;
 588             if (len < 0) {
 589                 goto rewind;
 590             }
 591
 592             cursor.id = vmsvga_fifo_read(s);
 593             cursor.hot_x = vmsvga_fifo_read(s);
 594             cursor.hot_y = vmsvga_fifo_read(s);
 595             cursor.width = x = vmsvga_fifo_read(s);
 596             cursor.height = y = vmsvga_fifo_read(s);
 597             vmsvga_fifo_read(s);
 598             cursor.bpp = vmsvga_fifo_read(s);
 599
 600             args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
 601             if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask ||
 602                 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) {
 603                     goto badcmd;
 604             }
 605
 606             len -= args;
 607             if (len < 0) {
 608                 goto rewind;
 609             }
 610
 611             for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) {
 612                 cursor.mask[args] = vmsvga_fifo_read_raw(s);
 613             }
 614             for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) {
 615                 cursor.image[args] = vmsvga_fifo_read_raw(s);
 616             }
 617 #ifdef HW_MOUSE_ACCEL
 618             vmsvga_cursor_define(s, &cursor);
 619             break;
 620 #else
 621             args = 0;
 622             goto badcmd;
 623 #endif
 624
 625         /*
 626          * Other commands that we at least know the number of arguments
 627          * for so we can avoid FIFO desync if driver uses them illegally.
 628          */
 629         case SVGA_CMD_DEFINE_ALPHA_CURSOR:
 630             len -= 6;
 631             if (len < 0) {
 632                 goto rewind;
 633             }
 634             vmsvga_fifo_read(s);
 635             vmsvga_fifo_read(s);
 636             vmsvga_fifo_read(s);
 637             x = vmsvga_fifo_read(s);
 638             y = vmsvga_fifo_read(s);
 639             args = x * y;
 640             goto badcmd;
 641         case SVGA_CMD_RECT_ROP_FILL:
 642             args = 6;
 643             goto badcmd;
 644         case SVGA_CMD_RECT_ROP_COPY:
 645             args = 7;
 646             goto badcmd;
 647         case SVGA_CMD_DRAW_GLYPH_CLIPPED:
 648             len -= 4;
 649             if (len < 0) {
 650                 goto rewind;
 651             }
 652             vmsvga_fifo_read(s);
 653             vmsvga_fifo_read(s);
 654             args = 7 + (vmsvga_fifo_read(s) >> 2);
 655             goto badcmd;
 656         case SVGA_CMD_SURFACE_ALPHA_BLEND:
 657             args = 12;
 658             goto badcmd;
 659
 660         /*
 661          * Other commands that are not listed as depending on any
 662          * CAPABILITIES bits, but are not described in the README either.
 663          */
 664         case SVGA_CMD_SURFACE_FILL:
 665         case SVGA_CMD_SURFACE_COPY:
 666         case SVGA_CMD_FRONT_ROP_FILL:
 667         case SVGA_CMD_FENCE:
 668         case SVGA_CMD_INVALID_CMD:
 669             break; /* Nop */
 670
 671         default:
 672             args = 0;
 673         badcmd:
 674             len -= args;
 675             if (len < 0) {
 676                 goto rewind;
 677             }
 678             while (args--) {
 679                 vmsvga_fifo_read(s);
 680             }
 681             printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
 682                    __func__, cmd);
 683             break;
 684
 685         rewind:
 686             s->cmd->stop = cmd_start;
 687             break;
 688         }
 689     }
 690
 691     s->syncing = 0;
 692 }
 693
 694 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
 695 {
 696     struct vmsvga_state_s *s = opaque;
 697
 698     return s->index;
 699 }
 700
 701 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
 702 {
 703     struct vmsvga_state_s *s = opaque;
 704
 705     s->index = index;
 706 }
 707
 708 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
 709 {
 710     uint32_t caps;
 711     struct vmsvga_state_s *s = opaque;
 712
 713     switch (s->index) {
 714     case SVGA_REG_ID:
 715         return s->svgaid;
 716
 717     case SVGA_REG_ENABLE:
 718         return s->enable;
 719
 720     case SVGA_REG_WIDTH:
 721         return s->width;
 722
 723     case SVGA_REG_HEIGHT:
 724         return s->height;
 725
 726     case SVGA_REG_MAX_WIDTH:
 727         return SVGA_MAX_WIDTH;
 728
 729     case SVGA_REG_MAX_HEIGHT:
 730         return SVGA_MAX_HEIGHT;
 731
 732     case SVGA_REG_DEPTH:
 733         return s->depth;
 734
 735     case SVGA_REG_BITS_PER_PIXEL:
 736         return (s->depth + 7) & ~7;
 737
 738     case SVGA_REG_PSEUDOCOLOR:
 739         return 0x0;
 740
 741     case SVGA_REG_RED_MASK:
 742         return s->wred;
 743     case SVGA_REG_GREEN_MASK:
 744         return s->wgreen;
 745     case SVGA_REG_BLUE_MASK:
 746         return s->wblue;
 747
 748     case SVGA_REG_BYTES_PER_LINE:
 749         return ((s->depth + 7) >> 3) * s->new_width;
 750
 751     case SVGA_REG_FB_START: {
 752         struct pci_vmsvga_state_s *pci_vmsvga
 753             = container_of(s, struct pci_vmsvga_state_s, chip);
 754         return pci_get_bar_addr(&pci_vmsvga->card, 1);
 755     }
 756
 757     case SVGA_REG_FB_OFFSET:
 758         return 0x0;
 759
 760     case SVGA_REG_VRAM_SIZE:
 761         return s->vga.vram_size;
 762
 763     case SVGA_REG_FB_SIZE:
 764         return s->fb_size;
 765
 766     case SVGA_REG_CAPABILITIES:
 767         caps = SVGA_CAP_NONE;
 768 #ifdef HW_RECT_ACCEL
 769         caps |= SVGA_CAP_RECT_COPY;
 770 #endif
 771 #ifdef HW_FILL_ACCEL
 772         caps |= SVGA_CAP_RECT_FILL;
 773 #endif
 774 #ifdef HW_MOUSE_ACCEL
 775         if (dpy_cursor_define_supported(s->vga.ds)) {
 776             caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
 777                     SVGA_CAP_CURSOR_BYPASS;
 778         }
 779 #endif
 780         return caps;
 781
 782     case SVGA_REG_MEM_START: {
 783         struct pci_vmsvga_state_s *pci_vmsvga
 784             = container_of(s, struct pci_vmsvga_state_s, chip);
 785         return pci_get_bar_addr(&pci_vmsvga->card, 2);
 786     }
 787
 788     case SVGA_REG_MEM_SIZE:
 789         return s->fifo_size;
 790
 791     case SVGA_REG_CONFIG_DONE:
 792         return s->config;
 793
 794     case SVGA_REG_SYNC:
 795     case SVGA_REG_BUSY:
 796         return s->syncing;
 797
 798     case SVGA_REG_GUEST_ID:
 799         return s->guest;
 800
 801     case SVGA_REG_CURSOR_ID:
 802         return s->cursor.id;
 803
 804     case SVGA_REG_CURSOR_X:
 805         return s->cursor.x;
 806
 807     case SVGA_REG_CURSOR_Y:
 808         return s->cursor.x;
 809
 810     case SVGA_REG_CURSOR_ON:
 811         return s->cursor.on;
 812
 813     case SVGA_REG_HOST_BITS_PER_PIXEL:
 814         return (s->depth + 7) & ~7;
 815
 816     case SVGA_REG_SCRATCH_SIZE:
 817         return s->scratch_size;
 818
 819     case SVGA_REG_MEM_REGS:
 820     case SVGA_REG_NUM_DISPLAYS:
 821     case SVGA_REG_PITCHLOCK:
 822     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 823         return 0;
 824
 825     default:
 826         if (s->index >= SVGA_SCRATCH_BASE &&
 827             s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
 828             return s->scratch[s->index - SVGA_SCRATCH_BASE];
 829         }
 830         printf("%s: Bad register %02x\n", __func__, s->index);
 831     }
 832
 833     return 0;
 834 }
 835
 836 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
 837 {
 838     struct vmsvga_state_s *s = opaque;
 839
 840     switch (s->index) {
 841     case SVGA_REG_ID:
 842         if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) {
 843             s->svgaid = value;
 844         }
 845         break;
 846
 847     case SVGA_REG_ENABLE:
 848         s->enable = value;
 849         s->config &= !!value;
 850         s->width = -1;
 851         s->height = -1;
 852         s->invalidated = 1;
 853         s->vga.invalidate(&s->vga);
 854         if (s->enable) {
 855             s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
 856             vga_dirty_log_stop(&s->vga);
 857         } else {
 858             vga_dirty_log_start(&s->vga);
 859         }
 860         break;
 861
 862     case SVGA_REG_WIDTH:
 863         s->new_width = value;
 864         s->invalidated = 1;
 865         break;
 866
 867     case SVGA_REG_HEIGHT:
 868         s->new_height = value;
 869         s->invalidated = 1;
 870         break;
 871
 872     case SVGA_REG_DEPTH:
 873     case SVGA_REG_BITS_PER_PIXEL:
 874         if (value != s->depth) {
 875             printf("%s: Bad colour depth: %i bits\n", __func__, value);
 876             s->config = 0;
 877         }
 878         break;
 879
 880     case SVGA_REG_CONFIG_DONE:
 881         if (value) {
 882             s->fifo = (uint32_t *) s->fifo_ptr;
 883             /* Check range and alignment.  */
 884             if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) {
 885                 break;
 886             }
 887             if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) {
 888                 break;
 889             }
 890             if (CMD(max) > SVGA_FIFO_SIZE) {
 891                 break;
 892             }
 893             if (CMD(max) < CMD(min) + 10 * 1024) {
 894                 break;
 895             }
 896         }
 897         s->config = !!value;
 898         break;
 899
 900     case SVGA_REG_SYNC:
 901         s->syncing = 1;
 902         vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
 903         break;
 904
 905     case SVGA_REG_GUEST_ID:
 906         s->guest = value;
 907 #ifdef VERBOSE
 908         if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
 909             ARRAY_SIZE(vmsvga_guest_id)) {
 910             printf("%s: guest runs %s.\n", __func__,
 911                    vmsvga_guest_id[value - GUEST_OS_BASE]);
 912         }
 913 #endif
 914         break;
 915
 916     case SVGA_REG_CURSOR_ID:
 917         s->cursor.id = value;
 918         break;
 919
 920     case SVGA_REG_CURSOR_X:
 921         s->cursor.x = value;
 922         break;
 923
 924     case SVGA_REG_CURSOR_Y:
 925         s->cursor.y = value;
 926         break;
 927
 928     case SVGA_REG_CURSOR_ON:
 929         s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
 930         s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
 931 #ifdef HW_MOUSE_ACCEL
 932         if (value <= SVGA_CURSOR_ON_SHOW) {
 933             dpy_mouse_set(s->vga.ds, s->cursor.x, s->cursor.y, s->cursor.on);
 934         }
 935 #endif
 936         break;
 937
 938     case SVGA_REG_MEM_REGS:
 939     case SVGA_REG_NUM_DISPLAYS:
 940     case SVGA_REG_PITCHLOCK:
 941     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 942         break;
 943
 944     default:
 945         if (s->index >= SVGA_SCRATCH_BASE &&
 946                 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
 947             s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
 948             break;
 949         }
 950         printf("%s: Bad register %02x\n", __func__, s->index);
 951     }
 952 }
 953
 954 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
 955 {
 956     printf("%s: what are we supposed to return?\n", __func__);
 957     return 0xcafe;
 958 }
 959
 960 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
 961 {
 962     printf("%s: what are we supposed to do with (%08x)?\n", __func__, data);
 963 }
 964
 965 static inline void vmsvga_size(struct vmsvga_state_s *s)
 966 {
 967     if (s->new_width != s->width || s->new_height != s->height) {
 968         s->width = s->new_width;
 969         s->height = s->new_height;
 970         qemu_console_resize(s->vga.ds, s->width, s->height);
 971         s->invalidated = 1;
 972     }
 973 }
 974
 975 static void vmsvga_update_display(void *opaque)
 976 {
 977     struct vmsvga_state_s *s = opaque;
 978     if (!s->enable) {
 979         s->vga.update(&s->vga);
 980         return;
 981     }
 982
 983     vmsvga_size(s);
 984
 985     vmsvga_fifo_run(s);
 986     vmsvga_update_rect_flush(s);
 987
 988     /*
 989      * Is it more efficient to look at vram VGA-dirty bits or wait
 990      * for the driver to issue SVGA_CMD_UPDATE?
 991      */
 992     if (s->invalidated) {
 993         s->invalidated = 0;
 994         vmsvga_update_screen(s);
 995     }
 996 }
 997
 998 static void vmsvga_reset(DeviceState *dev)
 999 {
1000     struct pci_vmsvga_state_s *pci =
1001         DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev);
1002     struct vmsvga_state_s *s = &pci->chip;
1003
1004     s->index = 0;
1005     s->enable = 0;
1006     s->config = 0;
1007     s->width = -1;
1008     s->height = -1;
1009     s->svgaid = SVGA_ID;
1010     s->cursor.on = 0;
1011     s->redraw_fifo_first = 0;
1012     s->redraw_fifo_last = 0;
1013     s->syncing = 0;
1014
1015     vga_dirty_log_start(&s->vga);
1016 }
1017
1018 static void vmsvga_invalidate_display(void *opaque)
1019 {
1020     struct vmsvga_state_s *s = opaque;
1021     if (!s->enable) {
1022         s->vga.invalidate(&s->vga);
1023         return;
1024     }
1025
1026     s->invalidated = 1;
1027 }
1028
1029 /* save the vga display in a PPM image even if no display is
1030    available */
1031 static void vmsvga_screen_dump(void *opaque, const char *filename, bool cswitch,
1032                                Error **errp)
1033 {
1034     struct vmsvga_state_s *s = opaque;
1035     if (!s->enable) {
1036         s->vga.screen_dump(&s->vga, filename, cswitch, errp);
1037         return;
1038     }
1039
1040     if (s->depth == 32) {
1041         DisplaySurface *ds = qemu_create_displaysurface_from(s->width,
1042                 s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
1043         ppm_save(filename, ds, errp);
1044         g_free(ds);
1045     }
1046 }
1047
1048 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
1049 {
1050     struct vmsvga_state_s *s = opaque;
1051
1052     if (s->vga.text_update) {
1053         s->vga.text_update(&s->vga, chardata);
1054     }
1055 }
1056
1057 static int vmsvga_post_load(void *opaque, int version_id)
1058 {
1059     struct vmsvga_state_s *s = opaque;
1060
1061     s->invalidated = 1;
1062     if (s->config) {
1063         s->fifo = (uint32_t *) s->fifo_ptr;
1064     }
1065     return 0;
1066 }
1067
1068 static const VMStateDescription vmstate_vmware_vga_internal = {
1069     .name = "vmware_vga_internal",
1070     .version_id = 0,
1071     .minimum_version_id = 0,
1072     .minimum_version_id_old = 0,
1073     .post_load = vmsvga_post_load,
1074     .fields      = (VMStateField[]) {
1075         VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
1076         VMSTATE_INT32(enable, struct vmsvga_state_s),
1077         VMSTATE_INT32(config, struct vmsvga_state_s),
1078         VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1079         VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1080         VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1081         VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1082         VMSTATE_INT32(index, struct vmsvga_state_s),
1083         VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1084                              scratch_size, 0, vmstate_info_uint32, uint32_t),
1085         VMSTATE_INT32(new_width, struct vmsvga_state_s),
1086         VMSTATE_INT32(new_height, struct vmsvga_state_s),
1087         VMSTATE_UINT32(guest, struct vmsvga_state_s),
1088         VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1089         VMSTATE_INT32(syncing, struct vmsvga_state_s),
1090         VMSTATE_INT32(fb_size, struct vmsvga_state_s),
1091         VMSTATE_END_OF_LIST()
1092     }
1093 };
1094
1095 static const VMStateDescription vmstate_vmware_vga = {
1096     .name = "vmware_vga",
1097     .version_id = 0,
1098     .minimum_version_id = 0,
1099     .minimum_version_id_old = 0,
1100     .fields      = (VMStateField[]) {
1101         VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
1102         VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1103                        vmstate_vmware_vga_internal, struct vmsvga_state_s),
1104         VMSTATE_END_OF_LIST()
1105     }
1106 };
1107
1108 static void vmsvga_init(struct vmsvga_state_s *s,
1109                         MemoryRegion *address_space, MemoryRegion *io)
1110 {
1111     s->scratch_size = SVGA_SCRATCH_SIZE;
1112     s->scratch = g_malloc(s->scratch_size * 4);
1113
1114     s->vga.ds = graphic_console_init(vmsvga_update_display,
1115                                      vmsvga_invalidate_display,
1116                                      vmsvga_screen_dump,
1117                                      vmsvga_text_update, s);
1118
1119
1120     s->fifo_size = SVGA_FIFO_SIZE;
1121     memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size);
1122     vmstate_register_ram_global(&s->fifo_ram);
1123     s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
1124
1125     vga_common_init(&s->vga);
1126     vga_init(&s->vga, address_space, io, true);
1127     vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
1128
1129     s->depth = ds_get_bits_per_pixel(s->vga.ds);
1130     s->bypp = ds_get_bytes_per_pixel(s->vga.ds);
1131     switch (s->depth) {
1132     case 8:
1133         s->wred   = 0x00000007;
1134         s->wgreen = 0x00000038;
1135         s->wblue  = 0x000000c0;
1136         break;
1137     case 15:
1138         s->wred   = 0x0000001f;
1139         s->wgreen = 0x000003e0;
1140         s->wblue  = 0x00007c00;
1141         break;
1142     case 16:
1143         s->wred   = 0x0000001f;
1144         s->wgreen = 0x000007e0;
1145         s->wblue  = 0x0000f800;
1146         break;
1147     case 24:
1148         s->wred   = 0x00ff0000;
1149         s->wgreen = 0x0000ff00;
1150         s->wblue  = 0x000000ff;
1151         break;
1152     case 32:
1153         s->wred   = 0x00ff0000;
1154         s->wgreen = 0x0000ff00;
1155         s->wblue  = 0x000000ff;
1156         break;
1157     }
1158 }
1159
1160 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr,
1161                                unsigned size)
1162 {
1163     struct vmsvga_state_s *s = opaque;
1164
1165     switch (addr) {
1166     case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr);
1167     case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr);
1168     case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr);
1169     default: return -1u;
1170     }
1171 }
1172
1173 static void vmsvga_io_write(void *opaque, hwaddr addr,
1174                             uint64_t data, unsigned size)
1175 {
1176     struct vmsvga_state_s *s = opaque;
1177
1178     switch (addr) {
1179     case SVGA_IO_MUL * SVGA_INDEX_PORT:
1180         vmsvga_index_write(s, addr, data);
1181         break;
1182     case SVGA_IO_MUL * SVGA_VALUE_PORT:
1183         vmsvga_value_write(s, addr, data);
1184         break;
1185     case SVGA_IO_MUL * SVGA_BIOS_PORT:
1186         vmsvga_bios_write(s, addr, data);
1187         break;
1188     }
1189 }
1190
1191 static const MemoryRegionOps vmsvga_io_ops = {
1192     .read = vmsvga_io_read,
1193     .write = vmsvga_io_write,
1194     .endianness = DEVICE_LITTLE_ENDIAN,
1195     .valid = {
1196         .min_access_size = 4,
1197         .max_access_size = 4,
1198     },
1199 };
1200
1201 static int pci_vmsvga_initfn(PCIDevice *dev)
1202 {
1203     struct pci_vmsvga_state_s *s =
1204         DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
1205     MemoryRegion *iomem;
1206
1207     iomem = &s->chip.vga.vram;
1208
1209     s->card.config[PCI_CACHE_LINE_SIZE] = 0x08;         /* Cache line size */
1210     s->card.config[PCI_LATENCY_TIMER] = 0x40;           /* Latency timer */
1211     s->card.config[PCI_INTERRUPT_LINE] = 0xff;          /* End */
1212
1213     memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip,
1214                           "vmsvga-io", 0x10);
1215     memory_region_set_flush_coalesced(&s->io_bar);
1216     pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1217
1218     vmsvga_init(&s->chip, pci_address_space(dev),
1219                 pci_address_space_io(dev));
1220
1221     pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem);
1222     pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
1223                      &s->chip.fifo_ram);
1224
1225     if (!dev->rom_bar) {
1226         /* compatibility with pc-0.13 and older */
1227         vga_init_vbe(&s->chip.vga, pci_address_space(dev));
1228     }
1229
1230     return 0;
1231 }
1232
1233 static Property vga_vmware_properties[] = {
1234     DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s,
1235                        chip.vga.vram_size_mb, 16),
1236     DEFINE_PROP_END_OF_LIST(),
1237 };
1238
1239 static void vmsvga_class_init(ObjectClass *klass, void *data)
1240 {
1241     DeviceClass *dc = DEVICE_CLASS(klass);
1242     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1243
1244     k->no_hotplug = 1;
1245     k->init = pci_vmsvga_initfn;
1246     k->romfile = "vgabios-vmware.bin";
1247     k->vendor_id = PCI_VENDOR_ID_VMWARE;
1248     k->device_id = SVGA_PCI_DEVICE_ID;
1249     k->class_id = PCI_CLASS_DISPLAY_VGA;
1250     k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
1251     k->subsystem_id = SVGA_PCI_DEVICE_ID;
1252     dc->reset = vmsvga_reset;
1253     dc->vmsd = &vmstate_vmware_vga;
1254     dc->props = vga_vmware_properties;
1255 }
1256
1257 static TypeInfo vmsvga_info = {
1258     .name          = "vmware-svga",
1259     .parent        = TYPE_PCI_DEVICE,
1260     .instance_size = sizeof(struct pci_vmsvga_state_s),
1261     .class_init    = vmsvga_class_init,
1262 };
1263
1264 static void vmsvga_register_types(void)
1265 {
1266     type_register_static(&vmsvga_info);
1267 }
1268
1269 type_init(vmsvga_register_types)