include/exec/cpu-defs.h

   1 /*
   2  * common defines for all CPUs
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_DEFS_H
  20 #define CPU_DEFS_H
  21
  22 #ifndef NEED_CPU_H
  23 #error cpu.h included from common code
  24 #endif
  25
  26 #include "qemu/host-utils.h"
  27 #include "qemu/thread.h"
  28 #include "qemu/queue.h"
  29 #ifdef CONFIG_TCG
  30 #include "tcg-target.h"
  31 #endif
  32 #ifndef CONFIG_USER_ONLY
  33 #include "exec/hwaddr.h"
  34 #endif
  35 #include "exec/memattrs.h"
  36
  37 #ifndef TARGET_LONG_BITS
  38 #error TARGET_LONG_BITS must be defined before including this header
  39 #endif
  40
  41 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
  42
  43 /* target_ulong is the type of a virtual address */
  44 #if TARGET_LONG_SIZE == 4
  45 typedef int32_t target_long;
  46 typedef uint32_t target_ulong;
  47 #define TARGET_FMT_lx "%08x"
  48 #define TARGET_FMT_ld "%d"
  49 #define TARGET_FMT_lu "%u"
  50 #elif TARGET_LONG_SIZE == 8
  51 typedef int64_t target_long;
  52 typedef uint64_t target_ulong;
  53 #define TARGET_FMT_lx "%016" PRIx64
  54 #define TARGET_FMT_ld "%" PRId64
  55 #define TARGET_FMT_lu "%" PRIu64
  56 #else
  57 #error TARGET_LONG_SIZE undefined
  58 #endif
  59
  60 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
  61 /* use a fully associative victim tlb of 8 entries */
  62 #define CPU_VTLB_SIZE 8
  63
  64 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
  65 #define CPU_TLB_ENTRY_BITS 4
  66 #else
  67 #define CPU_TLB_ENTRY_BITS 5
  68 #endif
  69
  70 #define CPU_TLB_DYN_MIN_BITS 6
  71 #define CPU_TLB_DYN_DEFAULT_BITS 8
  72
  73 # if HOST_LONG_BITS == 32
  74 /* Make sure we do not require a double-word shift for the TLB load */
  75 #  define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
  76 # else /* HOST_LONG_BITS == 64 */
  77 /*
  78  * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) ==
  79  * 2**34 == 16G of address space. This is roughly what one would expect a
  80  * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel
  81  * Skylake's Level-2 STLB has 16 1G entries.
  82  * Also, make sure we do not size the TLB past the guest's address space.
  83  */
  84 #  define CPU_TLB_DYN_MAX_BITS                                  \
  85     MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
  86 # endif
  87
  88 typedef struct CPUTLBEntry {
  89     /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
  90        bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not
  91                                     go directly to ram.
  92        bit 3                      : indicates that the entry is invalid
  93        bit 2..0                   : zero
  94     */
  95     union {
  96         struct {
  97             target_ulong addr_read;
  98             target_ulong addr_write;
  99             target_ulong addr_code;
 100             /* Addend to virtual address to get host address.  IO accesses
 101                use the corresponding iotlb value.  */
 102             uintptr_t addend;
 103         };
 104         /* padding to get a power of two size */
 105         uint8_t dummy[1 << CPU_TLB_ENTRY_BITS];
 106     };
 107 } CPUTLBEntry;
 108
 109 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
 110
 111 /* The IOTLB is not accessed directly inline by generated TCG code,
 112  * so the CPUIOTLBEntry layout is not as critical as that of the
 113  * CPUTLBEntry. (This is also why we don't want to combine the two
 114  * structs into one.)
 115  */
 116 typedef struct CPUIOTLBEntry {
 117     /*
 118      * @addr contains:
 119      *  - in the lower TARGET_PAGE_BITS, a physical section number
 120      *  - with the lower TARGET_PAGE_BITS masked off, an offset which
 121      *    must be added to the virtual address to obtain:
 122      *     + the ram_addr_t of the target RAM (if the physical section
 123      *       number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
 124      *     + the offset within the target MemoryRegion (otherwise)
 125      */
 126     hwaddr addr;
 127     MemTxAttrs attrs;
 128 } CPUIOTLBEntry;
 129
 130 /**
 131  * struct CPUTLBWindow
 132  * @begin_ns: host time (in ns) at the beginning of the time window
 133  * @max_entries: maximum number of entries observed in the window
 134  *
 135  * See also: tlb_mmu_resize_locked()
 136  */
 137 typedef struct CPUTLBWindow {
 138     int64_t begin_ns;
 139     size_t max_entries;
 140 } CPUTLBWindow;
 141
 142 typedef struct CPUTLBDesc {
 143     /*
 144      * Describe a region covering all of the large pages allocated
 145      * into the tlb.  When any page within this region is flushed,
 146      * we must flush the entire tlb.  The region is matched if
 147      * (addr & large_page_mask) == large_page_addr.
 148      */
 149     target_ulong large_page_addr;
 150     target_ulong large_page_mask;
 151     /* The next index to use in the tlb victim table.  */
 152     size_t vindex;
 153     CPUTLBWindow window;
 154     size_t n_used_entries;
 155 } CPUTLBDesc;
 156
 157 /*
 158  * Data elements that are shared between all MMU modes.
 159  */
 160 typedef struct CPUTLBCommon {
 161     /* Serialize updates to tlb_table and tlb_v_table, and others as noted. */
 162     QemuSpin lock;
 163     /*
 164      * Within dirty, for each bit N, modifications have been made to
 165      * mmu_idx N since the last time that mmu_idx was flushed.
 166      * Protected by tlb_c.lock.
 167      */
 168     uint16_t dirty;
 169     /*
 170      * Statistics.  These are not lock protected, but are read and
 171      * written atomically.  This allows the monitor to print a snapshot
 172      * of the stats without interfering with the cpu.
 173      */
 174     size_t full_flush_count;
 175     size_t part_flush_count;
 176     size_t elide_flush_count;
 177 } CPUTLBCommon;
 178
 179 # define CPU_TLB                                                        \
 180     /* tlb_mask[i] contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */    \
 181     uintptr_t tlb_mask[NB_MMU_MODES];                                   \
 182     CPUTLBEntry *tlb_table[NB_MMU_MODES];
 183 # define CPU_IOTLB                              \
 184     CPUIOTLBEntry *iotlb[NB_MMU_MODES];
 185
 186 /*
 187  * The meaning of each of the MMU modes is defined in the target code.
 188  * Note that NB_MMU_MODES is not yet defined; we can only reference it
 189  * within preprocessor defines that will be expanded later.
 190  */
 191 #define CPU_COMMON_TLB \
 192     CPUTLBCommon tlb_c;                                                 \
 193     CPUTLBDesc tlb_d[NB_MMU_MODES];                                     \
 194     CPU_TLB                                                             \
 195     CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE];               \
 196     CPU_IOTLB                                                           \
 197     CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE];
 198
 199 #else
 200
 201 #define CPU_COMMON_TLB
 202
 203 #endif
 204
 205
 206 #define CPU_COMMON                                                      \
 207     /* soft mmu support */                                              \
 208     CPU_COMMON_TLB                                                      \
 209
 210 #endif