4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "hw/core/cpu.h"
24 #include "hw/registerfields.h"
25 #include "exec/cpu-defs.h"
26 #include "fpu/softfloat-types.h"
27 #include "qom/object.h"
29 #define TCG_GUEST_DEFAULT_MO 0
31 #define TYPE_RISCV_CPU "riscv-cpu"
33 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
34 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
35 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
37 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
38 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
39 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
40 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
41 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
42 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
43 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
44 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
45 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
46 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
48 #if defined(TARGET_RISCV32)
49 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
50 #elif defined(TARGET_RISCV64)
51 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
54 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
55 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
57 #define RV(x) ((target_ulong)1 << (x - 'A'))
60 #define RVE RV('E') /* E and I are mutually exclusive */
71 /* S extension denotes that Supervisor mode exists, however it is possible
72 to have a core that support S mode but does not have an MMU and there
73 is currently no bit in misa to indicate whether an MMU exists or not
74 so a cpu features bitfield is required, likewise for optional PMP support */
82 #define PRIV_VERSION_1_10_0 0x00011000
83 #define PRIV_VERSION_1_11_0 0x00011100
85 #define VEXT_VERSION_0_07_1 0x00000701
91 TRANSLATE_G_STAGE_FAIL
94 #define MMU_USER_IDX 3
96 #define MAX_RISCV_PMPS (16)
98 typedef struct CPURISCVState CPURISCVState
;
100 #if !defined(CONFIG_USER_ONLY)
104 #define RV_VLEN_MAX 256
106 FIELD(VTYPE
, VLMUL
, 0, 2)
107 FIELD(VTYPE
, VSEW
, 2, 3)
108 FIELD(VTYPE
, VEDIV
, 5, 2)
109 FIELD(VTYPE
, RESERVED
, 7, sizeof(target_ulong
) * 8 - 9)
110 FIELD(VTYPE
, VILL
, sizeof(target_ulong
) * 8 - 1, 1)
112 struct CPURISCVState
{
113 target_ulong gpr
[32];
114 uint64_t fpr
[32]; /* assume both F and D extensions */
116 /* vector coprocessor state. */
117 uint64_t vreg
[32 * RV_VLEN_MAX
/ 64] QEMU_ALIGNED(16);
125 target_ulong load_res
;
126 target_ulong load_val
;
130 target_ulong badaddr
;
131 target_ulong guest_phys_fault_addr
;
133 target_ulong priv_ver
;
134 target_ulong vext_ver
;
136 target_ulong misa_mask
;
140 #ifdef CONFIG_USER_ONLY
144 #ifndef CONFIG_USER_ONLY
146 /* This contains QEMU specific information about the virt state. */
148 target_ulong resetvec
;
150 target_ulong mhartid
;
152 * For RV32 this is 32-bit mstatus and 32-bit mstatush.
153 * For RV64 this is a 64-bit mstatus.
162 target_ulong mideleg
;
164 target_ulong satp
; /* since: priv-1.10.0 */
166 target_ulong medeleg
;
175 target_ulong mtval
; /* since: priv-1.10.0 */
177 /* Hypervisor CSRs */
178 target_ulong hstatus
;
179 target_ulong hedeleg
;
180 target_ulong hideleg
;
181 target_ulong hcounteren
;
189 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
190 * For RV64 this is a 64-bit vsstatus.
194 target_ulong vsscratch
;
196 target_ulong vscause
;
204 target_ulong stvec_hs
;
205 target_ulong sscratch_hs
;
206 target_ulong sepc_hs
;
207 target_ulong scause_hs
;
208 target_ulong stval_hs
;
209 target_ulong satp_hs
;
212 /* Signals whether the current exception occurred with two-stage address
213 translation active. */
214 bool two_stage_lookup
;
216 target_ulong scounteren
;
217 target_ulong mcounteren
;
219 target_ulong sscratch
;
220 target_ulong mscratch
;
222 /* temporary htif regs */
227 /* physical memory protection */
228 pmp_table_t pmp_state
;
229 target_ulong mseccfg
;
231 /* machine specific rdtime callback */
232 uint64_t (*rdtime_fn
)(uint32_t);
233 uint32_t rdtime_fn_arg
;
235 /* True if in debugger mode. */
239 float_status fp_status
;
241 /* Fields from here on are preserved across CPU reset. */
242 QEMUTimer
*timer
; /* Internal timer */
245 OBJECT_DECLARE_TYPE(RISCVCPU
, RISCVCPUClass
,
250 * @parent_realize: The parent class' realize handler.
251 * @parent_reset: The parent class' reset handler.
255 struct RISCVCPUClass
{
257 CPUClass parent_class
;
259 DeviceRealize parent_realize
;
260 DeviceReset parent_reset
;
265 * @env: #CPURISCVState
273 CPUNegativeOffsetState neg
;
278 /* Configuration Settings */
308 static inline int riscv_has_ext(CPURISCVState
*env
, target_ulong ext
)
310 return (env
->misa
& ext
) != 0;
313 static inline bool riscv_feature(CPURISCVState
*env
, int feature
)
315 return env
->features
& (1ULL << feature
);
318 #include "cpu_user.h"
319 #include "cpu_bits.h"
321 extern const char * const riscv_int_regnames
[];
322 extern const char * const riscv_fpr_regnames
[];
323 extern const char * const riscv_excp_names
[];
324 extern const char * const riscv_intr_names
[];
326 const char *riscv_cpu_get_trap_name(target_ulong cause
, bool async
);
327 void riscv_cpu_do_interrupt(CPUState
*cpu
);
328 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f
, CPUState
*cs
,
329 int cpuid
, void *opaque
);
330 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f
, CPUState
*cs
,
331 int cpuid
, void *opaque
);
332 int riscv_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
333 int riscv_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
334 bool riscv_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
);
335 bool riscv_cpu_fp_enabled(CPURISCVState
*env
);
336 bool riscv_cpu_virt_enabled(CPURISCVState
*env
);
337 void riscv_cpu_set_virt_enabled(CPURISCVState
*env
, bool enable
);
338 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState
*env
);
339 void riscv_cpu_set_force_hs_excep(CPURISCVState
*env
, bool enable
);
340 bool riscv_cpu_two_stage_lookup(int mmu_idx
);
341 int riscv_cpu_mmu_index(CPURISCVState
*env
, bool ifetch
);
342 hwaddr
riscv_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
343 void riscv_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
344 MMUAccessType access_type
, int mmu_idx
,
346 bool riscv_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
347 MMUAccessType access_type
, int mmu_idx
,
348 bool probe
, uintptr_t retaddr
);
349 void riscv_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
350 vaddr addr
, unsigned size
,
351 MMUAccessType access_type
,
352 int mmu_idx
, MemTxAttrs attrs
,
353 MemTxResult response
, uintptr_t retaddr
);
354 char *riscv_isa_string(RISCVCPU
*cpu
);
355 void riscv_cpu_list(void);
357 #define cpu_signal_handler riscv_cpu_signal_handler
358 #define cpu_list riscv_cpu_list
359 #define cpu_mmu_index riscv_cpu_mmu_index
361 #ifndef CONFIG_USER_ONLY
362 void riscv_cpu_swap_hypervisor_regs(CPURISCVState
*env
);
363 int riscv_cpu_claim_interrupts(RISCVCPU
*cpu
, uint32_t interrupts
);
364 uint32_t riscv_cpu_update_mip(RISCVCPU
*cpu
, uint32_t mask
, uint32_t value
);
365 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
366 void riscv_cpu_set_rdtime_fn(CPURISCVState
*env
, uint64_t (*fn
)(uint32_t),
369 void riscv_cpu_set_mode(CPURISCVState
*env
, target_ulong newpriv
);
371 void riscv_translate_init(void);
372 int riscv_cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
);
373 void QEMU_NORETURN
riscv_raise_exception(CPURISCVState
*env
,
374 uint32_t exception
, uintptr_t pc
);
376 target_ulong
riscv_cpu_get_fflags(CPURISCVState
*env
);
377 void riscv_cpu_set_fflags(CPURISCVState
*env
, target_ulong
);
379 #define TB_FLAGS_MMU_MASK 7
380 #define TB_FLAGS_PRIV_MMU_MASK 3
381 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
382 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
384 typedef CPURISCVState CPUArchState
;
385 typedef RISCVCPU ArchCPU
;
386 #include "exec/cpu-all.h"
388 FIELD(TB_FLAGS
, VL_EQ_VLMAX
, 2, 1)
389 FIELD(TB_FLAGS
, LMUL
, 3, 2)
390 FIELD(TB_FLAGS
, SEW
, 5, 3)
391 FIELD(TB_FLAGS
, VILL
, 8, 1)
392 /* Is a Hypervisor instruction load/store allowed? */
393 FIELD(TB_FLAGS
, HLSX
, 9, 1)
395 bool riscv_cpu_is_32bit(CPURISCVState
*env
);
398 * A simplification for VLMAX
399 * = (1 << LMUL) * VLEN / (8 * (1 << SEW))
400 * = (VLEN << LMUL) / (8 << SEW)
401 * = (VLEN << LMUL) >> (SEW + 3)
402 * = VLEN >> (SEW + 3 - LMUL)
404 static inline uint32_t vext_get_vlmax(RISCVCPU
*cpu
, target_ulong vtype
)
408 sew
= FIELD_EX64(vtype
, VTYPE
, VSEW
);
409 lmul
= FIELD_EX64(vtype
, VTYPE
, VLMUL
);
410 return cpu
->cfg
.vlen
>> (sew
+ 3 - lmul
);
413 static inline void cpu_get_tb_cpu_state(CPURISCVState
*env
, target_ulong
*pc
,
414 target_ulong
*cs_base
, uint32_t *pflags
)
421 if (riscv_has_ext(env
, RVV
)) {
422 uint32_t vlmax
= vext_get_vlmax(env_archcpu(env
), env
->vtype
);
423 bool vl_eq_vlmax
= (env
->vstart
== 0) && (vlmax
== env
->vl
);
424 flags
= FIELD_DP32(flags
, TB_FLAGS
, VILL
,
425 FIELD_EX64(env
->vtype
, VTYPE
, VILL
));
426 flags
= FIELD_DP32(flags
, TB_FLAGS
, SEW
,
427 FIELD_EX64(env
->vtype
, VTYPE
, VSEW
));
428 flags
= FIELD_DP32(flags
, TB_FLAGS
, LMUL
,
429 FIELD_EX64(env
->vtype
, VTYPE
, VLMUL
));
430 flags
= FIELD_DP32(flags
, TB_FLAGS
, VL_EQ_VLMAX
, vl_eq_vlmax
);
432 flags
= FIELD_DP32(flags
, TB_FLAGS
, VILL
, 1);
435 #ifdef CONFIG_USER_ONLY
436 flags
|= TB_FLAGS_MSTATUS_FS
;
438 flags
|= cpu_mmu_index(env
, 0);
439 if (riscv_cpu_fp_enabled(env
)) {
440 flags
|= env
->mstatus
& MSTATUS_FS
;
443 if (riscv_has_ext(env
, RVH
)) {
444 if (env
->priv
== PRV_M
||
445 (env
->priv
== PRV_S
&& !riscv_cpu_virt_enabled(env
)) ||
446 (env
->priv
== PRV_U
&& !riscv_cpu_virt_enabled(env
) &&
447 get_field(env
->hstatus
, HSTATUS_HU
))) {
448 flags
= FIELD_DP32(flags
, TB_FLAGS
, HLSX
, 1);
456 RISCVException
riscv_csrrw(CPURISCVState
*env
, int csrno
,
457 target_ulong
*ret_value
,
458 target_ulong new_value
, target_ulong write_mask
);
459 RISCVException
riscv_csrrw_debug(CPURISCVState
*env
, int csrno
,
460 target_ulong
*ret_value
,
461 target_ulong new_value
,
462 target_ulong write_mask
);
464 static inline void riscv_csr_write(CPURISCVState
*env
, int csrno
,
467 riscv_csrrw(env
, csrno
, NULL
, val
, MAKE_64BIT_MASK(0, TARGET_LONG_BITS
));
470 static inline target_ulong
riscv_csr_read(CPURISCVState
*env
, int csrno
)
472 target_ulong val
= 0;
473 riscv_csrrw(env
, csrno
, &val
, 0, 0);
477 typedef RISCVException (*riscv_csr_predicate_fn
)(CPURISCVState
*env
,
479 typedef RISCVException (*riscv_csr_read_fn
)(CPURISCVState
*env
, int csrno
,
480 target_ulong
*ret_value
);
481 typedef RISCVException (*riscv_csr_write_fn
)(CPURISCVState
*env
, int csrno
,
482 target_ulong new_value
);
483 typedef RISCVException (*riscv_csr_op_fn
)(CPURISCVState
*env
, int csrno
,
484 target_ulong
*ret_value
,
485 target_ulong new_value
,
486 target_ulong write_mask
);
490 riscv_csr_predicate_fn predicate
;
491 riscv_csr_read_fn read
;
492 riscv_csr_write_fn write
;
494 } riscv_csr_operations
;
496 /* CSR function table constants */
498 CSR_TABLE_SIZE
= 0x1000
501 /* CSR function table */
502 extern riscv_csr_operations csr_ops
[CSR_TABLE_SIZE
];
504 void riscv_get_csr_ops(int csrno
, riscv_csr_operations
*ops
);
505 void riscv_set_csr_ops(int csrno
, riscv_csr_operations
*ops
);
507 void riscv_cpu_register_gdb_regs_for_features(CPUState
*cs
);
509 #endif /* RISCV_CPU_H */