4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
27 #include "exec/cpu_ldst.h"
28 #include "exec/translator.h"
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
33 #include "trace-tcg.h"
35 #include "fpu/softfloat.h"
38 //#define DEBUG_DISPATCH 1
40 #define DEFO32(name, offset) static TCGv QREG_##name;
41 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
46 static TCGv_i32 cpu_halted
;
47 static TCGv_i32 cpu_exception_index
;
49 static char cpu_reg_names
[2 * 8 * 3 + 5 * 4];
50 static TCGv cpu_dregs
[8];
51 static TCGv cpu_aregs
[8];
52 static TCGv_i64 cpu_macc
[4];
54 #define REG(insn, pos) (((insn) >> (pos)) & 7)
55 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
56 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
57 #define MACREG(acc) cpu_macc[acc]
58 #define QREG_SP get_areg(s, 7)
60 static TCGv NULL_QREG
;
61 #define IS_NULL_QREG(t) (t == NULL_QREG)
62 /* Used to distinguish stores from bad addressing modes. */
63 static TCGv store_dummy
;
65 #include "exec/gen-icount.h"
67 void m68k_tcg_init(void)
72 #define DEFO32(name, offset) \
73 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
74 offsetof(CPUM68KState, offset), #name);
75 #define DEFO64(name, offset) \
76 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
77 offsetof(CPUM68KState, offset), #name);
82 cpu_halted
= tcg_global_mem_new_i32(cpu_env
,
83 -offsetof(M68kCPU
, env
) +
84 offsetof(CPUState
, halted
), "HALTED");
85 cpu_exception_index
= tcg_global_mem_new_i32(cpu_env
,
86 -offsetof(M68kCPU
, env
) +
87 offsetof(CPUState
, exception_index
),
91 for (i
= 0; i
< 8; i
++) {
93 cpu_dregs
[i
] = tcg_global_mem_new(cpu_env
,
94 offsetof(CPUM68KState
, dregs
[i
]), p
);
97 cpu_aregs
[i
] = tcg_global_mem_new(cpu_env
,
98 offsetof(CPUM68KState
, aregs
[i
]), p
);
101 for (i
= 0; i
< 4; i
++) {
102 sprintf(p
, "ACC%d", i
);
103 cpu_macc
[i
] = tcg_global_mem_new_i64(cpu_env
,
104 offsetof(CPUM68KState
, macc
[i
]), p
);
108 NULL_QREG
= tcg_global_mem_new(cpu_env
, -4, "NULL");
109 store_dummy
= tcg_global_mem_new(cpu_env
, -8, "NULL");
112 /* internal defines */
113 typedef struct DisasContext
{
115 target_ulong insn_pc
; /* Start of the current instruction. */
118 CCOp cc_op
; /* Current CC operation */
120 struct TranslationBlock
*tb
;
121 int singlestep_enabled
;
128 static TCGv
get_areg(DisasContext
*s
, unsigned regno
)
130 if (s
->writeback_mask
& (1 << regno
)) {
131 return s
->writeback
[regno
];
133 return cpu_aregs
[regno
];
137 static void delay_set_areg(DisasContext
*s
, unsigned regno
,
138 TCGv val
, bool give_temp
)
140 if (s
->writeback_mask
& (1 << regno
)) {
142 tcg_temp_free(s
->writeback
[regno
]);
143 s
->writeback
[regno
] = val
;
145 tcg_gen_mov_i32(s
->writeback
[regno
], val
);
148 s
->writeback_mask
|= 1 << regno
;
150 s
->writeback
[regno
] = val
;
152 TCGv tmp
= tcg_temp_new();
153 s
->writeback
[regno
] = tmp
;
154 tcg_gen_mov_i32(tmp
, val
);
159 static void do_writebacks(DisasContext
*s
)
161 unsigned mask
= s
->writeback_mask
;
163 s
->writeback_mask
= 0;
165 unsigned regno
= ctz32(mask
);
166 tcg_gen_mov_i32(cpu_aregs
[regno
], s
->writeback
[regno
]);
167 tcg_temp_free(s
->writeback
[regno
]);
173 /* is_jmp field values */
174 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
175 #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
176 #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
177 #define DISAS_JUMP_NEXT DISAS_TARGET_3
179 #if defined(CONFIG_USER_ONLY)
182 #define IS_USER(s) (!(s->tb->flags & TB_FLAGS_MSR_S))
183 #define SFC_INDEX(s) ((s->tb->flags & TB_FLAGS_SFC_S) ? \
184 MMU_KERNEL_IDX : MMU_USER_IDX)
185 #define DFC_INDEX(s) ((s->tb->flags & TB_FLAGS_DFC_S) ? \
186 MMU_KERNEL_IDX : MMU_USER_IDX)
189 typedef void (*disas_proc
)(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
);
191 #ifdef DEBUG_DISPATCH
192 #define DISAS_INSN(name) \
193 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
195 static void disas_##name(CPUM68KState *env, DisasContext *s, \
198 qemu_log("Dispatch " #name "\n"); \
199 real_disas_##name(env, s, insn); \
201 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
204 #define DISAS_INSN(name) \
205 static void disas_##name(CPUM68KState *env, DisasContext *s, \
209 static const uint8_t cc_op_live
[CC_OP_NB
] = {
210 [CC_OP_DYNAMIC
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
211 [CC_OP_FLAGS
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
212 [CC_OP_ADDB
... CC_OP_ADDL
] = CCF_X
| CCF_N
| CCF_V
,
213 [CC_OP_SUBB
... CC_OP_SUBL
] = CCF_X
| CCF_N
| CCF_V
,
214 [CC_OP_CMPB
... CC_OP_CMPL
] = CCF_X
| CCF_N
| CCF_V
,
215 [CC_OP_LOGIC
] = CCF_X
| CCF_N
218 static void set_cc_op(DisasContext
*s
, CCOp op
)
220 CCOp old_op
= s
->cc_op
;
229 /* Discard CC computation that will no longer be used.
230 Note that X and N are never dead. */
231 dead
= cc_op_live
[old_op
] & ~cc_op_live
[op
];
233 tcg_gen_discard_i32(QREG_CC_C
);
236 tcg_gen_discard_i32(QREG_CC_Z
);
239 tcg_gen_discard_i32(QREG_CC_V
);
243 /* Update the CPU env CC_OP state. */
244 static void update_cc_op(DisasContext
*s
)
246 if (!s
->cc_op_synced
) {
248 tcg_gen_movi_i32(QREG_CC_OP
, s
->cc_op
);
252 /* Generate a jump to an immediate address. */
253 static void gen_jmp_im(DisasContext
*s
, uint32_t dest
)
256 tcg_gen_movi_i32(QREG_PC
, dest
);
257 s
->is_jmp
= DISAS_JUMP
;
260 /* Generate a jump to the address in qreg DEST. */
261 static void gen_jmp(DisasContext
*s
, TCGv dest
)
264 tcg_gen_mov_i32(QREG_PC
, dest
);
265 s
->is_jmp
= DISAS_JUMP
;
268 static void gen_raise_exception(int nr
)
270 TCGv_i32 tmp
= tcg_const_i32(nr
);
272 gen_helper_raise_exception(cpu_env
, tmp
);
273 tcg_temp_free_i32(tmp
);
276 static void gen_exception(DisasContext
*s
, uint32_t where
, int nr
)
278 gen_jmp_im(s
, where
);
279 gen_raise_exception(nr
);
282 static inline void gen_addr_fault(DisasContext
*s
)
284 gen_exception(s
, s
->insn_pc
, EXCP_ADDRESS
);
287 /* Generate a load from the specified address. Narrow values are
288 sign extended to full register width. */
289 static inline TCGv
gen_load(DisasContext
*s
, int opsize
, TCGv addr
,
293 tmp
= tcg_temp_new_i32();
297 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
299 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
303 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
305 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
308 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
311 g_assert_not_reached();
316 /* Generate a store. */
317 static inline void gen_store(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
322 tcg_gen_qemu_st8(val
, addr
, index
);
325 tcg_gen_qemu_st16(val
, addr
, index
);
328 tcg_gen_qemu_st32(val
, addr
, index
);
331 g_assert_not_reached();
341 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
342 otherwise generate a store. */
343 static TCGv
gen_ldst(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
344 ea_what what
, int index
)
346 if (what
== EA_STORE
) {
347 gen_store(s
, opsize
, addr
, val
, index
);
350 return gen_load(s
, opsize
, addr
, what
== EA_LOADS
, index
);
354 /* Read a 16-bit immediate constant */
355 static inline uint16_t read_im16(CPUM68KState
*env
, DisasContext
*s
)
358 im
= cpu_lduw_code(env
, s
->pc
);
363 /* Read an 8-bit immediate constant */
364 static inline uint8_t read_im8(CPUM68KState
*env
, DisasContext
*s
)
366 return read_im16(env
, s
);
369 /* Read a 32-bit immediate constant. */
370 static inline uint32_t read_im32(CPUM68KState
*env
, DisasContext
*s
)
373 im
= read_im16(env
, s
) << 16;
374 im
|= 0xffff & read_im16(env
, s
);
378 /* Read a 64-bit immediate constant. */
379 static inline uint64_t read_im64(CPUM68KState
*env
, DisasContext
*s
)
382 im
= (uint64_t)read_im32(env
, s
) << 32;
383 im
|= (uint64_t)read_im32(env
, s
);
387 /* Calculate and address index. */
388 static TCGv
gen_addr_index(DisasContext
*s
, uint16_t ext
, TCGv tmp
)
393 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
394 if ((ext
& 0x800) == 0) {
395 tcg_gen_ext16s_i32(tmp
, add
);
398 scale
= (ext
>> 9) & 3;
400 tcg_gen_shli_i32(tmp
, add
, scale
);
406 /* Handle a base + index + displacement effective addresss.
407 A NULL_QREG base means pc-relative. */
408 static TCGv
gen_lea_indexed(CPUM68KState
*env
, DisasContext
*s
, TCGv base
)
417 ext
= read_im16(env
, s
);
419 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
422 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
) &&
423 !m68k_feature(s
->env
, M68K_FEATURE_SCALED_INDEX
)) {
428 /* full extension word format */
429 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
432 if ((ext
& 0x30) > 0x10) {
433 /* base displacement */
434 if ((ext
& 0x30) == 0x20) {
435 bd
= (int16_t)read_im16(env
, s
);
437 bd
= read_im32(env
, s
);
442 tmp
= tcg_temp_new();
443 if ((ext
& 0x44) == 0) {
445 add
= gen_addr_index(s
, ext
, tmp
);
449 if ((ext
& 0x80) == 0) {
450 /* base not suppressed */
451 if (IS_NULL_QREG(base
)) {
452 base
= tcg_const_i32(offset
+ bd
);
455 if (!IS_NULL_QREG(add
)) {
456 tcg_gen_add_i32(tmp
, add
, base
);
462 if (!IS_NULL_QREG(add
)) {
464 tcg_gen_addi_i32(tmp
, add
, bd
);
468 add
= tcg_const_i32(bd
);
470 if ((ext
& 3) != 0) {
471 /* memory indirect */
472 base
= gen_load(s
, OS_LONG
, add
, 0, IS_USER(s
));
473 if ((ext
& 0x44) == 4) {
474 add
= gen_addr_index(s
, ext
, tmp
);
475 tcg_gen_add_i32(tmp
, add
, base
);
481 /* outer displacement */
482 if ((ext
& 3) == 2) {
483 od
= (int16_t)read_im16(env
, s
);
485 od
= read_im32(env
, s
);
491 tcg_gen_addi_i32(tmp
, add
, od
);
496 /* brief extension word format */
497 tmp
= tcg_temp_new();
498 add
= gen_addr_index(s
, ext
, tmp
);
499 if (!IS_NULL_QREG(base
)) {
500 tcg_gen_add_i32(tmp
, add
, base
);
502 tcg_gen_addi_i32(tmp
, tmp
, (int8_t)ext
);
504 tcg_gen_addi_i32(tmp
, add
, offset
+ (int8_t)ext
);
511 /* Sign or zero extend a value. */
513 static inline void gen_ext(TCGv res
, TCGv val
, int opsize
, int sign
)
518 tcg_gen_ext8s_i32(res
, val
);
520 tcg_gen_ext8u_i32(res
, val
);
525 tcg_gen_ext16s_i32(res
, val
);
527 tcg_gen_ext16u_i32(res
, val
);
531 tcg_gen_mov_i32(res
, val
);
534 g_assert_not_reached();
538 /* Evaluate all the CC flags. */
540 static void gen_flush_flags(DisasContext
*s
)
551 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
552 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
553 /* Compute signed overflow for addition. */
556 tcg_gen_sub_i32(t0
, QREG_CC_N
, QREG_CC_V
);
557 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_ADDB
, 1);
558 tcg_gen_xor_i32(t1
, QREG_CC_N
, QREG_CC_V
);
559 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
561 tcg_gen_andc_i32(QREG_CC_V
, t1
, QREG_CC_V
);
568 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
569 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
570 /* Compute signed overflow for subtraction. */
573 tcg_gen_add_i32(t0
, QREG_CC_N
, QREG_CC_V
);
574 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_SUBB
, 1);
575 tcg_gen_xor_i32(t1
, QREG_CC_N
, t0
);
576 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
578 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t1
);
585 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_C
, QREG_CC_N
, QREG_CC_V
);
586 tcg_gen_sub_i32(QREG_CC_Z
, QREG_CC_N
, QREG_CC_V
);
587 gen_ext(QREG_CC_Z
, QREG_CC_Z
, s
->cc_op
- CC_OP_CMPB
, 1);
588 /* Compute signed overflow for subtraction. */
590 tcg_gen_xor_i32(t0
, QREG_CC_Z
, QREG_CC_N
);
591 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, QREG_CC_N
);
592 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t0
);
594 tcg_gen_mov_i32(QREG_CC_N
, QREG_CC_Z
);
598 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
599 tcg_gen_movi_i32(QREG_CC_C
, 0);
600 tcg_gen_movi_i32(QREG_CC_V
, 0);
604 gen_helper_flush_flags(cpu_env
, QREG_CC_OP
);
609 t0
= tcg_const_i32(s
->cc_op
);
610 gen_helper_flush_flags(cpu_env
, t0
);
616 /* Note that flush_flags also assigned to env->cc_op. */
617 s
->cc_op
= CC_OP_FLAGS
;
620 static inline TCGv
gen_extend(TCGv val
, int opsize
, int sign
)
624 if (opsize
== OS_LONG
) {
627 tmp
= tcg_temp_new();
628 gen_ext(tmp
, val
, opsize
, sign
);
634 static void gen_logic_cc(DisasContext
*s
, TCGv val
, int opsize
)
636 gen_ext(QREG_CC_N
, val
, opsize
, 1);
637 set_cc_op(s
, CC_OP_LOGIC
);
640 static void gen_update_cc_cmp(DisasContext
*s
, TCGv dest
, TCGv src
, int opsize
)
642 tcg_gen_mov_i32(QREG_CC_N
, dest
);
643 tcg_gen_mov_i32(QREG_CC_V
, src
);
644 set_cc_op(s
, CC_OP_CMPB
+ opsize
);
647 static void gen_update_cc_add(TCGv dest
, TCGv src
, int opsize
)
649 gen_ext(QREG_CC_N
, dest
, opsize
, 1);
650 tcg_gen_mov_i32(QREG_CC_V
, src
);
653 static inline int opsize_bytes(int opsize
)
656 case OS_BYTE
: return 1;
657 case OS_WORD
: return 2;
658 case OS_LONG
: return 4;
659 case OS_SINGLE
: return 4;
660 case OS_DOUBLE
: return 8;
661 case OS_EXTENDED
: return 12;
662 case OS_PACKED
: return 12;
664 g_assert_not_reached();
668 static inline int insn_opsize(int insn
)
670 switch ((insn
>> 6) & 3) {
671 case 0: return OS_BYTE
;
672 case 1: return OS_WORD
;
673 case 2: return OS_LONG
;
675 g_assert_not_reached();
679 static inline int ext_opsize(int ext
, int pos
)
681 switch ((ext
>> pos
) & 7) {
682 case 0: return OS_LONG
;
683 case 1: return OS_SINGLE
;
684 case 2: return OS_EXTENDED
;
685 case 3: return OS_PACKED
;
686 case 4: return OS_WORD
;
687 case 5: return OS_DOUBLE
;
688 case 6: return OS_BYTE
;
690 g_assert_not_reached();
694 /* Assign value to a register. If the width is less than the register width
695 only the low part of the register is set. */
696 static void gen_partset_reg(int opsize
, TCGv reg
, TCGv val
)
701 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
702 tmp
= tcg_temp_new();
703 tcg_gen_ext8u_i32(tmp
, val
);
704 tcg_gen_or_i32(reg
, reg
, tmp
);
708 tcg_gen_andi_i32(reg
, reg
, 0xffff0000);
709 tmp
= tcg_temp_new();
710 tcg_gen_ext16u_i32(tmp
, val
);
711 tcg_gen_or_i32(reg
, reg
, tmp
);
716 tcg_gen_mov_i32(reg
, val
);
719 g_assert_not_reached();
723 /* Generate code for an "effective address". Does not adjust the base
724 register for autoincrement addressing modes. */
725 static TCGv
gen_lea_mode(CPUM68KState
*env
, DisasContext
*s
,
726 int mode
, int reg0
, int opsize
)
734 case 0: /* Data register direct. */
735 case 1: /* Address register direct. */
737 case 3: /* Indirect postincrement. */
738 if (opsize
== OS_UNSIZED
) {
742 case 2: /* Indirect register */
743 return get_areg(s
, reg0
);
744 case 4: /* Indirect predecrememnt. */
745 if (opsize
== OS_UNSIZED
) {
748 reg
= get_areg(s
, reg0
);
749 tmp
= tcg_temp_new();
750 if (reg0
== 7 && opsize
== OS_BYTE
&&
751 m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
752 tcg_gen_subi_i32(tmp
, reg
, 2);
754 tcg_gen_subi_i32(tmp
, reg
, opsize_bytes(opsize
));
757 case 5: /* Indirect displacement. */
758 reg
= get_areg(s
, reg0
);
759 tmp
= tcg_temp_new();
760 ext
= read_im16(env
, s
);
761 tcg_gen_addi_i32(tmp
, reg
, (int16_t)ext
);
763 case 6: /* Indirect index + displacement. */
764 reg
= get_areg(s
, reg0
);
765 return gen_lea_indexed(env
, s
, reg
);
768 case 0: /* Absolute short. */
769 offset
= (int16_t)read_im16(env
, s
);
770 return tcg_const_i32(offset
);
771 case 1: /* Absolute long. */
772 offset
= read_im32(env
, s
);
773 return tcg_const_i32(offset
);
774 case 2: /* pc displacement */
776 offset
+= (int16_t)read_im16(env
, s
);
777 return tcg_const_i32(offset
);
778 case 3: /* pc index+displacement. */
779 return gen_lea_indexed(env
, s
, NULL_QREG
);
780 case 4: /* Immediate. */
785 /* Should never happen. */
789 static TCGv
gen_lea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
792 int mode
= extract32(insn
, 3, 3);
793 int reg0
= REG(insn
, 0);
794 return gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
797 /* Generate code to load/store a value from/into an EA. If WHAT > 0 this is
798 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
799 ADDRP is non-null for readwrite operands. */
800 static TCGv
gen_ea_mode(CPUM68KState
*env
, DisasContext
*s
, int mode
, int reg0
,
801 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
,
804 TCGv reg
, tmp
, result
;
808 case 0: /* Data register direct. */
809 reg
= cpu_dregs
[reg0
];
810 if (what
== EA_STORE
) {
811 gen_partset_reg(opsize
, reg
, val
);
814 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
816 case 1: /* Address register direct. */
817 reg
= get_areg(s
, reg0
);
818 if (what
== EA_STORE
) {
819 tcg_gen_mov_i32(reg
, val
);
822 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
824 case 2: /* Indirect register */
825 reg
= get_areg(s
, reg0
);
826 return gen_ldst(s
, opsize
, reg
, val
, what
, index
);
827 case 3: /* Indirect postincrement. */
828 reg
= get_areg(s
, reg0
);
829 result
= gen_ldst(s
, opsize
, reg
, val
, what
, index
);
830 if (what
== EA_STORE
|| !addrp
) {
831 TCGv tmp
= tcg_temp_new();
832 if (reg0
== 7 && opsize
== OS_BYTE
&&
833 m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
834 tcg_gen_addi_i32(tmp
, reg
, 2);
836 tcg_gen_addi_i32(tmp
, reg
, opsize_bytes(opsize
));
838 delay_set_areg(s
, reg0
, tmp
, true);
841 case 4: /* Indirect predecrememnt. */
842 if (addrp
&& what
== EA_STORE
) {
845 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
846 if (IS_NULL_QREG(tmp
)) {
853 result
= gen_ldst(s
, opsize
, tmp
, val
, what
, index
);
854 if (what
== EA_STORE
|| !addrp
) {
855 delay_set_areg(s
, reg0
, tmp
, false);
858 case 5: /* Indirect displacement. */
859 case 6: /* Indirect index + displacement. */
861 if (addrp
&& what
== EA_STORE
) {
864 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
865 if (IS_NULL_QREG(tmp
)) {
872 return gen_ldst(s
, opsize
, tmp
, val
, what
, index
);
875 case 0: /* Absolute short. */
876 case 1: /* Absolute long. */
877 case 2: /* pc displacement */
878 case 3: /* pc index+displacement. */
880 case 4: /* Immediate. */
881 /* Sign extend values for consistency. */
884 if (what
== EA_LOADS
) {
885 offset
= (int8_t)read_im8(env
, s
);
887 offset
= read_im8(env
, s
);
891 if (what
== EA_LOADS
) {
892 offset
= (int16_t)read_im16(env
, s
);
894 offset
= read_im16(env
, s
);
898 offset
= read_im32(env
, s
);
901 g_assert_not_reached();
903 return tcg_const_i32(offset
);
908 /* Should never happen. */
912 static TCGv
gen_ea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
913 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
, int index
)
915 int mode
= extract32(insn
, 3, 3);
916 int reg0
= REG(insn
, 0);
917 return gen_ea_mode(env
, s
, mode
, reg0
, opsize
, val
, addrp
, what
, index
);
920 static TCGv_ptr
gen_fp_ptr(int freg
)
922 TCGv_ptr fp
= tcg_temp_new_ptr();
923 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fregs
[freg
]));
927 static TCGv_ptr
gen_fp_result_ptr(void)
929 TCGv_ptr fp
= tcg_temp_new_ptr();
930 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fp_result
));
934 static void gen_fp_move(TCGv_ptr dest
, TCGv_ptr src
)
939 t32
= tcg_temp_new();
940 tcg_gen_ld16u_i32(t32
, src
, offsetof(FPReg
, l
.upper
));
941 tcg_gen_st16_i32(t32
, dest
, offsetof(FPReg
, l
.upper
));
944 t64
= tcg_temp_new_i64();
945 tcg_gen_ld_i64(t64
, src
, offsetof(FPReg
, l
.lower
));
946 tcg_gen_st_i64(t64
, dest
, offsetof(FPReg
, l
.lower
));
947 tcg_temp_free_i64(t64
);
950 static void gen_load_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
,
956 t64
= tcg_temp_new_i64();
957 tmp
= tcg_temp_new();
960 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
961 gen_helper_exts32(cpu_env
, fp
, tmp
);
964 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
965 gen_helper_exts32(cpu_env
, fp
, tmp
);
968 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
969 gen_helper_exts32(cpu_env
, fp
, tmp
);
972 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
973 gen_helper_extf32(cpu_env
, fp
, tmp
);
976 tcg_gen_qemu_ld64(t64
, addr
, index
);
977 gen_helper_extf64(cpu_env
, fp
, t64
);
980 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
981 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
984 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
985 tcg_gen_shri_i32(tmp
, tmp
, 16);
986 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
987 tcg_gen_addi_i32(tmp
, addr
, 4);
988 tcg_gen_qemu_ld64(t64
, tmp
, index
);
989 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
992 /* unimplemented data type on 68040/ColdFire
993 * FIXME if needed for another FPU
995 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
998 g_assert_not_reached();
1001 tcg_temp_free_i64(t64
);
1004 static void gen_store_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
,
1010 t64
= tcg_temp_new_i64();
1011 tmp
= tcg_temp_new();
1014 gen_helper_reds32(tmp
, cpu_env
, fp
);
1015 tcg_gen_qemu_st8(tmp
, addr
, index
);
1018 gen_helper_reds32(tmp
, cpu_env
, fp
);
1019 tcg_gen_qemu_st16(tmp
, addr
, index
);
1022 gen_helper_reds32(tmp
, cpu_env
, fp
);
1023 tcg_gen_qemu_st32(tmp
, addr
, index
);
1026 gen_helper_redf32(tmp
, cpu_env
, fp
);
1027 tcg_gen_qemu_st32(tmp
, addr
, index
);
1030 gen_helper_redf64(t64
, cpu_env
, fp
);
1031 tcg_gen_qemu_st64(t64
, addr
, index
);
1034 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1035 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1038 tcg_gen_ld16u_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1039 tcg_gen_shli_i32(tmp
, tmp
, 16);
1040 tcg_gen_qemu_st32(tmp
, addr
, index
);
1041 tcg_gen_addi_i32(tmp
, addr
, 4);
1042 tcg_gen_ld_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1043 tcg_gen_qemu_st64(t64
, tmp
, index
);
1046 /* unimplemented data type on 68040/ColdFire
1047 * FIXME if needed for another FPU
1049 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1052 g_assert_not_reached();
1055 tcg_temp_free_i64(t64
);
1058 static void gen_ldst_fp(DisasContext
*s
, int opsize
, TCGv addr
,
1059 TCGv_ptr fp
, ea_what what
, int index
)
1061 if (what
== EA_STORE
) {
1062 gen_store_fp(s
, opsize
, addr
, fp
, index
);
1064 gen_load_fp(s
, opsize
, addr
, fp
, index
);
1068 static int gen_ea_mode_fp(CPUM68KState
*env
, DisasContext
*s
, int mode
,
1069 int reg0
, int opsize
, TCGv_ptr fp
, ea_what what
,
1072 TCGv reg
, addr
, tmp
;
1076 case 0: /* Data register direct. */
1077 reg
= cpu_dregs
[reg0
];
1078 if (what
== EA_STORE
) {
1083 gen_helper_reds32(reg
, cpu_env
, fp
);
1086 gen_helper_redf32(reg
, cpu_env
, fp
);
1089 g_assert_not_reached();
1092 tmp
= tcg_temp_new();
1095 tcg_gen_ext8s_i32(tmp
, reg
);
1096 gen_helper_exts32(cpu_env
, fp
, tmp
);
1099 tcg_gen_ext16s_i32(tmp
, reg
);
1100 gen_helper_exts32(cpu_env
, fp
, tmp
);
1103 gen_helper_exts32(cpu_env
, fp
, reg
);
1106 gen_helper_extf32(cpu_env
, fp
, reg
);
1109 g_assert_not_reached();
1114 case 1: /* Address register direct. */
1116 case 2: /* Indirect register */
1117 addr
= get_areg(s
, reg0
);
1118 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1120 case 3: /* Indirect postincrement. */
1121 addr
= cpu_aregs
[reg0
];
1122 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1123 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(opsize
));
1125 case 4: /* Indirect predecrememnt. */
1126 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1127 if (IS_NULL_QREG(addr
)) {
1130 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1131 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
1133 case 5: /* Indirect displacement. */
1134 case 6: /* Indirect index + displacement. */
1136 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1137 if (IS_NULL_QREG(addr
)) {
1140 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1144 case 0: /* Absolute short. */
1145 case 1: /* Absolute long. */
1146 case 2: /* pc displacement */
1147 case 3: /* pc index+displacement. */
1149 case 4: /* Immediate. */
1150 if (what
== EA_STORE
) {
1155 tmp
= tcg_const_i32((int8_t)read_im8(env
, s
));
1156 gen_helper_exts32(cpu_env
, fp
, tmp
);
1160 tmp
= tcg_const_i32((int16_t)read_im16(env
, s
));
1161 gen_helper_exts32(cpu_env
, fp
, tmp
);
1165 tmp
= tcg_const_i32(read_im32(env
, s
));
1166 gen_helper_exts32(cpu_env
, fp
, tmp
);
1170 tmp
= tcg_const_i32(read_im32(env
, s
));
1171 gen_helper_extf32(cpu_env
, fp
, tmp
);
1175 t64
= tcg_const_i64(read_im64(env
, s
));
1176 gen_helper_extf64(cpu_env
, fp
, t64
);
1177 tcg_temp_free_i64(t64
);
1180 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1181 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1184 tmp
= tcg_const_i32(read_im32(env
, s
) >> 16);
1185 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1187 t64
= tcg_const_i64(read_im64(env
, s
));
1188 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1189 tcg_temp_free_i64(t64
);
1192 /* unimplemented data type on 68040/ColdFire
1193 * FIXME if needed for another FPU
1195 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1198 g_assert_not_reached();
1208 static int gen_ea_fp(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
1209 int opsize
, TCGv_ptr fp
, ea_what what
, int index
)
1211 int mode
= extract32(insn
, 3, 3);
1212 int reg0
= REG(insn
, 0);
1213 return gen_ea_mode_fp(env
, s
, mode
, reg0
, opsize
, fp
, what
, index
);
1224 static void gen_cc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
1230 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1231 if (op
== CC_OP_CMPB
|| op
== CC_OP_CMPW
|| op
== CC_OP_CMPL
) {
1238 tcond
= TCG_COND_LEU
;
1242 tcond
= TCG_COND_LTU
;
1246 tcond
= TCG_COND_EQ
;
1251 c
->v2
= tcg_const_i32(0);
1252 c
->v1
= tmp
= tcg_temp_new();
1253 tcg_gen_sub_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1254 gen_ext(tmp
, tmp
, op
- CC_OP_CMPB
, 1);
1258 tcond
= TCG_COND_LT
;
1262 tcond
= TCG_COND_LE
;
1269 c
->v2
= tcg_const_i32(0);
1275 tcond
= TCG_COND_NEVER
;
1277 case 14: /* GT (!(Z || (N ^ V))) */
1278 case 15: /* LE (Z || (N ^ V)) */
1279 /* Logic operations clear V, which simplifies LE to (Z || N),
1280 and since Z and N are co-located, this becomes a normal
1282 if (op
== CC_OP_LOGIC
) {
1284 tcond
= TCG_COND_LE
;
1288 case 12: /* GE (!(N ^ V)) */
1289 case 13: /* LT (N ^ V) */
1290 /* Logic operations clear V, which simplifies this to N. */
1291 if (op
!= CC_OP_LOGIC
) {
1295 case 10: /* PL (!N) */
1296 case 11: /* MI (N) */
1297 /* Several cases represent N normally. */
1298 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1299 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1300 op
== CC_OP_LOGIC
) {
1302 tcond
= TCG_COND_LT
;
1306 case 6: /* NE (!Z) */
1307 case 7: /* EQ (Z) */
1308 /* Some cases fold Z into N. */
1309 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1310 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1311 op
== CC_OP_LOGIC
) {
1312 tcond
= TCG_COND_EQ
;
1317 case 4: /* CC (!C) */
1318 case 5: /* CS (C) */
1319 /* Some cases fold C into X. */
1320 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1321 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
) {
1322 tcond
= TCG_COND_NE
;
1327 case 8: /* VC (!V) */
1328 case 9: /* VS (V) */
1329 /* Logic operations clear V and C. */
1330 if (op
== CC_OP_LOGIC
) {
1331 tcond
= TCG_COND_NEVER
;
1338 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1345 /* Invalid, or handled above. */
1347 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1348 case 3: /* LS (C || Z) */
1349 c
->v1
= tmp
= tcg_temp_new();
1351 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1352 tcg_gen_or_i32(tmp
, tmp
, QREG_CC_C
);
1353 tcond
= TCG_COND_NE
;
1355 case 4: /* CC (!C) */
1356 case 5: /* CS (C) */
1358 tcond
= TCG_COND_NE
;
1360 case 6: /* NE (!Z) */
1361 case 7: /* EQ (Z) */
1363 tcond
= TCG_COND_EQ
;
1365 case 8: /* VC (!V) */
1366 case 9: /* VS (V) */
1368 tcond
= TCG_COND_LT
;
1370 case 10: /* PL (!N) */
1371 case 11: /* MI (N) */
1373 tcond
= TCG_COND_LT
;
1375 case 12: /* GE (!(N ^ V)) */
1376 case 13: /* LT (N ^ V) */
1377 c
->v1
= tmp
= tcg_temp_new();
1379 tcg_gen_xor_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1380 tcond
= TCG_COND_LT
;
1382 case 14: /* GT (!(Z || (N ^ V))) */
1383 case 15: /* LE (Z || (N ^ V)) */
1384 c
->v1
= tmp
= tcg_temp_new();
1386 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1387 tcg_gen_neg_i32(tmp
, tmp
);
1388 tmp2
= tcg_temp_new();
1389 tcg_gen_xor_i32(tmp2
, QREG_CC_N
, QREG_CC_V
);
1390 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1391 tcg_temp_free(tmp2
);
1392 tcond
= TCG_COND_LT
;
1397 if ((cond
& 1) == 0) {
1398 tcond
= tcg_invert_cond(tcond
);
1403 static void free_cond(DisasCompare
*c
)
1406 tcg_temp_free(c
->v1
);
1409 tcg_temp_free(c
->v2
);
1413 static void gen_jmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
1417 gen_cc_cond(&c
, s
, cond
);
1419 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
1423 /* Force a TB lookup after an instruction that changes the CPU state. */
1424 static void gen_lookup_tb(DisasContext
*s
)
1427 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
1428 s
->is_jmp
= DISAS_UPDATE
;
1431 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1432 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1433 op_sign ? EA_LOADS : EA_LOADU, IS_USER(s)); \
1434 if (IS_NULL_QREG(result)) { \
1435 gen_addr_fault(s); \
1440 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1441 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, \
1442 EA_STORE, IS_USER(s)); \
1443 if (IS_NULL_QREG(ea_result)) { \
1444 gen_addr_fault(s); \
1449 static inline bool use_goto_tb(DisasContext
*s
, uint32_t dest
)
1451 #ifndef CONFIG_USER_ONLY
1452 return (s
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
1453 (s
->insn_pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
1459 /* Generate a jump to an immediate address. */
1460 static void gen_jmp_tb(DisasContext
*s
, int n
, uint32_t dest
)
1462 if (unlikely(s
->singlestep_enabled
)) {
1463 gen_exception(s
, dest
, EXCP_DEBUG
);
1464 } else if (use_goto_tb(s
, dest
)) {
1466 tcg_gen_movi_i32(QREG_PC
, dest
);
1467 tcg_gen_exit_tb((uintptr_t)s
->tb
+ n
);
1469 gen_jmp_im(s
, dest
);
1472 s
->is_jmp
= DISAS_TB_JUMP
;
1481 cond
= (insn
>> 8) & 0xf;
1482 gen_cc_cond(&c
, s
, cond
);
1484 tmp
= tcg_temp_new();
1485 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
1488 tcg_gen_neg_i32(tmp
, tmp
);
1489 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
1501 reg
= DREG(insn
, 0);
1503 offset
= (int16_t)read_im16(env
, s
);
1504 l1
= gen_new_label();
1505 gen_jmpcc(s
, (insn
>> 8) & 0xf, l1
);
1507 tmp
= tcg_temp_new();
1508 tcg_gen_ext16s_i32(tmp
, reg
);
1509 tcg_gen_addi_i32(tmp
, tmp
, -1);
1510 gen_partset_reg(OS_WORD
, reg
, tmp
);
1511 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, -1, l1
);
1512 gen_jmp_tb(s
, 1, base
+ offset
);
1514 gen_jmp_tb(s
, 0, s
->pc
);
1517 DISAS_INSN(undef_mac
)
1519 gen_exception(s
, s
->insn_pc
, EXCP_LINEA
);
1522 DISAS_INSN(undef_fpu
)
1524 gen_exception(s
, s
->insn_pc
, EXCP_LINEF
);
1529 /* ??? This is both instructions that are as yet unimplemented
1530 for the 680x0 series, as well as those that are implemented
1531 but actually illegal for CPU32 or pre-68020. */
1532 qemu_log_mask(LOG_UNIMP
, "Illegal instruction: %04x @ %08x",
1534 gen_exception(s
, s
->insn_pc
, EXCP_UNSUPPORTED
);
1544 sign
= (insn
& 0x100) != 0;
1545 reg
= DREG(insn
, 9);
1546 tmp
= tcg_temp_new();
1548 tcg_gen_ext16s_i32(tmp
, reg
);
1550 tcg_gen_ext16u_i32(tmp
, reg
);
1551 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1552 tcg_gen_mul_i32(tmp
, tmp
, src
);
1553 tcg_gen_mov_i32(reg
, tmp
);
1554 gen_logic_cc(s
, tmp
, OS_LONG
);
1564 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1566 sign
= (insn
& 0x100) != 0;
1568 /* dest.l / src.w */
1570 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1571 destr
= tcg_const_i32(REG(insn
, 9));
1573 gen_helper_divsw(cpu_env
, destr
, src
);
1575 gen_helper_divuw(cpu_env
, destr
, src
);
1577 tcg_temp_free(destr
);
1579 set_cc_op(s
, CC_OP_FLAGS
);
1588 ext
= read_im16(env
, s
);
1590 sign
= (ext
& 0x0800) != 0;
1593 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
1594 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
1598 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1600 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1601 num
= tcg_const_i32(REG(ext
, 12));
1602 reg
= tcg_const_i32(REG(ext
, 0));
1604 gen_helper_divsll(cpu_env
, num
, reg
, den
);
1606 gen_helper_divull(cpu_env
, num
, reg
, den
);
1610 set_cc_op(s
, CC_OP_FLAGS
);
1614 /* divX.l <EA>, Dq 32/32 -> 32q */
1615 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1617 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1618 num
= tcg_const_i32(REG(ext
, 12));
1619 reg
= tcg_const_i32(REG(ext
, 0));
1621 gen_helper_divsl(cpu_env
, num
, reg
, den
);
1623 gen_helper_divul(cpu_env
, num
, reg
, den
);
1628 set_cc_op(s
, CC_OP_FLAGS
);
1631 static void bcd_add(TCGv dest
, TCGv src
)
1635 /* dest10 = dest10 + src10 + X
1639 * t3 = t2 + dest + X
1643 * t7 = (t6 >> 2) | (t6 >> 3)
1647 /* t1 = (src + 0x066) + dest + X
1648 * = result with some possible exceding 0x6
1651 t0
= tcg_const_i32(0x066);
1652 tcg_gen_add_i32(t0
, t0
, src
);
1654 t1
= tcg_temp_new();
1655 tcg_gen_add_i32(t1
, t0
, dest
);
1656 tcg_gen_add_i32(t1
, t1
, QREG_CC_X
);
1658 /* we will remove exceding 0x6 where there is no carry */
1660 /* t0 = (src + 0x0066) ^ dest
1661 * = t1 without carries
1664 tcg_gen_xor_i32(t0
, t0
, dest
);
1666 /* extract the carries
1668 * = only the carries
1671 tcg_gen_xor_i32(t0
, t0
, t1
);
1673 /* generate 0x1 where there is no carry
1674 * and for each 0x10, generate a 0x6
1677 tcg_gen_shri_i32(t0
, t0
, 3);
1678 tcg_gen_not_i32(t0
, t0
);
1679 tcg_gen_andi_i32(t0
, t0
, 0x22);
1680 tcg_gen_add_i32(dest
, t0
, t0
);
1681 tcg_gen_add_i32(dest
, dest
, t0
);
1684 /* remove the exceding 0x6
1685 * for digits that have not generated a carry
1688 tcg_gen_sub_i32(dest
, t1
, dest
);
1692 static void bcd_sub(TCGv dest
, TCGv src
)
1696 /* dest10 = dest10 - src10 - X
1697 * = bcd_add(dest + 1 - X, 0x199 - src)
1700 /* t0 = 0x066 + (0x199 - src) */
1702 t0
= tcg_temp_new();
1703 tcg_gen_subfi_i32(t0
, 0x1ff, src
);
1705 /* t1 = t0 + dest + 1 - X*/
1707 t1
= tcg_temp_new();
1708 tcg_gen_add_i32(t1
, t0
, dest
);
1709 tcg_gen_addi_i32(t1
, t1
, 1);
1710 tcg_gen_sub_i32(t1
, t1
, QREG_CC_X
);
1712 /* t2 = t0 ^ dest */
1714 t2
= tcg_temp_new();
1715 tcg_gen_xor_i32(t2
, t0
, dest
);
1719 tcg_gen_xor_i32(t0
, t1
, t2
);
1722 * t0 = (t2 >> 2) | (t2 >> 3)
1724 * to fit on 8bit operands, changed in:
1726 * t2 = ~(t0 >> 3) & 0x22
1731 tcg_gen_shri_i32(t2
, t0
, 3);
1732 tcg_gen_not_i32(t2
, t2
);
1733 tcg_gen_andi_i32(t2
, t2
, 0x22);
1734 tcg_gen_add_i32(t0
, t2
, t2
);
1735 tcg_gen_add_i32(t0
, t0
, t2
);
1738 /* return t1 - t0 */
1740 tcg_gen_sub_i32(dest
, t1
, t0
);
1745 static void bcd_flags(TCGv val
)
1747 tcg_gen_andi_i32(QREG_CC_C
, val
, 0x0ff);
1748 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_C
);
1750 tcg_gen_extract_i32(QREG_CC_C
, val
, 8, 1);
1752 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
1755 DISAS_INSN(abcd_reg
)
1760 gen_flush_flags(s
); /* !Z is sticky */
1762 src
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
1763 dest
= gen_extend(DREG(insn
, 9), OS_BYTE
, 0);
1765 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1770 DISAS_INSN(abcd_mem
)
1772 TCGv src
, dest
, addr
;
1774 gen_flush_flags(s
); /* !Z is sticky */
1776 /* Indirect pre-decrement load (mode 4) */
1778 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1779 NULL_QREG
, NULL
, EA_LOADU
, IS_USER(s
));
1780 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1781 NULL_QREG
, &addr
, EA_LOADU
, IS_USER(s
));
1785 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
,
1786 EA_STORE
, IS_USER(s
));
1791 DISAS_INSN(sbcd_reg
)
1795 gen_flush_flags(s
); /* !Z is sticky */
1797 src
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
1798 dest
= gen_extend(DREG(insn
, 9), OS_BYTE
, 0);
1802 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1807 DISAS_INSN(sbcd_mem
)
1809 TCGv src
, dest
, addr
;
1811 gen_flush_flags(s
); /* !Z is sticky */
1813 /* Indirect pre-decrement load (mode 4) */
1815 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1816 NULL_QREG
, NULL
, EA_LOADU
, IS_USER(s
));
1817 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1818 NULL_QREG
, &addr
, EA_LOADU
, IS_USER(s
));
1822 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
,
1823 EA_STORE
, IS_USER(s
));
1833 gen_flush_flags(s
); /* !Z is sticky */
1835 SRC_EA(env
, src
, OS_BYTE
, 0, &addr
);
1837 dest
= tcg_const_i32(0);
1840 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
1844 tcg_temp_free(dest
);
1857 add
= (insn
& 0x4000) != 0;
1858 opsize
= insn_opsize(insn
);
1859 reg
= gen_extend(DREG(insn
, 9), opsize
, 1);
1860 dest
= tcg_temp_new();
1862 SRC_EA(env
, tmp
, opsize
, 1, &addr
);
1866 SRC_EA(env
, src
, opsize
, 1, NULL
);
1869 tcg_gen_add_i32(dest
, tmp
, src
);
1870 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src
);
1871 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
1873 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, tmp
, src
);
1874 tcg_gen_sub_i32(dest
, tmp
, src
);
1875 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
1877 gen_update_cc_add(dest
, src
, opsize
);
1879 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1881 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
1883 tcg_temp_free(dest
);
1886 /* Reverse the order of the bits in REG. */
1890 reg
= DREG(insn
, 0);
1891 gen_helper_bitrev(reg
, reg
);
1894 DISAS_INSN(bitop_reg
)
1904 if ((insn
& 0x38) != 0)
1908 op
= (insn
>> 6) & 3;
1909 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1912 src2
= tcg_temp_new();
1913 if (opsize
== OS_BYTE
)
1914 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 7);
1916 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 31);
1918 tmp
= tcg_const_i32(1);
1919 tcg_gen_shl_i32(tmp
, tmp
, src2
);
1920 tcg_temp_free(src2
);
1922 tcg_gen_and_i32(QREG_CC_Z
, src1
, tmp
);
1924 dest
= tcg_temp_new();
1927 tcg_gen_xor_i32(dest
, src1
, tmp
);
1930 tcg_gen_andc_i32(dest
, src1
, tmp
);
1933 tcg_gen_or_i32(dest
, src1
, tmp
);
1940 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1942 tcg_temp_free(dest
);
1948 reg
= DREG(insn
, 0);
1950 gen_helper_sats(reg
, reg
, QREG_CC_V
);
1951 gen_logic_cc(s
, reg
, OS_LONG
);
1954 static void gen_push(DisasContext
*s
, TCGv val
)
1958 tmp
= tcg_temp_new();
1959 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1960 gen_store(s
, OS_LONG
, tmp
, val
, IS_USER(s
));
1961 tcg_gen_mov_i32(QREG_SP
, tmp
);
1965 static TCGv
mreg(int reg
)
1969 return cpu_dregs
[reg
];
1972 return cpu_aregs
[reg
& 7];
1977 TCGv addr
, incr
, tmp
, r
[16];
1978 int is_load
= (insn
& 0x0400) != 0;
1979 int opsize
= (insn
& 0x40) != 0 ? OS_LONG
: OS_WORD
;
1980 uint16_t mask
= read_im16(env
, s
);
1981 int mode
= extract32(insn
, 3, 3);
1982 int reg0
= REG(insn
, 0);
1985 tmp
= cpu_aregs
[reg0
];
1988 case 0: /* data register direct */
1989 case 1: /* addr register direct */
1994 case 2: /* indirect */
1997 case 3: /* indirect post-increment */
1999 /* post-increment is not allowed */
2004 case 4: /* indirect pre-decrement */
2006 /* pre-decrement is not allowed */
2009 /* We want a bare copy of the address reg, without any pre-decrement
2010 adjustment, as gen_lea would provide. */
2014 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
2015 if (IS_NULL_QREG(tmp
)) {
2021 addr
= tcg_temp_new();
2022 tcg_gen_mov_i32(addr
, tmp
);
2023 incr
= tcg_const_i32(opsize_bytes(opsize
));
2026 /* memory to register */
2027 for (i
= 0; i
< 16; i
++) {
2028 if (mask
& (1 << i
)) {
2029 r
[i
] = gen_load(s
, opsize
, addr
, 1, IS_USER(s
));
2030 tcg_gen_add_i32(addr
, addr
, incr
);
2033 for (i
= 0; i
< 16; i
++) {
2034 if (mask
& (1 << i
)) {
2035 tcg_gen_mov_i32(mreg(i
), r
[i
]);
2036 tcg_temp_free(r
[i
]);
2040 /* post-increment: movem (An)+,X */
2041 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2044 /* register to memory */
2046 /* pre-decrement: movem X,-(An) */
2047 for (i
= 15; i
>= 0; i
--) {
2048 if ((mask
<< i
) & 0x8000) {
2049 tcg_gen_sub_i32(addr
, addr
, incr
);
2050 if (reg0
+ 8 == i
&&
2051 m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
)) {
2052 /* M68020+: if the addressing register is the
2053 * register moved to memory, the value written
2054 * is the initial value decremented by the size of
2055 * the operation, regardless of how many actual
2056 * stores have been performed until this point.
2057 * M68000/M68010: the value is the initial value.
2059 tmp
= tcg_temp_new();
2060 tcg_gen_sub_i32(tmp
, cpu_aregs
[reg0
], incr
);
2061 gen_store(s
, opsize
, addr
, tmp
, IS_USER(s
));
2064 gen_store(s
, opsize
, addr
, mreg(i
), IS_USER(s
));
2068 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2070 for (i
= 0; i
< 16; i
++) {
2071 if (mask
& (1 << i
)) {
2072 gen_store(s
, opsize
, addr
, mreg(i
), IS_USER(s
));
2073 tcg_gen_add_i32(addr
, addr
, incr
);
2079 tcg_temp_free(incr
);
2080 tcg_temp_free(addr
);
2092 displ
= read_im16(env
, s
);
2094 addr
= AREG(insn
, 0);
2095 reg
= DREG(insn
, 9);
2097 abuf
= tcg_temp_new();
2098 tcg_gen_addi_i32(abuf
, addr
, displ
);
2099 dbuf
= tcg_temp_new();
2108 for ( ; i
> 0 ; i
--) {
2109 tcg_gen_shri_i32(dbuf
, reg
, (i
- 1) * 8);
2110 tcg_gen_qemu_st8(dbuf
, abuf
, IS_USER(s
));
2112 tcg_gen_addi_i32(abuf
, abuf
, 2);
2116 for ( ; i
> 0 ; i
--) {
2117 tcg_gen_qemu_ld8u(dbuf
, abuf
, IS_USER(s
));
2118 tcg_gen_deposit_i32(reg
, reg
, dbuf
, (i
- 1) * 8, 8);
2120 tcg_gen_addi_i32(abuf
, abuf
, 2);
2124 tcg_temp_free(abuf
);
2125 tcg_temp_free(dbuf
);
2128 DISAS_INSN(bitop_im
)
2138 if ((insn
& 0x38) != 0)
2142 op
= (insn
>> 6) & 3;
2144 bitnum
= read_im16(env
, s
);
2145 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
2146 if (bitnum
& 0xfe00) {
2147 disas_undef(env
, s
, insn
);
2151 if (bitnum
& 0xff00) {
2152 disas_undef(env
, s
, insn
);
2157 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
2160 if (opsize
== OS_BYTE
)
2166 tcg_gen_andi_i32(QREG_CC_Z
, src1
, mask
);
2169 tmp
= tcg_temp_new();
2172 tcg_gen_xori_i32(tmp
, src1
, mask
);
2175 tcg_gen_andi_i32(tmp
, src1
, ~mask
);
2178 tcg_gen_ori_i32(tmp
, src1
, mask
);
2183 DEST_EA(env
, insn
, opsize
, tmp
, &addr
);
2188 static TCGv
gen_get_ccr(DisasContext
*s
)
2193 dest
= tcg_temp_new();
2194 gen_helper_get_ccr(dest
, cpu_env
);
2198 static TCGv
gen_get_sr(DisasContext
*s
)
2203 ccr
= gen_get_ccr(s
);
2204 sr
= tcg_temp_new();
2205 tcg_gen_andi_i32(sr
, QREG_SR
, 0xffe0);
2206 tcg_gen_or_i32(sr
, sr
, ccr
);
2210 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
2213 tcg_gen_movi_i32(QREG_CC_C
, val
& CCF_C
? 1 : 0);
2214 tcg_gen_movi_i32(QREG_CC_V
, val
& CCF_V
? -1 : 0);
2215 tcg_gen_movi_i32(QREG_CC_Z
, val
& CCF_Z
? 0 : 1);
2216 tcg_gen_movi_i32(QREG_CC_N
, val
& CCF_N
? -1 : 0);
2217 tcg_gen_movi_i32(QREG_CC_X
, val
& CCF_X
? 1 : 0);
2219 TCGv sr
= tcg_const_i32(val
);
2220 gen_helper_set_sr(cpu_env
, sr
);
2223 set_cc_op(s
, CC_OP_FLAGS
);
2226 static void gen_set_sr(DisasContext
*s
, TCGv val
, int ccr_only
)
2229 gen_helper_set_ccr(cpu_env
, val
);
2231 gen_helper_set_sr(cpu_env
, val
);
2233 set_cc_op(s
, CC_OP_FLAGS
);
2236 static void gen_move_to_sr(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
2239 if ((insn
& 0x3f) == 0x3c) {
2241 val
= read_im16(env
, s
);
2242 gen_set_sr_im(s
, val
, ccr_only
);
2245 SRC_EA(env
, src
, OS_WORD
, 0, NULL
);
2246 gen_set_sr(s
, src
, ccr_only
);
2250 DISAS_INSN(arith_im
)
2258 bool with_SR
= ((insn
& 0x3f) == 0x3c);
2260 op
= (insn
>> 9) & 7;
2261 opsize
= insn_opsize(insn
);
2264 im
= tcg_const_i32((int8_t)read_im8(env
, s
));
2267 im
= tcg_const_i32((int16_t)read_im16(env
, s
));
2270 im
= tcg_const_i32(read_im32(env
, s
));
2277 /* SR/CCR can only be used with andi/eori/ori */
2278 if (op
== 2 || op
== 3 || op
== 6) {
2279 disas_undef(env
, s
, insn
);
2284 src1
= gen_get_ccr(s
);
2288 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
2291 src1
= gen_get_sr(s
);
2294 disas_undef(env
, s
, insn
);
2298 SRC_EA(env
, src1
, opsize
, 1, (op
== 6) ? NULL
: &addr
);
2300 dest
= tcg_temp_new();
2303 tcg_gen_or_i32(dest
, src1
, im
);
2305 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2307 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2308 gen_logic_cc(s
, dest
, opsize
);
2312 tcg_gen_and_i32(dest
, src1
, im
);
2314 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2316 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2317 gen_logic_cc(s
, dest
, opsize
);
2321 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, src1
, im
);
2322 tcg_gen_sub_i32(dest
, src1
, im
);
2323 gen_update_cc_add(dest
, im
, opsize
);
2324 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2325 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2328 tcg_gen_add_i32(dest
, src1
, im
);
2329 gen_update_cc_add(dest
, im
, opsize
);
2330 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
2331 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
2332 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2335 tcg_gen_xor_i32(dest
, src1
, im
);
2337 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2339 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2340 gen_logic_cc(s
, dest
, opsize
);
2344 gen_update_cc_cmp(s
, src1
, im
, opsize
);
2350 tcg_temp_free(dest
);
2362 switch ((insn
>> 9) & 3) {
2376 g_assert_not_reached();
2379 ext
= read_im16(env
, s
);
2381 /* cas Dc,Du,<EA> */
2383 addr
= gen_lea(env
, s
, insn
, opsize
);
2384 if (IS_NULL_QREG(addr
)) {
2389 cmp
= gen_extend(DREG(ext
, 0), opsize
, 1);
2391 /* if <EA> == Dc then
2393 * Dc = <EA> (because <EA> == Dc)
2398 load
= tcg_temp_new();
2399 tcg_gen_atomic_cmpxchg_i32(load
, addr
, cmp
, DREG(ext
, 6),
2401 /* update flags before setting cmp to load */
2402 gen_update_cc_cmp(s
, load
, cmp
, opsize
);
2403 gen_partset_reg(opsize
, DREG(ext
, 0), load
);
2405 tcg_temp_free(load
);
2407 switch (extract32(insn
, 3, 3)) {
2408 case 3: /* Indirect postincrement. */
2409 tcg_gen_addi_i32(AREG(insn
, 0), addr
, opsize_bytes(opsize
));
2411 case 4: /* Indirect predecrememnt. */
2412 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
2419 uint16_t ext1
, ext2
;
2423 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2425 ext1
= read_im16(env
, s
);
2427 if (ext1
& 0x8000) {
2428 /* Address Register */
2429 addr1
= AREG(ext1
, 12);
2432 addr1
= DREG(ext1
, 12);
2435 ext2
= read_im16(env
, s
);
2436 if (ext2
& 0x8000) {
2437 /* Address Register */
2438 addr2
= AREG(ext2
, 12);
2441 addr2
= DREG(ext2
, 12);
2444 /* if (R1) == Dc1 && (R2) == Dc2 then
2452 regs
= tcg_const_i32(REG(ext2
, 6) |
2453 (REG(ext1
, 6) << 3) |
2454 (REG(ext2
, 0) << 6) |
2455 (REG(ext1
, 0) << 9));
2456 if (tb_cflags(s
->tb
) & CF_PARALLEL
) {
2457 gen_helper_exit_atomic(cpu_env
);
2459 gen_helper_cas2w(cpu_env
, regs
, addr1
, addr2
);
2461 tcg_temp_free(regs
);
2463 /* Note that cas2w also assigned to env->cc_op. */
2464 s
->cc_op
= CC_OP_CMPW
;
2465 s
->cc_op_synced
= 1;
2470 uint16_t ext1
, ext2
;
2471 TCGv addr1
, addr2
, regs
;
2473 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2475 ext1
= read_im16(env
, s
);
2477 if (ext1
& 0x8000) {
2478 /* Address Register */
2479 addr1
= AREG(ext1
, 12);
2482 addr1
= DREG(ext1
, 12);
2485 ext2
= read_im16(env
, s
);
2486 if (ext2
& 0x8000) {
2487 /* Address Register */
2488 addr2
= AREG(ext2
, 12);
2491 addr2
= DREG(ext2
, 12);
2494 /* if (R1) == Dc1 && (R2) == Dc2 then
2502 regs
= tcg_const_i32(REG(ext2
, 6) |
2503 (REG(ext1
, 6) << 3) |
2504 (REG(ext2
, 0) << 6) |
2505 (REG(ext1
, 0) << 9));
2506 if (tb_cflags(s
->tb
) & CF_PARALLEL
) {
2507 gen_helper_cas2l_parallel(cpu_env
, regs
, addr1
, addr2
);
2509 gen_helper_cas2l(cpu_env
, regs
, addr1
, addr2
);
2511 tcg_temp_free(regs
);
2513 /* Note that cas2l also assigned to env->cc_op. */
2514 s
->cc_op
= CC_OP_CMPL
;
2515 s
->cc_op_synced
= 1;
2522 reg
= DREG(insn
, 0);
2523 tcg_gen_bswap32_i32(reg
, reg
);
2533 switch (insn
>> 12) {
2534 case 1: /* move.b */
2537 case 2: /* move.l */
2540 case 3: /* move.w */
2546 SRC_EA(env
, src
, opsize
, 1, NULL
);
2547 op
= (insn
>> 6) & 7;
2550 /* The value will already have been sign extended. */
2551 dest
= AREG(insn
, 9);
2552 tcg_gen_mov_i32(dest
, src
);
2556 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
2557 DEST_EA(env
, dest_ea
, opsize
, src
, NULL
);
2558 /* This will be correct because loads sign extend. */
2559 gen_logic_cc(s
, src
, opsize
);
2570 opsize
= insn_opsize(insn
);
2571 SRC_EA(env
, src
, opsize
, 1, &addr
);
2573 gen_flush_flags(s
); /* compute old Z */
2575 /* Perform substract with borrow.
2576 * (X, N) = -(src + X);
2579 z
= tcg_const_i32(0);
2580 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, z
, QREG_CC_X
, z
);
2581 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, z
, z
, QREG_CC_N
, QREG_CC_X
);
2583 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
2585 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
2587 /* Compute signed-overflow for negation. The normal formula for
2588 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2589 * this simplies to res & src.
2592 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_N
, src
);
2594 /* Copy the rest of the results into place. */
2595 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
2596 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
2598 set_cc_op(s
, CC_OP_FLAGS
);
2600 /* result is in QREG_CC_N */
2602 DEST_EA(env
, insn
, opsize
, QREG_CC_N
, &addr
);
2610 reg
= AREG(insn
, 9);
2611 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2612 if (IS_NULL_QREG(tmp
)) {
2616 tcg_gen_mov_i32(reg
, tmp
);
2624 zero
= tcg_const_i32(0);
2626 opsize
= insn_opsize(insn
);
2627 DEST_EA(env
, insn
, opsize
, zero
, NULL
);
2628 gen_logic_cc(s
, zero
, opsize
);
2629 tcg_temp_free(zero
);
2632 DISAS_INSN(move_from_ccr
)
2636 ccr
= gen_get_ccr(s
);
2637 DEST_EA(env
, insn
, OS_WORD
, ccr
, NULL
);
2647 opsize
= insn_opsize(insn
);
2648 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2649 dest
= tcg_temp_new();
2650 tcg_gen_neg_i32(dest
, src1
);
2651 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2652 gen_update_cc_add(dest
, src1
, opsize
);
2653 tcg_gen_setcondi_i32(TCG_COND_NE
, QREG_CC_X
, dest
, 0);
2654 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2655 tcg_temp_free(dest
);
2658 DISAS_INSN(move_to_ccr
)
2660 gen_move_to_sr(env
, s
, insn
, true);
2670 opsize
= insn_opsize(insn
);
2671 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2672 dest
= tcg_temp_new();
2673 tcg_gen_not_i32(dest
, src1
);
2674 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2675 gen_logic_cc(s
, dest
, opsize
);
2684 src1
= tcg_temp_new();
2685 src2
= tcg_temp_new();
2686 reg
= DREG(insn
, 0);
2687 tcg_gen_shli_i32(src1
, reg
, 16);
2688 tcg_gen_shri_i32(src2
, reg
, 16);
2689 tcg_gen_or_i32(reg
, src1
, src2
);
2690 tcg_temp_free(src2
);
2691 tcg_temp_free(src1
);
2692 gen_logic_cc(s
, reg
, OS_LONG
);
2697 gen_exception(s
, s
->insn_pc
, EXCP_DEBUG
);
2704 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2705 if (IS_NULL_QREG(tmp
)) {
2718 reg
= DREG(insn
, 0);
2719 op
= (insn
>> 6) & 7;
2720 tmp
= tcg_temp_new();
2722 tcg_gen_ext16s_i32(tmp
, reg
);
2724 tcg_gen_ext8s_i32(tmp
, reg
);
2726 gen_partset_reg(OS_WORD
, reg
, tmp
);
2728 tcg_gen_mov_i32(reg
, tmp
);
2729 gen_logic_cc(s
, tmp
, OS_LONG
);
2738 opsize
= insn_opsize(insn
);
2739 SRC_EA(env
, tmp
, opsize
, 1, NULL
);
2740 gen_logic_cc(s
, tmp
, opsize
);
2745 /* Implemented as a NOP. */
2750 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
2753 /* ??? This should be atomic. */
2760 dest
= tcg_temp_new();
2761 SRC_EA(env
, src1
, OS_BYTE
, 1, &addr
);
2762 gen_logic_cc(s
, src1
, OS_BYTE
);
2763 tcg_gen_ori_i32(dest
, src1
, 0x80);
2764 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
2765 tcg_temp_free(dest
);
2774 ext
= read_im16(env
, s
);
2779 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
2780 gen_exception(s
, s
->insn_pc
, EXCP_UNSUPPORTED
);
2784 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2787 tcg_gen_muls2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2789 tcg_gen_mulu2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2791 /* if Dl == Dh, 68040 returns low word */
2792 tcg_gen_mov_i32(DREG(ext
, 0), QREG_CC_N
);
2793 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_Z
);
2794 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
);
2796 tcg_gen_movi_i32(QREG_CC_V
, 0);
2797 tcg_gen_movi_i32(QREG_CC_C
, 0);
2799 set_cc_op(s
, CC_OP_FLAGS
);
2802 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2803 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
2804 tcg_gen_movi_i32(QREG_CC_C
, 0);
2806 tcg_gen_muls2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2807 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2808 tcg_gen_sari_i32(QREG_CC_Z
, QREG_CC_N
, 31);
2809 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_Z
);
2811 tcg_gen_mulu2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2812 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2813 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_C
);
2815 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
2816 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_N
);
2818 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
2820 set_cc_op(s
, CC_OP_FLAGS
);
2822 /* The upper 32 bits of the product are discarded, so
2823 muls.l and mulu.l are functionally equivalent. */
2824 tcg_gen_mul_i32(DREG(ext
, 12), src1
, DREG(ext
, 12));
2825 gen_logic_cc(s
, DREG(ext
, 12), OS_LONG
);
2829 static void gen_link(DisasContext
*s
, uint16_t insn
, int32_t offset
)
2834 reg
= AREG(insn
, 0);
2835 tmp
= tcg_temp_new();
2836 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
2837 gen_store(s
, OS_LONG
, tmp
, reg
, IS_USER(s
));
2838 if ((insn
& 7) != 7) {
2839 tcg_gen_mov_i32(reg
, tmp
);
2841 tcg_gen_addi_i32(QREG_SP
, tmp
, offset
);
2849 offset
= read_im16(env
, s
);
2850 gen_link(s
, insn
, offset
);
2857 offset
= read_im32(env
, s
);
2858 gen_link(s
, insn
, offset
);
2867 src
= tcg_temp_new();
2868 reg
= AREG(insn
, 0);
2869 tcg_gen_mov_i32(src
, reg
);
2870 tmp
= gen_load(s
, OS_LONG
, src
, 0, IS_USER(s
));
2871 tcg_gen_mov_i32(reg
, tmp
);
2872 tcg_gen_addi_i32(QREG_SP
, src
, 4);
2877 #if defined(CONFIG_SOFTMMU)
2881 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
2885 gen_helper_reset(cpu_env
);
2896 int16_t offset
= read_im16(env
, s
);
2898 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0, IS_USER(s
));
2899 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, offset
+ 4);
2907 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0, IS_USER(s
));
2908 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, 4);
2916 /* Load the target address first to ensure correct exception
2918 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2919 if (IS_NULL_QREG(tmp
)) {
2923 if ((insn
& 0x40) == 0) {
2925 gen_push(s
, tcg_const_i32(s
->pc
));
2939 if ((insn
& 070) == 010) {
2940 /* Operation on address register is always long. */
2943 opsize
= insn_opsize(insn
);
2945 SRC_EA(env
, src
, opsize
, 1, &addr
);
2946 imm
= (insn
>> 9) & 7;
2950 val
= tcg_const_i32(imm
);
2951 dest
= tcg_temp_new();
2952 tcg_gen_mov_i32(dest
, src
);
2953 if ((insn
& 0x38) == 0x08) {
2954 /* Don't update condition codes if the destination is an
2955 address register. */
2956 if (insn
& 0x0100) {
2957 tcg_gen_sub_i32(dest
, dest
, val
);
2959 tcg_gen_add_i32(dest
, dest
, val
);
2962 if (insn
& 0x0100) {
2963 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
2964 tcg_gen_sub_i32(dest
, dest
, val
);
2965 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2967 tcg_gen_add_i32(dest
, dest
, val
);
2968 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
2969 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
2971 gen_update_cc_add(dest
, val
, opsize
);
2974 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2975 tcg_temp_free(dest
);
2981 case 2: /* One extension word. */
2984 case 3: /* Two extension words. */
2987 case 4: /* No extension words. */
2990 disas_undef(env
, s
, insn
);
3002 op
= (insn
>> 8) & 0xf;
3003 offset
= (int8_t)insn
;
3005 offset
= (int16_t)read_im16(env
, s
);
3006 } else if (offset
== -1) {
3007 offset
= read_im32(env
, s
);
3011 gen_push(s
, tcg_const_i32(s
->pc
));
3015 l1
= gen_new_label();
3016 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
3017 gen_jmp_tb(s
, 1, base
+ offset
);
3019 gen_jmp_tb(s
, 0, s
->pc
);
3021 /* Unconditional branch. */
3023 gen_jmp_tb(s
, 0, base
+ offset
);
3029 tcg_gen_movi_i32(DREG(insn
, 9), (int8_t)insn
);
3030 gen_logic_cc(s
, DREG(insn
, 9), OS_LONG
);
3043 SRC_EA(env
, src
, opsize
, (insn
& 0x80) == 0, NULL
);
3044 reg
= DREG(insn
, 9);
3045 tcg_gen_mov_i32(reg
, src
);
3046 gen_logic_cc(s
, src
, opsize
);
3057 opsize
= insn_opsize(insn
);
3058 reg
= gen_extend(DREG(insn
, 9), opsize
, 0);
3059 dest
= tcg_temp_new();
3061 SRC_EA(env
, src
, opsize
, 0, &addr
);
3062 tcg_gen_or_i32(dest
, src
, reg
);
3063 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3065 SRC_EA(env
, src
, opsize
, 0, NULL
);
3066 tcg_gen_or_i32(dest
, src
, reg
);
3067 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
3069 gen_logic_cc(s
, dest
, opsize
);
3070 tcg_temp_free(dest
);
3078 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3079 reg
= AREG(insn
, 9);
3080 tcg_gen_sub_i32(reg
, reg
, src
);
3083 static inline void gen_subx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3087 gen_flush_flags(s
); /* compute old Z */
3089 /* Perform substract with borrow.
3090 * (X, N) = dest - (src + X);
3093 tmp
= tcg_const_i32(0);
3094 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, tmp
, QREG_CC_X
, tmp
);
3095 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, dest
, tmp
, QREG_CC_N
, QREG_CC_X
);
3096 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3097 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
3099 /* Compute signed-overflow for substract. */
3101 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, dest
);
3102 tcg_gen_xor_i32(tmp
, dest
, src
);
3103 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3106 /* Copy the rest of the results into place. */
3107 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3108 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3110 set_cc_op(s
, CC_OP_FLAGS
);
3112 /* result is in QREG_CC_N */
3115 DISAS_INSN(subx_reg
)
3121 opsize
= insn_opsize(insn
);
3123 src
= gen_extend(DREG(insn
, 0), opsize
, 1);
3124 dest
= gen_extend(DREG(insn
, 9), opsize
, 1);
3126 gen_subx(s
, src
, dest
, opsize
);
3128 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3131 DISAS_INSN(subx_mem
)
3139 opsize
= insn_opsize(insn
);
3141 addr_src
= AREG(insn
, 0);
3142 tcg_gen_subi_i32(addr_src
, addr_src
, opsize
);
3143 src
= gen_load(s
, opsize
, addr_src
, 1, IS_USER(s
));
3145 addr_dest
= AREG(insn
, 9);
3146 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize
);
3147 dest
= gen_load(s
, opsize
, addr_dest
, 1, IS_USER(s
));
3149 gen_subx(s
, src
, dest
, opsize
);
3151 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
, IS_USER(s
));
3153 tcg_temp_free(dest
);
3162 val
= (insn
>> 9) & 7;
3165 src
= tcg_const_i32(val
);
3166 gen_logic_cc(s
, src
, OS_LONG
);
3167 DEST_EA(env
, insn
, OS_LONG
, src
, NULL
);
3177 opsize
= insn_opsize(insn
);
3178 SRC_EA(env
, src
, opsize
, 1, NULL
);
3179 reg
= gen_extend(DREG(insn
, 9), opsize
, 1);
3180 gen_update_cc_cmp(s
, reg
, src
, opsize
);
3194 SRC_EA(env
, src
, opsize
, 1, NULL
);
3195 reg
= AREG(insn
, 9);
3196 gen_update_cc_cmp(s
, reg
, src
, OS_LONG
);
3201 int opsize
= insn_opsize(insn
);
3204 /* Post-increment load (mode 3) from Ay. */
3205 src
= gen_ea_mode(env
, s
, 3, REG(insn
, 0), opsize
,
3206 NULL_QREG
, NULL
, EA_LOADS
, IS_USER(s
));
3207 /* Post-increment load (mode 3) from Ax. */
3208 dst
= gen_ea_mode(env
, s
, 3, REG(insn
, 9), opsize
,
3209 NULL_QREG
, NULL
, EA_LOADS
, IS_USER(s
));
3211 gen_update_cc_cmp(s
, dst
, src
, opsize
);
3221 opsize
= insn_opsize(insn
);
3223 SRC_EA(env
, src
, opsize
, 0, &addr
);
3224 dest
= tcg_temp_new();
3225 tcg_gen_xor_i32(dest
, src
, DREG(insn
, 9));
3226 gen_logic_cc(s
, dest
, opsize
);
3227 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3228 tcg_temp_free(dest
);
3231 static void do_exg(TCGv reg1
, TCGv reg2
)
3233 TCGv temp
= tcg_temp_new();
3234 tcg_gen_mov_i32(temp
, reg1
);
3235 tcg_gen_mov_i32(reg1
, reg2
);
3236 tcg_gen_mov_i32(reg2
, temp
);
3237 tcg_temp_free(temp
);
3242 /* exchange Dx and Dy */
3243 do_exg(DREG(insn
, 9), DREG(insn
, 0));
3248 /* exchange Ax and Ay */
3249 do_exg(AREG(insn
, 9), AREG(insn
, 0));
3254 /* exchange Dx and Ay */
3255 do_exg(DREG(insn
, 9), AREG(insn
, 0));
3266 dest
= tcg_temp_new();
3268 opsize
= insn_opsize(insn
);
3269 reg
= DREG(insn
, 9);
3271 SRC_EA(env
, src
, opsize
, 0, &addr
);
3272 tcg_gen_and_i32(dest
, src
, reg
);
3273 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3275 SRC_EA(env
, src
, opsize
, 0, NULL
);
3276 tcg_gen_and_i32(dest
, src
, reg
);
3277 gen_partset_reg(opsize
, reg
, dest
);
3279 gen_logic_cc(s
, dest
, opsize
);
3280 tcg_temp_free(dest
);
3288 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3289 reg
= AREG(insn
, 9);
3290 tcg_gen_add_i32(reg
, reg
, src
);
3293 static inline void gen_addx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3297 gen_flush_flags(s
); /* compute old Z */
3299 /* Perform addition with carry.
3300 * (X, N) = src + dest + X;
3303 tmp
= tcg_const_i32(0);
3304 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_X
, tmp
, dest
, tmp
);
3305 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_N
, QREG_CC_X
, src
, tmp
);
3306 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3308 /* Compute signed-overflow for addition. */
3310 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3311 tcg_gen_xor_i32(tmp
, dest
, src
);
3312 tcg_gen_andc_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3315 /* Copy the rest of the results into place. */
3316 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3317 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3319 set_cc_op(s
, CC_OP_FLAGS
);
3321 /* result is in QREG_CC_N */
3324 DISAS_INSN(addx_reg
)
3330 opsize
= insn_opsize(insn
);
3332 dest
= gen_extend(DREG(insn
, 9), opsize
, 1);
3333 src
= gen_extend(DREG(insn
, 0), opsize
, 1);
3335 gen_addx(s
, src
, dest
, opsize
);
3337 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3340 DISAS_INSN(addx_mem
)
3348 opsize
= insn_opsize(insn
);
3350 addr_src
= AREG(insn
, 0);
3351 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
3352 src
= gen_load(s
, opsize
, addr_src
, 1, IS_USER(s
));
3354 addr_dest
= AREG(insn
, 9);
3355 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
3356 dest
= gen_load(s
, opsize
, addr_dest
, 1, IS_USER(s
));
3358 gen_addx(s
, src
, dest
, opsize
);
3360 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
, IS_USER(s
));
3362 tcg_temp_free(dest
);
3366 static inline void shift_im(DisasContext
*s
, uint16_t insn
, int opsize
)
3368 int count
= (insn
>> 9) & 7;
3369 int logical
= insn
& 8;
3370 int left
= insn
& 0x100;
3371 int bits
= opsize_bytes(opsize
) * 8;
3372 TCGv reg
= gen_extend(DREG(insn
, 0), opsize
, !logical
);
3378 tcg_gen_movi_i32(QREG_CC_V
, 0);
3380 tcg_gen_shri_i32(QREG_CC_C
, reg
, bits
- count
);
3381 tcg_gen_shli_i32(QREG_CC_N
, reg
, count
);
3383 /* Note that ColdFire always clears V (done above),
3384 while M68000 sets if the most significant bit is changed at
3385 any time during the shift operation */
3386 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3387 /* if shift count >= bits, V is (reg != 0) */
3388 if (count
>= bits
) {
3389 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, reg
, QREG_CC_V
);
3391 TCGv t0
= tcg_temp_new();
3392 tcg_gen_sari_i32(QREG_CC_V
, reg
, bits
- 1);
3393 tcg_gen_sari_i32(t0
, reg
, bits
- count
- 1);
3394 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, t0
);
3397 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3400 tcg_gen_shri_i32(QREG_CC_C
, reg
, count
- 1);
3402 tcg_gen_shri_i32(QREG_CC_N
, reg
, count
);
3404 tcg_gen_sari_i32(QREG_CC_N
, reg
, count
);
3408 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3409 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3410 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3411 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3413 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3414 set_cc_op(s
, CC_OP_FLAGS
);
3417 static inline void shift_reg(DisasContext
*s
, uint16_t insn
, int opsize
)
3419 int logical
= insn
& 8;
3420 int left
= insn
& 0x100;
3421 int bits
= opsize_bytes(opsize
) * 8;
3422 TCGv reg
= gen_extend(DREG(insn
, 0), opsize
, !logical
);
3426 t64
= tcg_temp_new_i64();
3427 s64
= tcg_temp_new_i64();
3428 s32
= tcg_temp_new();
3430 /* Note that m68k truncates the shift count modulo 64, not 32.
3431 In addition, a 64-bit shift makes it easy to find "the last
3432 bit shifted out", for the carry flag. */
3433 tcg_gen_andi_i32(s32
, DREG(insn
, 9), 63);
3434 tcg_gen_extu_i32_i64(s64
, s32
);
3435 tcg_gen_extu_i32_i64(t64
, reg
);
3437 /* Optimistically set V=0. Also used as a zero source below. */
3438 tcg_gen_movi_i32(QREG_CC_V
, 0);
3440 tcg_gen_shl_i64(t64
, t64
, s64
);
3442 if (opsize
== OS_LONG
) {
3443 tcg_gen_extr_i64_i32(QREG_CC_N
, QREG_CC_C
, t64
);
3444 /* Note that C=0 if shift count is 0, and we get that for free. */
3446 TCGv zero
= tcg_const_i32(0);
3447 tcg_gen_extrl_i64_i32(QREG_CC_N
, t64
);
3448 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_N
, bits
);
3449 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3450 s32
, zero
, zero
, QREG_CC_C
);
3451 tcg_temp_free(zero
);
3453 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3455 /* X = C, but only if the shift count was non-zero. */
3456 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3457 QREG_CC_C
, QREG_CC_X
);
3459 /* M68000 sets V if the most significant bit is changed at
3460 * any time during the shift operation. Do this via creating
3461 * an extension of the sign bit, comparing, and discarding
3462 * the bits below the sign bit. I.e.
3463 * int64_t s = (intN_t)reg;
3464 * int64_t t = (int64_t)(intN_t)reg << count;
3465 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3467 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3468 TCGv_i64 tt
= tcg_const_i64(32);
3469 /* if shift is greater than 32, use 32 */
3470 tcg_gen_movcond_i64(TCG_COND_GT
, s64
, s64
, tt
, tt
, s64
);
3471 tcg_temp_free_i64(tt
);
3472 /* Sign extend the input to 64 bits; re-do the shift. */
3473 tcg_gen_ext_i32_i64(t64
, reg
);
3474 tcg_gen_shl_i64(s64
, t64
, s64
);
3475 /* Clear all bits that are unchanged. */
3476 tcg_gen_xor_i64(t64
, t64
, s64
);
3477 /* Ignore the bits below the sign bit. */
3478 tcg_gen_andi_i64(t64
, t64
, -1ULL << (bits
- 1));
3479 /* If any bits remain set, we have overflow. */
3480 tcg_gen_setcondi_i64(TCG_COND_NE
, t64
, t64
, 0);
3481 tcg_gen_extrl_i64_i32(QREG_CC_V
, t64
);
3482 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3485 tcg_gen_shli_i64(t64
, t64
, 32);
3487 tcg_gen_shr_i64(t64
, t64
, s64
);
3489 tcg_gen_sar_i64(t64
, t64
, s64
);
3491 tcg_gen_extr_i64_i32(QREG_CC_C
, QREG_CC_N
, t64
);
3493 /* Note that C=0 if shift count is 0, and we get that for free. */
3494 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_C
, 31);
3496 /* X = C, but only if the shift count was non-zero. */
3497 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3498 QREG_CC_C
, QREG_CC_X
);
3500 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3501 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3504 tcg_temp_free_i64(s64
);
3505 tcg_temp_free_i64(t64
);
3507 /* Write back the result. */
3508 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3509 set_cc_op(s
, CC_OP_FLAGS
);
3512 DISAS_INSN(shift8_im
)
3514 shift_im(s
, insn
, OS_BYTE
);
3517 DISAS_INSN(shift16_im
)
3519 shift_im(s
, insn
, OS_WORD
);
3522 DISAS_INSN(shift_im
)
3524 shift_im(s
, insn
, OS_LONG
);
3527 DISAS_INSN(shift8_reg
)
3529 shift_reg(s
, insn
, OS_BYTE
);
3532 DISAS_INSN(shift16_reg
)
3534 shift_reg(s
, insn
, OS_WORD
);
3537 DISAS_INSN(shift_reg
)
3539 shift_reg(s
, insn
, OS_LONG
);
3542 DISAS_INSN(shift_mem
)
3544 int logical
= insn
& 8;
3545 int left
= insn
& 0x100;
3549 SRC_EA(env
, src
, OS_WORD
, !logical
, &addr
);
3550 tcg_gen_movi_i32(QREG_CC_V
, 0);
3552 tcg_gen_shri_i32(QREG_CC_C
, src
, 15);
3553 tcg_gen_shli_i32(QREG_CC_N
, src
, 1);
3555 /* Note that ColdFire always clears V,
3556 while M68000 sets if the most significant bit is changed at
3557 any time during the shift operation */
3558 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3559 src
= gen_extend(src
, OS_WORD
, 1);
3560 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3563 tcg_gen_mov_i32(QREG_CC_C
, src
);
3565 tcg_gen_shri_i32(QREG_CC_N
, src
, 1);
3567 tcg_gen_sari_i32(QREG_CC_N
, src
, 1);
3571 gen_ext(QREG_CC_N
, QREG_CC_N
, OS_WORD
, 1);
3572 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3573 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3574 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3576 DEST_EA(env
, insn
, OS_WORD
, QREG_CC_N
, &addr
);
3577 set_cc_op(s
, CC_OP_FLAGS
);
3580 static void rotate(TCGv reg
, TCGv shift
, int left
, int size
)
3584 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3585 tcg_gen_ext8u_i32(reg
, reg
);
3586 tcg_gen_muli_i32(reg
, reg
, 0x01010101);
3589 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3590 tcg_gen_deposit_i32(reg
, reg
, reg
, 16, 16);
3595 tcg_gen_rotl_i32(reg
, reg
, shift
);
3597 tcg_gen_rotr_i32(reg
, reg
, shift
);
3605 tcg_gen_ext8s_i32(reg
, reg
);
3608 tcg_gen_ext16s_i32(reg
, reg
);
3614 /* QREG_CC_X is not affected */
3616 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3617 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3620 tcg_gen_andi_i32(QREG_CC_C
, reg
, 1);
3622 tcg_gen_shri_i32(QREG_CC_C
, reg
, 31);
3625 tcg_gen_movi_i32(QREG_CC_V
, 0); /* always cleared */
3628 static void rotate_x_flags(TCGv reg
, TCGv X
, int size
)
3632 tcg_gen_ext8s_i32(reg
, reg
);
3635 tcg_gen_ext16s_i32(reg
, reg
);
3640 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3641 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3642 tcg_gen_mov_i32(QREG_CC_X
, X
);
3643 tcg_gen_mov_i32(QREG_CC_C
, X
);
3644 tcg_gen_movi_i32(QREG_CC_V
, 0);
3647 /* Result of rotate_x() is valid if 0 <= shift <= size */
3648 static TCGv
rotate_x(TCGv reg
, TCGv shift
, int left
, int size
)
3650 TCGv X
, shl
, shr
, shx
, sz
, zero
;
3652 sz
= tcg_const_i32(size
);
3654 shr
= tcg_temp_new();
3655 shl
= tcg_temp_new();
3656 shx
= tcg_temp_new();
3658 tcg_gen_mov_i32(shl
, shift
); /* shl = shift */
3659 tcg_gen_movi_i32(shr
, size
+ 1);
3660 tcg_gen_sub_i32(shr
, shr
, shift
); /* shr = size + 1 - shift */
3661 tcg_gen_subi_i32(shx
, shift
, 1); /* shx = shift - 1 */
3662 /* shx = shx < 0 ? size : shx; */
3663 zero
= tcg_const_i32(0);
3664 tcg_gen_movcond_i32(TCG_COND_LT
, shx
, shx
, zero
, sz
, shx
);
3665 tcg_temp_free(zero
);
3667 tcg_gen_mov_i32(shr
, shift
); /* shr = shift */
3668 tcg_gen_movi_i32(shl
, size
+ 1);
3669 tcg_gen_sub_i32(shl
, shl
, shift
); /* shl = size + 1 - shift */
3670 tcg_gen_sub_i32(shx
, sz
, shift
); /* shx = size - shift */
3673 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3675 tcg_gen_shl_i32(shl
, reg
, shl
);
3676 tcg_gen_shr_i32(shr
, reg
, shr
);
3677 tcg_gen_or_i32(reg
, shl
, shr
);
3680 tcg_gen_shl_i32(shx
, QREG_CC_X
, shx
);
3681 tcg_gen_or_i32(reg
, reg
, shx
);
3684 /* X = (reg >> size) & 1 */
3687 tcg_gen_shr_i32(X
, reg
, sz
);
3688 tcg_gen_andi_i32(X
, X
, 1);
3694 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3695 static TCGv
rotate32_x(TCGv reg
, TCGv shift
, int left
)
3697 TCGv_i64 t0
, shift64
;
3698 TCGv X
, lo
, hi
, zero
;
3700 shift64
= tcg_temp_new_i64();
3701 tcg_gen_extu_i32_i64(shift64
, shift
);
3703 t0
= tcg_temp_new_i64();
3706 lo
= tcg_temp_new();
3707 hi
= tcg_temp_new();
3710 /* create [reg:X:..] */
3712 tcg_gen_shli_i32(lo
, QREG_CC_X
, 31);
3713 tcg_gen_concat_i32_i64(t0
, lo
, reg
);
3717 tcg_gen_rotl_i64(t0
, t0
, shift64
);
3718 tcg_temp_free_i64(shift64
);
3720 /* result is [reg:..:reg:X] */
3722 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3723 tcg_gen_andi_i32(X
, lo
, 1);
3725 tcg_gen_shri_i32(lo
, lo
, 1);
3727 /* create [..:X:reg] */
3729 tcg_gen_concat_i32_i64(t0
, reg
, QREG_CC_X
);
3731 tcg_gen_rotr_i64(t0
, t0
, shift64
);
3732 tcg_temp_free_i64(shift64
);
3734 /* result is value: [X:reg:..:reg] */
3736 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3740 tcg_gen_shri_i32(X
, hi
, 31);
3742 /* extract result */
3744 tcg_gen_shli_i32(hi
, hi
, 1);
3746 tcg_temp_free_i64(t0
);
3747 tcg_gen_or_i32(lo
, lo
, hi
);
3750 /* if shift == 0, register and X are not affected */
3752 zero
= tcg_const_i32(0);
3753 tcg_gen_movcond_i32(TCG_COND_EQ
, X
, shift
, zero
, QREG_CC_X
, X
);
3754 tcg_gen_movcond_i32(TCG_COND_EQ
, reg
, shift
, zero
, reg
, lo
);
3755 tcg_temp_free(zero
);
3761 DISAS_INSN(rotate_im
)
3765 int left
= (insn
& 0x100);
3767 tmp
= (insn
>> 9) & 7;
3772 shift
= tcg_const_i32(tmp
);
3774 rotate(DREG(insn
, 0), shift
, left
, 32);
3776 TCGv X
= rotate32_x(DREG(insn
, 0), shift
, left
);
3777 rotate_x_flags(DREG(insn
, 0), X
, 32);
3780 tcg_temp_free(shift
);
3782 set_cc_op(s
, CC_OP_FLAGS
);
3785 DISAS_INSN(rotate8_im
)
3787 int left
= (insn
& 0x100);
3792 reg
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
3794 tmp
= (insn
>> 9) & 7;
3799 shift
= tcg_const_i32(tmp
);
3801 rotate(reg
, shift
, left
, 8);
3803 TCGv X
= rotate_x(reg
, shift
, left
, 8);
3804 rotate_x_flags(reg
, X
, 8);
3807 tcg_temp_free(shift
);
3808 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
3809 set_cc_op(s
, CC_OP_FLAGS
);
3812 DISAS_INSN(rotate16_im
)
3814 int left
= (insn
& 0x100);
3819 reg
= gen_extend(DREG(insn
, 0), OS_WORD
, 0);
3820 tmp
= (insn
>> 9) & 7;
3825 shift
= tcg_const_i32(tmp
);
3827 rotate(reg
, shift
, left
, 16);
3829 TCGv X
= rotate_x(reg
, shift
, left
, 16);
3830 rotate_x_flags(reg
, X
, 16);
3833 tcg_temp_free(shift
);
3834 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
3835 set_cc_op(s
, CC_OP_FLAGS
);
3838 DISAS_INSN(rotate_reg
)
3843 int left
= (insn
& 0x100);
3845 reg
= DREG(insn
, 0);
3846 src
= DREG(insn
, 9);
3847 /* shift in [0..63] */
3848 t0
= tcg_temp_new();
3849 tcg_gen_andi_i32(t0
, src
, 63);
3850 t1
= tcg_temp_new_i32();
3852 tcg_gen_andi_i32(t1
, src
, 31);
3853 rotate(reg
, t1
, left
, 32);
3854 /* if shift == 0, clear C */
3855 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3856 t0
, QREG_CC_V
/* 0 */,
3857 QREG_CC_V
/* 0 */, QREG_CC_C
);
3861 tcg_gen_movi_i32(t1
, 33);
3862 tcg_gen_remu_i32(t1
, t0
, t1
);
3863 X
= rotate32_x(DREG(insn
, 0), t1
, left
);
3864 rotate_x_flags(DREG(insn
, 0), X
, 32);
3869 set_cc_op(s
, CC_OP_FLAGS
);
3872 DISAS_INSN(rotate8_reg
)
3877 int left
= (insn
& 0x100);
3879 reg
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
3880 src
= DREG(insn
, 9);
3881 /* shift in [0..63] */
3882 t0
= tcg_temp_new_i32();
3883 tcg_gen_andi_i32(t0
, src
, 63);
3884 t1
= tcg_temp_new_i32();
3886 tcg_gen_andi_i32(t1
, src
, 7);
3887 rotate(reg
, t1
, left
, 8);
3888 /* if shift == 0, clear C */
3889 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3890 t0
, QREG_CC_V
/* 0 */,
3891 QREG_CC_V
/* 0 */, QREG_CC_C
);
3895 tcg_gen_movi_i32(t1
, 9);
3896 tcg_gen_remu_i32(t1
, t0
, t1
);
3897 X
= rotate_x(reg
, t1
, left
, 8);
3898 rotate_x_flags(reg
, X
, 8);
3903 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
3904 set_cc_op(s
, CC_OP_FLAGS
);
3907 DISAS_INSN(rotate16_reg
)
3912 int left
= (insn
& 0x100);
3914 reg
= gen_extend(DREG(insn
, 0), OS_WORD
, 0);
3915 src
= DREG(insn
, 9);
3916 /* shift in [0..63] */
3917 t0
= tcg_temp_new_i32();
3918 tcg_gen_andi_i32(t0
, src
, 63);
3919 t1
= tcg_temp_new_i32();
3921 tcg_gen_andi_i32(t1
, src
, 15);
3922 rotate(reg
, t1
, left
, 16);
3923 /* if shift == 0, clear C */
3924 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3925 t0
, QREG_CC_V
/* 0 */,
3926 QREG_CC_V
/* 0 */, QREG_CC_C
);
3930 tcg_gen_movi_i32(t1
, 17);
3931 tcg_gen_remu_i32(t1
, t0
, t1
);
3932 X
= rotate_x(reg
, t1
, left
, 16);
3933 rotate_x_flags(reg
, X
, 16);
3938 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
3939 set_cc_op(s
, CC_OP_FLAGS
);
3942 DISAS_INSN(rotate_mem
)
3947 int left
= (insn
& 0x100);
3949 SRC_EA(env
, src
, OS_WORD
, 0, &addr
);
3951 shift
= tcg_const_i32(1);
3952 if (insn
& 0x0200) {
3953 rotate(src
, shift
, left
, 16);
3955 TCGv X
= rotate_x(src
, shift
, left
, 16);
3956 rotate_x_flags(src
, X
, 16);
3959 tcg_temp_free(shift
);
3960 DEST_EA(env
, insn
, OS_WORD
, src
, &addr
);
3961 set_cc_op(s
, CC_OP_FLAGS
);
3964 DISAS_INSN(bfext_reg
)
3966 int ext
= read_im16(env
, s
);
3967 int is_sign
= insn
& 0x200;
3968 TCGv src
= DREG(insn
, 0);
3969 TCGv dst
= DREG(ext
, 12);
3970 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
3971 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
3972 int pos
= 32 - ofs
- len
; /* little bit-endian */
3973 TCGv tmp
= tcg_temp_new();
3976 /* In general, we're going to rotate the field so that it's at the
3977 top of the word and then right-shift by the compliment of the
3978 width to extend the field. */
3980 /* Variable width. */
3982 /* Variable offset. */
3983 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
3984 tcg_gen_rotl_i32(tmp
, src
, tmp
);
3986 tcg_gen_rotli_i32(tmp
, src
, ofs
);
3989 shift
= tcg_temp_new();
3990 tcg_gen_neg_i32(shift
, DREG(ext
, 0));
3991 tcg_gen_andi_i32(shift
, shift
, 31);
3992 tcg_gen_sar_i32(QREG_CC_N
, tmp
, shift
);
3994 tcg_gen_mov_i32(dst
, QREG_CC_N
);
3996 tcg_gen_shr_i32(dst
, tmp
, shift
);
3998 tcg_temp_free(shift
);
4000 /* Immediate width. */
4002 /* Variable offset */
4003 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4004 tcg_gen_rotl_i32(tmp
, src
, tmp
);
4008 /* Immediate offset. If the field doesn't wrap around the
4009 end of the word, rely on (s)extract completely. */
4011 tcg_gen_rotli_i32(tmp
, src
, ofs
);
4017 tcg_gen_sextract_i32(QREG_CC_N
, src
, pos
, len
);
4019 tcg_gen_mov_i32(dst
, QREG_CC_N
);
4021 tcg_gen_extract_i32(dst
, src
, pos
, len
);
4026 set_cc_op(s
, CC_OP_LOGIC
);
4029 DISAS_INSN(bfext_mem
)
4031 int ext
= read_im16(env
, s
);
4032 int is_sign
= insn
& 0x200;
4033 TCGv dest
= DREG(ext
, 12);
4034 TCGv addr
, len
, ofs
;
4036 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4037 if (IS_NULL_QREG(addr
)) {
4045 len
= tcg_const_i32(extract32(ext
, 0, 5));
4050 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4054 gen_helper_bfexts_mem(dest
, cpu_env
, addr
, ofs
, len
);
4055 tcg_gen_mov_i32(QREG_CC_N
, dest
);
4057 TCGv_i64 tmp
= tcg_temp_new_i64();
4058 gen_helper_bfextu_mem(tmp
, cpu_env
, addr
, ofs
, len
);
4059 tcg_gen_extr_i64_i32(dest
, QREG_CC_N
, tmp
);
4060 tcg_temp_free_i64(tmp
);
4062 set_cc_op(s
, CC_OP_LOGIC
);
4064 if (!(ext
& 0x20)) {
4067 if (!(ext
& 0x800)) {
4072 DISAS_INSN(bfop_reg
)
4074 int ext
= read_im16(env
, s
);
4075 TCGv src
= DREG(insn
, 0);
4076 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4077 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4078 TCGv mask
, tofs
, tlen
;
4082 if ((insn
& 0x0f00) == 0x0d00) { /* bfffo */
4083 tofs
= tcg_temp_new();
4084 tlen
= tcg_temp_new();
4087 if ((ext
& 0x820) == 0) {
4088 /* Immediate width and offset. */
4089 uint32_t maski
= 0x7fffffffu
>> (len
- 1);
4090 if (ofs
+ len
<= 32) {
4091 tcg_gen_shli_i32(QREG_CC_N
, src
, ofs
);
4093 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4095 tcg_gen_andi_i32(QREG_CC_N
, QREG_CC_N
, ~maski
);
4096 mask
= tcg_const_i32(ror32(maski
, ofs
));
4098 tcg_gen_movi_i32(tofs
, ofs
);
4099 tcg_gen_movi_i32(tlen
, len
);
4102 TCGv tmp
= tcg_temp_new();
4104 /* Variable width */
4105 tcg_gen_subi_i32(tmp
, DREG(ext
, 0), 1);
4106 tcg_gen_andi_i32(tmp
, tmp
, 31);
4107 mask
= tcg_const_i32(0x7fffffffu
);
4108 tcg_gen_shr_i32(mask
, mask
, tmp
);
4110 tcg_gen_addi_i32(tlen
, tmp
, 1);
4113 /* Immediate width */
4114 mask
= tcg_const_i32(0x7fffffffu
>> (len
- 1));
4116 tcg_gen_movi_i32(tlen
, len
);
4120 /* Variable offset */
4121 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4122 tcg_gen_rotl_i32(QREG_CC_N
, src
, tmp
);
4123 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4124 tcg_gen_rotr_i32(mask
, mask
, tmp
);
4126 tcg_gen_mov_i32(tofs
, tmp
);
4129 /* Immediate offset (and variable width) */
4130 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4131 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4132 tcg_gen_rotri_i32(mask
, mask
, ofs
);
4134 tcg_gen_movi_i32(tofs
, ofs
);
4139 set_cc_op(s
, CC_OP_LOGIC
);
4141 switch (insn
& 0x0f00) {
4142 case 0x0a00: /* bfchg */
4143 tcg_gen_eqv_i32(src
, src
, mask
);
4145 case 0x0c00: /* bfclr */
4146 tcg_gen_and_i32(src
, src
, mask
);
4148 case 0x0d00: /* bfffo */
4149 gen_helper_bfffo_reg(DREG(ext
, 12), QREG_CC_N
, tofs
, tlen
);
4150 tcg_temp_free(tlen
);
4151 tcg_temp_free(tofs
);
4153 case 0x0e00: /* bfset */
4154 tcg_gen_orc_i32(src
, src
, mask
);
4156 case 0x0800: /* bftst */
4157 /* flags already set; no other work to do. */
4160 g_assert_not_reached();
4162 tcg_temp_free(mask
);
4165 DISAS_INSN(bfop_mem
)
4167 int ext
= read_im16(env
, s
);
4168 TCGv addr
, len
, ofs
;
4171 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4172 if (IS_NULL_QREG(addr
)) {
4180 len
= tcg_const_i32(extract32(ext
, 0, 5));
4185 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4188 switch (insn
& 0x0f00) {
4189 case 0x0a00: /* bfchg */
4190 gen_helper_bfchg_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4192 case 0x0c00: /* bfclr */
4193 gen_helper_bfclr_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4195 case 0x0d00: /* bfffo */
4196 t64
= tcg_temp_new_i64();
4197 gen_helper_bfffo_mem(t64
, cpu_env
, addr
, ofs
, len
);
4198 tcg_gen_extr_i64_i32(DREG(ext
, 12), QREG_CC_N
, t64
);
4199 tcg_temp_free_i64(t64
);
4201 case 0x0e00: /* bfset */
4202 gen_helper_bfset_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4204 case 0x0800: /* bftst */
4205 gen_helper_bfexts_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4208 g_assert_not_reached();
4210 set_cc_op(s
, CC_OP_LOGIC
);
4212 if (!(ext
& 0x20)) {
4215 if (!(ext
& 0x800)) {
4220 DISAS_INSN(bfins_reg
)
4222 int ext
= read_im16(env
, s
);
4223 TCGv dst
= DREG(insn
, 0);
4224 TCGv src
= DREG(ext
, 12);
4225 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4226 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4227 int pos
= 32 - ofs
- len
; /* little bit-endian */
4230 tmp
= tcg_temp_new();
4233 /* Variable width */
4234 tcg_gen_neg_i32(tmp
, DREG(ext
, 0));
4235 tcg_gen_andi_i32(tmp
, tmp
, 31);
4236 tcg_gen_shl_i32(QREG_CC_N
, src
, tmp
);
4238 /* Immediate width */
4239 tcg_gen_shli_i32(QREG_CC_N
, src
, 32 - len
);
4241 set_cc_op(s
, CC_OP_LOGIC
);
4243 /* Immediate width and offset */
4244 if ((ext
& 0x820) == 0) {
4245 /* Check for suitability for deposit. */
4247 tcg_gen_deposit_i32(dst
, dst
, src
, pos
, len
);
4249 uint32_t maski
= -2U << (len
- 1);
4250 uint32_t roti
= (ofs
+ len
) & 31;
4251 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4252 tcg_gen_rotri_i32(tmp
, tmp
, roti
);
4253 tcg_gen_andi_i32(dst
, dst
, ror32(maski
, roti
));
4254 tcg_gen_or_i32(dst
, dst
, tmp
);
4257 TCGv mask
= tcg_temp_new();
4258 TCGv rot
= tcg_temp_new();
4261 /* Variable width */
4262 tcg_gen_subi_i32(rot
, DREG(ext
, 0), 1);
4263 tcg_gen_andi_i32(rot
, rot
, 31);
4264 tcg_gen_movi_i32(mask
, -2);
4265 tcg_gen_shl_i32(mask
, mask
, rot
);
4266 tcg_gen_mov_i32(rot
, DREG(ext
, 0));
4267 tcg_gen_andc_i32(tmp
, src
, mask
);
4269 /* Immediate width (variable offset) */
4270 uint32_t maski
= -2U << (len
- 1);
4271 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4272 tcg_gen_movi_i32(mask
, maski
);
4273 tcg_gen_movi_i32(rot
, len
& 31);
4276 /* Variable offset */
4277 tcg_gen_add_i32(rot
, rot
, DREG(ext
, 6));
4279 /* Immediate offset (variable width) */
4280 tcg_gen_addi_i32(rot
, rot
, ofs
);
4282 tcg_gen_andi_i32(rot
, rot
, 31);
4283 tcg_gen_rotr_i32(mask
, mask
, rot
);
4284 tcg_gen_rotr_i32(tmp
, tmp
, rot
);
4285 tcg_gen_and_i32(dst
, dst
, mask
);
4286 tcg_gen_or_i32(dst
, dst
, tmp
);
4289 tcg_temp_free(mask
);
4294 DISAS_INSN(bfins_mem
)
4296 int ext
= read_im16(env
, s
);
4297 TCGv src
= DREG(ext
, 12);
4298 TCGv addr
, len
, ofs
;
4300 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4301 if (IS_NULL_QREG(addr
)) {
4309 len
= tcg_const_i32(extract32(ext
, 0, 5));
4314 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4317 gen_helper_bfins_mem(QREG_CC_N
, cpu_env
, addr
, src
, ofs
, len
);
4318 set_cc_op(s
, CC_OP_LOGIC
);
4320 if (!(ext
& 0x20)) {
4323 if (!(ext
& 0x800)) {
4331 reg
= DREG(insn
, 0);
4332 gen_logic_cc(s
, reg
, OS_LONG
);
4333 gen_helper_ff1(reg
, reg
);
4341 switch ((insn
>> 7) & 3) {
4346 if (m68k_feature(env
, M68K_FEATURE_CHK2
)) {
4352 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4355 SRC_EA(env
, src
, opsize
, 1, NULL
);
4356 reg
= gen_extend(DREG(insn
, 9), opsize
, 1);
4359 gen_helper_chk(cpu_env
, reg
, src
);
4365 TCGv addr1
, addr2
, bound1
, bound2
, reg
;
4368 switch ((insn
>> 9) & 3) {
4379 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4383 ext
= read_im16(env
, s
);
4384 if ((ext
& 0x0800) == 0) {
4385 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4389 addr1
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4390 addr2
= tcg_temp_new();
4391 tcg_gen_addi_i32(addr2
, addr1
, opsize_bytes(opsize
));
4393 bound1
= gen_load(s
, opsize
, addr1
, 1, IS_USER(s
));
4394 tcg_temp_free(addr1
);
4395 bound2
= gen_load(s
, opsize
, addr2
, 1, IS_USER(s
));
4396 tcg_temp_free(addr2
);
4398 reg
= tcg_temp_new();
4400 tcg_gen_mov_i32(reg
, AREG(ext
, 12));
4402 gen_ext(reg
, DREG(ext
, 12), opsize
, 1);
4406 gen_helper_chk2(cpu_env
, reg
, bound1
, bound2
);
4408 tcg_temp_free(bound1
);
4409 tcg_temp_free(bound2
);
4412 static void m68k_copy_line(TCGv dst
, TCGv src
, int index
)
4417 addr
= tcg_temp_new();
4419 t0
= tcg_temp_new_i64();
4420 t1
= tcg_temp_new_i64();
4422 tcg_gen_andi_i32(addr
, src
, ~15);
4423 tcg_gen_qemu_ld64(t0
, addr
, index
);
4424 tcg_gen_addi_i32(addr
, addr
, 8);
4425 tcg_gen_qemu_ld64(t1
, addr
, index
);
4427 tcg_gen_andi_i32(addr
, dst
, ~15);
4428 tcg_gen_qemu_st64(t0
, addr
, index
);
4429 tcg_gen_addi_i32(addr
, addr
, 8);
4430 tcg_gen_qemu_st64(t1
, addr
, index
);
4432 tcg_temp_free_i64(t0
);
4433 tcg_temp_free_i64(t1
);
4434 tcg_temp_free(addr
);
4437 DISAS_INSN(move16_reg
)
4439 int index
= IS_USER(s
);
4443 ext
= read_im16(env
, s
);
4444 if ((ext
& (1 << 15)) == 0) {
4445 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4448 m68k_copy_line(AREG(ext
, 12), AREG(insn
, 0), index
);
4450 /* Ax can be Ay, so save Ay before incrementing Ax */
4451 tmp
= tcg_temp_new();
4452 tcg_gen_mov_i32(tmp
, AREG(ext
, 12));
4453 tcg_gen_addi_i32(AREG(insn
, 0), AREG(insn
, 0), 16);
4454 tcg_gen_addi_i32(AREG(ext
, 12), tmp
, 16);
4458 DISAS_INSN(move16_mem
)
4460 int index
= IS_USER(s
);
4463 reg
= AREG(insn
, 0);
4464 addr
= tcg_const_i32(read_im32(env
, s
));
4466 if ((insn
>> 3) & 1) {
4467 /* MOVE16 (xxx).L, (Ay) */
4468 m68k_copy_line(reg
, addr
, index
);
4470 /* MOVE16 (Ay), (xxx).L */
4471 m68k_copy_line(addr
, reg
, index
);
4474 tcg_temp_free(addr
);
4476 if (((insn
>> 3) & 2) == 0) {
4478 tcg_gen_addi_i32(reg
, reg
, 16);
4488 ext
= read_im16(env
, s
);
4489 if (ext
!= 0x46FC) {
4490 gen_exception(s
, addr
, EXCP_UNSUPPORTED
);
4493 ext
= read_im16(env
, s
);
4494 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
4495 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
4498 gen_push(s
, gen_get_sr(s
));
4499 gen_set_sr_im(s
, ext
, 0);
4502 DISAS_INSN(move_from_sr
)
4506 if (IS_USER(s
) && !m68k_feature(env
, M68K_FEATURE_M68000
)) {
4507 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4511 DEST_EA(env
, insn
, OS_WORD
, sr
, NULL
);
4514 #if defined(CONFIG_SOFTMMU)
4524 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4528 ext
= read_im16(env
, s
);
4530 opsize
= insn_opsize(insn
);
4533 /* address register */
4534 reg
= AREG(ext
, 12);
4538 reg
= DREG(ext
, 12);
4542 addr
= gen_lea(env
, s
, insn
, opsize
);
4543 if (IS_NULL_QREG(addr
)) {
4549 /* from reg to ea */
4550 gen_store(s
, opsize
, addr
, reg
, DFC_INDEX(s
));
4552 /* from ea to reg */
4553 TCGv tmp
= gen_load(s
, opsize
, addr
, 0, SFC_INDEX(s
));
4555 gen_ext(reg
, tmp
, opsize
, 1);
4557 gen_partset_reg(opsize
, reg
, tmp
);
4561 switch (extract32(insn
, 3, 3)) {
4562 case 3: /* Indirect postincrement. */
4563 tcg_gen_addi_i32(AREG(insn
, 0), addr
,
4564 REG(insn
, 0) == 7 && opsize
== OS_BYTE
4566 : opsize_bytes(opsize
));
4568 case 4: /* Indirect predecrememnt. */
4569 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4574 DISAS_INSN(move_to_sr
)
4577 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4580 gen_move_to_sr(env
, s
, insn
, false);
4584 DISAS_INSN(move_from_usp
)
4587 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4590 tcg_gen_ld_i32(AREG(insn
, 0), cpu_env
,
4591 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4594 DISAS_INSN(move_to_usp
)
4597 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4600 tcg_gen_st_i32(AREG(insn
, 0), cpu_env
,
4601 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4607 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4611 gen_exception(s
, s
->pc
, EXCP_HALT_INSN
);
4619 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4623 ext
= read_im16(env
, s
);
4625 gen_set_sr_im(s
, ext
, 0);
4626 tcg_gen_movi_i32(cpu_halted
, 1);
4627 gen_exception(s
, s
->pc
, EXCP_HLT
);
4633 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4636 gen_exception(s
, s
->insn_pc
, EXCP_RTE
);
4639 DISAS_INSN(cf_movec
)
4645 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4649 ext
= read_im16(env
, s
);
4652 reg
= AREG(ext
, 12);
4654 reg
= DREG(ext
, 12);
4656 gen_helper_cf_movec_to(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4660 DISAS_INSN(m68k_movec
)
4666 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4670 ext
= read_im16(env
, s
);
4673 reg
= AREG(ext
, 12);
4675 reg
= DREG(ext
, 12);
4678 gen_helper_m68k_movec_to(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4680 gen_helper_m68k_movec_from(reg
, cpu_env
, tcg_const_i32(ext
& 0xfff));
4688 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4691 /* ICache fetch. Implement as no-op. */
4697 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4700 /* Cache push/invalidate. Implement as no-op. */
4706 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4709 /* Cache push/invalidate. Implement as no-op. */
4715 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4718 /* Invalidate cache line. Implement as no-op. */
4721 #if defined(CONFIG_SOFTMMU)
4727 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4731 opmode
= tcg_const_i32((insn
>> 3) & 3);
4732 gen_helper_pflush(cpu_env
, AREG(insn
, 0), opmode
);
4733 tcg_temp_free(opmode
);
4741 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4744 is_read
= tcg_const_i32((insn
>> 5) & 1);
4745 gen_helper_ptest(cpu_env
, AREG(insn
, 0), is_read
);
4746 tcg_temp_free(is_read
);
4752 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4757 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
4760 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4763 /* TODO: Implement wdebug. */
4764 cpu_abort(CPU(cpu
), "WDEBUG not implemented");
4770 gen_exception(s
, s
->insn_pc
, EXCP_TRAP0
+ (insn
& 0xf));
4773 static void gen_load_fcr(DisasContext
*s
, TCGv res
, int reg
)
4777 tcg_gen_movi_i32(res
, 0);
4780 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4783 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpcr
));
4788 static void gen_store_fcr(DisasContext
*s
, TCGv val
, int reg
)
4794 tcg_gen_st_i32(val
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4797 gen_helper_set_fpcr(cpu_env
, val
);
4802 static void gen_qemu_store_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4804 int index
= IS_USER(s
);
4807 tmp
= tcg_temp_new();
4808 gen_load_fcr(s
, tmp
, reg
);
4809 tcg_gen_qemu_st32(tmp
, addr
, index
);
4813 static void gen_qemu_load_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4815 int index
= IS_USER(s
);
4818 tmp
= tcg_temp_new();
4819 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
4820 gen_store_fcr(s
, tmp
, reg
);
4825 static void gen_op_fmove_fcr(CPUM68KState
*env
, DisasContext
*s
,
4826 uint32_t insn
, uint32_t ext
)
4828 int mask
= (ext
>> 10) & 7;
4829 int is_write
= (ext
>> 13) & 1;
4830 int mode
= extract32(insn
, 3, 3);
4836 if (mask
!= M68K_FPIAR
&& mask
!= M68K_FPSR
&& mask
!= M68K_FPCR
) {
4837 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4841 gen_load_fcr(s
, DREG(insn
, 0), mask
);
4843 gen_store_fcr(s
, DREG(insn
, 0), mask
);
4846 case 1: /* An, only with FPIAR */
4847 if (mask
!= M68K_FPIAR
) {
4848 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4852 gen_load_fcr(s
, AREG(insn
, 0), mask
);
4854 gen_store_fcr(s
, AREG(insn
, 0), mask
);
4861 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
4862 if (IS_NULL_QREG(tmp
)) {
4867 addr
= tcg_temp_new();
4868 tcg_gen_mov_i32(addr
, tmp
);
4872 * 0b100 Floating-Point Control Register
4873 * 0b010 Floating-Point Status Register
4874 * 0b001 Floating-Point Instruction Address Register
4878 if (is_write
&& mode
== 4) {
4879 for (i
= 2; i
>= 0; i
--, mask
>>= 1) {
4881 gen_qemu_store_fcr(s
, addr
, 1 << i
);
4883 tcg_gen_subi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
4887 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4889 for (i
= 0; i
< 3; i
++, mask
>>= 1) {
4892 gen_qemu_store_fcr(s
, addr
, 1 << i
);
4894 gen_qemu_load_fcr(s
, addr
, 1 << i
);
4896 if (mask
!= 1 || mode
== 3) {
4897 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
4902 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4905 tcg_temp_free_i32(addr
);
4908 static void gen_op_fmovem(CPUM68KState
*env
, DisasContext
*s
,
4909 uint32_t insn
, uint32_t ext
)
4913 int mode
= (ext
>> 11) & 0x3;
4914 int is_load
= ((ext
& 0x2000) == 0);
4916 if (m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
4917 opsize
= OS_EXTENDED
;
4919 opsize
= OS_DOUBLE
; /* FIXME */
4922 addr
= gen_lea(env
, s
, insn
, opsize
);
4923 if (IS_NULL_QREG(addr
)) {
4928 tmp
= tcg_temp_new();
4930 /* Dynamic register list */
4931 tcg_gen_ext8u_i32(tmp
, DREG(ext
, 4));
4933 /* Static register list */
4934 tcg_gen_movi_i32(tmp
, ext
& 0xff);
4937 if (!is_load
&& (mode
& 2) == 0) {
4938 /* predecrement addressing mode
4939 * only available to store register to memory
4941 if (opsize
== OS_EXTENDED
) {
4942 gen_helper_fmovemx_st_predec(tmp
, cpu_env
, addr
, tmp
);
4944 gen_helper_fmovemd_st_predec(tmp
, cpu_env
, addr
, tmp
);
4947 /* postincrement addressing mode */
4948 if (opsize
== OS_EXTENDED
) {
4950 gen_helper_fmovemx_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
4952 gen_helper_fmovemx_st_postinc(tmp
, cpu_env
, addr
, tmp
);
4956 gen_helper_fmovemd_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
4958 gen_helper_fmovemd_st_postinc(tmp
, cpu_env
, addr
, tmp
);
4962 if ((insn
& 070) == 030 || (insn
& 070) == 040) {
4963 tcg_gen_mov_i32(AREG(insn
, 0), tmp
);
4968 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
4969 immediately before the next FP instruction is executed. */
4975 TCGv_ptr cpu_src
, cpu_dest
;
4977 ext
= read_im16(env
, s
);
4978 opmode
= ext
& 0x7f;
4979 switch ((ext
>> 13) & 7) {
4985 if (insn
== 0xf200 && (ext
& 0xfc00) == 0x5c00) {
4987 TCGv rom_offset
= tcg_const_i32(opmode
);
4988 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
4989 gen_helper_fconst(cpu_env
, cpu_dest
, rom_offset
);
4990 tcg_temp_free_ptr(cpu_dest
);
4991 tcg_temp_free(rom_offset
);
4995 case 3: /* fmove out */
4996 cpu_src
= gen_fp_ptr(REG(ext
, 7));
4997 opsize
= ext_opsize(ext
, 10);
4998 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
,
4999 EA_STORE
, IS_USER(s
)) == -1) {
5002 gen_helper_ftst(cpu_env
, cpu_src
);
5003 tcg_temp_free_ptr(cpu_src
);
5005 case 4: /* fmove to control register. */
5006 case 5: /* fmove from control register. */
5007 gen_op_fmove_fcr(env
, s
, insn
, ext
);
5009 case 6: /* fmovem */
5011 if ((ext
& 0x1000) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
5014 gen_op_fmovem(env
, s
, insn
, ext
);
5017 if (ext
& (1 << 14)) {
5018 /* Source effective address. */
5019 opsize
= ext_opsize(ext
, 10);
5020 cpu_src
= gen_fp_result_ptr();
5021 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
,
5022 EA_LOADS
, IS_USER(s
)) == -1) {
5027 /* Source register. */
5028 opsize
= OS_EXTENDED
;
5029 cpu_src
= gen_fp_ptr(REG(ext
, 10));
5031 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
5034 gen_fp_move(cpu_dest
, cpu_src
);
5036 case 0x40: /* fsmove */
5037 gen_helper_fsround(cpu_env
, cpu_dest
, cpu_src
);
5039 case 0x44: /* fdmove */
5040 gen_helper_fdround(cpu_env
, cpu_dest
, cpu_src
);
5043 gen_helper_firound(cpu_env
, cpu_dest
, cpu_src
);
5045 case 3: /* fintrz */
5046 gen_helper_fitrunc(cpu_env
, cpu_dest
, cpu_src
);
5049 gen_helper_fsqrt(cpu_env
, cpu_dest
, cpu_src
);
5051 case 0x41: /* fssqrt */
5052 gen_helper_fssqrt(cpu_env
, cpu_dest
, cpu_src
);
5054 case 0x45: /* fdsqrt */
5055 gen_helper_fdsqrt(cpu_env
, cpu_dest
, cpu_src
);
5057 case 0x18: /* fabs */
5058 gen_helper_fabs(cpu_env
, cpu_dest
, cpu_src
);
5060 case 0x58: /* fsabs */
5061 gen_helper_fsabs(cpu_env
, cpu_dest
, cpu_src
);
5063 case 0x5c: /* fdabs */
5064 gen_helper_fdabs(cpu_env
, cpu_dest
, cpu_src
);
5066 case 0x1a: /* fneg */
5067 gen_helper_fneg(cpu_env
, cpu_dest
, cpu_src
);
5069 case 0x5a: /* fsneg */
5070 gen_helper_fsneg(cpu_env
, cpu_dest
, cpu_src
);
5072 case 0x5e: /* fdneg */
5073 gen_helper_fdneg(cpu_env
, cpu_dest
, cpu_src
);
5075 case 0x1e: /* fgetexp */
5076 gen_helper_fgetexp(cpu_env
, cpu_dest
, cpu_src
);
5078 case 0x1f: /* fgetman */
5079 gen_helper_fgetman(cpu_env
, cpu_dest
, cpu_src
);
5081 case 0x20: /* fdiv */
5082 gen_helper_fdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5084 case 0x60: /* fsdiv */
5085 gen_helper_fsdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5087 case 0x64: /* fddiv */
5088 gen_helper_fddiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5090 case 0x21: /* fmod */
5091 gen_helper_fmod(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5093 case 0x22: /* fadd */
5094 gen_helper_fadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5096 case 0x62: /* fsadd */
5097 gen_helper_fsadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5099 case 0x66: /* fdadd */
5100 gen_helper_fdadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5102 case 0x23: /* fmul */
5103 gen_helper_fmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5105 case 0x63: /* fsmul */
5106 gen_helper_fsmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5108 case 0x67: /* fdmul */
5109 gen_helper_fdmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5111 case 0x24: /* fsgldiv */
5112 gen_helper_fsgldiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5114 case 0x25: /* frem */
5115 gen_helper_frem(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5117 case 0x26: /* fscale */
5118 gen_helper_fscale(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5120 case 0x27: /* fsglmul */
5121 gen_helper_fsglmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5123 case 0x28: /* fsub */
5124 gen_helper_fsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5126 case 0x68: /* fssub */
5127 gen_helper_fssub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5129 case 0x6c: /* fdsub */
5130 gen_helper_fdsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5132 case 0x38: /* fcmp */
5133 gen_helper_fcmp(cpu_env
, cpu_src
, cpu_dest
);
5135 case 0x3a: /* ftst */
5136 gen_helper_ftst(cpu_env
, cpu_src
);
5141 tcg_temp_free_ptr(cpu_src
);
5142 gen_helper_ftst(cpu_env
, cpu_dest
);
5143 tcg_temp_free_ptr(cpu_dest
);
5146 /* FIXME: Is this right for offset addressing modes? */
5148 disas_undef_fpu(env
, s
, insn
);
5151 static void gen_fcc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
5156 c
->v2
= tcg_const_i32(0);
5158 /* TODO: Raise BSUN exception. */
5159 fpsr
= tcg_temp_new();
5160 gen_load_fcr(s
, fpsr
, M68K_FPSR
);
5163 case 16: /* Signaling False */
5165 c
->tcond
= TCG_COND_NEVER
;
5167 case 1: /* EQual Z */
5168 case 17: /* Signaling EQual Z */
5169 c
->v1
= tcg_temp_new();
5171 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5172 c
->tcond
= TCG_COND_NE
;
5174 case 2: /* Ordered Greater Than !(A || Z || N) */
5175 case 18: /* Greater Than !(A || Z || N) */
5176 c
->v1
= tcg_temp_new();
5178 tcg_gen_andi_i32(c
->v1
, fpsr
,
5179 FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5180 c
->tcond
= TCG_COND_EQ
;
5182 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
5183 case 19: /* Greater than or Equal Z || !(A || N) */
5184 c
->v1
= tcg_temp_new();
5186 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5187 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
5188 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_Z
| FPSR_CC_N
);
5189 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
5190 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5191 c
->tcond
= TCG_COND_NE
;
5193 case 4: /* Ordered Less Than !(!N || A || Z); */
5194 case 20: /* Less Than !(!N || A || Z); */
5195 c
->v1
= tcg_temp_new();
5197 tcg_gen_xori_i32(c
->v1
, fpsr
, FPSR_CC_N
);
5198 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_N
| FPSR_CC_A
| FPSR_CC_Z
);
5199 c
->tcond
= TCG_COND_EQ
;
5201 case 5: /* Ordered Less than or Equal Z || (N && !A) */
5202 case 21: /* Less than or Equal Z || (N && !A) */
5203 c
->v1
= tcg_temp_new();
5205 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5206 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
5207 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
5208 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_Z
| FPSR_CC_N
);
5209 c
->tcond
= TCG_COND_NE
;
5211 case 6: /* Ordered Greater or Less than !(A || Z) */
5212 case 22: /* Greater or Less than !(A || Z) */
5213 c
->v1
= tcg_temp_new();
5215 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
5216 c
->tcond
= TCG_COND_EQ
;
5218 case 7: /* Ordered !A */
5219 case 23: /* Greater, Less or Equal !A */
5220 c
->v1
= tcg_temp_new();
5222 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5223 c
->tcond
= TCG_COND_EQ
;
5225 case 8: /* Unordered A */
5226 case 24: /* Not Greater, Less or Equal A */
5227 c
->v1
= tcg_temp_new();
5229 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5230 c
->tcond
= TCG_COND_NE
;
5232 case 9: /* Unordered or Equal A || Z */
5233 case 25: /* Not Greater or Less then A || Z */
5234 c
->v1
= tcg_temp_new();
5236 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
5237 c
->tcond
= TCG_COND_NE
;
5239 case 10: /* Unordered or Greater Than A || !(N || Z)) */
5240 case 26: /* Not Less or Equal A || !(N || Z)) */
5241 c
->v1
= tcg_temp_new();
5243 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5244 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
5245 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_A
| FPSR_CC_N
);
5246 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
5247 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5248 c
->tcond
= TCG_COND_NE
;
5250 case 11: /* Unordered or Greater or Equal A || Z || !N */
5251 case 27: /* Not Less Than A || Z || !N */
5252 c
->v1
= tcg_temp_new();
5254 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5255 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5256 c
->tcond
= TCG_COND_NE
;
5258 case 12: /* Unordered or Less Than A || (N && !Z) */
5259 case 28: /* Not Greater than or Equal A || (N && !Z) */
5260 c
->v1
= tcg_temp_new();
5262 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5263 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
5264 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
5265 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_A
| FPSR_CC_N
);
5266 c
->tcond
= TCG_COND_NE
;
5268 case 13: /* Unordered or Less or Equal A || Z || N */
5269 case 29: /* Not Greater Than A || Z || N */
5270 c
->v1
= tcg_temp_new();
5272 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5273 c
->tcond
= TCG_COND_NE
;
5275 case 14: /* Not Equal !Z */
5276 case 30: /* Signaling Not Equal !Z */
5277 c
->v1
= tcg_temp_new();
5279 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5280 c
->tcond
= TCG_COND_EQ
;
5283 case 31: /* Signaling True */
5285 c
->tcond
= TCG_COND_ALWAYS
;
5288 tcg_temp_free(fpsr
);
5291 static void gen_fjmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
5295 gen_fcc_cond(&c
, s
, cond
);
5297 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
5308 offset
= (int16_t)read_im16(env
, s
);
5309 if (insn
& (1 << 6)) {
5310 offset
= (offset
<< 16) | read_im16(env
, s
);
5313 l1
= gen_new_label();
5315 gen_fjmpcc(s
, insn
& 0x3f, l1
);
5316 gen_jmp_tb(s
, 0, s
->pc
);
5318 gen_jmp_tb(s
, 1, base
+ offset
);
5328 ext
= read_im16(env
, s
);
5330 gen_fcc_cond(&c
, s
, cond
);
5332 tmp
= tcg_temp_new();
5333 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
5336 tcg_gen_neg_i32(tmp
, tmp
);
5337 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
5341 #if defined(CONFIG_SOFTMMU)
5342 DISAS_INSN(frestore
)
5347 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
5350 if (m68k_feature(s
->env
, M68K_FEATURE_M68040
)) {
5351 SRC_EA(env
, addr
, OS_LONG
, 0, NULL
);
5352 /* FIXME: check the state frame */
5354 disas_undef(env
, s
, insn
);
5361 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
5365 if (m68k_feature(s
->env
, M68K_FEATURE_M68040
)) {
5366 /* always write IDLE */
5367 TCGv idle
= tcg_const_i32(0x41000000);
5368 DEST_EA(env
, insn
, OS_LONG
, idle
, NULL
);
5369 tcg_temp_free(idle
);
5371 disas_undef(env
, s
, insn
);
5376 static inline TCGv
gen_mac_extract_word(DisasContext
*s
, TCGv val
, int upper
)
5378 TCGv tmp
= tcg_temp_new();
5379 if (s
->env
->macsr
& MACSR_FI
) {
5381 tcg_gen_andi_i32(tmp
, val
, 0xffff0000);
5383 tcg_gen_shli_i32(tmp
, val
, 16);
5384 } else if (s
->env
->macsr
& MACSR_SU
) {
5386 tcg_gen_sari_i32(tmp
, val
, 16);
5388 tcg_gen_ext16s_i32(tmp
, val
);
5391 tcg_gen_shri_i32(tmp
, val
, 16);
5393 tcg_gen_ext16u_i32(tmp
, val
);
5398 static void gen_mac_clear_flags(void)
5400 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
,
5401 ~(MACSR_V
| MACSR_Z
| MACSR_N
| MACSR_EV
));
5417 s
->mactmp
= tcg_temp_new_i64();
5421 ext
= read_im16(env
, s
);
5423 acc
= ((insn
>> 7) & 1) | ((ext
>> 3) & 2);
5424 dual
= ((insn
& 0x30) != 0 && (ext
& 3) != 0);
5425 if (dual
&& !m68k_feature(s
->env
, M68K_FEATURE_CF_EMAC_B
)) {
5426 disas_undef(env
, s
, insn
);
5430 /* MAC with load. */
5431 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
5432 addr
= tcg_temp_new();
5433 tcg_gen_and_i32(addr
, tmp
, QREG_MAC_MASK
);
5434 /* Load the value now to ensure correct exception behavior.
5435 Perform writeback after reading the MAC inputs. */
5436 loadval
= gen_load(s
, OS_LONG
, addr
, 0, IS_USER(s
));
5439 rx
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(insn
, 12);
5440 ry
= (ext
& 8) ? AREG(ext
, 0) : DREG(ext
, 0);
5442 loadval
= addr
= NULL_QREG
;
5443 rx
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5444 ry
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5447 gen_mac_clear_flags();
5450 /* Disabled because conditional branches clobber temporary vars. */
5451 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && !dual
) {
5452 /* Skip the multiply if we know we will ignore it. */
5453 l1
= gen_new_label();
5454 tmp
= tcg_temp_new();
5455 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 1 << (acc
+ 8));
5456 gen_op_jmp_nz32(tmp
, l1
);
5460 if ((ext
& 0x0800) == 0) {
5462 rx
= gen_mac_extract_word(s
, rx
, (ext
& 0x80) != 0);
5463 ry
= gen_mac_extract_word(s
, ry
, (ext
& 0x40) != 0);
5465 if (s
->env
->macsr
& MACSR_FI
) {
5466 gen_helper_macmulf(s
->mactmp
, cpu_env
, rx
, ry
);
5468 if (s
->env
->macsr
& MACSR_SU
)
5469 gen_helper_macmuls(s
->mactmp
, cpu_env
, rx
, ry
);
5471 gen_helper_macmulu(s
->mactmp
, cpu_env
, rx
, ry
);
5472 switch ((ext
>> 9) & 3) {
5474 tcg_gen_shli_i64(s
->mactmp
, s
->mactmp
, 1);
5477 tcg_gen_shri_i64(s
->mactmp
, s
->mactmp
, 1);
5483 /* Save the overflow flag from the multiply. */
5484 saved_flags
= tcg_temp_new();
5485 tcg_gen_mov_i32(saved_flags
, QREG_MACSR
);
5487 saved_flags
= NULL_QREG
;
5491 /* Disabled because conditional branches clobber temporary vars. */
5492 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && dual
) {
5493 /* Skip the accumulate if the value is already saturated. */
5494 l1
= gen_new_label();
5495 tmp
= tcg_temp_new();
5496 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5497 gen_op_jmp_nz32(tmp
, l1
);
5502 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5504 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5506 if (s
->env
->macsr
& MACSR_FI
)
5507 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5508 else if (s
->env
->macsr
& MACSR_SU
)
5509 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5511 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5514 /* Disabled because conditional branches clobber temporary vars. */
5520 /* Dual accumulate variant. */
5521 acc
= (ext
>> 2) & 3;
5522 /* Restore the overflow flag from the multiplier. */
5523 tcg_gen_mov_i32(QREG_MACSR
, saved_flags
);
5525 /* Disabled because conditional branches clobber temporary vars. */
5526 if ((s
->env
->macsr
& MACSR_OMC
) != 0) {
5527 /* Skip the accumulate if the value is already saturated. */
5528 l1
= gen_new_label();
5529 tmp
= tcg_temp_new();
5530 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5531 gen_op_jmp_nz32(tmp
, l1
);
5535 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5537 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5538 if (s
->env
->macsr
& MACSR_FI
)
5539 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5540 else if (s
->env
->macsr
& MACSR_SU
)
5541 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5543 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5545 /* Disabled because conditional branches clobber temporary vars. */
5550 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(acc
));
5554 rw
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5555 tcg_gen_mov_i32(rw
, loadval
);
5556 /* FIXME: Should address writeback happen with the masked or
5558 switch ((insn
>> 3) & 7) {
5559 case 3: /* Post-increment. */
5560 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 4);
5562 case 4: /* Pre-decrement. */
5563 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5565 tcg_temp_free(loadval
);
5569 DISAS_INSN(from_mac
)
5575 rx
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5576 accnum
= (insn
>> 9) & 3;
5577 acc
= MACREG(accnum
);
5578 if (s
->env
->macsr
& MACSR_FI
) {
5579 gen_helper_get_macf(rx
, cpu_env
, acc
);
5580 } else if ((s
->env
->macsr
& MACSR_OMC
) == 0) {
5581 tcg_gen_extrl_i64_i32(rx
, acc
);
5582 } else if (s
->env
->macsr
& MACSR_SU
) {
5583 gen_helper_get_macs(rx
, acc
);
5585 gen_helper_get_macu(rx
, acc
);
5588 tcg_gen_movi_i64(acc
, 0);
5589 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5593 DISAS_INSN(move_mac
)
5595 /* FIXME: This can be done without a helper. */
5599 dest
= tcg_const_i32((insn
>> 9) & 3);
5600 gen_helper_mac_move(cpu_env
, dest
, tcg_const_i32(src
));
5601 gen_mac_clear_flags();
5602 gen_helper_mac_set_flags(cpu_env
, dest
);
5605 DISAS_INSN(from_macsr
)
5609 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5610 tcg_gen_mov_i32(reg
, QREG_MACSR
);
5613 DISAS_INSN(from_mask
)
5616 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5617 tcg_gen_mov_i32(reg
, QREG_MAC_MASK
);
5620 DISAS_INSN(from_mext
)
5624 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5625 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5626 if (s
->env
->macsr
& MACSR_FI
)
5627 gen_helper_get_mac_extf(reg
, cpu_env
, acc
);
5629 gen_helper_get_mac_exti(reg
, cpu_env
, acc
);
5632 DISAS_INSN(macsr_to_ccr
)
5634 TCGv tmp
= tcg_temp_new();
5635 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 0xf);
5636 gen_helper_set_sr(cpu_env
, tmp
);
5638 set_cc_op(s
, CC_OP_FLAGS
);
5646 accnum
= (insn
>> 9) & 3;
5647 acc
= MACREG(accnum
);
5648 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5649 if (s
->env
->macsr
& MACSR_FI
) {
5650 tcg_gen_ext_i32_i64(acc
, val
);
5651 tcg_gen_shli_i64(acc
, acc
, 8);
5652 } else if (s
->env
->macsr
& MACSR_SU
) {
5653 tcg_gen_ext_i32_i64(acc
, val
);
5655 tcg_gen_extu_i32_i64(acc
, val
);
5657 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5658 gen_mac_clear_flags();
5659 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(accnum
));
5662 DISAS_INSN(to_macsr
)
5665 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5666 gen_helper_set_macsr(cpu_env
, val
);
5673 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5674 tcg_gen_ori_i32(QREG_MAC_MASK
, val
, 0xffff0000);
5681 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5682 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5683 if (s
->env
->macsr
& MACSR_FI
)
5684 gen_helper_set_mac_extf(cpu_env
, val
, acc
);
5685 else if (s
->env
->macsr
& MACSR_SU
)
5686 gen_helper_set_mac_exts(cpu_env
, val
, acc
);
5688 gen_helper_set_mac_extu(cpu_env
, val
, acc
);
5691 static disas_proc opcode_table
[65536];
5694 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
5700 /* Sanity check. All set bits must be included in the mask. */
5701 if (opcode
& ~mask
) {
5703 "qemu internal error: bogus opcode definition %04x/%04x\n",
5707 /* This could probably be cleverer. For now just optimize the case where
5708 the top bits are known. */
5709 /* Find the first zero bit in the mask. */
5711 while ((i
& mask
) != 0)
5713 /* Iterate over all combinations of this and lower bits. */
5718 from
= opcode
& ~(i
- 1);
5720 for (i
= from
; i
< to
; i
++) {
5721 if ((i
& mask
) == opcode
)
5722 opcode_table
[i
] = proc
;
5726 /* Register m68k opcode handlers. Order is important.
5727 Later insn override earlier ones. */
5728 void register_m68k_insns (CPUM68KState
*env
)
5730 /* Build the opcode table only once to avoid
5731 multithreading issues. */
5732 if (opcode_table
[0] != NULL
) {
5736 /* use BASE() for instruction available
5737 * for CF_ISA_A and M68000.
5739 #define BASE(name, opcode, mask) \
5740 register_opcode(disas_##name, 0x##opcode, 0x##mask)
5741 #define INSN(name, opcode, mask, feature) do { \
5742 if (m68k_feature(env, M68K_FEATURE_##feature)) \
5743 BASE(name, opcode, mask); \
5745 BASE(undef
, 0000, 0000);
5746 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
5747 INSN(arith_im
, 0000, ff00
, M68000
);
5748 INSN(chk2
, 00c0
, f9c0
, CHK2
);
5749 INSN(bitrev
, 00c0
, fff8
, CF_ISA_APLUSC
);
5750 BASE(bitop_reg
, 0100, f1c0
);
5751 BASE(bitop_reg
, 0140, f1c0
);
5752 BASE(bitop_reg
, 0180, f1c0
);
5753 BASE(bitop_reg
, 01c0
, f1c0
);
5754 INSN(movep
, 0108, f138
, MOVEP
);
5755 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
5756 INSN(arith_im
, 0200, ff00
, M68000
);
5757 INSN(undef
, 02c0
, ffc0
, M68000
);
5758 INSN(byterev
, 02c0
, fff8
, CF_ISA_APLUSC
);
5759 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
5760 INSN(arith_im
, 0400, ff00
, M68000
);
5761 INSN(undef
, 04c0
, ffc0
, M68000
);
5762 INSN(arith_im
, 0600, ff00
, M68000
);
5763 INSN(undef
, 06c0
, ffc0
, M68000
);
5764 INSN(ff1
, 04c0
, fff8
, CF_ISA_APLUSC
);
5765 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
5766 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
5767 INSN(arith_im
, 0c00
, ff00
, M68000
);
5768 BASE(bitop_im
, 0800, ffc0
);
5769 BASE(bitop_im
, 0840, ffc0
);
5770 BASE(bitop_im
, 0880, ffc0
);
5771 BASE(bitop_im
, 08c0
, ffc0
);
5772 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
5773 INSN(arith_im
, 0a00
, ff00
, M68000
);
5774 #if defined(CONFIG_SOFTMMU)
5775 INSN(moves
, 0e00
, ff00
, M68000
);
5777 INSN(cas
, 0ac0
, ffc0
, CAS
);
5778 INSN(cas
, 0cc0
, ffc0
, CAS
);
5779 INSN(cas
, 0ec0
, ffc0
, CAS
);
5780 INSN(cas2w
, 0cfc
, ffff
, CAS
);
5781 INSN(cas2l
, 0efc
, ffff
, CAS
);
5782 BASE(move
, 1000, f000
);
5783 BASE(move
, 2000, f000
);
5784 BASE(move
, 3000, f000
);
5785 INSN(chk
, 4000, f040
, M68000
);
5786 INSN(strldsr
, 40e7
, ffff
, CF_ISA_APLUSC
);
5787 INSN(negx
, 4080, fff8
, CF_ISA_A
);
5788 INSN(negx
, 4000, ff00
, M68000
);
5789 INSN(undef
, 40c0
, ffc0
, M68000
);
5790 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
5791 INSN(move_from_sr
, 40c0
, ffc0
, M68000
);
5792 BASE(lea
, 41c0
, f1c0
);
5793 BASE(clr
, 4200, ff00
);
5794 BASE(undef
, 42c0
, ffc0
);
5795 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
5796 INSN(move_from_ccr
, 42c0
, ffc0
, M68000
);
5797 INSN(neg
, 4480, fff8
, CF_ISA_A
);
5798 INSN(neg
, 4400, ff00
, M68000
);
5799 INSN(undef
, 44c0
, ffc0
, M68000
);
5800 BASE(move_to_ccr
, 44c0
, ffc0
);
5801 INSN(not, 4680, fff8
, CF_ISA_A
);
5802 INSN(not, 4600, ff00
, M68000
);
5803 #if defined(CONFIG_SOFTMMU)
5804 BASE(move_to_sr
, 46c0
, ffc0
);
5806 INSN(nbcd
, 4800, ffc0
, M68000
);
5807 INSN(linkl
, 4808, fff8
, M68000
);
5808 BASE(pea
, 4840, ffc0
);
5809 BASE(swap
, 4840, fff8
);
5810 INSN(bkpt
, 4848, fff8
, BKPT
);
5811 INSN(movem
, 48d0
, fbf8
, CF_ISA_A
);
5812 INSN(movem
, 48e8
, fbf8
, CF_ISA_A
);
5813 INSN(movem
, 4880, fb80
, M68000
);
5814 BASE(ext
, 4880, fff8
);
5815 BASE(ext
, 48c0
, fff8
);
5816 BASE(ext
, 49c0
, fff8
);
5817 BASE(tst
, 4a00
, ff00
);
5818 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
5819 INSN(tas
, 4ac0
, ffc0
, M68000
);
5820 #if defined(CONFIG_SOFTMMU)
5821 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
5823 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
5824 BASE(illegal
, 4afc
, ffff
);
5825 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
5826 INSN(mull
, 4c00
, ffc0
, LONG_MULDIV
);
5827 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
5828 INSN(divl
, 4c40
, ffc0
, LONG_MULDIV
);
5829 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
5830 BASE(trap
, 4e40
, fff0
);
5831 BASE(link
, 4e50
, fff8
);
5832 BASE(unlk
, 4e58
, fff8
);
5833 #if defined(CONFIG_SOFTMMU)
5834 INSN(move_to_usp
, 4e60
, fff8
, USP
);
5835 INSN(move_from_usp
, 4e68
, fff8
, USP
);
5836 INSN(reset
, 4e70
, ffff
, M68000
);
5837 BASE(stop
, 4e72
, ffff
);
5838 BASE(rte
, 4e73
, ffff
);
5839 INSN(cf_movec
, 4e7b
, ffff
, CF_ISA_A
);
5840 INSN(m68k_movec
, 4e7a
, fffe
, M68000
);
5842 BASE(nop
, 4e71
, ffff
);
5843 INSN(rtd
, 4e74
, ffff
, RTD
);
5844 BASE(rts
, 4e75
, ffff
);
5845 BASE(jump
, 4e80
, ffc0
);
5846 BASE(jump
, 4ec0
, ffc0
);
5847 INSN(addsubq
, 5000, f080
, M68000
);
5848 BASE(addsubq
, 5080, f0c0
);
5849 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
); /* Scc.B Dx */
5850 INSN(scc
, 50c0
, f0c0
, M68000
); /* Scc.B <EA> */
5851 INSN(dbcc
, 50c8
, f0f8
, M68000
);
5852 INSN(tpf
, 51f8
, fff8
, CF_ISA_A
);
5854 /* Branch instructions. */
5855 BASE(branch
, 6000, f000
);
5856 /* Disable long branch instructions, then add back the ones we want. */
5857 BASE(undef
, 60ff
, f0ff
); /* All long branches. */
5858 INSN(branch
, 60ff
, f0ff
, CF_ISA_B
);
5859 INSN(undef
, 60ff
, ffff
, CF_ISA_B
); /* bra.l */
5860 INSN(branch
, 60ff
, ffff
, BRAL
);
5861 INSN(branch
, 60ff
, f0ff
, BCCL
);
5863 BASE(moveq
, 7000, f100
);
5864 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
5865 BASE(or, 8000, f000
);
5866 BASE(divw
, 80c0
, f0c0
);
5867 INSN(sbcd_reg
, 8100, f1f8
, M68000
);
5868 INSN(sbcd_mem
, 8108, f1f8
, M68000
);
5869 BASE(addsub
, 9000, f000
);
5870 INSN(undef
, 90c0
, f0c0
, CF_ISA_A
);
5871 INSN(subx_reg
, 9180, f1f8
, CF_ISA_A
);
5872 INSN(subx_reg
, 9100, f138
, M68000
);
5873 INSN(subx_mem
, 9108, f138
, M68000
);
5874 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
5875 INSN(suba
, 90c0
, f0c0
, M68000
);
5877 BASE(undef_mac
, a000
, f000
);
5878 INSN(mac
, a000
, f100
, CF_EMAC
);
5879 INSN(from_mac
, a180
, f9b0
, CF_EMAC
);
5880 INSN(move_mac
, a110
, f9fc
, CF_EMAC
);
5881 INSN(from_macsr
,a980
, f9f0
, CF_EMAC
);
5882 INSN(from_mask
, ad80
, fff0
, CF_EMAC
);
5883 INSN(from_mext
, ab80
, fbf0
, CF_EMAC
);
5884 INSN(macsr_to_ccr
, a9c0
, ffff
, CF_EMAC
);
5885 INSN(to_mac
, a100
, f9c0
, CF_EMAC
);
5886 INSN(to_macsr
, a900
, ffc0
, CF_EMAC
);
5887 INSN(to_mext
, ab00
, fbc0
, CF_EMAC
);
5888 INSN(to_mask
, ad00
, ffc0
, CF_EMAC
);
5890 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
5891 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
5892 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
5893 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
5894 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
5895 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
5896 INSN(cmp
, b000
, f100
, M68000
);
5897 INSN(eor
, b100
, f100
, M68000
);
5898 INSN(cmpm
, b108
, f138
, M68000
);
5899 INSN(cmpa
, b0c0
, f0c0
, M68000
);
5900 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
5901 BASE(and, c000
, f000
);
5902 INSN(exg_dd
, c140
, f1f8
, M68000
);
5903 INSN(exg_aa
, c148
, f1f8
, M68000
);
5904 INSN(exg_da
, c188
, f1f8
, M68000
);
5905 BASE(mulw
, c0c0
, f0c0
);
5906 INSN(abcd_reg
, c100
, f1f8
, M68000
);
5907 INSN(abcd_mem
, c108
, f1f8
, M68000
);
5908 BASE(addsub
, d000
, f000
);
5909 INSN(undef
, d0c0
, f0c0
, CF_ISA_A
);
5910 INSN(addx_reg
, d180
, f1f8
, CF_ISA_A
);
5911 INSN(addx_reg
, d100
, f138
, M68000
);
5912 INSN(addx_mem
, d108
, f138
, M68000
);
5913 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
5914 INSN(adda
, d0c0
, f0c0
, M68000
);
5915 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
5916 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
5917 INSN(shift8_im
, e000
, f0f0
, M68000
);
5918 INSN(shift16_im
, e040
, f0f0
, M68000
);
5919 INSN(shift_im
, e080
, f0f0
, M68000
);
5920 INSN(shift8_reg
, e020
, f0f0
, M68000
);
5921 INSN(shift16_reg
, e060
, f0f0
, M68000
);
5922 INSN(shift_reg
, e0a0
, f0f0
, M68000
);
5923 INSN(shift_mem
, e0c0
, fcc0
, M68000
);
5924 INSN(rotate_im
, e090
, f0f0
, M68000
);
5925 INSN(rotate8_im
, e010
, f0f0
, M68000
);
5926 INSN(rotate16_im
, e050
, f0f0
, M68000
);
5927 INSN(rotate_reg
, e0b0
, f0f0
, M68000
);
5928 INSN(rotate8_reg
, e030
, f0f0
, M68000
);
5929 INSN(rotate16_reg
, e070
, f0f0
, M68000
);
5930 INSN(rotate_mem
, e4c0
, fcc0
, M68000
);
5931 INSN(bfext_mem
, e9c0
, fdc0
, BITFIELD
); /* bfextu & bfexts */
5932 INSN(bfext_reg
, e9c0
, fdf8
, BITFIELD
);
5933 INSN(bfins_mem
, efc0
, ffc0
, BITFIELD
);
5934 INSN(bfins_reg
, efc0
, fff8
, BITFIELD
);
5935 INSN(bfop_mem
, eac0
, ffc0
, BITFIELD
); /* bfchg */
5936 INSN(bfop_reg
, eac0
, fff8
, BITFIELD
); /* bfchg */
5937 INSN(bfop_mem
, ecc0
, ffc0
, BITFIELD
); /* bfclr */
5938 INSN(bfop_reg
, ecc0
, fff8
, BITFIELD
); /* bfclr */
5939 INSN(bfop_mem
, edc0
, ffc0
, BITFIELD
); /* bfffo */
5940 INSN(bfop_reg
, edc0
, fff8
, BITFIELD
); /* bfffo */
5941 INSN(bfop_mem
, eec0
, ffc0
, BITFIELD
); /* bfset */
5942 INSN(bfop_reg
, eec0
, fff8
, BITFIELD
); /* bfset */
5943 INSN(bfop_mem
, e8c0
, ffc0
, BITFIELD
); /* bftst */
5944 INSN(bfop_reg
, e8c0
, fff8
, BITFIELD
); /* bftst */
5945 BASE(undef_fpu
, f000
, f000
);
5946 INSN(fpu
, f200
, ffc0
, CF_FPU
);
5947 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
5948 INSN(fpu
, f200
, ffc0
, FPU
);
5949 INSN(fscc
, f240
, ffc0
, FPU
);
5950 INSN(fbcc
, f280
, ff80
, FPU
);
5951 #if defined(CONFIG_SOFTMMU)
5952 INSN(frestore
, f340
, ffc0
, CF_FPU
);
5953 INSN(fsave
, f300
, ffc0
, CF_FPU
);
5954 INSN(frestore
, f340
, ffc0
, FPU
);
5955 INSN(fsave
, f300
, ffc0
, FPU
);
5956 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
5957 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
5958 INSN(cpush
, f420
, ff20
, M68040
);
5959 INSN(cinv
, f400
, ff20
, M68040
);
5960 INSN(pflush
, f500
, ffe0
, M68040
);
5961 INSN(ptest
, f548
, ffd8
, M68040
);
5962 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
5963 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
5965 INSN(move16_mem
, f600
, ffe0
, M68040
);
5966 INSN(move16_reg
, f620
, fff8
, M68040
);
5970 /* ??? Some of this implementation is not exception safe. We should always
5971 write back the result to memory before setting the condition codes. */
5972 static void disas_m68k_insn(CPUM68KState
* env
, DisasContext
*s
)
5974 uint16_t insn
= read_im16(env
, s
);
5975 opcode_table
[insn
](env
, s
, insn
);
5979 /* generate intermediate code for basic block 'tb'. */
5980 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
)
5982 CPUM68KState
*env
= cs
->env_ptr
;
5983 DisasContext dc1
, *dc
= &dc1
;
5984 target_ulong pc_start
;
5989 /* generate intermediate code */
5995 dc
->is_jmp
= DISAS_NEXT
;
5997 dc
->cc_op
= CC_OP_DYNAMIC
;
5998 dc
->cc_op_synced
= 1;
5999 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
6001 dc
->writeback_mask
= 0;
6003 max_insns
= tb_cflags(tb
) & CF_COUNT_MASK
;
6004 if (max_insns
== 0) {
6005 max_insns
= CF_COUNT_MASK
;
6007 if (max_insns
> TCG_MAX_INSNS
) {
6008 max_insns
= TCG_MAX_INSNS
;
6013 pc_offset
= dc
->pc
- pc_start
;
6014 tcg_gen_insn_start(dc
->pc
, dc
->cc_op
);
6017 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
6018 gen_exception(dc
, dc
->pc
, EXCP_DEBUG
);
6019 dc
->is_jmp
= DISAS_JUMP
;
6020 /* The address covered by the breakpoint must be included in
6021 [tb->pc, tb->pc + tb->size) in order to for it to be
6022 properly cleared -- thus we increment the PC here so that
6023 the logic setting tb->size below does the right thing. */
6028 if (num_insns
== max_insns
&& (tb_cflags(tb
) & CF_LAST_IO
)) {
6032 dc
->insn_pc
= dc
->pc
;
6033 disas_m68k_insn(env
, dc
);
6034 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
6035 !cs
->singlestep_enabled
&&
6037 (pc_offset
) < (TARGET_PAGE_SIZE
- 32) &&
6038 num_insns
< max_insns
);
6040 if (tb_cflags(tb
) & CF_LAST_IO
)
6042 if (unlikely(cs
->singlestep_enabled
)) {
6043 /* Make sure the pc is updated, and raise a debug exception. */
6046 tcg_gen_movi_i32(QREG_PC
, dc
->pc
);
6048 gen_helper_raise_exception(cpu_env
, tcg_const_i32(EXCP_DEBUG
));
6050 switch(dc
->is_jmp
) {
6053 gen_jmp_tb(dc
, 0, dc
->pc
);
6059 /* indicate that the hash table must be used to find the next TB */
6063 /* nothing more to generate */
6067 gen_tb_end(tb
, num_insns
);
6070 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
6071 && qemu_log_in_addr_range(pc_start
)) {
6073 qemu_log("----------------\n");
6074 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
6075 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
);
6080 tb
->size
= dc
->pc
- pc_start
;
6081 tb
->icount
= num_insns
;
6084 static double floatx80_to_double(CPUM68KState
*env
, uint16_t high
, uint64_t low
)
6086 floatx80 a
= { .high
= high
, .low
= low
};
6092 u
.f64
= floatx80_to_float64(a
, &env
->fp_status
);
6096 void m68k_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
6099 M68kCPU
*cpu
= M68K_CPU(cs
);
6100 CPUM68KState
*env
= &cpu
->env
;
6103 for (i
= 0; i
< 8; i
++) {
6104 cpu_fprintf(f
, "D%d = %08x A%d = %08x "
6105 "F%d = %04x %016"PRIx64
" (%12g)\n",
6106 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
6107 i
, env
->fregs
[i
].l
.upper
, env
->fregs
[i
].l
.lower
,
6108 floatx80_to_double(env
, env
->fregs
[i
].l
.upper
,
6109 env
->fregs
[i
].l
.lower
));
6111 cpu_fprintf (f
, "PC = %08x ", env
->pc
);
6112 sr
= env
->sr
| cpu_m68k_get_ccr(env
);
6113 cpu_fprintf(f
, "SR = %04x T:%x I:%x %c%c %c%c%c%c%c\n",
6114 sr
, (sr
& SR_T
) >> SR_T_SHIFT
, (sr
& SR_I
) >> SR_I_SHIFT
,
6115 (sr
& SR_S
) ? 'S' : 'U', (sr
& SR_M
) ? '%' : 'I',
6116 (sr
& CCF_X
) ? 'X' : '-', (sr
& CCF_N
) ? 'N' : '-',
6117 (sr
& CCF_Z
) ? 'Z' : '-', (sr
& CCF_V
) ? 'V' : '-',
6118 (sr
& CCF_C
) ? 'C' : '-');
6119 cpu_fprintf(f
, "FPSR = %08x %c%c%c%c ", env
->fpsr
,
6120 (env
->fpsr
& FPSR_CC_A
) ? 'A' : '-',
6121 (env
->fpsr
& FPSR_CC_I
) ? 'I' : '-',
6122 (env
->fpsr
& FPSR_CC_Z
) ? 'Z' : '-',
6123 (env
->fpsr
& FPSR_CC_N
) ? 'N' : '-');
6124 cpu_fprintf(f
, "\n "
6125 "FPCR = %04x ", env
->fpcr
);
6126 switch (env
->fpcr
& FPCR_PREC_MASK
) {
6128 cpu_fprintf(f
, "X ");
6131 cpu_fprintf(f
, "S ");
6134 cpu_fprintf(f
, "D ");
6137 switch (env
->fpcr
& FPCR_RND_MASK
) {
6139 cpu_fprintf(f
, "RN ");
6142 cpu_fprintf(f
, "RZ ");
6145 cpu_fprintf(f
, "RM ");
6148 cpu_fprintf(f
, "RP ");
6151 cpu_fprintf(f
, "\n");
6152 #ifdef CONFIG_SOFTMMU
6153 cpu_fprintf(f
, "%sA7(MSP) = %08x %sA7(USP) = %08x %sA7(ISP) = %08x\n",
6154 env
->current_sp
== M68K_SSP
? "->" : " ", env
->sp
[M68K_SSP
],
6155 env
->current_sp
== M68K_USP
? "->" : " ", env
->sp
[M68K_USP
],
6156 env
->current_sp
== M68K_ISP
? "->" : " ", env
->sp
[M68K_ISP
]);
6157 cpu_fprintf(f
, "VBR = 0x%08x\n", env
->vbr
);
6158 cpu_fprintf(f
, "SFC = %x DFC %x\n", env
->sfc
, env
->dfc
);
6159 cpu_fprintf(f
, "SSW %08x TCR %08x URP %08x SRP %08x\n",
6160 env
->mmu
.ssw
, env
->mmu
.tcr
, env
->mmu
.urp
, env
->mmu
.srp
);
6161 cpu_fprintf(f
, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n",
6162 env
->mmu
.ttr
[M68K_DTTR0
], env
->mmu
.ttr
[M68K_DTTR1
],
6163 env
->mmu
.ttr
[M68K_ITTR0
], env
->mmu
.ttr
[M68K_ITTR1
]);
6164 cpu_fprintf(f
, "MMUSR %08x, fault at %08x\n",
6165 env
->mmu
.mmusr
, env
->mmu
.ar
);
6169 void restore_state_to_opc(CPUM68KState
*env
, TranslationBlock
*tb
,
6172 int cc_op
= data
[1];
6174 if (cc_op
!= CC_OP_DYNAMIC
) {