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hw/arm/smmuv3: Abort on vfio or vhost case
[qemu/ar7.git] / hw / arm / fsl-imx7.c
blob26c1d27f7caca594cb6ba8d6a6b73427fae1963e
1 /*
2 * Copyright (c) 2018, Impinj, Inc.
3 *
4 * i.MX7 SoC definitions
5 *
6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
7 *
8 * Based on hw/arm/fsl-imx6.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu-common.h"
24 #include "hw/arm/fsl-imx7.h"
25 #include "hw/misc/unimp.h"
26 #include "sysemu/sysemu.h"
27 #include "qemu/error-report.h"
28
29 #define NAME_SIZE 20
30
31 static void fsl_imx7_init(Object *obj)
32 {
33 BusState *sysbus = sysbus_get_default();
34 FslIMX7State *s = FSL_IMX7(obj);
35 char name[NAME_SIZE];
36 int i;
37
38
39 for (i = 0; i < MIN(smp_cpus, FSL_IMX7_NUM_CPUS); i++) {
40 object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
41 ARM_CPU_TYPE_NAME("cortex-a7"));
42 snprintf(name, NAME_SIZE, "cpu%d", i);
43 object_property_add_child(obj, name, OBJECT(&s->cpu[i]),
44 &error_fatal);
45 }
46
47 /*
48 * A7MPCORE
49 */
50 object_initialize(&s->a7mpcore, sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV);
51 qdev_set_parent_bus(DEVICE(&s->a7mpcore), sysbus);
52 object_property_add_child(obj, "a7mpcore",
53 OBJECT(&s->a7mpcore), &error_fatal);
54
55 /*
56 * GPIOs 1 to 7
57 */
58 for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
59 object_initialize(&s->gpio[i], sizeof(s->gpio[i]),
60 TYPE_IMX_GPIO);
61 qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus);
62 snprintf(name, NAME_SIZE, "gpio%d", i);
63 object_property_add_child(obj, name,
64 OBJECT(&s->gpio[i]), &error_fatal);
65 }
66
67 /*
68 * GPT1, 2, 3, 4
69 */
70 for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
71 object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX7_GPT);
72 qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus);
73 snprintf(name, NAME_SIZE, "gpt%d", i);
74 object_property_add_child(obj, name, OBJECT(&s->gpt[i]),
75 &error_fatal);
76 }
77
78 /*
79 * CCM
80 */
81 object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX7_CCM);
82 qdev_set_parent_bus(DEVICE(&s->ccm), sysbus);
83 object_property_add_child(obj, "ccm", OBJECT(&s->ccm), &error_fatal);
84
85 /*
86 * Analog
87 */
88 object_initialize(&s->analog, sizeof(s->analog), TYPE_IMX7_ANALOG);
89 qdev_set_parent_bus(DEVICE(&s->analog), sysbus);
90 object_property_add_child(obj, "analog", OBJECT(&s->analog), &error_fatal);
91
92 /*
93 * GPCv2
94 */
95 object_initialize(&s->gpcv2, sizeof(s->gpcv2), TYPE_IMX_GPCV2);
96 qdev_set_parent_bus(DEVICE(&s->gpcv2), sysbus);
97 object_property_add_child(obj, "gpcv2", OBJECT(&s->gpcv2), &error_fatal);
98
99 for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
100 object_initialize(&s->spi[i], sizeof(s->spi[i]), TYPE_IMX_SPI);
101 qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
102 snprintf(name, NAME_SIZE, "spi%d", i + 1);
103 object_property_add_child(obj, name, OBJECT(&s->spi[i]), NULL);
104 }
105
106
107 for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
108 object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
109 qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
110 snprintf(name, NAME_SIZE, "i2c%d", i + 1);
111 object_property_add_child(obj, name, OBJECT(&s->i2c[i]), NULL);
112 }
113
114 /*
115 * UART
116 */
117 for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
118 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
119 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus);
120 snprintf(name, NAME_SIZE, "uart%d", i);
121 object_property_add_child(obj, name, OBJECT(&s->uart[i]),
122 &error_fatal);
123 }
124
125 /*
126 * Ethernet
127 */
128 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
129 object_initialize(&s->eth[i], sizeof(s->eth[i]), TYPE_IMX_ENET);
130 qdev_set_parent_bus(DEVICE(&s->eth[i]), sysbus);
131 snprintf(name, NAME_SIZE, "eth%d", i);
132 object_property_add_child(obj, name, OBJECT(&s->eth[i]),
133 &error_fatal);
134 }
135
136 /*
137 * SDHCI
138 */
139 for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
140 object_initialize(&s->usdhc[i], sizeof(s->usdhc[i]),
141 TYPE_IMX_USDHC);
142 qdev_set_parent_bus(DEVICE(&s->usdhc[i]), sysbus);
143 snprintf(name, NAME_SIZE, "usdhc%d", i);
144 object_property_add_child(obj, name, OBJECT(&s->usdhc[i]),
145 &error_fatal);
146 }
147
148 /*
149 * SNVS
150 */
151 object_initialize(&s->snvs, sizeof(s->snvs), TYPE_IMX7_SNVS);
152 qdev_set_parent_bus(DEVICE(&s->snvs), sysbus);
153 object_property_add_child(obj, "snvs", OBJECT(&s->snvs), &error_fatal);
154
155 /*
156 * Watchdog
157 */
158 for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
159 object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_IMX2_WDT);
160 qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus);
161 snprintf(name, NAME_SIZE, "wdt%d", i);
162 object_property_add_child(obj, name, OBJECT(&s->wdt[i]),
163 &error_fatal);
164 }
165
166 /*
167 * GPR
168 */
169 object_initialize(&s->gpr, sizeof(s->gpr), TYPE_IMX7_GPR);
170 qdev_set_parent_bus(DEVICE(&s->gpr), sysbus);
171 object_property_add_child(obj, "gpr", OBJECT(&s->gpr), &error_fatal);
172
173 object_initialize(&s->pcie, sizeof(s->pcie), TYPE_DESIGNWARE_PCIE_HOST);
174 qdev_set_parent_bus(DEVICE(&s->pcie), sysbus);
175 object_property_add_child(obj, "pcie", OBJECT(&s->pcie), &error_fatal);
176
177 for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
178 object_initialize(&s->usb[i],
179 sizeof(s->usb[i]), TYPE_CHIPIDEA);
180 qdev_set_parent_bus(DEVICE(&s->usb[i]), sysbus);
181 snprintf(name, NAME_SIZE, "usb%d", i);
182 object_property_add_child(obj, name,
183 OBJECT(&s->usb[i]), &error_fatal);
184 }
185 }
186
187 static void fsl_imx7_realize(DeviceState *dev, Error **errp)
188 {
189 FslIMX7State *s = FSL_IMX7(dev);
190 Object *o;
191 int i;
192 qemu_irq irq;
193 char name[NAME_SIZE];
194
195 if (smp_cpus > FSL_IMX7_NUM_CPUS) {
196 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
197 TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus);
198 return;
199 }
200
201 for (i = 0; i < smp_cpus; i++) {
202 o = OBJECT(&s->cpu[i]);
203
204 object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC,
205 "psci-conduit", &error_abort);
206
207 /* On uniprocessor, the CBAR is set to 0 */
208 if (smp_cpus > 1) {
209 object_property_set_int(o, FSL_IMX7_A7MPCORE_ADDR,
210 "reset-cbar", &error_abort);
211 }
212
213 if (i) {
214 /* Secondary CPUs start in PSCI powered-down state */
215 object_property_set_bool(o, true,
216 "start-powered-off", &error_abort);
217 }
218
219 object_property_set_bool(o, true, "realized", &error_abort);
220 }
221
222 /*
223 * A7MPCORE
224 */
225 object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu",
226 &error_abort);
227 object_property_set_int(OBJECT(&s->a7mpcore),
228 FSL_IMX7_MAX_IRQ + GIC_INTERNAL,
229 "num-irq", &error_abort);
230
231 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
232 &error_abort);
233 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
234
235 for (i = 0; i < smp_cpus; i++) {
236 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
237 DeviceState *d = DEVICE(qemu_get_cpu(i));
238
239 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
240 sysbus_connect_irq(sbd, i, irq);
241 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
242 sysbus_connect_irq(sbd, i + smp_cpus, irq);
243 }
244
245 /*
246 * A7MPCORE DAP
247 */
248 create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
249 0x100000);
250
251 /*
252 * GPT1, 2, 3, 4
253 */
254 for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
255 static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
256 FSL_IMX7_GPT1_ADDR,
257 FSL_IMX7_GPT2_ADDR,
258 FSL_IMX7_GPT3_ADDR,
259 FSL_IMX7_GPT4_ADDR,
260 };
261
262 s->gpt[i].ccm = IMX_CCM(&s->ccm);
263 object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized",
264 &error_abort);
265 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
266 }
267
268 for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
269 static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
270 FSL_IMX7_GPIO1_ADDR,
271 FSL_IMX7_GPIO2_ADDR,
272 FSL_IMX7_GPIO3_ADDR,
273 FSL_IMX7_GPIO4_ADDR,
274 FSL_IMX7_GPIO5_ADDR,
275 FSL_IMX7_GPIO6_ADDR,
276 FSL_IMX7_GPIO7_ADDR,
277 };
278
279 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized",
280 &error_abort);
281 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]);
282 }
283
284 /*
285 * IOMUXC and IOMUXC_LPSR
286 */
287 for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
288 static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
289 FSL_IMX7_IOMUXC_ADDR,
290 FSL_IMX7_IOMUXC_LPSR_ADDR,
291 };
292
293 snprintf(name, NAME_SIZE, "iomuxc%d", i);
294 create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
295 FSL_IMX7_IOMUXCn_SIZE);
296 }
297
298 /*
299 * CCM
300 */
301 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort);
302 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR);
303
304 /*
305 * Analog
306 */
307 object_property_set_bool(OBJECT(&s->analog), true, "realized",
308 &error_abort);
309 sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, FSL_IMX7_ANALOG_ADDR);
310
311 /*
312 * GPCv2
313 */
314 object_property_set_bool(OBJECT(&s->gpcv2), true,
315 "realized", &error_abort);
316 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
317
318 /* Initialize all ECSPI */
319 for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
320 static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
321 FSL_IMX7_ECSPI1_ADDR,
322 FSL_IMX7_ECSPI2_ADDR,
323 FSL_IMX7_ECSPI3_ADDR,
324 FSL_IMX7_ECSPI4_ADDR,
325 };
326
327 static const hwaddr FSL_IMX7_SPIn_IRQ[FSL_IMX7_NUM_ECSPIS] = {
328 FSL_IMX7_ECSPI1_IRQ,
329 FSL_IMX7_ECSPI2_IRQ,
330 FSL_IMX7_ECSPI3_IRQ,
331 FSL_IMX7_ECSPI4_IRQ,
332 };
333
334 /* Initialize the SPI */
335 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
336 &error_abort);
337 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
338 FSL_IMX7_SPIn_ADDR[i]);
339 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
340 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
341 FSL_IMX7_SPIn_IRQ[i]));
342 }
343
344 for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
345 static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
346 FSL_IMX7_I2C1_ADDR,
347 FSL_IMX7_I2C2_ADDR,
348 FSL_IMX7_I2C3_ADDR,
349 FSL_IMX7_I2C4_ADDR,
350 };
351
352 static const hwaddr FSL_IMX7_I2Cn_IRQ[FSL_IMX7_NUM_I2CS] = {
353 FSL_IMX7_I2C1_IRQ,
354 FSL_IMX7_I2C2_IRQ,
355 FSL_IMX7_I2C3_IRQ,
356 FSL_IMX7_I2C4_IRQ,
357 };
358
359 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized",
360 &error_abort);
361 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]);
362
363 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
364 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
365 FSL_IMX7_I2Cn_IRQ[i]));
366 }
367
368 /*
369 * UART
370 */
371 for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
372 static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
373 FSL_IMX7_UART1_ADDR,
374 FSL_IMX7_UART2_ADDR,
375 FSL_IMX7_UART3_ADDR,
376 FSL_IMX7_UART4_ADDR,
377 FSL_IMX7_UART5_ADDR,
378 FSL_IMX7_UART6_ADDR,
379 FSL_IMX7_UART7_ADDR,
380 };
381
382 static const int FSL_IMX7_UARTn_IRQ[FSL_IMX7_NUM_UARTS] = {
383 FSL_IMX7_UART1_IRQ,
384 FSL_IMX7_UART2_IRQ,
385 FSL_IMX7_UART3_IRQ,
386 FSL_IMX7_UART4_IRQ,
387 FSL_IMX7_UART5_IRQ,
388 FSL_IMX7_UART6_IRQ,
389 FSL_IMX7_UART7_IRQ,
390 };
391
392
393 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
394
395 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized",
396 &error_abort);
397
398 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]);
399
400 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]);
401 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq);
402 }
403
404 /*
405 * Ethernet
406 */
407 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
408 static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = {
409 FSL_IMX7_ENET1_ADDR,
410 FSL_IMX7_ENET2_ADDR,
411 };
412
413 object_property_set_uint(OBJECT(&s->eth[i]), FSL_IMX7_ETH_NUM_TX_RINGS,
414 "tx-ring-num", &error_abort);
415 qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
416 object_property_set_bool(OBJECT(&s->eth[i]), true, "realized",
417 &error_abort);
418
419 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]);
420
421 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0));
422 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq);
423 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3));
424 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq);
425 }
426
427 /*
428 * USDHC
429 */
430 for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
431 static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
432 FSL_IMX7_USDHC1_ADDR,
433 FSL_IMX7_USDHC2_ADDR,
434 FSL_IMX7_USDHC3_ADDR,
435 };
436
437 static const int FSL_IMX7_USDHCn_IRQ[FSL_IMX7_NUM_USDHCS] = {
438 FSL_IMX7_USDHC1_IRQ,
439 FSL_IMX7_USDHC2_IRQ,
440 FSL_IMX7_USDHC3_IRQ,
441 };
442
443 object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized",
444 &error_abort);
445
446 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
447 FSL_IMX7_USDHCn_ADDR[i]);
448
449 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]);
450 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq);
451 }
452
453 /*
454 * SNVS
455 */
456 object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort);
457 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
458
459 /*
460 * SRC
461 */
462 create_unimplemented_device("sdma", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
463
464 /*
465 * Watchdog
466 */
467 for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
468 static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
469 FSL_IMX7_WDOG1_ADDR,
470 FSL_IMX7_WDOG2_ADDR,
471 FSL_IMX7_WDOG3_ADDR,
472 FSL_IMX7_WDOG4_ADDR,
473 };
474
475 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
476 &error_abort);
477
478 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
479 }
480
481 /*
482 * SDMA
483 */
484 create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE);
485
486
487 object_property_set_bool(OBJECT(&s->gpr), true, "realized",
488 &error_abort);
489 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
490
491 object_property_set_bool(OBJECT(&s->pcie), true,
492 "realized", &error_abort);
493 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
494
495 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ);
496 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
497 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ);
498 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
499 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ);
500 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
501 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
502 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
503
504
505 for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
506 static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
507 FSL_IMX7_USBMISC1_ADDR,
508 FSL_IMX7_USBMISC2_ADDR,
509 FSL_IMX7_USBMISC3_ADDR,
510 };
511
512 static const hwaddr FSL_IMX7_USBn_ADDR[FSL_IMX7_NUM_USBS] = {
513 FSL_IMX7_USB1_ADDR,
514 FSL_IMX7_USB2_ADDR,
515 FSL_IMX7_USB3_ADDR,
516 };
517
518 static const hwaddr FSL_IMX7_USBn_IRQ[FSL_IMX7_NUM_USBS] = {
519 FSL_IMX7_USB1_IRQ,
520 FSL_IMX7_USB2_IRQ,
521 FSL_IMX7_USB3_IRQ,
522 };
523
524 object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
525 &error_abort);
526 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
527 FSL_IMX7_USBn_ADDR[i]);
528
529 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]);
530 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq);
531
532 snprintf(name, NAME_SIZE, "usbmisc%d", i);
533 create_unimplemented_device(name, FSL_IMX7_USBMISCn_ADDR[i],
534 FSL_IMX7_USBMISCn_SIZE);
535 }
536
537 /*
538 * ADCs
539 */
540 for (i = 0; i < FSL_IMX7_NUM_ADCS; i++) {
541 static const hwaddr FSL_IMX7_ADCn_ADDR[FSL_IMX7_NUM_ADCS] = {
542 FSL_IMX7_ADC1_ADDR,
543 FSL_IMX7_ADC2_ADDR,
544 };
545
546 snprintf(name, NAME_SIZE, "adc%d", i);
547 create_unimplemented_device(name, FSL_IMX7_ADCn_ADDR[i],
548 FSL_IMX7_ADCn_SIZE);
549 }
550
551 /*
552 * LCD
553 */
554 create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR,
555 FSL_IMX7_LCDIF_SIZE);
556 }
557
558 static void fsl_imx7_class_init(ObjectClass *oc, void *data)
559 {
560 DeviceClass *dc = DEVICE_CLASS(oc);
561
562 dc->realize = fsl_imx7_realize;
563
564 /* Reason: Uses serial_hds and nd_table in realize() directly */
565 dc->user_creatable = false;
566 dc->desc = "i.MX7 SOC";
567 }
568
569 static const TypeInfo fsl_imx7_type_info = {
570 .name = TYPE_FSL_IMX7,
571 .parent = TYPE_DEVICE,
572 .instance_size = sizeof(FslIMX7State),
573 .instance_init = fsl_imx7_init,
574 .class_init = fsl_imx7_class_init,
575 };
576
577 static void fsl_imx7_register_types(void)
578 {
579 type_register_static(&fsl_imx7_type_info);
580 }
581 type_init(fsl_imx7_register_types)
AR7 emulation for QEMU