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hw: move headers to include/
[qemu/ar7.git] / hw / ppc / ppc405_uc.c
blob82b8956ea83cbdd452dfec8f8d6baf43e77c3141
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/ppc/ppc.h"
26 #include "hw/ppc405.h"
27 #include "hw/char/serial.h"
28 #include "qemu/timer.h"
29 #include "sysemu/sysemu.h"
30 #include "qemu/log.h"
31 #include "exec/address-spaces.h"
32
33 #define DEBUG_OPBA
34 #define DEBUG_SDRAM
35 #define DEBUG_GPIO
36 #define DEBUG_SERIAL
37 #define DEBUG_OCM
38 //#define DEBUG_I2C
39 #define DEBUG_GPT
40 #define DEBUG_MAL
41 #define DEBUG_CLOCKS
42 //#define DEBUG_CLOCKS_LL
43
44 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
45 uint32_t flags)
46 {
47 ram_addr_t bdloc;
48 int i, n;
49
50 /* We put the bd structure at the top of memory */
51 if (bd->bi_memsize >= 0x01000000UL)
52 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
53 else
54 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
55 stl_be_phys(bdloc + 0x00, bd->bi_memstart);
56 stl_be_phys(bdloc + 0x04, bd->bi_memsize);
57 stl_be_phys(bdloc + 0x08, bd->bi_flashstart);
58 stl_be_phys(bdloc + 0x0C, bd->bi_flashsize);
59 stl_be_phys(bdloc + 0x10, bd->bi_flashoffset);
60 stl_be_phys(bdloc + 0x14, bd->bi_sramstart);
61 stl_be_phys(bdloc + 0x18, bd->bi_sramsize);
62 stl_be_phys(bdloc + 0x1C, bd->bi_bootflags);
63 stl_be_phys(bdloc + 0x20, bd->bi_ipaddr);
64 for (i = 0; i < 6; i++) {
65 stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
66 }
67 stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed);
68 stl_be_phys(bdloc + 0x2C, bd->bi_intfreq);
69 stl_be_phys(bdloc + 0x30, bd->bi_busfreq);
70 stl_be_phys(bdloc + 0x34, bd->bi_baudrate);
71 for (i = 0; i < 4; i++) {
72 stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
73 }
74 for (i = 0; i < 32; i++) {
75 stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]);
76 }
77 stl_be_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
78 stl_be_phys(bdloc + 0x60, bd->bi_pci_busfreq);
79 for (i = 0; i < 6; i++) {
80 stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
81 }
82 n = 0x6A;
83 if (flags & 0x00000001) {
84 for (i = 0; i < 6; i++)
85 stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
86 }
87 stl_be_phys(bdloc + n, bd->bi_opbfreq);
88 n += 4;
89 for (i = 0; i < 2; i++) {
90 stl_be_phys(bdloc + n, bd->bi_iic_fast[i]);
91 n += 4;
92 }
93
94 return bdloc;
95 }
96
97 /*****************************************************************************/
98 /* Shared peripherals */
99
100 /*****************************************************************************/
101 /* Peripheral local bus arbitrer */
102 enum {
103 PLB0_BESR = 0x084,
104 PLB0_BEAR = 0x086,
105 PLB0_ACR = 0x087,
106 };
107
108 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
109 struct ppc4xx_plb_t {
110 uint32_t acr;
111 uint32_t bear;
112 uint32_t besr;
113 };
114
115 static uint32_t dcr_read_plb (void *opaque, int dcrn)
116 {
117 ppc4xx_plb_t *plb;
118 uint32_t ret;
119
120 plb = opaque;
121 switch (dcrn) {
122 case PLB0_ACR:
123 ret = plb->acr;
124 break;
125 case PLB0_BEAR:
126 ret = plb->bear;
127 break;
128 case PLB0_BESR:
129 ret = plb->besr;
130 break;
131 default:
132 /* Avoid gcc warning */
133 ret = 0;
134 break;
135 }
136
137 return ret;
138 }
139
140 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
141 {
142 ppc4xx_plb_t *plb;
143
144 plb = opaque;
145 switch (dcrn) {
146 case PLB0_ACR:
147 /* We don't care about the actual parameters written as
148 * we don't manage any priorities on the bus
149 */
150 plb->acr = val & 0xF8000000;
151 break;
152 case PLB0_BEAR:
153 /* Read only */
154 break;
155 case PLB0_BESR:
156 /* Write-clear */
157 plb->besr &= ~val;
158 break;
159 }
160 }
161
162 static void ppc4xx_plb_reset (void *opaque)
163 {
164 ppc4xx_plb_t *plb;
165
166 plb = opaque;
167 plb->acr = 0x00000000;
168 plb->bear = 0x00000000;
169 plb->besr = 0x00000000;
170 }
171
172 static void ppc4xx_plb_init(CPUPPCState *env)
173 {
174 ppc4xx_plb_t *plb;
175
176 plb = g_malloc0(sizeof(ppc4xx_plb_t));
177 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
178 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
179 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
180 qemu_register_reset(ppc4xx_plb_reset, plb);
181 }
182
183 /*****************************************************************************/
184 /* PLB to OPB bridge */
185 enum {
186 POB0_BESR0 = 0x0A0,
187 POB0_BESR1 = 0x0A2,
188 POB0_BEAR = 0x0A4,
189 };
190
191 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
192 struct ppc4xx_pob_t {
193 uint32_t bear;
194 uint32_t besr0;
195 uint32_t besr1;
196 };
197
198 static uint32_t dcr_read_pob (void *opaque, int dcrn)
199 {
200 ppc4xx_pob_t *pob;
201 uint32_t ret;
202
203 pob = opaque;
204 switch (dcrn) {
205 case POB0_BEAR:
206 ret = pob->bear;
207 break;
208 case POB0_BESR0:
209 ret = pob->besr0;
210 break;
211 case POB0_BESR1:
212 ret = pob->besr1;
213 break;
214 default:
215 /* Avoid gcc warning */
216 ret = 0;
217 break;
218 }
219
220 return ret;
221 }
222
223 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
224 {
225 ppc4xx_pob_t *pob;
226
227 pob = opaque;
228 switch (dcrn) {
229 case POB0_BEAR:
230 /* Read only */
231 break;
232 case POB0_BESR0:
233 /* Write-clear */
234 pob->besr0 &= ~val;
235 break;
236 case POB0_BESR1:
237 /* Write-clear */
238 pob->besr1 &= ~val;
239 break;
240 }
241 }
242
243 static void ppc4xx_pob_reset (void *opaque)
244 {
245 ppc4xx_pob_t *pob;
246
247 pob = opaque;
248 /* No error */
249 pob->bear = 0x00000000;
250 pob->besr0 = 0x0000000;
251 pob->besr1 = 0x0000000;
252 }
253
254 static void ppc4xx_pob_init(CPUPPCState *env)
255 {
256 ppc4xx_pob_t *pob;
257
258 pob = g_malloc0(sizeof(ppc4xx_pob_t));
259 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
260 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
261 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
262 qemu_register_reset(ppc4xx_pob_reset, pob);
263 }
264
265 /*****************************************************************************/
266 /* OPB arbitrer */
267 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
268 struct ppc4xx_opba_t {
269 MemoryRegion io;
270 uint8_t cr;
271 uint8_t pr;
272 };
273
274 static uint32_t opba_readb (void *opaque, hwaddr addr)
275 {
276 ppc4xx_opba_t *opba;
277 uint32_t ret;
278
279 #ifdef DEBUG_OPBA
280 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
281 #endif
282 opba = opaque;
283 switch (addr) {
284 case 0x00:
285 ret = opba->cr;
286 break;
287 case 0x01:
288 ret = opba->pr;
289 break;
290 default:
291 ret = 0x00;
292 break;
293 }
294
295 return ret;
296 }
297
298 static void opba_writeb (void *opaque,
299 hwaddr addr, uint32_t value)
300 {
301 ppc4xx_opba_t *opba;
302
303 #ifdef DEBUG_OPBA
304 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
305 value);
306 #endif
307 opba = opaque;
308 switch (addr) {
309 case 0x00:
310 opba->cr = value & 0xF8;
311 break;
312 case 0x01:
313 opba->pr = value & 0xFF;
314 break;
315 default:
316 break;
317 }
318 }
319
320 static uint32_t opba_readw (void *opaque, hwaddr addr)
321 {
322 uint32_t ret;
323
324 #ifdef DEBUG_OPBA
325 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
326 #endif
327 ret = opba_readb(opaque, addr) << 8;
328 ret |= opba_readb(opaque, addr + 1);
329
330 return ret;
331 }
332
333 static void opba_writew (void *opaque,
334 hwaddr addr, uint32_t value)
335 {
336 #ifdef DEBUG_OPBA
337 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
338 value);
339 #endif
340 opba_writeb(opaque, addr, value >> 8);
341 opba_writeb(opaque, addr + 1, value);
342 }
343
344 static uint32_t opba_readl (void *opaque, hwaddr addr)
345 {
346 uint32_t ret;
347
348 #ifdef DEBUG_OPBA
349 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
350 #endif
351 ret = opba_readb(opaque, addr) << 24;
352 ret |= opba_readb(opaque, addr + 1) << 16;
353
354 return ret;
355 }
356
357 static void opba_writel (void *opaque,
358 hwaddr addr, uint32_t value)
359 {
360 #ifdef DEBUG_OPBA
361 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
362 value);
363 #endif
364 opba_writeb(opaque, addr, value >> 24);
365 opba_writeb(opaque, addr + 1, value >> 16);
366 }
367
368 static const MemoryRegionOps opba_ops = {
369 .old_mmio = {
370 .read = { opba_readb, opba_readw, opba_readl, },
371 .write = { opba_writeb, opba_writew, opba_writel, },
372 },
373 .endianness = DEVICE_NATIVE_ENDIAN,
374 };
375
376 static void ppc4xx_opba_reset (void *opaque)
377 {
378 ppc4xx_opba_t *opba;
379
380 opba = opaque;
381 opba->cr = 0x00; /* No dynamic priorities - park disabled */
382 opba->pr = 0x11;
383 }
384
385 static void ppc4xx_opba_init(hwaddr base)
386 {
387 ppc4xx_opba_t *opba;
388
389 opba = g_malloc0(sizeof(ppc4xx_opba_t));
390 #ifdef DEBUG_OPBA
391 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
392 #endif
393 memory_region_init_io(&opba->io, &opba_ops, opba, "opba", 0x002);
394 memory_region_add_subregion(get_system_memory(), base, &opba->io);
395 qemu_register_reset(ppc4xx_opba_reset, opba);
396 }
397
398 /*****************************************************************************/
399 /* Code decompression controller */
400 /* XXX: TODO */
401
402 /*****************************************************************************/
403 /* Peripheral controller */
404 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
405 struct ppc4xx_ebc_t {
406 uint32_t addr;
407 uint32_t bcr[8];
408 uint32_t bap[8];
409 uint32_t bear;
410 uint32_t besr0;
411 uint32_t besr1;
412 uint32_t cfg;
413 };
414
415 enum {
416 EBC0_CFGADDR = 0x012,
417 EBC0_CFGDATA = 0x013,
418 };
419
420 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
421 {
422 ppc4xx_ebc_t *ebc;
423 uint32_t ret;
424
425 ebc = opaque;
426 switch (dcrn) {
427 case EBC0_CFGADDR:
428 ret = ebc->addr;
429 break;
430 case EBC0_CFGDATA:
431 switch (ebc->addr) {
432 case 0x00: /* B0CR */
433 ret = ebc->bcr[0];
434 break;
435 case 0x01: /* B1CR */
436 ret = ebc->bcr[1];
437 break;
438 case 0x02: /* B2CR */
439 ret = ebc->bcr[2];
440 break;
441 case 0x03: /* B3CR */
442 ret = ebc->bcr[3];
443 break;
444 case 0x04: /* B4CR */
445 ret = ebc->bcr[4];
446 break;
447 case 0x05: /* B5CR */
448 ret = ebc->bcr[5];
449 break;
450 case 0x06: /* B6CR */
451 ret = ebc->bcr[6];
452 break;
453 case 0x07: /* B7CR */
454 ret = ebc->bcr[7];
455 break;
456 case 0x10: /* B0AP */
457 ret = ebc->bap[0];
458 break;
459 case 0x11: /* B1AP */
460 ret = ebc->bap[1];
461 break;
462 case 0x12: /* B2AP */
463 ret = ebc->bap[2];
464 break;
465 case 0x13: /* B3AP */
466 ret = ebc->bap[3];
467 break;
468 case 0x14: /* B4AP */
469 ret = ebc->bap[4];
470 break;
471 case 0x15: /* B5AP */
472 ret = ebc->bap[5];
473 break;
474 case 0x16: /* B6AP */
475 ret = ebc->bap[6];
476 break;
477 case 0x17: /* B7AP */
478 ret = ebc->bap[7];
479 break;
480 case 0x20: /* BEAR */
481 ret = ebc->bear;
482 break;
483 case 0x21: /* BESR0 */
484 ret = ebc->besr0;
485 break;
486 case 0x22: /* BESR1 */
487 ret = ebc->besr1;
488 break;
489 case 0x23: /* CFG */
490 ret = ebc->cfg;
491 break;
492 default:
493 ret = 0x00000000;
494 break;
495 }
496 break;
497 default:
498 ret = 0x00000000;
499 break;
500 }
501
502 return ret;
503 }
504
505 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
506 {
507 ppc4xx_ebc_t *ebc;
508
509 ebc = opaque;
510 switch (dcrn) {
511 case EBC0_CFGADDR:
512 ebc->addr = val;
513 break;
514 case EBC0_CFGDATA:
515 switch (ebc->addr) {
516 case 0x00: /* B0CR */
517 break;
518 case 0x01: /* B1CR */
519 break;
520 case 0x02: /* B2CR */
521 break;
522 case 0x03: /* B3CR */
523 break;
524 case 0x04: /* B4CR */
525 break;
526 case 0x05: /* B5CR */
527 break;
528 case 0x06: /* B6CR */
529 break;
530 case 0x07: /* B7CR */
531 break;
532 case 0x10: /* B0AP */
533 break;
534 case 0x11: /* B1AP */
535 break;
536 case 0x12: /* B2AP */
537 break;
538 case 0x13: /* B3AP */
539 break;
540 case 0x14: /* B4AP */
541 break;
542 case 0x15: /* B5AP */
543 break;
544 case 0x16: /* B6AP */
545 break;
546 case 0x17: /* B7AP */
547 break;
548 case 0x20: /* BEAR */
549 break;
550 case 0x21: /* BESR0 */
551 break;
552 case 0x22: /* BESR1 */
553 break;
554 case 0x23: /* CFG */
555 break;
556 default:
557 break;
558 }
559 break;
560 default:
561 break;
562 }
563 }
564
565 static void ebc_reset (void *opaque)
566 {
567 ppc4xx_ebc_t *ebc;
568 int i;
569
570 ebc = opaque;
571 ebc->addr = 0x00000000;
572 ebc->bap[0] = 0x7F8FFE80;
573 ebc->bcr[0] = 0xFFE28000;
574 for (i = 0; i < 8; i++) {
575 ebc->bap[i] = 0x00000000;
576 ebc->bcr[i] = 0x00000000;
577 }
578 ebc->besr0 = 0x00000000;
579 ebc->besr1 = 0x00000000;
580 ebc->cfg = 0x80400000;
581 }
582
583 static void ppc405_ebc_init(CPUPPCState *env)
584 {
585 ppc4xx_ebc_t *ebc;
586
587 ebc = g_malloc0(sizeof(ppc4xx_ebc_t));
588 qemu_register_reset(&ebc_reset, ebc);
589 ppc_dcr_register(env, EBC0_CFGADDR,
590 ebc, &dcr_read_ebc, &dcr_write_ebc);
591 ppc_dcr_register(env, EBC0_CFGDATA,
592 ebc, &dcr_read_ebc, &dcr_write_ebc);
593 }
594
595 /*****************************************************************************/
596 /* DMA controller */
597 enum {
598 DMA0_CR0 = 0x100,
599 DMA0_CT0 = 0x101,
600 DMA0_DA0 = 0x102,
601 DMA0_SA0 = 0x103,
602 DMA0_SG0 = 0x104,
603 DMA0_CR1 = 0x108,
604 DMA0_CT1 = 0x109,
605 DMA0_DA1 = 0x10A,
606 DMA0_SA1 = 0x10B,
607 DMA0_SG1 = 0x10C,
608 DMA0_CR2 = 0x110,
609 DMA0_CT2 = 0x111,
610 DMA0_DA2 = 0x112,
611 DMA0_SA2 = 0x113,
612 DMA0_SG2 = 0x114,
613 DMA0_CR3 = 0x118,
614 DMA0_CT3 = 0x119,
615 DMA0_DA3 = 0x11A,
616 DMA0_SA3 = 0x11B,
617 DMA0_SG3 = 0x11C,
618 DMA0_SR = 0x120,
619 DMA0_SGC = 0x123,
620 DMA0_SLP = 0x125,
621 DMA0_POL = 0x126,
622 };
623
624 typedef struct ppc405_dma_t ppc405_dma_t;
625 struct ppc405_dma_t {
626 qemu_irq irqs[4];
627 uint32_t cr[4];
628 uint32_t ct[4];
629 uint32_t da[4];
630 uint32_t sa[4];
631 uint32_t sg[4];
632 uint32_t sr;
633 uint32_t sgc;
634 uint32_t slp;
635 uint32_t pol;
636 };
637
638 static uint32_t dcr_read_dma (void *opaque, int dcrn)
639 {
640 return 0;
641 }
642
643 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
644 {
645 }
646
647 static void ppc405_dma_reset (void *opaque)
648 {
649 ppc405_dma_t *dma;
650 int i;
651
652 dma = opaque;
653 for (i = 0; i < 4; i++) {
654 dma->cr[i] = 0x00000000;
655 dma->ct[i] = 0x00000000;
656 dma->da[i] = 0x00000000;
657 dma->sa[i] = 0x00000000;
658 dma->sg[i] = 0x00000000;
659 }
660 dma->sr = 0x00000000;
661 dma->sgc = 0x00000000;
662 dma->slp = 0x7C000000;
663 dma->pol = 0x00000000;
664 }
665
666 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
667 {
668 ppc405_dma_t *dma;
669
670 dma = g_malloc0(sizeof(ppc405_dma_t));
671 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
672 qemu_register_reset(&ppc405_dma_reset, dma);
673 ppc_dcr_register(env, DMA0_CR0,
674 dma, &dcr_read_dma, &dcr_write_dma);
675 ppc_dcr_register(env, DMA0_CT0,
676 dma, &dcr_read_dma, &dcr_write_dma);
677 ppc_dcr_register(env, DMA0_DA0,
678 dma, &dcr_read_dma, &dcr_write_dma);
679 ppc_dcr_register(env, DMA0_SA0,
680 dma, &dcr_read_dma, &dcr_write_dma);
681 ppc_dcr_register(env, DMA0_SG0,
682 dma, &dcr_read_dma, &dcr_write_dma);
683 ppc_dcr_register(env, DMA0_CR1,
684 dma, &dcr_read_dma, &dcr_write_dma);
685 ppc_dcr_register(env, DMA0_CT1,
686 dma, &dcr_read_dma, &dcr_write_dma);
687 ppc_dcr_register(env, DMA0_DA1,
688 dma, &dcr_read_dma, &dcr_write_dma);
689 ppc_dcr_register(env, DMA0_SA1,
690 dma, &dcr_read_dma, &dcr_write_dma);
691 ppc_dcr_register(env, DMA0_SG1,
692 dma, &dcr_read_dma, &dcr_write_dma);
693 ppc_dcr_register(env, DMA0_CR2,
694 dma, &dcr_read_dma, &dcr_write_dma);
695 ppc_dcr_register(env, DMA0_CT2,
696 dma, &dcr_read_dma, &dcr_write_dma);
697 ppc_dcr_register(env, DMA0_DA2,
698 dma, &dcr_read_dma, &dcr_write_dma);
699 ppc_dcr_register(env, DMA0_SA2,
700 dma, &dcr_read_dma, &dcr_write_dma);
701 ppc_dcr_register(env, DMA0_SG2,
702 dma, &dcr_read_dma, &dcr_write_dma);
703 ppc_dcr_register(env, DMA0_CR3,
704 dma, &dcr_read_dma, &dcr_write_dma);
705 ppc_dcr_register(env, DMA0_CT3,
706 dma, &dcr_read_dma, &dcr_write_dma);
707 ppc_dcr_register(env, DMA0_DA3,
708 dma, &dcr_read_dma, &dcr_write_dma);
709 ppc_dcr_register(env, DMA0_SA3,
710 dma, &dcr_read_dma, &dcr_write_dma);
711 ppc_dcr_register(env, DMA0_SG3,
712 dma, &dcr_read_dma, &dcr_write_dma);
713 ppc_dcr_register(env, DMA0_SR,
714 dma, &dcr_read_dma, &dcr_write_dma);
715 ppc_dcr_register(env, DMA0_SGC,
716 dma, &dcr_read_dma, &dcr_write_dma);
717 ppc_dcr_register(env, DMA0_SLP,
718 dma, &dcr_read_dma, &dcr_write_dma);
719 ppc_dcr_register(env, DMA0_POL,
720 dma, &dcr_read_dma, &dcr_write_dma);
721 }
722
723 /*****************************************************************************/
724 /* GPIO */
725 typedef struct ppc405_gpio_t ppc405_gpio_t;
726 struct ppc405_gpio_t {
727 MemoryRegion io;
728 uint32_t or;
729 uint32_t tcr;
730 uint32_t osrh;
731 uint32_t osrl;
732 uint32_t tsrh;
733 uint32_t tsrl;
734 uint32_t odr;
735 uint32_t ir;
736 uint32_t rr1;
737 uint32_t isr1h;
738 uint32_t isr1l;
739 };
740
741 static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)
742 {
743 #ifdef DEBUG_GPIO
744 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
745 #endif
746
747 return 0;
748 }
749
750 static void ppc405_gpio_writeb (void *opaque,
751 hwaddr addr, uint32_t value)
752 {
753 #ifdef DEBUG_GPIO
754 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
755 value);
756 #endif
757 }
758
759 static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)
760 {
761 #ifdef DEBUG_GPIO
762 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
763 #endif
764
765 return 0;
766 }
767
768 static void ppc405_gpio_writew (void *opaque,
769 hwaddr addr, uint32_t value)
770 {
771 #ifdef DEBUG_GPIO
772 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
773 value);
774 #endif
775 }
776
777 static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)
778 {
779 #ifdef DEBUG_GPIO
780 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
781 #endif
782
783 return 0;
784 }
785
786 static void ppc405_gpio_writel (void *opaque,
787 hwaddr addr, uint32_t value)
788 {
789 #ifdef DEBUG_GPIO
790 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
791 value);
792 #endif
793 }
794
795 static const MemoryRegionOps ppc405_gpio_ops = {
796 .old_mmio = {
797 .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
798 .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
799 },
800 .endianness = DEVICE_NATIVE_ENDIAN,
801 };
802
803 static void ppc405_gpio_reset (void *opaque)
804 {
805 }
806
807 static void ppc405_gpio_init(hwaddr base)
808 {
809 ppc405_gpio_t *gpio;
810
811 gpio = g_malloc0(sizeof(ppc405_gpio_t));
812 #ifdef DEBUG_GPIO
813 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
814 #endif
815 memory_region_init_io(&gpio->io, &ppc405_gpio_ops, gpio, "pgio", 0x038);
816 memory_region_add_subregion(get_system_memory(), base, &gpio->io);
817 qemu_register_reset(&ppc405_gpio_reset, gpio);
818 }
819
820 /*****************************************************************************/
821 /* On Chip Memory */
822 enum {
823 OCM0_ISARC = 0x018,
824 OCM0_ISACNTL = 0x019,
825 OCM0_DSARC = 0x01A,
826 OCM0_DSACNTL = 0x01B,
827 };
828
829 typedef struct ppc405_ocm_t ppc405_ocm_t;
830 struct ppc405_ocm_t {
831 MemoryRegion ram;
832 MemoryRegion isarc_ram;
833 MemoryRegion dsarc_ram;
834 uint32_t isarc;
835 uint32_t isacntl;
836 uint32_t dsarc;
837 uint32_t dsacntl;
838 };
839
840 static void ocm_update_mappings (ppc405_ocm_t *ocm,
841 uint32_t isarc, uint32_t isacntl,
842 uint32_t dsarc, uint32_t dsacntl)
843 {
844 #ifdef DEBUG_OCM
845 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
846 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
847 " (%08" PRIx32 " %08" PRIx32 ")\n",
848 isarc, isacntl, dsarc, dsacntl,
849 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
850 #endif
851 if (ocm->isarc != isarc ||
852 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
853 if (ocm->isacntl & 0x80000000) {
854 /* Unmap previously assigned memory region */
855 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
856 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
857 }
858 if (isacntl & 0x80000000) {
859 /* Map new instruction memory region */
860 #ifdef DEBUG_OCM
861 printf("OCM map ISA %08" PRIx32 "\n", isarc);
862 #endif
863 memory_region_add_subregion(get_system_memory(), isarc,
864 &ocm->isarc_ram);
865 }
866 }
867 if (ocm->dsarc != dsarc ||
868 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
869 if (ocm->dsacntl & 0x80000000) {
870 /* Beware not to unmap the region we just mapped */
871 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
872 /* Unmap previously assigned memory region */
873 #ifdef DEBUG_OCM
874 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
875 #endif
876 memory_region_del_subregion(get_system_memory(),
877 &ocm->dsarc_ram);
878 }
879 }
880 if (dsacntl & 0x80000000) {
881 /* Beware not to remap the region we just mapped */
882 if (!(isacntl & 0x80000000) || dsarc != isarc) {
883 /* Map new data memory region */
884 #ifdef DEBUG_OCM
885 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
886 #endif
887 memory_region_add_subregion(get_system_memory(), dsarc,
888 &ocm->dsarc_ram);
889 }
890 }
891 }
892 }
893
894 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
895 {
896 ppc405_ocm_t *ocm;
897 uint32_t ret;
898
899 ocm = opaque;
900 switch (dcrn) {
901 case OCM0_ISARC:
902 ret = ocm->isarc;
903 break;
904 case OCM0_ISACNTL:
905 ret = ocm->isacntl;
906 break;
907 case OCM0_DSARC:
908 ret = ocm->dsarc;
909 break;
910 case OCM0_DSACNTL:
911 ret = ocm->dsacntl;
912 break;
913 default:
914 ret = 0;
915 break;
916 }
917
918 return ret;
919 }
920
921 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
922 {
923 ppc405_ocm_t *ocm;
924 uint32_t isarc, dsarc, isacntl, dsacntl;
925
926 ocm = opaque;
927 isarc = ocm->isarc;
928 dsarc = ocm->dsarc;
929 isacntl = ocm->isacntl;
930 dsacntl = ocm->dsacntl;
931 switch (dcrn) {
932 case OCM0_ISARC:
933 isarc = val & 0xFC000000;
934 break;
935 case OCM0_ISACNTL:
936 isacntl = val & 0xC0000000;
937 break;
938 case OCM0_DSARC:
939 isarc = val & 0xFC000000;
940 break;
941 case OCM0_DSACNTL:
942 isacntl = val & 0xC0000000;
943 break;
944 }
945 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
946 ocm->isarc = isarc;
947 ocm->dsarc = dsarc;
948 ocm->isacntl = isacntl;
949 ocm->dsacntl = dsacntl;
950 }
951
952 static void ocm_reset (void *opaque)
953 {
954 ppc405_ocm_t *ocm;
955 uint32_t isarc, dsarc, isacntl, dsacntl;
956
957 ocm = opaque;
958 isarc = 0x00000000;
959 isacntl = 0x00000000;
960 dsarc = 0x00000000;
961 dsacntl = 0x00000000;
962 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
963 ocm->isarc = isarc;
964 ocm->dsarc = dsarc;
965 ocm->isacntl = isacntl;
966 ocm->dsacntl = dsacntl;
967 }
968
969 static void ppc405_ocm_init(CPUPPCState *env)
970 {
971 ppc405_ocm_t *ocm;
972
973 ocm = g_malloc0(sizeof(ppc405_ocm_t));
974 /* XXX: Size is 4096 or 0x04000000 */
975 memory_region_init_ram(&ocm->isarc_ram, "ppc405.ocm", 4096);
976 vmstate_register_ram_global(&ocm->isarc_ram);
977 memory_region_init_alias(&ocm->dsarc_ram, "ppc405.dsarc", &ocm->isarc_ram,
978 0, 4096);
979 qemu_register_reset(&ocm_reset, ocm);
980 ppc_dcr_register(env, OCM0_ISARC,
981 ocm, &dcr_read_ocm, &dcr_write_ocm);
982 ppc_dcr_register(env, OCM0_ISACNTL,
983 ocm, &dcr_read_ocm, &dcr_write_ocm);
984 ppc_dcr_register(env, OCM0_DSARC,
985 ocm, &dcr_read_ocm, &dcr_write_ocm);
986 ppc_dcr_register(env, OCM0_DSACNTL,
987 ocm, &dcr_read_ocm, &dcr_write_ocm);
988 }
989
990 /*****************************************************************************/
991 /* I2C controller */
992 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
993 struct ppc4xx_i2c_t {
994 qemu_irq irq;
995 MemoryRegion iomem;
996 uint8_t mdata;
997 uint8_t lmadr;
998 uint8_t hmadr;
999 uint8_t cntl;
1000 uint8_t mdcntl;
1001 uint8_t sts;
1002 uint8_t extsts;
1003 uint8_t sdata;
1004 uint8_t lsadr;
1005 uint8_t hsadr;
1006 uint8_t clkdiv;
1007 uint8_t intrmsk;
1008 uint8_t xfrcnt;
1009 uint8_t xtcntlss;
1010 uint8_t directcntl;
1011 };
1012
1013 static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr)
1014 {
1015 ppc4xx_i2c_t *i2c;
1016 uint32_t ret;
1017
1018 #ifdef DEBUG_I2C
1019 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1020 #endif
1021 i2c = opaque;
1022 switch (addr) {
1023 case 0x00:
1024 // i2c_readbyte(&i2c->mdata);
1025 ret = i2c->mdata;
1026 break;
1027 case 0x02:
1028 ret = i2c->sdata;
1029 break;
1030 case 0x04:
1031 ret = i2c->lmadr;
1032 break;
1033 case 0x05:
1034 ret = i2c->hmadr;
1035 break;
1036 case 0x06:
1037 ret = i2c->cntl;
1038 break;
1039 case 0x07:
1040 ret = i2c->mdcntl;
1041 break;
1042 case 0x08:
1043 ret = i2c->sts;
1044 break;
1045 case 0x09:
1046 ret = i2c->extsts;
1047 break;
1048 case 0x0A:
1049 ret = i2c->lsadr;
1050 break;
1051 case 0x0B:
1052 ret = i2c->hsadr;
1053 break;
1054 case 0x0C:
1055 ret = i2c->clkdiv;
1056 break;
1057 case 0x0D:
1058 ret = i2c->intrmsk;
1059 break;
1060 case 0x0E:
1061 ret = i2c->xfrcnt;
1062 break;
1063 case 0x0F:
1064 ret = i2c->xtcntlss;
1065 break;
1066 case 0x10:
1067 ret = i2c->directcntl;
1068 break;
1069 default:
1070 ret = 0x00;
1071 break;
1072 }
1073 #ifdef DEBUG_I2C
1074 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
1075 #endif
1076
1077 return ret;
1078 }
1079
1080 static void ppc4xx_i2c_writeb (void *opaque,
1081 hwaddr addr, uint32_t value)
1082 {
1083 ppc4xx_i2c_t *i2c;
1084
1085 #ifdef DEBUG_I2C
1086 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1087 value);
1088 #endif
1089 i2c = opaque;
1090 switch (addr) {
1091 case 0x00:
1092 i2c->mdata = value;
1093 // i2c_sendbyte(&i2c->mdata);
1094 break;
1095 case 0x02:
1096 i2c->sdata = value;
1097 break;
1098 case 0x04:
1099 i2c->lmadr = value;
1100 break;
1101 case 0x05:
1102 i2c->hmadr = value;
1103 break;
1104 case 0x06:
1105 i2c->cntl = value;
1106 break;
1107 case 0x07:
1108 i2c->mdcntl = value & 0xDF;
1109 break;
1110 case 0x08:
1111 i2c->sts &= ~(value & 0x0A);
1112 break;
1113 case 0x09:
1114 i2c->extsts &= ~(value & 0x8F);
1115 break;
1116 case 0x0A:
1117 i2c->lsadr = value;
1118 break;
1119 case 0x0B:
1120 i2c->hsadr = value;
1121 break;
1122 case 0x0C:
1123 i2c->clkdiv = value;
1124 break;
1125 case 0x0D:
1126 i2c->intrmsk = value;
1127 break;
1128 case 0x0E:
1129 i2c->xfrcnt = value & 0x77;
1130 break;
1131 case 0x0F:
1132 i2c->xtcntlss = value;
1133 break;
1134 case 0x10:
1135 i2c->directcntl = value & 0x7;
1136 break;
1137 }
1138 }
1139
1140 static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr)
1141 {
1142 uint32_t ret;
1143
1144 #ifdef DEBUG_I2C
1145 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1146 #endif
1147 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1148 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1149
1150 return ret;
1151 }
1152
1153 static void ppc4xx_i2c_writew (void *opaque,
1154 hwaddr addr, uint32_t value)
1155 {
1156 #ifdef DEBUG_I2C
1157 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1158 value);
1159 #endif
1160 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1161 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1162 }
1163
1164 static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr)
1165 {
1166 uint32_t ret;
1167
1168 #ifdef DEBUG_I2C
1169 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1170 #endif
1171 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1172 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1173 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1174 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1175
1176 return ret;
1177 }
1178
1179 static void ppc4xx_i2c_writel (void *opaque,
1180 hwaddr addr, uint32_t value)
1181 {
1182 #ifdef DEBUG_I2C
1183 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1184 value);
1185 #endif
1186 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1187 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1188 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1189 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1190 }
1191
1192 static const MemoryRegionOps i2c_ops = {
1193 .old_mmio = {
1194 .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
1195 .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
1196 },
1197 .endianness = DEVICE_NATIVE_ENDIAN,
1198 };
1199
1200 static void ppc4xx_i2c_reset (void *opaque)
1201 {
1202 ppc4xx_i2c_t *i2c;
1203
1204 i2c = opaque;
1205 i2c->mdata = 0x00;
1206 i2c->sdata = 0x00;
1207 i2c->cntl = 0x00;
1208 i2c->mdcntl = 0x00;
1209 i2c->sts = 0x00;
1210 i2c->extsts = 0x00;
1211 i2c->clkdiv = 0x00;
1212 i2c->xfrcnt = 0x00;
1213 i2c->directcntl = 0x0F;
1214 }
1215
1216 static void ppc405_i2c_init(hwaddr base, qemu_irq irq)
1217 {
1218 ppc4xx_i2c_t *i2c;
1219
1220 i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
1221 i2c->irq = irq;
1222 #ifdef DEBUG_I2C
1223 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1224 #endif
1225 memory_region_init_io(&i2c->iomem, &i2c_ops, i2c, "i2c", 0x011);
1226 memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
1227 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1228 }
1229
1230 /*****************************************************************************/
1231 /* General purpose timers */
1232 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1233 struct ppc4xx_gpt_t {
1234 MemoryRegion iomem;
1235 int64_t tb_offset;
1236 uint32_t tb_freq;
1237 struct QEMUTimer *timer;
1238 qemu_irq irqs[5];
1239 uint32_t oe;
1240 uint32_t ol;
1241 uint32_t im;
1242 uint32_t is;
1243 uint32_t ie;
1244 uint32_t comp[5];
1245 uint32_t mask[5];
1246 };
1247
1248 static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)
1249 {
1250 #ifdef DEBUG_GPT
1251 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1252 #endif
1253 /* XXX: generate a bus fault */
1254 return -1;
1255 }
1256
1257 static void ppc4xx_gpt_writeb (void *opaque,
1258 hwaddr addr, uint32_t value)
1259 {
1260 #ifdef DEBUG_I2C
1261 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1262 value);
1263 #endif
1264 /* XXX: generate a bus fault */
1265 }
1266
1267 static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)
1268 {
1269 #ifdef DEBUG_GPT
1270 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1271 #endif
1272 /* XXX: generate a bus fault */
1273 return -1;
1274 }
1275
1276 static void ppc4xx_gpt_writew (void *opaque,
1277 hwaddr addr, uint32_t value)
1278 {
1279 #ifdef DEBUG_I2C
1280 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1281 value);
1282 #endif
1283 /* XXX: generate a bus fault */
1284 }
1285
1286 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1287 {
1288 /* XXX: TODO */
1289 return 0;
1290 }
1291
1292 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1293 {
1294 /* XXX: TODO */
1295 }
1296
1297 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1298 {
1299 uint32_t mask;
1300 int i;
1301
1302 mask = 0x80000000;
1303 for (i = 0; i < 5; i++) {
1304 if (gpt->oe & mask) {
1305 /* Output is enabled */
1306 if (ppc4xx_gpt_compare(gpt, i)) {
1307 /* Comparison is OK */
1308 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1309 } else {
1310 /* Comparison is KO */
1311 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1312 }
1313 }
1314 mask = mask >> 1;
1315 }
1316 }
1317
1318 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1319 {
1320 uint32_t mask;
1321 int i;
1322
1323 mask = 0x00008000;
1324 for (i = 0; i < 5; i++) {
1325 if (gpt->is & gpt->im & mask)
1326 qemu_irq_raise(gpt->irqs[i]);
1327 else
1328 qemu_irq_lower(gpt->irqs[i]);
1329 mask = mask >> 1;
1330 }
1331 }
1332
1333 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1334 {
1335 /* XXX: TODO */
1336 }
1337
1338 static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
1339 {
1340 ppc4xx_gpt_t *gpt;
1341 uint32_t ret;
1342 int idx;
1343
1344 #ifdef DEBUG_GPT
1345 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1346 #endif
1347 gpt = opaque;
1348 switch (addr) {
1349 case 0x00:
1350 /* Time base counter */
1351 ret = muldiv64(qemu_get_clock_ns(vm_clock) + gpt->tb_offset,
1352 gpt->tb_freq, get_ticks_per_sec());
1353 break;
1354 case 0x10:
1355 /* Output enable */
1356 ret = gpt->oe;
1357 break;
1358 case 0x14:
1359 /* Output level */
1360 ret = gpt->ol;
1361 break;
1362 case 0x18:
1363 /* Interrupt mask */
1364 ret = gpt->im;
1365 break;
1366 case 0x1C:
1367 case 0x20:
1368 /* Interrupt status */
1369 ret = gpt->is;
1370 break;
1371 case 0x24:
1372 /* Interrupt enable */
1373 ret = gpt->ie;
1374 break;
1375 case 0x80 ... 0x90:
1376 /* Compare timer */
1377 idx = (addr - 0x80) >> 2;
1378 ret = gpt->comp[idx];
1379 break;
1380 case 0xC0 ... 0xD0:
1381 /* Compare mask */
1382 idx = (addr - 0xC0) >> 2;
1383 ret = gpt->mask[idx];
1384 break;
1385 default:
1386 ret = -1;
1387 break;
1388 }
1389
1390 return ret;
1391 }
1392
1393 static void ppc4xx_gpt_writel (void *opaque,
1394 hwaddr addr, uint32_t value)
1395 {
1396 ppc4xx_gpt_t *gpt;
1397 int idx;
1398
1399 #ifdef DEBUG_I2C
1400 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1401 value);
1402 #endif
1403 gpt = opaque;
1404 switch (addr) {
1405 case 0x00:
1406 /* Time base counter */
1407 gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
1408 - qemu_get_clock_ns(vm_clock);
1409 ppc4xx_gpt_compute_timer(gpt);
1410 break;
1411 case 0x10:
1412 /* Output enable */
1413 gpt->oe = value & 0xF8000000;
1414 ppc4xx_gpt_set_outputs(gpt);
1415 break;
1416 case 0x14:
1417 /* Output level */
1418 gpt->ol = value & 0xF8000000;
1419 ppc4xx_gpt_set_outputs(gpt);
1420 break;
1421 case 0x18:
1422 /* Interrupt mask */
1423 gpt->im = value & 0x0000F800;
1424 break;
1425 case 0x1C:
1426 /* Interrupt status set */
1427 gpt->is |= value & 0x0000F800;
1428 ppc4xx_gpt_set_irqs(gpt);
1429 break;
1430 case 0x20:
1431 /* Interrupt status clear */
1432 gpt->is &= ~(value & 0x0000F800);
1433 ppc4xx_gpt_set_irqs(gpt);
1434 break;
1435 case 0x24:
1436 /* Interrupt enable */
1437 gpt->ie = value & 0x0000F800;
1438 ppc4xx_gpt_set_irqs(gpt);
1439 break;
1440 case 0x80 ... 0x90:
1441 /* Compare timer */
1442 idx = (addr - 0x80) >> 2;
1443 gpt->comp[idx] = value & 0xF8000000;
1444 ppc4xx_gpt_compute_timer(gpt);
1445 break;
1446 case 0xC0 ... 0xD0:
1447 /* Compare mask */
1448 idx = (addr - 0xC0) >> 2;
1449 gpt->mask[idx] = value & 0xF8000000;
1450 ppc4xx_gpt_compute_timer(gpt);
1451 break;
1452 }
1453 }
1454
1455 static const MemoryRegionOps gpt_ops = {
1456 .old_mmio = {
1457 .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
1458 .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
1459 },
1460 .endianness = DEVICE_NATIVE_ENDIAN,
1461 };
1462
1463 static void ppc4xx_gpt_cb (void *opaque)
1464 {
1465 ppc4xx_gpt_t *gpt;
1466
1467 gpt = opaque;
1468 ppc4xx_gpt_set_irqs(gpt);
1469 ppc4xx_gpt_set_outputs(gpt);
1470 ppc4xx_gpt_compute_timer(gpt);
1471 }
1472
1473 static void ppc4xx_gpt_reset (void *opaque)
1474 {
1475 ppc4xx_gpt_t *gpt;
1476 int i;
1477
1478 gpt = opaque;
1479 qemu_del_timer(gpt->timer);
1480 gpt->oe = 0x00000000;
1481 gpt->ol = 0x00000000;
1482 gpt->im = 0x00000000;
1483 gpt->is = 0x00000000;
1484 gpt->ie = 0x00000000;
1485 for (i = 0; i < 5; i++) {
1486 gpt->comp[i] = 0x00000000;
1487 gpt->mask[i] = 0x00000000;
1488 }
1489 }
1490
1491 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
1492 {
1493 ppc4xx_gpt_t *gpt;
1494 int i;
1495
1496 gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
1497 for (i = 0; i < 5; i++) {
1498 gpt->irqs[i] = irqs[i];
1499 }
1500 gpt->timer = qemu_new_timer_ns(vm_clock, &ppc4xx_gpt_cb, gpt);
1501 #ifdef DEBUG_GPT
1502 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1503 #endif
1504 memory_region_init_io(&gpt->iomem, &gpt_ops, gpt, "gpt", 0x0d4);
1505 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
1506 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1507 }
1508
1509 /*****************************************************************************/
1510 /* MAL */
1511 enum {
1512 MAL0_CFG = 0x180,
1513 MAL0_ESR = 0x181,
1514 MAL0_IER = 0x182,
1515 MAL0_TXCASR = 0x184,
1516 MAL0_TXCARR = 0x185,
1517 MAL0_TXEOBISR = 0x186,
1518 MAL0_TXDEIR = 0x187,
1519 MAL0_RXCASR = 0x190,
1520 MAL0_RXCARR = 0x191,
1521 MAL0_RXEOBISR = 0x192,
1522 MAL0_RXDEIR = 0x193,
1523 MAL0_TXCTP0R = 0x1A0,
1524 MAL0_TXCTP1R = 0x1A1,
1525 MAL0_TXCTP2R = 0x1A2,
1526 MAL0_TXCTP3R = 0x1A3,
1527 MAL0_RXCTP0R = 0x1C0,
1528 MAL0_RXCTP1R = 0x1C1,
1529 MAL0_RCBS0 = 0x1E0,
1530 MAL0_RCBS1 = 0x1E1,
1531 };
1532
1533 typedef struct ppc40x_mal_t ppc40x_mal_t;
1534 struct ppc40x_mal_t {
1535 qemu_irq irqs[4];
1536 uint32_t cfg;
1537 uint32_t esr;
1538 uint32_t ier;
1539 uint32_t txcasr;
1540 uint32_t txcarr;
1541 uint32_t txeobisr;
1542 uint32_t txdeir;
1543 uint32_t rxcasr;
1544 uint32_t rxcarr;
1545 uint32_t rxeobisr;
1546 uint32_t rxdeir;
1547 uint32_t txctpr[4];
1548 uint32_t rxctpr[2];
1549 uint32_t rcbs[2];
1550 };
1551
1552 static void ppc40x_mal_reset (void *opaque);
1553
1554 static uint32_t dcr_read_mal (void *opaque, int dcrn)
1555 {
1556 ppc40x_mal_t *mal;
1557 uint32_t ret;
1558
1559 mal = opaque;
1560 switch (dcrn) {
1561 case MAL0_CFG:
1562 ret = mal->cfg;
1563 break;
1564 case MAL0_ESR:
1565 ret = mal->esr;
1566 break;
1567 case MAL0_IER:
1568 ret = mal->ier;
1569 break;
1570 case MAL0_TXCASR:
1571 ret = mal->txcasr;
1572 break;
1573 case MAL0_TXCARR:
1574 ret = mal->txcarr;
1575 break;
1576 case MAL0_TXEOBISR:
1577 ret = mal->txeobisr;
1578 break;
1579 case MAL0_TXDEIR:
1580 ret = mal->txdeir;
1581 break;
1582 case MAL0_RXCASR:
1583 ret = mal->rxcasr;
1584 break;
1585 case MAL0_RXCARR:
1586 ret = mal->rxcarr;
1587 break;
1588 case MAL0_RXEOBISR:
1589 ret = mal->rxeobisr;
1590 break;
1591 case MAL0_RXDEIR:
1592 ret = mal->rxdeir;
1593 break;
1594 case MAL0_TXCTP0R:
1595 ret = mal->txctpr[0];
1596 break;
1597 case MAL0_TXCTP1R:
1598 ret = mal->txctpr[1];
1599 break;
1600 case MAL0_TXCTP2R:
1601 ret = mal->txctpr[2];
1602 break;
1603 case MAL0_TXCTP3R:
1604 ret = mal->txctpr[3];
1605 break;
1606 case MAL0_RXCTP0R:
1607 ret = mal->rxctpr[0];
1608 break;
1609 case MAL0_RXCTP1R:
1610 ret = mal->rxctpr[1];
1611 break;
1612 case MAL0_RCBS0:
1613 ret = mal->rcbs[0];
1614 break;
1615 case MAL0_RCBS1:
1616 ret = mal->rcbs[1];
1617 break;
1618 default:
1619 ret = 0;
1620 break;
1621 }
1622
1623 return ret;
1624 }
1625
1626 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
1627 {
1628 ppc40x_mal_t *mal;
1629 int idx;
1630
1631 mal = opaque;
1632 switch (dcrn) {
1633 case MAL0_CFG:
1634 if (val & 0x80000000)
1635 ppc40x_mal_reset(mal);
1636 mal->cfg = val & 0x00FFC087;
1637 break;
1638 case MAL0_ESR:
1639 /* Read/clear */
1640 mal->esr &= ~val;
1641 break;
1642 case MAL0_IER:
1643 mal->ier = val & 0x0000001F;
1644 break;
1645 case MAL0_TXCASR:
1646 mal->txcasr = val & 0xF0000000;
1647 break;
1648 case MAL0_TXCARR:
1649 mal->txcarr = val & 0xF0000000;
1650 break;
1651 case MAL0_TXEOBISR:
1652 /* Read/clear */
1653 mal->txeobisr &= ~val;
1654 break;
1655 case MAL0_TXDEIR:
1656 /* Read/clear */
1657 mal->txdeir &= ~val;
1658 break;
1659 case MAL0_RXCASR:
1660 mal->rxcasr = val & 0xC0000000;
1661 break;
1662 case MAL0_RXCARR:
1663 mal->rxcarr = val & 0xC0000000;
1664 break;
1665 case MAL0_RXEOBISR:
1666 /* Read/clear */
1667 mal->rxeobisr &= ~val;
1668 break;
1669 case MAL0_RXDEIR:
1670 /* Read/clear */
1671 mal->rxdeir &= ~val;
1672 break;
1673 case MAL0_TXCTP0R:
1674 idx = 0;
1675 goto update_tx_ptr;
1676 case MAL0_TXCTP1R:
1677 idx = 1;
1678 goto update_tx_ptr;
1679 case MAL0_TXCTP2R:
1680 idx = 2;
1681 goto update_tx_ptr;
1682 case MAL0_TXCTP3R:
1683 idx = 3;
1684 update_tx_ptr:
1685 mal->txctpr[idx] = val;
1686 break;
1687 case MAL0_RXCTP0R:
1688 idx = 0;
1689 goto update_rx_ptr;
1690 case MAL0_RXCTP1R:
1691 idx = 1;
1692 update_rx_ptr:
1693 mal->rxctpr[idx] = val;
1694 break;
1695 case MAL0_RCBS0:
1696 idx = 0;
1697 goto update_rx_size;
1698 case MAL0_RCBS1:
1699 idx = 1;
1700 update_rx_size:
1701 mal->rcbs[idx] = val & 0x000000FF;
1702 break;
1703 }
1704 }
1705
1706 static void ppc40x_mal_reset (void *opaque)
1707 {
1708 ppc40x_mal_t *mal;
1709
1710 mal = opaque;
1711 mal->cfg = 0x0007C000;
1712 mal->esr = 0x00000000;
1713 mal->ier = 0x00000000;
1714 mal->rxcasr = 0x00000000;
1715 mal->rxdeir = 0x00000000;
1716 mal->rxeobisr = 0x00000000;
1717 mal->txcasr = 0x00000000;
1718 mal->txdeir = 0x00000000;
1719 mal->txeobisr = 0x00000000;
1720 }
1721
1722 static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
1723 {
1724 ppc40x_mal_t *mal;
1725 int i;
1726
1727 mal = g_malloc0(sizeof(ppc40x_mal_t));
1728 for (i = 0; i < 4; i++)
1729 mal->irqs[i] = irqs[i];
1730 qemu_register_reset(&ppc40x_mal_reset, mal);
1731 ppc_dcr_register(env, MAL0_CFG,
1732 mal, &dcr_read_mal, &dcr_write_mal);
1733 ppc_dcr_register(env, MAL0_ESR,
1734 mal, &dcr_read_mal, &dcr_write_mal);
1735 ppc_dcr_register(env, MAL0_IER,
1736 mal, &dcr_read_mal, &dcr_write_mal);
1737 ppc_dcr_register(env, MAL0_TXCASR,
1738 mal, &dcr_read_mal, &dcr_write_mal);
1739 ppc_dcr_register(env, MAL0_TXCARR,
1740 mal, &dcr_read_mal, &dcr_write_mal);
1741 ppc_dcr_register(env, MAL0_TXEOBISR,
1742 mal, &dcr_read_mal, &dcr_write_mal);
1743 ppc_dcr_register(env, MAL0_TXDEIR,
1744 mal, &dcr_read_mal, &dcr_write_mal);
1745 ppc_dcr_register(env, MAL0_RXCASR,
1746 mal, &dcr_read_mal, &dcr_write_mal);
1747 ppc_dcr_register(env, MAL0_RXCARR,
1748 mal, &dcr_read_mal, &dcr_write_mal);
1749 ppc_dcr_register(env, MAL0_RXEOBISR,
1750 mal, &dcr_read_mal, &dcr_write_mal);
1751 ppc_dcr_register(env, MAL0_RXDEIR,
1752 mal, &dcr_read_mal, &dcr_write_mal);
1753 ppc_dcr_register(env, MAL0_TXCTP0R,
1754 mal, &dcr_read_mal, &dcr_write_mal);
1755 ppc_dcr_register(env, MAL0_TXCTP1R,
1756 mal, &dcr_read_mal, &dcr_write_mal);
1757 ppc_dcr_register(env, MAL0_TXCTP2R,
1758 mal, &dcr_read_mal, &dcr_write_mal);
1759 ppc_dcr_register(env, MAL0_TXCTP3R,
1760 mal, &dcr_read_mal, &dcr_write_mal);
1761 ppc_dcr_register(env, MAL0_RXCTP0R,
1762 mal, &dcr_read_mal, &dcr_write_mal);
1763 ppc_dcr_register(env, MAL0_RXCTP1R,
1764 mal, &dcr_read_mal, &dcr_write_mal);
1765 ppc_dcr_register(env, MAL0_RCBS0,
1766 mal, &dcr_read_mal, &dcr_write_mal);
1767 ppc_dcr_register(env, MAL0_RCBS1,
1768 mal, &dcr_read_mal, &dcr_write_mal);
1769 }
1770
1771 /*****************************************************************************/
1772 /* SPR */
1773 void ppc40x_core_reset(PowerPCCPU *cpu)
1774 {
1775 CPUPPCState *env = &cpu->env;
1776 target_ulong dbsr;
1777
1778 printf("Reset PowerPC core\n");
1779 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1780 dbsr = env->spr[SPR_40x_DBSR];
1781 dbsr &= ~0x00000300;
1782 dbsr |= 0x00000100;
1783 env->spr[SPR_40x_DBSR] = dbsr;
1784 }
1785
1786 void ppc40x_chip_reset(PowerPCCPU *cpu)
1787 {
1788 CPUPPCState *env = &cpu->env;
1789 target_ulong dbsr;
1790
1791 printf("Reset PowerPC chip\n");
1792 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1793 /* XXX: TODO reset all internal peripherals */
1794 dbsr = env->spr[SPR_40x_DBSR];
1795 dbsr &= ~0x00000300;
1796 dbsr |= 0x00000200;
1797 env->spr[SPR_40x_DBSR] = dbsr;
1798 }
1799
1800 void ppc40x_system_reset(PowerPCCPU *cpu)
1801 {
1802 printf("Reset PowerPC system\n");
1803 qemu_system_reset_request();
1804 }
1805
1806 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
1807 {
1808 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1809
1810 switch ((val >> 28) & 0x3) {
1811 case 0x0:
1812 /* No action */
1813 break;
1814 case 0x1:
1815 /* Core reset */
1816 ppc40x_core_reset(cpu);
1817 break;
1818 case 0x2:
1819 /* Chip reset */
1820 ppc40x_chip_reset(cpu);
1821 break;
1822 case 0x3:
1823 /* System reset */
1824 ppc40x_system_reset(cpu);
1825 break;
1826 }
1827 }
1828
1829 /*****************************************************************************/
1830 /* PowerPC 405CR */
1831 enum {
1832 PPC405CR_CPC0_PLLMR = 0x0B0,
1833 PPC405CR_CPC0_CR0 = 0x0B1,
1834 PPC405CR_CPC0_CR1 = 0x0B2,
1835 PPC405CR_CPC0_PSR = 0x0B4,
1836 PPC405CR_CPC0_JTAGID = 0x0B5,
1837 PPC405CR_CPC0_ER = 0x0B9,
1838 PPC405CR_CPC0_FR = 0x0BA,
1839 PPC405CR_CPC0_SR = 0x0BB,
1840 };
1841
1842 enum {
1843 PPC405CR_CPU_CLK = 0,
1844 PPC405CR_TMR_CLK = 1,
1845 PPC405CR_PLB_CLK = 2,
1846 PPC405CR_SDRAM_CLK = 3,
1847 PPC405CR_OPB_CLK = 4,
1848 PPC405CR_EXT_CLK = 5,
1849 PPC405CR_UART_CLK = 6,
1850 PPC405CR_CLK_NB = 7,
1851 };
1852
1853 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1854 struct ppc405cr_cpc_t {
1855 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1856 uint32_t sysclk;
1857 uint32_t psr;
1858 uint32_t cr0;
1859 uint32_t cr1;
1860 uint32_t jtagid;
1861 uint32_t pllmr;
1862 uint32_t er;
1863 uint32_t fr;
1864 };
1865
1866 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1867 {
1868 uint64_t VCO_out, PLL_out;
1869 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1870 int M, D0, D1, D2;
1871
1872 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1873 if (cpc->pllmr & 0x80000000) {
1874 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1875 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1876 M = D0 * D1 * D2;
1877 VCO_out = cpc->sysclk * M;
1878 if (VCO_out < 400000000 || VCO_out > 800000000) {
1879 /* PLL cannot lock */
1880 cpc->pllmr &= ~0x80000000;
1881 goto bypass_pll;
1882 }
1883 PLL_out = VCO_out / D2;
1884 } else {
1885 /* Bypass PLL */
1886 bypass_pll:
1887 M = D0;
1888 PLL_out = cpc->sysclk * M;
1889 }
1890 CPU_clk = PLL_out;
1891 if (cpc->cr1 & 0x00800000)
1892 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1893 else
1894 TMR_clk = CPU_clk;
1895 PLB_clk = CPU_clk / D0;
1896 SDRAM_clk = PLB_clk;
1897 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1898 OPB_clk = PLB_clk / D0;
1899 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1900 EXT_clk = PLB_clk / D0;
1901 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1902 UART_clk = CPU_clk / D0;
1903 /* Setup CPU clocks */
1904 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1905 /* Setup time-base clock */
1906 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1907 /* Setup PLB clock */
1908 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1909 /* Setup SDRAM clock */
1910 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1911 /* Setup OPB clock */
1912 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1913 /* Setup external clock */
1914 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1915 /* Setup UART clock */
1916 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1917 }
1918
1919 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1920 {
1921 ppc405cr_cpc_t *cpc;
1922 uint32_t ret;
1923
1924 cpc = opaque;
1925 switch (dcrn) {
1926 case PPC405CR_CPC0_PLLMR:
1927 ret = cpc->pllmr;
1928 break;
1929 case PPC405CR_CPC0_CR0:
1930 ret = cpc->cr0;
1931 break;
1932 case PPC405CR_CPC0_CR1:
1933 ret = cpc->cr1;
1934 break;
1935 case PPC405CR_CPC0_PSR:
1936 ret = cpc->psr;
1937 break;
1938 case PPC405CR_CPC0_JTAGID:
1939 ret = cpc->jtagid;
1940 break;
1941 case PPC405CR_CPC0_ER:
1942 ret = cpc->er;
1943 break;
1944 case PPC405CR_CPC0_FR:
1945 ret = cpc->fr;
1946 break;
1947 case PPC405CR_CPC0_SR:
1948 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1949 break;
1950 default:
1951 /* Avoid gcc warning */
1952 ret = 0;
1953 break;
1954 }
1955
1956 return ret;
1957 }
1958
1959 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1960 {
1961 ppc405cr_cpc_t *cpc;
1962
1963 cpc = opaque;
1964 switch (dcrn) {
1965 case PPC405CR_CPC0_PLLMR:
1966 cpc->pllmr = val & 0xFFF77C3F;
1967 break;
1968 case PPC405CR_CPC0_CR0:
1969 cpc->cr0 = val & 0x0FFFFFFE;
1970 break;
1971 case PPC405CR_CPC0_CR1:
1972 cpc->cr1 = val & 0x00800000;
1973 break;
1974 case PPC405CR_CPC0_PSR:
1975 /* Read-only */
1976 break;
1977 case PPC405CR_CPC0_JTAGID:
1978 /* Read-only */
1979 break;
1980 case PPC405CR_CPC0_ER:
1981 cpc->er = val & 0xBFFC0000;
1982 break;
1983 case PPC405CR_CPC0_FR:
1984 cpc->fr = val & 0xBFFC0000;
1985 break;
1986 case PPC405CR_CPC0_SR:
1987 /* Read-only */
1988 break;
1989 }
1990 }
1991
1992 static void ppc405cr_cpc_reset (void *opaque)
1993 {
1994 ppc405cr_cpc_t *cpc;
1995 int D;
1996
1997 cpc = opaque;
1998 /* Compute PLLMR value from PSR settings */
1999 cpc->pllmr = 0x80000000;
2000 /* PFWD */
2001 switch ((cpc->psr >> 30) & 3) {
2002 case 0:
2003 /* Bypass */
2004 cpc->pllmr &= ~0x80000000;
2005 break;
2006 case 1:
2007 /* Divide by 3 */
2008 cpc->pllmr |= 5 << 16;
2009 break;
2010 case 2:
2011 /* Divide by 4 */
2012 cpc->pllmr |= 4 << 16;
2013 break;
2014 case 3:
2015 /* Divide by 6 */
2016 cpc->pllmr |= 2 << 16;
2017 break;
2018 }
2019 /* PFBD */
2020 D = (cpc->psr >> 28) & 3;
2021 cpc->pllmr |= (D + 1) << 20;
2022 /* PT */
2023 D = (cpc->psr >> 25) & 7;
2024 switch (D) {
2025 case 0x2:
2026 cpc->pllmr |= 0x13;
2027 break;
2028 case 0x4:
2029 cpc->pllmr |= 0x15;
2030 break;
2031 case 0x5:
2032 cpc->pllmr |= 0x16;
2033 break;
2034 default:
2035 break;
2036 }
2037 /* PDC */
2038 D = (cpc->psr >> 23) & 3;
2039 cpc->pllmr |= D << 26;
2040 /* ODP */
2041 D = (cpc->psr >> 21) & 3;
2042 cpc->pllmr |= D << 10;
2043 /* EBPD */
2044 D = (cpc->psr >> 17) & 3;
2045 cpc->pllmr |= D << 24;
2046 cpc->cr0 = 0x0000003C;
2047 cpc->cr1 = 0x2B0D8800;
2048 cpc->er = 0x00000000;
2049 cpc->fr = 0x00000000;
2050 ppc405cr_clk_setup(cpc);
2051 }
2052
2053 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2054 {
2055 int D;
2056
2057 /* XXX: this should be read from IO pins */
2058 cpc->psr = 0x00000000; /* 8 bits ROM */
2059 /* PFWD */
2060 D = 0x2; /* Divide by 4 */
2061 cpc->psr |= D << 30;
2062 /* PFBD */
2063 D = 0x1; /* Divide by 2 */
2064 cpc->psr |= D << 28;
2065 /* PDC */
2066 D = 0x1; /* Divide by 2 */
2067 cpc->psr |= D << 23;
2068 /* PT */
2069 D = 0x5; /* M = 16 */
2070 cpc->psr |= D << 25;
2071 /* ODP */
2072 D = 0x1; /* Divide by 2 */
2073 cpc->psr |= D << 21;
2074 /* EBDP */
2075 D = 0x2; /* Divide by 4 */
2076 cpc->psr |= D << 17;
2077 }
2078
2079 static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
2080 uint32_t sysclk)
2081 {
2082 ppc405cr_cpc_t *cpc;
2083
2084 cpc = g_malloc0(sizeof(ppc405cr_cpc_t));
2085 memcpy(cpc->clk_setup, clk_setup,
2086 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2087 cpc->sysclk = sysclk;
2088 cpc->jtagid = 0x42051049;
2089 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2090 &dcr_read_crcpc, &dcr_write_crcpc);
2091 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2092 &dcr_read_crcpc, &dcr_write_crcpc);
2093 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2094 &dcr_read_crcpc, &dcr_write_crcpc);
2095 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2096 &dcr_read_crcpc, &dcr_write_crcpc);
2097 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2098 &dcr_read_crcpc, &dcr_write_crcpc);
2099 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2100 &dcr_read_crcpc, &dcr_write_crcpc);
2101 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2102 &dcr_read_crcpc, &dcr_write_crcpc);
2103 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2104 &dcr_read_crcpc, &dcr_write_crcpc);
2105 ppc405cr_clk_init(cpc);
2106 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2107 }
2108
2109 CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
2110 MemoryRegion ram_memories[4],
2111 hwaddr ram_bases[4],
2112 hwaddr ram_sizes[4],
2113 uint32_t sysclk, qemu_irq **picp,
2114 int do_init)
2115 {
2116 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2117 qemu_irq dma_irqs[4];
2118 PowerPCCPU *cpu;
2119 CPUPPCState *env;
2120 qemu_irq *pic, *irqs;
2121
2122 memset(clk_setup, 0, sizeof(clk_setup));
2123 cpu = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2124 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2125 env = &cpu->env;
2126 /* Memory mapped devices registers */
2127 /* PLB arbitrer */
2128 ppc4xx_plb_init(env);
2129 /* PLB to OPB bridge */
2130 ppc4xx_pob_init(env);
2131 /* OBP arbitrer */
2132 ppc4xx_opba_init(0xef600600);
2133 /* Universal interrupt controller */
2134 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2135 irqs[PPCUIC_OUTPUT_INT] =
2136 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2137 irqs[PPCUIC_OUTPUT_CINT] =
2138 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2139 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2140 *picp = pic;
2141 /* SDRAM controller */
2142 ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
2143 ram_bases, ram_sizes, do_init);
2144 /* External bus controller */
2145 ppc405_ebc_init(env);
2146 /* DMA controller */
2147 dma_irqs[0] = pic[26];
2148 dma_irqs[1] = pic[25];
2149 dma_irqs[2] = pic[24];
2150 dma_irqs[3] = pic[23];
2151 ppc405_dma_init(env, dma_irqs);
2152 /* Serial ports */
2153 if (serial_hds[0] != NULL) {
2154 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2155 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2156 DEVICE_BIG_ENDIAN);
2157 }
2158 if (serial_hds[1] != NULL) {
2159 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2160 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2161 DEVICE_BIG_ENDIAN);
2162 }
2163 /* IIC controller */
2164 ppc405_i2c_init(0xef600500, pic[2]);
2165 /* GPIO */
2166 ppc405_gpio_init(0xef600700);
2167 /* CPU control */
2168 ppc405cr_cpc_init(env, clk_setup, sysclk);
2169
2170 return env;
2171 }
2172
2173 /*****************************************************************************/
2174 /* PowerPC 405EP */
2175 /* CPU control */
2176 enum {
2177 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2178 PPC405EP_CPC0_BOOT = 0x0F1,
2179 PPC405EP_CPC0_EPCTL = 0x0F3,
2180 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2181 PPC405EP_CPC0_UCR = 0x0F5,
2182 PPC405EP_CPC0_SRR = 0x0F6,
2183 PPC405EP_CPC0_JTAGID = 0x0F7,
2184 PPC405EP_CPC0_PCI = 0x0F9,
2185 #if 0
2186 PPC405EP_CPC0_ER = xxx,
2187 PPC405EP_CPC0_FR = xxx,
2188 PPC405EP_CPC0_SR = xxx,
2189 #endif
2190 };
2191
2192 enum {
2193 PPC405EP_CPU_CLK = 0,
2194 PPC405EP_PLB_CLK = 1,
2195 PPC405EP_OPB_CLK = 2,
2196 PPC405EP_EBC_CLK = 3,
2197 PPC405EP_MAL_CLK = 4,
2198 PPC405EP_PCI_CLK = 5,
2199 PPC405EP_UART0_CLK = 6,
2200 PPC405EP_UART1_CLK = 7,
2201 PPC405EP_CLK_NB = 8,
2202 };
2203
2204 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2205 struct ppc405ep_cpc_t {
2206 uint32_t sysclk;
2207 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2208 uint32_t boot;
2209 uint32_t epctl;
2210 uint32_t pllmr[2];
2211 uint32_t ucr;
2212 uint32_t srr;
2213 uint32_t jtagid;
2214 uint32_t pci;
2215 /* Clock and power management */
2216 uint32_t er;
2217 uint32_t fr;
2218 uint32_t sr;
2219 };
2220
2221 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2222 {
2223 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2224 uint32_t UART0_clk, UART1_clk;
2225 uint64_t VCO_out, PLL_out;
2226 int M, D;
2227
2228 VCO_out = 0;
2229 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2230 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2231 #ifdef DEBUG_CLOCKS_LL
2232 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2233 #endif
2234 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2235 #ifdef DEBUG_CLOCKS_LL
2236 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2237 #endif
2238 VCO_out = cpc->sysclk * M * D;
2239 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2240 /* Error - unlock the PLL */
2241 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2242 #if 0
2243 cpc->pllmr[1] &= ~0x80000000;
2244 goto pll_bypass;
2245 #endif
2246 }
2247 PLL_out = VCO_out / D;
2248 /* Pretend the PLL is locked */
2249 cpc->boot |= 0x00000001;
2250 } else {
2251 #if 0
2252 pll_bypass:
2253 #endif
2254 PLL_out = cpc->sysclk;
2255 if (cpc->pllmr[1] & 0x40000000) {
2256 /* Pretend the PLL is not locked */
2257 cpc->boot &= ~0x00000001;
2258 }
2259 }
2260 /* Now, compute all other clocks */
2261 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2262 #ifdef DEBUG_CLOCKS_LL
2263 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2264 #endif
2265 CPU_clk = PLL_out / D;
2266 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2267 #ifdef DEBUG_CLOCKS_LL
2268 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2269 #endif
2270 PLB_clk = CPU_clk / D;
2271 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2272 #ifdef DEBUG_CLOCKS_LL
2273 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2274 #endif
2275 OPB_clk = PLB_clk / D;
2276 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2277 #ifdef DEBUG_CLOCKS_LL
2278 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2279 #endif
2280 EBC_clk = PLB_clk / D;
2281 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2282 #ifdef DEBUG_CLOCKS_LL
2283 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2284 #endif
2285 MAL_clk = PLB_clk / D;
2286 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2287 #ifdef DEBUG_CLOCKS_LL
2288 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2289 #endif
2290 PCI_clk = PLB_clk / D;
2291 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2292 #ifdef DEBUG_CLOCKS_LL
2293 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2294 #endif
2295 UART0_clk = PLL_out / D;
2296 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2297 #ifdef DEBUG_CLOCKS_LL
2298 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2299 #endif
2300 UART1_clk = PLL_out / D;
2301 #ifdef DEBUG_CLOCKS
2302 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2303 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2304 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2305 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2306 " UART1 %" PRIu32 "\n",
2307 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2308 UART0_clk, UART1_clk);
2309 #endif
2310 /* Setup CPU clocks */
2311 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2312 /* Setup PLB clock */
2313 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2314 /* Setup OPB clock */
2315 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2316 /* Setup external clock */
2317 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2318 /* Setup MAL clock */
2319 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2320 /* Setup PCI clock */
2321 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2322 /* Setup UART0 clock */
2323 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2324 /* Setup UART1 clock */
2325 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2326 }
2327
2328 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
2329 {
2330 ppc405ep_cpc_t *cpc;
2331 uint32_t ret;
2332
2333 cpc = opaque;
2334 switch (dcrn) {
2335 case PPC405EP_CPC0_BOOT:
2336 ret = cpc->boot;
2337 break;
2338 case PPC405EP_CPC0_EPCTL:
2339 ret = cpc->epctl;
2340 break;
2341 case PPC405EP_CPC0_PLLMR0:
2342 ret = cpc->pllmr[0];
2343 break;
2344 case PPC405EP_CPC0_PLLMR1:
2345 ret = cpc->pllmr[1];
2346 break;
2347 case PPC405EP_CPC0_UCR:
2348 ret = cpc->ucr;
2349 break;
2350 case PPC405EP_CPC0_SRR:
2351 ret = cpc->srr;
2352 break;
2353 case PPC405EP_CPC0_JTAGID:
2354 ret = cpc->jtagid;
2355 break;
2356 case PPC405EP_CPC0_PCI:
2357 ret = cpc->pci;
2358 break;
2359 default:
2360 /* Avoid gcc warning */
2361 ret = 0;
2362 break;
2363 }
2364
2365 return ret;
2366 }
2367
2368 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
2369 {
2370 ppc405ep_cpc_t *cpc;
2371
2372 cpc = opaque;
2373 switch (dcrn) {
2374 case PPC405EP_CPC0_BOOT:
2375 /* Read-only register */
2376 break;
2377 case PPC405EP_CPC0_EPCTL:
2378 /* Don't care for now */
2379 cpc->epctl = val & 0xC00000F3;
2380 break;
2381 case PPC405EP_CPC0_PLLMR0:
2382 cpc->pllmr[0] = val & 0x00633333;
2383 ppc405ep_compute_clocks(cpc);
2384 break;
2385 case PPC405EP_CPC0_PLLMR1:
2386 cpc->pllmr[1] = val & 0xC0F73FFF;
2387 ppc405ep_compute_clocks(cpc);
2388 break;
2389 case PPC405EP_CPC0_UCR:
2390 /* UART control - don't care for now */
2391 cpc->ucr = val & 0x003F7F7F;
2392 break;
2393 case PPC405EP_CPC0_SRR:
2394 cpc->srr = val;
2395 break;
2396 case PPC405EP_CPC0_JTAGID:
2397 /* Read-only */
2398 break;
2399 case PPC405EP_CPC0_PCI:
2400 cpc->pci = val;
2401 break;
2402 }
2403 }
2404
2405 static void ppc405ep_cpc_reset (void *opaque)
2406 {
2407 ppc405ep_cpc_t *cpc = opaque;
2408
2409 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2410 cpc->epctl = 0x00000000;
2411 cpc->pllmr[0] = 0x00011010;
2412 cpc->pllmr[1] = 0x40000000;
2413 cpc->ucr = 0x00000000;
2414 cpc->srr = 0x00040000;
2415 cpc->pci = 0x00000000;
2416 cpc->er = 0x00000000;
2417 cpc->fr = 0x00000000;
2418 cpc->sr = 0x00000000;
2419 ppc405ep_compute_clocks(cpc);
2420 }
2421
2422 /* XXX: sysclk should be between 25 and 100 MHz */
2423 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
2424 uint32_t sysclk)
2425 {
2426 ppc405ep_cpc_t *cpc;
2427
2428 cpc = g_malloc0(sizeof(ppc405ep_cpc_t));
2429 memcpy(cpc->clk_setup, clk_setup,
2430 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2431 cpc->jtagid = 0x20267049;
2432 cpc->sysclk = sysclk;
2433 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2434 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2435 &dcr_read_epcpc, &dcr_write_epcpc);
2436 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2437 &dcr_read_epcpc, &dcr_write_epcpc);
2438 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2439 &dcr_read_epcpc, &dcr_write_epcpc);
2440 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2441 &dcr_read_epcpc, &dcr_write_epcpc);
2442 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2443 &dcr_read_epcpc, &dcr_write_epcpc);
2444 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2445 &dcr_read_epcpc, &dcr_write_epcpc);
2446 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2447 &dcr_read_epcpc, &dcr_write_epcpc);
2448 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2449 &dcr_read_epcpc, &dcr_write_epcpc);
2450 #if 0
2451 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2452 &dcr_read_epcpc, &dcr_write_epcpc);
2453 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2454 &dcr_read_epcpc, &dcr_write_epcpc);
2455 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2456 &dcr_read_epcpc, &dcr_write_epcpc);
2457 #endif
2458 }
2459
2460 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
2461 MemoryRegion ram_memories[2],
2462 hwaddr ram_bases[2],
2463 hwaddr ram_sizes[2],
2464 uint32_t sysclk, qemu_irq **picp,
2465 int do_init)
2466 {
2467 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2468 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2469 PowerPCCPU *cpu;
2470 CPUPPCState *env;
2471 qemu_irq *pic, *irqs;
2472
2473 memset(clk_setup, 0, sizeof(clk_setup));
2474 /* init CPUs */
2475 cpu = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2476 &tlb_clk_setup, sysclk);
2477 env = &cpu->env;
2478 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2479 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2480 /* Internal devices init */
2481 /* Memory mapped devices registers */
2482 /* PLB arbitrer */
2483 ppc4xx_plb_init(env);
2484 /* PLB to OPB bridge */
2485 ppc4xx_pob_init(env);
2486 /* OBP arbitrer */
2487 ppc4xx_opba_init(0xef600600);
2488 /* Initialize timers */
2489 ppc_booke_timers_init(cpu, sysclk, 0);
2490 /* Universal interrupt controller */
2491 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2492 irqs[PPCUIC_OUTPUT_INT] =
2493 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2494 irqs[PPCUIC_OUTPUT_CINT] =
2495 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2496 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2497 *picp = pic;
2498 /* SDRAM controller */
2499 /* XXX 405EP has no ECC interrupt */
2500 ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
2501 ram_bases, ram_sizes, do_init);
2502 /* External bus controller */
2503 ppc405_ebc_init(env);
2504 /* DMA controller */
2505 dma_irqs[0] = pic[5];
2506 dma_irqs[1] = pic[6];
2507 dma_irqs[2] = pic[7];
2508 dma_irqs[3] = pic[8];
2509 ppc405_dma_init(env, dma_irqs);
2510 /* IIC controller */
2511 ppc405_i2c_init(0xef600500, pic[2]);
2512 /* GPIO */
2513 ppc405_gpio_init(0xef600700);
2514 /* Serial ports */
2515 if (serial_hds[0] != NULL) {
2516 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2517 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2518 DEVICE_BIG_ENDIAN);
2519 }
2520 if (serial_hds[1] != NULL) {
2521 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2522 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2523 DEVICE_BIG_ENDIAN);
2524 }
2525 /* OCM */
2526 ppc405_ocm_init(env);
2527 /* GPT */
2528 gpt_irqs[0] = pic[19];
2529 gpt_irqs[1] = pic[20];
2530 gpt_irqs[2] = pic[21];
2531 gpt_irqs[3] = pic[22];
2532 gpt_irqs[4] = pic[23];
2533 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2534 /* PCI */
2535 /* Uses pic[3], pic[16], pic[18] */
2536 /* MAL */
2537 mal_irqs[0] = pic[11];
2538 mal_irqs[1] = pic[12];
2539 mal_irqs[2] = pic[13];
2540 mal_irqs[3] = pic[14];
2541 ppc405_mal_init(env, mal_irqs);
2542 /* Ethernet */
2543 /* Uses pic[9], pic[15], pic[17] */
2544 /* CPU control */
2545 ppc405ep_cpc_init(env, clk_setup, sysclk);
2546
2547 return env;
2548 }
AR7 emulation for QEMU