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target-m68k: add 680x0 divu/divs variants
[qemu/ar7.git] / target / m68k / translate.c
blob737009e0b5432b29b21454157d799512974b2c22
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/log.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 //#define DEBUG_DISPATCH 1
37
38 /* Fake floating point. */
39 #define tcg_gen_mov_f64 tcg_gen_mov_i64
40 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
41 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
42
43 #define DEFO32(name, offset) static TCGv QREG_##name;
44 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
45 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;
46 #include "qregs.def"
47 #undef DEFO32
48 #undef DEFO64
49 #undef DEFF64
50
51 static TCGv_i32 cpu_halted;
52 static TCGv_i32 cpu_exception_index;
53
54 static TCGv_env cpu_env;
55
56 static char cpu_reg_names[3*8*3 + 5*4];
57 static TCGv cpu_dregs[8];
58 static TCGv cpu_aregs[8];
59 static TCGv_i64 cpu_fregs[8];
60 static TCGv_i64 cpu_macc[4];
61
62 #define REG(insn, pos) (((insn) >> (pos)) & 7)
63 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
64 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
65 #define FREG(insn, pos) cpu_fregs[REG(insn, pos)]
66 #define MACREG(acc) cpu_macc[acc]
67 #define QREG_SP get_areg(s, 7)
68
69 static TCGv NULL_QREG;
70 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
71 /* Used to distinguish stores from bad addressing modes. */
72 static TCGv store_dummy;
73
74 #include "exec/gen-icount.h"
75
76 void m68k_tcg_init(void)
77 {
78 char *p;
79 int i;
80
81 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
82 tcg_ctx.tcg_env = cpu_env;
83
84 #define DEFO32(name, offset) \
85 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
86 offsetof(CPUM68KState, offset), #name);
87 #define DEFO64(name, offset) \
88 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
89 offsetof(CPUM68KState, offset), #name);
90 #define DEFF64(name, offset) DEFO64(name, offset)
91 #include "qregs.def"
92 #undef DEFO32
93 #undef DEFO64
94 #undef DEFF64
95
96 cpu_halted = tcg_global_mem_new_i32(cpu_env,
97 -offsetof(M68kCPU, env) +
98 offsetof(CPUState, halted), "HALTED");
99 cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
100 -offsetof(M68kCPU, env) +
101 offsetof(CPUState, exception_index),
102 "EXCEPTION");
103
104 p = cpu_reg_names;
105 for (i = 0; i < 8; i++) {
106 sprintf(p, "D%d", i);
107 cpu_dregs[i] = tcg_global_mem_new(cpu_env,
108 offsetof(CPUM68KState, dregs[i]), p);
109 p += 3;
110 sprintf(p, "A%d", i);
111 cpu_aregs[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUM68KState, aregs[i]), p);
113 p += 3;
114 sprintf(p, "F%d", i);
115 cpu_fregs[i] = tcg_global_mem_new_i64(cpu_env,
116 offsetof(CPUM68KState, fregs[i]), p);
117 p += 3;
118 }
119 for (i = 0; i < 4; i++) {
120 sprintf(p, "ACC%d", i);
121 cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
122 offsetof(CPUM68KState, macc[i]), p);
123 p += 5;
124 }
125
126 NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
127 store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
128 }
129
130 /* internal defines */
131 typedef struct DisasContext {
132 CPUM68KState *env;
133 target_ulong insn_pc; /* Start of the current instruction. */
134 target_ulong pc;
135 int is_jmp;
136 CCOp cc_op; /* Current CC operation */
137 int cc_op_synced;
138 int user;
139 uint32_t fpcr;
140 struct TranslationBlock *tb;
141 int singlestep_enabled;
142 TCGv_i64 mactmp;
143 int done_mac;
144 int writeback_mask;
145 TCGv writeback[8];
146 } DisasContext;
147
148 static TCGv get_areg(DisasContext *s, unsigned regno)
149 {
150 if (s->writeback_mask & (1 << regno)) {
151 return s->writeback[regno];
152 } else {
153 return cpu_aregs[regno];
154 }
155 }
156
157 static void delay_set_areg(DisasContext *s, unsigned regno,
158 TCGv val, bool give_temp)
159 {
160 if (s->writeback_mask & (1 << regno)) {
161 if (give_temp) {
162 tcg_temp_free(s->writeback[regno]);
163 s->writeback[regno] = val;
164 } else {
165 tcg_gen_mov_i32(s->writeback[regno], val);
166 }
167 } else {
168 s->writeback_mask |= 1 << regno;
169 if (give_temp) {
170 s->writeback[regno] = val;
171 } else {
172 TCGv tmp = tcg_temp_new();
173 s->writeback[regno] = tmp;
174 tcg_gen_mov_i32(tmp, val);
175 }
176 }
177 }
178
179 static void do_writebacks(DisasContext *s)
180 {
181 unsigned mask = s->writeback_mask;
182 if (mask) {
183 s->writeback_mask = 0;
184 do {
185 unsigned regno = ctz32(mask);
186 tcg_gen_mov_i32(cpu_aregs[regno], s->writeback[regno]);
187 tcg_temp_free(s->writeback[regno]);
188 mask &= mask - 1;
189 } while (mask);
190 }
191 }
192
193 #define DISAS_JUMP_NEXT 4
194
195 #if defined(CONFIG_USER_ONLY)
196 #define IS_USER(s) 1
197 #else
198 #define IS_USER(s) s->user
199 #endif
200
201 /* XXX: move that elsewhere */
202 /* ??? Fix exceptions. */
203 static void *gen_throws_exception;
204 #define gen_last_qop NULL
205
206 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
207
208 #ifdef DEBUG_DISPATCH
209 #define DISAS_INSN(name) \
210 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
211 uint16_t insn); \
212 static void disas_##name(CPUM68KState *env, DisasContext *s, \
213 uint16_t insn) \
214 { \
215 qemu_log("Dispatch " #name "\n"); \
216 real_disas_##name(env, s, insn); \
217 } \
218 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
219 uint16_t insn)
220 #else
221 #define DISAS_INSN(name) \
222 static void disas_##name(CPUM68KState *env, DisasContext *s, \
223 uint16_t insn)
224 #endif
225
226 static const uint8_t cc_op_live[CC_OP_NB] = {
227 [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
228 [CC_OP_ADDB ... CC_OP_ADDL] = CCF_X | CCF_N | CCF_V,
229 [CC_OP_SUBB ... CC_OP_SUBL] = CCF_X | CCF_N | CCF_V,
230 [CC_OP_CMPB ... CC_OP_CMPL] = CCF_X | CCF_N | CCF_V,
231 [CC_OP_LOGIC] = CCF_X | CCF_N
232 };
233
234 static void set_cc_op(DisasContext *s, CCOp op)
235 {
236 CCOp old_op = s->cc_op;
237 int dead;
238
239 if (old_op == op) {
240 return;
241 }
242 s->cc_op = op;
243 s->cc_op_synced = 0;
244
245 /* Discard CC computation that will no longer be used.
246 Note that X and N are never dead. */
247 dead = cc_op_live[old_op] & ~cc_op_live[op];
248 if (dead & CCF_C) {
249 tcg_gen_discard_i32(QREG_CC_C);
250 }
251 if (dead & CCF_Z) {
252 tcg_gen_discard_i32(QREG_CC_Z);
253 }
254 if (dead & CCF_V) {
255 tcg_gen_discard_i32(QREG_CC_V);
256 }
257 }
258
259 /* Update the CPU env CC_OP state. */
260 static void update_cc_op(DisasContext *s)
261 {
262 if (!s->cc_op_synced) {
263 s->cc_op_synced = 1;
264 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
265 }
266 }
267
268 /* Generate a load from the specified address. Narrow values are
269 sign extended to full register width. */
270 static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
271 {
272 TCGv tmp;
273 int index = IS_USER(s);
274 tmp = tcg_temp_new_i32();
275 switch(opsize) {
276 case OS_BYTE:
277 if (sign)
278 tcg_gen_qemu_ld8s(tmp, addr, index);
279 else
280 tcg_gen_qemu_ld8u(tmp, addr, index);
281 break;
282 case OS_WORD:
283 if (sign)
284 tcg_gen_qemu_ld16s(tmp, addr, index);
285 else
286 tcg_gen_qemu_ld16u(tmp, addr, index);
287 break;
288 case OS_LONG:
289 case OS_SINGLE:
290 tcg_gen_qemu_ld32u(tmp, addr, index);
291 break;
292 default:
293 g_assert_not_reached();
294 }
295 gen_throws_exception = gen_last_qop;
296 return tmp;
297 }
298
299 static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)
300 {
301 TCGv_i64 tmp;
302 int index = IS_USER(s);
303 tmp = tcg_temp_new_i64();
304 tcg_gen_qemu_ldf64(tmp, addr, index);
305 gen_throws_exception = gen_last_qop;
306 return tmp;
307 }
308
309 /* Generate a store. */
310 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
311 {
312 int index = IS_USER(s);
313 switch(opsize) {
314 case OS_BYTE:
315 tcg_gen_qemu_st8(val, addr, index);
316 break;
317 case OS_WORD:
318 tcg_gen_qemu_st16(val, addr, index);
319 break;
320 case OS_LONG:
321 case OS_SINGLE:
322 tcg_gen_qemu_st32(val, addr, index);
323 break;
324 default:
325 g_assert_not_reached();
326 }
327 gen_throws_exception = gen_last_qop;
328 }
329
330 static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)
331 {
332 int index = IS_USER(s);
333 tcg_gen_qemu_stf64(val, addr, index);
334 gen_throws_exception = gen_last_qop;
335 }
336
337 typedef enum {
338 EA_STORE,
339 EA_LOADU,
340 EA_LOADS
341 } ea_what;
342
343 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
344 otherwise generate a store. */
345 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
346 ea_what what)
347 {
348 if (what == EA_STORE) {
349 gen_store(s, opsize, addr, val);
350 return store_dummy;
351 } else {
352 return gen_load(s, opsize, addr, what == EA_LOADS);
353 }
354 }
355
356 /* Read a 16-bit immediate constant */
357 static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
358 {
359 uint16_t im;
360 im = cpu_lduw_code(env, s->pc);
361 s->pc += 2;
362 return im;
363 }
364
365 /* Read an 8-bit immediate constant */
366 static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s)
367 {
368 return read_im16(env, s);
369 }
370
371 /* Read a 32-bit immediate constant. */
372 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
373 {
374 uint32_t im;
375 im = read_im16(env, s) << 16;
376 im |= 0xffff & read_im16(env, s);
377 return im;
378 }
379
380 /* Calculate and address index. */
381 static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
382 {
383 TCGv add;
384 int scale;
385
386 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
387 if ((ext & 0x800) == 0) {
388 tcg_gen_ext16s_i32(tmp, add);
389 add = tmp;
390 }
391 scale = (ext >> 9) & 3;
392 if (scale != 0) {
393 tcg_gen_shli_i32(tmp, add, scale);
394 add = tmp;
395 }
396 return add;
397 }
398
399 /* Handle a base + index + displacement effective addresss.
400 A NULL_QREG base means pc-relative. */
401 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
402 {
403 uint32_t offset;
404 uint16_t ext;
405 TCGv add;
406 TCGv tmp;
407 uint32_t bd, od;
408
409 offset = s->pc;
410 ext = read_im16(env, s);
411
412 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
413 return NULL_QREG;
414
415 if (m68k_feature(s->env, M68K_FEATURE_M68000) &&
416 !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) {
417 ext &= ~(3 << 9);
418 }
419
420 if (ext & 0x100) {
421 /* full extension word format */
422 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
423 return NULL_QREG;
424
425 if ((ext & 0x30) > 0x10) {
426 /* base displacement */
427 if ((ext & 0x30) == 0x20) {
428 bd = (int16_t)read_im16(env, s);
429 } else {
430 bd = read_im32(env, s);
431 }
432 } else {
433 bd = 0;
434 }
435 tmp = tcg_temp_new();
436 if ((ext & 0x44) == 0) {
437 /* pre-index */
438 add = gen_addr_index(s, ext, tmp);
439 } else {
440 add = NULL_QREG;
441 }
442 if ((ext & 0x80) == 0) {
443 /* base not suppressed */
444 if (IS_NULL_QREG(base)) {
445 base = tcg_const_i32(offset + bd);
446 bd = 0;
447 }
448 if (!IS_NULL_QREG(add)) {
449 tcg_gen_add_i32(tmp, add, base);
450 add = tmp;
451 } else {
452 add = base;
453 }
454 }
455 if (!IS_NULL_QREG(add)) {
456 if (bd != 0) {
457 tcg_gen_addi_i32(tmp, add, bd);
458 add = tmp;
459 }
460 } else {
461 add = tcg_const_i32(bd);
462 }
463 if ((ext & 3) != 0) {
464 /* memory indirect */
465 base = gen_load(s, OS_LONG, add, 0);
466 if ((ext & 0x44) == 4) {
467 add = gen_addr_index(s, ext, tmp);
468 tcg_gen_add_i32(tmp, add, base);
469 add = tmp;
470 } else {
471 add = base;
472 }
473 if ((ext & 3) > 1) {
474 /* outer displacement */
475 if ((ext & 3) == 2) {
476 od = (int16_t)read_im16(env, s);
477 } else {
478 od = read_im32(env, s);
479 }
480 } else {
481 od = 0;
482 }
483 if (od != 0) {
484 tcg_gen_addi_i32(tmp, add, od);
485 add = tmp;
486 }
487 }
488 } else {
489 /* brief extension word format */
490 tmp = tcg_temp_new();
491 add = gen_addr_index(s, ext, tmp);
492 if (!IS_NULL_QREG(base)) {
493 tcg_gen_add_i32(tmp, add, base);
494 if ((int8_t)ext)
495 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
496 } else {
497 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
498 }
499 add = tmp;
500 }
501 return add;
502 }
503
504 /* Sign or zero extend a value. */
505
506 static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign)
507 {
508 switch (opsize) {
509 case OS_BYTE:
510 if (sign) {
511 tcg_gen_ext8s_i32(res, val);
512 } else {
513 tcg_gen_ext8u_i32(res, val);
514 }
515 break;
516 case OS_WORD:
517 if (sign) {
518 tcg_gen_ext16s_i32(res, val);
519 } else {
520 tcg_gen_ext16u_i32(res, val);
521 }
522 break;
523 case OS_LONG:
524 tcg_gen_mov_i32(res, val);
525 break;
526 default:
527 g_assert_not_reached();
528 }
529 }
530
531 /* Evaluate all the CC flags. */
532
533 static void gen_flush_flags(DisasContext *s)
534 {
535 TCGv t0, t1;
536
537 switch (s->cc_op) {
538 case CC_OP_FLAGS:
539 return;
540
541 case CC_OP_ADDB:
542 case CC_OP_ADDW:
543 case CC_OP_ADDL:
544 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
545 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
546 /* Compute signed overflow for addition. */
547 t0 = tcg_temp_new();
548 t1 = tcg_temp_new();
549 tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V);
550 gen_ext(t0, t0, s->cc_op - CC_OP_ADDB, 1);
551 tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
552 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
553 tcg_temp_free(t0);
554 tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V);
555 tcg_temp_free(t1);
556 break;
557
558 case CC_OP_SUBB:
559 case CC_OP_SUBW:
560 case CC_OP_SUBL:
561 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
562 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
563 /* Compute signed overflow for subtraction. */
564 t0 = tcg_temp_new();
565 t1 = tcg_temp_new();
566 tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V);
567 gen_ext(t0, t0, s->cc_op - CC_OP_SUBB, 1);
568 tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
569 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
570 tcg_temp_free(t0);
571 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1);
572 tcg_temp_free(t1);
573 break;
574
575 case CC_OP_CMPB:
576 case CC_OP_CMPW:
577 case CC_OP_CMPL:
578 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V);
579 tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V);
580 gen_ext(QREG_CC_Z, QREG_CC_Z, s->cc_op - CC_OP_CMPB, 1);
581 /* Compute signed overflow for subtraction. */
582 t0 = tcg_temp_new();
583 tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N);
584 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N);
585 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0);
586 tcg_temp_free(t0);
587 tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z);
588 break;
589
590 case CC_OP_LOGIC:
591 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
592 tcg_gen_movi_i32(QREG_CC_C, 0);
593 tcg_gen_movi_i32(QREG_CC_V, 0);
594 break;
595
596 case CC_OP_DYNAMIC:
597 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
598 break;
599
600 default:
601 t0 = tcg_const_i32(s->cc_op);
602 gen_helper_flush_flags(cpu_env, t0);
603 tcg_temp_free(t0);
604 break;
605 }
606
607 /* Note that flush_flags also assigned to env->cc_op. */
608 s->cc_op = CC_OP_FLAGS;
609 s->cc_op_synced = 1;
610 }
611
612 static inline TCGv gen_extend(TCGv val, int opsize, int sign)
613 {
614 TCGv tmp;
615
616 if (opsize == OS_LONG) {
617 tmp = val;
618 } else {
619 tmp = tcg_temp_new();
620 gen_ext(tmp, val, opsize, sign);
621 }
622
623 return tmp;
624 }
625
626 static void gen_logic_cc(DisasContext *s, TCGv val, int opsize)
627 {
628 gen_ext(QREG_CC_N, val, opsize, 1);
629 set_cc_op(s, CC_OP_LOGIC);
630 }
631
632 static void gen_update_cc_cmp(DisasContext *s, TCGv dest, TCGv src, int opsize)
633 {
634 tcg_gen_mov_i32(QREG_CC_N, dest);
635 tcg_gen_mov_i32(QREG_CC_V, src);
636 set_cc_op(s, CC_OP_CMPB + opsize);
637 }
638
639 static void gen_update_cc_add(TCGv dest, TCGv src, int opsize)
640 {
641 gen_ext(QREG_CC_N, dest, opsize, 1);
642 tcg_gen_mov_i32(QREG_CC_V, src);
643 }
644
645 static inline int opsize_bytes(int opsize)
646 {
647 switch (opsize) {
648 case OS_BYTE: return 1;
649 case OS_WORD: return 2;
650 case OS_LONG: return 4;
651 case OS_SINGLE: return 4;
652 case OS_DOUBLE: return 8;
653 case OS_EXTENDED: return 12;
654 case OS_PACKED: return 12;
655 default:
656 g_assert_not_reached();
657 }
658 }
659
660 static inline int insn_opsize(int insn)
661 {
662 switch ((insn >> 6) & 3) {
663 case 0: return OS_BYTE;
664 case 1: return OS_WORD;
665 case 2: return OS_LONG;
666 default:
667 g_assert_not_reached();
668 }
669 }
670
671 /* Assign value to a register. If the width is less than the register width
672 only the low part of the register is set. */
673 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
674 {
675 TCGv tmp;
676 switch (opsize) {
677 case OS_BYTE:
678 tcg_gen_andi_i32(reg, reg, 0xffffff00);
679 tmp = tcg_temp_new();
680 tcg_gen_ext8u_i32(tmp, val);
681 tcg_gen_or_i32(reg, reg, tmp);
682 break;
683 case OS_WORD:
684 tcg_gen_andi_i32(reg, reg, 0xffff0000);
685 tmp = tcg_temp_new();
686 tcg_gen_ext16u_i32(tmp, val);
687 tcg_gen_or_i32(reg, reg, tmp);
688 break;
689 case OS_LONG:
690 case OS_SINGLE:
691 tcg_gen_mov_i32(reg, val);
692 break;
693 default:
694 g_assert_not_reached();
695 }
696 }
697
698 /* Generate code for an "effective address". Does not adjust the base
699 register for autoincrement addressing modes. */
700 static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
701 int mode, int reg0, int opsize)
702 {
703 TCGv reg;
704 TCGv tmp;
705 uint16_t ext;
706 uint32_t offset;
707
708 switch (mode) {
709 case 0: /* Data register direct. */
710 case 1: /* Address register direct. */
711 return NULL_QREG;
712 case 2: /* Indirect register */
713 case 3: /* Indirect postincrement. */
714 return get_areg(s, reg0);
715 case 4: /* Indirect predecrememnt. */
716 reg = get_areg(s, reg0);
717 tmp = tcg_temp_new();
718 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
719 return tmp;
720 case 5: /* Indirect displacement. */
721 reg = get_areg(s, reg0);
722 tmp = tcg_temp_new();
723 ext = read_im16(env, s);
724 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
725 return tmp;
726 case 6: /* Indirect index + displacement. */
727 reg = get_areg(s, reg0);
728 return gen_lea_indexed(env, s, reg);
729 case 7: /* Other */
730 switch (reg0) {
731 case 0: /* Absolute short. */
732 offset = (int16_t)read_im16(env, s);
733 return tcg_const_i32(offset);
734 case 1: /* Absolute long. */
735 offset = read_im32(env, s);
736 return tcg_const_i32(offset);
737 case 2: /* pc displacement */
738 offset = s->pc;
739 offset += (int16_t)read_im16(env, s);
740 return tcg_const_i32(offset);
741 case 3: /* pc index+displacement. */
742 return gen_lea_indexed(env, s, NULL_QREG);
743 case 4: /* Immediate. */
744 default:
745 return NULL_QREG;
746 }
747 }
748 /* Should never happen. */
749 return NULL_QREG;
750 }
751
752 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
753 int opsize)
754 {
755 int mode = extract32(insn, 3, 3);
756 int reg0 = REG(insn, 0);
757 return gen_lea_mode(env, s, mode, reg0, opsize);
758 }
759
760 /* Generate code to load/store a value from/into an EA. If WHAT > 0 this is
761 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
762 ADDRP is non-null for readwrite operands. */
763 static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
764 int opsize, TCGv val, TCGv *addrp, ea_what what)
765 {
766 TCGv reg, tmp, result;
767 int32_t offset;
768
769 switch (mode) {
770 case 0: /* Data register direct. */
771 reg = cpu_dregs[reg0];
772 if (what == EA_STORE) {
773 gen_partset_reg(opsize, reg, val);
774 return store_dummy;
775 } else {
776 return gen_extend(reg, opsize, what == EA_LOADS);
777 }
778 case 1: /* Address register direct. */
779 reg = get_areg(s, reg0);
780 if (what == EA_STORE) {
781 tcg_gen_mov_i32(reg, val);
782 return store_dummy;
783 } else {
784 return gen_extend(reg, opsize, what == EA_LOADS);
785 }
786 case 2: /* Indirect register */
787 reg = get_areg(s, reg0);
788 return gen_ldst(s, opsize, reg, val, what);
789 case 3: /* Indirect postincrement. */
790 reg = get_areg(s, reg0);
791 result = gen_ldst(s, opsize, reg, val, what);
792 if (what == EA_STORE || !addrp) {
793 TCGv tmp = tcg_temp_new();
794 tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
795 delay_set_areg(s, reg0, tmp, true);
796 }
797 return result;
798 case 4: /* Indirect predecrememnt. */
799 if (addrp && what == EA_STORE) {
800 tmp = *addrp;
801 } else {
802 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
803 if (IS_NULL_QREG(tmp)) {
804 return tmp;
805 }
806 if (addrp) {
807 *addrp = tmp;
808 }
809 }
810 result = gen_ldst(s, opsize, tmp, val, what);
811 if (what == EA_STORE || !addrp) {
812 delay_set_areg(s, reg0, tmp, false);
813 }
814 return result;
815 case 5: /* Indirect displacement. */
816 case 6: /* Indirect index + displacement. */
817 do_indirect:
818 if (addrp && what == EA_STORE) {
819 tmp = *addrp;
820 } else {
821 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
822 if (IS_NULL_QREG(tmp)) {
823 return tmp;
824 }
825 if (addrp) {
826 *addrp = tmp;
827 }
828 }
829 return gen_ldst(s, opsize, tmp, val, what);
830 case 7: /* Other */
831 switch (reg0) {
832 case 0: /* Absolute short. */
833 case 1: /* Absolute long. */
834 case 2: /* pc displacement */
835 case 3: /* pc index+displacement. */
836 goto do_indirect;
837 case 4: /* Immediate. */
838 /* Sign extend values for consistency. */
839 switch (opsize) {
840 case OS_BYTE:
841 if (what == EA_LOADS) {
842 offset = (int8_t)read_im8(env, s);
843 } else {
844 offset = read_im8(env, s);
845 }
846 break;
847 case OS_WORD:
848 if (what == EA_LOADS) {
849 offset = (int16_t)read_im16(env, s);
850 } else {
851 offset = read_im16(env, s);
852 }
853 break;
854 case OS_LONG:
855 offset = read_im32(env, s);
856 break;
857 default:
858 g_assert_not_reached();
859 }
860 return tcg_const_i32(offset);
861 default:
862 return NULL_QREG;
863 }
864 }
865 /* Should never happen. */
866 return NULL_QREG;
867 }
868
869 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
870 int opsize, TCGv val, TCGv *addrp, ea_what what)
871 {
872 int mode = extract32(insn, 3, 3);
873 int reg0 = REG(insn, 0);
874 return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what);
875 }
876
877 typedef struct {
878 TCGCond tcond;
879 bool g1;
880 bool g2;
881 TCGv v1;
882 TCGv v2;
883 } DisasCompare;
884
885 static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
886 {
887 TCGv tmp, tmp2;
888 TCGCond tcond;
889 CCOp op = s->cc_op;
890
891 /* The CC_OP_CMP form can handle most normal comparisons directly. */
892 if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) {
893 c->g1 = c->g2 = 1;
894 c->v1 = QREG_CC_N;
895 c->v2 = QREG_CC_V;
896 switch (cond) {
897 case 2: /* HI */
898 case 3: /* LS */
899 tcond = TCG_COND_LEU;
900 goto done;
901 case 4: /* CC */
902 case 5: /* CS */
903 tcond = TCG_COND_LTU;
904 goto done;
905 case 6: /* NE */
906 case 7: /* EQ */
907 tcond = TCG_COND_EQ;
908 goto done;
909 case 10: /* PL */
910 case 11: /* MI */
911 c->g1 = c->g2 = 0;
912 c->v2 = tcg_const_i32(0);
913 c->v1 = tmp = tcg_temp_new();
914 tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
915 gen_ext(tmp, tmp, op - CC_OP_CMPB, 1);
916 /* fallthru */
917 case 12: /* GE */
918 case 13: /* LT */
919 tcond = TCG_COND_LT;
920 goto done;
921 case 14: /* GT */
922 case 15: /* LE */
923 tcond = TCG_COND_LE;
924 goto done;
925 }
926 }
927
928 c->g1 = 1;
929 c->g2 = 0;
930 c->v2 = tcg_const_i32(0);
931
932 switch (cond) {
933 case 0: /* T */
934 case 1: /* F */
935 c->v1 = c->v2;
936 tcond = TCG_COND_NEVER;
937 goto done;
938 case 14: /* GT (!(Z || (N ^ V))) */
939 case 15: /* LE (Z || (N ^ V)) */
940 /* Logic operations clear V, which simplifies LE to (Z || N),
941 and since Z and N are co-located, this becomes a normal
942 comparison vs N. */
943 if (op == CC_OP_LOGIC) {
944 c->v1 = QREG_CC_N;
945 tcond = TCG_COND_LE;
946 goto done;
947 }
948 break;
949 case 12: /* GE (!(N ^ V)) */
950 case 13: /* LT (N ^ V) */
951 /* Logic operations clear V, which simplifies this to N. */
952 if (op != CC_OP_LOGIC) {
953 break;
954 }
955 /* fallthru */
956 case 10: /* PL (!N) */
957 case 11: /* MI (N) */
958 /* Several cases represent N normally. */
959 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
960 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
961 op == CC_OP_LOGIC) {
962 c->v1 = QREG_CC_N;
963 tcond = TCG_COND_LT;
964 goto done;
965 }
966 break;
967 case 6: /* NE (!Z) */
968 case 7: /* EQ (Z) */
969 /* Some cases fold Z into N. */
970 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
971 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
972 op == CC_OP_LOGIC) {
973 tcond = TCG_COND_EQ;
974 c->v1 = QREG_CC_N;
975 goto done;
976 }
977 break;
978 case 4: /* CC (!C) */
979 case 5: /* CS (C) */
980 /* Some cases fold C into X. */
981 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
982 op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL) {
983 tcond = TCG_COND_NE;
984 c->v1 = QREG_CC_X;
985 goto done;
986 }
987 /* fallthru */
988 case 8: /* VC (!V) */
989 case 9: /* VS (V) */
990 /* Logic operations clear V and C. */
991 if (op == CC_OP_LOGIC) {
992 tcond = TCG_COND_NEVER;
993 c->v1 = c->v2;
994 goto done;
995 }
996 break;
997 }
998
999 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1000 gen_flush_flags(s);
1001
1002 switch (cond) {
1003 case 0: /* T */
1004 case 1: /* F */
1005 default:
1006 /* Invalid, or handled above. */
1007 abort();
1008 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1009 case 3: /* LS (C || Z) */
1010 c->v1 = tmp = tcg_temp_new();
1011 c->g1 = 0;
1012 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1013 tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
1014 tcond = TCG_COND_NE;
1015 break;
1016 case 4: /* CC (!C) */
1017 case 5: /* CS (C) */
1018 c->v1 = QREG_CC_C;
1019 tcond = TCG_COND_NE;
1020 break;
1021 case 6: /* NE (!Z) */
1022 case 7: /* EQ (Z) */
1023 c->v1 = QREG_CC_Z;
1024 tcond = TCG_COND_EQ;
1025 break;
1026 case 8: /* VC (!V) */
1027 case 9: /* VS (V) */
1028 c->v1 = QREG_CC_V;
1029 tcond = TCG_COND_LT;
1030 break;
1031 case 10: /* PL (!N) */
1032 case 11: /* MI (N) */
1033 c->v1 = QREG_CC_N;
1034 tcond = TCG_COND_LT;
1035 break;
1036 case 12: /* GE (!(N ^ V)) */
1037 case 13: /* LT (N ^ V) */
1038 c->v1 = tmp = tcg_temp_new();
1039 c->g1 = 0;
1040 tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
1041 tcond = TCG_COND_LT;
1042 break;
1043 case 14: /* GT (!(Z || (N ^ V))) */
1044 case 15: /* LE (Z || (N ^ V)) */
1045 c->v1 = tmp = tcg_temp_new();
1046 c->g1 = 0;
1047 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1048 tcg_gen_neg_i32(tmp, tmp);
1049 tmp2 = tcg_temp_new();
1050 tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
1051 tcg_gen_or_i32(tmp, tmp, tmp2);
1052 tcg_temp_free(tmp2);
1053 tcond = TCG_COND_LT;
1054 break;
1055 }
1056
1057 done:
1058 if ((cond & 1) == 0) {
1059 tcond = tcg_invert_cond(tcond);
1060 }
1061 c->tcond = tcond;
1062 }
1063
1064 static void free_cond(DisasCompare *c)
1065 {
1066 if (!c->g1) {
1067 tcg_temp_free(c->v1);
1068 }
1069 if (!c->g2) {
1070 tcg_temp_free(c->v2);
1071 }
1072 }
1073
1074 static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
1075 {
1076 DisasCompare c;
1077
1078 gen_cc_cond(&c, s, cond);
1079 update_cc_op(s);
1080 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
1081 free_cond(&c);
1082 }
1083
1084 /* Force a TB lookup after an instruction that changes the CPU state. */
1085 static void gen_lookup_tb(DisasContext *s)
1086 {
1087 update_cc_op(s);
1088 tcg_gen_movi_i32(QREG_PC, s->pc);
1089 s->is_jmp = DISAS_UPDATE;
1090 }
1091
1092 /* Generate a jump to an immediate address. */
1093 static void gen_jmp_im(DisasContext *s, uint32_t dest)
1094 {
1095 update_cc_op(s);
1096 tcg_gen_movi_i32(QREG_PC, dest);
1097 s->is_jmp = DISAS_JUMP;
1098 }
1099
1100 /* Generate a jump to the address in qreg DEST. */
1101 static void gen_jmp(DisasContext *s, TCGv dest)
1102 {
1103 update_cc_op(s);
1104 tcg_gen_mov_i32(QREG_PC, dest);
1105 s->is_jmp = DISAS_JUMP;
1106 }
1107
1108 static void gen_exception(DisasContext *s, uint32_t where, int nr)
1109 {
1110 update_cc_op(s);
1111 gen_jmp_im(s, where);
1112 gen_helper_raise_exception(cpu_env, tcg_const_i32(nr));
1113 }
1114
1115 static inline void gen_addr_fault(DisasContext *s)
1116 {
1117 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
1118 }
1119
1120 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1121 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1122 op_sign ? EA_LOADS : EA_LOADU); \
1123 if (IS_NULL_QREG(result)) { \
1124 gen_addr_fault(s); \
1125 return; \
1126 } \
1127 } while (0)
1128
1129 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1130 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
1131 if (IS_NULL_QREG(ea_result)) { \
1132 gen_addr_fault(s); \
1133 return; \
1134 } \
1135 } while (0)
1136
1137 static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
1138 {
1139 #ifndef CONFIG_USER_ONLY
1140 return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
1141 (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
1142 #else
1143 return true;
1144 #endif
1145 }
1146
1147 /* Generate a jump to an immediate address. */
1148 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
1149 {
1150 if (unlikely(s->singlestep_enabled)) {
1151 gen_exception(s, dest, EXCP_DEBUG);
1152 } else if (use_goto_tb(s, dest)) {
1153 tcg_gen_goto_tb(n);
1154 tcg_gen_movi_i32(QREG_PC, dest);
1155 tcg_gen_exit_tb((uintptr_t)s->tb + n);
1156 } else {
1157 gen_jmp_im(s, dest);
1158 tcg_gen_exit_tb(0);
1159 }
1160 s->is_jmp = DISAS_TB_JUMP;
1161 }
1162
1163 DISAS_INSN(scc)
1164 {
1165 DisasCompare c;
1166 int cond;
1167 TCGv tmp;
1168
1169 cond = (insn >> 8) & 0xf;
1170 gen_cc_cond(&c, s, cond);
1171
1172 tmp = tcg_temp_new();
1173 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
1174 free_cond(&c);
1175
1176 tcg_gen_neg_i32(tmp, tmp);
1177 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
1178 tcg_temp_free(tmp);
1179 }
1180
1181 DISAS_INSN(dbcc)
1182 {
1183 TCGLabel *l1;
1184 TCGv reg;
1185 TCGv tmp;
1186 int16_t offset;
1187 uint32_t base;
1188
1189 reg = DREG(insn, 0);
1190 base = s->pc;
1191 offset = (int16_t)read_im16(env, s);
1192 l1 = gen_new_label();
1193 gen_jmpcc(s, (insn >> 8) & 0xf, l1);
1194
1195 tmp = tcg_temp_new();
1196 tcg_gen_ext16s_i32(tmp, reg);
1197 tcg_gen_addi_i32(tmp, tmp, -1);
1198 gen_partset_reg(OS_WORD, reg, tmp);
1199 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1);
1200 gen_jmp_tb(s, 1, base + offset);
1201 gen_set_label(l1);
1202 gen_jmp_tb(s, 0, s->pc);
1203 }
1204
1205 DISAS_INSN(undef_mac)
1206 {
1207 gen_exception(s, s->pc - 2, EXCP_LINEA);
1208 }
1209
1210 DISAS_INSN(undef_fpu)
1211 {
1212 gen_exception(s, s->pc - 2, EXCP_LINEF);
1213 }
1214
1215 DISAS_INSN(undef)
1216 {
1217 M68kCPU *cpu = m68k_env_get_cpu(env);
1218
1219 gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
1220 cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
1221 }
1222
1223 DISAS_INSN(mulw)
1224 {
1225 TCGv reg;
1226 TCGv tmp;
1227 TCGv src;
1228 int sign;
1229
1230 sign = (insn & 0x100) != 0;
1231 reg = DREG(insn, 9);
1232 tmp = tcg_temp_new();
1233 if (sign)
1234 tcg_gen_ext16s_i32(tmp, reg);
1235 else
1236 tcg_gen_ext16u_i32(tmp, reg);
1237 SRC_EA(env, src, OS_WORD, sign, NULL);
1238 tcg_gen_mul_i32(tmp, tmp, src);
1239 tcg_gen_mov_i32(reg, tmp);
1240 gen_logic_cc(s, tmp, OS_LONG);
1241 }
1242
1243 DISAS_INSN(divw)
1244 {
1245 int sign;
1246 TCGv src;
1247 TCGv destr;
1248
1249 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1250
1251 sign = (insn & 0x100) != 0;
1252
1253 /* dest.l / src.w */
1254
1255 SRC_EA(env, src, OS_WORD, sign, NULL);
1256 destr = tcg_const_i32(REG(insn, 9));
1257 if (sign) {
1258 gen_helper_divsw(cpu_env, destr, src);
1259 } else {
1260 gen_helper_divuw(cpu_env, destr, src);
1261 }
1262 tcg_temp_free(destr);
1263
1264 set_cc_op(s, CC_OP_FLAGS);
1265 }
1266
1267 DISAS_INSN(divl)
1268 {
1269 TCGv num, reg, den;
1270 int sign;
1271 uint16_t ext;
1272
1273 ext = read_im16(env, s);
1274
1275 sign = (ext & 0x0800) != 0;
1276
1277 if (ext & 0x400) {
1278 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
1279 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
1280 return;
1281 }
1282
1283 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1284
1285 SRC_EA(env, den, OS_LONG, 0, NULL);
1286 num = tcg_const_i32(REG(ext, 12));
1287 reg = tcg_const_i32(REG(ext, 0));
1288 if (sign) {
1289 gen_helper_divsll(cpu_env, num, reg, den);
1290 } else {
1291 gen_helper_divull(cpu_env, num, reg, den);
1292 }
1293 tcg_temp_free(reg);
1294 tcg_temp_free(num);
1295 set_cc_op(s, CC_OP_FLAGS);
1296 return;
1297 }
1298
1299 /* divX.l <EA>, Dq 32/32 -> 32q */
1300 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1301
1302 SRC_EA(env, den, OS_LONG, 0, NULL);
1303 num = tcg_const_i32(REG(ext, 12));
1304 reg = tcg_const_i32(REG(ext, 0));
1305 if (sign) {
1306 gen_helper_divsl(cpu_env, num, reg, den);
1307 } else {
1308 gen_helper_divul(cpu_env, num, reg, den);
1309 }
1310 tcg_temp_free(reg);
1311 tcg_temp_free(num);
1312
1313 set_cc_op(s, CC_OP_FLAGS);
1314 }
1315
1316 DISAS_INSN(addsub)
1317 {
1318 TCGv reg;
1319 TCGv dest;
1320 TCGv src;
1321 TCGv tmp;
1322 TCGv addr;
1323 int add;
1324 int opsize;
1325
1326 add = (insn & 0x4000) != 0;
1327 opsize = insn_opsize(insn);
1328 reg = gen_extend(DREG(insn, 9), opsize, 1);
1329 dest = tcg_temp_new();
1330 if (insn & 0x100) {
1331 SRC_EA(env, tmp, opsize, 1, &addr);
1332 src = reg;
1333 } else {
1334 tmp = reg;
1335 SRC_EA(env, src, opsize, 1, NULL);
1336 }
1337 if (add) {
1338 tcg_gen_add_i32(dest, tmp, src);
1339 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src);
1340 set_cc_op(s, CC_OP_ADDB + opsize);
1341 } else {
1342 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src);
1343 tcg_gen_sub_i32(dest, tmp, src);
1344 set_cc_op(s, CC_OP_SUBB + opsize);
1345 }
1346 gen_update_cc_add(dest, src, opsize);
1347 if (insn & 0x100) {
1348 DEST_EA(env, insn, opsize, dest, &addr);
1349 } else {
1350 gen_partset_reg(opsize, DREG(insn, 9), dest);
1351 }
1352 tcg_temp_free(dest);
1353 }
1354
1355 /* Reverse the order of the bits in REG. */
1356 DISAS_INSN(bitrev)
1357 {
1358 TCGv reg;
1359 reg = DREG(insn, 0);
1360 gen_helper_bitrev(reg, reg);
1361 }
1362
1363 DISAS_INSN(bitop_reg)
1364 {
1365 int opsize;
1366 int op;
1367 TCGv src1;
1368 TCGv src2;
1369 TCGv tmp;
1370 TCGv addr;
1371 TCGv dest;
1372
1373 if ((insn & 0x38) != 0)
1374 opsize = OS_BYTE;
1375 else
1376 opsize = OS_LONG;
1377 op = (insn >> 6) & 3;
1378 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1379
1380 gen_flush_flags(s);
1381 src2 = tcg_temp_new();
1382 if (opsize == OS_BYTE)
1383 tcg_gen_andi_i32(src2, DREG(insn, 9), 7);
1384 else
1385 tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
1386
1387 tmp = tcg_const_i32(1);
1388 tcg_gen_shl_i32(tmp, tmp, src2);
1389 tcg_temp_free(src2);
1390
1391 tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
1392
1393 dest = tcg_temp_new();
1394 switch (op) {
1395 case 1: /* bchg */
1396 tcg_gen_xor_i32(dest, src1, tmp);
1397 break;
1398 case 2: /* bclr */
1399 tcg_gen_andc_i32(dest, src1, tmp);
1400 break;
1401 case 3: /* bset */
1402 tcg_gen_or_i32(dest, src1, tmp);
1403 break;
1404 default: /* btst */
1405 break;
1406 }
1407 tcg_temp_free(tmp);
1408 if (op) {
1409 DEST_EA(env, insn, opsize, dest, &addr);
1410 }
1411 tcg_temp_free(dest);
1412 }
1413
1414 DISAS_INSN(sats)
1415 {
1416 TCGv reg;
1417 reg = DREG(insn, 0);
1418 gen_flush_flags(s);
1419 gen_helper_sats(reg, reg, QREG_CC_V);
1420 gen_logic_cc(s, reg, OS_LONG);
1421 }
1422
1423 static void gen_push(DisasContext *s, TCGv val)
1424 {
1425 TCGv tmp;
1426
1427 tmp = tcg_temp_new();
1428 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1429 gen_store(s, OS_LONG, tmp, val);
1430 tcg_gen_mov_i32(QREG_SP, tmp);
1431 }
1432
1433 DISAS_INSN(movem)
1434 {
1435 TCGv addr;
1436 int i;
1437 uint16_t mask;
1438 TCGv reg;
1439 TCGv tmp;
1440 int is_load;
1441
1442 mask = read_im16(env, s);
1443 tmp = gen_lea(env, s, insn, OS_LONG);
1444 if (IS_NULL_QREG(tmp)) {
1445 gen_addr_fault(s);
1446 return;
1447 }
1448 addr = tcg_temp_new();
1449 tcg_gen_mov_i32(addr, tmp);
1450 is_load = ((insn & 0x0400) != 0);
1451 for (i = 0; i < 16; i++, mask >>= 1) {
1452 if (mask & 1) {
1453 if (i < 8)
1454 reg = DREG(i, 0);
1455 else
1456 reg = AREG(i, 0);
1457 if (is_load) {
1458 tmp = gen_load(s, OS_LONG, addr, 0);
1459 tcg_gen_mov_i32(reg, tmp);
1460 } else {
1461 gen_store(s, OS_LONG, addr, reg);
1462 }
1463 if (mask != 1)
1464 tcg_gen_addi_i32(addr, addr, 4);
1465 }
1466 }
1467 }
1468
1469 DISAS_INSN(bitop_im)
1470 {
1471 int opsize;
1472 int op;
1473 TCGv src1;
1474 uint32_t mask;
1475 int bitnum;
1476 TCGv tmp;
1477 TCGv addr;
1478
1479 if ((insn & 0x38) != 0)
1480 opsize = OS_BYTE;
1481 else
1482 opsize = OS_LONG;
1483 op = (insn >> 6) & 3;
1484
1485 bitnum = read_im16(env, s);
1486 if (bitnum & 0xff00) {
1487 disas_undef(env, s, insn);
1488 return;
1489 }
1490
1491 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1492
1493 gen_flush_flags(s);
1494 if (opsize == OS_BYTE)
1495 bitnum &= 7;
1496 else
1497 bitnum &= 31;
1498 mask = 1 << bitnum;
1499
1500 tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
1501
1502 if (op) {
1503 tmp = tcg_temp_new();
1504 switch (op) {
1505 case 1: /* bchg */
1506 tcg_gen_xori_i32(tmp, src1, mask);
1507 break;
1508 case 2: /* bclr */
1509 tcg_gen_andi_i32(tmp, src1, ~mask);
1510 break;
1511 case 3: /* bset */
1512 tcg_gen_ori_i32(tmp, src1, mask);
1513 break;
1514 default: /* btst */
1515 break;
1516 }
1517 DEST_EA(env, insn, opsize, tmp, &addr);
1518 tcg_temp_free(tmp);
1519 }
1520 }
1521
1522 DISAS_INSN(arith_im)
1523 {
1524 int op;
1525 TCGv im;
1526 TCGv src1;
1527 TCGv dest;
1528 TCGv addr;
1529 int opsize;
1530
1531 op = (insn >> 9) & 7;
1532 opsize = insn_opsize(insn);
1533 switch (opsize) {
1534 case OS_BYTE:
1535 im = tcg_const_i32((int8_t)read_im8(env, s));
1536 break;
1537 case OS_WORD:
1538 im = tcg_const_i32((int16_t)read_im16(env, s));
1539 break;
1540 case OS_LONG:
1541 im = tcg_const_i32(read_im32(env, s));
1542 break;
1543 default:
1544 abort();
1545 }
1546 SRC_EA(env, src1, opsize, 1, (op == 6) ? NULL : &addr);
1547 dest = tcg_temp_new();
1548 switch (op) {
1549 case 0: /* ori */
1550 tcg_gen_or_i32(dest, src1, im);
1551 gen_logic_cc(s, dest, opsize);
1552 break;
1553 case 1: /* andi */
1554 tcg_gen_and_i32(dest, src1, im);
1555 gen_logic_cc(s, dest, opsize);
1556 break;
1557 case 2: /* subi */
1558 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im);
1559 tcg_gen_sub_i32(dest, src1, im);
1560 gen_update_cc_add(dest, im, opsize);
1561 set_cc_op(s, CC_OP_SUBB + opsize);
1562 break;
1563 case 3: /* addi */
1564 tcg_gen_add_i32(dest, src1, im);
1565 gen_update_cc_add(dest, im, opsize);
1566 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im);
1567 set_cc_op(s, CC_OP_ADDB + opsize);
1568 break;
1569 case 5: /* eori */
1570 tcg_gen_xor_i32(dest, src1, im);
1571 gen_logic_cc(s, dest, opsize);
1572 break;
1573 case 6: /* cmpi */
1574 gen_update_cc_cmp(s, src1, im, opsize);
1575 break;
1576 default:
1577 abort();
1578 }
1579 tcg_temp_free(im);
1580 if (op != 6) {
1581 DEST_EA(env, insn, opsize, dest, &addr);
1582 }
1583 tcg_temp_free(dest);
1584 }
1585
1586 DISAS_INSN(byterev)
1587 {
1588 TCGv reg;
1589
1590 reg = DREG(insn, 0);
1591 tcg_gen_bswap32_i32(reg, reg);
1592 }
1593
1594 DISAS_INSN(move)
1595 {
1596 TCGv src;
1597 TCGv dest;
1598 int op;
1599 int opsize;
1600
1601 switch (insn >> 12) {
1602 case 1: /* move.b */
1603 opsize = OS_BYTE;
1604 break;
1605 case 2: /* move.l */
1606 opsize = OS_LONG;
1607 break;
1608 case 3: /* move.w */
1609 opsize = OS_WORD;
1610 break;
1611 default:
1612 abort();
1613 }
1614 SRC_EA(env, src, opsize, 1, NULL);
1615 op = (insn >> 6) & 7;
1616 if (op == 1) {
1617 /* movea */
1618 /* The value will already have been sign extended. */
1619 dest = AREG(insn, 9);
1620 tcg_gen_mov_i32(dest, src);
1621 } else {
1622 /* normal move */
1623 uint16_t dest_ea;
1624 dest_ea = ((insn >> 9) & 7) | (op << 3);
1625 DEST_EA(env, dest_ea, opsize, src, NULL);
1626 /* This will be correct because loads sign extend. */
1627 gen_logic_cc(s, src, opsize);
1628 }
1629 }
1630
1631 DISAS_INSN(negx)
1632 {
1633 TCGv z;
1634 TCGv src;
1635 TCGv addr;
1636 int opsize;
1637
1638 opsize = insn_opsize(insn);
1639 SRC_EA(env, src, opsize, 1, &addr);
1640
1641 gen_flush_flags(s); /* compute old Z */
1642
1643 /* Perform substract with borrow.
1644 * (X, N) = -(src + X);
1645 */
1646
1647 z = tcg_const_i32(0);
1648 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z);
1649 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X);
1650 tcg_temp_free(z);
1651 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
1652
1653 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
1654
1655 /* Compute signed-overflow for negation. The normal formula for
1656 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
1657 * this simplies to res & src.
1658 */
1659
1660 tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src);
1661
1662 /* Copy the rest of the results into place. */
1663 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
1664 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
1665
1666 set_cc_op(s, CC_OP_FLAGS);
1667
1668 /* result is in QREG_CC_N */
1669
1670 DEST_EA(env, insn, opsize, QREG_CC_N, &addr);
1671 }
1672
1673 DISAS_INSN(lea)
1674 {
1675 TCGv reg;
1676 TCGv tmp;
1677
1678 reg = AREG(insn, 9);
1679 tmp = gen_lea(env, s, insn, OS_LONG);
1680 if (IS_NULL_QREG(tmp)) {
1681 gen_addr_fault(s);
1682 return;
1683 }
1684 tcg_gen_mov_i32(reg, tmp);
1685 }
1686
1687 DISAS_INSN(clr)
1688 {
1689 int opsize;
1690
1691 opsize = insn_opsize(insn);
1692 DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL);
1693 gen_logic_cc(s, tcg_const_i32(0), opsize);
1694 }
1695
1696 static TCGv gen_get_ccr(DisasContext *s)
1697 {
1698 TCGv dest;
1699
1700 gen_flush_flags(s);
1701 update_cc_op(s);
1702 dest = tcg_temp_new();
1703 gen_helper_get_ccr(dest, cpu_env);
1704 return dest;
1705 }
1706
1707 DISAS_INSN(move_from_ccr)
1708 {
1709 TCGv ccr;
1710
1711 ccr = gen_get_ccr(s);
1712 DEST_EA(env, insn, OS_WORD, ccr, NULL);
1713 }
1714
1715 DISAS_INSN(neg)
1716 {
1717 TCGv src1;
1718 TCGv dest;
1719 TCGv addr;
1720 int opsize;
1721
1722 opsize = insn_opsize(insn);
1723 SRC_EA(env, src1, opsize, 1, &addr);
1724 dest = tcg_temp_new();
1725 tcg_gen_neg_i32(dest, src1);
1726 set_cc_op(s, CC_OP_SUBB + opsize);
1727 gen_update_cc_add(dest, src1, opsize);
1728 tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0);
1729 DEST_EA(env, insn, opsize, dest, &addr);
1730 tcg_temp_free(dest);
1731 }
1732
1733 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
1734 {
1735 if (ccr_only) {
1736 tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0);
1737 tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0);
1738 tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1);
1739 tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
1740 tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
1741 } else {
1742 gen_helper_set_sr(cpu_env, tcg_const_i32(val));
1743 }
1744 set_cc_op(s, CC_OP_FLAGS);
1745 }
1746
1747 static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
1748 int ccr_only)
1749 {
1750 if ((insn & 0x38) == 0) {
1751 if (ccr_only) {
1752 gen_helper_set_ccr(cpu_env, DREG(insn, 0));
1753 } else {
1754 gen_helper_set_sr(cpu_env, DREG(insn, 0));
1755 }
1756 set_cc_op(s, CC_OP_FLAGS);
1757 } else if ((insn & 0x3f) == 0x3c) {
1758 uint16_t val;
1759 val = read_im16(env, s);
1760 gen_set_sr_im(s, val, ccr_only);
1761 } else {
1762 disas_undef(env, s, insn);
1763 }
1764 }
1765
1766
1767 DISAS_INSN(move_to_ccr)
1768 {
1769 gen_set_sr(env, s, insn, 1);
1770 }
1771
1772 DISAS_INSN(not)
1773 {
1774 TCGv src1;
1775 TCGv dest;
1776 TCGv addr;
1777 int opsize;
1778
1779 opsize = insn_opsize(insn);
1780 SRC_EA(env, src1, opsize, 1, &addr);
1781 dest = tcg_temp_new();
1782 tcg_gen_not_i32(dest, src1);
1783 DEST_EA(env, insn, opsize, dest, &addr);
1784 gen_logic_cc(s, dest, opsize);
1785 }
1786
1787 DISAS_INSN(swap)
1788 {
1789 TCGv src1;
1790 TCGv src2;
1791 TCGv reg;
1792
1793 src1 = tcg_temp_new();
1794 src2 = tcg_temp_new();
1795 reg = DREG(insn, 0);
1796 tcg_gen_shli_i32(src1, reg, 16);
1797 tcg_gen_shri_i32(src2, reg, 16);
1798 tcg_gen_or_i32(reg, src1, src2);
1799 gen_logic_cc(s, reg, OS_LONG);
1800 }
1801
1802 DISAS_INSN(bkpt)
1803 {
1804 gen_exception(s, s->pc - 2, EXCP_DEBUG);
1805 }
1806
1807 DISAS_INSN(pea)
1808 {
1809 TCGv tmp;
1810
1811 tmp = gen_lea(env, s, insn, OS_LONG);
1812 if (IS_NULL_QREG(tmp)) {
1813 gen_addr_fault(s);
1814 return;
1815 }
1816 gen_push(s, tmp);
1817 }
1818
1819 DISAS_INSN(ext)
1820 {
1821 int op;
1822 TCGv reg;
1823 TCGv tmp;
1824
1825 reg = DREG(insn, 0);
1826 op = (insn >> 6) & 7;
1827 tmp = tcg_temp_new();
1828 if (op == 3)
1829 tcg_gen_ext16s_i32(tmp, reg);
1830 else
1831 tcg_gen_ext8s_i32(tmp, reg);
1832 if (op == 2)
1833 gen_partset_reg(OS_WORD, reg, tmp);
1834 else
1835 tcg_gen_mov_i32(reg, tmp);
1836 gen_logic_cc(s, tmp, OS_LONG);
1837 }
1838
1839 DISAS_INSN(tst)
1840 {
1841 int opsize;
1842 TCGv tmp;
1843
1844 opsize = insn_opsize(insn);
1845 SRC_EA(env, tmp, opsize, 1, NULL);
1846 gen_logic_cc(s, tmp, opsize);
1847 }
1848
1849 DISAS_INSN(pulse)
1850 {
1851 /* Implemented as a NOP. */
1852 }
1853
1854 DISAS_INSN(illegal)
1855 {
1856 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
1857 }
1858
1859 /* ??? This should be atomic. */
1860 DISAS_INSN(tas)
1861 {
1862 TCGv dest;
1863 TCGv src1;
1864 TCGv addr;
1865
1866 dest = tcg_temp_new();
1867 SRC_EA(env, src1, OS_BYTE, 1, &addr);
1868 gen_logic_cc(s, src1, OS_BYTE);
1869 tcg_gen_ori_i32(dest, src1, 0x80);
1870 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1871 }
1872
1873 DISAS_INSN(mull)
1874 {
1875 uint16_t ext;
1876 TCGv src1;
1877 int sign;
1878
1879 ext = read_im16(env, s);
1880
1881 sign = ext & 0x800;
1882
1883 if (ext & 0x400) {
1884 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
1885 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
1886 return;
1887 }
1888
1889 SRC_EA(env, src1, OS_LONG, 0, NULL);
1890
1891 if (sign) {
1892 tcg_gen_muls2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
1893 } else {
1894 tcg_gen_mulu2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
1895 }
1896 /* if Dl == Dh, 68040 returns low word */
1897 tcg_gen_mov_i32(DREG(ext, 0), QREG_CC_N);
1898 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_Z);
1899 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N);
1900
1901 tcg_gen_movi_i32(QREG_CC_V, 0);
1902 tcg_gen_movi_i32(QREG_CC_C, 0);
1903
1904 set_cc_op(s, CC_OP_FLAGS);
1905 return;
1906 }
1907 SRC_EA(env, src1, OS_LONG, 0, NULL);
1908 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
1909 tcg_gen_movi_i32(QREG_CC_C, 0);
1910 if (sign) {
1911 tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
1912 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
1913 tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31);
1914 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z);
1915 } else {
1916 tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
1917 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
1918 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C);
1919 }
1920 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
1921 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N);
1922
1923 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
1924
1925 set_cc_op(s, CC_OP_FLAGS);
1926 } else {
1927 /* The upper 32 bits of the product are discarded, so
1928 muls.l and mulu.l are functionally equivalent. */
1929 tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12));
1930 gen_logic_cc(s, DREG(ext, 12), OS_LONG);
1931 }
1932 }
1933
1934 static void gen_link(DisasContext *s, uint16_t insn, int32_t offset)
1935 {
1936 TCGv reg;
1937 TCGv tmp;
1938
1939 reg = AREG(insn, 0);
1940 tmp = tcg_temp_new();
1941 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1942 gen_store(s, OS_LONG, tmp, reg);
1943 if ((insn & 7) != 7) {
1944 tcg_gen_mov_i32(reg, tmp);
1945 }
1946 tcg_gen_addi_i32(QREG_SP, tmp, offset);
1947 tcg_temp_free(tmp);
1948 }
1949
1950 DISAS_INSN(link)
1951 {
1952 int16_t offset;
1953
1954 offset = read_im16(env, s);
1955 gen_link(s, insn, offset);
1956 }
1957
1958 DISAS_INSN(linkl)
1959 {
1960 int32_t offset;
1961
1962 offset = read_im32(env, s);
1963 gen_link(s, insn, offset);
1964 }
1965
1966 DISAS_INSN(unlk)
1967 {
1968 TCGv src;
1969 TCGv reg;
1970 TCGv tmp;
1971
1972 src = tcg_temp_new();
1973 reg = AREG(insn, 0);
1974 tcg_gen_mov_i32(src, reg);
1975 tmp = gen_load(s, OS_LONG, src, 0);
1976 tcg_gen_mov_i32(reg, tmp);
1977 tcg_gen_addi_i32(QREG_SP, src, 4);
1978 }
1979
1980 DISAS_INSN(nop)
1981 {
1982 }
1983
1984 DISAS_INSN(rts)
1985 {
1986 TCGv tmp;
1987
1988 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
1989 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
1990 gen_jmp(s, tmp);
1991 }
1992
1993 DISAS_INSN(jump)
1994 {
1995 TCGv tmp;
1996
1997 /* Load the target address first to ensure correct exception
1998 behavior. */
1999 tmp = gen_lea(env, s, insn, OS_LONG);
2000 if (IS_NULL_QREG(tmp)) {
2001 gen_addr_fault(s);
2002 return;
2003 }
2004 if ((insn & 0x40) == 0) {
2005 /* jsr */
2006 gen_push(s, tcg_const_i32(s->pc));
2007 }
2008 gen_jmp(s, tmp);
2009 }
2010
2011 DISAS_INSN(addsubq)
2012 {
2013 TCGv src;
2014 TCGv dest;
2015 TCGv val;
2016 int imm;
2017 TCGv addr;
2018 int opsize;
2019
2020 if ((insn & 070) == 010) {
2021 /* Operation on address register is always long. */
2022 opsize = OS_LONG;
2023 } else {
2024 opsize = insn_opsize(insn);
2025 }
2026 SRC_EA(env, src, opsize, 1, &addr);
2027 imm = (insn >> 9) & 7;
2028 if (imm == 0) {
2029 imm = 8;
2030 }
2031 val = tcg_const_i32(imm);
2032 dest = tcg_temp_new();
2033 tcg_gen_mov_i32(dest, src);
2034 if ((insn & 0x38) == 0x08) {
2035 /* Don't update condition codes if the destination is an
2036 address register. */
2037 if (insn & 0x0100) {
2038 tcg_gen_sub_i32(dest, dest, val);
2039 } else {
2040 tcg_gen_add_i32(dest, dest, val);
2041 }
2042 } else {
2043 if (insn & 0x0100) {
2044 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
2045 tcg_gen_sub_i32(dest, dest, val);
2046 set_cc_op(s, CC_OP_SUBB + opsize);
2047 } else {
2048 tcg_gen_add_i32(dest, dest, val);
2049 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
2050 set_cc_op(s, CC_OP_ADDB + opsize);
2051 }
2052 gen_update_cc_add(dest, val, opsize);
2053 }
2054 DEST_EA(env, insn, opsize, dest, &addr);
2055 }
2056
2057 DISAS_INSN(tpf)
2058 {
2059 switch (insn & 7) {
2060 case 2: /* One extension word. */
2061 s->pc += 2;
2062 break;
2063 case 3: /* Two extension words. */
2064 s->pc += 4;
2065 break;
2066 case 4: /* No extension words. */
2067 break;
2068 default:
2069 disas_undef(env, s, insn);
2070 }
2071 }
2072
2073 DISAS_INSN(branch)
2074 {
2075 int32_t offset;
2076 uint32_t base;
2077 int op;
2078 TCGLabel *l1;
2079
2080 base = s->pc;
2081 op = (insn >> 8) & 0xf;
2082 offset = (int8_t)insn;
2083 if (offset == 0) {
2084 offset = (int16_t)read_im16(env, s);
2085 } else if (offset == -1) {
2086 offset = read_im32(env, s);
2087 }
2088 if (op == 1) {
2089 /* bsr */
2090 gen_push(s, tcg_const_i32(s->pc));
2091 }
2092 if (op > 1) {
2093 /* Bcc */
2094 l1 = gen_new_label();
2095 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
2096 gen_jmp_tb(s, 1, base + offset);
2097 gen_set_label(l1);
2098 gen_jmp_tb(s, 0, s->pc);
2099 } else {
2100 /* Unconditional branch. */
2101 gen_jmp_tb(s, 0, base + offset);
2102 }
2103 }
2104
2105 DISAS_INSN(moveq)
2106 {
2107 uint32_t val;
2108
2109 val = (int8_t)insn;
2110 tcg_gen_movi_i32(DREG(insn, 9), val);
2111 gen_logic_cc(s, tcg_const_i32(val), OS_LONG);
2112 }
2113
2114 DISAS_INSN(mvzs)
2115 {
2116 int opsize;
2117 TCGv src;
2118 TCGv reg;
2119
2120 if (insn & 0x40)
2121 opsize = OS_WORD;
2122 else
2123 opsize = OS_BYTE;
2124 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
2125 reg = DREG(insn, 9);
2126 tcg_gen_mov_i32(reg, src);
2127 gen_logic_cc(s, src, opsize);
2128 }
2129
2130 DISAS_INSN(or)
2131 {
2132 TCGv reg;
2133 TCGv dest;
2134 TCGv src;
2135 TCGv addr;
2136 int opsize;
2137
2138 opsize = insn_opsize(insn);
2139 reg = gen_extend(DREG(insn, 9), opsize, 0);
2140 dest = tcg_temp_new();
2141 if (insn & 0x100) {
2142 SRC_EA(env, src, opsize, 0, &addr);
2143 tcg_gen_or_i32(dest, src, reg);
2144 DEST_EA(env, insn, opsize, dest, &addr);
2145 } else {
2146 SRC_EA(env, src, opsize, 0, NULL);
2147 tcg_gen_or_i32(dest, src, reg);
2148 gen_partset_reg(opsize, DREG(insn, 9), dest);
2149 }
2150 gen_logic_cc(s, dest, opsize);
2151 }
2152
2153 DISAS_INSN(suba)
2154 {
2155 TCGv src;
2156 TCGv reg;
2157
2158 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
2159 reg = AREG(insn, 9);
2160 tcg_gen_sub_i32(reg, reg, src);
2161 }
2162
2163 static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
2164 {
2165 TCGv tmp;
2166
2167 gen_flush_flags(s); /* compute old Z */
2168
2169 /* Perform substract with borrow.
2170 * (X, N) = dest - (src + X);
2171 */
2172
2173 tmp = tcg_const_i32(0);
2174 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp);
2175 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X);
2176 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
2177 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
2178
2179 /* Compute signed-overflow for substract. */
2180
2181 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
2182 tcg_gen_xor_i32(tmp, dest, src);
2183 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp);
2184 tcg_temp_free(tmp);
2185
2186 /* Copy the rest of the results into place. */
2187 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
2188 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
2189
2190 set_cc_op(s, CC_OP_FLAGS);
2191
2192 /* result is in QREG_CC_N */
2193 }
2194
2195 DISAS_INSN(subx_reg)
2196 {
2197 TCGv dest;
2198 TCGv src;
2199 int opsize;
2200
2201 opsize = insn_opsize(insn);
2202
2203 src = gen_extend(DREG(insn, 0), opsize, 1);
2204 dest = gen_extend(DREG(insn, 9), opsize, 1);
2205
2206 gen_subx(s, src, dest, opsize);
2207
2208 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
2209 }
2210
2211 DISAS_INSN(subx_mem)
2212 {
2213 TCGv src;
2214 TCGv addr_src;
2215 TCGv dest;
2216 TCGv addr_dest;
2217 int opsize;
2218
2219 opsize = insn_opsize(insn);
2220
2221 addr_src = AREG(insn, 0);
2222 tcg_gen_subi_i32(addr_src, addr_src, opsize);
2223 src = gen_load(s, opsize, addr_src, 1);
2224
2225 addr_dest = AREG(insn, 9);
2226 tcg_gen_subi_i32(addr_dest, addr_dest, opsize);
2227 dest = gen_load(s, opsize, addr_dest, 1);
2228
2229 gen_subx(s, src, dest, opsize);
2230
2231 gen_store(s, opsize, addr_dest, QREG_CC_N);
2232 }
2233
2234 DISAS_INSN(mov3q)
2235 {
2236 TCGv src;
2237 int val;
2238
2239 val = (insn >> 9) & 7;
2240 if (val == 0)
2241 val = -1;
2242 src = tcg_const_i32(val);
2243 gen_logic_cc(s, src, OS_LONG);
2244 DEST_EA(env, insn, OS_LONG, src, NULL);
2245 }
2246
2247 DISAS_INSN(cmp)
2248 {
2249 TCGv src;
2250 TCGv reg;
2251 int opsize;
2252
2253 opsize = insn_opsize(insn);
2254 SRC_EA(env, src, opsize, 1, NULL);
2255 reg = gen_extend(DREG(insn, 9), opsize, 1);
2256 gen_update_cc_cmp(s, reg, src, opsize);
2257 }
2258
2259 DISAS_INSN(cmpa)
2260 {
2261 int opsize;
2262 TCGv src;
2263 TCGv reg;
2264
2265 if (insn & 0x100) {
2266 opsize = OS_LONG;
2267 } else {
2268 opsize = OS_WORD;
2269 }
2270 SRC_EA(env, src, opsize, 1, NULL);
2271 reg = AREG(insn, 9);
2272 gen_update_cc_cmp(s, reg, src, OS_LONG);
2273 }
2274
2275 DISAS_INSN(cmpm)
2276 {
2277 int opsize = insn_opsize(insn);
2278 TCGv src, dst;
2279
2280 /* Post-increment load (mode 3) from Ay. */
2281 src = gen_ea_mode(env, s, 3, REG(insn, 0), opsize,
2282 NULL_QREG, NULL, EA_LOADS);
2283 /* Post-increment load (mode 3) from Ax. */
2284 dst = gen_ea_mode(env, s, 3, REG(insn, 9), opsize,
2285 NULL_QREG, NULL, EA_LOADS);
2286
2287 gen_update_cc_cmp(s, dst, src, opsize);
2288 }
2289
2290 DISAS_INSN(eor)
2291 {
2292 TCGv src;
2293 TCGv dest;
2294 TCGv addr;
2295 int opsize;
2296
2297 opsize = insn_opsize(insn);
2298
2299 SRC_EA(env, src, opsize, 0, &addr);
2300 dest = tcg_temp_new();
2301 tcg_gen_xor_i32(dest, src, DREG(insn, 9));
2302 gen_logic_cc(s, dest, opsize);
2303 DEST_EA(env, insn, opsize, dest, &addr);
2304 }
2305
2306 static void do_exg(TCGv reg1, TCGv reg2)
2307 {
2308 TCGv temp = tcg_temp_new();
2309 tcg_gen_mov_i32(temp, reg1);
2310 tcg_gen_mov_i32(reg1, reg2);
2311 tcg_gen_mov_i32(reg2, temp);
2312 tcg_temp_free(temp);
2313 }
2314
2315 DISAS_INSN(exg_dd)
2316 {
2317 /* exchange Dx and Dy */
2318 do_exg(DREG(insn, 9), DREG(insn, 0));
2319 }
2320
2321 DISAS_INSN(exg_aa)
2322 {
2323 /* exchange Ax and Ay */
2324 do_exg(AREG(insn, 9), AREG(insn, 0));
2325 }
2326
2327 DISAS_INSN(exg_da)
2328 {
2329 /* exchange Dx and Ay */
2330 do_exg(DREG(insn, 9), AREG(insn, 0));
2331 }
2332
2333 DISAS_INSN(and)
2334 {
2335 TCGv src;
2336 TCGv reg;
2337 TCGv dest;
2338 TCGv addr;
2339 int opsize;
2340
2341 dest = tcg_temp_new();
2342
2343 opsize = insn_opsize(insn);
2344 reg = DREG(insn, 9);
2345 if (insn & 0x100) {
2346 SRC_EA(env, src, opsize, 0, &addr);
2347 tcg_gen_and_i32(dest, src, reg);
2348 DEST_EA(env, insn, opsize, dest, &addr);
2349 } else {
2350 SRC_EA(env, src, opsize, 0, NULL);
2351 tcg_gen_and_i32(dest, src, reg);
2352 gen_partset_reg(opsize, reg, dest);
2353 }
2354 tcg_temp_free(dest);
2355 gen_logic_cc(s, dest, opsize);
2356 }
2357
2358 DISAS_INSN(adda)
2359 {
2360 TCGv src;
2361 TCGv reg;
2362
2363 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
2364 reg = AREG(insn, 9);
2365 tcg_gen_add_i32(reg, reg, src);
2366 }
2367
2368 static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
2369 {
2370 TCGv tmp;
2371
2372 gen_flush_flags(s); /* compute old Z */
2373
2374 /* Perform addition with carry.
2375 * (X, N) = src + dest + X;
2376 */
2377
2378 tmp = tcg_const_i32(0);
2379 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp);
2380 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp);
2381 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
2382
2383 /* Compute signed-overflow for addition. */
2384
2385 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
2386 tcg_gen_xor_i32(tmp, dest, src);
2387 tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp);
2388 tcg_temp_free(tmp);
2389
2390 /* Copy the rest of the results into place. */
2391 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
2392 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
2393
2394 set_cc_op(s, CC_OP_FLAGS);
2395
2396 /* result is in QREG_CC_N */
2397 }
2398
2399 DISAS_INSN(addx_reg)
2400 {
2401 TCGv dest;
2402 TCGv src;
2403 int opsize;
2404
2405 opsize = insn_opsize(insn);
2406
2407 dest = gen_extend(DREG(insn, 9), opsize, 1);
2408 src = gen_extend(DREG(insn, 0), opsize, 1);
2409
2410 gen_addx(s, src, dest, opsize);
2411
2412 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
2413 }
2414
2415 DISAS_INSN(addx_mem)
2416 {
2417 TCGv src;
2418 TCGv addr_src;
2419 TCGv dest;
2420 TCGv addr_dest;
2421 int opsize;
2422
2423 opsize = insn_opsize(insn);
2424
2425 addr_src = AREG(insn, 0);
2426 tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize));
2427 src = gen_load(s, opsize, addr_src, 1);
2428
2429 addr_dest = AREG(insn, 9);
2430 tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize));
2431 dest = gen_load(s, opsize, addr_dest, 1);
2432
2433 gen_addx(s, src, dest, opsize);
2434
2435 gen_store(s, opsize, addr_dest, QREG_CC_N);
2436 }
2437
2438 /* TODO: This could be implemented without helper functions. */
2439 DISAS_INSN(shift_im)
2440 {
2441 TCGv reg;
2442 int tmp;
2443 TCGv shift;
2444
2445 set_cc_op(s, CC_OP_FLAGS);
2446
2447 reg = DREG(insn, 0);
2448 tmp = (insn >> 9) & 7;
2449 if (tmp == 0)
2450 tmp = 8;
2451 shift = tcg_const_i32(tmp);
2452 /* No need to flush flags becuse we know we will set C flag. */
2453 if (insn & 0x100) {
2454 gen_helper_shl_cc(reg, cpu_env, reg, shift);
2455 } else {
2456 if (insn & 8) {
2457 gen_helper_shr_cc(reg, cpu_env, reg, shift);
2458 } else {
2459 gen_helper_sar_cc(reg, cpu_env, reg, shift);
2460 }
2461 }
2462 }
2463
2464 DISAS_INSN(shift_reg)
2465 {
2466 TCGv reg;
2467 TCGv shift;
2468
2469 reg = DREG(insn, 0);
2470 shift = DREG(insn, 9);
2471 if (insn & 0x100) {
2472 gen_helper_shl_cc(reg, cpu_env, reg, shift);
2473 } else {
2474 if (insn & 8) {
2475 gen_helper_shr_cc(reg, cpu_env, reg, shift);
2476 } else {
2477 gen_helper_sar_cc(reg, cpu_env, reg, shift);
2478 }
2479 }
2480 set_cc_op(s, CC_OP_FLAGS);
2481 }
2482
2483 DISAS_INSN(ff1)
2484 {
2485 TCGv reg;
2486 reg = DREG(insn, 0);
2487 gen_logic_cc(s, reg, OS_LONG);
2488 gen_helper_ff1(reg, reg);
2489 }
2490
2491 static TCGv gen_get_sr(DisasContext *s)
2492 {
2493 TCGv ccr;
2494 TCGv sr;
2495
2496 ccr = gen_get_ccr(s);
2497 sr = tcg_temp_new();
2498 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
2499 tcg_gen_or_i32(sr, sr, ccr);
2500 return sr;
2501 }
2502
2503 DISAS_INSN(strldsr)
2504 {
2505 uint16_t ext;
2506 uint32_t addr;
2507
2508 addr = s->pc - 2;
2509 ext = read_im16(env, s);
2510 if (ext != 0x46FC) {
2511 gen_exception(s, addr, EXCP_UNSUPPORTED);
2512 return;
2513 }
2514 ext = read_im16(env, s);
2515 if (IS_USER(s) || (ext & SR_S) == 0) {
2516 gen_exception(s, addr, EXCP_PRIVILEGE);
2517 return;
2518 }
2519 gen_push(s, gen_get_sr(s));
2520 gen_set_sr_im(s, ext, 0);
2521 }
2522
2523 DISAS_INSN(move_from_sr)
2524 {
2525 TCGv sr;
2526
2527 if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) {
2528 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2529 return;
2530 }
2531 sr = gen_get_sr(s);
2532 DEST_EA(env, insn, OS_WORD, sr, NULL);
2533 }
2534
2535 DISAS_INSN(move_to_sr)
2536 {
2537 if (IS_USER(s)) {
2538 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2539 return;
2540 }
2541 gen_set_sr(env, s, insn, 0);
2542 gen_lookup_tb(s);
2543 }
2544
2545 DISAS_INSN(move_from_usp)
2546 {
2547 if (IS_USER(s)) {
2548 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2549 return;
2550 }
2551 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
2552 offsetof(CPUM68KState, sp[M68K_USP]));
2553 }
2554
2555 DISAS_INSN(move_to_usp)
2556 {
2557 if (IS_USER(s)) {
2558 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2559 return;
2560 }
2561 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
2562 offsetof(CPUM68KState, sp[M68K_USP]));
2563 }
2564
2565 DISAS_INSN(halt)
2566 {
2567 gen_exception(s, s->pc, EXCP_HALT_INSN);
2568 }
2569
2570 DISAS_INSN(stop)
2571 {
2572 uint16_t ext;
2573
2574 if (IS_USER(s)) {
2575 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2576 return;
2577 }
2578
2579 ext = read_im16(env, s);
2580
2581 gen_set_sr_im(s, ext, 0);
2582 tcg_gen_movi_i32(cpu_halted, 1);
2583 gen_exception(s, s->pc, EXCP_HLT);
2584 }
2585
2586 DISAS_INSN(rte)
2587 {
2588 if (IS_USER(s)) {
2589 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2590 return;
2591 }
2592 gen_exception(s, s->pc - 2, EXCP_RTE);
2593 }
2594
2595 DISAS_INSN(movec)
2596 {
2597 uint16_t ext;
2598 TCGv reg;
2599
2600 if (IS_USER(s)) {
2601 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2602 return;
2603 }
2604
2605 ext = read_im16(env, s);
2606
2607 if (ext & 0x8000) {
2608 reg = AREG(ext, 12);
2609 } else {
2610 reg = DREG(ext, 12);
2611 }
2612 gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg);
2613 gen_lookup_tb(s);
2614 }
2615
2616 DISAS_INSN(intouch)
2617 {
2618 if (IS_USER(s)) {
2619 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2620 return;
2621 }
2622 /* ICache fetch. Implement as no-op. */
2623 }
2624
2625 DISAS_INSN(cpushl)
2626 {
2627 if (IS_USER(s)) {
2628 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2629 return;
2630 }
2631 /* Cache push/invalidate. Implement as no-op. */
2632 }
2633
2634 DISAS_INSN(wddata)
2635 {
2636 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2637 }
2638
2639 DISAS_INSN(wdebug)
2640 {
2641 M68kCPU *cpu = m68k_env_get_cpu(env);
2642
2643 if (IS_USER(s)) {
2644 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2645 return;
2646 }
2647 /* TODO: Implement wdebug. */
2648 cpu_abort(CPU(cpu), "WDEBUG not implemented");
2649 }
2650
2651 DISAS_INSN(trap)
2652 {
2653 gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
2654 }
2655
2656 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2657 immediately before the next FP instruction is executed. */
2658 DISAS_INSN(fpu)
2659 {
2660 uint16_t ext;
2661 int32_t offset;
2662 int opmode;
2663 TCGv_i64 src;
2664 TCGv_i64 dest;
2665 TCGv_i64 res;
2666 TCGv tmp32;
2667 int round;
2668 int set_dest;
2669 int opsize;
2670
2671 ext = read_im16(env, s);
2672 opmode = ext & 0x7f;
2673 switch ((ext >> 13) & 7) {
2674 case 0: case 2:
2675 break;
2676 case 1:
2677 goto undef;
2678 case 3: /* fmove out */
2679 src = FREG(ext, 7);
2680 tmp32 = tcg_temp_new_i32();
2681 /* fmove */
2682 /* ??? TODO: Proper behavior on overflow. */
2683 switch ((ext >> 10) & 7) {
2684 case 0:
2685 opsize = OS_LONG;
2686 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2687 break;
2688 case 1:
2689 opsize = OS_SINGLE;
2690 gen_helper_f64_to_f32(tmp32, cpu_env, src);
2691 break;
2692 case 4:
2693 opsize = OS_WORD;
2694 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2695 break;
2696 case 5: /* OS_DOUBLE */
2697 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2698 switch ((insn >> 3) & 7) {
2699 case 2:
2700 case 3:
2701 break;
2702 case 4:
2703 tcg_gen_addi_i32(tmp32, tmp32, -8);
2704 break;
2705 case 5:
2706 offset = cpu_ldsw_code(env, s->pc);
2707 s->pc += 2;
2708 tcg_gen_addi_i32(tmp32, tmp32, offset);
2709 break;
2710 default:
2711 goto undef;
2712 }
2713 gen_store64(s, tmp32, src);
2714 switch ((insn >> 3) & 7) {
2715 case 3:
2716 tcg_gen_addi_i32(tmp32, tmp32, 8);
2717 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2718 break;
2719 case 4:
2720 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2721 break;
2722 }
2723 tcg_temp_free_i32(tmp32);
2724 return;
2725 case 6:
2726 opsize = OS_BYTE;
2727 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2728 break;
2729 default:
2730 goto undef;
2731 }
2732 DEST_EA(env, insn, opsize, tmp32, NULL);
2733 tcg_temp_free_i32(tmp32);
2734 return;
2735 case 4: /* fmove to control register. */
2736 switch ((ext >> 10) & 7) {
2737 case 4: /* FPCR */
2738 /* Not implemented. Ignore writes. */
2739 break;
2740 case 1: /* FPIAR */
2741 case 2: /* FPSR */
2742 default:
2743 cpu_abort(NULL, "Unimplemented: fmove to control %d",
2744 (ext >> 10) & 7);
2745 }
2746 break;
2747 case 5: /* fmove from control register. */
2748 switch ((ext >> 10) & 7) {
2749 case 4: /* FPCR */
2750 /* Not implemented. Always return zero. */
2751 tmp32 = tcg_const_i32(0);
2752 break;
2753 case 1: /* FPIAR */
2754 case 2: /* FPSR */
2755 default:
2756 cpu_abort(NULL, "Unimplemented: fmove from control %d",
2757 (ext >> 10) & 7);
2758 goto undef;
2759 }
2760 DEST_EA(env, insn, OS_LONG, tmp32, NULL);
2761 break;
2762 case 6: /* fmovem */
2763 case 7:
2764 {
2765 TCGv addr;
2766 uint16_t mask;
2767 int i;
2768 if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
2769 goto undef;
2770 tmp32 = gen_lea(env, s, insn, OS_LONG);
2771 if (IS_NULL_QREG(tmp32)) {
2772 gen_addr_fault(s);
2773 return;
2774 }
2775 addr = tcg_temp_new_i32();
2776 tcg_gen_mov_i32(addr, tmp32);
2777 mask = 0x80;
2778 for (i = 0; i < 8; i++) {
2779 if (ext & mask) {
2780 dest = FREG(i, 0);
2781 if (ext & (1 << 13)) {
2782 /* store */
2783 tcg_gen_qemu_stf64(dest, addr, IS_USER(s));
2784 } else {
2785 /* load */
2786 tcg_gen_qemu_ldf64(dest, addr, IS_USER(s));
2787 }
2788 if (ext & (mask - 1))
2789 tcg_gen_addi_i32(addr, addr, 8);
2790 }
2791 mask >>= 1;
2792 }
2793 tcg_temp_free_i32(addr);
2794 }
2795 return;
2796 }
2797 if (ext & (1 << 14)) {
2798 /* Source effective address. */
2799 switch ((ext >> 10) & 7) {
2800 case 0: opsize = OS_LONG; break;
2801 case 1: opsize = OS_SINGLE; break;
2802 case 4: opsize = OS_WORD; break;
2803 case 5: opsize = OS_DOUBLE; break;
2804 case 6: opsize = OS_BYTE; break;
2805 default:
2806 goto undef;
2807 }
2808 if (opsize == OS_DOUBLE) {
2809 tmp32 = tcg_temp_new_i32();
2810 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2811 switch ((insn >> 3) & 7) {
2812 case 2:
2813 case 3:
2814 break;
2815 case 4:
2816 tcg_gen_addi_i32(tmp32, tmp32, -8);
2817 break;
2818 case 5:
2819 offset = cpu_ldsw_code(env, s->pc);
2820 s->pc += 2;
2821 tcg_gen_addi_i32(tmp32, tmp32, offset);
2822 break;
2823 case 7:
2824 offset = cpu_ldsw_code(env, s->pc);
2825 offset += s->pc - 2;
2826 s->pc += 2;
2827 tcg_gen_addi_i32(tmp32, tmp32, offset);
2828 break;
2829 default:
2830 goto undef;
2831 }
2832 src = gen_load64(s, tmp32);
2833 switch ((insn >> 3) & 7) {
2834 case 3:
2835 tcg_gen_addi_i32(tmp32, tmp32, 8);
2836 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2837 break;
2838 case 4:
2839 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2840 break;
2841 }
2842 tcg_temp_free_i32(tmp32);
2843 } else {
2844 SRC_EA(env, tmp32, opsize, 1, NULL);
2845 src = tcg_temp_new_i64();
2846 switch (opsize) {
2847 case OS_LONG:
2848 case OS_WORD:
2849 case OS_BYTE:
2850 gen_helper_i32_to_f64(src, cpu_env, tmp32);
2851 break;
2852 case OS_SINGLE:
2853 gen_helper_f32_to_f64(src, cpu_env, tmp32);
2854 break;
2855 }
2856 }
2857 } else {
2858 /* Source register. */
2859 src = FREG(ext, 10);
2860 }
2861 dest = FREG(ext, 7);
2862 res = tcg_temp_new_i64();
2863 if (opmode != 0x3a)
2864 tcg_gen_mov_f64(res, dest);
2865 round = 1;
2866 set_dest = 1;
2867 switch (opmode) {
2868 case 0: case 0x40: case 0x44: /* fmove */
2869 tcg_gen_mov_f64(res, src);
2870 break;
2871 case 1: /* fint */
2872 gen_helper_iround_f64(res, cpu_env, src);
2873 round = 0;
2874 break;
2875 case 3: /* fintrz */
2876 gen_helper_itrunc_f64(res, cpu_env, src);
2877 round = 0;
2878 break;
2879 case 4: case 0x41: case 0x45: /* fsqrt */
2880 gen_helper_sqrt_f64(res, cpu_env, src);
2881 break;
2882 case 0x18: case 0x58: case 0x5c: /* fabs */
2883 gen_helper_abs_f64(res, src);
2884 break;
2885 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2886 gen_helper_chs_f64(res, src);
2887 break;
2888 case 0x20: case 0x60: case 0x64: /* fdiv */
2889 gen_helper_div_f64(res, cpu_env, res, src);
2890 break;
2891 case 0x22: case 0x62: case 0x66: /* fadd */
2892 gen_helper_add_f64(res, cpu_env, res, src);
2893 break;
2894 case 0x23: case 0x63: case 0x67: /* fmul */
2895 gen_helper_mul_f64(res, cpu_env, res, src);
2896 break;
2897 case 0x28: case 0x68: case 0x6c: /* fsub */
2898 gen_helper_sub_f64(res, cpu_env, res, src);
2899 break;
2900 case 0x38: /* fcmp */
2901 gen_helper_sub_cmp_f64(res, cpu_env, res, src);
2902 set_dest = 0;
2903 round = 0;
2904 break;
2905 case 0x3a: /* ftst */
2906 tcg_gen_mov_f64(res, src);
2907 set_dest = 0;
2908 round = 0;
2909 break;
2910 default:
2911 goto undef;
2912 }
2913 if (ext & (1 << 14)) {
2914 tcg_temp_free_i64(src);
2915 }
2916 if (round) {
2917 if (opmode & 0x40) {
2918 if ((opmode & 0x4) != 0)
2919 round = 0;
2920 } else if ((s->fpcr & M68K_FPCR_PREC) == 0) {
2921 round = 0;
2922 }
2923 }
2924 if (round) {
2925 TCGv tmp = tcg_temp_new_i32();
2926 gen_helper_f64_to_f32(tmp, cpu_env, res);
2927 gen_helper_f32_to_f64(res, cpu_env, tmp);
2928 tcg_temp_free_i32(tmp);
2929 }
2930 tcg_gen_mov_f64(QREG_FP_RESULT, res);
2931 if (set_dest) {
2932 tcg_gen_mov_f64(dest, res);
2933 }
2934 tcg_temp_free_i64(res);
2935 return;
2936 undef:
2937 /* FIXME: Is this right for offset addressing modes? */
2938 s->pc -= 2;
2939 disas_undef_fpu(env, s, insn);
2940 }
2941
2942 DISAS_INSN(fbcc)
2943 {
2944 uint32_t offset;
2945 uint32_t addr;
2946 TCGv flag;
2947 TCGLabel *l1;
2948
2949 addr = s->pc;
2950 offset = cpu_ldsw_code(env, s->pc);
2951 s->pc += 2;
2952 if (insn & (1 << 6)) {
2953 offset = (offset << 16) | read_im16(env, s);
2954 }
2955
2956 l1 = gen_new_label();
2957 /* TODO: Raise BSUN exception. */
2958 flag = tcg_temp_new();
2959 gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT);
2960 /* Jump to l1 if condition is true. */
2961 switch (insn & 0xf) {
2962 case 0: /* f */
2963 break;
2964 case 1: /* eq (=0) */
2965 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2966 break;
2967 case 2: /* ogt (=1) */
2968 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1);
2969 break;
2970 case 3: /* oge (=0 or =1) */
2971 tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1);
2972 break;
2973 case 4: /* olt (=-1) */
2974 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1);
2975 break;
2976 case 5: /* ole (=-1 or =0) */
2977 tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1);
2978 break;
2979 case 6: /* ogl (=-1 or =1) */
2980 tcg_gen_andi_i32(flag, flag, 1);
2981 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2982 break;
2983 case 7: /* or (=2) */
2984 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1);
2985 break;
2986 case 8: /* un (<2) */
2987 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1);
2988 break;
2989 case 9: /* ueq (=0 or =2) */
2990 tcg_gen_andi_i32(flag, flag, 1);
2991 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2992 break;
2993 case 10: /* ugt (>0) */
2994 tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1);
2995 break;
2996 case 11: /* uge (>=0) */
2997 tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1);
2998 break;
2999 case 12: /* ult (=-1 or =2) */
3000 tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1);
3001 break;
3002 case 13: /* ule (!=1) */
3003 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1);
3004 break;
3005 case 14: /* ne (!=0) */
3006 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
3007 break;
3008 case 15: /* t */
3009 tcg_gen_br(l1);
3010 break;
3011 }
3012 gen_jmp_tb(s, 0, s->pc);
3013 gen_set_label(l1);
3014 gen_jmp_tb(s, 1, addr + offset);
3015 }
3016
3017 DISAS_INSN(frestore)
3018 {
3019 M68kCPU *cpu = m68k_env_get_cpu(env);
3020
3021 /* TODO: Implement frestore. */
3022 cpu_abort(CPU(cpu), "FRESTORE not implemented");
3023 }
3024
3025 DISAS_INSN(fsave)
3026 {
3027 M68kCPU *cpu = m68k_env_get_cpu(env);
3028
3029 /* TODO: Implement fsave. */
3030 cpu_abort(CPU(cpu), "FSAVE not implemented");
3031 }
3032
3033 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
3034 {
3035 TCGv tmp = tcg_temp_new();
3036 if (s->env->macsr & MACSR_FI) {
3037 if (upper)
3038 tcg_gen_andi_i32(tmp, val, 0xffff0000);
3039 else
3040 tcg_gen_shli_i32(tmp, val, 16);
3041 } else if (s->env->macsr & MACSR_SU) {
3042 if (upper)
3043 tcg_gen_sari_i32(tmp, val, 16);
3044 else
3045 tcg_gen_ext16s_i32(tmp, val);
3046 } else {
3047 if (upper)
3048 tcg_gen_shri_i32(tmp, val, 16);
3049 else
3050 tcg_gen_ext16u_i32(tmp, val);
3051 }
3052 return tmp;
3053 }
3054
3055 static void gen_mac_clear_flags(void)
3056 {
3057 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
3058 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
3059 }
3060
3061 DISAS_INSN(mac)
3062 {
3063 TCGv rx;
3064 TCGv ry;
3065 uint16_t ext;
3066 int acc;
3067 TCGv tmp;
3068 TCGv addr;
3069 TCGv loadval;
3070 int dual;
3071 TCGv saved_flags;
3072
3073 if (!s->done_mac) {
3074 s->mactmp = tcg_temp_new_i64();
3075 s->done_mac = 1;
3076 }
3077
3078 ext = read_im16(env, s);
3079
3080 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
3081 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
3082 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
3083 disas_undef(env, s, insn);
3084 return;
3085 }
3086 if (insn & 0x30) {
3087 /* MAC with load. */
3088 tmp = gen_lea(env, s, insn, OS_LONG);
3089 addr = tcg_temp_new();
3090 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
3091 /* Load the value now to ensure correct exception behavior.
3092 Perform writeback after reading the MAC inputs. */
3093 loadval = gen_load(s, OS_LONG, addr, 0);
3094
3095 acc ^= 1;
3096 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
3097 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
3098 } else {
3099 loadval = addr = NULL_QREG;
3100 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
3101 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
3102 }
3103
3104 gen_mac_clear_flags();
3105 #if 0
3106 l1 = -1;
3107 /* Disabled because conditional branches clobber temporary vars. */
3108 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
3109 /* Skip the multiply if we know we will ignore it. */
3110 l1 = gen_new_label();
3111 tmp = tcg_temp_new();
3112 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
3113 gen_op_jmp_nz32(tmp, l1);
3114 }
3115 #endif
3116
3117 if ((ext & 0x0800) == 0) {
3118 /* Word. */
3119 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
3120 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
3121 }
3122 if (s->env->macsr & MACSR_FI) {
3123 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
3124 } else {
3125 if (s->env->macsr & MACSR_SU)
3126 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
3127 else
3128 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
3129 switch ((ext >> 9) & 3) {
3130 case 1:
3131 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
3132 break;
3133 case 3:
3134 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
3135 break;
3136 }
3137 }
3138
3139 if (dual) {
3140 /* Save the overflow flag from the multiply. */
3141 saved_flags = tcg_temp_new();
3142 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
3143 } else {
3144 saved_flags = NULL_QREG;
3145 }
3146
3147 #if 0
3148 /* Disabled because conditional branches clobber temporary vars. */
3149 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
3150 /* Skip the accumulate if the value is already saturated. */
3151 l1 = gen_new_label();
3152 tmp = tcg_temp_new();
3153 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
3154 gen_op_jmp_nz32(tmp, l1);
3155 }
3156 #endif
3157
3158 if (insn & 0x100)
3159 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
3160 else
3161 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
3162
3163 if (s->env->macsr & MACSR_FI)
3164 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
3165 else if (s->env->macsr & MACSR_SU)
3166 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
3167 else
3168 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
3169
3170 #if 0
3171 /* Disabled because conditional branches clobber temporary vars. */
3172 if (l1 != -1)
3173 gen_set_label(l1);
3174 #endif
3175
3176 if (dual) {
3177 /* Dual accumulate variant. */
3178 acc = (ext >> 2) & 3;
3179 /* Restore the overflow flag from the multiplier. */
3180 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
3181 #if 0
3182 /* Disabled because conditional branches clobber temporary vars. */
3183 if ((s->env->macsr & MACSR_OMC) != 0) {
3184 /* Skip the accumulate if the value is already saturated. */
3185 l1 = gen_new_label();
3186 tmp = tcg_temp_new();
3187 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
3188 gen_op_jmp_nz32(tmp, l1);
3189 }
3190 #endif
3191 if (ext & 2)
3192 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
3193 else
3194 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
3195 if (s->env->macsr & MACSR_FI)
3196 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
3197 else if (s->env->macsr & MACSR_SU)
3198 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
3199 else
3200 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
3201 #if 0
3202 /* Disabled because conditional branches clobber temporary vars. */
3203 if (l1 != -1)
3204 gen_set_label(l1);
3205 #endif
3206 }
3207 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
3208
3209 if (insn & 0x30) {
3210 TCGv rw;
3211 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
3212 tcg_gen_mov_i32(rw, loadval);
3213 /* FIXME: Should address writeback happen with the masked or
3214 unmasked value? */
3215 switch ((insn >> 3) & 7) {
3216 case 3: /* Post-increment. */
3217 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
3218 break;
3219 case 4: /* Pre-decrement. */
3220 tcg_gen_mov_i32(AREG(insn, 0), addr);
3221 }
3222 }
3223 }
3224
3225 DISAS_INSN(from_mac)
3226 {
3227 TCGv rx;
3228 TCGv_i64 acc;
3229 int accnum;
3230
3231 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
3232 accnum = (insn >> 9) & 3;
3233 acc = MACREG(accnum);
3234 if (s->env->macsr & MACSR_FI) {
3235 gen_helper_get_macf(rx, cpu_env, acc);
3236 } else if ((s->env->macsr & MACSR_OMC) == 0) {
3237 tcg_gen_extrl_i64_i32(rx, acc);
3238 } else if (s->env->macsr & MACSR_SU) {
3239 gen_helper_get_macs(rx, acc);
3240 } else {
3241 gen_helper_get_macu(rx, acc);
3242 }
3243 if (insn & 0x40) {
3244 tcg_gen_movi_i64(acc, 0);
3245 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
3246 }
3247 }
3248
3249 DISAS_INSN(move_mac)
3250 {
3251 /* FIXME: This can be done without a helper. */
3252 int src;
3253 TCGv dest;
3254 src = insn & 3;
3255 dest = tcg_const_i32((insn >> 9) & 3);
3256 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
3257 gen_mac_clear_flags();
3258 gen_helper_mac_set_flags(cpu_env, dest);
3259 }
3260
3261 DISAS_INSN(from_macsr)
3262 {
3263 TCGv reg;
3264
3265 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
3266 tcg_gen_mov_i32(reg, QREG_MACSR);
3267 }
3268
3269 DISAS_INSN(from_mask)
3270 {
3271 TCGv reg;
3272 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
3273 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
3274 }
3275
3276 DISAS_INSN(from_mext)
3277 {
3278 TCGv reg;
3279 TCGv acc;
3280 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
3281 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
3282 if (s->env->macsr & MACSR_FI)
3283 gen_helper_get_mac_extf(reg, cpu_env, acc);
3284 else
3285 gen_helper_get_mac_exti(reg, cpu_env, acc);
3286 }
3287
3288 DISAS_INSN(macsr_to_ccr)
3289 {
3290 TCGv tmp = tcg_temp_new();
3291 tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
3292 gen_helper_set_sr(cpu_env, tmp);
3293 tcg_temp_free(tmp);
3294 set_cc_op(s, CC_OP_FLAGS);
3295 }
3296
3297 DISAS_INSN(to_mac)
3298 {
3299 TCGv_i64 acc;
3300 TCGv val;
3301 int accnum;
3302 accnum = (insn >> 9) & 3;
3303 acc = MACREG(accnum);
3304 SRC_EA(env, val, OS_LONG, 0, NULL);
3305 if (s->env->macsr & MACSR_FI) {
3306 tcg_gen_ext_i32_i64(acc, val);
3307 tcg_gen_shli_i64(acc, acc, 8);
3308 } else if (s->env->macsr & MACSR_SU) {
3309 tcg_gen_ext_i32_i64(acc, val);
3310 } else {
3311 tcg_gen_extu_i32_i64(acc, val);
3312 }
3313 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
3314 gen_mac_clear_flags();
3315 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
3316 }
3317
3318 DISAS_INSN(to_macsr)
3319 {
3320 TCGv val;
3321 SRC_EA(env, val, OS_LONG, 0, NULL);
3322 gen_helper_set_macsr(cpu_env, val);
3323 gen_lookup_tb(s);
3324 }
3325
3326 DISAS_INSN(to_mask)
3327 {
3328 TCGv val;
3329 SRC_EA(env, val, OS_LONG, 0, NULL);
3330 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
3331 }
3332
3333 DISAS_INSN(to_mext)
3334 {
3335 TCGv val;
3336 TCGv acc;
3337 SRC_EA(env, val, OS_LONG, 0, NULL);
3338 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
3339 if (s->env->macsr & MACSR_FI)
3340 gen_helper_set_mac_extf(cpu_env, val, acc);
3341 else if (s->env->macsr & MACSR_SU)
3342 gen_helper_set_mac_exts(cpu_env, val, acc);
3343 else
3344 gen_helper_set_mac_extu(cpu_env, val, acc);
3345 }
3346
3347 static disas_proc opcode_table[65536];
3348
3349 static void
3350 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
3351 {
3352 int i;
3353 int from;
3354 int to;
3355
3356 /* Sanity check. All set bits must be included in the mask. */
3357 if (opcode & ~mask) {
3358 fprintf(stderr,
3359 "qemu internal error: bogus opcode definition %04x/%04x\n",
3360 opcode, mask);
3361 abort();
3362 }
3363 /* This could probably be cleverer. For now just optimize the case where
3364 the top bits are known. */
3365 /* Find the first zero bit in the mask. */
3366 i = 0x8000;
3367 while ((i & mask) != 0)
3368 i >>= 1;
3369 /* Iterate over all combinations of this and lower bits. */
3370 if (i == 0)
3371 i = 1;
3372 else
3373 i <<= 1;
3374 from = opcode & ~(i - 1);
3375 to = from + i;
3376 for (i = from; i < to; i++) {
3377 if ((i & mask) == opcode)
3378 opcode_table[i] = proc;
3379 }
3380 }
3381
3382 /* Register m68k opcode handlers. Order is important.
3383 Later insn override earlier ones. */
3384 void register_m68k_insns (CPUM68KState *env)
3385 {
3386 /* Build the opcode table only once to avoid
3387 multithreading issues. */
3388 if (opcode_table[0] != NULL) {
3389 return;
3390 }
3391
3392 /* use BASE() for instruction available
3393 * for CF_ISA_A and M68000.
3394 */
3395 #define BASE(name, opcode, mask) \
3396 register_opcode(disas_##name, 0x##opcode, 0x##mask)
3397 #define INSN(name, opcode, mask, feature) do { \
3398 if (m68k_feature(env, M68K_FEATURE_##feature)) \
3399 BASE(name, opcode, mask); \
3400 } while(0)
3401 BASE(undef, 0000, 0000);
3402 INSN(arith_im, 0080, fff8, CF_ISA_A);
3403 INSN(arith_im, 0000, ff00, M68000);
3404 INSN(undef, 00c0, ffc0, M68000);
3405 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
3406 BASE(bitop_reg, 0100, f1c0);
3407 BASE(bitop_reg, 0140, f1c0);
3408 BASE(bitop_reg, 0180, f1c0);
3409 BASE(bitop_reg, 01c0, f1c0);
3410 INSN(arith_im, 0280, fff8, CF_ISA_A);
3411 INSN(arith_im, 0200, ff00, M68000);
3412 INSN(undef, 02c0, ffc0, M68000);
3413 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
3414 INSN(arith_im, 0480, fff8, CF_ISA_A);
3415 INSN(arith_im, 0400, ff00, M68000);
3416 INSN(undef, 04c0, ffc0, M68000);
3417 INSN(arith_im, 0600, ff00, M68000);
3418 INSN(undef, 06c0, ffc0, M68000);
3419 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
3420 INSN(arith_im, 0680, fff8, CF_ISA_A);
3421 INSN(arith_im, 0c00, ff38, CF_ISA_A);
3422 INSN(arith_im, 0c00, ff00, M68000);
3423 BASE(bitop_im, 0800, ffc0);
3424 BASE(bitop_im, 0840, ffc0);
3425 BASE(bitop_im, 0880, ffc0);
3426 BASE(bitop_im, 08c0, ffc0);
3427 INSN(arith_im, 0a80, fff8, CF_ISA_A);
3428 INSN(arith_im, 0a00, ff00, M68000);
3429 BASE(move, 1000, f000);
3430 BASE(move, 2000, f000);
3431 BASE(move, 3000, f000);
3432 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
3433 INSN(negx, 4080, fff8, CF_ISA_A);
3434 INSN(negx, 4000, ff00, M68000);
3435 INSN(undef, 40c0, ffc0, M68000);
3436 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
3437 INSN(move_from_sr, 40c0, ffc0, M68000);
3438 BASE(lea, 41c0, f1c0);
3439 BASE(clr, 4200, ff00);
3440 BASE(undef, 42c0, ffc0);
3441 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
3442 INSN(move_from_ccr, 42c0, ffc0, M68000);
3443 INSN(neg, 4480, fff8, CF_ISA_A);
3444 INSN(neg, 4400, ff00, M68000);
3445 INSN(undef, 44c0, ffc0, M68000);
3446 BASE(move_to_ccr, 44c0, ffc0);
3447 INSN(not, 4680, fff8, CF_ISA_A);
3448 INSN(not, 4600, ff00, M68000);
3449 INSN(undef, 46c0, ffc0, M68000);
3450 INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
3451 INSN(linkl, 4808, fff8, M68000);
3452 BASE(pea, 4840, ffc0);
3453 BASE(swap, 4840, fff8);
3454 INSN(bkpt, 4848, fff8, BKPT);
3455 BASE(movem, 48c0, fbc0);
3456 BASE(ext, 4880, fff8);
3457 BASE(ext, 48c0, fff8);
3458 BASE(ext, 49c0, fff8);
3459 BASE(tst, 4a00, ff00);
3460 INSN(tas, 4ac0, ffc0, CF_ISA_B);
3461 INSN(tas, 4ac0, ffc0, M68000);
3462 INSN(halt, 4ac8, ffff, CF_ISA_A);
3463 INSN(pulse, 4acc, ffff, CF_ISA_A);
3464 BASE(illegal, 4afc, ffff);
3465 INSN(mull, 4c00, ffc0, CF_ISA_A);
3466 INSN(mull, 4c00, ffc0, LONG_MULDIV);
3467 INSN(divl, 4c40, ffc0, CF_ISA_A);
3468 INSN(divl, 4c40, ffc0, LONG_MULDIV);
3469 INSN(sats, 4c80, fff8, CF_ISA_B);
3470 BASE(trap, 4e40, fff0);
3471 BASE(link, 4e50, fff8);
3472 BASE(unlk, 4e58, fff8);
3473 INSN(move_to_usp, 4e60, fff8, USP);
3474 INSN(move_from_usp, 4e68, fff8, USP);
3475 BASE(nop, 4e71, ffff);
3476 BASE(stop, 4e72, ffff);
3477 BASE(rte, 4e73, ffff);
3478 BASE(rts, 4e75, ffff);
3479 INSN(movec, 4e7b, ffff, CF_ISA_A);
3480 BASE(jump, 4e80, ffc0);
3481 BASE(jump, 4ec0, ffc0);
3482 INSN(addsubq, 5000, f080, M68000);
3483 BASE(addsubq, 5080, f0c0);
3484 INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */
3485 INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */
3486 INSN(dbcc, 50c8, f0f8, M68000);
3487 INSN(tpf, 51f8, fff8, CF_ISA_A);
3488
3489 /* Branch instructions. */
3490 BASE(branch, 6000, f000);
3491 /* Disable long branch instructions, then add back the ones we want. */
3492 BASE(undef, 60ff, f0ff); /* All long branches. */
3493 INSN(branch, 60ff, f0ff, CF_ISA_B);
3494 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
3495 INSN(branch, 60ff, ffff, BRAL);
3496 INSN(branch, 60ff, f0ff, BCCL);
3497
3498 BASE(moveq, 7000, f100);
3499 INSN(mvzs, 7100, f100, CF_ISA_B);
3500 BASE(or, 8000, f000);
3501 BASE(divw, 80c0, f0c0);
3502 BASE(addsub, 9000, f000);
3503 INSN(undef, 90c0, f0c0, CF_ISA_A);
3504 INSN(subx_reg, 9180, f1f8, CF_ISA_A);
3505 INSN(subx_reg, 9100, f138, M68000);
3506 INSN(subx_mem, 9108, f138, M68000);
3507 INSN(suba, 91c0, f1c0, CF_ISA_A);
3508 INSN(suba, 90c0, f0c0, M68000);
3509
3510 BASE(undef_mac, a000, f000);
3511 INSN(mac, a000, f100, CF_EMAC);
3512 INSN(from_mac, a180, f9b0, CF_EMAC);
3513 INSN(move_mac, a110, f9fc, CF_EMAC);
3514 INSN(from_macsr,a980, f9f0, CF_EMAC);
3515 INSN(from_mask, ad80, fff0, CF_EMAC);
3516 INSN(from_mext, ab80, fbf0, CF_EMAC);
3517 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
3518 INSN(to_mac, a100, f9c0, CF_EMAC);
3519 INSN(to_macsr, a900, ffc0, CF_EMAC);
3520 INSN(to_mext, ab00, fbc0, CF_EMAC);
3521 INSN(to_mask, ad00, ffc0, CF_EMAC);
3522
3523 INSN(mov3q, a140, f1c0, CF_ISA_B);
3524 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
3525 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
3526 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
3527 INSN(cmp, b080, f1c0, CF_ISA_A);
3528 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
3529 INSN(cmp, b000, f100, M68000);
3530 INSN(eor, b100, f100, M68000);
3531 INSN(cmpm, b108, f138, M68000);
3532 INSN(cmpa, b0c0, f0c0, M68000);
3533 INSN(eor, b180, f1c0, CF_ISA_A);
3534 BASE(and, c000, f000);
3535 INSN(exg_dd, c140, f1f8, M68000);
3536 INSN(exg_aa, c148, f1f8, M68000);
3537 INSN(exg_da, c188, f1f8, M68000);
3538 BASE(mulw, c0c0, f0c0);
3539 BASE(addsub, d000, f000);
3540 INSN(undef, d0c0, f0c0, CF_ISA_A);
3541 INSN(addx_reg, d180, f1f8, CF_ISA_A);
3542 INSN(addx_reg, d100, f138, M68000);
3543 INSN(addx_mem, d108, f138, M68000);
3544 INSN(adda, d1c0, f1c0, CF_ISA_A);
3545 INSN(adda, d0c0, f0c0, M68000);
3546 INSN(shift_im, e080, f0f0, CF_ISA_A);
3547 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
3548 INSN(undef_fpu, f000, f000, CF_ISA_A);
3549 INSN(fpu, f200, ffc0, CF_FPU);
3550 INSN(fbcc, f280, ffc0, CF_FPU);
3551 INSN(frestore, f340, ffc0, CF_FPU);
3552 INSN(fsave, f340, ffc0, CF_FPU);
3553 INSN(intouch, f340, ffc0, CF_ISA_A);
3554 INSN(cpushl, f428, ff38, CF_ISA_A);
3555 INSN(wddata, fb00, ff00, CF_ISA_A);
3556 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
3557 #undef INSN
3558 }
3559
3560 /* ??? Some of this implementation is not exception safe. We should always
3561 write back the result to memory before setting the condition codes. */
3562 static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
3563 {
3564 uint16_t insn = read_im16(env, s);
3565 opcode_table[insn](env, s, insn);
3566 do_writebacks(s);
3567 }
3568
3569 /* generate intermediate code for basic block 'tb'. */
3570 void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
3571 {
3572 M68kCPU *cpu = m68k_env_get_cpu(env);
3573 CPUState *cs = CPU(cpu);
3574 DisasContext dc1, *dc = &dc1;
3575 target_ulong pc_start;
3576 int pc_offset;
3577 int num_insns;
3578 int max_insns;
3579
3580 /* generate intermediate code */
3581 pc_start = tb->pc;
3582
3583 dc->tb = tb;
3584
3585 dc->env = env;
3586 dc->is_jmp = DISAS_NEXT;
3587 dc->pc = pc_start;
3588 dc->cc_op = CC_OP_DYNAMIC;
3589 dc->cc_op_synced = 1;
3590 dc->singlestep_enabled = cs->singlestep_enabled;
3591 dc->fpcr = env->fpcr;
3592 dc->user = (env->sr & SR_S) == 0;
3593 dc->done_mac = 0;
3594 dc->writeback_mask = 0;
3595 num_insns = 0;
3596 max_insns = tb->cflags & CF_COUNT_MASK;
3597 if (max_insns == 0) {
3598 max_insns = CF_COUNT_MASK;
3599 }
3600 if (max_insns > TCG_MAX_INSNS) {
3601 max_insns = TCG_MAX_INSNS;
3602 }
3603
3604 gen_tb_start(tb);
3605 do {
3606 pc_offset = dc->pc - pc_start;
3607 gen_throws_exception = NULL;
3608 tcg_gen_insn_start(dc->pc, dc->cc_op);
3609 num_insns++;
3610
3611 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
3612 gen_exception(dc, dc->pc, EXCP_DEBUG);
3613 dc->is_jmp = DISAS_JUMP;
3614 /* The address covered by the breakpoint must be included in
3615 [tb->pc, tb->pc + tb->size) in order to for it to be
3616 properly cleared -- thus we increment the PC here so that
3617 the logic setting tb->size below does the right thing. */
3618 dc->pc += 2;
3619 break;
3620 }
3621
3622 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
3623 gen_io_start();
3624 }
3625
3626 dc->insn_pc = dc->pc;
3627 disas_m68k_insn(env, dc);
3628 } while (!dc->is_jmp && !tcg_op_buf_full() &&
3629 !cs->singlestep_enabled &&
3630 !singlestep &&
3631 (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
3632 num_insns < max_insns);
3633
3634 if (tb->cflags & CF_LAST_IO)
3635 gen_io_end();
3636 if (unlikely(cs->singlestep_enabled)) {
3637 /* Make sure the pc is updated, and raise a debug exception. */
3638 if (!dc->is_jmp) {
3639 update_cc_op(dc);
3640 tcg_gen_movi_i32(QREG_PC, dc->pc);
3641 }
3642 gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
3643 } else {
3644 switch(dc->is_jmp) {
3645 case DISAS_NEXT:
3646 update_cc_op(dc);
3647 gen_jmp_tb(dc, 0, dc->pc);
3648 break;
3649 default:
3650 case DISAS_JUMP:
3651 case DISAS_UPDATE:
3652 update_cc_op(dc);
3653 /* indicate that the hash table must be used to find the next TB */
3654 tcg_gen_exit_tb(0);
3655 break;
3656 case DISAS_TB_JUMP:
3657 /* nothing more to generate */
3658 break;
3659 }
3660 }
3661 gen_tb_end(tb, num_insns);
3662
3663 #ifdef DEBUG_DISAS
3664 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
3665 && qemu_log_in_addr_range(pc_start)) {
3666 qemu_log_lock();
3667 qemu_log("----------------\n");
3668 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3669 log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
3670 qemu_log("\n");
3671 qemu_log_unlock();
3672 }
3673 #endif
3674 tb->size = dc->pc - pc_start;
3675 tb->icount = num_insns;
3676 }
3677
3678 void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3679 int flags)
3680 {
3681 M68kCPU *cpu = M68K_CPU(cs);
3682 CPUM68KState *env = &cpu->env;
3683 int i;
3684 uint16_t sr;
3685 CPU_DoubleU u;
3686 for (i = 0; i < 8; i++)
3687 {
3688 u.d = env->fregs[i];
3689 cpu_fprintf(f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3690 i, env->dregs[i], i, env->aregs[i],
3691 i, u.l.upper, u.l.lower, *(double *)&u.d);
3692 }
3693 cpu_fprintf (f, "PC = %08x ", env->pc);
3694 sr = env->sr | cpu_m68k_get_ccr(env);
3695 cpu_fprintf(f, "SR = %04x %c%c%c%c%c ", sr, (sr & CCF_X) ? 'X' : '-',
3696 (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
3697 (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
3698 cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result);
3699 }
3700
3701 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
3702 target_ulong *data)
3703 {
3704 int cc_op = data[1];
3705 env->pc = data[0];
3706 if (cc_op != CC_OP_DYNAMIC) {
3707 env->cc_op = cc_op;
3708 }
3709 }
AR7 emulation for QEMU