target/arm: Enforce alignment for sve LD1R
[qemu/ar7.git] / accel / tcg / tcg-accel-ops-icount.h
blobd884aa2aaacb13f7db26854e9c5411c0900ddac2
1 /*
2 * QEMU TCG Single Threaded vCPUs implementation using instruction counting
4 * Copyright 2020 SUSE LLC
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 */
10 #ifndef TCG_CPUS_ICOUNT_H
11 #define TCG_CPUS_ICOUNT_H
13 void icount_handle_deadline(void);
14 void icount_prepare_for_run(CPUState *cpu);
15 void icount_process_data(CPUState *cpu);
17 void icount_handle_interrupt(CPUState *cpu, int mask);
19 #endif /* TCG_CPUS_ICOUNT_H */