4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
22 #include "qemu/cutils.h"
24 #include "exec/exec-all.h"
25 #include "exec/target_page.h"
27 #include "hw/qdev-core.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #if defined(CONFIG_USER_ONLY)
40 #else /* !CONFIG_USER_ONLY */
42 #include "exec/memory.h"
43 #include "exec/ioport.h"
44 #include "sysemu/dma.h"
45 #include "sysemu/numa.h"
46 #include "sysemu/hw_accel.h"
47 #include "exec/address-spaces.h"
48 #include "sysemu/xen-mapcache.h"
49 #include "trace-root.h"
51 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
52 #include <linux/falloc.h>
56 #include "qemu/rcu_queue.h"
57 #include "qemu/main-loop.h"
58 #include "translate-all.h"
59 #include "sysemu/replay.h"
61 #include "exec/memory-internal.h"
62 #include "exec/ram_addr.h"
65 #include "migration/vmstate.h"
67 #include "qemu/range.h"
69 #include "qemu/mmap-alloc.h"
72 #include "monitor/monitor.h"
74 //#define DEBUG_SUBPAGE
76 #if !defined(CONFIG_USER_ONLY)
77 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
78 * are protected by the ramlist lock.
80 RAMList ram_list
= { .blocks
= QLIST_HEAD_INITIALIZER(ram_list
.blocks
) };
82 static MemoryRegion
*system_memory
;
83 static MemoryRegion
*system_io
;
85 AddressSpace address_space_io
;
86 AddressSpace address_space_memory
;
88 MemoryRegion io_mem_rom
, io_mem_notdirty
;
89 static MemoryRegion io_mem_unassigned
;
91 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
92 #define RAM_PREALLOC (1 << 0)
94 /* RAM is mmap-ed with MAP_SHARED */
95 #define RAM_SHARED (1 << 1)
97 /* Only a portion of RAM (used_length) is actually used, and migrated.
98 * This used_length size can change across reboots.
100 #define RAM_RESIZEABLE (1 << 2)
102 /* UFFDIO_ZEROPAGE is available on this RAMBlock to atomically
103 * zero the page and wake waiting processes.
104 * (Set during postcopy)
106 #define RAM_UF_ZEROPAGE (1 << 3)
108 /* RAM can be migrated */
109 #define RAM_MIGRATABLE (1 << 4)
112 #ifdef TARGET_PAGE_BITS_VARY
113 int target_page_bits
;
114 bool target_page_bits_decided
;
117 struct CPUTailQ cpus
= QTAILQ_HEAD_INITIALIZER(cpus
);
118 /* current CPU in the current thread. It is only valid inside
120 __thread CPUState
*current_cpu
;
121 /* 0 = Do not count executed instructions.
122 1 = Precise instruction counting.
123 2 = Adaptive rate instruction counting. */
126 uintptr_t qemu_host_page_size
;
127 intptr_t qemu_host_page_mask
;
129 bool set_preferred_target_page_bits(int bits
)
131 /* The target page size is the lowest common denominator for all
132 * the CPUs in the system, so we can only make it smaller, never
133 * larger. And we can't make it smaller once we've committed to
136 #ifdef TARGET_PAGE_BITS_VARY
137 assert(bits
>= TARGET_PAGE_BITS_MIN
);
138 if (target_page_bits
== 0 || target_page_bits
> bits
) {
139 if (target_page_bits_decided
) {
142 target_page_bits
= bits
;
148 #if !defined(CONFIG_USER_ONLY)
150 static void finalize_target_page_bits(void)
152 #ifdef TARGET_PAGE_BITS_VARY
153 if (target_page_bits
== 0) {
154 target_page_bits
= TARGET_PAGE_BITS_MIN
;
156 target_page_bits_decided
= true;
160 typedef struct PhysPageEntry PhysPageEntry
;
162 struct PhysPageEntry
{
163 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
165 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
169 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
171 /* Size of the L2 (and L3, etc) page tables. */
172 #define ADDR_SPACE_BITS 64
175 #define P_L2_SIZE (1 << P_L2_BITS)
177 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
179 typedef PhysPageEntry Node
[P_L2_SIZE
];
181 typedef struct PhysPageMap
{
184 unsigned sections_nb
;
185 unsigned sections_nb_alloc
;
187 unsigned nodes_nb_alloc
;
189 MemoryRegionSection
*sections
;
192 struct AddressSpaceDispatch
{
193 MemoryRegionSection
*mru_section
;
194 /* This is a multi-level map on the physical address space.
195 * The bottom level has pointers to MemoryRegionSections.
197 PhysPageEntry phys_map
;
201 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
202 typedef struct subpage_t
{
206 uint16_t sub_section
[];
209 #define PHYS_SECTION_UNASSIGNED 0
210 #define PHYS_SECTION_NOTDIRTY 1
211 #define PHYS_SECTION_ROM 2
212 #define PHYS_SECTION_WATCH 3
214 static void io_mem_init(void);
215 static void memory_map_init(void);
216 static void tcg_commit(MemoryListener
*listener
);
218 static MemoryRegion io_mem_watch
;
221 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
222 * @cpu: the CPU whose AddressSpace this is
223 * @as: the AddressSpace itself
224 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
225 * @tcg_as_listener: listener for tracking changes to the AddressSpace
227 struct CPUAddressSpace
{
230 struct AddressSpaceDispatch
*memory_dispatch
;
231 MemoryListener tcg_as_listener
;
234 struct DirtyBitmapSnapshot
{
237 unsigned long dirty
[];
242 #if !defined(CONFIG_USER_ONLY)
244 static void phys_map_node_reserve(PhysPageMap
*map
, unsigned nodes
)
246 static unsigned alloc_hint
= 16;
247 if (map
->nodes_nb
+ nodes
> map
->nodes_nb_alloc
) {
248 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, alloc_hint
);
249 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, map
->nodes_nb
+ nodes
);
250 map
->nodes
= g_renew(Node
, map
->nodes
, map
->nodes_nb_alloc
);
251 alloc_hint
= map
->nodes_nb_alloc
;
255 static uint32_t phys_map_node_alloc(PhysPageMap
*map
, bool leaf
)
262 ret
= map
->nodes_nb
++;
264 assert(ret
!= PHYS_MAP_NODE_NIL
);
265 assert(ret
!= map
->nodes_nb_alloc
);
267 e
.skip
= leaf
? 0 : 1;
268 e
.ptr
= leaf
? PHYS_SECTION_UNASSIGNED
: PHYS_MAP_NODE_NIL
;
269 for (i
= 0; i
< P_L2_SIZE
; ++i
) {
270 memcpy(&p
[i
], &e
, sizeof(e
));
275 static void phys_page_set_level(PhysPageMap
*map
, PhysPageEntry
*lp
,
276 hwaddr
*index
, hwaddr
*nb
, uint16_t leaf
,
280 hwaddr step
= (hwaddr
)1 << (level
* P_L2_BITS
);
282 if (lp
->skip
&& lp
->ptr
== PHYS_MAP_NODE_NIL
) {
283 lp
->ptr
= phys_map_node_alloc(map
, level
== 0);
285 p
= map
->nodes
[lp
->ptr
];
286 lp
= &p
[(*index
>> (level
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
288 while (*nb
&& lp
< &p
[P_L2_SIZE
]) {
289 if ((*index
& (step
- 1)) == 0 && *nb
>= step
) {
295 phys_page_set_level(map
, lp
, index
, nb
, leaf
, level
- 1);
301 static void phys_page_set(AddressSpaceDispatch
*d
,
302 hwaddr index
, hwaddr nb
,
305 /* Wildly overreserve - it doesn't matter much. */
306 phys_map_node_reserve(&d
->map
, 3 * P_L2_LEVELS
);
308 phys_page_set_level(&d
->map
, &d
->phys_map
, &index
, &nb
, leaf
, P_L2_LEVELS
- 1);
311 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
312 * and update our entry so we can skip it and go directly to the destination.
314 static void phys_page_compact(PhysPageEntry
*lp
, Node
*nodes
)
316 unsigned valid_ptr
= P_L2_SIZE
;
321 if (lp
->ptr
== PHYS_MAP_NODE_NIL
) {
326 for (i
= 0; i
< P_L2_SIZE
; i
++) {
327 if (p
[i
].ptr
== PHYS_MAP_NODE_NIL
) {
334 phys_page_compact(&p
[i
], nodes
);
338 /* We can only compress if there's only one child. */
343 assert(valid_ptr
< P_L2_SIZE
);
345 /* Don't compress if it won't fit in the # of bits we have. */
346 if (lp
->skip
+ p
[valid_ptr
].skip
>= (1 << 3)) {
350 lp
->ptr
= p
[valid_ptr
].ptr
;
351 if (!p
[valid_ptr
].skip
) {
352 /* If our only child is a leaf, make this a leaf. */
353 /* By design, we should have made this node a leaf to begin with so we
354 * should never reach here.
355 * But since it's so simple to handle this, let's do it just in case we
360 lp
->skip
+= p
[valid_ptr
].skip
;
364 void address_space_dispatch_compact(AddressSpaceDispatch
*d
)
366 if (d
->phys_map
.skip
) {
367 phys_page_compact(&d
->phys_map
, d
->map
.nodes
);
371 static inline bool section_covers_addr(const MemoryRegionSection
*section
,
374 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
375 * the section must cover the entire address space.
377 return int128_gethi(section
->size
) ||
378 range_covers_byte(section
->offset_within_address_space
,
379 int128_getlo(section
->size
), addr
);
382 static MemoryRegionSection
*phys_page_find(AddressSpaceDispatch
*d
, hwaddr addr
)
384 PhysPageEntry lp
= d
->phys_map
, *p
;
385 Node
*nodes
= d
->map
.nodes
;
386 MemoryRegionSection
*sections
= d
->map
.sections
;
387 hwaddr index
= addr
>> TARGET_PAGE_BITS
;
390 for (i
= P_L2_LEVELS
; lp
.skip
&& (i
-= lp
.skip
) >= 0;) {
391 if (lp
.ptr
== PHYS_MAP_NODE_NIL
) {
392 return §ions
[PHYS_SECTION_UNASSIGNED
];
395 lp
= p
[(index
>> (i
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
398 if (section_covers_addr(§ions
[lp
.ptr
], addr
)) {
399 return §ions
[lp
.ptr
];
401 return §ions
[PHYS_SECTION_UNASSIGNED
];
405 bool memory_region_is_unassigned(MemoryRegion
*mr
)
407 return mr
!= &io_mem_rom
&& mr
!= &io_mem_notdirty
&& !mr
->rom_device
408 && mr
!= &io_mem_watch
;
411 /* Called from RCU critical section */
412 static MemoryRegionSection
*address_space_lookup_region(AddressSpaceDispatch
*d
,
414 bool resolve_subpage
)
416 MemoryRegionSection
*section
= atomic_read(&d
->mru_section
);
419 if (!section
|| section
== &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
] ||
420 !section_covers_addr(section
, addr
)) {
421 section
= phys_page_find(d
, addr
);
422 atomic_set(&d
->mru_section
, section
);
424 if (resolve_subpage
&& section
->mr
->subpage
) {
425 subpage
= container_of(section
->mr
, subpage_t
, iomem
);
426 section
= &d
->map
.sections
[subpage
->sub_section
[SUBPAGE_IDX(addr
)]];
431 /* Called from RCU critical section */
432 static MemoryRegionSection
*
433 address_space_translate_internal(AddressSpaceDispatch
*d
, hwaddr addr
, hwaddr
*xlat
,
434 hwaddr
*plen
, bool resolve_subpage
)
436 MemoryRegionSection
*section
;
440 section
= address_space_lookup_region(d
, addr
, resolve_subpage
);
441 /* Compute offset within MemoryRegionSection */
442 addr
-= section
->offset_within_address_space
;
444 /* Compute offset within MemoryRegion */
445 *xlat
= addr
+ section
->offset_within_region
;
449 /* MMIO registers can be expected to perform full-width accesses based only
450 * on their address, without considering adjacent registers that could
451 * decode to completely different MemoryRegions. When such registers
452 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
453 * regions overlap wildly. For this reason we cannot clamp the accesses
456 * If the length is small (as is the case for address_space_ldl/stl),
457 * everything works fine. If the incoming length is large, however,
458 * the caller really has to do the clamping through memory_access_size.
460 if (memory_region_is_ram(mr
)) {
461 diff
= int128_sub(section
->size
, int128_make64(addr
));
462 *plen
= int128_get64(int128_min(diff
, int128_make64(*plen
)));
468 * address_space_translate_iommu - translate an address through an IOMMU
469 * memory region and then through the target address space.
471 * @iommu_mr: the IOMMU memory region that we start the translation from
472 * @addr: the address to be translated through the MMU
473 * @xlat: the translated address offset within the destination memory region.
474 * It cannot be %NULL.
475 * @plen_out: valid read/write length of the translated address. It
477 * @page_mask_out: page mask for the translated address. This
478 * should only be meaningful for IOMMU translated
479 * addresses, since there may be huge pages that this bit
480 * would tell. It can be %NULL if we don't care about it.
481 * @is_write: whether the translation operation is for write
482 * @is_mmio: whether this can be MMIO, set true if it can
483 * @target_as: the address space targeted by the IOMMU
484 * @attrs: transaction attributes
486 * This function is called from RCU critical section. It is the common
487 * part of flatview_do_translate and address_space_translate_cached.
489 static MemoryRegionSection
address_space_translate_iommu(IOMMUMemoryRegion
*iommu_mr
,
492 hwaddr
*page_mask_out
,
495 AddressSpace
**target_as
,
498 MemoryRegionSection
*section
;
499 hwaddr page_mask
= (hwaddr
)-1;
503 IOMMUMemoryRegionClass
*imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
507 if (imrc
->attrs_to_index
) {
508 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
511 iotlb
= imrc
->translate(iommu_mr
, addr
, is_write
?
512 IOMMU_WO
: IOMMU_RO
, iommu_idx
);
514 if (!(iotlb
.perm
& (1 << is_write
))) {
518 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
519 | (addr
& iotlb
.addr_mask
));
520 page_mask
&= iotlb
.addr_mask
;
521 *plen_out
= MIN(*plen_out
, (addr
| iotlb
.addr_mask
) - addr
+ 1);
522 *target_as
= iotlb
.target_as
;
524 section
= address_space_translate_internal(
525 address_space_to_dispatch(iotlb
.target_as
), addr
, xlat
,
528 iommu_mr
= memory_region_get_iommu(section
->mr
);
529 } while (unlikely(iommu_mr
));
532 *page_mask_out
= page_mask
;
537 return (MemoryRegionSection
) { .mr
= &io_mem_unassigned
};
541 * flatview_do_translate - translate an address in FlatView
543 * @fv: the flat view that we want to translate on
544 * @addr: the address to be translated in above address space
545 * @xlat: the translated address offset within memory region. It
547 * @plen_out: valid read/write length of the translated address. It
548 * can be @NULL when we don't care about it.
549 * @page_mask_out: page mask for the translated address. This
550 * should only be meaningful for IOMMU translated
551 * addresses, since there may be huge pages that this bit
552 * would tell. It can be @NULL if we don't care about it.
553 * @is_write: whether the translation operation is for write
554 * @is_mmio: whether this can be MMIO, set true if it can
555 * @target_as: the address space targeted by the IOMMU
556 * @attrs: memory transaction attributes
558 * This function is called from RCU critical section
560 static MemoryRegionSection
flatview_do_translate(FlatView
*fv
,
564 hwaddr
*page_mask_out
,
567 AddressSpace
**target_as
,
570 MemoryRegionSection
*section
;
571 IOMMUMemoryRegion
*iommu_mr
;
572 hwaddr plen
= (hwaddr
)(-1);
578 section
= address_space_translate_internal(
579 flatview_to_dispatch(fv
), addr
, xlat
,
582 iommu_mr
= memory_region_get_iommu(section
->mr
);
583 if (unlikely(iommu_mr
)) {
584 return address_space_translate_iommu(iommu_mr
, xlat
,
585 plen_out
, page_mask_out
,
590 /* Not behind an IOMMU, use default page size. */
591 *page_mask_out
= ~TARGET_PAGE_MASK
;
597 /* Called from RCU critical section */
598 IOMMUTLBEntry
address_space_get_iotlb_entry(AddressSpace
*as
, hwaddr addr
,
599 bool is_write
, MemTxAttrs attrs
)
601 MemoryRegionSection section
;
602 hwaddr xlat
, page_mask
;
605 * This can never be MMIO, and we don't really care about plen,
608 section
= flatview_do_translate(address_space_to_flatview(as
), addr
, &xlat
,
609 NULL
, &page_mask
, is_write
, false, &as
,
612 /* Illegal translation */
613 if (section
.mr
== &io_mem_unassigned
) {
617 /* Convert memory region offset into address space offset */
618 xlat
+= section
.offset_within_address_space
-
619 section
.offset_within_region
;
621 return (IOMMUTLBEntry
) {
623 .iova
= addr
& ~page_mask
,
624 .translated_addr
= xlat
& ~page_mask
,
625 .addr_mask
= page_mask
,
626 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
631 return (IOMMUTLBEntry
) {0};
634 /* Called from RCU critical section */
635 MemoryRegion
*flatview_translate(FlatView
*fv
, hwaddr addr
, hwaddr
*xlat
,
636 hwaddr
*plen
, bool is_write
,
640 MemoryRegionSection section
;
641 AddressSpace
*as
= NULL
;
643 /* This can be MMIO, so setup MMIO bit. */
644 section
= flatview_do_translate(fv
, addr
, xlat
, plen
, NULL
,
645 is_write
, true, &as
, attrs
);
648 if (xen_enabled() && memory_access_is_direct(mr
, is_write
)) {
649 hwaddr page
= ((addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
) - addr
;
650 *plen
= MIN(page
, *plen
);
656 typedef struct TCGIOMMUNotifier
{
664 static void tcg_iommu_unmap_notify(IOMMUNotifier
*n
, IOMMUTLBEntry
*iotlb
)
666 TCGIOMMUNotifier
*notifier
= container_of(n
, TCGIOMMUNotifier
, n
);
668 if (!notifier
->active
) {
671 tlb_flush(notifier
->cpu
);
672 notifier
->active
= false;
673 /* We leave the notifier struct on the list to avoid reallocating it later.
674 * Generally the number of IOMMUs a CPU deals with will be small.
675 * In any case we can't unregister the iommu notifier from a notify
680 static void tcg_register_iommu_notifier(CPUState
*cpu
,
681 IOMMUMemoryRegion
*iommu_mr
,
684 /* Make sure this CPU has an IOMMU notifier registered for this
685 * IOMMU/IOMMU index combination, so that we can flush its TLB
686 * when the IOMMU tells us the mappings we've cached have changed.
688 MemoryRegion
*mr
= MEMORY_REGION(iommu_mr
);
689 TCGIOMMUNotifier
*notifier
;
692 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
693 notifier
= &g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
, i
);
694 if (notifier
->mr
== mr
&& notifier
->iommu_idx
== iommu_idx
) {
698 if (i
== cpu
->iommu_notifiers
->len
) {
699 /* Not found, add a new entry at the end of the array */
700 cpu
->iommu_notifiers
= g_array_set_size(cpu
->iommu_notifiers
, i
+ 1);
701 notifier
= &g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
, i
);
704 notifier
->iommu_idx
= iommu_idx
;
706 /* Rather than trying to register interest in the specific part
707 * of the iommu's address space that we've accessed and then
708 * expand it later as subsequent accesses touch more of it, we
709 * just register interest in the whole thing, on the assumption
710 * that iommu reconfiguration will be rare.
712 iommu_notifier_init(¬ifier
->n
,
713 tcg_iommu_unmap_notify
,
714 IOMMU_NOTIFIER_UNMAP
,
718 memory_region_register_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
721 if (!notifier
->active
) {
722 notifier
->active
= true;
726 static void tcg_iommu_free_notifier_list(CPUState
*cpu
)
728 /* Destroy the CPU's notifier list */
730 TCGIOMMUNotifier
*notifier
;
732 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
733 notifier
= &g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
, i
);
734 memory_region_unregister_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
736 g_array_free(cpu
->iommu_notifiers
, true);
739 /* Called from RCU critical section */
740 MemoryRegionSection
*
741 address_space_translate_for_iotlb(CPUState
*cpu
, int asidx
, hwaddr addr
,
742 hwaddr
*xlat
, hwaddr
*plen
,
743 MemTxAttrs attrs
, int *prot
)
745 MemoryRegionSection
*section
;
746 IOMMUMemoryRegion
*iommu_mr
;
747 IOMMUMemoryRegionClass
*imrc
;
750 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpu
->cpu_ases
[asidx
].memory_dispatch
);
753 section
= address_space_translate_internal(d
, addr
, &addr
, plen
, false);
755 iommu_mr
= memory_region_get_iommu(section
->mr
);
760 imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
762 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
763 tcg_register_iommu_notifier(cpu
, iommu_mr
, iommu_idx
);
764 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
765 * doesn't short-cut its translation table walk.
767 iotlb
= imrc
->translate(iommu_mr
, addr
, IOMMU_NONE
, iommu_idx
);
768 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
769 | (addr
& iotlb
.addr_mask
));
770 /* Update the caller's prot bits to remove permissions the IOMMU
771 * is giving us a failure response for. If we get down to no
772 * permissions left at all we can give up now.
774 if (!(iotlb
.perm
& IOMMU_RO
)) {
775 *prot
&= ~(PAGE_READ
| PAGE_EXEC
);
777 if (!(iotlb
.perm
& IOMMU_WO
)) {
778 *prot
&= ~PAGE_WRITE
;
785 d
= flatview_to_dispatch(address_space_to_flatview(iotlb
.target_as
));
788 assert(!memory_region_is_iommu(section
->mr
));
793 return &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
];
797 #if !defined(CONFIG_USER_ONLY)
799 static int cpu_common_post_load(void *opaque
, int version_id
)
801 CPUState
*cpu
= opaque
;
803 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
804 version_id is increased. */
805 cpu
->interrupt_request
&= ~0x01;
808 /* loadvm has just updated the content of RAM, bypassing the
809 * usual mechanisms that ensure we flush TBs for writes to
810 * memory we've translated code from. So we must flush all TBs,
811 * which will now be stale.
818 static int cpu_common_pre_load(void *opaque
)
820 CPUState
*cpu
= opaque
;
822 cpu
->exception_index
= -1;
827 static bool cpu_common_exception_index_needed(void *opaque
)
829 CPUState
*cpu
= opaque
;
831 return tcg_enabled() && cpu
->exception_index
!= -1;
834 static const VMStateDescription vmstate_cpu_common_exception_index
= {
835 .name
= "cpu_common/exception_index",
837 .minimum_version_id
= 1,
838 .needed
= cpu_common_exception_index_needed
,
839 .fields
= (VMStateField
[]) {
840 VMSTATE_INT32(exception_index
, CPUState
),
841 VMSTATE_END_OF_LIST()
845 static bool cpu_common_crash_occurred_needed(void *opaque
)
847 CPUState
*cpu
= opaque
;
849 return cpu
->crash_occurred
;
852 static const VMStateDescription vmstate_cpu_common_crash_occurred
= {
853 .name
= "cpu_common/crash_occurred",
855 .minimum_version_id
= 1,
856 .needed
= cpu_common_crash_occurred_needed
,
857 .fields
= (VMStateField
[]) {
858 VMSTATE_BOOL(crash_occurred
, CPUState
),
859 VMSTATE_END_OF_LIST()
863 const VMStateDescription vmstate_cpu_common
= {
864 .name
= "cpu_common",
866 .minimum_version_id
= 1,
867 .pre_load
= cpu_common_pre_load
,
868 .post_load
= cpu_common_post_load
,
869 .fields
= (VMStateField
[]) {
870 VMSTATE_UINT32(halted
, CPUState
),
871 VMSTATE_UINT32(interrupt_request
, CPUState
),
872 VMSTATE_END_OF_LIST()
874 .subsections
= (const VMStateDescription
*[]) {
875 &vmstate_cpu_common_exception_index
,
876 &vmstate_cpu_common_crash_occurred
,
883 CPUState
*qemu_get_cpu(int index
)
888 if (cpu
->cpu_index
== index
) {
896 #if !defined(CONFIG_USER_ONLY)
897 void cpu_address_space_init(CPUState
*cpu
, int asidx
,
898 const char *prefix
, MemoryRegion
*mr
)
900 CPUAddressSpace
*newas
;
901 AddressSpace
*as
= g_new0(AddressSpace
, 1);
905 as_name
= g_strdup_printf("%s-%d", prefix
, cpu
->cpu_index
);
906 address_space_init(as
, mr
, as_name
);
909 /* Target code should have set num_ases before calling us */
910 assert(asidx
< cpu
->num_ases
);
913 /* address space 0 gets the convenience alias */
917 /* KVM cannot currently support multiple address spaces. */
918 assert(asidx
== 0 || !kvm_enabled());
920 if (!cpu
->cpu_ases
) {
921 cpu
->cpu_ases
= g_new0(CPUAddressSpace
, cpu
->num_ases
);
924 newas
= &cpu
->cpu_ases
[asidx
];
928 newas
->tcg_as_listener
.commit
= tcg_commit
;
929 memory_listener_register(&newas
->tcg_as_listener
, as
);
933 AddressSpace
*cpu_get_address_space(CPUState
*cpu
, int asidx
)
935 /* Return the AddressSpace corresponding to the specified index */
936 return cpu
->cpu_ases
[asidx
].as
;
940 void cpu_exec_unrealizefn(CPUState
*cpu
)
942 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
944 cpu_list_remove(cpu
);
946 if (cc
->vmsd
!= NULL
) {
947 vmstate_unregister(NULL
, cc
->vmsd
, cpu
);
949 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
950 vmstate_unregister(NULL
, &vmstate_cpu_common
, cpu
);
952 #ifndef CONFIG_USER_ONLY
953 tcg_iommu_free_notifier_list(cpu
);
957 Property cpu_common_props
[] = {
958 #ifndef CONFIG_USER_ONLY
959 /* Create a memory property for softmmu CPU object,
960 * so users can wire up its memory. (This can't go in qom/cpu.c
961 * because that file is compiled only once for both user-mode
962 * and system builds.) The default if no link is set up is to use
963 * the system address space.
965 DEFINE_PROP_LINK("memory", CPUState
, memory
, TYPE_MEMORY_REGION
,
968 DEFINE_PROP_END_OF_LIST(),
971 void cpu_exec_initfn(CPUState
*cpu
)
976 #ifndef CONFIG_USER_ONLY
977 cpu
->thread_id
= qemu_get_thread_id();
978 cpu
->memory
= system_memory
;
979 object_ref(OBJECT(cpu
->memory
));
983 void cpu_exec_realizefn(CPUState
*cpu
, Error
**errp
)
985 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
986 static bool tcg_target_initialized
;
990 if (tcg_enabled() && !tcg_target_initialized
) {
991 tcg_target_initialized
= true;
992 cc
->tcg_initialize();
995 #ifndef CONFIG_USER_ONLY
996 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
997 vmstate_register(NULL
, cpu
->cpu_index
, &vmstate_cpu_common
, cpu
);
999 if (cc
->vmsd
!= NULL
) {
1000 vmstate_register(NULL
, cpu
->cpu_index
, cc
->vmsd
, cpu
);
1003 cpu
->iommu_notifiers
= g_array_new(false, true, sizeof(TCGIOMMUNotifier
));
1007 const char *parse_cpu_model(const char *cpu_model
)
1011 gchar
**model_pieces
;
1012 const char *cpu_type
;
1014 model_pieces
= g_strsplit(cpu_model
, ",", 2);
1016 oc
= cpu_class_by_name(CPU_RESOLVING_TYPE
, model_pieces
[0]);
1018 error_report("unable to find CPU model '%s'", model_pieces
[0]);
1019 g_strfreev(model_pieces
);
1023 cpu_type
= object_class_get_name(oc
);
1025 cc
->parse_features(cpu_type
, model_pieces
[1], &error_fatal
);
1026 g_strfreev(model_pieces
);
1030 #if defined(CONFIG_USER_ONLY)
1031 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1034 tb_invalidate_phys_page_range(pc
, pc
+ 1, 0);
1038 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1041 hwaddr phys
= cpu_get_phys_page_attrs_debug(cpu
, pc
, &attrs
);
1042 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
1044 /* Locks grabbed by tb_invalidate_phys_addr */
1045 tb_invalidate_phys_addr(cpu
->cpu_ases
[asidx
].as
,
1046 phys
| (pc
& ~TARGET_PAGE_MASK
), attrs
);
1051 #if defined(CONFIG_USER_ONLY)
1052 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1057 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1063 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1067 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1068 int flags
, CPUWatchpoint
**watchpoint
)
1073 /* Add a watchpoint. */
1074 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1075 int flags
, CPUWatchpoint
**watchpoint
)
1079 /* forbid ranges which are empty or run off the end of the address space */
1080 if (len
== 0 || (addr
+ len
- 1) < addr
) {
1081 error_report("tried to set invalid watchpoint at %"
1082 VADDR_PRIx
", len=%" VADDR_PRIu
, addr
, len
);
1085 wp
= g_malloc(sizeof(*wp
));
1091 /* keep all GDB-injected watchpoints in front */
1092 if (flags
& BP_GDB
) {
1093 QTAILQ_INSERT_HEAD(&cpu
->watchpoints
, wp
, entry
);
1095 QTAILQ_INSERT_TAIL(&cpu
->watchpoints
, wp
, entry
);
1098 tlb_flush_page(cpu
, addr
);
1105 /* Remove a specific watchpoint. */
1106 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1111 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1112 if (addr
== wp
->vaddr
&& len
== wp
->len
1113 && flags
== (wp
->flags
& ~BP_WATCHPOINT_HIT
)) {
1114 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1121 /* Remove a specific watchpoint by reference. */
1122 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1124 QTAILQ_REMOVE(&cpu
->watchpoints
, watchpoint
, entry
);
1126 tlb_flush_page(cpu
, watchpoint
->vaddr
);
1131 /* Remove all matching watchpoints. */
1132 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1134 CPUWatchpoint
*wp
, *next
;
1136 QTAILQ_FOREACH_SAFE(wp
, &cpu
->watchpoints
, entry
, next
) {
1137 if (wp
->flags
& mask
) {
1138 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1143 /* Return true if this watchpoint address matches the specified
1144 * access (ie the address range covered by the watchpoint overlaps
1145 * partially or completely with the address range covered by the
1148 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint
*wp
,
1152 /* We know the lengths are non-zero, but a little caution is
1153 * required to avoid errors in the case where the range ends
1154 * exactly at the top of the address space and so addr + len
1155 * wraps round to zero.
1157 vaddr wpend
= wp
->vaddr
+ wp
->len
- 1;
1158 vaddr addrend
= addr
+ len
- 1;
1160 return !(addr
> wpend
|| wp
->vaddr
> addrend
);
1165 /* Add a breakpoint. */
1166 int cpu_breakpoint_insert(CPUState
*cpu
, vaddr pc
, int flags
,
1167 CPUBreakpoint
**breakpoint
)
1171 bp
= g_malloc(sizeof(*bp
));
1176 /* keep all GDB-injected breakpoints in front */
1177 if (flags
& BP_GDB
) {
1178 QTAILQ_INSERT_HEAD(&cpu
->breakpoints
, bp
, entry
);
1180 QTAILQ_INSERT_TAIL(&cpu
->breakpoints
, bp
, entry
);
1183 breakpoint_invalidate(cpu
, pc
);
1191 /* Remove a specific breakpoint. */
1192 int cpu_breakpoint_remove(CPUState
*cpu
, vaddr pc
, int flags
)
1196 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
1197 if (bp
->pc
== pc
&& bp
->flags
== flags
) {
1198 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1205 /* Remove a specific breakpoint by reference. */
1206 void cpu_breakpoint_remove_by_ref(CPUState
*cpu
, CPUBreakpoint
*breakpoint
)
1208 QTAILQ_REMOVE(&cpu
->breakpoints
, breakpoint
, entry
);
1210 breakpoint_invalidate(cpu
, breakpoint
->pc
);
1215 /* Remove all matching breakpoints. */
1216 void cpu_breakpoint_remove_all(CPUState
*cpu
, int mask
)
1218 CPUBreakpoint
*bp
, *next
;
1220 QTAILQ_FOREACH_SAFE(bp
, &cpu
->breakpoints
, entry
, next
) {
1221 if (bp
->flags
& mask
) {
1222 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1227 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1228 CPU loop after each instruction */
1229 void cpu_single_step(CPUState
*cpu
, int enabled
)
1231 if (cpu
->singlestep_enabled
!= enabled
) {
1232 cpu
->singlestep_enabled
= enabled
;
1233 if (kvm_enabled()) {
1234 kvm_update_guest_debug(cpu
, 0);
1236 /* must flush all the translated code to avoid inconsistencies */
1237 /* XXX: only flush what is necessary */
1243 void cpu_abort(CPUState
*cpu
, const char *fmt
, ...)
1250 fprintf(stderr
, "qemu: fatal: ");
1251 vfprintf(stderr
, fmt
, ap
);
1252 fprintf(stderr
, "\n");
1253 cpu_dump_state(cpu
, stderr
, fprintf
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1254 if (qemu_log_separate()) {
1256 qemu_log("qemu: fatal: ");
1257 qemu_log_vprintf(fmt
, ap2
);
1259 log_cpu_state(cpu
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1267 #if defined(CONFIG_USER_ONLY)
1269 struct sigaction act
;
1270 sigfillset(&act
.sa_mask
);
1271 act
.sa_handler
= SIG_DFL
;
1273 sigaction(SIGABRT
, &act
, NULL
);
1279 #if !defined(CONFIG_USER_ONLY)
1280 /* Called from RCU critical section */
1281 static RAMBlock
*qemu_get_ram_block(ram_addr_t addr
)
1285 block
= atomic_rcu_read(&ram_list
.mru_block
);
1286 if (block
&& addr
- block
->offset
< block
->max_length
) {
1289 RAMBLOCK_FOREACH(block
) {
1290 if (addr
- block
->offset
< block
->max_length
) {
1295 fprintf(stderr
, "Bad ram offset %" PRIx64
"\n", (uint64_t)addr
);
1299 /* It is safe to write mru_block outside the iothread lock. This
1304 * xxx removed from list
1308 * call_rcu(reclaim_ramblock, xxx);
1311 * atomic_rcu_set is not needed here. The block was already published
1312 * when it was placed into the list. Here we're just making an extra
1313 * copy of the pointer.
1315 ram_list
.mru_block
= block
;
1319 static void tlb_reset_dirty_range_all(ram_addr_t start
, ram_addr_t length
)
1326 assert(tcg_enabled());
1327 end
= TARGET_PAGE_ALIGN(start
+ length
);
1328 start
&= TARGET_PAGE_MASK
;
1331 block
= qemu_get_ram_block(start
);
1332 assert(block
== qemu_get_ram_block(end
- 1));
1333 start1
= (uintptr_t)ramblock_ptr(block
, start
- block
->offset
);
1335 tlb_reset_dirty(cpu
, start1
, length
);
1340 /* Note: start and end must be within the same ram block. */
1341 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start
,
1345 DirtyMemoryBlocks
*blocks
;
1346 unsigned long end
, page
;
1353 end
= TARGET_PAGE_ALIGN(start
+ length
) >> TARGET_PAGE_BITS
;
1354 page
= start
>> TARGET_PAGE_BITS
;
1358 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1360 while (page
< end
) {
1361 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1362 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1363 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1365 dirty
|= bitmap_test_and_clear_atomic(blocks
->blocks
[idx
],
1372 if (dirty
&& tcg_enabled()) {
1373 tlb_reset_dirty_range_all(start
, length
);
1379 DirtyBitmapSnapshot
*cpu_physical_memory_snapshot_and_clear_dirty
1380 (ram_addr_t start
, ram_addr_t length
, unsigned client
)
1382 DirtyMemoryBlocks
*blocks
;
1383 unsigned long align
= 1UL << (TARGET_PAGE_BITS
+ BITS_PER_LEVEL
);
1384 ram_addr_t first
= QEMU_ALIGN_DOWN(start
, align
);
1385 ram_addr_t last
= QEMU_ALIGN_UP(start
+ length
, align
);
1386 DirtyBitmapSnapshot
*snap
;
1387 unsigned long page
, end
, dest
;
1389 snap
= g_malloc0(sizeof(*snap
) +
1390 ((last
- first
) >> (TARGET_PAGE_BITS
+ 3)));
1391 snap
->start
= first
;
1394 page
= first
>> TARGET_PAGE_BITS
;
1395 end
= last
>> TARGET_PAGE_BITS
;
1400 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1402 while (page
< end
) {
1403 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1404 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1405 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1407 assert(QEMU_IS_ALIGNED(offset
, (1 << BITS_PER_LEVEL
)));
1408 assert(QEMU_IS_ALIGNED(num
, (1 << BITS_PER_LEVEL
)));
1409 offset
>>= BITS_PER_LEVEL
;
1411 bitmap_copy_and_clear_atomic(snap
->dirty
+ dest
,
1412 blocks
->blocks
[idx
] + offset
,
1415 dest
+= num
>> BITS_PER_LEVEL
;
1420 if (tcg_enabled()) {
1421 tlb_reset_dirty_range_all(start
, length
);
1427 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot
*snap
,
1431 unsigned long page
, end
;
1433 assert(start
>= snap
->start
);
1434 assert(start
+ length
<= snap
->end
);
1436 end
= TARGET_PAGE_ALIGN(start
+ length
- snap
->start
) >> TARGET_PAGE_BITS
;
1437 page
= (start
- snap
->start
) >> TARGET_PAGE_BITS
;
1439 while (page
< end
) {
1440 if (test_bit(page
, snap
->dirty
)) {
1448 /* Called from RCU critical section */
1449 hwaddr
memory_region_section_get_iotlb(CPUState
*cpu
,
1450 MemoryRegionSection
*section
,
1452 hwaddr paddr
, hwaddr xlat
,
1454 target_ulong
*address
)
1459 if (memory_region_is_ram(section
->mr
)) {
1461 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1462 if (!section
->readonly
) {
1463 iotlb
|= PHYS_SECTION_NOTDIRTY
;
1465 iotlb
|= PHYS_SECTION_ROM
;
1468 AddressSpaceDispatch
*d
;
1470 d
= flatview_to_dispatch(section
->fv
);
1471 iotlb
= section
- d
->map
.sections
;
1475 /* Make accesses to pages with watchpoints go via the
1476 watchpoint trap routines. */
1477 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1478 if (cpu_watchpoint_address_matches(wp
, vaddr
, TARGET_PAGE_SIZE
)) {
1479 /* Avoid trapping reads of pages with a write breakpoint. */
1480 if ((prot
& PAGE_WRITE
) || (wp
->flags
& BP_MEM_READ
)) {
1481 iotlb
= PHYS_SECTION_WATCH
+ paddr
;
1482 *address
|= TLB_MMIO
;
1490 #endif /* defined(CONFIG_USER_ONLY) */
1492 #if !defined(CONFIG_USER_ONLY)
1494 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
1496 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
);
1498 static void *(*phys_mem_alloc
)(size_t size
, uint64_t *align
, bool shared
) =
1499 qemu_anon_ram_alloc
;
1502 * Set a custom physical guest memory alloator.
1503 * Accelerators with unusual needs may need this. Hopefully, we can
1504 * get rid of it eventually.
1506 void phys_mem_set_alloc(void *(*alloc
)(size_t, uint64_t *align
, bool shared
))
1508 phys_mem_alloc
= alloc
;
1511 static uint16_t phys_section_add(PhysPageMap
*map
,
1512 MemoryRegionSection
*section
)
1514 /* The physical section number is ORed with a page-aligned
1515 * pointer to produce the iotlb entries. Thus it should
1516 * never overflow into the page-aligned value.
1518 assert(map
->sections_nb
< TARGET_PAGE_SIZE
);
1520 if (map
->sections_nb
== map
->sections_nb_alloc
) {
1521 map
->sections_nb_alloc
= MAX(map
->sections_nb_alloc
* 2, 16);
1522 map
->sections
= g_renew(MemoryRegionSection
, map
->sections
,
1523 map
->sections_nb_alloc
);
1525 map
->sections
[map
->sections_nb
] = *section
;
1526 memory_region_ref(section
->mr
);
1527 return map
->sections_nb
++;
1530 static void phys_section_destroy(MemoryRegion
*mr
)
1532 bool have_sub_page
= mr
->subpage
;
1534 memory_region_unref(mr
);
1536 if (have_sub_page
) {
1537 subpage_t
*subpage
= container_of(mr
, subpage_t
, iomem
);
1538 object_unref(OBJECT(&subpage
->iomem
));
1543 static void phys_sections_free(PhysPageMap
*map
)
1545 while (map
->sections_nb
> 0) {
1546 MemoryRegionSection
*section
= &map
->sections
[--map
->sections_nb
];
1547 phys_section_destroy(section
->mr
);
1549 g_free(map
->sections
);
1553 static void register_subpage(FlatView
*fv
, MemoryRegionSection
*section
)
1555 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1557 hwaddr base
= section
->offset_within_address_space
1559 MemoryRegionSection
*existing
= phys_page_find(d
, base
);
1560 MemoryRegionSection subsection
= {
1561 .offset_within_address_space
= base
,
1562 .size
= int128_make64(TARGET_PAGE_SIZE
),
1566 assert(existing
->mr
->subpage
|| existing
->mr
== &io_mem_unassigned
);
1568 if (!(existing
->mr
->subpage
)) {
1569 subpage
= subpage_init(fv
, base
);
1571 subsection
.mr
= &subpage
->iomem
;
1572 phys_page_set(d
, base
>> TARGET_PAGE_BITS
, 1,
1573 phys_section_add(&d
->map
, &subsection
));
1575 subpage
= container_of(existing
->mr
, subpage_t
, iomem
);
1577 start
= section
->offset_within_address_space
& ~TARGET_PAGE_MASK
;
1578 end
= start
+ int128_get64(section
->size
) - 1;
1579 subpage_register(subpage
, start
, end
,
1580 phys_section_add(&d
->map
, section
));
1584 static void register_multipage(FlatView
*fv
,
1585 MemoryRegionSection
*section
)
1587 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1588 hwaddr start_addr
= section
->offset_within_address_space
;
1589 uint16_t section_index
= phys_section_add(&d
->map
, section
);
1590 uint64_t num_pages
= int128_get64(int128_rshift(section
->size
,
1594 phys_page_set(d
, start_addr
>> TARGET_PAGE_BITS
, num_pages
, section_index
);
1597 void flatview_add_to_dispatch(FlatView
*fv
, MemoryRegionSection
*section
)
1599 MemoryRegionSection now
= *section
, remain
= *section
;
1600 Int128 page_size
= int128_make64(TARGET_PAGE_SIZE
);
1602 if (now
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1603 uint64_t left
= TARGET_PAGE_ALIGN(now
.offset_within_address_space
)
1604 - now
.offset_within_address_space
;
1606 now
.size
= int128_min(int128_make64(left
), now
.size
);
1607 register_subpage(fv
, &now
);
1609 now
.size
= int128_zero();
1611 while (int128_ne(remain
.size
, now
.size
)) {
1612 remain
.size
= int128_sub(remain
.size
, now
.size
);
1613 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1614 remain
.offset_within_region
+= int128_get64(now
.size
);
1616 if (int128_lt(remain
.size
, page_size
)) {
1617 register_subpage(fv
, &now
);
1618 } else if (remain
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1619 now
.size
= page_size
;
1620 register_subpage(fv
, &now
);
1622 now
.size
= int128_and(now
.size
, int128_neg(page_size
));
1623 register_multipage(fv
, &now
);
1628 void qemu_flush_coalesced_mmio_buffer(void)
1631 kvm_flush_coalesced_mmio_buffer();
1634 void qemu_mutex_lock_ramlist(void)
1636 qemu_mutex_lock(&ram_list
.mutex
);
1639 void qemu_mutex_unlock_ramlist(void)
1641 qemu_mutex_unlock(&ram_list
.mutex
);
1644 void ram_block_dump(Monitor
*mon
)
1650 monitor_printf(mon
, "%24s %8s %18s %18s %18s\n",
1651 "Block Name", "PSize", "Offset", "Used", "Total");
1652 RAMBLOCK_FOREACH(block
) {
1653 psize
= size_to_str(block
->page_size
);
1654 monitor_printf(mon
, "%24s %8s 0x%016" PRIx64
" 0x%016" PRIx64
1655 " 0x%016" PRIx64
"\n", block
->idstr
, psize
,
1656 (uint64_t)block
->offset
,
1657 (uint64_t)block
->used_length
,
1658 (uint64_t)block
->max_length
);
1666 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1667 * may or may not name the same files / on the same filesystem now as
1668 * when we actually open and map them. Iterate over the file
1669 * descriptors instead, and use qemu_fd_getpagesize().
1671 static int find_max_supported_pagesize(Object
*obj
, void *opaque
)
1673 long *hpsize_min
= opaque
;
1675 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1676 long hpsize
= host_memory_backend_pagesize(MEMORY_BACKEND(obj
));
1678 if (hpsize
< *hpsize_min
) {
1679 *hpsize_min
= hpsize
;
1686 long qemu_getrampagesize(void)
1688 long hpsize
= LONG_MAX
;
1689 long mainrampagesize
;
1690 Object
*memdev_root
;
1692 mainrampagesize
= qemu_mempath_getpagesize(mem_path
);
1694 /* it's possible we have memory-backend objects with
1695 * hugepage-backed RAM. these may get mapped into system
1696 * address space via -numa parameters or memory hotplug
1697 * hooks. we want to take these into account, but we
1698 * also want to make sure these supported hugepage
1699 * sizes are applicable across the entire range of memory
1700 * we may boot from, so we take the min across all
1701 * backends, and assume normal pages in cases where a
1702 * backend isn't backed by hugepages.
1704 memdev_root
= object_resolve_path("/objects", NULL
);
1706 object_child_foreach(memdev_root
, find_max_supported_pagesize
, &hpsize
);
1708 if (hpsize
== LONG_MAX
) {
1709 /* No additional memory regions found ==> Report main RAM page size */
1710 return mainrampagesize
;
1713 /* If NUMA is disabled or the NUMA nodes are not backed with a
1714 * memory-backend, then there is at least one node using "normal" RAM,
1715 * so if its page size is smaller we have got to report that size instead.
1717 if (hpsize
> mainrampagesize
&&
1718 (nb_numa_nodes
== 0 || numa_info
[0].node_memdev
== NULL
)) {
1721 error_report("Huge page support disabled (n/a for main memory).");
1724 return mainrampagesize
;
1730 long qemu_getrampagesize(void)
1732 return getpagesize();
1737 static int64_t get_file_size(int fd
)
1739 int64_t size
= lseek(fd
, 0, SEEK_END
);
1746 static int file_ram_open(const char *path
,
1747 const char *region_name
,
1752 char *sanitized_name
;
1758 fd
= open(path
, O_RDWR
);
1760 /* @path names an existing file, use it */
1763 if (errno
== ENOENT
) {
1764 /* @path names a file that doesn't exist, create it */
1765 fd
= open(path
, O_RDWR
| O_CREAT
| O_EXCL
, 0644);
1770 } else if (errno
== EISDIR
) {
1771 /* @path names a directory, create a file there */
1772 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1773 sanitized_name
= g_strdup(region_name
);
1774 for (c
= sanitized_name
; *c
!= '\0'; c
++) {
1780 filename
= g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path
,
1782 g_free(sanitized_name
);
1784 fd
= mkstemp(filename
);
1792 if (errno
!= EEXIST
&& errno
!= EINTR
) {
1793 error_setg_errno(errp
, errno
,
1794 "can't open backing store %s for guest RAM",
1799 * Try again on EINTR and EEXIST. The latter happens when
1800 * something else creates the file between our two open().
1807 static void *file_ram_alloc(RAMBlock
*block
,
1815 block
->page_size
= qemu_fd_getpagesize(fd
);
1816 if (block
->mr
->align
% block
->page_size
) {
1817 error_setg(errp
, "alignment 0x%" PRIx64
1818 " must be multiples of page size 0x%zx",
1819 block
->mr
->align
, block
->page_size
);
1822 block
->mr
->align
= MAX(block
->page_size
, block
->mr
->align
);
1823 #if defined(__s390x__)
1824 if (kvm_enabled()) {
1825 block
->mr
->align
= MAX(block
->mr
->align
, QEMU_VMALLOC_ALIGN
);
1829 if (memory
< block
->page_size
) {
1830 error_setg(errp
, "memory size 0x" RAM_ADDR_FMT
" must be equal to "
1831 "or larger than page size 0x%zx",
1832 memory
, block
->page_size
);
1836 memory
= ROUND_UP(memory
, block
->page_size
);
1839 * ftruncate is not supported by hugetlbfs in older
1840 * hosts, so don't bother bailing out on errors.
1841 * If anything goes wrong with it under other filesystems,
1844 * Do not truncate the non-empty backend file to avoid corrupting
1845 * the existing data in the file. Disabling shrinking is not
1846 * enough. For example, the current vNVDIMM implementation stores
1847 * the guest NVDIMM labels at the end of the backend file. If the
1848 * backend file is later extended, QEMU will not be able to find
1849 * those labels. Therefore, extending the non-empty backend file
1850 * is disabled as well.
1852 if (truncate
&& ftruncate(fd
, memory
)) {
1853 perror("ftruncate");
1856 area
= qemu_ram_mmap(fd
, memory
, block
->mr
->align
,
1857 block
->flags
& RAM_SHARED
);
1858 if (area
== MAP_FAILED
) {
1859 error_setg_errno(errp
, errno
,
1860 "unable to map backing store for guest RAM");
1865 os_mem_prealloc(fd
, area
, memory
, smp_cpus
, errp
);
1866 if (errp
&& *errp
) {
1867 qemu_ram_munmap(area
, memory
);
1877 /* Allocate space within the ram_addr_t space that governs the
1879 * Called with the ramlist lock held.
1881 static ram_addr_t
find_ram_offset(ram_addr_t size
)
1883 RAMBlock
*block
, *next_block
;
1884 ram_addr_t offset
= RAM_ADDR_MAX
, mingap
= RAM_ADDR_MAX
;
1886 assert(size
!= 0); /* it would hand out same offset multiple times */
1888 if (QLIST_EMPTY_RCU(&ram_list
.blocks
)) {
1892 RAMBLOCK_FOREACH(block
) {
1893 ram_addr_t candidate
, next
= RAM_ADDR_MAX
;
1895 /* Align blocks to start on a 'long' in the bitmap
1896 * which makes the bitmap sync'ing take the fast path.
1898 candidate
= block
->offset
+ block
->max_length
;
1899 candidate
= ROUND_UP(candidate
, BITS_PER_LONG
<< TARGET_PAGE_BITS
);
1901 /* Search for the closest following block
1904 RAMBLOCK_FOREACH(next_block
) {
1905 if (next_block
->offset
>= candidate
) {
1906 next
= MIN(next
, next_block
->offset
);
1910 /* If it fits remember our place and remember the size
1911 * of gap, but keep going so that we might find a smaller
1912 * gap to fill so avoiding fragmentation.
1914 if (next
- candidate
>= size
&& next
- candidate
< mingap
) {
1916 mingap
= next
- candidate
;
1919 trace_find_ram_offset_loop(size
, candidate
, offset
, next
, mingap
);
1922 if (offset
== RAM_ADDR_MAX
) {
1923 fprintf(stderr
, "Failed to find gap of requested size: %" PRIu64
"\n",
1928 trace_find_ram_offset(size
, offset
);
1933 unsigned long last_ram_page(void)
1936 ram_addr_t last
= 0;
1939 RAMBLOCK_FOREACH(block
) {
1940 last
= MAX(last
, block
->offset
+ block
->max_length
);
1943 return last
>> TARGET_PAGE_BITS
;
1946 static void qemu_ram_setup_dump(void *addr
, ram_addr_t size
)
1950 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1951 if (!machine_dump_guest_core(current_machine
)) {
1952 ret
= qemu_madvise(addr
, size
, QEMU_MADV_DONTDUMP
);
1954 perror("qemu_madvise");
1955 fprintf(stderr
, "madvise doesn't support MADV_DONTDUMP, "
1956 "but dump_guest_core=off specified\n");
1961 const char *qemu_ram_get_idstr(RAMBlock
*rb
)
1966 bool qemu_ram_is_shared(RAMBlock
*rb
)
1968 return rb
->flags
& RAM_SHARED
;
1971 /* Note: Only set at the start of postcopy */
1972 bool qemu_ram_is_uf_zeroable(RAMBlock
*rb
)
1974 return rb
->flags
& RAM_UF_ZEROPAGE
;
1977 void qemu_ram_set_uf_zeroable(RAMBlock
*rb
)
1979 rb
->flags
|= RAM_UF_ZEROPAGE
;
1982 bool qemu_ram_is_migratable(RAMBlock
*rb
)
1984 return rb
->flags
& RAM_MIGRATABLE
;
1987 void qemu_ram_set_migratable(RAMBlock
*rb
)
1989 rb
->flags
|= RAM_MIGRATABLE
;
1992 void qemu_ram_unset_migratable(RAMBlock
*rb
)
1994 rb
->flags
&= ~RAM_MIGRATABLE
;
1997 /* Called with iothread lock held. */
1998 void qemu_ram_set_idstr(RAMBlock
*new_block
, const char *name
, DeviceState
*dev
)
2003 assert(!new_block
->idstr
[0]);
2006 char *id
= qdev_get_dev_path(dev
);
2008 snprintf(new_block
->idstr
, sizeof(new_block
->idstr
), "%s/", id
);
2012 pstrcat(new_block
->idstr
, sizeof(new_block
->idstr
), name
);
2015 RAMBLOCK_FOREACH(block
) {
2016 if (block
!= new_block
&&
2017 !strcmp(block
->idstr
, new_block
->idstr
)) {
2018 fprintf(stderr
, "RAMBlock \"%s\" already registered, abort!\n",
2026 /* Called with iothread lock held. */
2027 void qemu_ram_unset_idstr(RAMBlock
*block
)
2029 /* FIXME: arch_init.c assumes that this is not called throughout
2030 * migration. Ignore the problem since hot-unplug during migration
2031 * does not work anyway.
2034 memset(block
->idstr
, 0, sizeof(block
->idstr
));
2038 size_t qemu_ram_pagesize(RAMBlock
*rb
)
2040 return rb
->page_size
;
2043 /* Returns the largest size of page in use */
2044 size_t qemu_ram_pagesize_largest(void)
2049 RAMBLOCK_FOREACH(block
) {
2050 largest
= MAX(largest
, qemu_ram_pagesize(block
));
2056 static int memory_try_enable_merging(void *addr
, size_t len
)
2058 if (!machine_mem_merge(current_machine
)) {
2059 /* disabled by the user */
2063 return qemu_madvise(addr
, len
, QEMU_MADV_MERGEABLE
);
2066 /* Only legal before guest might have detected the memory size: e.g. on
2067 * incoming migration, or right after reset.
2069 * As memory core doesn't know how is memory accessed, it is up to
2070 * resize callback to update device state and/or add assertions to detect
2071 * misuse, if necessary.
2073 int qemu_ram_resize(RAMBlock
*block
, ram_addr_t newsize
, Error
**errp
)
2077 newsize
= HOST_PAGE_ALIGN(newsize
);
2079 if (block
->used_length
== newsize
) {
2083 if (!(block
->flags
& RAM_RESIZEABLE
)) {
2084 error_setg_errno(errp
, EINVAL
,
2085 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2086 " in != 0x" RAM_ADDR_FMT
, block
->idstr
,
2087 newsize
, block
->used_length
);
2091 if (block
->max_length
< newsize
) {
2092 error_setg_errno(errp
, EINVAL
,
2093 "Length too large: %s: 0x" RAM_ADDR_FMT
2094 " > 0x" RAM_ADDR_FMT
, block
->idstr
,
2095 newsize
, block
->max_length
);
2099 cpu_physical_memory_clear_dirty_range(block
->offset
, block
->used_length
);
2100 block
->used_length
= newsize
;
2101 cpu_physical_memory_set_dirty_range(block
->offset
, block
->used_length
,
2103 memory_region_set_size(block
->mr
, newsize
);
2104 if (block
->resized
) {
2105 block
->resized(block
->idstr
, newsize
, block
->host
);
2110 /* Called with ram_list.mutex held */
2111 static void dirty_memory_extend(ram_addr_t old_ram_size
,
2112 ram_addr_t new_ram_size
)
2114 ram_addr_t old_num_blocks
= DIV_ROUND_UP(old_ram_size
,
2115 DIRTY_MEMORY_BLOCK_SIZE
);
2116 ram_addr_t new_num_blocks
= DIV_ROUND_UP(new_ram_size
,
2117 DIRTY_MEMORY_BLOCK_SIZE
);
2120 /* Only need to extend if block count increased */
2121 if (new_num_blocks
<= old_num_blocks
) {
2125 for (i
= 0; i
< DIRTY_MEMORY_NUM
; i
++) {
2126 DirtyMemoryBlocks
*old_blocks
;
2127 DirtyMemoryBlocks
*new_blocks
;
2130 old_blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[i
]);
2131 new_blocks
= g_malloc(sizeof(*new_blocks
) +
2132 sizeof(new_blocks
->blocks
[0]) * new_num_blocks
);
2134 if (old_num_blocks
) {
2135 memcpy(new_blocks
->blocks
, old_blocks
->blocks
,
2136 old_num_blocks
* sizeof(old_blocks
->blocks
[0]));
2139 for (j
= old_num_blocks
; j
< new_num_blocks
; j
++) {
2140 new_blocks
->blocks
[j
] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE
);
2143 atomic_rcu_set(&ram_list
.dirty_memory
[i
], new_blocks
);
2146 g_free_rcu(old_blocks
, rcu
);
2151 static void ram_block_add(RAMBlock
*new_block
, Error
**errp
, bool shared
)
2154 RAMBlock
*last_block
= NULL
;
2155 ram_addr_t old_ram_size
, new_ram_size
;
2158 old_ram_size
= last_ram_page();
2160 qemu_mutex_lock_ramlist();
2161 new_block
->offset
= find_ram_offset(new_block
->max_length
);
2163 if (!new_block
->host
) {
2164 if (xen_enabled()) {
2165 xen_ram_alloc(new_block
->offset
, new_block
->max_length
,
2166 new_block
->mr
, &err
);
2168 error_propagate(errp
, err
);
2169 qemu_mutex_unlock_ramlist();
2173 new_block
->host
= phys_mem_alloc(new_block
->max_length
,
2174 &new_block
->mr
->align
, shared
);
2175 if (!new_block
->host
) {
2176 error_setg_errno(errp
, errno
,
2177 "cannot set up guest memory '%s'",
2178 memory_region_name(new_block
->mr
));
2179 qemu_mutex_unlock_ramlist();
2182 memory_try_enable_merging(new_block
->host
, new_block
->max_length
);
2186 new_ram_size
= MAX(old_ram_size
,
2187 (new_block
->offset
+ new_block
->max_length
) >> TARGET_PAGE_BITS
);
2188 if (new_ram_size
> old_ram_size
) {
2189 dirty_memory_extend(old_ram_size
, new_ram_size
);
2191 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2192 * QLIST (which has an RCU-friendly variant) does not have insertion at
2193 * tail, so save the last element in last_block.
2195 RAMBLOCK_FOREACH(block
) {
2197 if (block
->max_length
< new_block
->max_length
) {
2202 QLIST_INSERT_BEFORE_RCU(block
, new_block
, next
);
2203 } else if (last_block
) {
2204 QLIST_INSERT_AFTER_RCU(last_block
, new_block
, next
);
2205 } else { /* list is empty */
2206 QLIST_INSERT_HEAD_RCU(&ram_list
.blocks
, new_block
, next
);
2208 ram_list
.mru_block
= NULL
;
2210 /* Write list before version */
2213 qemu_mutex_unlock_ramlist();
2215 cpu_physical_memory_set_dirty_range(new_block
->offset
,
2216 new_block
->used_length
,
2219 if (new_block
->host
) {
2220 qemu_ram_setup_dump(new_block
->host
, new_block
->max_length
);
2221 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_HUGEPAGE
);
2222 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2223 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_DONTFORK
);
2224 ram_block_notify_add(new_block
->host
, new_block
->max_length
);
2229 RAMBlock
*qemu_ram_alloc_from_fd(ram_addr_t size
, MemoryRegion
*mr
,
2233 RAMBlock
*new_block
;
2234 Error
*local_err
= NULL
;
2237 if (xen_enabled()) {
2238 error_setg(errp
, "-mem-path not supported with Xen");
2242 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2244 "host lacks kvm mmu notifiers, -mem-path unsupported");
2248 if (phys_mem_alloc
!= qemu_anon_ram_alloc
) {
2250 * file_ram_alloc() needs to allocate just like
2251 * phys_mem_alloc, but we haven't bothered to provide
2255 "-mem-path not supported with this accelerator");
2259 size
= HOST_PAGE_ALIGN(size
);
2260 file_size
= get_file_size(fd
);
2261 if (file_size
> 0 && file_size
< size
) {
2262 error_setg(errp
, "backing store %s size 0x%" PRIx64
2263 " does not match 'size' option 0x" RAM_ADDR_FMT
,
2264 mem_path
, file_size
, size
);
2268 new_block
= g_malloc0(sizeof(*new_block
));
2270 new_block
->used_length
= size
;
2271 new_block
->max_length
= size
;
2272 new_block
->flags
= share
? RAM_SHARED
: 0;
2273 new_block
->host
= file_ram_alloc(new_block
, size
, fd
, !file_size
, errp
);
2274 if (!new_block
->host
) {
2279 ram_block_add(new_block
, &local_err
, share
);
2282 error_propagate(errp
, local_err
);
2290 RAMBlock
*qemu_ram_alloc_from_file(ram_addr_t size
, MemoryRegion
*mr
,
2291 bool share
, const char *mem_path
,
2298 fd
= file_ram_open(mem_path
, memory_region_name(mr
), &created
, errp
);
2303 block
= qemu_ram_alloc_from_fd(size
, mr
, share
, fd
, errp
);
2317 RAMBlock
*qemu_ram_alloc_internal(ram_addr_t size
, ram_addr_t max_size
,
2318 void (*resized
)(const char*,
2321 void *host
, bool resizeable
, bool share
,
2322 MemoryRegion
*mr
, Error
**errp
)
2324 RAMBlock
*new_block
;
2325 Error
*local_err
= NULL
;
2327 size
= HOST_PAGE_ALIGN(size
);
2328 max_size
= HOST_PAGE_ALIGN(max_size
);
2329 new_block
= g_malloc0(sizeof(*new_block
));
2331 new_block
->resized
= resized
;
2332 new_block
->used_length
= size
;
2333 new_block
->max_length
= max_size
;
2334 assert(max_size
>= size
);
2336 new_block
->page_size
= getpagesize();
2337 new_block
->host
= host
;
2339 new_block
->flags
|= RAM_PREALLOC
;
2342 new_block
->flags
|= RAM_RESIZEABLE
;
2344 ram_block_add(new_block
, &local_err
, share
);
2347 error_propagate(errp
, local_err
);
2353 RAMBlock
*qemu_ram_alloc_from_ptr(ram_addr_t size
, void *host
,
2354 MemoryRegion
*mr
, Error
**errp
)
2356 return qemu_ram_alloc_internal(size
, size
, NULL
, host
, false,
2360 RAMBlock
*qemu_ram_alloc(ram_addr_t size
, bool share
,
2361 MemoryRegion
*mr
, Error
**errp
)
2363 return qemu_ram_alloc_internal(size
, size
, NULL
, NULL
, false,
2367 RAMBlock
*qemu_ram_alloc_resizeable(ram_addr_t size
, ram_addr_t maxsz
,
2368 void (*resized
)(const char*,
2371 MemoryRegion
*mr
, Error
**errp
)
2373 return qemu_ram_alloc_internal(size
, maxsz
, resized
, NULL
, true,
2377 static void reclaim_ramblock(RAMBlock
*block
)
2379 if (block
->flags
& RAM_PREALLOC
) {
2381 } else if (xen_enabled()) {
2382 xen_invalidate_map_cache_entry(block
->host
);
2384 } else if (block
->fd
>= 0) {
2385 qemu_ram_munmap(block
->host
, block
->max_length
);
2389 qemu_anon_ram_free(block
->host
, block
->max_length
);
2394 void qemu_ram_free(RAMBlock
*block
)
2401 ram_block_notify_remove(block
->host
, block
->max_length
);
2404 qemu_mutex_lock_ramlist();
2405 QLIST_REMOVE_RCU(block
, next
);
2406 ram_list
.mru_block
= NULL
;
2407 /* Write list before version */
2410 call_rcu(block
, reclaim_ramblock
, rcu
);
2411 qemu_mutex_unlock_ramlist();
2415 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
)
2422 RAMBLOCK_FOREACH(block
) {
2423 offset
= addr
- block
->offset
;
2424 if (offset
< block
->max_length
) {
2425 vaddr
= ramblock_ptr(block
, offset
);
2426 if (block
->flags
& RAM_PREALLOC
) {
2428 } else if (xen_enabled()) {
2432 if (block
->fd
>= 0) {
2433 flags
|= (block
->flags
& RAM_SHARED
?
2434 MAP_SHARED
: MAP_PRIVATE
);
2435 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2436 flags
, block
->fd
, offset
);
2439 * Remap needs to match alloc. Accelerators that
2440 * set phys_mem_alloc never remap. If they did,
2441 * we'd need a remap hook here.
2443 assert(phys_mem_alloc
== qemu_anon_ram_alloc
);
2445 flags
|= MAP_PRIVATE
| MAP_ANONYMOUS
;
2446 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2449 if (area
!= vaddr
) {
2450 error_report("Could not remap addr: "
2451 RAM_ADDR_FMT
"@" RAM_ADDR_FMT
"",
2455 memory_try_enable_merging(vaddr
, length
);
2456 qemu_ram_setup_dump(vaddr
, length
);
2461 #endif /* !_WIN32 */
2463 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2464 * This should not be used for general purpose DMA. Use address_space_map
2465 * or address_space_rw instead. For local memory (e.g. video ram) that the
2466 * device owns, use memory_region_get_ram_ptr.
2468 * Called within RCU critical section.
2470 void *qemu_map_ram_ptr(RAMBlock
*ram_block
, ram_addr_t addr
)
2472 RAMBlock
*block
= ram_block
;
2474 if (block
== NULL
) {
2475 block
= qemu_get_ram_block(addr
);
2476 addr
-= block
->offset
;
2479 if (xen_enabled() && block
->host
== NULL
) {
2480 /* We need to check if the requested address is in the RAM
2481 * because we don't want to map the entire memory in QEMU.
2482 * In that case just map until the end of the page.
2484 if (block
->offset
== 0) {
2485 return xen_map_cache(addr
, 0, 0, false);
2488 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, false);
2490 return ramblock_ptr(block
, addr
);
2493 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2494 * but takes a size argument.
2496 * Called within RCU critical section.
2498 static void *qemu_ram_ptr_length(RAMBlock
*ram_block
, ram_addr_t addr
,
2499 hwaddr
*size
, bool lock
)
2501 RAMBlock
*block
= ram_block
;
2506 if (block
== NULL
) {
2507 block
= qemu_get_ram_block(addr
);
2508 addr
-= block
->offset
;
2510 *size
= MIN(*size
, block
->max_length
- addr
);
2512 if (xen_enabled() && block
->host
== NULL
) {
2513 /* We need to check if the requested address is in the RAM
2514 * because we don't want to map the entire memory in QEMU.
2515 * In that case just map the requested area.
2517 if (block
->offset
== 0) {
2518 return xen_map_cache(addr
, *size
, lock
, lock
);
2521 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, lock
);
2524 return ramblock_ptr(block
, addr
);
2527 /* Return the offset of a hostpointer within a ramblock */
2528 ram_addr_t
qemu_ram_block_host_offset(RAMBlock
*rb
, void *host
)
2530 ram_addr_t res
= (uint8_t *)host
- (uint8_t *)rb
->host
;
2531 assert((uintptr_t)host
>= (uintptr_t)rb
->host
);
2532 assert(res
< rb
->max_length
);
2538 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2541 * ptr: Host pointer to look up
2542 * round_offset: If true round the result offset down to a page boundary
2543 * *ram_addr: set to result ram_addr
2544 * *offset: set to result offset within the RAMBlock
2546 * Returns: RAMBlock (or NULL if not found)
2548 * By the time this function returns, the returned pointer is not protected
2549 * by RCU anymore. If the caller is not within an RCU critical section and
2550 * does not hold the iothread lock, it must have other means of protecting the
2551 * pointer, such as a reference to the region that includes the incoming
2554 RAMBlock
*qemu_ram_block_from_host(void *ptr
, bool round_offset
,
2558 uint8_t *host
= ptr
;
2560 if (xen_enabled()) {
2561 ram_addr_t ram_addr
;
2563 ram_addr
= xen_ram_addr_from_mapcache(ptr
);
2564 block
= qemu_get_ram_block(ram_addr
);
2566 *offset
= ram_addr
- block
->offset
;
2573 block
= atomic_rcu_read(&ram_list
.mru_block
);
2574 if (block
&& block
->host
&& host
- block
->host
< block
->max_length
) {
2578 RAMBLOCK_FOREACH(block
) {
2579 /* This case append when the block is not mapped. */
2580 if (block
->host
== NULL
) {
2583 if (host
- block
->host
< block
->max_length
) {
2592 *offset
= (host
- block
->host
);
2594 *offset
&= TARGET_PAGE_MASK
;
2601 * Finds the named RAMBlock
2603 * name: The name of RAMBlock to find
2605 * Returns: RAMBlock (or NULL if not found)
2607 RAMBlock
*qemu_ram_block_by_name(const char *name
)
2611 RAMBLOCK_FOREACH(block
) {
2612 if (!strcmp(name
, block
->idstr
)) {
2620 /* Some of the softmmu routines need to translate from a host pointer
2621 (typically a TLB entry) back to a ram offset. */
2622 ram_addr_t
qemu_ram_addr_from_host(void *ptr
)
2627 block
= qemu_ram_block_from_host(ptr
, false, &offset
);
2629 return RAM_ADDR_INVALID
;
2632 return block
->offset
+ offset
;
2635 /* Called within RCU critical section. */
2636 void memory_notdirty_write_prepare(NotDirtyInfo
*ndi
,
2639 ram_addr_t ram_addr
,
2643 ndi
->ram_addr
= ram_addr
;
2644 ndi
->mem_vaddr
= mem_vaddr
;
2648 assert(tcg_enabled());
2649 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
2650 ndi
->pages
= page_collection_lock(ram_addr
, ram_addr
+ size
);
2651 tb_invalidate_phys_page_fast(ndi
->pages
, ram_addr
, size
);
2655 /* Called within RCU critical section. */
2656 void memory_notdirty_write_complete(NotDirtyInfo
*ndi
)
2659 assert(tcg_enabled());
2660 page_collection_unlock(ndi
->pages
);
2664 /* Set both VGA and migration bits for simplicity and to remove
2665 * the notdirty callback faster.
2667 cpu_physical_memory_set_dirty_range(ndi
->ram_addr
, ndi
->size
,
2668 DIRTY_CLIENTS_NOCODE
);
2669 /* we remove the notdirty callback only if the code has been
2671 if (!cpu_physical_memory_is_clean(ndi
->ram_addr
)) {
2672 tlb_set_dirty(ndi
->cpu
, ndi
->mem_vaddr
);
2676 /* Called within RCU critical section. */
2677 static void notdirty_mem_write(void *opaque
, hwaddr ram_addr
,
2678 uint64_t val
, unsigned size
)
2682 memory_notdirty_write_prepare(&ndi
, current_cpu
, current_cpu
->mem_io_vaddr
,
2685 stn_p(qemu_map_ram_ptr(NULL
, ram_addr
), size
, val
);
2686 memory_notdirty_write_complete(&ndi
);
2689 static bool notdirty_mem_accepts(void *opaque
, hwaddr addr
,
2690 unsigned size
, bool is_write
,
2696 static const MemoryRegionOps notdirty_mem_ops
= {
2697 .write
= notdirty_mem_write
,
2698 .valid
.accepts
= notdirty_mem_accepts
,
2699 .endianness
= DEVICE_NATIVE_ENDIAN
,
2701 .min_access_size
= 1,
2702 .max_access_size
= 8,
2706 .min_access_size
= 1,
2707 .max_access_size
= 8,
2712 /* Generate a debug exception if a watchpoint has been hit. */
2713 static void check_watchpoint(int offset
, int len
, MemTxAttrs attrs
, int flags
)
2715 CPUState
*cpu
= current_cpu
;
2716 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
2720 assert(tcg_enabled());
2721 if (cpu
->watchpoint_hit
) {
2722 /* We re-entered the check after replacing the TB. Now raise
2723 * the debug interrupt so that is will trigger after the
2724 * current instruction. */
2725 cpu_interrupt(cpu
, CPU_INTERRUPT_DEBUG
);
2728 vaddr
= (cpu
->mem_io_vaddr
& TARGET_PAGE_MASK
) + offset
;
2729 vaddr
= cc
->adjust_watchpoint_address(cpu
, vaddr
, len
);
2730 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
2731 if (cpu_watchpoint_address_matches(wp
, vaddr
, len
)
2732 && (wp
->flags
& flags
)) {
2733 if (flags
== BP_MEM_READ
) {
2734 wp
->flags
|= BP_WATCHPOINT_HIT_READ
;
2736 wp
->flags
|= BP_WATCHPOINT_HIT_WRITE
;
2738 wp
->hitaddr
= vaddr
;
2739 wp
->hitattrs
= attrs
;
2740 if (!cpu
->watchpoint_hit
) {
2741 if (wp
->flags
& BP_CPU
&&
2742 !cc
->debug_check_watchpoint(cpu
, wp
)) {
2743 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2746 cpu
->watchpoint_hit
= wp
;
2749 tb_check_watchpoint(cpu
);
2750 if (wp
->flags
& BP_STOP_BEFORE_ACCESS
) {
2751 cpu
->exception_index
= EXCP_DEBUG
;
2755 /* Force execution of one insn next time. */
2756 cpu
->cflags_next_tb
= 1 | curr_cflags();
2758 cpu_loop_exit_noexc(cpu
);
2762 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2767 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2768 so these check for a hit then pass through to the normal out-of-line
2770 static MemTxResult
watch_mem_read(void *opaque
, hwaddr addr
, uint64_t *pdata
,
2771 unsigned size
, MemTxAttrs attrs
)
2775 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2776 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2778 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_READ
);
2781 data
= address_space_ldub(as
, addr
, attrs
, &res
);
2784 data
= address_space_lduw(as
, addr
, attrs
, &res
);
2787 data
= address_space_ldl(as
, addr
, attrs
, &res
);
2790 data
= address_space_ldq(as
, addr
, attrs
, &res
);
2798 static MemTxResult
watch_mem_write(void *opaque
, hwaddr addr
,
2799 uint64_t val
, unsigned size
,
2803 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2804 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2806 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_WRITE
);
2809 address_space_stb(as
, addr
, val
, attrs
, &res
);
2812 address_space_stw(as
, addr
, val
, attrs
, &res
);
2815 address_space_stl(as
, addr
, val
, attrs
, &res
);
2818 address_space_stq(as
, addr
, val
, attrs
, &res
);
2825 static const MemoryRegionOps watch_mem_ops
= {
2826 .read_with_attrs
= watch_mem_read
,
2827 .write_with_attrs
= watch_mem_write
,
2828 .endianness
= DEVICE_NATIVE_ENDIAN
,
2830 .min_access_size
= 1,
2831 .max_access_size
= 8,
2835 .min_access_size
= 1,
2836 .max_access_size
= 8,
2841 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
2842 MemTxAttrs attrs
, uint8_t *buf
, int len
);
2843 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
2844 const uint8_t *buf
, int len
);
2845 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, int len
,
2846 bool is_write
, MemTxAttrs attrs
);
2848 static MemTxResult
subpage_read(void *opaque
, hwaddr addr
, uint64_t *data
,
2849 unsigned len
, MemTxAttrs attrs
)
2851 subpage_t
*subpage
= opaque
;
2855 #if defined(DEBUG_SUBPAGE)
2856 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
"\n", __func__
,
2857 subpage
, len
, addr
);
2859 res
= flatview_read(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2863 *data
= ldn_p(buf
, len
);
2867 static MemTxResult
subpage_write(void *opaque
, hwaddr addr
,
2868 uint64_t value
, unsigned len
, MemTxAttrs attrs
)
2870 subpage_t
*subpage
= opaque
;
2873 #if defined(DEBUG_SUBPAGE)
2874 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2875 " value %"PRIx64
"\n",
2876 __func__
, subpage
, len
, addr
, value
);
2878 stn_p(buf
, len
, value
);
2879 return flatview_write(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2882 static bool subpage_accepts(void *opaque
, hwaddr addr
,
2883 unsigned len
, bool is_write
,
2886 subpage_t
*subpage
= opaque
;
2887 #if defined(DEBUG_SUBPAGE)
2888 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx
"\n",
2889 __func__
, subpage
, is_write
? 'w' : 'r', len
, addr
);
2892 return flatview_access_valid(subpage
->fv
, addr
+ subpage
->base
,
2893 len
, is_write
, attrs
);
2896 static const MemoryRegionOps subpage_ops
= {
2897 .read_with_attrs
= subpage_read
,
2898 .write_with_attrs
= subpage_write
,
2899 .impl
.min_access_size
= 1,
2900 .impl
.max_access_size
= 8,
2901 .valid
.min_access_size
= 1,
2902 .valid
.max_access_size
= 8,
2903 .valid
.accepts
= subpage_accepts
,
2904 .endianness
= DEVICE_NATIVE_ENDIAN
,
2907 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
2912 if (start
>= TARGET_PAGE_SIZE
|| end
>= TARGET_PAGE_SIZE
)
2914 idx
= SUBPAGE_IDX(start
);
2915 eidx
= SUBPAGE_IDX(end
);
2916 #if defined(DEBUG_SUBPAGE)
2917 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2918 __func__
, mmio
, start
, end
, idx
, eidx
, section
);
2920 for (; idx
<= eidx
; idx
++) {
2921 mmio
->sub_section
[idx
] = section
;
2927 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
)
2931 mmio
= g_malloc0(sizeof(subpage_t
) + TARGET_PAGE_SIZE
* sizeof(uint16_t));
2934 memory_region_init_io(&mmio
->iomem
, NULL
, &subpage_ops
, mmio
,
2935 NULL
, TARGET_PAGE_SIZE
);
2936 mmio
->iomem
.subpage
= true;
2937 #if defined(DEBUG_SUBPAGE)
2938 printf("%s: %p base " TARGET_FMT_plx
" len %08x\n", __func__
,
2939 mmio
, base
, TARGET_PAGE_SIZE
);
2941 subpage_register(mmio
, 0, TARGET_PAGE_SIZE
-1, PHYS_SECTION_UNASSIGNED
);
2946 static uint16_t dummy_section(PhysPageMap
*map
, FlatView
*fv
, MemoryRegion
*mr
)
2949 MemoryRegionSection section
= {
2952 .offset_within_address_space
= 0,
2953 .offset_within_region
= 0,
2954 .size
= int128_2_64(),
2957 return phys_section_add(map
, §ion
);
2960 static void readonly_mem_write(void *opaque
, hwaddr addr
,
2961 uint64_t val
, unsigned size
)
2963 /* Ignore any write to ROM. */
2966 static bool readonly_mem_accepts(void *opaque
, hwaddr addr
,
2967 unsigned size
, bool is_write
,
2973 /* This will only be used for writes, because reads are special cased
2974 * to directly access the underlying host ram.
2976 static const MemoryRegionOps readonly_mem_ops
= {
2977 .write
= readonly_mem_write
,
2978 .valid
.accepts
= readonly_mem_accepts
,
2979 .endianness
= DEVICE_NATIVE_ENDIAN
,
2981 .min_access_size
= 1,
2982 .max_access_size
= 8,
2986 .min_access_size
= 1,
2987 .max_access_size
= 8,
2992 MemoryRegionSection
*iotlb_to_section(CPUState
*cpu
,
2993 hwaddr index
, MemTxAttrs attrs
)
2995 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
2996 CPUAddressSpace
*cpuas
= &cpu
->cpu_ases
[asidx
];
2997 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpuas
->memory_dispatch
);
2998 MemoryRegionSection
*sections
= d
->map
.sections
;
3000 return §ions
[index
& ~TARGET_PAGE_MASK
];
3003 static void io_mem_init(void)
3005 memory_region_init_io(&io_mem_rom
, NULL
, &readonly_mem_ops
,
3006 NULL
, NULL
, UINT64_MAX
);
3007 memory_region_init_io(&io_mem_unassigned
, NULL
, &unassigned_mem_ops
, NULL
,
3010 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
3011 * which can be called without the iothread mutex.
3013 memory_region_init_io(&io_mem_notdirty
, NULL
, ¬dirty_mem_ops
, NULL
,
3015 memory_region_clear_global_locking(&io_mem_notdirty
);
3017 memory_region_init_io(&io_mem_watch
, NULL
, &watch_mem_ops
, NULL
,
3021 AddressSpaceDispatch
*address_space_dispatch_new(FlatView
*fv
)
3023 AddressSpaceDispatch
*d
= g_new0(AddressSpaceDispatch
, 1);
3026 n
= dummy_section(&d
->map
, fv
, &io_mem_unassigned
);
3027 assert(n
== PHYS_SECTION_UNASSIGNED
);
3028 n
= dummy_section(&d
->map
, fv
, &io_mem_notdirty
);
3029 assert(n
== PHYS_SECTION_NOTDIRTY
);
3030 n
= dummy_section(&d
->map
, fv
, &io_mem_rom
);
3031 assert(n
== PHYS_SECTION_ROM
);
3032 n
= dummy_section(&d
->map
, fv
, &io_mem_watch
);
3033 assert(n
== PHYS_SECTION_WATCH
);
3035 d
->phys_map
= (PhysPageEntry
) { .ptr
= PHYS_MAP_NODE_NIL
, .skip
= 1 };
3040 void address_space_dispatch_free(AddressSpaceDispatch
*d
)
3042 phys_sections_free(&d
->map
);
3046 static void tcg_commit(MemoryListener
*listener
)
3048 CPUAddressSpace
*cpuas
;
3049 AddressSpaceDispatch
*d
;
3051 assert(tcg_enabled());
3052 /* since each CPU stores ram addresses in its TLB cache, we must
3053 reset the modified entries */
3054 cpuas
= container_of(listener
, CPUAddressSpace
, tcg_as_listener
);
3055 cpu_reloading_memory_map();
3056 /* The CPU and TLB are protected by the iothread lock.
3057 * We reload the dispatch pointer now because cpu_reloading_memory_map()
3058 * may have split the RCU critical section.
3060 d
= address_space_to_dispatch(cpuas
->as
);
3061 atomic_rcu_set(&cpuas
->memory_dispatch
, d
);
3062 tlb_flush(cpuas
->cpu
);
3065 static void memory_map_init(void)
3067 system_memory
= g_malloc(sizeof(*system_memory
));
3069 memory_region_init(system_memory
, NULL
, "system", UINT64_MAX
);
3070 address_space_init(&address_space_memory
, system_memory
, "memory");
3072 system_io
= g_malloc(sizeof(*system_io
));
3073 memory_region_init_io(system_io
, NULL
, &unassigned_io_ops
, NULL
, "io",
3075 address_space_init(&address_space_io
, system_io
, "I/O");
3078 MemoryRegion
*get_system_memory(void)
3080 return system_memory
;
3083 MemoryRegion
*get_system_io(void)
3088 #endif /* !defined(CONFIG_USER_ONLY) */
3090 /* physical memory access (slow version, mainly for debug) */
3091 #if defined(CONFIG_USER_ONLY)
3092 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3093 uint8_t *buf
, int len
, int is_write
)
3100 page
= addr
& TARGET_PAGE_MASK
;
3101 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3104 flags
= page_get_flags(page
);
3105 if (!(flags
& PAGE_VALID
))
3108 if (!(flags
& PAGE_WRITE
))
3110 /* XXX: this code should not depend on lock_user */
3111 if (!(p
= lock_user(VERIFY_WRITE
, addr
, l
, 0)))
3114 unlock_user(p
, addr
, l
);
3116 if (!(flags
& PAGE_READ
))
3118 /* XXX: this code should not depend on lock_user */
3119 if (!(p
= lock_user(VERIFY_READ
, addr
, l
, 1)))
3122 unlock_user(p
, addr
, 0);
3133 static void invalidate_and_set_dirty(MemoryRegion
*mr
, hwaddr addr
,
3136 uint8_t dirty_log_mask
= memory_region_get_dirty_log_mask(mr
);
3137 addr
+= memory_region_get_ram_addr(mr
);
3139 /* No early return if dirty_log_mask is or becomes 0, because
3140 * cpu_physical_memory_set_dirty_range will still call
3141 * xen_modified_memory.
3143 if (dirty_log_mask
) {
3145 cpu_physical_memory_range_includes_clean(addr
, length
, dirty_log_mask
);
3147 if (dirty_log_mask
& (1 << DIRTY_MEMORY_CODE
)) {
3148 assert(tcg_enabled());
3150 tb_invalidate_phys_range(addr
, addr
+ length
);
3152 dirty_log_mask
&= ~(1 << DIRTY_MEMORY_CODE
);
3154 cpu_physical_memory_set_dirty_range(addr
, length
, dirty_log_mask
);
3157 static int memory_access_size(MemoryRegion
*mr
, unsigned l
, hwaddr addr
)
3159 unsigned access_size_max
= mr
->ops
->valid
.max_access_size
;
3161 /* Regions are assumed to support 1-4 byte accesses unless
3162 otherwise specified. */
3163 if (access_size_max
== 0) {
3164 access_size_max
= 4;
3167 /* Bound the maximum access by the alignment of the address. */
3168 if (!mr
->ops
->impl
.unaligned
) {
3169 unsigned align_size_max
= addr
& -addr
;
3170 if (align_size_max
!= 0 && align_size_max
< access_size_max
) {
3171 access_size_max
= align_size_max
;
3175 /* Don't attempt accesses larger than the maximum. */
3176 if (l
> access_size_max
) {
3177 l
= access_size_max
;
3184 static bool prepare_mmio_access(MemoryRegion
*mr
)
3186 bool unlocked
= !qemu_mutex_iothread_locked();
3187 bool release_lock
= false;
3189 if (unlocked
&& mr
->global_locking
) {
3190 qemu_mutex_lock_iothread();
3192 release_lock
= true;
3194 if (mr
->flush_coalesced_mmio
) {
3196 qemu_mutex_lock_iothread();
3198 qemu_flush_coalesced_mmio_buffer();
3200 qemu_mutex_unlock_iothread();
3204 return release_lock
;
3207 /* Called within RCU critical section. */
3208 static MemTxResult
flatview_write_continue(FlatView
*fv
, hwaddr addr
,
3211 int len
, hwaddr addr1
,
3212 hwaddr l
, MemoryRegion
*mr
)
3216 MemTxResult result
= MEMTX_OK
;
3217 bool release_lock
= false;
3220 if (!memory_access_is_direct(mr
, true)) {
3221 release_lock
|= prepare_mmio_access(mr
);
3222 l
= memory_access_size(mr
, l
, addr1
);
3223 /* XXX: could force current_cpu to NULL to avoid
3225 val
= ldn_p(buf
, l
);
3226 result
|= memory_region_dispatch_write(mr
, addr1
, val
, l
, attrs
);
3229 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3230 memcpy(ptr
, buf
, l
);
3231 invalidate_and_set_dirty(mr
, addr1
, l
);
3235 qemu_mutex_unlock_iothread();
3236 release_lock
= false;
3248 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3254 /* Called from RCU critical section. */
3255 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
3256 const uint8_t *buf
, int len
)
3261 MemTxResult result
= MEMTX_OK
;
3264 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3265 result
= flatview_write_continue(fv
, addr
, attrs
, buf
, len
,
3271 /* Called within RCU critical section. */
3272 MemTxResult
flatview_read_continue(FlatView
*fv
, hwaddr addr
,
3273 MemTxAttrs attrs
, uint8_t *buf
,
3274 int len
, hwaddr addr1
, hwaddr l
,
3279 MemTxResult result
= MEMTX_OK
;
3280 bool release_lock
= false;
3283 if (!memory_access_is_direct(mr
, false)) {
3285 release_lock
|= prepare_mmio_access(mr
);
3286 l
= memory_access_size(mr
, l
, addr1
);
3287 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, l
, attrs
);
3291 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3292 memcpy(buf
, ptr
, l
);
3296 qemu_mutex_unlock_iothread();
3297 release_lock
= false;
3309 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3315 /* Called from RCU critical section. */
3316 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
3317 MemTxAttrs attrs
, uint8_t *buf
, int len
)
3324 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3325 return flatview_read_continue(fv
, addr
, attrs
, buf
, len
,
3329 MemTxResult
address_space_read_full(AddressSpace
*as
, hwaddr addr
,
3330 MemTxAttrs attrs
, uint8_t *buf
, int len
)
3332 MemTxResult result
= MEMTX_OK
;
3337 fv
= address_space_to_flatview(as
);
3338 result
= flatview_read(fv
, addr
, attrs
, buf
, len
);
3345 MemTxResult
address_space_write(AddressSpace
*as
, hwaddr addr
,
3347 const uint8_t *buf
, int len
)
3349 MemTxResult result
= MEMTX_OK
;
3354 fv
= address_space_to_flatview(as
);
3355 result
= flatview_write(fv
, addr
, attrs
, buf
, len
);
3362 MemTxResult
address_space_rw(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
,
3363 uint8_t *buf
, int len
, bool is_write
)
3366 return address_space_write(as
, addr
, attrs
, buf
, len
);
3368 return address_space_read_full(as
, addr
, attrs
, buf
, len
);
3372 void cpu_physical_memory_rw(hwaddr addr
, uint8_t *buf
,
3373 int len
, int is_write
)
3375 address_space_rw(&address_space_memory
, addr
, MEMTXATTRS_UNSPECIFIED
,
3376 buf
, len
, is_write
);
3379 enum write_rom_type
{
3384 static inline void cpu_physical_memory_write_rom_internal(AddressSpace
*as
,
3385 hwaddr addr
, const uint8_t *buf
, int len
, enum write_rom_type type
)
3395 mr
= address_space_translate(as
, addr
, &addr1
, &l
, true,
3396 MEMTXATTRS_UNSPECIFIED
);
3398 if (!(memory_region_is_ram(mr
) ||
3399 memory_region_is_romd(mr
))) {
3400 l
= memory_access_size(mr
, l
, addr1
);
3403 ptr
= qemu_map_ram_ptr(mr
->ram_block
, addr1
);
3406 memcpy(ptr
, buf
, l
);
3407 invalidate_and_set_dirty(mr
, addr1
, l
);
3410 flush_icache_range((uintptr_t)ptr
, (uintptr_t)ptr
+ l
);
3421 /* used for ROM loading : can write in RAM and ROM */
3422 void cpu_physical_memory_write_rom(AddressSpace
*as
, hwaddr addr
,
3423 const uint8_t *buf
, int len
)
3425 cpu_physical_memory_write_rom_internal(as
, addr
, buf
, len
, WRITE_DATA
);
3428 void cpu_flush_icache_range(hwaddr start
, int len
)
3431 * This function should do the same thing as an icache flush that was
3432 * triggered from within the guest. For TCG we are always cache coherent,
3433 * so there is no need to flush anything. For KVM / Xen we need to flush
3434 * the host's instruction cache at least.
3436 if (tcg_enabled()) {
3440 cpu_physical_memory_write_rom_internal(&address_space_memory
,
3441 start
, NULL
, len
, FLUSH_CACHE
);
3452 static BounceBuffer bounce
;
3454 typedef struct MapClient
{
3456 QLIST_ENTRY(MapClient
) link
;
3459 QemuMutex map_client_list_lock
;
3460 static QLIST_HEAD(map_client_list
, MapClient
) map_client_list
3461 = QLIST_HEAD_INITIALIZER(map_client_list
);
3463 static void cpu_unregister_map_client_do(MapClient
*client
)
3465 QLIST_REMOVE(client
, link
);
3469 static void cpu_notify_map_clients_locked(void)
3473 while (!QLIST_EMPTY(&map_client_list
)) {
3474 client
= QLIST_FIRST(&map_client_list
);
3475 qemu_bh_schedule(client
->bh
);
3476 cpu_unregister_map_client_do(client
);
3480 void cpu_register_map_client(QEMUBH
*bh
)
3482 MapClient
*client
= g_malloc(sizeof(*client
));
3484 qemu_mutex_lock(&map_client_list_lock
);
3486 QLIST_INSERT_HEAD(&map_client_list
, client
, link
);
3487 if (!atomic_read(&bounce
.in_use
)) {
3488 cpu_notify_map_clients_locked();
3490 qemu_mutex_unlock(&map_client_list_lock
);
3493 void cpu_exec_init_all(void)
3495 qemu_mutex_init(&ram_list
.mutex
);
3496 /* The data structures we set up here depend on knowing the page size,
3497 * so no more changes can be made after this point.
3498 * In an ideal world, nothing we did before we had finished the
3499 * machine setup would care about the target page size, and we could
3500 * do this much later, rather than requiring board models to state
3501 * up front what their requirements are.
3503 finalize_target_page_bits();
3506 qemu_mutex_init(&map_client_list_lock
);
3509 void cpu_unregister_map_client(QEMUBH
*bh
)
3513 qemu_mutex_lock(&map_client_list_lock
);
3514 QLIST_FOREACH(client
, &map_client_list
, link
) {
3515 if (client
->bh
== bh
) {
3516 cpu_unregister_map_client_do(client
);
3520 qemu_mutex_unlock(&map_client_list_lock
);
3523 static void cpu_notify_map_clients(void)
3525 qemu_mutex_lock(&map_client_list_lock
);
3526 cpu_notify_map_clients_locked();
3527 qemu_mutex_unlock(&map_client_list_lock
);
3530 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, int len
,
3531 bool is_write
, MemTxAttrs attrs
)
3538 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3539 if (!memory_access_is_direct(mr
, is_write
)) {
3540 l
= memory_access_size(mr
, l
, addr
);
3541 if (!memory_region_access_valid(mr
, xlat
, l
, is_write
, attrs
)) {
3552 bool address_space_access_valid(AddressSpace
*as
, hwaddr addr
,
3553 int len
, bool is_write
,
3560 fv
= address_space_to_flatview(as
);
3561 result
= flatview_access_valid(fv
, addr
, len
, is_write
, attrs
);
3567 flatview_extend_translation(FlatView
*fv
, hwaddr addr
,
3569 MemoryRegion
*mr
, hwaddr base
, hwaddr len
,
3570 bool is_write
, MemTxAttrs attrs
)
3574 MemoryRegion
*this_mr
;
3580 if (target_len
== 0) {
3585 this_mr
= flatview_translate(fv
, addr
, &xlat
,
3586 &len
, is_write
, attrs
);
3587 if (this_mr
!= mr
|| xlat
!= base
+ done
) {
3593 /* Map a physical memory region into a host virtual address.
3594 * May map a subset of the requested range, given by and returned in *plen.
3595 * May return NULL if resources needed to perform the mapping are exhausted.
3596 * Use only for reads OR writes - not for read-modify-write operations.
3597 * Use cpu_register_map_client() to know when retrying the map operation is
3598 * likely to succeed.
3600 void *address_space_map(AddressSpace
*as
,
3618 fv
= address_space_to_flatview(as
);
3619 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3621 if (!memory_access_is_direct(mr
, is_write
)) {
3622 if (atomic_xchg(&bounce
.in_use
, true)) {
3626 /* Avoid unbounded allocations */
3627 l
= MIN(l
, TARGET_PAGE_SIZE
);
3628 bounce
.buffer
= qemu_memalign(TARGET_PAGE_SIZE
, l
);
3632 memory_region_ref(mr
);
3635 flatview_read(fv
, addr
, MEMTXATTRS_UNSPECIFIED
,
3641 return bounce
.buffer
;
3645 memory_region_ref(mr
);
3646 *plen
= flatview_extend_translation(fv
, addr
, len
, mr
, xlat
,
3647 l
, is_write
, attrs
);
3648 ptr
= qemu_ram_ptr_length(mr
->ram_block
, xlat
, plen
, true);
3654 /* Unmaps a memory region previously mapped by address_space_map().
3655 * Will also mark the memory as dirty if is_write == 1. access_len gives
3656 * the amount of memory that was actually read or written by the caller.
3658 void address_space_unmap(AddressSpace
*as
, void *buffer
, hwaddr len
,
3659 int is_write
, hwaddr access_len
)
3661 if (buffer
!= bounce
.buffer
) {
3665 mr
= memory_region_from_host(buffer
, &addr1
);
3668 invalidate_and_set_dirty(mr
, addr1
, access_len
);
3670 if (xen_enabled()) {
3671 xen_invalidate_map_cache_entry(buffer
);
3673 memory_region_unref(mr
);
3677 address_space_write(as
, bounce
.addr
, MEMTXATTRS_UNSPECIFIED
,
3678 bounce
.buffer
, access_len
);
3680 qemu_vfree(bounce
.buffer
);
3681 bounce
.buffer
= NULL
;
3682 memory_region_unref(bounce
.mr
);
3683 atomic_mb_set(&bounce
.in_use
, false);
3684 cpu_notify_map_clients();
3687 void *cpu_physical_memory_map(hwaddr addr
,
3691 return address_space_map(&address_space_memory
, addr
, plen
, is_write
,
3692 MEMTXATTRS_UNSPECIFIED
);
3695 void cpu_physical_memory_unmap(void *buffer
, hwaddr len
,
3696 int is_write
, hwaddr access_len
)
3698 return address_space_unmap(&address_space_memory
, buffer
, len
, is_write
, access_len
);
3701 #define ARG1_DECL AddressSpace *as
3704 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3705 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3706 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3707 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3708 #define RCU_READ_LOCK(...) rcu_read_lock()
3709 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3710 #include "memory_ldst.inc.c"
3712 int64_t address_space_cache_init(MemoryRegionCache
*cache
,
3718 AddressSpaceDispatch
*d
;
3725 cache
->fv
= address_space_get_flatview(as
);
3726 d
= flatview_to_dispatch(cache
->fv
);
3727 cache
->mrs
= *address_space_translate_internal(d
, addr
, &cache
->xlat
, &l
, true);
3730 memory_region_ref(mr
);
3731 if (memory_access_is_direct(mr
, is_write
)) {
3732 /* We don't care about the memory attributes here as we're only
3733 * doing this if we found actual RAM, which behaves the same
3734 * regardless of attributes; so UNSPECIFIED is fine.
3736 l
= flatview_extend_translation(cache
->fv
, addr
, len
, mr
,
3737 cache
->xlat
, l
, is_write
,
3738 MEMTXATTRS_UNSPECIFIED
);
3739 cache
->ptr
= qemu_ram_ptr_length(mr
->ram_block
, cache
->xlat
, &l
, true);
3745 cache
->is_write
= is_write
;
3749 void address_space_cache_invalidate(MemoryRegionCache
*cache
,
3753 assert(cache
->is_write
);
3754 if (likely(cache
->ptr
)) {
3755 invalidate_and_set_dirty(cache
->mrs
.mr
, addr
+ cache
->xlat
, access_len
);
3759 void address_space_cache_destroy(MemoryRegionCache
*cache
)
3761 if (!cache
->mrs
.mr
) {
3765 if (xen_enabled()) {
3766 xen_invalidate_map_cache_entry(cache
->ptr
);
3768 memory_region_unref(cache
->mrs
.mr
);
3769 flatview_unref(cache
->fv
);
3770 cache
->mrs
.mr
= NULL
;
3774 /* Called from RCU critical section. This function has the same
3775 * semantics as address_space_translate, but it only works on a
3776 * predefined range of a MemoryRegion that was mapped with
3777 * address_space_cache_init.
3779 static inline MemoryRegion
*address_space_translate_cached(
3780 MemoryRegionCache
*cache
, hwaddr addr
, hwaddr
*xlat
,
3781 hwaddr
*plen
, bool is_write
, MemTxAttrs attrs
)
3783 MemoryRegionSection section
;
3785 IOMMUMemoryRegion
*iommu_mr
;
3786 AddressSpace
*target_as
;
3788 assert(!cache
->ptr
);
3789 *xlat
= addr
+ cache
->xlat
;
3792 iommu_mr
= memory_region_get_iommu(mr
);
3798 section
= address_space_translate_iommu(iommu_mr
, xlat
, plen
,
3799 NULL
, is_write
, true,
3804 /* Called from RCU critical section. address_space_read_cached uses this
3805 * out of line function when the target is an MMIO or IOMMU region.
3808 address_space_read_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3815 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, false,
3816 MEMTXATTRS_UNSPECIFIED
);
3817 flatview_read_continue(cache
->fv
,
3818 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3822 /* Called from RCU critical section. address_space_write_cached uses this
3823 * out of line function when the target is an MMIO or IOMMU region.
3826 address_space_write_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3827 const void *buf
, int len
)
3833 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, true,
3834 MEMTXATTRS_UNSPECIFIED
);
3835 flatview_write_continue(cache
->fv
,
3836 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3840 #define ARG1_DECL MemoryRegionCache *cache
3842 #define SUFFIX _cached_slow
3843 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3844 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3845 #define MAP_RAM(mr, ofs) (cache->ptr + (ofs - cache->xlat))
3846 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3847 #define RCU_READ_LOCK() ((void)0)
3848 #define RCU_READ_UNLOCK() ((void)0)
3849 #include "memory_ldst.inc.c"
3851 /* virtual memory access for debug (includes writing to ROM) */
3852 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3853 uint8_t *buf
, int len
, int is_write
)
3859 cpu_synchronize_state(cpu
);
3864 page
= addr
& TARGET_PAGE_MASK
;
3865 phys_addr
= cpu_get_phys_page_attrs_debug(cpu
, page
, &attrs
);
3866 asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3867 /* if no physical page mapped, return an error */
3868 if (phys_addr
== -1)
3870 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3873 phys_addr
+= (addr
& ~TARGET_PAGE_MASK
);
3875 cpu_physical_memory_write_rom(cpu
->cpu_ases
[asidx
].as
,
3878 address_space_rw(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3879 MEMTXATTRS_UNSPECIFIED
,
3890 * Allows code that needs to deal with migration bitmaps etc to still be built
3891 * target independent.
3893 size_t qemu_target_page_size(void)
3895 return TARGET_PAGE_SIZE
;
3898 int qemu_target_page_bits(void)
3900 return TARGET_PAGE_BITS
;
3903 int qemu_target_page_bits_min(void)
3905 return TARGET_PAGE_BITS_MIN
;
3910 * A helper function for the _utterly broken_ virtio device model to find out if
3911 * it's running on a big endian machine. Don't do this at home kids!
3913 bool target_words_bigendian(void);
3914 bool target_words_bigendian(void)
3916 #if defined(TARGET_WORDS_BIGENDIAN)
3923 #ifndef CONFIG_USER_ONLY
3924 bool cpu_physical_memory_is_io(hwaddr phys_addr
)
3931 mr
= address_space_translate(&address_space_memory
,
3932 phys_addr
, &phys_addr
, &l
, false,
3933 MEMTXATTRS_UNSPECIFIED
);
3935 res
= !(memory_region_is_ram(mr
) || memory_region_is_romd(mr
));
3940 int qemu_ram_foreach_block(RAMBlockIterFunc func
, void *opaque
)
3946 RAMBLOCK_FOREACH(block
) {
3947 ret
= func(block
->idstr
, block
->host
, block
->offset
,
3948 block
->used_length
, opaque
);
3957 int qemu_ram_foreach_migratable_block(RAMBlockIterFunc func
, void *opaque
)
3963 RAMBLOCK_FOREACH(block
) {
3964 if (!qemu_ram_is_migratable(block
)) {
3967 ret
= func(block
->idstr
, block
->host
, block
->offset
,
3968 block
->used_length
, opaque
);
3978 * Unmap pages of memory from start to start+length such that
3979 * they a) read as 0, b) Trigger whatever fault mechanism
3980 * the OS provides for postcopy.
3981 * The pages must be unmapped by the end of the function.
3982 * Returns: 0 on success, none-0 on failure
3985 int ram_block_discard_range(RAMBlock
*rb
, uint64_t start
, size_t length
)
3989 uint8_t *host_startaddr
= rb
->host
+ start
;
3991 if ((uintptr_t)host_startaddr
& (rb
->page_size
- 1)) {
3992 error_report("ram_block_discard_range: Unaligned start address: %p",
3997 if ((start
+ length
) <= rb
->used_length
) {
3998 bool need_madvise
, need_fallocate
;
3999 uint8_t *host_endaddr
= host_startaddr
+ length
;
4000 if ((uintptr_t)host_endaddr
& (rb
->page_size
- 1)) {
4001 error_report("ram_block_discard_range: Unaligned end address: %p",
4006 errno
= ENOTSUP
; /* If we are missing MADVISE etc */
4008 /* The logic here is messy;
4009 * madvise DONTNEED fails for hugepages
4010 * fallocate works on hugepages and shmem
4012 need_madvise
= (rb
->page_size
== qemu_host_page_size
);
4013 need_fallocate
= rb
->fd
!= -1;
4014 if (need_fallocate
) {
4015 /* For a file, this causes the area of the file to be zero'd
4016 * if read, and for hugetlbfs also causes it to be unmapped
4017 * so a userfault will trigger.
4019 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
4020 ret
= fallocate(rb
->fd
, FALLOC_FL_PUNCH_HOLE
| FALLOC_FL_KEEP_SIZE
,
4024 error_report("ram_block_discard_range: Failed to fallocate "
4025 "%s:%" PRIx64
" +%zx (%d)",
4026 rb
->idstr
, start
, length
, ret
);
4031 error_report("ram_block_discard_range: fallocate not available/file"
4032 "%s:%" PRIx64
" +%zx (%d)",
4033 rb
->idstr
, start
, length
, ret
);
4038 /* For normal RAM this causes it to be unmapped,
4039 * for shared memory it causes the local mapping to disappear
4040 * and to fall back on the file contents (which we just
4041 * fallocate'd away).
4043 #if defined(CONFIG_MADVISE)
4044 ret
= madvise(host_startaddr
, length
, MADV_DONTNEED
);
4047 error_report("ram_block_discard_range: Failed to discard range "
4048 "%s:%" PRIx64
" +%zx (%d)",
4049 rb
->idstr
, start
, length
, ret
);
4054 error_report("ram_block_discard_range: MADVISE not available"
4055 "%s:%" PRIx64
" +%zx (%d)",
4056 rb
->idstr
, start
, length
, ret
);
4060 trace_ram_block_discard_range(rb
->idstr
, host_startaddr
, length
,
4061 need_madvise
, need_fallocate
, ret
);
4063 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
4064 "/%zx/" RAM_ADDR_FMT
")",
4065 rb
->idstr
, start
, length
, rb
->used_length
);
4074 void page_size_init(void)
4076 /* NOTE: we can always suppose that qemu_host_page_size >=
4078 if (qemu_host_page_size
== 0) {
4079 qemu_host_page_size
= qemu_real_host_page_size
;
4081 if (qemu_host_page_size
< TARGET_PAGE_SIZE
) {
4082 qemu_host_page_size
= TARGET_PAGE_SIZE
;
4084 qemu_host_page_mask
= -(intptr_t)qemu_host_page_size
;
4087 #if !defined(CONFIG_USER_ONLY)
4089 static void mtree_print_phys_entries(fprintf_function mon
, void *f
,
4090 int start
, int end
, int skip
, int ptr
)
4092 if (start
== end
- 1) {
4093 mon(f
, "\t%3d ", start
);
4095 mon(f
, "\t%3d..%-3d ", start
, end
- 1);
4097 mon(f
, " skip=%d ", skip
);
4098 if (ptr
== PHYS_MAP_NODE_NIL
) {
4101 mon(f
, " ptr=#%d", ptr
);
4103 mon(f
, " ptr=[%d]", ptr
);
4108 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
4109 int128_sub((size), int128_one())) : 0)
4111 void mtree_print_dispatch(fprintf_function mon
, void *f
,
4112 AddressSpaceDispatch
*d
, MemoryRegion
*root
)
4116 mon(f
, " Dispatch\n");
4117 mon(f
, " Physical sections\n");
4119 for (i
= 0; i
< d
->map
.sections_nb
; ++i
) {
4120 MemoryRegionSection
*s
= d
->map
.sections
+ i
;
4121 const char *names
[] = { " [unassigned]", " [not dirty]",
4122 " [ROM]", " [watch]" };
4124 mon(f
, " #%d @" TARGET_FMT_plx
".." TARGET_FMT_plx
" %s%s%s%s%s",
4126 s
->offset_within_address_space
,
4127 s
->offset_within_address_space
+ MR_SIZE(s
->mr
->size
),
4128 s
->mr
->name
? s
->mr
->name
: "(noname)",
4129 i
< ARRAY_SIZE(names
) ? names
[i
] : "",
4130 s
->mr
== root
? " [ROOT]" : "",
4131 s
== d
->mru_section
? " [MRU]" : "",
4132 s
->mr
->is_iommu
? " [iommu]" : "");
4135 mon(f
, " alias=%s", s
->mr
->alias
->name
?
4136 s
->mr
->alias
->name
: "noname");
4141 mon(f
, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
4142 P_L2_BITS
, P_L2_LEVELS
, d
->phys_map
.ptr
, d
->phys_map
.skip
);
4143 for (i
= 0; i
< d
->map
.nodes_nb
; ++i
) {
4146 Node
*n
= d
->map
.nodes
+ i
;
4148 mon(f
, " [%d]\n", i
);
4150 for (j
= 0, jprev
= 0, prev
= *n
[0]; j
< ARRAY_SIZE(*n
); ++j
) {
4151 PhysPageEntry
*pe
= *n
+ j
;
4153 if (pe
->ptr
== prev
.ptr
&& pe
->skip
== prev
.skip
) {
4157 mtree_print_phys_entries(mon
, f
, jprev
, j
, prev
.skip
, prev
.ptr
);
4163 if (jprev
!= ARRAY_SIZE(*n
)) {
4164 mtree_print_phys_entries(mon
, f
, jprev
, j
, prev
.skip
, prev
.ptr
);